Transportable telemetry workstation

NASA Astrophysics Data System (ADS)

Collins, Aaron S.

1989-09-01

The goal was to complete the design of a prototype for a Transportable Telemetry Workstation (TTW). The Macintosh 2 is used to provide a low-cost system which can house real-time cards mounted on the NuBus inside the Macintosh 2 plus provide a standardized user interface on the Macintosh 2 console. Prior to a telemetry run, the user will be able to configure his real-time telemetry processing functions from the Macintosh 2 console. During a telemetry run, the real-time cards will store the telemetry data directly on a hard disk while permitting viewing of the data cards on the Macintosh 2 console on various selectable formats. The user will view the cards in terms of the functions they perform and the selectable paths through the cards, it is not required to become involved directly in hardware issue except in terms of the functional configuration of the system components. The TTW will accept telemetry data from an RS422 serial input data bus, pass it through a frame synchronizer card and on to a real time controller card via a telemetry backplane bus. The controller card will then route the data to a hard disk through a SCSI interface, and/or to a user interface on the Macintosh 2 console by way of the Macintosh 2 NuBus. The three major components to be designed, therefore, are the TTW Controller Card, the TTW Synchronizer Card, and the NuBus/Macintosh 2 User Interface. Design and prototyping of this state-of-the-art, transportable, low-cost, easy-to-use multiprocessor telemetry system is continuing. Other functions are planned for the future.

Intelligent lightening system of urban and rural road traffic based on pyroelectric infrared detector

NASA Astrophysics Data System (ADS)

Miao, Man-Xiang

2007-12-01

By using the photo-voltage characteristics of pyroelectric infrared detector to fulfill signal acquisition, the detecting signal is processed with the core of a single chip microprocessor AT89C51. AT89C51 controls the CAN bus controller SJA1000/transceiver 82C250 to structure CAN bus communication system to transmit data through serial interface MAX232 connected with PC. The intelligent lightening system of urban and rural road traffic was carried out. In this paper, its construction and part's methods of hardware and software design were introduced in detail.

High Speed All-Optical Data Distribution Network

NASA Astrophysics Data System (ADS)

Braun, Steve; Hodara, Henri

2017-11-01

This article describes the performance and capabilities of an all-optical network featuring low latency, high speed file transfer between serially connected optical nodes. A basic component of the network is a network interface card (NIC) implemented through a unique planar lightwave circuit (PLC) that performs add/drop data and optical signal amplification. The network uses a linear bus topology with nodes in a "T" configuration, as described in the text. The signal is sent optically (hence, no latency) to all nodes via wavelength division multiplexing (WDM), with each node receiver tuned to wavelength of choice via an optical de-multiplexer. Each "T" node routes a portion of the signal to/from the bus through optical couplers, embedded in the network interface card (NIC), to each of the 1 through n computers.

CAMAC: A Unique Application with a Pocket Terminal.

DTIC Science & Technology

1982-09-16

POCKET TERMINAL S. PERFORMING ORG. REPORT NUMSIER I. AUTWOR(o) S. CONTRACT OR GRANT NUMU41’e() A.D. Elmond S. PERFORMING ORGANIZATION NAME AND ADORIESS 10...port of any CAMAC crate. In addition to being a maintenance device, the HHTT is a " smart " device that can control operations in a CAMAC crate. The...system LSI 11/23 microprocessor through an Asynchronous Serial Port (ASP) interface module. This ASP interface consists of: 1) Crystal Clock 2) MIK -Bus

Design and Integration of a Three Degrees-of-Freedom Robotic Vehicle with Control Moment Gyro for the Autonomous Multi-Agent Physically Interacting Spacecraft (AMPHIS) Testbed

DTIC Science & Technology

2006-09-01

required directional control for each thruster due to their high precision and equivalent power and computer interface requirements to those for the...Universal Serial Bus) ports, LPT (Line Printing Terminal) and KVM (Keyboard-Video- Mouse) interfaces. Additionally, power is supplied to the computer through...of the IDE cable to the Prometheus Development Kit ACC-IDEEXT. Connect a small drive power connector from the desktop ATX power supply to the ACC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hymel, Ross

The Public Key (PK) FPGA software performs asymmetric authentication using the 163-bit Elliptic Curve Digital Signature Algorithm (ECDSA) on an embedded FPGA platform. A digital signature is created on user-supplied data, and communication with a host system is performed via a Serial Peripheral Interface (SPI) bus. Software includes all components necessary for signing, including custom random number generator for key creation and SHA-256 for data hashing.

NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions

NASA Technical Reports Server (NTRS)

He, Yutao; Shalom, Eddy; Chau, Savio N.; Some, Raphael R.; Bolotin, Gary S.

2011-01-01

A paper discusses NEXUS, a common, next-generation avionics interconnect that is transparently compatible with wired, fiber-optic, and RF physical layers; provides a flexible, scalable, packet switched topology; is fault-tolerant with sub-microsecond detection/recovery latency; has scalable bandwidth from 1 Kbps to 10 Gbps; has guaranteed real-time determinism with sub-microsecond latency/jitter; has built-in testability; features low power consumption (< 100 mW per Gbps); is lightweight with about a 5,000-logic-gate footprint; and is implemented in a small Bus Interface Unit (BIU) with reconfigurable back-end providing interface to legacy subsystems. NEXUS enhances a commercial interconnect standard, Serial RapidIO, to meet avionics interconnect requirements without breaking the standard. This unified interconnect technology can be used to meet performance, power, size, and reliability requirements of all ranges of equipment, sensors, and actuators at chip-to-chip, board-to-board, or box-to-box boundary. Early results from in-house modeling activity of Serial RapidIO using VisualSim indicate that the use of a switched, high-performance avionics network will provide a quantum leap in spacecraft onboard science and autonomy capability for science and exploration missions.

Use of CCSDS Packets Over SpaceWire to Control Hardware

NASA Technical Reports Server (NTRS)

Haddad, Omar; Blau, Michael; Haghani, Noosha; Yuknis, William; Albaijes, Dennis

2012-01-01

For the Lunar Reconnaissance Orbiter, the Command and Data Handling subsystem consisted of several electronic hardware assemblies that were connected with SpaceWire serial links. Electronic hardware would be commanded/controlled and telemetry data was obtained using the SpaceWire links. Prior art focused on parallel data buses and other types of serial buses, which were not compatible with the SpaceWire and the core flight executive (CFE) software bus. This innovation applies to anything that utilizes both SpaceWire networks and the CFE software. The CCSDS (Consultative Committee for Space Data Systems) packet contains predetermined values in its payload fields that electronic hardware attached at the terminus of the SpaceWire node would decode, interpret, and execute. The hardware s interpretation of the packet data would enable the hardware to change its state/configuration (command) or generate status (telemetry). The primary purpose is to provide an interface that is compatible with the hardware and the CFE software bus. By specifying the format of the CCSDS packet, it is possible to specify how the resulting hardware is to be built (in terms of digital logic) that results in a hardware design that can be controlled by the CFE software bus in the final application

Design Report for Isolated RS-485 Bus Node

DTIC Science & Technology

2016-07-01

controlled wired RS-485 network. The Android-based smartphone or tablet is used in conjunction with a USB to serial bridge to operate as the bus master in...Android-based smartphone or tablet is used in conjunction with a USB to serial bridge to operate as the bus master in the system. The Android device

A novel ultrasonic phased array inspection system to NDT for offshore platform structures

NASA Astrophysics Data System (ADS)

Wang, Hua; Shan, Baohua; Wang, Xin; Ou, Jinping

2007-01-01

A novel ultrasonic phased array detection system is developed for nondestructive testing (NDT). The purpose of the system is to make acquisition of data in real-time from 64-element ultrasonic phased array transducer, and to enable real- time processing of the acquired data. The system is composed of five main parts: master unit, main board, eight transmit/receive units, a 64-element transducer and an external PC. The system can be used with 64 element transducers, excite 32 elements, receive and sample echo signals form 32 elements simultaneously at 62.5MHz with 8 bit precision. The external PC is used as the user interface showing the real time images and controls overall operation of the system through USB serial link. The use of Universal Serial Bus (USB) improves the transform speed and reduces hardware interface complexity. The program of the system is written in Visual C++.NET and is platform independent.

Lunar Reconnaissance Orbiter (LRO) Command and Data Handling Flight Electronics Subsystem

NASA Technical Reports Server (NTRS)

Nguyen, Quang; Yuknis, William; Haghani, Noosha; Pursley, Scott; Haddad, Omar

2012-01-01

A document describes a high-performance, modular, and state-of-the-art Command and Data Handling (C&DH) system developed for use on the Lunar Reconnaissance Orbiter (LRO) mission. This system implements a complete hardware C&DH subsystem in a single chassis enclosure that includes a processor card, 48 Gbytes of solid-state recorder memory, data buses including MIL-STD-1553B, custom RS-422, SpaceWire, analog collection, switched power services, and interfaces to the Ka-Band and S-Band RF communications systems. The C&DH team capitalized on extensive experience with hardware and software with PCI bus design, SpaceWire networking, Actel FPGA design, digital flight design techniques, and the use of VxWorks for the real-time operating system. The resulting hardware architecture was implemented to meet the LRO mission requirements. The C&DH comprises an enclosure, a backplane, a low-voltage power converter, a single-board computer, a communications interface board, four data storage boards, a housekeeping and digital input/output board, and an analog data acquisition board. The interfaces between the C&DH and the instruments and avionics are connected through a SpaceWire network, a MIL-STD-1553 bus, and a combination of synchronous and asynchronous serial data transfers over RS-422 and LVDS (low-voltage differential-signaling) electrical interfaces. The C&DH acts as the spacecraft data system with an instrument data manager providing all software and internal bus scheduling, ingestion of science data, distribution of commands, and performing science operations in real time.

The fiber-optic high-speed data bus for a new generation of military aircraft

NASA Astrophysics Data System (ADS)

Uhlhorn, Roger W.

1991-02-01

The avionic suite for the next generation of military aircraft is being designed with component and module commonality in mind in order to control recurring costs and capitalize on economy of scale. The backbone of the suite fashioned out of these modular building blocks is the fiber-optic bit-serial time-division multiplexed high-speed data bus (HSDB), operating at 50 Mb/s, which provides command and control communications among most of the aircraft subsystems and can be used to provide communications for a fly-by-light flight-control system or for the block transfer of data between mass memories and data processors. The fiber-optic HSDB is examined from the top down, beginning with an overview of the evolution of avionic architectures. A review is given of the standardization activity associated with development of the network, the protocols chosen to implement the desired communication functions, configuration options, and the fiber-optic components used in the bus interfaces or other active nodes of the network. It is believed that the utility of the bus extends beyond aircraft to spacecraft, ships, and land vehicles.

Serial Back-Plane Technologies in Advanced Avionics Architectures

NASA Technical Reports Server (NTRS)

Varnavas, Kosta

2005-01-01

Current back plane technologies such as VME, and current personal computer back planes such as PCI, are shared bus systems that can exhibit nondeterministic latencies. This means a card can take control of the bus and use resources indefinitely affecting the ability of other cards in the back plane to acquire the bus. This provides a real hit on the reliability of the system. Additionally, these parallel busses only have bandwidths in the 100s of megahertz range and EMI and noise effects get worse the higher the bandwidth goes. To provide scalable, fault-tolerant, advanced computing systems, more applicable to today s connected computing environment and to better meet the needs of future requirements for advanced space instruments and vehicles, serial back-plane technologies should be implemented in advanced avionics architectures. Serial backplane technologies eliminate the problem of one card getting the bus and never relinquishing it, or one minor problem on the backplane bringing the whole system down. Being serial instead of parallel improves the reliability by reducing many of the signal integrity issues associated with parallel back planes and thus significantly improves reliability. The increased speeds associated with a serial backplane are an added bonus.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Electrical Design and Evaluation of Asynchronous Serial Bus Communication Network of 48 Sensor Platform LSIs with Single-Ended I/O for Integrated MEMS-LSI Sensors.

PubMed

Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Muroyama, Masanori

2018-01-15

For installing many sensors in a limited space with a limited computing resource, the digitization of the sensor output at the site of sensation has advantages such as a small amount of wiring, low signal interference and high scalability. For this purpose, we have developed a dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) (referred to as "sensor platform LSI") for bus-networked Micro-Electro-Mechanical-Systems (MEMS)-LSI integrated sensors. In this LSI, collision avoidance, adaptation and event-driven functions are simply implemented to relieve data collision and congestion in asynchronous serial bus communication. In this study, we developed a network system with 48 sensor platform LSIs based on Printed Circuit Board (PCB) in a backbone bus topology with the bus length being 2.4 m. We evaluated the serial communication performance when 48 LSIs operated simultaneously with the adaptation function. The number of data packets received from each LSI was almost identical, and the average sampling frequency of 384 capacitance channels (eight for each LSI) was 73.66 Hz.

Non-contact data access with direction identification for industrial differential serial bus

NASA Astrophysics Data System (ADS)

Xie, Kai; Li, Xiaoping; Zhang, Hanlu; Yang, Ming; Ye, Yinghao

2013-06-01

We propose a non-contact method for accessing data in industrial differential serial bus applications, which could serve as an effective and safe online testing and diagnosing tool. The data stream and the transmission direction are reconstructed simultaneously from the near-field emanations of a twisted pair, eliminating direct contact with the actual conductors, and avoiding damage to the insulation (only the outer sheathing is removed). A non-contact probe with the ability to sense electric and magnetic fields is presented, as are theories for data reconstruction, direction identification, and a circuit implementation. The prototype was built using inexpensive components and then tested on a standard RS-485 industrial serial bus. Experimental results verified the validity of the proposed scheme.

High-Speed Ring Bus

NASA Technical Reports Server (NTRS)

Wysocky, Terry; Kopf, Edward, Jr.; Katanyoutananti, Sunant; Steiner, Carl; Balian, Harry

2010-01-01

The high-speed ring bus at the Jet Propulsion Laboratory (JPL) allows for future growth trends in spacecraft seen with future scientific missions. This innovation constitutes an enhancement of the 1393 bus as documented in the Institute of Electrical and Electronics Engineers (IEEE) 1393-1999 standard for a spaceborne fiber-optic data bus. It allows for high-bandwidth and time synchronization of all nodes on the ring. The JPL ring bus allows for interconnection of active units with autonomous operation and increased fault handling at high bandwidths. It minimizes the flight software interface with an intelligent physical layer design that has few states to manage as well as simplified testability. The design will soon be documented in the AS-1393 standard (Serial Hi-Rel Ring Network for Aerospace Applications). The framework is designed for "Class A" spacecraft operation and provides redundant data paths. It is based on "fault containment regions" and "redundant functional regions (RFR)" and has a method for allocating cables that completely supports the redundancy in spacecraft design, allowing for a complete RFR to fail. This design reduces the mass of the bus by incorporating both the Control Unit and the Data Unit in the same hardware. The standard uses ATM (asynchronous transfer mode) packets, standardized by ITU-T, ANSI, ETSI, and the ATM Forum. The IEEE-1393 standard uses the UNI form of the packet and provides no protection for the data portion of the cell. The JPL design adds optional formatting to this data portion. This design extends fault protection beyond that of the interconnect. This includes adding protection to the data portion that is contained within the Bus Interface Units (BIUs) and by adding to the signal interface between the Data Host and the JPL 1393 Ring Bus. Data transfer on the ring bus does not involve a master or initiator. Following bus protocol, any BIU may transmit data on the ring whenever it has data received from its host. There is no centralized arbitration or bus granting. The JPL design provides for autonomous synchronization of the nodes on the ring bus. An address-synchronous latency adjust buffer (LAB) has been designed that cannot get out of synchronization and needs no external input. Also, a priority-driven cable selection behavior has been programmed into each unit on the ring bus. This makes the bus able to connect itself up, according to a maximum redundancy priority system, without the need for computer intervention at startup. Switching around a failed or switched-off unit is also autonomous. The JPL bus provides a map of all the active units for the host computer to read and use for fault management. With regard to timing, this enhanced bus recognizes coordinated timing on a spacecraft as critical and addresses this with a single source of absolute and relative time, which is broadcast to all units on the bus with synchronization maintained to the tens of nanoseconds. Each BIU consists of up to five programmable triggers, which may be programmed for synchronization of events within the spacecraft of instrument. All JPL-formatted data transmitted on the ring bus are automatically time-stamped.

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

NASA Astrophysics Data System (ADS)

Tamborini, D.; Portaluppi, D.; Villa, F.; Tisa, S.; Tosi, A.

2014-11-01

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs.

PubMed

Tamborini, D; Portaluppi, D; Villa, F; Tisa, S; Tosi, A

2014-11-01

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

TMS communications software. Volume 2: Bus interface unit

NASA Technical Reports Server (NTRS)

Gregor, P. J.

1979-01-01

A data bus communication system to support the space shuttle's Trend Monitoring System (TMS) and to provide a basis for evaluation of the bus concept is described. Installation of the system included developing both hardware and software interfaces between the bus and the specific TMS computers and terminals. The software written for the microprocessor-based bus interface units is described. The software implements both the general bus communications protocol and also the specific interface protocols for the TMS computers and terminals.

Electrical Design and Evaluation of Asynchronous Serial Bus Communication Network of 48 Sensor Platform LSIs with Single-Ended I/O for Integrated MEMS-LSI Sensors

PubMed Central

Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki

2018-01-01

For installing many sensors in a limited space with a limited computing resource, the digitization of the sensor output at the site of sensation has advantages such as a small amount of wiring, low signal interference and high scalability. For this purpose, we have developed a dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) (referred to as “sensor platform LSI”) for bus-networked Micro-Electro-Mechanical-Systems (MEMS)-LSI integrated sensors. In this LSI, collision avoidance, adaptation and event-driven functions are simply implemented to relieve data collision and congestion in asynchronous serial bus communication. In this study, we developed a network system with 48 sensor platform LSIs based on Printed Circuit Board (PCB) in a backbone bus topology with the bus length being 2.4 m. We evaluated the serial communication performance when 48 LSIs operated simultaneously with the adaptation function. The number of data packets received from each LSI was almost identical, and the average sampling frequency of 384 capacitance channels (eight for each LSI) was 73.66 Hz. PMID:29342923

Design of a CAN bus interface for photoelectric encoder in the spaceflight camera

NASA Astrophysics Data System (ADS)

Sun, Ying; Wan, Qiu-hua; She, Rong-hong; Zhao, Chang-hai; Jiang, Yong

2009-05-01

In order to make photoelectric encoder usable in a spaceflight camera which adopts CAN bus as the communication method, CAN bus interface of the photoelectric encoder is designed in this paper. CAN bus interface hardware circuit of photoelectric encoder consists of CAN bus controller SJA 1000, CAN bus transceiver TJA1050 and singlechip. CAN bus interface controlling software program is completed in C language. A ten-meter shield twisted pair line is used as the transmission medium in the spaceflight camera, and speed rate is 600kbps.The experiments show that: the photoelectric encoder with CAN bus interface which has the advantages of more reliability, real-time, transfer rate and transfer distance overcomes communication line's shortcomings of classical photoelectric encoder system. The system works well in automatic measuring and controlling system.

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tamborini, D., E-mail: davide.tamborini@polimi.it; Portaluppi, D.; Villa, F.

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically usefulmore » for time-correlated single-photon counting application) through an independent serial link.« less

Efficient and Robust Data Collection Using Compact Micro Hardware, Distributed Bus Architectures and Optimizing Software

NASA Technical Reports Server (NTRS)

Chau, Savio; Vatan, Farrokh; Randolph, Vincent; Baroth, Edmund C.

2006-01-01

Future In-Space propulsion systems for exploration programs will invariably require data collection from a large number of sensors. Consider the sensors needed for monitoring several vehicle systems states of health, including the collection of structural health data, over a large area. This would include the fuel tanks, habitat structure, and science containment of systems required for Lunar, Mars, or deep space exploration. Such a system would consist of several hundred or even thousands of sensors. Conventional avionics system design will require these sensors to be connected to a few Remote Health Units (RHU), which are connected to robust, micro flight computers through a serial bus. This results in a large mass of cabling and unacceptable weight. This paper first gives a survey of several techniques that may reduce the cabling mass for sensors. These techniques can be categorized into four classes: power line communication, serial sensor buses, compound serial buses, and wireless network. The power line communication approach uses the power line to carry both power and data, so that the conventional data lines can be eliminated. The serial sensor bus approach reduces most of the cabling by connecting all the sensors with a single (or redundant) serial bus. Many standard buses for industrial control and sensor buses can support several hundreds of nodes, however, have not been space qualified. Conventional avionics serial buses such as the Mil-Std-1553B bus and IEEE 1394a are space qualified but can support only a limited number of nodes. The third approach is to combine avionics buses to increase their addressability. The reliability, EMI/EMC, and flight qualification issues of wireless networks have to be addressed. Several wireless networks such as the IEEE 802.11 and Ultra Wide Band are surveyed in this paper. The placement of sensors can also affect cable mass. Excessive sensors increase the number of cables unnecessarily. Insufficient number of sensors may not provide adequate coverage of the system. This paper also discusses an optimal technique to place and validate sensors.

MIL-STD-1553 dynamic bus controller/remote terminal hybrid set

NASA Astrophysics Data System (ADS)

Friedman, S. N.

This paper describes the performance, physical and electrical requirements of a Dual Redundant BUS Interface Unit (BIU) acting as a BUS Controller Interface Unit (BCIU) or Remote Terminal Unit (RTU) between a Motorola 68000 VME BUS and MIL-STD-1553B Multiplex Data Bus. A discussion of how the BIU Hybrid set is programmed, and operates as a BCIU or RTU, will be included. This paper will review Dynamic Bus Control and other Mode Code capabilities. The BIU Hybrid Set interfaces to a 68000 Microprocessor with a VME Bus using programmed I/O transfers. This special interface will be discussed along with the internal Dual Access Memory (4K x 16) used to support the data exchanges between the CPU and the BIU Hybrid Set. The hybrid set's physical size and power requirements will be covered. This includes the present Double Eurocard the BIU function is presently being offered on.

TMS communications software. Volume 1: Computer interfaces

NASA Technical Reports Server (NTRS)

Brown, J. S.; Lenker, M. D.

1979-01-01

A prototype bus communications system, which is being used to support the Trend Monitoring System (TMS) as well as for evaluation of the bus concept is considered. Hardware and software interfaces to the MODCOMP and NOVA minicomputers are included. The system software required to drive the interfaces in each TMS computer is described. Documentation of other software for bus statistics monitoring and for transferring files across the bus is also included.

An automatic molecular beam microwave Fourier transform spectrometer

NASA Astrophysics Data System (ADS)

Andresen, U.; Dreizler, H.; Grabow, J.-U.; Stahl, W.

1990-12-01

The general setup of an automatic MB-MWFT spectrometer for use in the 4-18 GHz range and its software details are discussed. The experimental control and data handling are performed on a personal computer using an interactive program. The parameters of the MW source and the resonator are controlled via IEEE bus and several serial interface ports. The tuning and measuring processes are automated and the efficiency is increased if unknown spectra are to be scanned. As an example, the spectrum of carbonyl sulfide has been measured automatically. The spectrometer is superior to all other kinds of rotational spectroscopic methods in both speed and unambiguity.

Radiation-Tolerant Dual Data Bus

NASA Technical Reports Server (NTRS)

Kinstler, Gary A.

2007-01-01

An architecture, and a method of utilizing the architecture, have been proposed to enable error-free operation of a data bus that includes, and is connected to, commercial off-the-shelf (COTS) circuits and components that are inherently susceptible to singleevent upsets [SEUs (bit flips caused by impinging high-energy particles and photons)]. The architecture and method are applicable, more specifically, to data-bus circuitry based on the Institute for Electrical and Electronics Engineers (IEEE) 1394b standard for a high-speed serial bus.

AIAA spacecraft GN&C interface standards initiative: Overview

NASA Technical Reports Server (NTRS)

Challoner, A. Dorian

1995-01-01

The American Institute of Aeronautics and Astronautics (AIAA) has undertaken an important standards initiative in the area of spacecraft guidance, navigation, and control (GN&C) subsystem interfaces. The objective of this effort is to establish standards that will promote interchangeability of major GN&C components, thus enabling substantially lower spacecraft development costs. Although initiated by developers of conventional spacecraft GN&C, it is anticipated that interface standards will also be of value in reducing the development costs of micro-engineered spacecraft. The standardization targets are specifically limited to interfaces only, including information (i.e. data and signal), power, mechanical, thermal, and environmental interfaces between various GN&C components and between GN&C subsystems and other subsystems. The current emphasis is on information interfaces between various hardware elements (e.g., between star trackers and flight computers). The poster presentation will briefly describe the program, including the mechanics and schedule, and will publicize the technical products as they exist at the time of the conference. In particular, the rationale for the adoption of the AS1773 fiber-optic serial data bus and the status of data interface standards at the application layer will be presented.

Survey on the implementation and reliability of CubeSat electrical bus interfaces

NASA Astrophysics Data System (ADS)

Bouwmeester, Jasper; Langer, Martin; Gill, Eberhard

2017-06-01

This paper provides results and conclusions on a survey on the implementation and reliability aspects of CubeSat bus interfaces, with an emphasis on the data bus and power distribution. It provides recommendations for a future CubeSat bus standard. The survey is based on a literature study and a questionnaire representing 60 launched CubeSats and 44 to be launched CubeSats. It is found that the bus interfaces are not the main driver for mission failures. However, it is concluded that the Inter Integrated Circuit (I2C) data bus, as implemented in a great majority of the CubeSats, caused some catastrophic satellite failures and a vast amount of bus lockups. The power distribution may lead to catastrophic failures if the power lines are not protected against overcurrent. A connector and wiring standard widely implemented in CubeSats is based on the PC/104 standard. Most participants find the 104 pin connector of this standard too large. For a future CubeSat bus interface standard, it is recommended to implement a reliable data bus, a power distribution with overcurrent protection and a wiring harness with smaller connectors compared with PC/104.

Remotely Accessible Testbed for Software Defined Radio Development

NASA Technical Reports Server (NTRS)

Lux, James P.; Lang, Minh; Peters, Kenneth J.; Taylor, Gregory H.

2012-01-01

Previous development testbeds have assumed that the developer was physically present in front of the hardware being used. No provision for remote operation of basic functions (power on/off or reset) was made, because the developer/operator was sitting in front of the hardware, and could just push the button manually. In this innovation, a completely remotely accessible testbed has been created, with all diagnostic equipment and tools set up for remote access, and using standardized interfaces so that failed equipment can be quickly replaced. In this testbed, over 95% of the operating hours were used for testing without the developer being physically present. The testbed includes a pair of personal computers, one running Linux and one running Windows. A variety of peripherals is connected via Ethernet and USB (universal serial bus) interfaces. A private internal Ethernet is used to connect to test instruments and other devices, so that the sole connection to the outside world is via the two PCs. An important design consideration was that all of the instruments and interfaces used stable, long-lived industry standards, such as Ethernet, USB, and GPIB (general purpose interface bus). There are no plug-in cards for the two PCs, so there are no problems with finding replacement computers with matching interfaces, device drivers, and installation. The only thing unique to the two PCs is the locally developed software, which is not specific to computer or operating system version. If a device (including one of the computers) were to fail or become unavailable (e.g., a test instrument needed to be recalibrated), replacing it is a straightforward process with a standard, off-the-shelf device.

The universal serial bus endoscope: design and initial clinical experience.

PubMed

Hernandez-Zendejas, Gregorio; Dobke, Marek K; Guerrerosantos, Jose

2004-01-01

Endoscopic forehead lift is a well-established procedure in aesthetic plastic surgery. Many agree that currently available video-endoscopic equipment is bulky, multipieced and sometimes cumbersome in the operating theater. A novel system, the Universal Serial Bus Endoscope (USBE) was designed to simplify and reduce the number of necessary equipment pieces in the endoscopic setup. The USBE is attached by a single cable to a Universal Serial Bus (USB) port of a laptop computer. A built-in miniaturized cold light source provides illumination. A built-in digital camera chip enables procedure recording. The real-time images and movies obtained with USBE are displayed on the computer's screen and recorded on the laptop's hard disk drive. In this study, 25 patients underwent endoscopic browlift using the USBE system to test its clinical usefulness, all with good results and without complications or need for revision. The USBE was found to be reliable and easier to use than current video-endoscope equipment. The operative time needed to complete the procedure by the authors was reduced approximately 50%. The design and main technical characteristics of the USBE are presented.

Generating Fast and Accurate Compliance Reports for Various Data Rates

NASA Astrophysics Data System (ADS)

Penugonda, Srinath

As the demands on the industry data rates have increased there is a need for interoperable interfaces to function flawlessly. Added to this complexity, the number of I/O data lines are also increasing making it more time consuming to design and test. This in general leads to creating of compliance standards to which interfaces must adhere. The goal of this theses is to aid the Signal Integrity Engineers with a better and fast way of rendering a full picture of the interface compliance parameters. Three different interfaces at various data rates were chosen. They are: 25Gbps Very Short Reach (VSR) based on Optical Internetworking Forum (OIF), Mobile Industry Processer Interface (MIPI) particularly for camera based on MIPI Alliance organization upto 1.5Gbps and for a passive Universal Serial Bus (USB) Type-C cable based on USB organization particularly for generation-I with data rate of 10Gbps. After a full understanding of each of the interfaces, a complete end-to-end reports for each of the interfaces were developed with an easy to use user interface. A standard one-to-one comparison is done with commercially available software tools for the above mentioned interfaces. The tools were developed in MATLAB and Python. Data was usually obtained by probing at interconnect, from either an oscilloscope or vector network analyzer.

TMS communications hardware. Volume 2: Bus interface unit

NASA Technical Reports Server (NTRS)

Brown, J. S.; Hopkins, G. T.

1979-01-01

A prototype coaxial cable bus communication system used in the Trend Monitoring System to interconnect intelligent graphics terminals to a host minicomputer is described. The terminals and host are connected to the bus through a microprocessor-based RF modem termed a Bus Interface Unit (BIU). The BIU hardware and the Carrier Sense Multiple Access Listen-While-Talk protocol used on the network are described.

Method of recording bioelectrical signals using a capacitive coupling

NASA Astrophysics Data System (ADS)

Simon, V. A.; Gerasimov, V. A.; Kostrin, D. K.; Selivanov, L. M.; Uhov, A. A.

2017-11-01

In this article a technique for the bioelectrical signals acquisition by means of the capacitive sensors is described. A feedback loop for the ultra-high impedance biasing of the input instrumentation amplifier, which provides receiving of the electrical cardiac signal (ECS) through a capacitive coupling, is proposed. The mains 50/60 Hz noise is suppressed by a narrow-band stop filter with an independent notch frequency and quality factor tuning. Filter output is attached to a ΣΔ analog-to-digital converter (ADC), which acquires the filtered signal with a 24-bit resolution. Signal processing board is connected through universal serial bus interface to a personal computer, where ECS in a digital form is recorded and processed.

Programmable data communications controller requirements

NASA Technical Reports Server (NTRS)

1977-01-01

The design requirements for a Programmable Data Communications Controller (PDCC) that reduces the difficulties in attaching data terminal equipment to a computer are presented. The PDCC is an interface between the computer I/O channel and the bit serial communication lines. Each communication line is supported by a communication port that handles all line control functions and performs most terminal control functions. The port is fabricated on a printed circuit board that plugs into a card chassis, mating with a connector that is joined to all other card stations by a data bus. Ports are individually programmable; each includes a microprocessor, a programmable read-only memory for instruction storage, and a random access memory for data storage.

Design of temperature monitoring system based on CAN bus

NASA Astrophysics Data System (ADS)

Zhang, Li

2017-10-01

The remote temperature monitoring system based on the Controller Area Network (CAN) bus is designed to collect the multi-node remote temperature. By using the STM32F103 as main controller and multiple DS18B20s as temperature sensors, the system achieves a master-slave node data acquisition and transmission based on the CAN bus protocol. And making use of the serial port communication technology to communicate with the host computer, the system achieves the function of remote temperature storage, historical data show and the temperature waveform display.

The other fiber, the other fabric, the other way

NASA Astrophysics Data System (ADS)

Stephens, Gary R.

1993-02-01

Coaxial cable and distributed switches provide a way to configure high-speed Fiber Channel fabrics. This type of fabric provides a cost-effective alternative to a fabric of optical fibers and centralized cross-point switches. The fabric topology is a simple tree. Products using parallel busses require a significant change to migrate to a serial bus. Coaxial cables and distributed switches require a smaller technology shift for these device manufacturers. Each distributed switch permits both medium type and speed changes. The fabric can grow and bridge to optical fibers as the needs expand. A distributed fabric permits earlier entry into high-speed serial operations. For very low-cost fabrics, a distributed switch may permit a link configured as a loop. The loop eliminates half of the ports when compared to a switched point-to-point fabric. A fabric of distributed switches can interface to a cross-point switch fabric. The expected sequence of migration is: closed loops, small closed fabrics, and, finally, bridges, to connect optical cross-point switch fabrics. This paper presents the concept of distributed fabrics, including address assignment, frame routing, and general operation.

Continuous-waveform constant-current isolated physiological stimulator

NASA Astrophysics Data System (ADS)

Holcomb, Mark R.; Devine, Jack M.; Harder, Rene; Sidorov, Veniamin Y.

2012-04-01

We have developed an isolated continuous-waveform constant-current physiological stimulator that is powered and controlled by universal serial bus (USB) interface. The stimulator is composed of a custom printed circuit board (PCB), 16-MHz MSP430F2618 microcontroller with two integrated 12-bit digital to analog converters (DAC0, DAC1), high-speed H-Bridge, voltage-controlled current source (VCCS), isolated USB communication and power circuitry, two isolated transistor-transistor logic (TTL) inputs, and a serial 16 × 2 character liquid crystal display. The stimulators are designed to produce current stimuli in the range of ±15 mA indefinitely using a 20V source and to be used in ex vivo cardiac experiments, but they are suitable for use in a wide variety of research or student experiments that require precision control of continuous waveforms or synchronization with external events. The device was designed with customization in mind and has features that allow it to be integrated into current and future experimental setups. Dual TTL inputs allow replacement by two or more traditional stimulators in common experimental configurations. The MSP430 software is written in C++ and compiled with IAR Embedded Workbench 5.20.2. A control program written in C++ runs on a Windows personal computer and has a graphical user interface that allows the user to control all aspects of the device.

The NASA bus communications listening device software

NASA Technical Reports Server (NTRS)

Allen, M. A.

1979-01-01

The development of the bus listener is presented. Special software was developed to control the 'bus interface units' (BIU) connecting each of these devices to a communications cable to form the bus communication network. The code used in the BTU is described.

Optical digital techniques

NASA Technical Reports Server (NTRS)

1979-01-01

Optical interface losses between transmitter-to-fiber interface, connector-to-connector interface, and fiber-to-receiver interface were studied. System effects such as pulse dispersion, risetimes of the sources and detectors, type of fibers used, output power of the sources, and detector sensitivity were considered. Data bus systems such as TEE, Star, and Hybrid were analyzed. The matter of single fiber versus bundle technologies for future avionics systems was considered. The existing data bus system on Space Shuttle was examined and an optical analog was derived for a fiber bundle system, along with the associated power margin. System tests were performed on a feasibility model of a 9-port Star data bus system including BER, star losses, connector losses, etc. The same system was subjected to EMI between the range of 200 Hz to 10 GHz at 20V/m levels. A lightning test was also performed which simulated the conditions similar to those on Space Shuttle. The data bus system was found to be EMI and lightning hard. It is concluded that an optical data bus system is feasible for shuttle orbiter type vehicles.

Network device interface for digitally interfacing data channels to a controller a via network

NASA Technical Reports Server (NTRS)

Konz, Daniel W. (Inventor); Ellerbrock, Philip J. (Inventor); Grant, Robert L. (Inventor); Winkelmann, Joseph P. (Inventor)

2006-01-01

The present invention provides a network device interface and method for digitally connecting a plurality of data channels to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. In one embodiment, the bus controller transmits messages to the network device interface containing a plurality of bits having a value defined by a transition between first and second states in the bits. The network device interface determines timing of the data sequence of the message and uses the determined timing to communicate with the bus controller.

Interface For MIL-STD-1553B Data Bus

NASA Technical Reports Server (NTRS)

Davies, Bryan L.; Osborn, Stephen H.; Sullender, Craig C.

1993-01-01

Electronic control-logic subsystem acts as interface between microcontroller and MIL-STD-1553B data bus. Subsystem made of relatively small number of integrated circuits. Advantages include low power, few integrated-circuit chips, and little need for control signals.

Information management advanced development. Volume 3: Digital data bus breadboard

NASA Technical Reports Server (NTRS)

Gerber, C. R.

1972-01-01

The design, development, and evaluation of the digital data bus breadboard for the modular space station are discussed. Subjects presented are: (1) requirements summary, (2) parametric data for bus design, (3) redundancy concepts, and (4) data bus breadboard performance and interface requirements.

NASA's 3D Flight Computer for Space Applications

NASA Technical Reports Server (NTRS)

Alkalai, Leon

2000-01-01

The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998. This computer, developed in the 1995-97 time frame, contains many new computer technologies previously never used in deep-space systems. They include: advanced 3D packaging architecture for future low-mass and low-volume avionics systems; high-density 3D packaged chip-stacks for both volatile and non-volatile mass memory: 400 Mbytes of local DRAM memory, and 128 Mbytes of Flash memory; high-bandwidth Peripheral Component Interface (Per) local-bus with a bridge to VME; high-bandwidth (20 Mbps) fiber-optic serial bus; and other attributes, such as standard support for Design for Testability (DFT). Even though this computer system did not complete on time for delivery to the DS1 project, it was an important development along a technology roadmap towards highly integrated and highly miniaturized avionics systems for deep-space applications. This continued technology development is now being performed by NASA's Deep Space System Development Program (also known as X2000) and within JPL's Center for Integrated Space Microsystems (CISM).

Method and systems for a radiation tolerant bus interface circuit

NASA Technical Reports Server (NTRS)

Kinstler, Gary A. (Inventor)

2007-01-01

A bus management tool that allows communication to be maintained between a group of nodes operatively connected on two busses in the presence of radiation by transmitting periodically a first message from one to another of the nodes on one of the busses, determining whether the first message was received by the other of the nodes on the first bus, and when it is determined that the first message was not received by the other of the nodes, transmitting a recovery command to the other of the nodes on a second of the of busses. Methods, systems, and articles of manufacture consistent with the present invention also provide for a bus recovery tool on the other node that re-initializes a bus interface circuit operatively connecting the other node to the first bus in response to the recovery command.

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Konz, Daniel W. (Inventor); Ellerbrock, Philip J. (Inventor); Grant, Robert L. (Inventor); Winkelmann, Joseph P. (Inventor)

2006-01-01

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is then converted into digital signals and transmitted back to the controller. In one embodiment, the bus controller sends commands and data a defined bit rate, and the network device interface senses this bit rate and sends data back to the bus controller using the defined bit rate.

New control system for the 1.5m and 0.9m telescopes at Sierra Nevada Observatory

NASA Astrophysics Data System (ADS)

Costillo, Luis P.; Ramos, J. Luis; Ibáñez, J. Miguel; Aparicio, Beatriz; Herránz, Miguel; García, Antonio J.

2006-06-01

The Sierra Nevada Observatory (Granada, Spain) has a number of telescopes. Our study will focus on two Nasmyth telescopes with apertures of 1.5m and 0.9m and an equatorial mount. The system currently installed to control these telescopes is a 1995 centralized VME module. However, given the problems which have arisen due to the number of wires and other complications, we have decided to change this control module. We will control each telescope with a distributed control philosophy, using a serial linear communication bus between independent nodes, although all system capabilities are accessible from a central unit anywhere and at any time via internet. We have divided the tasks and have one node for alpha control, another for delta control, one for the dome, one for the focus and the central unit to interface with a pc. The nodes for alpha, delta and the dome will be used by means of FPGA's in order to efficiently sample the encoders and the control algorithms, and to generate the output for the motors and the servo. The focus will have a microcontroller, and the system is easy to expand in the event of the inclusion of more nodes. After having studied several fieldbus systems, we have opted for the CAN bus, because of its reliability and broadcasting possibilities. In this way, all the important information will be on the bus, and every node will be able to access the information at any time. This document explains the new design made in the IAA for the new consoles of control whose basic characteristics are, the distributed control, the hardware simplify, the cable remove, the safety and maintenance improve and facilitating the observation improving the interface with the user, and finally to prepare the system for the remote observation.

From Waiting for the Bus to Storming the Bastille: From Sartrean Seriality to the Relationships that Form Classroom Communities

ERIC Educational Resources Information Center

Blenkinsop, Sean

2012-01-01

One of the tasks of Jean-Paul Sartre's later work was to consider how an individual could live freely within a free community. This paper examines how Sartre describes the process of group formation and the implications of this discussion for education. The paper begins with his metaphor of a bus queue in order to describe a series. Then, by means…

Interface Provides Standard-Bus Communication

NASA Technical Reports Server (NTRS)

Culliton, William G.

1995-01-01

Microprocessor-controlled interface (IEEE-488/LVABI) incorporates service-request and direct-memory-access features. Is circuit card enabling digital communication between system called "laser auto-covariance buffer interface" (LVABI) and compatible personal computer via general-purpose interface bus (GPIB) conforming to Institute for Electrical and Electronics Engineers (IEEE) Standard 488. Interface serves as second interface enabling first interface to exploit advantages of GPIB, via utility software written specifically for GPIB. Advantages include compatibility with multitasking and support of communication among multiple computers. Basic concept also applied in designing interfaces for circuits other than LVABI for unidirectional or bidirectional handling of parallel data up to 16 bits wide.

Testing of Environmental Satellite Bus-Instrument Interfaces Using Engineering Models

NASA Technical Reports Server (NTRS)

Gagnier, Donald; Hayner, Rick; Nosek, Thomas; Roza, Michael; Hendershot, James E.; Razzaghi, Andrea I.

2004-01-01

This paper discusses the formulation and execution of a laboratory test of the electrical interfaces between multiple atmospheric scientific instruments and the spacecraft bus that carries them. The testing, performed in 2002, used engineering models of the instruments and the Aura spacecraft bus electronics. Aura is one of NASA s Earth Observatory System missions. The test was designed to evaluate the complex interfaces in the command and data handling subsystems prior to integration of the complete flight instruments on the spacecraft. A problem discovered during the flight integration phase of the observatory can cause significant cost and schedule impacts. The tests successfully revealed problems and led to their resolution before the full-up integration phase, saving significant cost and schedule. This approach could be beneficial for future environmental satellite programs involving the integration of multiple, complex scientific instruments onto a spacecraft bus.

Multiplexer/Demultiplexer Loading Tool (MDMLT)

NASA Technical Reports Server (NTRS)

Brewer, Lenox Allen; Hale, Elizabeth; Martella, Robert; Gyorfi, Ryan

2012-01-01

The purpose of the MDMLT is to improve the reliability and speed of loading multiplexers/demultiplexers (MDMs) in the Software Development and Integration Laboratory (SDIL) by automating the configuration management (CM) of the loads in the MDMs, automating the loading procedure, and providing the capability to load multiple or all MDMs concurrently. This loading may be accomplished in parallel, or single MDMs (remote). The MDMLT is a Web-based tool that is capable of loading the entire International Space Station (ISS) MDM configuration in parallel. It is able to load Flight Equivalent Units (FEUs), enhanced, standard, and prototype MDMs as well as both EEPROM (Electrically Erasable Programmable Read-Only Memory) and SSMMU (Solid State Mass Memory Unit) (MASS Memory). This software has extensive configuration management to track loading history, and the performance improvement means of loading the entire ISS MDM configuration of 49 MDMs in approximately 30 minutes, as opposed to 36 hours, which is what it took previously utilizing the flight method of S-Band uplink. The laptop version recently added to the MDMLT suite allows remote lab loading with the CM of information entered into a common database when it is reconnected to the network. This allows the program to reconfigure the test rigs quickly between shifts, allowing the lab to support a variety of onboard configurations during a single day, based on upcoming or current missions. The MDMLT Computer Software Configuration Item (CSCI) supports a Web-based command and control interface to the user. An interface to the SDIL File Transfer Protocol (FTP) server is supported to import Integrated Flight Loads (IFLs) and Internal Product Release Notes (IPRNs) into the database. An interface to the Monitor and Control System (MCS) is supported to control the power state, and to enable or disable the debug port of the MDMs to be loaded. Two direct interfaces to the MDM are supported: a serial interface (debug port) to receive MDM memory dump data and the calculated checksum, and the Small Computer System Interface (SCSI) to transfer load files to MDMs with hard disks. File transfer from the MDM Loading Tool to EEPROM within the MDM is performed via the MILSTD- 1553 bus, making use of the Real- Time Input/Output Processors (RTIOP) when using the rig-based MDMLT, and via a bus box when using the laptop MDMLT. The bus box is a cost-effective alternative to PC-1553 cards for the laptop. It is noted that this system can be modified and adapted to any avionic laboratory for spacecraft computer loading, ship avionics, or aircraft avionics where multiple configurations and strong configuration management of software/firmware loads are required.

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-05-31

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

Dynamically reconfigurable photovoltaic system

DOEpatents

Okandan, Murat; Nielson, Gregory N.

2016-12-27

A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

a Portable Pixel Detector Operating as AN Active Nuclear Emulsion and its Application for X-Ray and Neutron Tomography

NASA Astrophysics Data System (ADS)

Vykydal, Z.; Jakubek, J.; Holy, T.; Pospisil, S.

2006-04-01

This work is devoted to the development of a USB1.1 (Universal Serial Bus) based read out system for the Medipix2 detector to achieve maximum portability of this position sensitive detecting device. All necessary detector support is integrated into one compact system (80 × 50 × 20 mm3) including the detector bias source (up to 100 V). The read out interface can control external I2C based devices, so in case of tomography it is easy to synchronize detector shutter with stepper motor control. An additional significant advantage of the USB interface is the support of back side pulse processing. This feature enables to determine the energy additionally to the position of a heavy charged particle hitting the sensor. Due to the small pixel dimensions it is also possible to distinguish the type of single quanta of radiation from the track created in the pixel detector as in case of an active nuclear emulsion.

Time-resolved laser-induced fluorescence system

NASA Astrophysics Data System (ADS)

Bautista, F. J.; De la Rosa, J.; Gallegos, F. J.

2006-02-01

Fluorescence methods are being used increasingly in the measurement of species concentrations in gases, liquids and solids. Laser induced fluorescence is spontaneous emission from atoms or molecules that have been excited by laser radiation. Here we present a time resolved fluorescence instrument that consists of a 5 μJ Nitrogen laser (337.1 nm), a sample holder, a quartz optical fiber, a spectrometer, a PMT and a PC that allows the measurement of visible fluorescence spectra (350-750 nm). Time response of the system is approximately 5 ns. The instrument has been used in the measurement of colored bond paper, antifreeze, diesel, cochineal pigment and malignant tissues. The data acquisition was achieved through computer control of a digital oscilloscope (using General Purpose Interface Bus GPIB) and the spectrometer via serial (RS232). The instrument software provides a graphic interface that lets make some data acquisition tasks like finding fluorescence spectra, and fluorescence lifetimes. The software was developed using the Lab-View 6i graphic programming package and can be easily managed in order to add more functions to it.

Medusa: A Scalable MR Console Using USB

PubMed Central

Stang, Pascal P.; Conolly, Steven M.; Santos, Juan M.; Pauly, John M.; Scott, Greig C.

2012-01-01

MRI pulse sequence consoles typically employ closed proprietary hardware, software, and interfaces, making difficult any adaptation for innovative experimental technology. Yet MRI systems research is trending to higher channel count receivers, transmitters, gradient/shims, and unique interfaces for interventional applications. Customized console designs are now feasible for researchers with modern electronic components, but high data rates, synchronization, scalability, and cost present important challenges. Implementing large multi-channel MR systems with efficiency and flexibility requires a scalable modular architecture. With Medusa, we propose an open system architecture using the Universal Serial Bus (USB) for scalability, combined with distributed processing and buffering to address the high data rates and strict synchronization required by multi-channel MRI. Medusa uses a modular design concept based on digital synthesizer, receiver, and gradient blocks, in conjunction with fast programmable logic for sampling and synchronization. Medusa is a form of synthetic instrument, being reconfigurable for a variety of medical/scientific instrumentation needs. The Medusa distributed architecture, scalability, and data bandwidth limits are presented, and its flexibility is demonstrated in a variety of novel MRI applications. PMID:21954200

CoNNeCT Baseband Processor Module Boot Code SoftWare (BCSW)

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K.; Orozco, David S.; Byrne, D. J.; Allen, Steven J.; Sahasrabudhe, Adit; Lang, Minh

2012-01-01

This software provides essential startup and initialization routines for the CoNNeCT baseband processor module (BPM) hardware upon power-up. A command and data handling (C&DH) interface is provided via 1553 and diagnostic serial interfaces to invoke operational, reconfiguration, and test commands within the code. The BCSW has features unique to the hardware it is responsible for managing. In this case, the CoNNeCT BPM is configured with an updated CPU (Atmel AT697 SPARC processor) and a unique set of memory and I/O peripherals that require customized software to operate. These features include configuration of new AT697 registers, interfacing to a new HouseKeeper with a flash controller interface, a new dual Xilinx configuration/scrub interface, and an updated 1553 remote terminal (RT) core. The BCSW is intended to provide a "safe" mode for the BPM when initially powered on or when an unexpected trap occurs, causing the processor to reset. The BCSW allows the 1553 bus controller in the spacecraft or payload controller to operate the BPM over 1553 to upload code; upload Xilinx bit files; perform rudimentary tests; read, write, and copy the non-volatile flash memory; and configure the Xilinx interface. Commands also exist over 1553 to cause the CPU to jump or call a specified address to begin execution of user-supplied code. This may be in the form of a real-time operating system, test routine, or specific application code to run on the BPM.

Four-Channel PC/104 MIL-STD-1553 Circuit Board

NASA Technical Reports Server (NTRS)

Cox, Gary L.

2004-01-01

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Diesel exhaust causing low-dose irritant asthma with latency?

PubMed

Adewole, Femi; Moore, Vicky C; Robertson, Alastair S; Burge, P S

2009-09-01

Diesel exhaust exposure may cause acute irritant-induced asthma and potentiate allergen-induced asthma. There are no previous reports of occupational asthma due to diesel exhaust. To describe occupational asthma with latency in workers exposed to diesel exhaust in bus garages. The Shield database of occupational asthma notifications in the West Midlands, UK, was searched between 1990 and 2006 for workers where diesel exhaust exposure was thought to be the cause of the occupational asthma. Those without other confounding exposures whose occupational asthma was validated by serial peak expiratory flow (PEF) analysis using Oasys software were included. Fifteen workers were identified with occupational asthma attributed to diesel exhaust. Three had validated new-onset asthma with latency. All worked in bus garages where diesel exhaust exposure was the only likely cause of their occupational asthma. Occupational asthma was confirmed by measures of non-specific reactivity and serial measurements of PEF with Oasys scores of 2.9, 3.73 and 4 (positive score > 2.5). The known non-specific irritant effects of diesel exhaust suggest that this is an example of low-dose irritant-induced asthma and that exposures to diesel exhaust in at least some bus garages are at a sufficient level to cause this.

77 FR 35718 - Certain Universal Serial Bus (“USB”) Portable Storage Devices, Including USB Flash Drives and...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-14

... on the Commission's electronic docket (EDIS) at http://edis.usitc.gov . Hearing-impaired persons are... Sunnyvale, California; Kingston Technology Company, Inc. of Fountain Valley, California; Patriot Memory, LLC...

Expanded serial communication capability for the transport systems research vehicle laptop computers

NASA Technical Reports Server (NTRS)

Easley, Wesley C.

1991-01-01

A recent upgrade of the Transport Systems Research Vehicle (TSRV) operated by the Advanced Transport Operating Systems Program Office at the NASA Langley Research Center included installation of a number of Grid 1500 series laptop computers. Each unit is a 80386-based IBM PC clone. RS-232 data busses are needed for TSRV flight research programs, and it has been advantageous to extend the application of the Grids in this area. Use was made of the expansion features of the Grid internal bus to add a user programmable serial communication channel. Software to allow use of the Grid bus expansion has been written and placed in a Turbo C library for incorporation into applications programs in a transparent manner via function calls. Port setup; interrupt-driven, two-way data transfer; and software flow control are built into the library functions.

Testing of Environmental Satellite Bus-Instrument Interfaces Using Engineering Models

NASA Technical Reports Server (NTRS)

Gagnier, Don; Hayner, Rick; Roza, Michael; Nosek, Thomas; Razzaghi, Andrea

2004-01-01

This paper discusses the formulation and execution of a laboratory test of the electrical interfaces between multiple atmospheric science instruments and the spacecraft bus that carries them. The testing, performed in 2002, used engineering models of the instruments that will be flown on the Aura s p a c m and of the Aura spacecraft bus electronics. Aura is one of NASA's Earth Observing System @OS) Program missions managed by the Goddard Space Flight Center. The test was designed to evaluate the complex interfaces in the spacecraft and instrument command and data handling (C&DH) subsystems prior to integration of the complete flight instruments on the spacecraft. A problem discovered during (and not before) the flight hardware integration phase can cause significant cost and schedule impacts. The testing successfully surfaced problems and led to their resolution before the full-up integration phase, saving significant cost and schedule time. This approach could be used on future environmental satellite programs involving multiple, complex scientific instruments being integrated onto a bus.

A study of multiplex data bus techniques for the space shuttle

NASA Technical Reports Server (NTRS)

Kearney, R. J.; Kalange, M. A.

1972-01-01

A comprehensive technology base for the design of a multiplexed data bus subsystem is provided. Extensive analyses, both analytical and empirical, were performed. Subjects covered are classified under the following headings: requirements identification and analysis; transmission media studies; signal design and detection studies; synchronization, timing, and control studies; user-subsystem interface studies; operational reliability analyses; design of candidate data bus configurations; and evaluation of candidate data bus designs.

Integrated test system of infrared and laser data based on USB 3.0

NASA Astrophysics Data System (ADS)

Fu, Hui Quan; Tang, Lin Bo; Zhang, Chao; Zhao, Bao Jun; Li, Mao Wen

2017-07-01

Based on USB3.0, this paper presents the design method of an integrated test system for both infrared image data and laser signal data processing module. The core of the design is FPGA logic control, the design uses dual-chip DDR3 SDRAM to achieve high-speed laser data cache, and receive parallel LVDS image data through serial-to-parallel conversion chip, and it achieves high-speed data communication between the system and host computer through the USB3.0 bus. The experimental results show that the developed PC software realizes the real-time display of 14-bit LVDS original image after 14-to-8 bit conversion and JPEG2000 compressed image after decompression in software, and can realize the real-time display of the acquired laser signal data. The correctness of the test system design is verified, indicating that the interface link is normal.

Interface For Dual-Channel MIL-STD-1553 Data Bus

NASA Technical Reports Server (NTRS)

Davies, Bryan L.; Heaps, Timothy L.

1992-01-01

Digital electronic subsystem made of commercially available programmable logic arrays and discrete logic devices serves as interface between microprocessor and dual-channel MIL-STD-1553 data bus. Subsystem consumes only 800 mW of power. Provides flexibility in that it is controllable via firmware. Includes only two reading-and-writing ports: one for status and control signals, other for transmission and reception of data.

Spacelab, Spacehab, and Space Station Freedom payload interface projects

NASA Technical Reports Server (NTRS)

Smith, Dean Lance

1992-01-01

Contributions were made to several projects. Howard Nguyen was assisted in developing the Space Station RPS (Rack Power Supply). The RPS is a computer controlled power supply that helps test equipment used for experiments before the equipment is installed on Space Station Freedom. Ron Bennett of General Electric Government Services was assisted in the design and analysis of the Standard Interface Rack Controller hardware and software. An analysis was made of the GPIB (General Purpose Interface Bus), looking for any potential problems while transmitting data across the bus, such as the interaction of the bus controller with a data talker and its listeners. An analysis was made of GPIB bus communications in general, including any negative impact the bus may have on transmitting data back to Earth. A study was made of transmitting digital data back to Earth over a video channel. A report was written about the study and a revised version of the report will be submitted for publication. Work was started on the design of a PC/AT compatible circuit board that will combine digital data with a video signal. Another PC/AT compatible circuit board is being designed to recover the digital data from the video signal. A proposal was submitted to support the continued development of the interface boards after the author returns to Memphis State University in the fall. A study was also made of storing circuit board design software and data on the hard disk server of a LAN (Local Area Network) that connects several IBM style PCs. A report was written that makes several recommendations. A preliminary design review was started of the AIVS (Automatic Interface Verification System). The summer was over before any significant contribution could be made to this project.

Interfacing external sensors with Android smartphones through near field communication

NASA Astrophysics Data System (ADS)

Leikanger, Tore; Häkkinen, Juha; Schuss, Christian

2017-04-01

In this paper, we present and evaluate a new approach to communicate with inter-integrated circuit (I2C) enabled circuits such as sensors over near field communication (NFC). The NFC-to-I2C interface was designed using a non-standard NFC command to control the I2C bus directly from a smartphone, which was controlling both, the read and write operations on the I2C bus. The NFC-to-I2C interface was reporting back the data bytes on the bus to the smartphone when the transaction was completed successfully. The proposed system was tested experimentally, both, with write and read requests to a commercial microcontroller featuring a hardware I2C port, as well as reading a commercial I2C enabled humidity and temperature sensor. We present experimental results of the system which show that our approach enables an easy interface between smartphones and external sensors. Interfacing external sensors is useful and beneficial for smartphone users, especially, if certain types of sensors are not available on smartphones.

Study and design on USB wireless laser communication system

NASA Astrophysics Data System (ADS)

Wang, Aihua; Zheng, Jiansheng; Ai, Yong

2004-04-01

We give the definition of USB wireless laser communication system (WLCS) and the brief introduction to the protocol of USB, the standard of hardware is also given. The paper analyses the hardware and software of USB WLCS. Wireless laser communication part and USB interface circuit part are discussed in detail. We also give the periphery design of the chip AN2131Q, the control circuit to realize the transformation from parallel port to serial bus, and the circuit of laser sending and receiving of laser communication part, which are simply, cheap and workable. And then the four part of software are analyzed as followed. We have consummated the ISR in the firmware frame to develop the periphery device of USB. We have debugged and consummated the 'ezload,' and the GPD of the drivers. Windows application performs functions and schedules the corresponding API functions to let the interface practical and beautiful. The system can realize USB wireless laser communication between computers, which distance is farther than 50 meters, and top speed can be bigger than 8 Mbps. The system is of great practical sense to resolve the issues of high-speed communication among increasing districts without fiber trunk network.

SCSI Communication Test Bus

NASA Technical Reports Server (NTRS)

Hua, Chanh V.; D'Ambrose, John J.; Jaworski, Richard C.; Halula, Elaine M.; Thornton, David N.; Heligman, Robert L.; Turner, Michael R.

1990-01-01

Small Computer System Interface (SCSI) communication test bus provides high-data-rate, standard interconnection enabling communication among International Business Machines (IBM) Personal System/2 Micro Channel, other devices connected to Micro Channel, test equipment, and host computer. Serves primarily as nonintrusive input/output attachment to PS/2 Micro Channel bus, providing rapid communication for debugger. Opens up possibility of using debugger in real-time applications.

Configurable Crossbar Switch for Deterministic, Low-latency Inter-blade Communications in a MicroTCA Platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karamooz, Saeed; Breeding, John Eric; Justice, T Alan

As MicroTCA expands into applications beyond the telecommunications industry from which it originated, it faces new challenges in the area of inter-blade communications. The ability to achieve deterministic, low-latency communications between blades is critical to realizing a scalable architecture. In the past, legacy bus architectures accomplished inter-blade communications using dedicated parallel buses across the backplane. Because of limited fabric resources on its backplane, MicroTCA uses the carrier hub (MCH) for this purpose. Unfortunately, MCH products from commercial vendors are limited to standard bus protocols such as PCI Express, Serial Rapid IO and 10/40GbE. While these protocols have exceptional throughput capability,more » they are neither deterministic nor necessarily low-latency. To overcome this limitation, an MCH has been developed based on the Xilinx Virtex-7 690T FPGA. This MCH provides the system architect/developer complete flexibility in both the interface protocol and routing of information between blades. In this paper, we present the application of this configurable MCH concept to the Machine Protection System under development for the Spallation Neutron Sources's proton accelerator. Specifically, we demonstrate the use of the configurable MCH as a 12x4-lane crossbar switch using the Aurora protocol to achieve a deterministic, low-latency data link. In this configuration, the crossbar has an aggregate bandwidth of 48 GB/s.« less

Modular, thermal bus-to-radiator integral heat exchanger design for Space Station Freedom

NASA Technical Reports Server (NTRS)

Chambliss, Joe; Ewert, Michael

1990-01-01

The baseline concept is introduced for the 'integral heat exchanger' (IHX) which is the interface of the two-phase thermal bus with the heat-rejecting radiator panels. A direct bus-to-radiator heat-pipe integral connection replaces the present interface hardware to reduce the weight and complexity of the heat-exchange mechanism. The IHX is presented in detail and compared to the baseline system assuming certain values for heat rejection, mass per unit width, condenser capacity, contact conductance, and assembly mass. The spreadsheet comparison can be used to examine a variety of parameters such as radiator length and configuration. The IHX is shown to permit the reduction of panel size and system mass in response to better conductance and packaging efficiency. The IHX is found to be a suitable heat-rejection system for the Space Station Freedom because it uses present technology and eliminates the interface mechanisms.

Multiple IMU system hardware interface design, volume 2

NASA Technical Reports Server (NTRS)

Landey, M.; Brown, D.

1975-01-01

The design of each system component is described. Emphasis is placed on functional requirements unique in this system, including data bus communication, data bus transmitters and receivers, and ternary-to-binary torquing decision logic. Mechanization drawings are presented.

Universal Controller for Spacecraft Mechanisms

NASA Technical Reports Server (NTRS)

Levanas, Greg; McCarthy, Thomas; Hunter, Don; Buchanan, Christine; Johnson, Michael; Cozy, Raymond; Morgan, Albert; Tran, Hung

2006-01-01

An electronic control unit has been fabricated and tested that can be replicated as a universal interface between the electronic infrastructure of a spacecraft and a brushless-motor (or other electromechanical actuator) driven mechanism that performs a specific mechanical function within the overall spacecraft system. The unit includes interfaces to a variety of spacecraft sensors, power outputs, and has selectable actuator control parameters making the assembly a mechanism controller. Several control topologies are selectable and reconfigurable at any time. This allows the same actuator to perform different functions during the mission life of the spacecraft. The unit includes complementary metal oxide/semiconductor electronic components on a circuit board of a type called rigid flex (signifying flexible printed wiring along with a rigid substrate). The rigid flex board is folded to make the unit fit into a housing on the back of a motor. The assembly has redundant critical interfaces, allowing the controller to perform time-critical operations when no human interface with the hardware is possible. The controller is designed to function over a wide temperature range without the need for thermal control, including withstanding significant thermal cycling, making it usable in nearly all environments that spacecraft or landers will endure. A prototype has withstood 1,500 thermal cycles between 120 and +85 C without significant deterioration of its packaging or electronic function. Because there is no need for thermal control and the unit is addressed through a serial bus interface, the cabling and other system hardware are substantially reduced in quantity and complexity, with corresponding reductions in overall spacecraft mass and cost.

Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Ellerbrock, Philip J. (Inventor); Grant, Robert L. (Inventor); Konz, Daniel W. (Inventor); Winkelmann, Joseph P. (Inventor)

2005-01-01

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is then converted by the network device interface into digital signals and transmitted back to the controller. In one advantageous embodiment, the network device interface uses a specialized protocol for communicating across the network bus that uses a low-level instruction set and has low overhead for data communication.

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Konz, Daniel W. (Inventor); Winkelmann, Joseph P. (Inventor); Ellerbrock, Philip J. (Inventor); Grant, Robert L. (Inventor)

2007-01-01

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is converted into digital signals and transmitted to the controller. In some embodiments, network device interfaces associated with different data channels coordinate communications with the other interfaces based on either a transition in a command message sent by the bus controller or a synchronous clock signal.

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Ellerbrock, Philip J. (Inventor); Winkelmann, Joseph P. (Inventor); Grant, Robert L. (Inventor); Konz, Daniel W. (Inventor)

2006-01-01

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is then converted by the network device interface into digital signals and transmitted back to the controller. In one advantageous embodiment, the network device interface is a state machine, such as an ASIC, that operates independent of a processor in communicating with the bus controller and data channels.

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Ellerbrock, Philip J. (Inventor); Konz, Daniel W. (Inventor); Winkelmann, Joseph P. (Inventor); Grant, Robert L. (Inventor)

2004-01-01

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is then converted by the network device interface into digital signals and transmitted back to the controller. In one advantageous embodiment, the network device interface uses a specialized protocol for communicating across the network bus that uses a low-level instruction set and has low overhead for data communication.

Decentralized and Modular Electrical Architecture

NASA Astrophysics Data System (ADS)

Elisabelar, Christian; Lebaratoux, Laurence

2014-08-01

This paper presents the studies made on the definition and design of a decentralized and modular electrical architecture that can be used for power distribution, active thermal control (ATC), standard inputs-outputs electrical interfaces.Traditionally implemented inside central unit like OBC or RTU, these interfaces can be dispatched in the satellite by using MicroRTU.CNES propose a similar approach of MicroRTU. The system is based on a bus called BRIO (Bus Réparti des IO), which is composed, by a power bus and a RS485 digital bus. BRIO architecture is made with several miniature terminals called BTCU (BRIO Terminal Control Unit) distributed in the spacecraft.The challenge was to design and develop the BTCU with very little volume, low consumption and low cost. The standard BTCU models are developed and qualified with a configuration dedicated to ATC, while the first flight model will fly on MICROSCOPE for PYRO actuations and analogue acquisitions. The design of the BTCU is made in order to be easily adaptable for all type of electric interface needs.Extension of this concept is envisaged for power conditioning and distribution unit, and a Modular PCDU based on BRIO concept is proposed.

[Universal electrogustometer EG-2].

PubMed

Wałkanis, Andrzej; Czesak, Michał; Pleskacz, Witold A

2011-01-01

Electrogustometry is a method for taste diagnosis and measurement. The EG-2 project is being developed in cooperation between Warsaw University of Technology and Military institute of Medicine in Warsaw. The device is an evolution of the recent universal electrogustometer EG-1 prototype. Due to considerations and experiences acquired during prototype usage, many enhancements have been incorporated into device. The aim was to create an easy-to-use, portable, battery powered device, enabled for fast measurements. Developed electrogustometer is using innovative, low-power microprocessor system, which control whole device. User interface is based on 5.7" graphical LCD (Liquid Crystal Display) and touchscreen. It can be directly operated by finger or with optional stylus. Dedicated GUI (Graphical User Interface) offers simple, predefined measurements and advance settings of signal parameters. It is also possible to store measurements results and patients data in an internal memory. User interface is multilanguage. Signals for patients examinations, supplied with bipolar electrode, are generated by an on-board circuit using DDS (Direct-Digital Synthesis) and DAC (Digital-to-Analog Converter). Electrogustometer is able to generate DC, sinus, triangle or rectangle signals with current amplitude from 0 to 500 pA and frequency form 0 to 500 Hz. Device is designed for manual and automeasurement modes. By using USB (Universal Serial Bus) port it is possible to retrieve data stored in internal memory and charging of built-in Li-lon battery as a source of power.

Common Readout Unit (CRU) - A new readout architecture for the ALICE experiment

NASA Astrophysics Data System (ADS)

Mitra, J.; Khan, S. A.; Mukherjee, S.; Paul, R.

2016-03-01

The ALICE experiment at the CERN Large Hadron Collider (LHC) is presently going for a major upgrade in order to fully exploit the scientific potential of the upcoming high luminosity run, scheduled to start in the year 2021. The high interaction rate and the large event size will result in an experimental data flow of about 1 TB/s from the detectors, which need to be processed before sending to the online computing system and data storage. This processing is done in a dedicated Common Readout Unit (CRU), proposed for data aggregation, trigger and timing distribution and control moderation. It act as common interface between sub-detector electronic systems, computing system and trigger processors. The interface links include GBT, TTC-PON and PCIe. GBT (Gigabit transceiver) is used for detector data payload transmission and fixed latency path for trigger distribution between CRU and detector readout electronics. TTC-PON (Timing, Trigger and Control via Passive Optical Network) is employed for time multiplex trigger distribution between CRU and Central Trigger Processor (CTP). PCIe (Peripheral Component Interconnect Express) is the high-speed serial computer expansion bus standard for bulk data transport between CRU boards and processors. In this article, we give an overview of CRU architecture in ALICE, discuss the different interfaces, along with the firmware design and implementation of CRU on the LHCb PCIe40 board.

Current limiting remote power control module

NASA Technical Reports Server (NTRS)

Hopkins, Douglas C.

1990-01-01

The power source for the Space Station Freedom will be fully utilized nearly all of the time. As such, any loads on the system will need to operate within expected limits. Should any load draw an inordinate amount of power, the bus voltage for the system may sag and disrupt the operation of other loads. To protect the bus and loads some type of power interface between the bus and each load must be provided. This interface is most crucial when load faults occur. A possible system configuration is presented. The proposed interface is the Current Limiting Remote Power Controller (CL-RPC). Such an interface should provide the following power functions: limit overloading and resulting undervoltage; prevent catastrophic failure and still provide for redundancy management within the load; minimize cable heating; and provide accurate current measurement. A functional block diagram of the power processing stage of a CL-RPC is included. There are four functions that drive the circuit design: rate control of current; current sensing; the variable conductance switch (VCS) technology; and the algorithm used for current limiting. Each function is discussed separately.

Network Management System for Tactical Mobile Ad Hoc Network Segments

DTIC Science & Technology

2011-09-01

Protocol UFO UHF Follow-On UHF Ultra High Frequency USB Universal Serial Bus VHF Very High Frequency VIRT Valuable Information at the Right Time...military satellite system known as the UHF Follow-on system ( UFO ) only provides capacity for 600 concurrent users. DoD users also have commercial

Discharging a DC bus capacitor of an electrical converter system

DOEpatents

Kajouke, Lateef A; Perisic, Milun; Ransom, Ray M

2014-10-14

A system and method of discharging a bus capacitor of a bidirectional matrix converter of a vehicle are presented here. The method begins by electrically shorting the AC interface of the converter after an AC energy source is disconnected from the AC interface. The method continues by arranging a plurality of switching elements of a second energy conversion module into a discharge configuration to establish an electrical current path from a first terminal of an isolation module, through an inductive element, and to a second terminal of the isolation module. The method also modulates a plurality of switching elements of a first energy conversion module, while maintaining the discharge configuration of the second energy conversion module, to at least partially discharge a DC bus capacitor.

Serial network simplifies the design of multiple microcomputer systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Folkes, D.

1981-01-01

Recently there has been a lot of interest in developing network communication schemes for carrying digital data between locally distributed computing stations. Many of these schemes have focused on distributed networking techniques for data processing applications. These applications suggest the use of a serial, multipoint bus, where a number of remote intelligent units act as slaves to a central or host computer. Each slave would be serially addressable from the host and would perform required operations upon being addressed by the host. Based on an MK3873 single-chip microcomputer, the SCU 20 is designed to be such a remote slave device.more » The capabilities of the SCU 20 and its use in systems applications are examined.« less

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Ellerbrock, Philip J. (Inventor); Grant, Robert L. (Inventor); Winkelmann, Joseph P. (Inventor); Konz, Daniel W. (Inventor)

2009-01-01

A communications system and method are provided for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is converted into digital signals and transmitted to the controller. Network device interfaces associated with different data channels can coordinate communications with the other interfaces based on either a transition in a command message sent by the bus controller or a synchronous clock signal.

Microfluidic Serial Dilution Circuit

PubMed Central

Paegel, Brian M.; Grover, William H.; Skelley, Alison M.; Mathies, Richard A.; Joyce, Gerald F.

2008-01-01

In vitro evolution of RNA molecules requires a method for executing many consecutive serial dilutions. To solve this problem, a microfluidic circuit has been fabricated in a three-layer glass-PDMS-glass device. The 400-nL serial dilution circuit contains five integrated membrane valves: three two-way valves arranged in a loop to drive cyclic mixing of the diluent and carryover, and two bus valves to control fluidic access to the circuit through input and output channels. By varying the valve placement in the circuit, carryover fractions from 0.04 to 0.2 were obtained. Each dilution process, which is comprised of a diluent flush cycle followed by a mixing cycle, is carried out with no pipeting, and a sample volume of 400 nL is sufficient for conducting an arbitrary number of serial dilutions. Mixing is precisely controlled by changing the cyclic pumping rate, with a minimum mixing time of 22 s. This microfluidic circuit is generally applicable for integrating automated serial dilution and sample preparation in almost any microfluidic architecture. PMID:17073422

A compact 45 kV curve tracer with picoampere current measurement capability.

PubMed

Sullivan, W W; Mauch, D; Bullick, A; Hettler, C; Neuber, A; Dickens, J

2013-03-01

This paper discusses a compact high voltage curve tracer for high voltage semiconductor device characterization. The system sources up to 3 mA at up to 45 kV in dc conditions. It measures from 328 V to 60 kV with 15 V resolution and from 9.4 pA to 4 mA with 100 fA minimum resolution. Control software for the system is written in Microsoft Visual C# and features real-time measurement control and IV plotting, arc-protection and detection, an electrically isolated universal serial bus interface, and easy data exporting capabilities. The system has survived numerous catastrophic high voltage device-under-test arcing failures with no loss of measurement capability or system damage. Overall sweep times are typically under 2 min, and the curve tracer system was used to characterize the blocking performance of high voltage ceramic capacitors, high voltage silicon carbide photoconductive semiconductor switches, and high voltage coaxial cable.

Command Interface ASIC - Analog Interface ASIC Chip Set

NASA Technical Reports Server (NTRS)

Ruiz, Baldes; Jaffe, Burton; Burke, Gary; Lung, Gerald; Pixler, Gregory; Plummer, Joe; Katanyoutanant,, Sunant; Whitaker, William

2003-01-01

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.

Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

NASA Technical Reports Server (NTRS)

Bartram, Peter N.

1989-01-01

The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hansen, Timothy M.; Palmintier, Bryan; Suryanarayanan, Siddharth

As more Smart Grid technologies (e.g., distributed photovoltaic, spatially distributed electric vehicle charging) are integrated into distribution grids, static distribution simulations are no longer sufficient for performing modeling and analysis. GridLAB-D is an agent-based distribution system simulation environment that allows fine-grained end-user models, including geospatial and network topology detail. A problem exists in that, without outside intervention, once the GridLAB-D simulation begins execution, it will run to completion without allowing the real-time interaction of Smart Grid controls, such as home energy management systems and aggregator control. We address this lack of runtime interaction by designing a flexible communication interface, Bus.pymore » (pronounced bus-dot-pie), that uses Python to pass messages between one or more GridLAB-D instances and a Smart Grid simulator. This work describes the design and implementation of Bus.py, discusses its usefulness in terms of some Smart Grid scenarios, and provides an example of an aggregator-based residential demand response system interacting with GridLAB-D through Bus.py. The small scale example demonstrates the validity of the interface and shows that an aggregator using said interface is able to control residential loads in GridLAB-D during runtime to cause a reduction in the peak load on the distribution system in (a) peak reduction and (b) time-of-use pricing cases.« less

Isolating USB connections in medical equipment.

PubMed

Broeders, Jan-Hein

2009-01-01

Although offering several benefits, the universal serial bus (USB) port has not been rapidly adopted for connecting medical equipment. This is because it could affect safety procedures, with equipment not operating isolated from the mains. To overcome this, a single package isolation device has been developed that can be inserted directly into the USB signal path.

Infrared-Proximity-Sensor Modules For Robot

NASA Technical Reports Server (NTRS)

Parton, William; Wegerif, Daniel; Rosinski, Douglas

1995-01-01

Collision-avoidance system for articulated robot manipulators uses infrared proximity sensors grouped together in array of sensor modules. Sensor modules, called "sensorCells," distributed processing board-level products for acquiring data from proximity-sensors strategically mounted on robot manipulators. Each sensorCell self-contained and consists of multiple sensing elements, discrete electronics, microcontroller and communications components. Modules connected to central control computer by redundant serial digital communication subsystem including both serial and a multi-drop bus. Detects objects made of various materials at distance of up to 50 cm. For some materials, such as thermal protection system tiles, detection range reduced to approximately 20 cm.

NEW EPICS/RTEMS IOC BASED ON ALTERA SOC AT JEFFERSON LAB

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, Jianxun; Seaton, Chad; Allison, Trent L.

A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA is being designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 Hard Processor System (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via U-Boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDR3 SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications atmore » runtime. U-Boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run RTEMS and EPICS. The first design of the SoC IOC will be compatible with Jefferson Lab’s current PC104 IOCs, which have been running in CEBAF 10 years. The next design would be mounting in a chassis and connected to a daughter card via standard HSMC connectors. This standard SoC IOC will become the next generation of low-level IOC for the accelerator controls at Jefferson Lab.« less

Concept Study on a Flexible Standard Bus for Small Scientific Satellites

NASA Astrophysics Data System (ADS)

Fukuda, Seisuke; Sawai, Shujiro; Sakai, Shin-Ichiro; Saito, Hirobumi; Tohma, Takayuki; Takahashi, Junko; Toriumi, Tsuyoshi; Kitade, Kenji

In this paper, a new standard bus system for a series of small scientific satellites in the Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency (ISAS/JAXA) is described. Since each mission proposed for the series has a wide variety of requirements, a lot of efforts are needed to enhance flexibility of the standard bus. Some concepts from different viewpoints are proposed. First, standardization layers concerning satellite configuration, instruments, interfaces, and design methods are defined respectively. Methods of product platform engineering, which classify specifications of the bus system into a core platform, alternative variants, and selectable variants, are also investigated in order to realize a semi-custom-made bus. Furthermore, a tradeoff between integration and modularization architecture is fully considered.

Smart Power Supply for Battery-Powered Systems

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.; Greer, Lawrence; Prokop, Norman F.; Flatico, Joseph M.

2010-01-01

A power supply for battery-powered systems has been designed with an embedded controller that is capable of monitoring and maintaining batteries, charging hardware, while maintaining output power. The power supply is primarily designed for rovers and other remote science and engineering vehicles, but it can be used in any battery alone, or battery and charging source applications. The supply can function autonomously, or can be connected to a host processor through a serial communications link. It can be programmed a priori or on the fly to return current and voltage readings to a host. It has two output power busses: a constant 24-V direct current nominal bus, and a programmable bus for output from approximately 24 up to approximately 50 V. The programmable bus voltage level, and its output power limit, can be changed on the fly as well. The power supply also offers options to reduce the programmable bus to 24 V when the set power limit is reached, limiting output power in the case of a system fault detected in the system. The smart power supply is based on an embedded 8051-type single-chip microcontroller. This choice was made in that a credible progression to flight (radiation hard, high reliability) can be assumed as many 8051 processors or gate arrays capable of accepting 8051-type core presently exist and will continue to do so for some time. To solve the problem of centralized control, this innovation moves an embedded microcontroller to the power supply and assigns it the task of overseeing the operation and charging of the power supply assets. This embedded processor is connected to the application central processor via a serial data link such that the central processor can request updates of various parameters within the supply, such as battery current, bus voltage, remaining power in battery estimations, etc. This supply has a direct connection to the battery bus for common (quiescent) power application. Because components from multiple vendors may have differing power needs, this supply also has a secondary power bus, which can be programmed a priori or on-the-fly to boost the primary battery voltage level from 24 to 50 V to accommodate various loads as they are brought on line. Through voltage and current monitoring, the device can also shield the charging source from overloads, keep it within safe operating modes, and can meter available power to the application and maintain safe operations.

Network Extender for MIL-STD-1553 Bus

NASA Technical Reports Server (NTRS)

Marcus, Julius; Hanson, T. David

2003-01-01

An extender system for MIL-STD-1553 buses transparently couples bus components at multiple developer sites. The bus network extender is a relatively inexpensive system that minimizes the time and cost of integration of avionic systems by providing a convenient mechanism for early testing without the need to transport the usual test equipment and personnel to an integration facility. This bus network extender can thus alleviate overloading of the test facility while enabling the detection of interface problems that can occur during the integration of avionic systems. With this bus extender in place, developers can correct and adjust their own hardware and software before products leave a development site. Currently resident at Johnson Space Center, the bus network extender is used to test the functionality of equipment that, although remotely located, is connected through a MILSTD- 1553 bus. Inasmuch as the standard bus protocol for avionic equipment is that of MIL-STD-1553, companies that supply MIL-STD-1553-compliant equipment to government or industry and that need long-distance communication support might benefit from this network bus extender

Development of gallium arsenide high-speed, low-power serial parallel interface modules: Executive summary

NASA Technical Reports Server (NTRS)

1988-01-01

Final report to NASA LeRC on the development of gallium arsenide (GaAS) high-speed, low power serial/parallel interface modules. The report discusses the development and test of a family of 16, 32 and 64 bit parallel to serial and serial to parallel integrated circuits using a self aligned gate MESFET technology developed at the Honeywell Sensors and Signal Processing Laboratory. Lab testing demonstrated 1.3 GHz clock rates at a power of 300 mW. This work was accomplished under contract number NAS3-24676.

Interface Circuit Board For Space-Shuttle Communications

NASA Technical Reports Server (NTRS)

Parrish, Brett T.

1995-01-01

Report describes interface electronic circuit developed to enable ground controllers to send commands and data via Ku-band radio uplink to multiple circuits connected to standard IEEE-488 general-purpose interface bus in space shuttle. Design of circuit extends data-throughput capability of communication system.

A Survey of Some Approaches to Distributed Data Base & Distributed File System Architecture.

DTIC Science & Technology

1980-01-01

BUS POD A DD A 12 12 A = A Cell D = D Cell Figure 7-1: MUFFIN logical architecture - 45 - MUFI January 1980 ".-.Bus Interface V Conventional Processor...and Applied Mathematics (14), * December, 1966. [Kimbleton 791 Kimbleton, Stephen; Wang, Pearl; and Fong, Elizabeth. XNDM: An Experimental Network

Plug-and-Play Environmental Monitoring Spacecraft Subsystem

NASA Technical Reports Server (NTRS)

Patel, Jagdish; Brinza, David E.; Tran, Tuan A.; Blaes, Brent R.

2011-01-01

A Space Environment Monitor (SEM) subsystem architecture has been developed and demonstrated that can benefit future spacecraft by providing (1) real-time knowledge of the spacecraft state in terms of exposure to the environment; (2) critical, instantaneous information for anomaly resolution; and (3) invaluable environmental data for designing future missions. The SEM architecture consists of a network of plug-and- play (PnP) Sensor Interface Units (SIUs), each servicing one or more environmental sensors. The SEM architecture is influenced by the IEEE Smart Transducer Interface Bus standard (IEEE Std 1451) for its PnP functionality. A network of PnP Spacecraft SIUs is enabling technology for gathering continuous real-time information critical to validating spacecraft health in harsh space environments. The demonstrated system that provided a proof-of-concept of the SEM architecture consisted of three SIUs for measurement of total ionizing dose (TID) and single event upset (SEU) radiation effects, electromagnetic interference (EMI), and deep dielectric charging through use of a prototype Internal Electro-Static Discharge Monitor (IESDM). Each SIU consists of two stacked 2X2 in. (approximately 5X5 cm) circuit boards: a Bus Interface Unit (BIU) board that provides data conversion, processing and connection to the SEM power-and-data bus, and a Sensor Interface Electronics (SIE) board that provides sensor interface needs and data path connection to the BIU.

Alignment and testing of critical interface fixtures for the James Webb Space Telescope

NASA Astrophysics Data System (ADS)

McLean, Kyle; Bagdanove, Paul; Berrier, Joshua; Cofie, Emmanuel; Glassman, Tiffany; Hadjimichael, Theodore; Johnson, Eric; Levi, Joshua; Lo, Amy; McMann, Joseph; Ohl, Raymond; Osgood, Dean; Parker, James; Redman, Kevin; Roberts, Vicki; Stephens, Matthew; Sutton, Adam; Wenzel, Greg; Young, Jerrod

2017-08-01

NASA's James Webb Space Telescope (JWST) is a 6.5m diameter, segmented, deployable telescope for cryogenic IR space astronomy. The JWST Observatory architecture includes the Primary Mirror Backplane Support Structure (PMBSS) and Integrated Science Instrument Module (ISIM) Electronics Compartment (IEC) which is designed to integrate to the spacecraft bus via six cup/cone interfaces. Prior to integration to the spacecraft bus, the JWST observatory must undergo environmental testing, handling, and transportation. Multiple fixtures were developed to support these tasks including the vibration fixture and handling and integration fixture (HIF). This work reports on the development of the nominal alignment of the six interfaces and metrology operations performed for the JWST observatory to safely integrate them for successful environmental testing.

Alignment and Testing of Critical Interface Fixtures for the James Webb Space Telescope

NASA Technical Reports Server (NTRS)

Mclean, Kyle; Bagdanove, Paul; Berrier, Joshua; Cofie, Emmanuel; Glassman, Tiffany; Hadjimichael, Theodore; Johnson, Eric; Levi, Joshua; Lo, Amy; McMann, Joseph;

Alignment and Testing of Critical Interface Fixtures for the James Webb Space Telescope

NASA Technical Reports Server (NTRS)

Mclean, Kyle; Bagdanove, Paul; Berrier, Joshua; Cofie, Emmanuel; Glassman, Tiffany; Hadjimichael, Theodore; Johnson, Eric; Levi, Joshua; Lo, Amy; McMann, Joseph;

Fast Low-Cost Multiple Sensor Readout System

DOEpatents

Carter-Lewis, David; Krennich, Frank; Le Bohec, Stephane; Petry, Dirk; Sleege, Gary

2004-04-06

A low resolution data acquisition system is presented. The data acquisition system has a plurality of readout modules serially connected to a controller. Each readout module has a FPGA in communication with analog to digital (A/D) converters, which are connected to sensors. The A/D converter has eight bit or lower resolution. The FPGA detects when a command is addressed to it and commands the A/D converters to convert analog sensor data into digital data. The digital data is sent on a high speed serial communication bus to the controller. A graphical display is used in one embodiment to indicate if a sensor reading is outside of a predetermined range.

Implementation of a Landscape Lighting System to Display Images

NASA Astrophysics Data System (ADS)

Sun, Gi-Ju; Cho, Sung-Jae; Kim, Chang-Beom; Moon, Cheol-Hong

The system implemented in this study consists of a PC, MASTER, SLAVEs and MODULEs. The PC sets the various landscape lighting displays, and the image files can be sent to the MASTER through a virtual serial port connected to the USB (Universal Serial Bus). The MASTER sends a sync signal to the SLAVE. The SLAVE uses the signal received from the MASTER and the landscape lighting display pattern. The video file is saved in the NAND Flash memory and the R, G, B signals are separated using the self-made display signal and sent to the MODULE so that it can display the image.

A portable toolbox to monitor and evaluate signal operations.

DOT National Transportation Integrated Search

2011-10-01

Researchers from the Texas Transportation Institute developed a portable tool consisting of a fieldhardened : computer interfacing with the traffic signal cabinet through special enhanced Bus Interface Units. : The toolbox consisted of a monitoring t...

Eight microprocessor-based instrument data systems in the Galileo Orbiter spacecraft

NASA Technical Reports Server (NTRS)

Barry, R. C.

1980-01-01

Instrument data systems consist of a microprocessor, 3K bytes of Read Only Memory and 3K bytes of Random Access Memory. It interfaces with the spacecraft data bus through an isolated user interface with a direct memory access bus adaptor, and/or parallel data from instrument devices such as registers, buffers, analog to digital converters, multiplexers, and solid state sensors. These data systems support the spacecraft hardware and software communication protocol, decode and process instrument commands, generate continuous instrument operating modes, control the instrument mechanisms, acquire, process, format, and output instrument science data.

A minimal SATA III Host Controller based on FPGA

NASA Astrophysics Data System (ADS)

Liu, Hailiang

2018-03-01

SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

76 FR 42730 - In the Matter of Certain Univeral Serial Bus (“USB”) Portable Storage Devices, Including USB...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-19

..., as amended, 19 U.S.C. 1337, on behalf of Trek 2000 International Ltd., of Singapore; Trek Technology (Singapore) Pte. Ltd. of Singapore; and S-Com System (S) Pte. Ltd. of Singapore. The complaint alleges...''). The complaint further alleges that an industry in the United States exists as required by subsection...

Adaptive Distributed Intelligent Control Architecture for Future Propulsion Systems (Preprint)

DTIC Science & Technology

2007-04-01

weight will be reduced by replacing heavy harness assemblies and FADECs , with distributed processing elements interconnected. This paper reviews...Digital Electronic Controls ( FADECs ), with distributed processing elements interconnected through a serial bus. Efficient data flow throughout the...because intelligence is embedded in components while overall control is maintained in the FADEC . The need for Distributed Control Systems in

CANOPEN Controller IP Core

NASA Astrophysics Data System (ADS)

Caramia, Maurizio; Montagna, Mario; Furano, Gianluca; Winton, Alistair

2010-08-01

This paper will describe the activities performed by Thales Alenia Space Italia supported by the European Space Agency in the definition of a CAN bus interface to be used on Exomars. The final goal of this activity is the development of an IP core, to be used in a slave node, able to manage both the CAN bus Data Link and Application Layer totally in hardware. The activity has been focused on the needs of the EXOMARS mission where devices with different computational performances are all managed by the onboard computer through the CAN bus.

Circuit for Communication Over Power Lines

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

2011-01-01

Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

Distributed multiport memory architecture

NASA Technical Reports Server (NTRS)

Kohl, W. H. (Inventor)

1983-01-01

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Instrumentation & Data Acquisition System (D AS) Engineer

NASA Technical Reports Server (NTRS)

Jackson, Markus Deon

2015-01-01

The primary job of an Instrumentation and Data Acquisition System (DAS) Engineer is to properly measure physical phenomenon of hardware using appropriate instrumentation and DAS equipment designed to record data during a specified test of the hardware. A DAS system includes a CPU or processor, a data storage device such as a hard drive, a data communication bus such as Universal Serial Bus, software to control the DAS system processes like calibrations, recording of data and processing of data. It also includes signal conditioning amplifiers, and certain sensors for specified measurements. My internship responsibilities have included testing and adjusting Pacific Instruments Model 9355 signal conditioning amplifiers, writing and performing checkout procedures, writing and performing calibration procedures while learning the basics of instrumentation.

A serial digital data communications device. [for real time flight simulation

NASA Technical Reports Server (NTRS)

Fetter, J. L.

1977-01-01

A general purpose computer peripheral device which is used to provide a full-duplex, serial, digital data transmission link between a Xerox Sigma computer and a wide variety of external equipment, including computers, terminals, and special purpose devices is reported. The interface has an extensive set of user defined options to assist the user in establishing the necessary data links. This report describes those options and other features of the serial communications interface and its performance by discussing its application to a particular problem.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy.

PubMed

Mehta, M M; Chandrasekhar, V

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy

NASA Astrophysics Data System (ADS)

Mehta, M. M.; Chandrasekhar, V.

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

The Wettzell System Monitoring Concept and First Realizations

NASA Technical Reports Server (NTRS)

Ettl, Martin; Neidhardt, Alexander; Muehlbauer, Matthias; Ploetz, Christian; Beaudoin, Christopher

2010-01-01

Automated monitoring of operational system parameters for the geodetic space techniques is becoming more important in order to improve the geodetic data and to ensure the safety and stability of automatic and remote-controlled observations. Therefore, the Wettzell group has developed the system monitoring software, SysMon, which is based on a reliable, remotely-controllable hardware/software realization. A multi-layered data logging system based on a fanless, robust industrial PC with an internal database system is used to collect data from several external, serial, bus, or PCI-based sensors. The internal communication is realized with Remote Procedure Calls (RPC) and uses generative programming with the interface software generator idl2rpc.pl developed at Wettzell. Each data monitoring stream can be configured individually via configuration files to define the logging rates or analog-digital-conversion parameters. First realizations are currently installed at the new laser ranging system at Wettzell to address safety issues and at the VLBI station O Higgins as a meteorological data logger. The system monitoring concept should be realized for the Wettzell radio telescope in the near future.

Development of a portable Linux-based ECG measurement and monitoring system.

PubMed

Tan, Tan-Hsu; Chang, Ching-Su; Huang, Yung-Fa; Chen, Yung-Fu; Lee, Cheng

2011-08-01

This work presents a portable Linux-based electrocardiogram (ECG) signals measurement and monitoring system. The proposed system consists of an ECG front end and an embedded Linux platform (ELP). The ECG front end digitizes 12-lead ECG signals acquired from electrodes and then delivers them to the ELP via a universal serial bus (USB) interface for storage, signal processing, and graphic display. The proposed system can be installed anywhere (e.g., offices, homes, healthcare centers and ambulances) to allow people to self-monitor their health conditions at any time. The proposed system also enables remote diagnosis via Internet. Additionally, the system has a 7-in. interactive TFT-LCD touch screen that enables users to execute various functions, such as scaling a single-lead or multiple-lead ECG waveforms. The effectiveness of the proposed system was verified by using a commercial 12-lead ECG signal simulator and in vivo experiments. In addition to its portability, the proposed system is license-free as Linux, an open-source code, is utilized during software development. The cost-effectiveness of the system significantly enhances its practical application for personal healthcare.

Information management system study results. Volume 2: IMS study results appendixes

NASA Technical Reports Server (NTRS)

1971-01-01

Computer systems program specifications are presented for the modular space station information management system. These are the computer program contract end item, data bus system, data bus breadboard, and display interface adapter specifications. The performance, design, tests, and qualification requirements are established for the implementation of the information management system. For Vol. 1, see N72-19972.

Apparatus, system and method for providing cryptographic key information with physically unclonable function circuitry

DOEpatents

Areno, Matthew

2015-12-08

Techniques and mechanisms for providing a value from physically unclonable function (PUF) circuitry for a cryptographic operation of a security module. In an embodiment, a cryptographic engine receives a value from PUF circuitry and based on the value, outputs a result of a cryptographic operation to a bus of the security module. The bus couples the cryptographic engine to control logic or interface logic of the security module. In another embodiment, the value is provided to the cryptographic engine from the PUF circuitry via a signal line which is distinct from the bus, where any exchange of the value by either of the cryptographic engine and the PUF circuitry is for communication of the first value independent of the bus.

Integrated circuit-based instrumentation for microchip capillary electrophoresis.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Martel, S; Elliott, D G; Backhouse, C J

2010-09-01

Although electrophoresis with laser-induced fluorescence (LIF) detection has tremendous potential in lab on chip-based point-of-care disease diagnostics, the wider use of microchip electrophoresis has been limited by the size and cost of the instrumentation. To address this challenge, the authors designed an integrated circuit (IC, i.e. a microelectronic chip, with total silicon area of <0.25 cm2, less than 5 mmx5 mm, and power consumption of 28 mW), which, with a minimal additional infrastructure, can perform microchip electrophoresis with LIF detection. The present work enables extremely compact and inexpensive portable systems consisting of one or more complementary metal-oxide-semiconductor (CMOS) chips and several other low-cost components. There are, to the authors' knowledge, no other reports of a CMOS-based LIF capillary electrophoresis instrument (i.e. high voltage generation, switching, control and interface circuit combined with LIF detection). This instrument is powered and controlled using a universal serial bus (USB) interface to a laptop computer. The authors demonstrate this IC in various configurations and can readily analyse the DNA produced by a standard medical diagnostic protocol (end-labelled polymerase chain reaction (PCR) product) with a limit of detection of approximately 1 ng/microl (approximately 1 ng of total DNA). The authors believe that this approach may ultimately enable lab-on-a-chip-based electrophoretic instruments that cost on the order of several dollars.

Laboratory Assessment of Commercially Available Ultrasonic Rangefinders

DTIC Science & Technology

2015-11-01

measurements . The Arduino board and ultrasonic rangefinder were connected to the computer via universal serial bus (USB) cable, which acted as both...the MB1023 sensor placed at 0.5 meters from an office space wall. Based on these p-values, measurements from three different angles were not...taking acoustic measurements in a particular environment, transducers and noise sources must first be spatially located. The United States Army

A Serial Bus Architecture for Parallel Processing Systems

DTIC Science & Technology

1986-09-01

pins are needed to effect the data transfer. As Integrated Circuits grow in computational power, more communication capacity is needed, pushing...chip. The wider the communication path the more pins are needed to effect the data transfer. As Integrated Circuits grow in computational power, more...13 2. A Suitable Architecture Sought 14 II. OPTIMUM ARCHITECTURE OF LARGE INTEGRATED A. PARTIONING SILICON FOR MAXIMUM 1? 1. Transistor

Cloud Computing Solutions for the Marine Corps: An Architecture to Support Expeditionary Logistics

DTIC Science & Technology

2013-09-01

reform IT financial , acquisition, and contracting practices (Takai, 2012). The second step is to optimize data center consolidation . Kundra (2010...the U.S. Government. IRB Protocol number ____N/A____. 12a. DISTRIBUTION / AVAILABILITY STATEMENT Approved for public release;distribution is...USB universal serial bus USMCELC United States Marine Corps Expeditionary Logistics Cloud UUNS urgent universal needs statement xix VA volt

Evaluation of the ImmerVision IMV1-1/3NI Panomorph Lens on a Small Unmanned Ground Vehicle (SUGV)

DTIC Science & Technology

2013-07-01

360°. For the above reason, a 1.3-MP Chameleon color universal serial bus (USB) camera with a 1/3-in CCD from PGR was selected instead of...recommended qualified cameras to host the panomorph lens. Having the advantage of a small footprint, the Chameleon camera with the IMV1 lens can be easily

Software interface for high-speed readout of particle detectors based on the CoaXPress communication standard

NASA Astrophysics Data System (ADS)

Hejtmánek, M.; Neue, G.; Voleš, P.

2015-06-01

This article is devoted to the software design and development of a high-speed readout application used for interfacing particle detectors via the CoaXPress communication standard. The CoaXPress provides an asymmetric high-speed serial connection over a single coaxial cable. It uses a widely available 75 Ω BNC standard and can operate in various modes with a data throughput ranging from 1.25 Gbps up to 25 Gbps. Moreover, it supports a low speed uplink with a fixed bit rate of 20.833 Mbps, which can be used to control and upload configuration data to the particle detector. The CoaXPress interface is an upcoming standard in medical imaging, therefore its usage promises long-term compatibility and versatility. This work presents an example of how to develop DAQ system for a pixel detector. For this purpose, a flexible DAQ card was developed using the XILINX Spartan 6 FPGA. The DAQ card is connected to the framegrabber FireBird CXP6 Quad, which is plugged in the PCI Express bus of the standard PC. The data transmission was performed between the FPGA and framegrabber card via the standard coaxial cable in communication mode with a bit rate of 3.125 Gbps. Using the Medipix2 Quad pixel detector, the framerate of 100 fps was achieved. The front-end application makes use of the FireBird framegrabber software development kit and is suitable for data acquisition as well as control of the detector through the registers implemented in the FPGA.

A programmable positioning stepper-motor controller with a multibus/IEEE 796 compatible interface.

PubMed

Papoff, P; Ricci, D

1984-02-01

A programmable positioning stepper-motor controller, based on the Multibus/IEEE 796 standard interface, has been assembled by use of some intelligent and programmable integrated circuits. This controller, organized as a bus-slave unit, has been planned for local management of up to four stepper motors working simultaneously. The number of steps, the direction of rotation and the step-rate for the positioning of each motor are issued by the bus master microcomputer to the controller which handles all the required operations. Once each positioning has been performed, the controller informs the master by generating a proper bus-vectored interrupt. Displacements in up to 64,000 steps may be programmed with step-rates ranging from 0.1 to 6550 steps/sec. This device, for which only low-cost, high-performance components are required, can be successfully used in a wide range of applications and can be easily extended to control more than four stepper motors.

Serial Interface through Stream Protocol on EPICS Platform for Distributed Control and Monitoring

NASA Astrophysics Data System (ADS)

Das Gupta, Arnab; Srivastava, Amit K.; Sunil, S.; Khan, Ziauddin

2017-04-01

Remote operation of any equipment or device is implemented in distributed systems in order to control and proper monitoring of process values. For such remote operations, Experimental Physics and Industrial Control System (EPICS) is used as one of the important software tool for control and monitoring of a wide range of scientific parameters. A hardware interface is developed for implementation of EPICS software so that different equipment such as data converters, power supplies, pump controllers etc. could be remotely operated through stream protocol. EPICS base was setup on windows as well as Linux operating system for control and monitoring while EPICS modules such as asyn and stream device were used to interface the equipment with standard RS-232/RS-485 protocol. Stream Device protocol communicates with the serial line with an interface to asyn drivers. Graphical user interface and alarm handling were implemented with Motif Editor and Display Manager (MEDM) and Alarm Handler (ALH) command line channel access utility tools. This paper will describe the developed application which was tested with different equipment and devices serially interfaced to the PCs on a distributed network.

Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus

NASA Technical Reports Server (NTRS)

Ruiz, Ian B.; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

NASA Technical Reports Server (NTRS)

Ruiz, B. Ian; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

Thematic mapper protoflight model preshipment review data package. Volume 4: Appendix. Part A: Multiplexer data book 2

NASA Technical Reports Server (NTRS)

1982-01-01

Final performance test data for the thematic mapper flight model multiplexer are presented in tables. Aspects covered include A/D thresholds for bands 5, 6, and 7; cross talk; the thermistor; bilevel commands signal parameters; A/D threshold ambient, voltage margin low bus; serial data and bit clock parameters; and the wire check. Tests were conducted at ambient temperature.

Wireless Sensor Buoys for Perimeter Security of Military Vessels and Seabases

DTIC Science & Technology

2015-12-01

however, additional sensors utilizing modern technology and a self -forming, as well as self - healing , network could further diminish attacks against...Space SSDF Ship’s Self -Defense Force UAV Unmanned Aerial Vehicle UGS Unattended Ground Sensor USB Universal Serial Bus USMC United States Marine...conditions may delay their reaction resulting in the attacking surface craft entering into a critically close position. The Ship’s Self -Defense

Implementation of Ada protocols on Mil-STD-1553 B data bus

NASA Technical Reports Server (NTRS)

Ruhman, Smil; Rosemberg, Flavia

1986-01-01

Standardization activity of data communication in avionic systems started in 1968 for the purpose of total system integration and the elimination of heavy wire bundles carrying signals between various subassemblies. The growing complexity of avionic systems is straining the capabilities of MIL-STD-1553 B (first issued in 1973), but a much greater challenge to it is posed by Ada, the standard language adopted for real-time, computer embedded-systems. Hardware implementation of Ada communication protocols in a contention/token bus or token ring network is proposed. However, during the transition period when the current command/response multiplex data bus is still flourishing and the development environment for distributed multi-computer Ada systems is as yet lacking, a temporary accomodation of the standard language with the standard bus could be very useful and even highly desirable. By concentrating all status informtion and decisions at the bus controller, it was found to be possible to construct an elegant and efficient harware impelementation of the Ada protocols at the bus interface. This solution is discussed.

Digital Autonomous Terminal Access Communication (DATAC) system

NASA Technical Reports Server (NTRS)

Novacki, Stanley M., III

1987-01-01

In order to accommodate the increasing number of computerized subsystems aboard today's more fuel efficient aircraft, the Boeing Co. has developed the DATAC (Digital Autonomous Terminal Access Control) bus to minimize the need for point-to-point wiring to interconnect these various systems, thereby reducing total aircraft weight and maintaining an economical flight configuration. The DATAC bus is essentially a local area network providing interconnections for any of the flight management and control systems aboard the aircraft. The task of developing a Bus Monitor Unit was broken down into four subtasks: (1) providing a hardware interface between the DATAC bus and the Z8000-based microcomputer system to be used as the bus monitor; (2) establishing a communication link between the Z8000 system and a CP/M-based computer system; (3) generation of data reduction and display software to output data to the console device; and (4) development of a DATAC Terminal Simulator to facilitate testing of the hardware and software which transfer data between the DATAC's bus and the operator's console in a near real time environment. These tasks are briefly discussed.

A programmable controller based on CAN field bus embedded microprocessor and FPGA

NASA Astrophysics Data System (ADS)

Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

2008-10-01

One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

TripAdvisor^{N-D}: A Tourism-Inspired High-Dimensional Space Exploration Framework with Overview and Detail.

PubMed

Nam, Julia EunJu; Mueller, Klaus

2013-02-01

Gaining a true appreciation of high-dimensional space remains difficult since all of the existing high-dimensional space exploration techniques serialize the space travel in some way. This is not so foreign to us since we, when traveling, also experience the world in a serial fashion. But we typically have access to a map to help with positioning, orientation, navigation, and trip planning. Here, we propose a multivariate data exploration tool that compares high-dimensional space navigation with a sightseeing trip. It decomposes this activity into five major tasks: 1) Identify the sights: use a map to identify the sights of interest and their location; 2) Plan the trip: connect the sights of interest along a specifyable path; 3) Go on the trip: travel along the route; 4) Hop off the bus: experience the location, look around, zoom into detail; and 5) Orient and localize: regain bearings in the map. We describe intuitive and interactive tools for all of these tasks, both global navigation within the map and local exploration of the data distributions. For the latter, we describe a polygonal touchpad interface which enables users to smoothly tilt the projection plane in high-dimensional space to produce multivariate scatterplots that best convey the data relationships under investigation. Motion parallax and illustrative motion trails aid in the perception of these transient patterns. We describe the use of our system within two applications: 1) the exploratory discovery of data configurations that best fit a personal preference in the presence of tradeoffs and 2) interactive cluster analysis via cluster sculpting in N-D.

Definition, analysis and development of an optical data distribution network for integrated avionics and control systems

NASA Technical Reports Server (NTRS)

Burns, R. R.

1981-01-01

The potential and functional requirements of fiber optic bus designs for next generation aircraft are assessed. State-of-the-art component evaluations and projections were used in the system study. Complex networks were decomposed into dedicated structures, star buses, and serial buses for detailed analysis. Comparisons of dedicated links, star buses, and serial buses with and without full duplex operation and with considerations for terminal to terminal communication requirements were obtained. This baseline was then used to consider potential extensions of busing methods to include wavelength multiplexing and optical switches. Example buses were illustrated for various areas of the aircraft as potential starting points for more detail analysis as the platform becomes definitized.

Lab Inputs for Common Micros.

ERIC Educational Resources Information Center

Tinker, Robert

1984-01-01

The game paddle inputs of Apple microcomputers provide a simple way to get laboratory measurements into the computer. Discusses these game paddles and the necessary interface software. Includes schematics for Apple built-in paddle electronics, TRS-80 game paddle I/O, Commodore circuit for user port, and bus interface for Sinclair/Timex, Commodore,…

An Overview of Starfish: A Table-Centric Tool for Interactive Synthesis

NASA Technical Reports Server (NTRS)

Tsow, Alex

2008-01-01

Engineering is an interactive process that requires intelligent interaction at many levels. My thesis [1] advances an engineering discipline for high-level synthesis and architectural decomposition that integrates perspicuous representation, designer interaction, and mathematical rigor. Starfish, the software prototype for the design method, implements a table-centric transformation system for reorganizing control-dominated system expressions into high-level architectures. Based on the digital design derivation (DDD) system a designer-guided synthesis technique that applies correctness preserving transformations to synchronous data flow specifications expressed as co- recursive stream equations Starfish enhances user interaction and extends the reachable design space by incorporating four innovations: behavior tables, serialization tables, data refinement, and operator retiming. Behavior tables express systems of co-recursive stream equations as a table of guarded signal updates. Developers and users of the DDD system used manually constructed behavior tables to help them decide which transformations to apply and how to specify them. These design exercises produced several formally constructed hardware implementations: the FM9001 microprocessor, an SECD machine for evaluating LISP, and the SchemEngine, garbage collected machine for interpreting a byte-code representation of compiled Scheme programs. Bose and Tuna, two of DDD s developers, have subsequently commercialized the design derivation methodology at Derivation Systems, Inc. (DSI). DSI has formally derived and validated PCI bus interfaces and a Java byte-code processor; they further executed a contract to prototype SPIDER-NASA's ultra-reliable communications bus. To date, most derivations from DDD and DRS have targeted hardware due to its synchronous design paradigm. However, Starfish expressions are independent of the synchronization mechanism; there is no commitment to hardware or globally broadcast clocks. Though software back-ends for design derivation are limited to the DDD stream-interpreter, targeting synchronous or real-time software is not substantively different from targeting hardware.

Design of a real-time wind turbine simulator using a custom parallel architecture

NASA Technical Reports Server (NTRS)

Hoffman, John A.; Gluck, R.; Sridhar, S.

1995-01-01

The design of a new parallel-processing digital simulator is described. The new simulator has been developed specifically for analysis of wind energy systems in real time. The new processor has been named: the Wind Energy System Time-domain simulator, version 3 (WEST-3). Like previous WEST versions, WEST-3 performs many computations in parallel. The modules in WEST-3 are pure digital processors, however. These digital processors can be programmed individually and operated in concert to achieve real-time simulation of wind turbine systems. Because of this programmability, WEST-3 is very much more flexible and general than its two predecessors. The design features of WEST-3 are described to show how the system produces high-speed solutions of nonlinear time-domain equations. WEST-3 has two very fast Computational Units (CU's) that use minicomputer technology plus special architectural features that make them many times faster than a microcomputer. These CU's are needed to perform the complex computations associated with the wind turbine rotor system in real time. The parallel architecture of the CU causes several tasks to be done in each cycle, including an IO operation and the combination of a multiply, add, and store. The WEST-3 simulator can be expanded at any time for additional computational power. This is possible because the CU's interfaced to each other and to other portions of the simulation using special serial buses. These buses can be 'patched' together in essentially any configuration (in a manner very similar to the programming methods used in analog computation) to balance the input/ output requirements. CU's can be added in any number to share a given computational load. This flexible bus feature is very different from many other parallel processors which usually have a throughput limit because of rigid bus architecture.

Experiences with integral microelectronics on smart structures for space

NASA Astrophysics Data System (ADS)

Nye, Ted; Casteel, Scott; Navarro, Sergio A.; Kraml, Bob

1995-05-01

One feature of a smart structure implies that some computational and signal processing capability can be performed at a local level, perhaps integral to the controlled structure. This requires electronics with a minimal mechanical influence regarding structural stiffening, heat dissipation, weight, and electrical interface connectivity. The Advanced Controls Technology Experiment II (ACTEX II) space-flight experiments implemented such a local control electronics scheme by utilizing composite smart members with integral processing electronics. These microelectronics, tested to MIL-STD-883B levels, were fabricated with conventional thick film on ceramic multichip module techniques. Kovar housings and aluminum-kapton multilayer insulation was used to protect against harsh space radiation and thermal environments. Development and acceptance testing showed the electronics design was extremely robust, operating in vacuum and at temperature range with minimal gain variations occurring just above room temperatures. Four electronics modules, used for the flight hardware configuration, were connected by a RS-485 2 Mbit per second serial data bus. The data bus was controlled by Actel field programmable gate arrays arranged in a single master, four slave configuration. An Intel 80C196KD microprocessor was chosen as the digital compensator in each controller. It was used to apply a series of selectable biquad filters, implemented via Delta Transforms. Instability in any compensator was expected to appear as large amplitude oscillations in the deployed structure. Thus, over-vibration detection circuitry with automatic output isolation was incorporated into the design. This was not used however, since during experiment integration and test, intentionally induced compensator instabilities resulted in benign mechanical oscillation symptoms. Not too surprisingly, it was determined that instabilities were most detectable by large temperature increases in the electronics, typically noticeable within minutes of unstable operation.

Spacecraft Reed-Solomon downlink module

NASA Technical Reports Server (NTRS)

Luong, Huy H. (Inventor); Donaldson, James A. (Inventor); Wood, Steven H. (Inventor)

1998-01-01

Apparatus and method for providing downlink frames to be transmitted from a spacecraft to a ground station. Each downlink frame includes a synchronization pattern and a transfer frame. The apparatus may comprise a monolithic Reed-Solomon downlink (RSDL) encoding chip coupled to data buffers for storing transfer frames. The RSKL chip includes a timing device, a bus interface, a timing and control unit, a synchronization pattern unit, and a Reed-Solomon encoding unit, and a bus arbiter.

Mechanical Serial-Sectioning Data Assistant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Poulter, Gregory A.; Madison, Jonathan D.

Mechanical Serial-Sectioning Data Assistant (MECH-SSDA) is a real-time data analytics software with graphical user-interface that; 1) tracks and visualizes material removal rates for mechanical serial-sectioning experiments using at least two height measurement methods; 2) tracks process time for specific segments of the serial-sectioning experiment; and 3) alerts the user to anomalies in expected removal rate, process time or unanticipated operational pauses

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

NASA Technical Reports Server (NTRS)

Katzman, Vladimir

2012-01-01

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Power conversion apparatus and method

DOEpatents

Su, Gui-Jia [Knoxville, TN

2012-02-07

A power conversion apparatus includes an interfacing circuit that enables a current source inverter to operate from a voltage energy storage device (voltage source), such as a battery, ultracapacitor or fuel cell. The interfacing circuit, also referred to as a voltage-to-current converter, transforms the voltage source into a current source that feeds a DC current to a current source inverter. The voltage-to-current converter also provides means for controlling and maintaining a constant DC bus current that supplies the current source inverter. The voltage-to-current converter also enables the current source inverter to charge the voltage energy storage device, such as during dynamic braking of a hybrid electric vehicle, without the need of reversing the direction of the DC bus current.

Error protection capability of space shuttle data bus designs

NASA Technical Reports Server (NTRS)

Proch, G. E.

1974-01-01

Error protection assurance in the reliability of digital data communications is discussed. The need for error protection on the space shuttle data bus system has been recognized and specified as a hardware requirement. The error protection techniques of particular concern are those designed into the Shuttle Main Engine Interface (MEI) and the Orbiter Multiplex Interface Adapter (MIA). The techniques and circuit design details proposed for these hardware are analyzed in this report to determine their error protection capability. The capability is calculated in terms of the probability of an undetected word error. Calculated results are reported for a noise environment that ranges from the nominal noise level stated in the hardware specifications to burst levels which may occur in extreme or anomalous conditions.

Bluetooth wireless monitoring, diagnosis and calibration interface for control system of fuel cell bus in Olympic demonstration

NASA Astrophysics Data System (ADS)

Hua, Jianfeng; Lin, Xinfan; Xu, Liangfei; Li, Jianqiu; Ouyang, Minggao

With the worldwide deterioration of the natural environment and the fossil fuel crisis, the possible commercialization of fuel cell vehicles has become a hot topic. In July 2008, Beijing started a clean public transportation plan for the 29th Olympic games. Three fuel cell city buses and 497 other low-emission vehicles are now serving the Olympic core area and Beijing urban areas. The fuel cell buses will operate along a fixed bus line for 1 year as a public demonstration of green energy vehicles. Due to the specialized nature of fuel cell engines and electrified power-train systems, measurement, monitoring and calibration devices are indispensable. Based on the latest Bluetooth wireless technology, a novel Bluetooth universal data interface was developed for the control system of the fuel cell city bus. On this platform, a series of wireless portable control auxiliary systems have been implemented, including wireless calibration, a monitoring system and an in-system programming platform, all of which are ensuring normal operation of the fuel cell buses used in the demonstration.

Spacelab interface development test, volume 1, sections 1-6

NASA Technical Reports Server (NTRS)

Harris, L. H.

1979-01-01

Data recorded during the following tests is presented: pulse coded modulator master unit to Spacelab (S/L) interface, master timing unit to S/L interface, multiplexer-demultiplexer/serial input-output to S/L interface, and special tests.

Exploiting a GSM Network for Precise Payload Delivery

DTIC Science & Technology

2009-05-07

N is shown in Fig.6. As shown in this figure the Snowflake payload now includes a standard Blackberry 8310 cell phone , which communicates with the...weather station, measuring winds and barometric pressure, serial to Bluetooth interface, and Blackberry 8310 cell phone . The portable Kestrel 4000...interfacing the serial stream with a standard Blackberry 8310 cell phone carrying a AT&T SIM card. 6 American Institute of Aeronautics and

[A novel serial port auto trigger system for MOSFET dose acquisition].

PubMed

Luo, Guangwen; Qi, Zhenyu

2013-01-01

To synchronize the radiation of microSelectron-HDR (Nucletron afterloading machine) and measurement of MOSFET dose system, a trigger system based on interface circuit was designed and corresponding monitor and trigger program were developed on Qt platform. This interface and control system was tested and showed stable operate and reliable work. This adopted serial port detect technique may expand to trigger application of other medical devices.

TACS Central Control Facility.

DTIC Science & Technology

1981-02-12

PULSE RTC REAL TIME CLOCK -{> I . SIGNAL INVERSION UASC UNIVERSAL ASYNCHRONOUS SERIAL - ---- 4w SPECIAL INTERFACE CONTROLLER Fiq. 2-1. MAC hardware...34 Universal Asynchronous Serial Controller" (UASC) cards. The cards implement an RS-232 standard interface. All controllers are set to operate at a data...Bridwell and I. Richer, "A Preliminary Design of a TDMA System for FLEETSAT," Technical Note 1975-5, Lincoln Laboratory, M.I.T. (12 March 1975), DDC

International Space Station Bus Regulation With NASA Glenn Research Center Flywheel Energy Storage System Development Unit

NASA Technical Reports Server (NTRS)

Kascak, Peter E.; Kenny, Barbara H.; Dever, Timothy P.; Santiago, Walter; Jansen, Ralph H.

2001-01-01

An experimental flywheel energy storage system is described. This system is being used to develop a flywheel based replacement for the batteries on the International Space Station (ISS). Motor control algorithms which allow the flywheel to interface with a simplified model of the ISS power bus, and function similarly to the existing ISS battery system, are described. Results of controller experimental verification on a 300 W-hr flywheel are presented.

Adaptive Optics System with Deformable Composite Mirror and High Speed, Ultra-Compact Electronics

NASA Astrophysics Data System (ADS)

Chen, Peter C.; Knowles, G. J.; Shea, B. G.

2006-06-01

We report development of a novel adaptive optics system for optical astronomy. Key components are very thin Deformable Mirrors (DM) made of fiber reinforced polymer resins, subminiature PMN-PT actuators, and low power, high bandwidth electronics drive system with compact packaging and minimal wiring. By using specific formulations of fibers, resins, and laminate construction, we are able to fabricate mirror face sheets that are thin (< 2mm), have smooth surfaces and excellent optical shape. The mirrors are not astigmatic and do not develop surface irregularities when cooled. The actuators are small footprint multilayer PMN-PT ceramic devices with large stroke (2- 20 microns), high linearity, low hysteresis, low power, and flat frequency response to >2 KHz. By utilizing QorTek’s proprietary synthetic impendence power supply technology, all the power, control, and signal extraction for many hundreds to 1000s of actuators and sensors can be implemented on a single matrix controller printed circuit board co-mounted with the DM. The matrix controller, in turn requires only a single serial bus interface, thereby obviating the need for massive wiring harnesses. The technology can be scaled up to multi-meter aperture DMs with >100K actuators.

Development of the Second Generation Berry Impact Recording Device (BIRD II)

PubMed Central

Xu, Rui; Li, Changying

2015-01-01

To quantitatively measure the impacts during blueberry harvesting and post-harvest handling, this study designed the second generation Berry Impact Recording Device (BIRD II) sensor with a size of 21 mm in diameter and a weight of 3.9 g, which reduced the size by 17% and the weight by 50% compared to the previous prototype. The sensor was able to measure accelerations up to 346 g at a maximum frequency of 2 KHz. Universal Serial Bus (USB) was used to directly connect the sensor with the computer, removing the interface box used previously. LabVIEW-based PC software was designed to configure the sensor, download and process the data. The sensor was calibrated using a centrifuge. The accuracy of the sensor was between −1.76 g to 2.17 g, and the precision was between 0.21 g to 0.81 g. Dynamic drop tests showed that BIRD II had smaller variance in measurements than BIRD I. In terms of size and weight, BIRD II is more similar to an average blueberry fruit than BIRD I, which leads to more accurate measurements of the impacts for blueberries. PMID:25664430

Line-scan system for continuous hand authentication

NASA Astrophysics Data System (ADS)

Liu, Xiaofeng; Kong, Lingsheng; Diao, Zhihui; Jia, Ping

2017-03-01

An increasing number of heavy machinery and vehicles have come into service, giving rise to a significant concern over protecting these high-security systems from misuse. Conventionally, authentication performed merely at the initial login may not be sufficient for detecting intruders throughout the operating session. To address this critical security flaw, a line-scan continuous hand authentication system with the appearance of an operating rod is proposed. Given that the operating rod is occupied throughout the operating period, it can be a possible solution for unobtrusively recording the personal characteristics for continuous monitoring. The ergonomics in the physiological and psychological aspects are fully considered. Under the shape constraints, a highly integrated line-scan sensor, a controller unit, and a gear motor with encoder are utilized. This system is suitable for both the desktop and embedded platforms with a universal serial bus interface. The volume of the proposed system is smaller than 15% of current multispectral area-based camera systems. Based on experiments on a database with 4000 images from 200 volunteers, a competitive equal error rate of 0.1179% is achieved, which is far more accurate than the state-of-the-art continuous authentication systems using other modalities.

Implementing Ethernet Services on the Payload Executive Processor (PEP)

NASA Technical Reports Server (NTRS)

Pruett, David; Guyette, Greg

2016-01-01

The Ethernet interface is more common and easier interface to implement for payload developers already familiar with Ethernet protocol in their labs. The Ethernet interface allows for a more distributed payload architecture. Connections can be placed in locations not serviced by the PEP 1553 bus. The Ethernet interface provides a new access port into the PEP so as to use the already existing services. Initial capability will include a subset of services with a plan to expand services later.

Fiber optical sensing on-board communication satellites

NASA Astrophysics Data System (ADS)

Hurni, A.; Lemke, N. M. K.; Roner, M.; Obermaier, J.; Putzer, P.; Kuhenuri Chami, N.

2017-11-01

Striving constantly to reduce mass, AIT effort and overall cost of the classical point-to-point wired temperature sensor harness on-board telecommunication satellites, OHB System (formerly Kayser-Threde) has introduced the Hybrid Sensor Bus (HSB) system. As a future spacecraft platform element, HSB relies on electrical remote sensor units as well as fiber-optical sensors, both of which can serially be connected in a bus architecture. HSB is a modular measurement system with many applications, also thanks to the opportunities posed by the digital I²C bus. The emphasis, however, is on the introduction of fiber optics and especially fiber-Bragg grating (FBG) temperature sensors as disruptive innovation for the company's satellite platforms. The light weight FBG sensors are directly inscribed in mechanically robust and radiation tolerant fibers, reducing the need for optical fiber connectors and splices to a minimum. Wherever an FBG sensor shall be used, the fiber is glued together with a corresponding temperature transducer to the satellites structure or to a subsystem. The transducer is necessary to provide decoupling of mechanical stress, but simultaneously ensure a high thermal conductivity. HSB has been developed in the frame of an ESA-ARTES program with European and German co-funding and will be verified as flight demonstrator on-board the German Heinrich Hertz satellite (H2Sat). In this paper the Engineering Model development of HSB is presented and a Fiber-optical Sensor Multiplexer for a more flexible sensor bus architecture is introduced. The HSB system aims at telecommunication satellite platforms with an operational life time beyond 15 years in geostationary orbit. It claims a high compatibility in terms of performance and interfaces with existing platforms while it was designed with future applications with increased radiation exposure already in mind. In its basic configuration HSB consists of four modules which are the Power Supply Unit, the HSB Controller Module, the Interrogator Controller Module and the Analog Front-End for the fiber-optical interrogation. The Interrogator Controller Module handles both, the electrical and fiber-optical sensor network. For the latter it is to be completed by the Analog Front-End. On this front-end, a tunable laser diode is implemented for the scanning of the FBG sensors. The reflected spectra are measured on multiple fiber channels and are then evaluated by use of a peak detection algorithm in order to obtain a precise temperature measurement. The precise operation of the photonic system on long terms can be guaranteed thanks to an inorbit calibration concept.

Increasing the Automation and Autonomy for Spacecraft Operations with Criteria Action Table

NASA Technical Reports Server (NTRS)

Li, Zhen-Ping; Savki, Cetin

2005-01-01

The Criteria Action Table (CAT) is an automation tool developed for monitoring real time system messages for specific events and processes in order to take user defined actions based on a set of user-defined rules. CAT was developed by Lockheed Martin Space Operations as a part of a larger NASA effort at the Goddard Space Flight Center (GSFC) to create a component-based, middleware-based, and standard-based general purpose ground system architecture referred as GMSEC - the GSFC Mission Services Evolution Center. CAT has been integrated into the upgraded ground systems for Tropical Rainfall Measuring Mission (TRMM) and Small Explorer (SMEX) satellites and it plays the central role in their automation effort to reduce the cost and increase the reliability for spacecraft operations. The GMSEC architecture provides a standard communication interface and protocol for components to publish/describe messages to an information bus. It also provides a standard message definition so components can send and receive messages to the bus interface rather than each other, thus reducing the component-to-component coupling, interface, protocols, and link (socket) management. With the GMSEC architecture, components can publish standard event messages to the bus for all nominal, significant, and surprising events in regard to satellite, celestial, ground system, or any other activity. In addition to sending standard event messages, each GMSEC compliant component is required to accept and process GMSEC directive request messages.

Analyzing GAIAN Database (GaianDB) on a Tactical Network

DTIC Science & Technology

2015-11-30

we connected 3 Raspberry Pi’s running GaianDB and our augmented version of splatform to a network of 3 CSRs. The Raspberry Pi is a low power, low...based on Debian from a connected secure digital high capacity (SDHC) card or a universal serial bus (USB) device. The Raspberry Pi comes equipped with...requirements, capabilities, and cost make the Raspberry Pi a useful device for sensor experimentation. From there, we performed 3 types of benchmarks

A synchronous serial bus for multidimensional array acoustic logging tool

NASA Astrophysics Data System (ADS)

Men, Baiyong; Ju, Xiaodong; Lu, Junqiang; Qiao, Wenxiao

2016-12-01

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master-slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

Investigation of Techniques for Simulating Communications and Tracking Subsystems on Space Station Freedom

NASA Technical Reports Server (NTRS)

Deacetis, Louis A.

1991-01-01

The need to reduce the costs of Space Station Freedom has resulted in a major redesign and downsizing of the Station in general, and its Communications and Tracking (C&T) components in particular. Earlier models and simulations of the C&T Space-to-Ground Subsystem (SGS) in particular are no longer valid. There thus exists a general need for updated, high fidelity simulations of C&T subsystems. This project explored simulation techniques and methods that might be used in developing new simulations of C&T subsystems, including the SGS. Three requirements were placed on the simulations to be developed: (1) they run on IBM PC/XT/AT compatible computers; (2) they be written in Ada as much as possible; and (3) since control and monitoring of the C&T subsystems will involve communication via a MIL-STD-1553B serial bus, that the possibility of commanding the simulator and monitoring its sensors via that bus be included in the design of the simulator. The result of the project is a prototype of a simulation of the Assembly/Contingency Transponder of the SGS, written in Ada, which can be controlled from another PC via a MIL-STD-1553B bus.

Design and development of an automatic data acquisition system for a balance study using a smartcard system.

PubMed

Ambrozy, C; Kolar, N A; Rattay, F

2010-01-01

For measurement value logging of board angle values during balance training, it is necessary to develop a measurement system. This study will provide data for a balance study using the smartcard. The data acquisition comes automatically. An individually training plan for each proband is necessary. To store the proband identification a smartcard with an I2C data bus protocol and an E2PROM memory system is used. For reading the smartcard data a smartcard reader is connected via universal serial bus (USB) to a notebook. The data acquisition and smartcard read programme is designed with Microsoft® Visual C#. A training plan file contains the individual training plan for each proband. The data of the test persons are saved in a proband directory. Each event is automatically saved as a log-file for the exact documentation. This system makes study development easy and time-saving.

Systems evaluation of thermal bus concepts

NASA Technical Reports Server (NTRS)

Stalmach, D. D.

1982-01-01

Thermal bus concepts, to provide a centralized thermal utility for large, multihundred kilowatt space platforms, were studied and the results are summarized. Concepts were generated, defined, and screened for inclusion in system level thermal bus trades. Parametric trade studies were conducted in order to define the operational envelope, performance, and physical characteristics of each. Two concepts were selected as offering the most promise for thermal bus development. All of four concepts involved two phase flow in order to meet the required isothermal nature of the thermal bus. Two of the concepts employ a mechanical means to circulate the working fluid, a liquid pump in one case and a vapor compressor in another. Another concept utilizes direct osmosis as the driving force of the thermal bus. The fourth concept was a high capacity monogroove heat pipe. After preliminary sizing and screening, three of these concepts were selected to carry into the trade studies. The monogroove heat pipe concept was deemed unsuitable for further consideration because of its heat transport limitations. One additional concept utilizing capillary forces to drive the working fluid was added. Parametric system level trade studies were performed. Sizing and weight calculations were performed for thermal bus sizes ranging from 5 to 350 kW and operating temperatures in the range of 4 to 120 C. System level considerations such as heat rejection and electrical power penalties and interface temperature losses were included in the weight calculations.

The use of virtual ground to control transmembrane voltages and measure bilayer currents in serial arrays of droplet interface bilayers

NASA Astrophysics Data System (ADS)

Sarles, Stephen A.

2013-09-01

The droplet interface bilayer (DIB) is a simple technique for constructing a stable lipid bilayer at the interface of two lipid-encased water droplets submerged in oil. Networks of DIBs formed by connecting more than two droplets constitute a new form of modular biomolecular smart material, where the transduction properties of a single lipid bilayer can affect the actions performed at other interface bilayers in the network via diffusion through the aqueous environments of shared droplet connections. The passive electrical properties of a lipid bilayer and the arrangement of droplets that determine the paths for transport in the network require specific electrical control to stimulate and interrogate each bilayer. Here, we explore the use of virtual ground for electrodes inserted into specific droplets in the network and employ a multichannel patch clamp amplifier to characterize bilayer formation and ion-channel activity in a serial DIB array. Analysis of serial connections of DIBs is discussed to understand how assigning electrode connections to the measurement device can be used to measure activity across all lipid membranes within a network. Serial arrays of DIBs are assembled using the regulated attachment method within a multi-compartment flexible substrate, and wire-type electrodes inserted into each droplet compartment of the substrate enable the application of voltage and measurement of current in each droplet in the array.

Insider Threat Control: Using Universal Serial Bus (USB) Device Auditing to Detect Possible Data Exfiltration by Malicious Insiders

DTIC Science & Technology

2013-01-01

under Contract No. FA8721-05- C -0003 with Carnegie Mellon University for the operation of the Software Engineering Institute, a federally funded...logging capabilities or further modify the control to best suit its needs. 1.1 Audience and Structure of This Report This report is a hands -on guide...the follow- ing directory: C :\\Admin_Tools\\USB_Audit\\ When selecting a deployment path, avoid using spaces in directory names since this will cause

TMS communications hardware. Volume 1: Computer interfaces

NASA Technical Reports Server (NTRS)

Brown, J. S.; Weinrich, S. S.

1979-01-01

A prototpye coaxial cable bus communications system was designed to be used in the Trend Monitoring System (TMS) to connect intelligent graphics terminals (based around a Data General NOVA/3 computer) to a MODCOMP IV host minicomputer. The direct memory access (DMA) interfaces which were utilized for each of these computers are identified. It is shown that for the MODCOMP, an off-the-shell board was suitable, while for the NOVAs, custon interface circuitry was designed and implemented.

COTS-Based Fault Tolerance in Deep Space: Qualitative and Quantitative Analyses of a Bus Network Architecture

NASA Technical Reports Server (NTRS)

Tai, Ann T.; Chau, Savio N.; Alkalai, Leon

2000-01-01

Using COTS products, standards and intellectual properties (IPs) for all the system and component interfaces is a crucial step toward significant reduction of both system cost and development cost as the COTS interfaces enable other COTS products and IPs to be readily accommodated by the target system architecture. With respect to the long-term survivable systems for deep-space missions, the major challenge for us is, under stringent power and mass constraints, to achieve ultra-high reliability of the system comprising COTS products and standards that are not developed for mission-critical applications. The spirit of our solution is to exploit the pertinent standard features of a COTS product to circumvent its shortcomings, though these standard features may not be originally designed for highly reliable systems. In this paper, we discuss our experiences and findings on the design of an IEEE 1394 compliant fault-tolerant COTS-based bus architecture. We first derive and qualitatively analyze a -'stacktree topology" that not only complies with IEEE 1394 but also enables the implementation of a fault-tolerant bus architecture without node redundancy. We then present a quantitative evaluation that demonstrates significant reliability improvement from the COTS-based fault tolerance.

Time-recovering PCI-AER interface for bio-inspired spiking systems

NASA Astrophysics Data System (ADS)

Paz-Vicente, R.; Linares-Barranco, A.; Cascado, D.; Vicente, S.; Jimenez, G.; Civit, A.

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) inject a sequence of events at some point of the AER structure. This is necessary for testing and debugging complex AER systems. This paper presents a PCI to AER interface, that dispatches a sequence of events received from the PCI bus with embedded timing information to establish when each event will be delivered. A set of specialized states machines has been introduced to recovery the possible time delays introduced by the asynchronous AER bus. On the input channel, the interface capture events assigning a timestamp and delivers them through the PCI bus to MATLAB applications. It has been implemented in real time hardware using VHDL and it has been tested in a PCI-AER board, developed by authors, that includes a Spartan II 200 FPGA. The demonstration hardware is currently capable to send and receive events at a peak rate of 8,3 Mev/sec, and a typical rate of 1 Mev/sec.

Note: Design of a full photon-timing recorder down to 1-ns resolution for fluorescence fluctuation measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nishimura, Goro, E-mail: gnishi@imd.es.hokudai.ac.jp

2015-10-15

A photon timing recorder was realized in a field programmable gate array to capture all timing data of photons on multiple channels with down to a 1-ns resolution and to transfer all data to a host computer in real-time through universal serial bus with more than 10 M events/s transfer rate. The main concept is that photon time series can be regarded as a serial communication data stream. This recorder was successfully applied for simultaneous measurements of fluorescence fluctuation and lifetime of near-infrared dyes in solution. This design is not only limited to the fluorescence fluctuation measurement but also applicablemore » to any kind of photon counting experiments in a nanosecond time range because of the simple and easily modifiable design.« less

Use of small stand-alone Internet nodes as a distributed control system

NASA Astrophysics Data System (ADS)

Goodwin, Robert W.; Kucera, Michael J.; Shea, Michael F.

1994-12-01

For several years, the standard model for accelerator control systems has been workstation consoles connected to VME local stations by a Local Area Network with analog and digital data being accessed via a field bus to custom I/O interface electronics. Commercially available hardware has now made it possible to implement a small stand-alone data acquisition station that combines the LAN connection, the computer, and the analog and digital I/O interface on a single board. This eliminates the complexity of a field bus and the associated proprietary I/O hardware. A minimum control system is one data acquisition station and a Macintosh or workstation console, both connected to the network; larger systems have more consoles and nodes. An implementation of this architecture is described along with performance and operational experience.

The high speed interconnect system architecture and operation

NASA Astrophysics Data System (ADS)

Anderson, Steven C.

The design and operation of a fiber-optic high-speed interconnect system (HSIS) being developed to meet the requirements of future avionics and flight-control hardware with distributed-system architectures are discussed. The HSIS is intended for 100-Mb/s operation of a local-area network with up to 256 stations. It comprises a bus transmission system (passive star couplers and linear media linked by active elements) and network interface units (NIUs). Each NIU is designed to perform the physical, data link, network, and transport functions defined by the ISO OSI Basic Reference Model (1982 and 1983) and incorporates a fiber-optic transceiver, a high-speed protocol based on the SAE AE-9B linear token-passing data bus (1986), and a specialized application interface unit. The operating modes and capabilities of HSIS are described in detail and illustrated with diagrams.

Application of new electro-optic technology to Space Station Freedom data management system

NASA Technical Reports Server (NTRS)

Husbands, C. R.; Girard, M. M.

1993-01-01

A low risk design methodology to permit the local bus structures to support increased data carrying capacities and to speed messages and data flow between nodes or stations on the Space Station Freedom Data Management System in anticipation of growing requirements was evaluated and recommended. The recommended design employs a collateral fiber optic technique that follows a NATO avionic standard that is developed, tested, and available. Application of this process will permit a potential 25 fold increase in data transfer performance on the local wire bus network with a fiber optic network, maintaining the functionality of the low-speed bus and supporting all of the redundant transmission and fault detection capabilities designed into the existing system. The application of wavelength division multiplexing (WDM) technology to both the local data bus and global data bus segments of the Data Management System to support anticipated additional highspeed data transmission requirements was also examined. Techniques were examined to provide a dual wavelength implementation of the fiber optic collateral networks. This dual wavelength implementation would permit each local bus to support two simultaneous high-speed transfers on the same fiber optic bus structure and operate within the limits of the existing protocol standard. A second WDM study examined the use of spectral sliced technology to provide a fourfold increase in the Fiber Distributed Data Interface (FDDI) global bus networks without requiring modifications to the existing installed cable plant. Computer simulations presented indicated that this data rate improvement can be achieved with commercially available optical components.

The AI Bus architecture for distributed knowledge-based systems

NASA Technical Reports Server (NTRS)

Schultz, Roger D.; Stobie, Iain

1991-01-01

The AI Bus architecture is layered, distributed object oriented framework developed to support the requirements of advanced technology programs for an order of magnitude improvement in software costs. The consequent need for highly autonomous computer systems, adaptable to new technology advances over a long lifespan, led to the design of an open architecture and toolbox for building large scale, robust, production quality systems. The AI Bus accommodates a mix of knowledge based and conventional components, running on heterogeneous, distributed real world and testbed environment. The concepts and design is described of the AI Bus architecture and its current implementation status as a Unix C++ library or reusable objects. Each high level semiautonomous agent process consists of a number of knowledge sources together with interagent communication mechanisms based on shared blackboards and message passing acquaintances. Standard interfaces and protocols are followed for combining and validating subsystems. Dynamic probes or demons provide an event driven means for providing active objects with shared access to resources, and each other, while not violating their security.

A Digital Motion Control System for Large Telescopes

NASA Astrophysics Data System (ADS)

Hunter, T. R.; Wilson, R. W.; Kimberk, R.; Leiker, P. S.

2001-05-01

We have designed and programmed a digital motion control system for large telescopes, in particular, the 6-meter antennas of the Submillimeter Array on Mauna Kea. The system consists of a single robust, high-reliability microcontroller board which implements a two-axis velocity servo while monitoring and responding to critical safety parameters. Excellent tracking performance has been achieved with this system (0.3 arcsecond RMS at sidereal rate). The 24x24 centimeter four-layer printed circuit board contains a multitude of hardware devices: 40 digital inputs (for limit switches and fault indicators), 32 digital outputs (to enable/disable motor amplifiers and brakes), a quad 22-bit ADC (to read the motor tachometers), four 16-bit DACs (that provide torque signals to the motor amplifiers), a 32-LED status panel, a serial port to the LynxOS PowerPC antenna computer (RS422/460kbps), a serial port to the Palm Vx handpaddle (RS232/115kbps), and serial links to the low-resolution absolute encoders on the azimuth and elevation axes. Each section of the board employs independent ground planes and power supplies, with optical isolation on all I/O channels. The processor is an Intel 80C196KC 16-bit microcontroller running at 20MHz on an 8-bit bus. This processor executes an interrupt-driven, scheduler-based software system written in C and assembled into an EPROM with user-accessible variables stored in NVSRAM. Under normal operation, velocity update requests arrive at 100Hz from the position-loop servo process running independently on the antenna computer. A variety of telescope safety checks are performed at 279Hz including routine servicing of a 6 millisecond watchdog timer. Additional ADCs onboard the microcontroller monitor the winding temperature and current in the brushless three-phase drive motors. The PID servo gains can be dynamically changed in software. Calibration factors and software filters can be applied to the tachometer readings prior to the application of the servo gains in the torque computations. The Palm pilot handpaddle displays the complete status of the telescope and allows full local control of the drives in an intuitive, touchscreen user interface which is especially useful during reconfigurations of the antenna array.

Can in Space-Status and Future after ECSS-E-ST-50-15C Release

NASA Astrophysics Data System (ADS)

Taylor, Chris; Furano, Gianluca; Valverde-Carretero, Alberto; Marinis, Kostas; Magistrati, Giorgio; Bolognino, Luca; Richard Jansen, King Lam; Caramia, Maurizio; Grau Llovera, Angel; Dalenq, Jean; Vinet, Francois

2015-09-01

Nowadays Controller Area Network (CAN) Bus is used more and more in spacecraft onboard applications. It has already been successfully used in many missions (ATV, SMART-1, MATROSHKA, SSTL Satellites, SENTINEL-2 etc.), will soon be the the main onboard communications bus for the EXOMars Mission and in will enable extended capabilities on future European Telecom palatforms. CAN Bus provides numerous advantages (robust, low cost, low power consumption, European, etc.). Thanks to its wide acceptance in the commercial market, numerous development tools are available that support and reduce the cost of all the engineering process, from specifications and design to the final assembly, integration and tests. Since 2009, ESA-ESTEC established an ESA-Industry Working Group on CAN Bus, in order to identify the main issues for its use in space applications and drive research and development. This long process has finally provided as output an ECSS standard and a set of building blocks that fully enable deployment of CAN bus for platform and payload use in all classes of space missions. The EXOMars project team has spearheaded these efforts, taking as reference the draft guidelines, and has taken into account the particularities of the EXOMars mission requirements, in order to provide a consistent methodology for the development of the multiple units that need to interface with the CAN Bus. The selection of CANOpen as preferred higher layer protocol for CAN in space application is due to the experience and hindsight developed during this long and sometimes not linear process. Two notable efforts were the development of an hardware support layer (the CCIPC IP core) for the CANOpen protocol and the qualification of three rad hard transceivers compliant with CAN commercial ISO physical standard. The CCIPC development has been performed concurrently with the ECSS-E-50-15C standardization activities. This approach has allowed the constant monitoring of the adopted IP core design solution by the ECSS Working Group. The first flight of the CCIPC is foreseen in 2016 with the EXOMARS Entry Descent and Landing Demonstrator Module. This paper will focus on the implementation of CAN Bus for all the future sapce DHSs, both on the technical aspects of physical layer selection, particularities of the higher layer protocol, etc. and on the methodology aspects related to the procurement of multiple heterogeneous units that are required to provide a standard interface to the Bus. Finally, a critical review of the current CAN Bus draft ECSS standard will be presented, based on advantages and difficulties encountered in the application of the current draft standard in the ongoing space applications.

Memory-based frame synchronizer. [for digital communication systems

NASA Technical Reports Server (NTRS)

Stattel, R. J.; Niswander, J. K. (Inventor)

1981-01-01

A frame synchronizer for use in digital communications systems wherein data formats can be easily and dynamically changed is described. The use of memory array elements provide increased flexibility in format selection and sync word selection in addition to real time reconfiguration ability. The frame synchronizer comprises a serial-to-parallel converter which converts a serial input data stream to a constantly changing parallel data output. This parallel data output is supplied to programmable sync word recognizers each consisting of a multiplexer and a random access memory (RAM). The multiplexer is connected to both the parallel data output and an address bus which may be connected to a microprocessor or computer for purposes of programming the sync word recognizer. The RAM is used as an associative memory or decorder and is programmed to identify a specific sync word. Additional programmable RAMs are used as counter decoders to define word bit length, frame word length, and paragraph frame length.

Modular Integrated Stackable Layers (MISL) 1.1 Design Specification. Design Guideline Document

NASA Technical Reports Server (NTRS)

Yim, Hester J.

2012-01-01

This document establishes the design guideline of the Modular Instrumentation Data Acquisition (MI-DAQ) system in utilization of several designs available in EV. The MI- DAQ provides the options to the customers depending on their system requirements i.e. a 28V interface power supply, a low power battery operated system, a low power microcontroller, a higher performance microcontroller, a USB interface, a Ethernet interface, a wireless communication, various sensor interfaces, etc. Depending on customer's requirements, the each functional board can be stacked up from a bottom level of power supply to a higher level of stack to provide user interfaces. The stack up of boards are accomplished by a predefined and standardized power bus and data bus connections which are included in this document along with other physical and electrical guidelines. This guideline also provides information for a new design options. This specification is the product of a collaboration between NASA/JSC/EV and Texas A&M University. The goal of the collaboration is to open source the specification and allow outside entities to design, build, and market modules that are compatible with the specification. NASA has designed and is using numerous modules that are compatible to this specification. A limited number of these modules will also be released as open source designs to support the collaboration. The released designs are listed in the Applicable Documents.

An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection.

PubMed

Perelman, Yevgeny; Ginosar, Ran

2007-01-01

A mixed-signal front-end processor for multichannel neuronal recording is described. It receives 12 differential-input channels of implanted recording electrodes. A programmable cutoff High Pass Filter (HPF) blocks dc and low-frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency Local Field Potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF, in a range of 8-13 kHz. Amplifier offsets are compensated by 5-bit calibration digital-to-analog converters (DACs). The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into 10-bit digital form, and streamed out over a serial digital bus at up to 8 Mbps. A threshold filter suppresses inactive portions of the signal and emits only spike segments of programmable length. A prototype has been fabricated on a 0.35-microm CMOS process and tested successfully, demonstrating a 3-microV noise level. Special interface system incorporating an embedded CPU core in a programmable logic device accompanied by real-time software has been developed to allow connectivity to a computer host.

Spacewire on Earth orbiting scatterometers

NASA Technical Reports Server (NTRS)

Bachmann, Alex; Lang, Minh; Lux, James; Steffke, Richard

2002-01-01

The need for a high speed, reliable and easy to implement communication link has led to the development of a space flight oriented version of IEEE 1355 called SpaceWire. SpaceWire is based on high-speed (200 Mbps) serial point-to-point links using Low Voltage Differential Signaling (LVDS). SpaceWIre has provisions for routing messages between a large network of processors, using wormhole routing for low overhead and latency. {additionally, there are available space qualified hybrids, which provide the Link layer to the user's bus}. A test bed of multiple digital signal processor breadboards, demonstrating the ability to meet signal processing requirements for an orbiting scatterometer has been implemented using three Astrium MCM-DSPs, each breadboard consists of a Multi Chip Module (MCM) that combines a space qualified Digital Signal Processor and peripherals, including IEEE-1355 links. With the addition of appropriate physical layer interfaces and software on the DSP, the SpaceWire link is used to communicate between processors on the test bed, e.g. sending timing references, commands, status, and science data among the processors. Results are presented on development issues surrounding the use of SpaceWire in this environment, from physical layer implementation (cables, connectors, LVDS drivers) to diagnostic tools, driver firmware, and development methodology. The tools, methods, and hardware, software challenges and preliminary performance are investigated and discussed.

A PC-based bus monitor program for use with the transport systems research vehicle RS-232 communication interfaces

NASA Technical Reports Server (NTRS)

Easley, Wesley C.

1991-01-01

Experiment critical use of RS-232 data busses in the Transport Systems Research Vehicle (TSRV) operated by the Advanced Transport Operating Systems Program Office at the NASA Langley Research Center has recently increased. Each application utilizes a number of nonidentical computer and peripheral configurations and requires task specific software development. To aid these development tasks, an IBM PC-based RS-232 bus monitoring system was produced. It can simultaneously monitor two communication ports of a PC or clone, including the nonstandard bus expansion of the TSRV Grid laptop computers. Display occurs in a separate window for each port's input with binary display being selectable. A number of other features including binary log files, screen capture to files, and a full range of communication parameters are provided.

Fast assembling of neuron fragments in serial 3D sections.

PubMed

Chen, Hanbo; Iascone, Daniel Maxim; da Costa, Nuno Maçarico; Lein, Ed S; Liu, Tianming; Peng, Hanchuan

2017-09-01

Reconstructing neurons from 3D image-stacks of serial sections of thick brain tissue is very time-consuming and often becomes a bottleneck in high-throughput brain mapping projects. We developed NeuronStitcher, a software suite for stitching non-overlapping neuron fragments reconstructed in serial 3D image sections. With its efficient algorithm and user-friendly interface, NeuronStitcher has been used successfully to reconstruct very large and complex human and mouse neurons.

Universal Serial Bus Architecture for Removable Media (USB-ARM)

DOE Office of Scientific and Technical Information (OSTI.GOV)

2011-03-09

USB-ARM creates operating system drivers which sit between removable media and the user and applications. The drivers isolate the media and submit the contents of the media to a virtual machine containing an entire scanning system. This scanning system may include traditional anti-virus, but also allows more detailed analysis of files, including dynamic run-time analysis, helping to prevent "zero-day" threats not already identified in anti-virus signatures. Once cleared, the media is presented to the operating system, at which point it becomes available to users and applications.

CIB: an improved communication architecture for real-time monitoring of aerospace materials, instruments, and sensors on the ISS.

PubMed

Krasowski, Michael J; Prokop, Norman F; Flatico, Joseph M; Greer, Lawrence C; Jenkins, Phillip P; Neudeck, Philip G; Chen, Liangyu; Spina, Danny C

2013-01-01

The Communications Interface Board (CIB) is an improved communications architecture that was demonstrated on the International Space Station (ISS). ISS communication interfaces allowing for real-time telemetry and health monitoring require a significant amount of development. The CIB simplifies the communications interface to the ISS for real-time health monitoring, telemetry, and control of resident sensors or experiments. With a simpler interface available to the telemetry bus, more sensors or experiments may be flown. The CIB accomplishes this by acting as a bridge between the ISS MIL-STD-1553 low-rate telemetry (LRT) bus and the sensors allowing for two-way command and telemetry data transfer. The CIB was designed to be highly reliable and radiation hard for an extended flight in low Earth orbit (LEO) and has been proven with over 40 months of flight operation on the outside of ISS supporting two sets of flight experiments. Since the CIB is currently operating in flight on the ISS, recent results of operations will be provided. Additionally, as a vehicle health monitoring enabling technology, an overview and results from two experiments enabled by the CIB will be provided. Future applications for vehicle health monitoring utilizing the CIB architecture will also be discussed.

CIB: An Improved Communication Architecture for Real-Time Monitoring of Aerospace Materials, Instruments, and Sensors on the ISS

PubMed Central

Krasowski, Michael J.; Prokop, Norman F.; Flatico, Joseph M.; Greer, Lawrence C.; Jenkins, Phillip P.; Neudeck, Philip G.; Chen, Liangyu; Spina, Danny C.

2013-01-01

The Communications Interface Board (CIB) is an improved communications architecture that was demonstrated on the International Space Station (ISS). ISS communication interfaces allowing for real-time telemetry and health monitoring require a significant amount of development. The CIB simplifies the communications interface to the ISS for real-time health monitoring, telemetry, and control of resident sensors or experiments. With a simpler interface available to the telemetry bus, more sensors or experiments may be flown. The CIB accomplishes this by acting as a bridge between the ISS MIL-STD-1553 low-rate telemetry (LRT) bus and the sensors allowing for two-way command and telemetry data transfer. The CIB was designed to be highly reliable and radiation hard for an extended flight in low Earth orbit (LEO) and has been proven with over 40 months of flight operation on the outside of ISS supporting two sets of flight experiments. Since the CIB is currently operating in flight on the ISS, recent results of operations will be provided. Additionally, as a vehicle health monitoring enabling technology, an overview and results from two experiments enabled by the CIB will be provided. Future applications for vehicle health monitoring utilizing the CIB architecture will also be discussed. PMID:23983621

LANES - LOCAL AREA NETWORK EXTENSIBLE SIMULATOR

NASA Technical Reports Server (NTRS)

Gibson, J.

1994-01-01

The Local Area Network Extensible Simulator (LANES) provides a method for simulating the performance of high speed local area network (LAN) technology. LANES was developed as a design and analysis tool for networking on board the Space Station. The load, network, link and physical layers of a layered network architecture are all modeled. LANES models to different lower-layer protocols, the Fiber Distributed Data Interface (FDDI) and the Star*Bus. The load and network layers are included in the model as a means of introducing upper-layer processing delays associated with message transmission; they do not model any particular protocols. FDDI is an American National Standard and an International Organization for Standardization (ISO) draft standard for a 100 megabit-per-second fiber-optic token ring. Specifications for the LANES model of FDDI are taken from the Draft Proposed American National Standard FDDI Token Ring Media Access Control (MAC), document number X3T9.5/83-16 Rev. 10, February 28, 1986. This is a mature document describing the FDDI media-access-control protocol. Star*Bus, also known as the Fiber Optic Demonstration System, is a protocol for a 100 megabit-per-second fiber-optic star-topology LAN. This protocol, along with a hardware prototype, was developed by Sperry Corporation under contract to NASA Goddard Space Flight Center as a candidate LAN protocol for the Space Station. LANES can be used to analyze performance of a networking system based on either FDDI or Star*Bus under a variety of loading conditions. Delays due to upper-layer processing can easily be nullified, allowing analysis of FDDI or Star*Bus as stand-alone protocols. LANES is a parameter-driven simulation; it provides considerable flexibility in specifying both protocol an run-time parameters. Code has been optimized for fast execution and detailed tracing facilities have been included. LANES was written in FORTRAN 77 for implementation on a DEC VAX under VMS 4.6. It consists of two programs, a simulation program and a user-interface program. The simulation program requires the SLAM II simulation library from Pritsker and Associates, W. Lafayette IN; the user interface is implemented using the Ingres database manager from Relational Technology, Inc. Information about running the simulation program without the user-interface program is contained in the documentation. The memory requirement is 129,024 bytes. LANES was developed in 1988.

Survey and Analysis of Environmental Requirements for Shipboard Electronic Equipment Applications. Appendix B. Volume 3.

DTIC Science & Technology

1991-07-31

memory banks Up to 1.25MByte SRAM 5 planes of 2048 x 1024 pixels Programmable video parameters max 720 x 512 pixels Sixteen colors TTL RGBI standard...bit I/O extension bus (VLXbus) Up to 2048 KByte 0-wait state static RAM BTT (Built-In-Test) PAL selectable dual ported VMEbus address Two RS-232/422...16, 25, or 33 MHz) A16/24:D08/16 VMEbus interface 8/16-bit I/O Extension bus (VLXbus) Up to 2048 KByte 32-bit wide static RAM -- 0-wait state at 16

Hi Fi Audio Tape to Sun Workstation Transfer System for Digital Audio Data

DTIC Science & Technology

1994-03-01

33 Figure 13 The Interface Memory Map (for 64K X 32 SRAM ). [Ref. 10] ..... 35 Figure 14 Main board data bus connection to the DM bus...module are described separately below. DSP-LINK’C OR SCSI 2K x 32 SRAM 40MMO 51K x 32 atuffersOM C SBus TMS320C30 - - Slave Floating Point A t a...and an ENABLE signal is sent to the device along with a read or a write signal. The memory map of the board with 64k SRAM is shown in Figure 13. The

Specification, Measurement, and Control of Electrical Switching Transients

NASA Technical Reports Server (NTRS)

Javor, K.

1999-01-01

There have been several instances of susceptibility to switching transients. The Space Shuttle Spacelab Remote Acquisition Unit (RAU-A standard interface between Spacelab payloads and the Shuttle communications system) will shut down if the input 28 Vdc bus drops below 22 volts for more than 80 gs. Although a MIL-STD-461 derivative CS06 requirement was levied on the RAU, it failed to find this susceptibility. A heavy payload on one aircraft sags the 28 volt bus below 20 volts for milliseconds. Dc-dc converters have an operating voltage. A typical 28 Vdc-to-5 Vdc converter operates within tolerance when input potential is between 17-40 Vdc, A hold-up capacitor can be used to extend the time this range is presented to the convener when the line potential sags or surges outside this range. The designer must know the range of normal transients in order to choose the correct value of hold-up. This report describes the phenomena of electrical power bus transients induced by the switching of loads both on and off the bus, and control thereof.

A data acquisition and control system for high-speed gamma-ray tomography

NASA Astrophysics Data System (ADS)

Hjertaker, B. T.; Maad, R.; Schuster, E.; Almås, O. A.; Johansen, G. A.

2008-09-01

A data acquisition and control system (DACS) for high-speed gamma-ray tomography based on the USB (Universal Serial Bus) and Ethernet communication protocols has been designed and implemented. The high-speed gamma-ray tomograph comprises five 500 mCi 241Am gamma-ray sources, each at a principal energy of 59.5 keV, which corresponds to five detector modules, each consisting of 17 CdZnTe detectors. The DACS design is based on Microchip's PIC18F4550 and PIC18F4620 microcontrollers, which facilitates an USB 2.0 interface protocol and an Ethernet (IEEE 802.3) interface protocol, respectively. By implementing the USB- and Ethernet-based DACS, a sufficiently high data acquisition rate is obtained and no dedicated hardware installation is required for the data acquisition computer, assuming that it is already equipped with a standard USB and/or Ethernet port. The API (Application Programming Interface) for the DACS is founded on the National Instrument's LabVIEW® graphical development tool, which provides a simple and robust foundation for further application software developments for the tomograph. The data acquisition interval, i.e. the integration time, of the high-speed gamma-ray tomograph is user selectable and is a function of the statistical measurement accuracy required for the specific application. The bandwidth of the DACS is 85 kBytes s-1 for the USB communication protocol and 28 kBytes s-1 for the Ethernet protocol. When using the iterative least square technique reconstruction algorithm with a 1 ms integration time, the USB-based DACS provides an online image update rate of 38 Hz, i.e. 38 frames per second, whereas 31 Hz for the Ethernet-based DACS. The off-line image update rate (storage to disk) for the USB-based DACS is 278 Hz using a 1 ms integration time. Initial characterization of the high-speed gamma-ray tomograph using the DACS on polypropylene phantoms is presented in the paper.

Boeing's STAR-FODB test results

NASA Astrophysics Data System (ADS)

Fritz, Martin E.; de la Chapelle, Michael; Van Ausdal, Arthur W.

1995-05-01

Boeing has successfully concluded a 2 1/2 year, two phase developmental contract for the STAR-Fiber Optic Data Bus (FODB) that is intended for future space-based applications. The first phase included system analysis, trade studies, behavior modeling, and architecture and protocal selection. During this phase we selected AS4074 Linear Token Passing Bus (LTPB) protocol operating at 200 Mbps, along with the passive, star-coupled fiber media. The second phase involved design, build, integration, and performance and environmental test of brassboard hardware. The resulting brassboard hardware successfully passed performance testing, providing 200 Mbps operation with a 32 X 32 star-coupled medium. This hardware is suitable for a spaceflight experiment to validate ground testing and analysis and to demonstrate performace in the intended environment. The fiber bus interface unit (FBIU) is a multichip module containing transceiver, protocol, and data formatting chips, buffer memory, and a station management controller. The FBIU has been designed for low power, high reliability, and radiation tolerance. Nine FBIUs were built and integrated with the fiber optic physical layer consisting of the fiber cable plant (FCP) and star coupler assembly (SCA). Performance and environmental testing, including radiation exposure, was performed on selected FBIUs and the physical layer. The integrated system was demonstrated with a full motion color video image transfer across the bus while simultaneously performing utility functions with a fiber bus control module (FBCM) over a telemetry and control (T&C) bus, in this case AS1773.

The Design of a Fault-Tolerant COTS-Based Bus Architecture for Space Applications

NASA Technical Reports Server (NTRS)

Chau, Savio N.; Alkalai, Leon; Tai, Ann T.

2000-01-01

The high-performance, scalability and miniaturization requirements together with the power, mass and cost constraints mandate the use of commercial-off-the-shelf (COTS) components and standards in the X2000 avionics system architecture for deep-space missions. In this paper, we report our experiences and findings on the design of an IEEE 1394 compliant fault-tolerant COTS-based bus architecture. While the COTS standard IEEE 1394 adequately supports power management, high performance and scalability, its topological criteria impose restrictions on fault tolerance realization. To circumvent the difficulties, we derive a "stack-tree" topology that not only complies with the IEEE 1394 standard but also facilitates fault tolerance realization in a spaceborne system with limited dedicated resource redundancies. Moreover, by exploiting pertinent standard features of the 1394 interface which are not purposely designed for fault tolerance, we devise a comprehensive set of fault detection mechanisms to support the fault-tolerant bus architecture.

Design of an ammonia two-phase Prototype Thermal Bus for Space Station

NASA Technical Reports Server (NTRS)

Brown, Richard F.; Gustafson, Eric; Parish, Richard

1987-01-01

The feasibility of two-phase heat transport systems for use on Space Station was demonstrated by testing the Thermal Bus Technology Demonstrator (TBTD) as part of the Integrated Two-Phase System Test in NASA-JSC's Thermal Test Bed. Under contract to NASA-JSC, Grumman is currently developing the successor to the TBTD, the Prototype Thermal Bus System (TBS). The TBS design, which uses ammonia as the working fluid, is intended to achieve a higher fidelity level than the TBTD by incorporating both improvements based on TBTD testing and realistic design margins, and by addressing Space Station issues such as redundancy and maintenance. The TBS is currently being fabricated, with testing scheduled for late 1987/early 1988. This paper describes the TBS design which features fully redundant plumbing loops, five evaporators designed to represent different heat acquisition interfaces, 14 condensers which mate with either space radiators or facility heat exchangers, and several modular components.

An optical disk archive for a data base management system

NASA Technical Reports Server (NTRS)

Thomas, Douglas T.

1985-01-01

An overview is given of a data base management system that can catalog and archive data at rates up to 50M bits/sec. Emphasis is on the laser disk system that is used for the archive. All key components in the system (3 Vax 11/780s, a SEL 32/2750, a high speed communication interface, and the optical disk) are interfaced to a 100M bits/sec 16-port fiber optic bus to achieve the high data rates. The basic data unit is an autonomous data packet. Each packet contains a primary and secondary header and can be up to a million bits in length. The data packets are recorded on the optical disk at the same time the packet headers are being used by the relational data base management software ORACLE to create a directory independent of the packet recording process. The user then interfaces to the VAX that contains the directory for a quick-look scan or retrieval of the packet(s). The total system functions are distributed between the VAX and the SEL. The optical disk unit records the data with an argon laser at 100M bits/sec from its buffer, which is interfaced to the fiber optic bus. The same laser is used in the read cycle by reducing the laser power. Additional information is given in the form of outlines, charts, and diagrams.

Robust interface between flying and topological qubits

PubMed Central

Xue, Zheng-Yuan; Gong, Ming; Liu, Jia; Hu, Yong; Zhu, Shi-Liang; Wang, Z. D.

2015-01-01

Hybrid architectures, consisting of conventional and topological qubits, have recently attracted much attention due to their capability in consolidating robustness of topological qubits and universality of conventional qubits. However, these two kinds of qubits are normally constructed in significantly different energy scales, and thus the energy mismatch is a major obstacle for their coupling, which can support the exchange of quantum information between them. Here we propose a microwave photonic quantum bus for a strong direct coupling between the topological and conventional qubits, where the energy mismatch is compensated by an external driving field. In the framework of tight-binding simulation and perturbation approach, we show that the energy splitting of Majorana fermions in a finite length nanowire, which we use to define topological qubits, is still robust against local perturbations due to the topology of the system. Therefore, the present scheme realizes a rather robust interface between the flying and topological qubits. Finally, we demonstrate that this quantum bus can also be used to generate multipartitie entangled states with the topological qubits. PMID:26216201

DOE Office of Scientific and Technical Information (OSTI.GOV)

Youssef, Tarek A.; Elsayed, Ahmed T.; Mohammed, Osama A.

This study presents the design and implementation of a communication and control infrastructure for smart grid operation. The proposed infrastructure enhances the reliability of the measurements and control network. The advantages of utilizing the data-centric over message-centric communication approach are discussed in the context of smart grid applications. The data distribution service (DDS) is used to implement a data-centric common data bus for the smart grid. This common data bus improves the communication reliability, enabling distributed control and smart load management. These enhancements are achieved by avoiding a single point of failure while enabling peer-to-peer communication and an automatic discoverymore » feature for dynamic participating nodes. The infrastructure and ideas presented in this paper were implemented and tested on the smart grid testbed. A toolbox and application programing interface for the testbed infrastructure are developed in order to facilitate interoperability and remote access to the testbed. This interface allows control, monitoring, and performing of experiments remotely. Furthermore, it could be used to integrate multidisciplinary testbeds to study complex cyber-physical systems (CPS).« less

CCSDS Time-Critical Onboard Networking Service

NASA Technical Reports Server (NTRS)

Parkes, Steve; Schnurr, Rick; Marquart, Jane; Menke, Greg; Ciccone, Massimiliano

2006-01-01

The Consultative Committee for Space Data Systems (CCSDS) is developing recommendations for communication services onboard spacecraft. Today many different communication buses are used on spacecraft requiring software with the same basic functionality to be rewritten for each type of bus. This impacts on the application software resulting in custom software for almost every new mission. The Spacecraft Onboard Interface Services (SOIS) working group aims to provide a consistent interface to various onboard buses and sub-networks, enabling a common interface to the application software. The eventual goal is reusable software that can be easily ported to new missions and run on a range of onboard buses without substantial modification. The system engineer will then be able to select a bus based on its performance, power, etc and be confident that a particular choice of bus will not place excessive demands on software development. This paper describes the SOIS Intra-Networking Service which is designed to enable data transfer and multiplexing of a variety of internetworking protocols with a range of quality of service support, over underlying heterogeneous data links. The Intra-network service interface provides users with a common Quality of Service interface when transporting data across a variety of underlying data links. Supported Quality of Service (QoS) elements include: Priority, Resource Reservation and Retry/Redundancy. These three QoS elements combine and map into four TCONS services for onboard data communications: Best Effort, Assured, Reserved, and Guaranteed. Data to be transported is passed to the Intra-network service with a requested QoS. The requested QoS includes the type of service, priority and where appropriate, a channel identifier. The data is de-multiplexed, prioritized, and the required resources for transport are allocated. The data is then passed to the appropriate data link for transfer across the bus. The SOIS supported data links may inherently provide the quality of service support requested by the intra-network layer. In the case where the data link does not have the required level of support, the missing functionality is added by SOIS. As a result of this architecture, re-usable software applications can be designed and used across missions thereby promoting common mission operations. In addition, the protocol multiplexing function enables the blending of multiple onboard networks. This paper starts by giving an overview of the SOIS architecture in section 11, illustrating where the TCONS services fit into the overall architecture. It then describes the quality of service approach adopted, in section III. The prototyping efforts that have been going on are introduced in section JY. Finally, in section V the current status of the CCSDS recommendations is summarized.

Interface standards for computer equipment

NASA Technical Reports Server (NTRS)

1976-01-01

The ability to configure data systems using modules provided by independent manufacturers is complicated by the wide range of electrical, mechanical, and functional characteristics exhibited within the equipment provided by different manufacturers of computers, peripherals, and terminal devices. A number of international organizations were and still are involved in the creation of standards that enable devices to be interconnected with minimal difficulty, usually involving only a cable or data bus connection that is defined by the standard. The elements covered by an interface standard are covered and the most prominent interface standards presently in use are identified and described.

Actuator digital interface unit (AIU). [control units for space shuttle data system

NASA Technical Reports Server (NTRS)

1973-01-01

Alternate versions of the actuator interface unit are presented. One alternate is a dual-failure immune configuration which feeds a look-and-switch dual-failure immune hydraulic system. The other alternate is a single-failure immune configuration which feeds a majority voting hydraulic system. Both systems communicate with the data bus through data terminals dedicated to each user subsystem. Both operational control data and configuration control information are processed in and out of the subsystem via the data terminal which yields the actuator interface subsystem, self-managing within its failure immunity capability.

Implementation of a Serial Delay Insertion Type Loop Communication for a Real Time Multitransputer System.

DTIC Science & Technology

1985-06-01

just pass the message WAIT NOW AFTER Rlock + timeo t -- if time is out write.screen( TIME IS OUT") MAIN PROGRAM* CHAN linki , link2, link3, link4...PAR D.I.Loop.Interface (link4, linkl,) D.I.Loop.Interface ( linki , link2, 2) D.I.Loop.Interface (link2, link3, 3) JD.I Loop.Interface (link3, link4, 4

A USB 2.0 computer interface for the UCO/Lick CCD cameras

NASA Astrophysics Data System (ADS)

Wei, Mingzhi; Stover, Richard J.

2004-09-01

The new UCO/Lick Observatory CCD camera uses a 200 MHz fiber optic cable to transmit image data and an RS232 serial line for low speed bidirectional command and control. Increasingly RS232 is a legacy interface supported on fewer computers. The fiber optic cable requires either a custom interface board that is plugged into the mainboard of the image acquisition computer to accept the fiber directly or an interface converter that translates the fiber data onto a widely used standard interface. We present here a simple USB 2.0 interface for the UCO/Lick camera. A single USB cable connects to the image acquisition computer and the camera's RS232 serial and fiber optic cables plug into the USB interface. Since most computers now support USB 2.0 the Lick interface makes it possible to use the camera on essentially any modern computer that has the supporting software. No hardware modifications or additions to the computer are needed. The necessary device driver software has been written for the Linux operating system which is now widely used at Lick Observatory. The complete data acquisition software for the Lick CCD camera is running on a variety of PC style computers as well as an HP laptop.

Space station automation of common module power management and distribution, volume 2

NASA Technical Reports Server (NTRS)

Ashworth, B.; Riedesel, J.; Myers, C.; Jakstas, L.; Smith, D.

1990-01-01

The new Space Station Module Power Management and Distribution System (SSM/PMAD) testbed automation system is described. The subjects discussed include testbed 120 volt dc star bus configuration and operation, SSM/PMAD automation system architecture, fault recovery and management expert system (FRAMES) rules english representation, the SSM/PMAD user interface, and the SSM/PMAD future direction. Several appendices are presented and include the following: SSM/PMAD interface user manual version 1.0, SSM/PMAD lowest level processor (LLP) reference, SSM/PMAD technical reference version 1.0, SSM/PMAD LLP visual control logic representation's (VCLR's), SSM/PMAD LLP/FRAMES interface control document (ICD) , and SSM/PMAD LLP switchgear interface controller (SIC) ICD.

Renewable Electrolysis | Hydrogen and Fuel Cells | NREL

Science.gov Websites

variable-input power conditions Designing and developing shared power-electronics packages and controllers Development NREL develops power electronics interfaces for renewable electrolysis systems to characterize and constant voltage DC bus and power electronics to regulate power output and to convert wild alternating

CAMAC throughput of a new RISC-based data acquisition computer at the DIII-D tokamak

NASA Astrophysics Data System (ADS)

Vanderlaan, J. F.; Cummings, J. W.

1993-10-01

The amount of experimental data acquired per plasma discharge at DIII-D has continued to grow. The largest shot size in May 1991 was 49 Mbyte; in May 1992, 66 Mbyte; and in April 1993, 80 Mbyte. The increasing load has prompted the installation of a new Motorola 88100-based MODCOMP computer to supplement the existing core of three older MODCOMP data acquisition CPU's. New Kinetic Systems CAMAC serial highway driver hardware runs on the 88100 VME bus. The new operating system is MODCOMP REAL/IX version of AT&T System V UNIX with real-time extensions and networking capabilities; future plans call for installation of additional computers of this type for tokamak and neutral beam control functions. Experiences with the CAMAC hardware and software will be chronicled, including observation of data throughput. The Enhanced Serial Highway crate controller is advertised as twice as fast as the previous crate controller, and computer I/O speeds are expected to also increase data rates.

Ultra-compact coherent receiver with serial interface for pluggable transceiver.

PubMed

Itoh, Toshihiro; Nakajima, Fumito; Ohno, Tetsuichiro; Yamanaka, Shogo; Soma, Shunichi; Saida, Takashi; Nosaka, Hideyuki; Murata, Koichi

2014-09-22

An ultra-compact integrated coherent receiver with a volume of 1.3 cc using a quad-channel transimpedance amplifier (TIA)-IC chip with a serial peripheral interface (SPI) is demonstrated for the first time. The TIA with the SPI and photodiode (PD) bias circuits, a miniature dual polarization optical hybrid, an octal-PD and small optical coupling system enabled the realization of the compact receiver. Measured transmission performance with 32 Gbaud dual-polarization quadrature phase shift keying signal is equivalent to that of the conventional multi-source agreement-based integrated coherent receiver with dual channel TIA-ICs. By comparing the bit-error rate (BER) performance with that under continuous SPI access, we also confirmed that there is no BER degradation caused by SPI interface access. Such an ultra-compact receiver is promising for realizing a new generation of pluggable transceivers.

GMSEC Interface Specification Document 2016 March

NASA Technical Reports Server (NTRS)

Handy, Matthew

2016-01-01

The GMSEC Interface Specification Document contains the standard set of defined messages. Each GMSEC standard message contains a GMSEC Information Bus Header section and a Message Contents section. Each message section identifies required fields, optional fields, data type and recommended use of the fields. Additionally, this document includes the message subjects associated with the standard messages. The system design of the operations center should ensure the components that are selected use both the API and the defined standard messages in order to achieve full interoperability from component to component.

Speech-Enabled Interfaces for Travel Information Systems with Large Grammars

NASA Astrophysics Data System (ADS)

Zhao, Baoli; Allen, Tony; Bargiela, Andrzej

This paper introduces three grammar-segmentation methods capable of handling the large grammar issues associated with producing a real-time speech-enabled VXML bus travel application for London. Large grammars tend to produce relatively slow recognition interfaces and this work shows how this limitation can be successfully addressed. Comparative experimental results show that the novel last-word recognition based grammar segmentation method described here achieves an optimal balance between recognition rate, speed of processing and naturalness of interaction.

Experimentation and Evaluation of Advanced Integrated System Concepts.

DTIC Science & Technology

1980-09-26

ART). (b) Selects one of four trunk circuits from each trunk (m) Dual Modem and Loop Interface (DMLI) card. circuit card. (n) Dictation and paging...Arbitrator L Bus - Modems ET _Modems Modems Figure 4-1 Certain Telenet Processor models (see Section 4.3 for details) can be equipped with redundancy to...JMemory Bank B Memory Bank A ArbittrAto Arbitrator A t a i Interface U a Modems $ Figure 4-2 In a system with common logic redundancy all centrally

Instrumentation System Diagnoses a Thermocouple

NASA Technical Reports Server (NTRS)

Perotti, Jose; Santiago, Josephine; Mata, Carlos; Vokrot, Peter; Zavala, Carlos; Burns, Bradley

2008-01-01

An improved self-validating thermocouple (SVT) instrumentation system not only acquires readings from a thermocouple but is also capable of detecting deterioration and a variety of discrete faults in the thermocouple and its lead wires. Prime examples of detectable discrete faults and deterioration include open- and short-circuit conditions and debonding of the thermocouple junction from the object, the temperature of which one seeks to measure. Debonding is the most common cause of errors in thermocouple measurements, but most prior SVT instrumentation systems have not been capable of detecting debonding. The improved SVT instrumentation system includes power circuitry, a cold-junction compensator, signal-conditioning circuitry, pulse-width-modulation (PWM) thermocouple-excitation circuitry, an analog-to-digital converter (ADC), a digital data processor, and a universal serial bus (USB) interface. The system can operate in any of the following three modes: temperature measurement, thermocouple validation, and bonding/debonding detection. The software running in the processor includes components that implement statistical algorithms to evaluate the state of the thermocouple and the instrumentation system. When the power is first turned on, the user can elect to start a diagnosis/ monitoring sequence, in which the PWM is used to estimate the characteristic times corresponding to the correct configuration. The user also has the option of using previous diagnostic values, which are stored in an electrically erasable, programmable read-only memory so that they are available every time the power is turned on.

SNE Industrial Fieldbus Interface

NASA Technical Reports Server (NTRS)

Lucena, Angel; Raines, Matthew; Oostdyk, Rebecca; Mata, Carlos

2011-01-01

Programmable logic controllers (PLCs) have very limited diagnostic and no prognostic capabilities, while current smart sensor designs do not have the capability to communicate over Fieldbus networks. The aim is to interface smart sensors with PLCs so that health and status information, such as failure mode identification and measurement tolerance, can be communicated via an industrial Fieldbus such as ControlNet. The SNE Industrial Fieldbus Interface (SIFI) is an embedded device that acts as a communication module in a networked smart sensor. The purpose is to enable a smart sensor to communicate health and status information to other devices, such as PLCs, via an industrial Fieldbus networking protocol. The SNE (Smart Network Element) is attached to a commercial off-the-shelf Any bus-S interface module through the SIFI. Numerous Anybus-S modules are available, each one designed to interface with a specific Fieldbus. Development of the SIFI focused on communications using the ControlNet protocol, but any of the Anybus-S modules can be used. The SIFI communicates with the Any-bus module via a data buffer and mailbox system on the Anybus module, and supplies power to the module. The Anybus module transmits and receives data on the Fieldbus using the proper protocol. The SIFI is intended to be connected to other existing SNE modules in order to monitor the health and status of a transducer. The SIFI can also monitor aspects of its own health using an onboard watchdog timer and voltage monitors. The SIFI also has the hardware to drive a touchscreen LCD (liquid crystal display) unit for manual configuration and status monitoring.

Radiation-Tolerant, SpaceWire-Compatible Switching Fabric

NASA Technical Reports Server (NTRS)

Katzman, Vladimir

2011-01-01

Current and future near-Earth and deep space exploration programs and space defense programs require the development of robust intra-spacecraft serial data transfer electronics that must be reconfigurable, fault-tolerant, and have the ability to operate effectively for long periods of time in harsh environmental conditions. Existing data transfer systems based on state-of-the-art serial data transfer protocols or passive backplanes are slow, power-hungry, and poorly reconfigurable. They provide limited expandability and poor tolerance to radiation effects and total ionizing dose (TID) in particular, which presents harmful threats to modern submicron electronics. This novel approach is based on a standard library of differential cells tolerant to TID, and patented, multi-level serial interface architecture that ensures the reliable operation of serial interconnects without application of a data-strobe or other encoding techniques. This proprietary, high-speed differential interface presents a lowpower solution fully compatible with the SpaceWire (SW) protocol. It replaces a dual data-strobe link with two identical independent data channels, thus improving the system s tolerance to harsh environments through additional double redundancy. Each channel incorporates an automatic line integrity control circuitry that delivers error signals in case of broken or shorted lines.

Loran-C flight test software

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1978-01-01

The software package developed for the KIM-1 Micro-System and the Mini-L PLL receiver to simplify taking flight test data is described along with the address and data bus buffers used in the KIM-1 Micro-system. The interface hardware and timing are also presented to describe completely the software programs.

Systems design study of the Pioneer Venus spacecraft. Volume 1: Technical analyses and tradeoffs, sections 8-12 (part 4 of 4)

NASA Technical Reports Server (NTRS)

1973-01-01

The probe bus and orbiter subsystems are defined, and tradeoffs analyzed. Subsystems discussed include: communications, electric power, data handling, attitude determination and control, propulsion, thermal control, structure and mechanisms, NASA/ESRO orbiter interface, mission operation, and flight support.

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.

PubMed

Yousefzadeh, Amirreza; Jablonski, Miroslaw; Iakymchuk, Taras; Linares-Barranco, Alejandro; Rosado, Alfredo; Plana, Luis A; Temple, Steve; Serrano-Gotarredona, Teresa; Furber, Steve B; Linares-Barranco, Bernabe

2017-10-01

Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

A design of LED adaptive dimming lighting system based on incremental PID controller

NASA Astrophysics Data System (ADS)

He, Xiangyan; Xiao, Zexin; He, Shaojia

2010-11-01

As a new generation energy-saving lighting source, LED is applied widely in various technology and industry fields. The requirement of its adaptive lighting technology is more and more rigorous, especially in the automatic on-line detecting system. In this paper, a closed loop feedback LED adaptive dimming lighting system based on incremental PID controller is designed, which consists of MEGA16 chip as a Micro-controller Unit (MCU), the ambient light sensor BH1750 chip with Inter-Integrated Circuit (I2C), and constant-current driving circuit. A given value of light intensity required for the on-line detecting environment need to be saved to the register of MCU. The optical intensity, detected by BH1750 chip in real time, is converted to digital signal by AD converter of the BH1750 chip, and then transmitted to MEGA16 chip through I2C serial bus. Since the variation law of light intensity in the on-line detecting environment is usually not easy to be established, incremental Proportional-Integral-Differential (PID) algorithm is applied in this system. Control variable obtained by the incremental PID determines duty cycle of Pulse-Width Modulation (PWM). Consequently, LED's forward current is adjusted by PWM, and the luminous intensity of the detection environment is stabilized by self-adaptation. The coefficients of incremental PID are obtained respectively after experiments. Compared with the traditional LED dimming system, it has advantages of anti-interference, simple construction, fast response, and high stability by the use of incremental PID algorithm and BH1750 chip with I2C serial bus. Therefore, it is suitable for the adaptive on-line detecting applications.

Space station common module thermal management: Design and construction of a test bed

NASA Technical Reports Server (NTRS)

Barile, R. G.

1986-01-01

In this project, a thermal test bed was designed, simulated, and planned for construction. The thermal system features interior and exterior thermal loads and interfacing with the central-radiator thermal bus. Components of the test bed include body mounted radiator loop with interface heat exchangers (600 Btu/hr); an internal loop with cabin air-conditioning and cold plates (3400 Btu/hr); interface heat exchangers to the central bus (13,000 Btu/hr); and provisions for new technology including advanced radiators, thermal storage, and refrigeration. The apparatus will be mounted in a chamber, heated with lamps, and tested in a vacuum chamber with LN2-cooled walls. Simulation of the test bed was accomplished using a DEC PRO 350 computer and the software package TK! olver. Key input variables were absorbed solar radiation and cold plate loads. The results indicate temperatures on the two loops will be nominal when the radiation and cold plate loads are in the range of 25% to 75% of peak loads. If all loads fall to zero, except the cabin air system which was fixed, the radiator fluid will drop below -100 F and may cause excessive pressure drop. If all loads reach 100%, the cabin air temperature could rise to 96 F.

Modeling inter-signal arrival times for accurate detection of CAN bus signal injection attacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moore, Michael Roy; Bridges, Robert A; Combs, Frank L

Modern vehicles rely on hundreds of on-board electronic control units (ECUs) communicating over in-vehicle networks. As external interfaces to the car control networks (such as the on-board diagnostic (OBD) port, auxiliary media ports, etc.) become common, and vehicle-to-vehicle / vehicle-to-infrastructure technology is in the near future, the attack surface for vehicles grows, exposing control networks to potentially life-critical attacks. This paper addresses the need for securing the CAN bus by detecting anomalous traffic patterns via unusual refresh rates of certain commands. While previous works have identified signal frequency as an important feature for CAN bus intrusion detection, this paper providesmore » the first such algorithm with experiments on five attack scenarios. Our data-driven anomaly detection algorithm requires only five seconds of training time (on normal data) and achieves true positive / false discovery rates of 0.9998/0.00298, respectively (micro-averaged across the five experimental tests).« less

Autonomous Cryogenics Loading Operations Simulation Software: Knowledgebase Autonomous Test Engineer

NASA Technical Reports Server (NTRS)

Wehner, Walter S.

2012-01-01

The Simulation Software, KATE (Knowledgebase Autonomous Test Engineer), is used to demonstrate the automatic identification of faults in a system. The ACLO (Autonomous Cryogenics Loading Operation) project uses KATE to monitor and find faults in the loading of the cryogenics int o a vehicle fuel tank. The KATE software interfaces with the IHM (Integrated Health Management) systems bus to communicate with other systems that are part of ACLO. One system that KATE uses the IHM bus to communicate with is AIS (Advanced Inspection System). KATE will send messages to AIS when there is a detected anomaly. These messages include visual inspection of specific valves, pressure gauges and control messages to have AIS open or close manual valves. My goals include implementing the connection to the IHM bus within KATE and for the AIS project. I will also be working on implementing changes to KATE's Ul and implementing the physics objects in KATE that will model portions of the cryogenics loading operation.

Computer Program Development Specification for IDAMST Operational Flight Program Application, Software Type B5. Addendum 1.

DTIC Science & Technology

1976-07-30

Interface Requirements 4 3.1.1.1 Interface Block Diagram 4 3.1.1.2 Detailed Interface Definition 7 3.1.1.2.1 Subsystems 7 3.1.1.2.2 Controls & Displays 11 r...116 3.2.3.2 Navigation Brute Force 121 3.2.3.3 Cargo Brute Force 125 3.2.3.4 Sensor Brute Force 129 3.2.3.5 Controls /Displays Brute Force 135 3.2.3.6...STD-T553 Multiplex Data Bus, with the avionic subsystems, flight * control system, the controls /displays, engine sensors, and airframe sensors. 3.1

Marine Vessel Traffic System

DTIC Science & Technology

2001-06-19

Queue Get Put The MutexQ module provides primitive queue operations which synchronize access to the queues and ensure queue structure integrity...interface provides for synchronous data rates ranging from 64 Kbps to 1.536 Mbps, while an RS-232 interface accommodates asynchronous data up to...interface VME Communications processor 57 and 8-channel serial I/O board. This board set provides a 68040 processor and 8-channels of synchronous

Formal design specification of a Processor Interface Unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1992-01-01

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.

Data management system CIU and DIU. Appendix A: CIU and DIU schematics

NASA Technical Reports Server (NTRS)

1975-01-01

The Computer Interface Unit (CIU) and the Data Interface Unit (DIU) of the Data Management System (DMS) were described as to their functional location, purpose and function. This describes the CIU and DIU at the unit level illustrating their interface thru the Data Bus (DBUS) and to other DMS units. All unit level interfaces are defined as to function and characteristics. The controls, indicators, test points and connectors are listed and function, location and application are described for each. The mechanical configuration is defined and illustrated to provide card and component location for modification or repair purposes. Unique disassembly and assembly requirements are outlined where applicable. A unit internal functional block diagram level description is provided.

Computer hardware for radiologists: Part 2.

PubMed

Indrajit, Ik; Alam, A

2010-11-01

Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the 'ever increasing' digital future.

HERMES travels by CAN bus

NASA Astrophysics Data System (ADS)

Waller, Lewis G.; Shortridge, Keith; Farrell, Tony J.; Vuong, Minh; Muller, Rolf; Sheinis, Andrew I.

2014-07-01

The new HERMES spectrograph represents the first foray by AAO into the use of commercial off-the-shelf industrial field bus technology for instrument control, and we regard the final system, with its relatively simple wiring requirements, as a great success. However, both software and hardware teams had to work together to solve a number of problems integrating the chosen CANopen/CAN bus system into our normal observing systems. A Linux system running in an industrial PC chassis ran the HERMES control software, using a PCI CAN bus interface connected to a number of distributed CANopen/CAN bus I/O devices and servo amplifiers. In the main, the servo amplifiers performed impressively, although some experimentation with homing algorithms was required, and we hit a significant hurdle when we discovered that we needed to disable some of the encoders used during observations; we learned a lot about how servo amplifiers respond when their encoders are turned off, and about how encoders react to losing power. The software was based around a commercial CANopen library from Copley Controls. Early worries about how this heavily multithreaded library would work with our standard data acquisition system led to the development of a very low-level CANopen software simulator to verify the design. This also enabled the software group to develop and test almost all the control software well in advance of the construction of the hardware. In the end, the instrument went from initial installation at the telescope to successful commissioning remarkably smoothly.

A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications †

PubMed Central

Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Muroyama, Masanori

2017-01-01

Robot tactile sensation can enhance human–robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as “sensor platform LSI”) as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated. PMID:29061954

A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications.

PubMed

Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Nonomura, Yutaka; Muroyama, Masanori

2017-08-28

Robot tactile sensation can enhance human-robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as "sensor platform LSI") as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated.

Impacts of Vehicle (In)Security

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chugg, J.; Rohde, K.

Nuclear and radioactive material is routinely transported worldwide every day. Since 2010, the complexity of the transport vehicle to support such activities has grown exponentially. Many core functions of a vehicle are now handled by small embedded computer modules with more being added each year to enhance the owner’s experience and convenience. With a system as complex as today’s automobile, the potential for cyber security issues is certain. Hackers have begun exploring this new domain with public information increasingly disseminated. Because vehicles are allowed into and around secure nuclear facilities, the potential for using a vehicle as a new cybermore » entry point or vector into the facility is now plausible and must be mitigated. In addition, compromising such a vehicle could aide in illicit removal of nuclear material, putting sensitive cargo at risk. Because cyber attacks can now be introduced using vehicles, cyber security, needs to be integrated into an organization’s design basis threat document. Essentially, a vehicle now extends the perimeter for which security professionals are responsible.Electronic Control Units (ECU) responsible for handling all core and ancillary vehicle functions are interconnected using the controller area network (CAN) bus. A typical CAN network in a modern automobile contains 50 or more ECUs. The CAN protocol now supports a wide variety of areas, including automotive, road transportation, rail transportation, industrial automation, power generation, maritime, military vehicles, aviation, and medical devices. In many ways, the nuclear industry is employing the CAN bus protocol or other similar broadcast serial networks. This paper will provide an overview of the current state of automobile and CAN Bus security, as well as an overview of what has been publicly disclosed by many research organizations. It will then present several hypotheses of how vehicle security issues may impact nuclear activities. An initial discussion of how a vehicle can be used as a new threat vector to penetrate secure facilities will be presented. This includes how a modern automobile can be used as the exploitation mechanism for nearby devices such as laptops, cell phones, and wireless access points. Additional discussion will highlight how vehicle security might impact transportation of nuclear material through remote exploitation of a moving vehicle. The final discussion will include what possible implications might be relative to the physical protection systems at nuclear facilities. The audience will also be given details regarding the complexity of attack, thus implying the likelihood of successful exploitation, and information on how such attacks may be mitigated. Emerging security products for automobiles will be discussed and other mitigation methods will be detailed (e.g. disabling vehicle cellular modems). As a result, the audience will have a greater understanding of how to add vehicle security as a part of a comprehensive nuclear security policy.Finally, this paper will highlight the similarities between CAN Bus and other broadcast serial bus networks such as Profibus or DeviceNet, helping educate the reader on how susceptible this type of networking is to nefarious attacks and how it might affect components connected to many different nuclear systems, including control systems, safety systems, emergency systems, and support systems.« less

Research of the small satellite data management system

NASA Astrophysics Data System (ADS)

Yu, Xiaozhou; Zhou, Fengqi; Zhou, Jun

2007-11-01

Small satellite is the integration of light weight, small volume and low launch cost. It is a promising approach to realize the future space mission. A detailed study of the data management system has been carried out, with using new reconfiguration method based on System On Programmable Chip (SOPC). Compared with common structure of satellite, the Central Terminal Unit (CTU), the Remote Terminal Unit (RTU) and Serial Data Bus (SDB) of the data management are all integrated in single chip. Thus the reliability of the satellite is greatly improved. At the same time, the data management system has powerful performance owing to the modern FPGA processing ability.

General purpose programmable accelerator board

DOEpatents

Robertson, Perry J.; Witzke, Edward L.

2001-01-01

A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

Energy Systems Integration News | Energy Systems Integration Facility |

Science.gov Websites

Power Grid Simulation at a Distance NREL and Idaho National Laboratory (INL) have successfully connected of Power System Modeling and Simulation: "Bus.py: A GridLAB-D Communication Interface for Smart Modeling and Simulation" session at the IEEE PES General Meeting in Denver, Colorado, from 15 p.m. on

Data distribution service-based interoperability framework for smart grid testbed infrastructure

DOE PAGES

Youssef, Tarek A.; Elsayed, Ahmed T.; Mohammed, Osama A.

2016-03-02

This study presents the design and implementation of a communication and control infrastructure for smart grid operation. The proposed infrastructure enhances the reliability of the measurements and control network. The advantages of utilizing the data-centric over message-centric communication approach are discussed in the context of smart grid applications. The data distribution service (DDS) is used to implement a data-centric common data bus for the smart grid. This common data bus improves the communication reliability, enabling distributed control and smart load management. These enhancements are achieved by avoiding a single point of failure while enabling peer-to-peer communication and an automatic discoverymore » feature for dynamic participating nodes. The infrastructure and ideas presented in this paper were implemented and tested on the smart grid testbed. A toolbox and application programing interface for the testbed infrastructure are developed in order to facilitate interoperability and remote access to the testbed. This interface allows control, monitoring, and performing of experiments remotely. Furthermore, it could be used to integrate multidisciplinary testbeds to study complex cyber-physical systems (CPS).« less

Smart sensors development based on a distributed bus for microsystems applications

NASA Astrophysics Data System (ADS)

Ferrer, Carles; Lorente, Bibiana

2003-04-01

Our main objective in this work has been to develop a comunication system applicable between sensors and actuators and the data processing circuitry inside the microsystem in order to develop a flexible and modular architecture. This communication system is based on the use of a dedicated sensor bus composed by only two wires (a bidirectional data line and a clock line for sincronization). The basic philosophy of this development has been to create an IP model with VHDL for the bus driver that can be added to the sensor or the actuator to create an smart device that could be easily plugged with the other componets of the microsystem architecture. This methodology can be applied to a high integrated microsystem based on an extensively use of microelectronics technologies (ASICs, SoCs & MCMs). The reduced number of wires is an extraordinary advatage because produce a minimal interconnection between all the components and as a consequence the size of the microinstrument becomes smaller. The second aspect that we have considered in this development has been to reach a communication protocol that permits to built-up a very simple but robust bus driver interface that minimize the circuit overhead. This interconnection system has been applied to biomedical and aerospatial microsystems applications.

SpaceWire Driver Software for Special DSPs

NASA Technical Reports Server (NTRS)

Clark, Douglas; Lux, James; Nishimoto, Kouji; Lang, Minh

2003-01-01

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

High-Performance Satellite/Terrestrial-Network Gateway

NASA Technical Reports Server (NTRS)

Beering, David R.

2005-01-01

A gateway has been developed to enable digital communication between (1) the high-rate receiving equipment at NASA's White Sands complex and (2) a standard terrestrial digital communication network at data rates up to 622 Mb/s. The design of this gateway can also be adapted for use in commercial Earth/satellite and digital communication networks, and in terrestrial digital communication networks that include wireless subnetworks. Gateway as used here signifies an electronic circuit that serves as an interface between two electronic communication networks so that a computer (or other terminal) on one network can communicate with a terminal on the other network. The connection between this gateway and the high-rate receiving equipment is made via a synchronous serial data interface at the emitter-coupled-logic (ECL) level. The connection between this gateway and a standard asynchronous transfer mode (ATM) terrestrial communication network is made via a standard user network interface with a synchronous optical network (SONET) connector. The gateway contains circuitry that performs the conversion between the ECL and SONET interfaces. The data rate of the SONET interface can be either 155.52 or 622.08 Mb/s. The gateway derives its clock signal from a satellite modem in the high-rate receiving equipment and, hence, is agile in the sense that it adapts to the data rate of the serial interface.

TIA Software User's Manual

NASA Technical Reports Server (NTRS)

Cramer, K. Elliott; Syed, Hazari I.

1995-01-01

This user's manual describes the installation and operation of TIA, the Thermal-Imaging acquisition and processing Application, developed by the Nondestructive Evaluation Sciences Branch at NASA Langley Research Center, Hampton, Virginia. TIA is a user friendly graphical interface application for the Macintosh 2 and higher series computers. The software has been developed to interface with the Perceptics/Westinghouse Pixelpipe(TM) and PixelStore(TM) NuBus cards and the GW Instruments MacADIOS(TM) input-output (I/O) card for the Macintosh for imaging thermal data. The software is also capable of performing generic image-processing functions.

Single-channel ground airborne radio system (SINCGARS) based remote control for the M1 Abrahms

NASA Astrophysics Data System (ADS)

Urda, Joseph R.

1995-04-01

Remote control of the Ml Abrahms Main Battle Tank through a minefield breach operation will remove the vehicle crew from the inherent hazard. A successful remote control system will provide automotive control yet not impair normal operation. This requires a minimum of physical parts, and an unobtrusive installation. Most importantly, a system failure must not impair the regular operation as a manned system. The system itself need not be complex. A minefield breach only requires simple control of automotive function and a mine plow interface. Control hardware for the Ml-Al can be reduced to two linear actuators, an electrical interface for the engine control unit, an interface for the mine plow, and the associated cables. Communication between vehicle control and operator control takes place over the vehicles organic radio (typically SINCGARS). This helps reduce the number of special purpose components for the remote control device. The device is currently awaiting an automotive safety test to prepare for its safety release. Because of the specific nature of the MDL-STD 1553-B data bus the device will not control an M1-A2 Main Battle Tank. The architecture will allow control of the M1-A2 through the 1553-B data bus however the physical hardware has not been constructed. The control scheme will not change. The communication interface will provide greater flexibility when interfacing to the vehicle tactical radio. Operational utility will be determined by U.S. Army Training and Doctrine Command personnel. The obvious benefit is that if a remote tank is lost during a minefield breach the crew is saved.

Dumping Low and High Resolution Graphics on the Apple IIe Microcomputer System.

ERIC Educational Resources Information Center

Fletcher, Richard K., Jr.; Ruckman, Frank, Jr.

This paper discusses and outlines procedures for obtaining a hard copy of the graphic output of a microcomputer or "dumping a graphic" using the Apple Dot Matrix Printer with the Apple Parallel Interface Card, and the Imagewriter Printer with the Apple Super Serial Interface Card. Hardware configurations and instructions for high…

Interfacing Optical Document Scanners: Principles and Practical Considerations.

ERIC Educational Resources Information Center

Krus, David J.; Kodimer, Dennis

1987-01-01

Handlers for interfacing the ScanTron and 2700 Optical Mark Readers with the IBM AT/XT/PC and Tandy 2000/1000/3000 iAPX 88/186/286 based computers were described. Differences between programing an RS232C serial port using BIOS interrupts and directly addressing the Motorola 8550 ART microprocessor were discussed. (Author/LMO)

Circuit and Method for Communication Over DC Power Line

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.; Prokop, Norman F.

2007-01-01

A circuit and method for transmitting and receiving on-off-keyed (OOK) signals with fractional signal-to-noise ratios uses available high-temperature silicon- on-insulator (SOI) components to move computational, sensing, and actuation abilities closer to high-temperature or high-ionizing radiation environments such as vehicle engine compartments, deep-hole drilling environments, industrial control and monitoring of processes like smelting, and operations near nuclear reactors and in space. This device allows for the networking of multiple, like nodes to each other and to a central processor. It can do this with nothing more than the already in-situ power wiring of the system. The device s microprocessor allows it to make intelligent decisions within the vehicle operational loop and to effect control outputs to its associated actuators. The figure illustrates how each node converts digital serial data to OOK 18-kHz in transmit mode and vice-versa in receive mode; though operations at lower frequencies or up to a megahertz are within reason using this method and these parts. This innovation s technique modulates a DC power bus with millivolt-level signals through a MOSFET (metal oxide semiconductor field effect transistor) and resistor by OOK. It receives and demodulates this signal from the DC power bus through capacitive coupling at high temperature and in high ionizing radiation environments. The demodulation of the OOK signal is accomplished by using an asynchronous quadrature detection technique realized by a quasi-discrete Fourier transform through use of the quadrature components (0 and 90 phases) of the carrier frequency as generated by the microcontroller and as a function of the selected crystal frequency driving its oscillator. The detected signal is rectified using an absolute-value circuit containing no diodes (diodes being non-operational at high temperatures), and only operational amplifiers. The absolute values of the two phases of the received signal are then summed and hard limited (digitized) by comparing them to a reference level and are then input into a microprocessor as a serial bit stream. The quasi-discrete Fourier transform is performed in high-temperature components (operational amplifiers, analog switches, resistors, and capacitors). The demodulated signal is a serial data stream that is input to the UART (universal asynchronous receiver transmitter) receiver pin of the microprocessor. The OOK of the carrier frequency uses the output of the UART pin as an enabling signal that drives the gate of the MOSFET. Logic low bits enable the carrier frequency (realized by using the 0 phase signal from the microcontroller, though either phase may be used) to be DC-coupled to the power supply bus through a current-limiting resistor mounted between the MOSFET drain and the supply rail. The presence of logic lows on the power supply rail is realized by carrier bursts while logic highs are realized by the absence of bursts.

Using ARINC 818 Avionics Digital Video Bus (ADVB) for military displays

NASA Astrophysics Data System (ADS)

Alexander, Jon; Keller, Tim

2007-04-01

ARINC 818 Avionics Digital Video Bus (ADVB) is a new digital video interface and protocol standard developed especially for high bandwidth uncompressed digital video. The first draft of this standard, released in January of 2007, has been advanced by ARINC and the aerospace community to meet the acute needs of commercial aviation for higher performance digital video. This paper analyzes ARINC 818 for use in military display systems found in avionics, helicopters, and ground vehicles. The flexibility of ARINC 818 for the diverse resolutions, grayscales, pixel formats, and frame rates of military displays is analyzed as well as the suitability of ARINC 818 to support requirements for military video systems including bandwidth, latency, and reliability. Implementation issues relevant to military displays are presented.

RICA: a reliable and image configurable arena for cyborg bumblebee based on CAN bus.

PubMed

Gong, Fan; Zheng, Nenggan; Xue, Lei; Xu, Kedi; Zheng, Xiaoxiang

2014-01-01

In this paper, we designed a reliable and image configurable flight arena, RICA, for developing cyborg bumblebees. To meet the spatial and temporal requirements of bumblebees, the Controller Area Network (CAN) bus is adopted to interconnect the LED display modules to ensure the reliability and real-time performance of the arena system. Easily-configurable interfaces on a desktop computer implemented by python scripts are provided to transmit the visual patterns to the LED distributor online and configure RICA dynamically. The new arena system will be a power tool to investigate the quantitative relationship between the visual inputs and induced flight behaviors and also will be helpful to the visual-motor research in other related fields.

Atmosphere, Magnetosphere and Plasmas in Space (AMPS). Spacelab payload definition study. Volume 3, book 2: AMPS equipment to Spacelab ICD

NASA Technical Reports Server (NTRS)

1976-01-01

The interfaces between AMPS Payload No.(TBD) and Spacelab are described. The interfaces specified cover the AMPS physical, electrical, and thermal interfaces that are established to prescribe the standard Spacelab configuration required to perform the mission. If the configuration definition changes due to change of Spacelab equipment model, or serial numbers, then reidentification of the Labcraft payload may be required.

Access to CAMAC from VxWorks and UNIX in DART

DOE Office of Scientific and Technical Information (OSTI.GOV)

Streets, J.; Meadows, J.; Moore, C.

1995-05-01

As part of the DART Project the authors have developed a package of software for CAMAC access from UNIX and VxWorks platforms, with support for several hardware interfaces. They report on developments for the CES CBD8210 VME to parallel CAMAC, the Hytec VSD2992 VME to serial CAMAC and Jorway 411S SCSI to parallel and serial CAMAC branch drivers, and give a summary of the timings obtained.

Creating, Storing, and Dumping Low and High Resolution Graphics on the Apple IIe Microcomputer System.

ERIC Educational Resources Information Center

Fletcher, Richard K., Jr.

This description of procedures for dumping high and low resolution graphics using the Apple IIe microcomputer system focuses on two special hardware configurations that are commonly used in schools--the Apple Dot Matrix Printer with the Apple Parallel Interface Card, and the Imagewriter Printer with the Apple Super Serial Interface Card. Special…

New methodology of designing inexpensive hybrid control-acquisition systems for mechatronic constructions.

PubMed

Augustyn, Jacek

2013-12-13

This article presents a new methodology for designing a hybrid control and acquisition system consisting of a 32-bit SoC microsystem connected via a direct Universal Serial Bus (USB) with a standard commercial off-the-shelf (COTS) component running the Android operating system. It is proposed to utilize it avoiding the use of an additional converter. An Android-based component was chosen to explore the potential for a mobile, compact and energy efficient solution with easy to build user interfaces and easy wireless integration with other computer systems. This paper presents results of practical implementation and analysis of experimental real-time performance. It covers closed control loop time between the sensor/actuator module and the Android operating system as well as the real-time sensor data stream within such a system. Some optimisations are proposed and their influence on real-time performance was investigated. The proposed methodology is intended for acquisition and control of mechatronic systems, especially mobile robots. It can be used in a wide range of control applications as well as embedded acquisition-recording devices, including energy quality measurements, smart-grids and medicine. It is demonstrated that the proposed methodology can be employed without developing specific device drivers. The latency achieved was less than 0.5 ms and the sensor data stream throughput was on the order of 750 KB/s (compared to 3 ms latency and 300 KB/s in traditional solutions).

New Methodology of Designing Inexpensive Hybrid Control-Acquisition Systems for Mechatronic Constructions

PubMed Central

Augustyn, Jacek

2013-01-01

This article presents a new methodology for designing a hybrid control and acquisition system consisting of a 32-bit SoC microsystem connected via a direct Universal Serial Bus (USB) with a standard commercial off-the-shelf (COTS) component running the Android operating system. It is proposed to utilize it avoiding the use of an additional converter. An Android-based component was chosen to explore the potential for a mobile, compact and energy efficient solution with easy to build user interfaces and easy wireless integration with other computer systems. This paper presents results of practical implementation and analysis of experimental real-time performance. It covers closed control loop time between the sensor/actuator module and the Android operating system as well as the real-time sensor data stream within such a system. Some optimisations are proposed and their influence on real-time performance was investigated. The proposed methodology is intended for acquisition and control of mechatronic systems, especially mobile robots. It can be used in a wide range of control applications as well as embedded acquisition-recording devices, including energy quality measurements, smart-grids and medicine. It is demonstrated that the proposed methodology can be employed without developing specific device drivers. The latency achieved was less than 0.5 ms and the sensor data stream throughput was on the order of 750 KB/s (compared to 3 ms latency and 300 KB/s in traditional solutions). PMID:24351633

Optical backplane interconnect switch for data processors and computers

NASA Technical Reports Server (NTRS)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Mission Management Computer and Sequencing Hardware for RLV-TD HEX-01 Mission

NASA Astrophysics Data System (ADS)

Gupta, Sukrat; Raj, Remya; Mathew, Asha Mary; Koshy, Anna Priya; Paramasivam, R.; Mookiah, T.

2017-12-01

Reusable Launch Vehicle-Technology Demonstrator Hypersonic Experiment (RLV-TD HEX-01) mission posed some unique challenges in the design and development of avionics hardware. This work presents the details of mission critical avionics hardware mainly Mission Management Computer (MMC) and sequencing hardware. The Navigation, Guidance and Control (NGC) chain for RLV-TD is dual redundant with cross-strapped Remote Terminals (RTs) interfaced through MIL-STD-1553B bus. MMC is Bus Controller on the 1553 bus, which does the function of GPS aided navigation, guidance, digital autopilot and sequencing for the RLV-TD launch vehicle in different periodicities (10, 20, 500 ms). Digital autopilot execution in MMC with a periodicity of 10 ms (in ascent phase) is introduced for the first time and successfully demonstrated in the flight. MMC is built around Intel i960 processor and has inbuilt fault tolerance features like ECC for memories. Fault Detection and Isolation schemes are implemented to isolate the failed MMC. The sequencing hardware comprises Stage Processing System (SPS) and Command Execution Module (CEM). SPS is `RT' on the 1553 bus which receives the sequencing and control related commands from MMCs and posts to downstream modules after proper error handling for final execution. SPS is designed as a high reliability system by incorporating various fault tolerance and fault detection features. CEM is a relay based module for sequence command execution.

IEEE 1451.2 based Smart sensor system using ADuc847

NASA Astrophysics Data System (ADS)

Sreejithlal, A.; Ajith, Jose

IEEE 1451 standard defines a standard interface for connecting transducers to microprocessor based data acquisition systems, instrumentation systems, control and field networks. Smart transducer interface module (STIM) acts as a unit which provides signal conditioning, digitization and data packet generation functions to the transducers connected to it. This paper describes the implementation of a microcontroller based smart transducer interface module based on IEEE 1451.2 standard. The module, implemented using ADuc847 microcontroller has 2 transducer channels and is programmed using Embedded C language. The Sensor system consists of a Network Controlled Application Processor (NCAP) module which controls the Smart transducer interface module (STIM) over an IEEE1451.2-RS232 bus. The NCAP module is implemented as a software module in C# language. The hardware details, control principles involved and the software implementation for the STIM are described in detail.

A real time data acquisition system using the MIL-STD-1553B bus. [for transmission of data to host computer for control law processing

NASA Technical Reports Server (NTRS)

Peri, Frank, Jr.

1992-01-01

A flight digital data acquisition system that uses the MIL-STD-1553B bus for transmission of data to a host computer for control law processing is described. The instrument, the Remote Interface Unit (RIU), can accommodate up to 16 input channels and eight output channels. The RIU employs a digital signal processor to perform local digital filtering before sending data to the host. The system allows flexible sensor and actuator data organization to facilitate quick control law computations on the host computer. The instrument can also run simple control laws autonomously without host intervention. The RIU and host computer together have replaced a similar larger, ground minicomputer system with favorable results.

Telemetry Standards, IRIG Standard 106-17. Chapter 10. Digital Recording Standard

DTIC Science & Technology

2017-07-01

10-28 10.7.9 Required Discrete Control Functions...1553 data bus, time, analog, video, Aeronautical Radio, Inc. 429, discrete , and Universal Asynchronous Receiver and Transmitter containing...Interfaces 10.3, 10.4 Fibre Channel and/or IEEE 1394b Data Download Port 10.3, 10.7 Discrete Lines and/or RS-232 and 422 Full Duplex Communication 10.3

Active Low Intrusion Hybrid Monitor for Wireless Sensor Networks

PubMed Central

Navia, Marlon; Campelo, Jose C.; Bonastre, Alberto; Ors, Rafael; Capella, Juan V.; Serrano, Juan J.

2015-01-01

Several systems have been proposed to monitor wireless sensor networks (WSN). These systems may be active (causing a high degree of intrusion) or passive (low observability inside the nodes). This paper presents the implementation of an active hybrid (hardware and software) monitor with low intrusion. It is based on the addition to the sensor node of a monitor node (hardware part) which, through a standard interface, is able to receive the monitoring information sent by a piece of software executed in the sensor node. The intrusion on time, code, and energy caused in the sensor nodes by the monitor is evaluated as a function of data size and the interface used. Then different interfaces, commonly available in sensor nodes, are evaluated: serial transmission (USART), serial peripheral interface (SPI), and parallel. The proposed hybrid monitor provides highly detailed information, barely disturbed by the measurement tool (interference), about the behavior of the WSN that may be used to evaluate many properties such as performance, dependability, security, etc. Monitor nodes are self-powered and may be removed after the monitoring campaign to be reused in other campaigns and/or WSNs. No other hardware-independent monitoring platforms with such low interference have been found in the literature. PMID:26393604

Effect of display size on visual attention.

PubMed

Chen, I-Ping; Liao, Chia-Ning; Yeh, Shih-Hao

2011-06-01

Attention plays an important role in the design of human-machine interfaces. However, current knowledge about attention is largely based on data obtained when using devices of moderate display size. With advancement in display technology comes the need for understanding attention behavior over a wider range of viewing sizes. The effect of display size on test participants' visual search performance was studied. The participants (N = 12) performed two types of visual search tasks, that is, parallel and serial search, under three display-size conditions (16 degrees, 32 degrees, and 60 degrees). Serial, but not parallel, search was affected by display size. In the serial task, mean reaction time for detecting a target increased with the display size.

The surface chemical reactivity of particles and its impact on human health

NASA Astrophysics Data System (ADS)

Setyan, A.; Sauvain, J. J.; Riediker, M.; Guillemin, M.; Rossi, M. J.

2017-12-01

The chemical composition of the particle-air interface is the gateway to chemical reactions of gases with condensed phase particles. It is of prime importance to understand the reactivity of particles and their interaction with surrounding gases, biological membranes, and solid supports. We used a Knudsen flow reactor to quantify functional groups on the surface of a few selected particle types. This technique is based on a heterogeneous titration reaction between a probe gas and a specific functional group on the particle surface. Six probe gases have been selected for the identification and quantification of important functional groups: N(CH3)3 for the titration of acidic sites, NH2OH for the detection of carbonyl functions (aldehydes and ketones) and/or oxidized sites owing to its strong reducing properties, CF3COOH and HCl for basic sites of different strength, O3 and NO2 for oxidizable groups. We also studied the kinetics of the reactions between particles and probe gases (uptake coefficient γ0). We tested the surface chemical composition and oxidation states of laboratory-generated aerosols (3 amorphous carbons, 2 flame soots, 2 Diesel particles, 2 secondary organic aerosols [SOA], 4 multiwall carbon nanotubes [MWCNT], 3 TiO2, and 2 metal salts) and of aerosols sampled in several bus depots. The sampling of particles in the bus depots was accompanied by the collection of urine samples of mechanics working full-time in these bus depots, and the quantification of 8-hydroxy-2'-deoxyguanosine, a biomarker of oxidative stress. The increase in oxidative stress biomarker levels over a working day was correlated (p<0.05) with the number of olefinic and/or PAH sites on the surface of particles sampled at the bus depots, obtained from O3 uptakes, as well as with the initial uptake coefficient (γ0) of five probe gases used in the field. This correlation with γ0 suggests the idea of competing pathways occurring at the interface of the aerosol particles between the generation of reactive oxygen species (ROS) responsible for oxidative stress and cellular antioxidants.

Access to CAMAC from VxWorks and UNIX in DART

NASA Astrophysics Data System (ADS)

Streets, J.; Meadows, J.; Moore, C.; Pordes, R.; Slimmer, D.; Vittone, M.; Stern, E.

1996-02-01

As part of the DART Project [Data acquisition for the next Generation Fermilab Fixed Target Experiments] we have developed a package of software for CAMAC access from UNIX and VxWorks platforms, with support for several hardware interfaces. We report on developments for the CES CBD8210 VME to parallel CAMAC, the Hytec VSD2992 VME to serial CAMAC and Jorway 411s SCSI to parallel and serial CAMAC branch drivers, and give a summary of the timings obtained.

Test-bench system for a borehole azimuthal acoustic reflection imaging logging tool

NASA Astrophysics Data System (ADS)

Liu, Xianping; Ju, Xiaodong; Qiao, Wenxiao; Lu, Junqiang; Men, Baiyong; Liu, Dong

2016-06-01

The borehole azimuthal acoustic reflection imaging logging tool (BAAR) is a new generation of imaging logging tool, which is able to investigate stratums in a relatively larger range of space around the borehole. The BAAR is designed based on the idea of modularization with a very complex structure, so it has become urgent for us to develop a dedicated test-bench system to debug each module of the BAAR. With the help of a test-bench system introduced in this paper, test and calibration of BAAR can be easily achieved. The test-bench system is designed based on the client/server model. The hardware system mainly consists of a host computer, an embedded controlling board, a bus interface board, a data acquisition board and a telemetry communication board. The host computer serves as the human machine interface and processes the uploaded data. The software running on the host computer is designed based on VC++. The embedded controlling board uses Advanced Reduced Instruction Set Machines 7 (ARM7) as the micro controller and communicates with the host computer via Ethernet. The software for the embedded controlling board is developed based on the operating system uClinux. The bus interface board, data acquisition board and telemetry communication board are designed based on a field programmable gate array (FPGA) and provide test interfaces for the logging tool. To examine the feasibility of the test-bench system, it was set up to perform a test on BAAR. By analyzing the test results, an unqualified channel of the electronic receiving cabin was discovered. It is suggested that the test-bench system can be used to quickly determine the working condition of sub modules of BAAR and it is of great significance in improving production efficiency and accelerating industrial production of the logging tool.

Distributed On-line Monitoring System Based on Modem and Public Phone Net

NASA Astrophysics Data System (ADS)

Chen, Dandan; Zhang, Qiushi; Li, Guiru

In order to solve the monitoring problem of urban sewage disposal, a distributed on-line monitoring system is proposed. By introducing dial-up communication technology based on Modem, the serial communication program can rationally solve the information transmission problem between master station and slave station. The realization of serial communication program is based on the MSComm control of C++ Builder 6.0.The software includes real-time data operation part and history data handling part, which using Microsoft SQL Server 2000 for database, and C++ Builder6.0 for user interface. The monitoring center displays a user interface with alarm information of over-standard data and real-time curve. Practical application shows that the system has successfully accomplished the real-time data acquisition from data gather station, and stored them in the terminal database.

Interfacing sensory input with motor output: does the control architecture converge to a serial process along a single channel?

PubMed Central

van de Kamp, Cornelis; Gawthrop, Peter J.; Gollee, Henrik; Lakie, Martin; Loram, Ian D.

2013-01-01

Modular organization in control architecture may underlie the versatility of human motor control; but the nature of the interface relating sensory input through task-selection in the space of performance variables to control actions in the space of the elemental variables is currently unknown. Our central question is whether the control architecture converges to a serial process along a single channel? In discrete reaction time experiments, psychologists have firmly associated a serial single channel hypothesis with refractoriness and response selection [psychological refractory period (PRP)]. Recently, we developed a methodology and evidence identifying refractoriness in sustained control of an external single degree-of-freedom system. We hypothesize that multi-segmental whole-body control also shows refractoriness. Eight participants controlled their whole body to ensure a head marker tracked a target as fast and accurately as possible. Analysis showed enhanced delays in response to stimuli with close temporal proximity to the preceding stimulus. Consistent with our preceding work, this evidence is incompatible with control as a linear time invariant process. This evidence is consistent with a single-channel serial ballistic process within the intermittent control paradigm with an intermittent interval of around 0.5 s. A control architecture reproducing intentional human movement control must reproduce refractoriness. Intermittent control is designed to provide computational time for an online optimization process and is appropriate for flexible adaptive control. For human motor control we suggest that parallel sensory input converges to a serial, single channel process involving planning, selection, and temporal inhibition of alternative responses prior to low dimensional motor output. Such design could aid robots to reproduce the flexibility of human control. PMID:23675342

Generic Bluetooth Data Module

DTIC Science & Technology

2002-09-01

to Ref (1). 34 RS232.java Serial Coomunication port class To Bluetooth module HCI.java Host Control Interface class L2CAP.java Logical Link Control...standard protocol for transporting IP datagrams over point-to-point link . It is designed to run over RFCOMM to accomplish point-to-point connections...Control and Adaption Host Controller Interface Link Manager Baseband / Link Controller Radio Figure 2. Bluetooth layers (From Ref. [3].) C

LabVIEW Interface for PCI-SpaceWire Interface Card

NASA Technical Reports Server (NTRS)

Lux, James; Loya, Frank; Bachmann, Alex

2005-01-01

This software provides a LabView interface to the NT drivers for the PCISpaceWire card, which is a peripheral component interface (PCI) bus interface that conforms to the IEEE-1355/ SpaceWire standard. As SpaceWire grows in popularity, the ability to use SpaceWire links within LabVIEW will be important to electronic ground support equipment vendors. In addition, there is a need for a high-level LabVIEW interface to the low-level device- driver software supplied with the card. The LabVIEW virtual instrument (VI) provides graphical interfaces to support all (1) SpaceWire link functions, including message handling and routing; (2) monitoring as a passive tap using specialized hardware; and (3) low-level access to satellite mission-control subsystem functions. The software is supplied in a zip file that contains LabVIEW VI files, which provide various functions of the PCI-SpaceWire card, as well as higher-link-level functions. The VIs are suitably named according to the matching function names in the driver manual. A number of test programs also are provided to exercise various functions.

Coherent Dynamics of a Hybrid Quantum Spin-Mechanical Oscillator System

NASA Astrophysics Data System (ADS)

Lee, Kenneth William, III

A fully functional quantum computer must contain at least two important components: a quantum memory for storing and manipulating quantum information and a quantum data bus to securely transfer information between quantum memories. Typically, a quantum memory is composed of a matter system, such as an atom or an electron spin, due to their prolonged quantum coherence. Alternatively, a quantum data bus is typically composed of some propagating degree of freedom, such as a photon, which can retain quantum information over long distances. Therefore, a quantum computer will likely be a hybrid quantum device, consisting of two or more disparate quantum systems. However, there must be a reliable and controllable quantum interface between the memory and bus in order to faithfully interconvert quantum information. The current engineering challenge for quantum computers is scaling the device to large numbers of controllable quantum systems, which will ultimately depend on the choice of the quantum elements and interfaces utilized in the device. In this thesis, we present and characterize a hybrid quantum device comprised of single nitrogen-vacancy (NV) centers embedded in a high quality factor diamond mechanical oscillator. The electron spin of the NV center is a leading candidate for the realization of a quantum memory due to its exceptional quantum coherence times. On the other hand, mechanical oscillators are highly sensitive to a wide variety of external forces, and have the potential to serve as a long-range quantum bus between quantum systems of disparate energy scales. These two elements are interfaced through crystal strain generated by vibrations of the mechanical oscillator. Importantly, a strain interface allows for a scalable architecture, and furthermore, opens the door to integration into a larger quantum network through coupling to an optical interface. There are a few important engineering challenges associated with this device. First, there have been no previous demonstrations of a strain-mediated spin-mechanical interface and hence the system is largely uncharacterized. Second, fabricating high quality diamond mechanical oscillators is difficult due to the robust and chemically inert nature of diamond. Finally, engineering highly coherent NV centers with a coherent optical interface in nanostructured diamond remains an outstanding challenge. In this thesis, we theoretically and experimentally address each of these challenges, and show that with future improvements, this device is suitable for future quantum-enabled applications. First, we theoretically and experimentally demonstrate a dynamic, strain-mediated coupling between the spin and orbital degrees of freedom of the NV center and the driven mechanical motion of a single-crystal diamond cantilever. We employ Ramsey interferometry to demonstrate coherent, mechanical driving of the NV spin evolution. Using this interferometry technique, we present the first demonstration of nanoscale strain imaging, and quantitatively characterize the previously unknown spin-strain coupling constants. Next, we use the driven motion of the cantilever to perform deterministic control of the frequency and polarization dependence of the optical transitions of the NV center. Importantly, this experiment constitutes the first demonstration of on-chip control of both the frequency and polarization state of a single photon produced by a quantum emitter. In the final experiment, we use mechanical driving to engineer a series of spin ``clock" states and demonstrate a significant increase in the spin coherence time of the NV center. We conclude this thesis with a theoretical discussion of prospective applications for this device, including generation of non-classical mechanical states and spin-spin entanglement, as well as an evaluation of the current limitations of our devices, including a possible avenues for improvement to reach the regime of strong spin-phonon coupling.

Advanced flight control system study

NASA Technical Reports Server (NTRS)

Mcgough, J.; Moses, K.; Klafin, J. F.

1982-01-01

The architecture, requirements, and system elements of an ultrareliable, advanced flight control system are described. The basic criteria are functional reliability of 10 to the minus 10 power/hour of flight and only 6 month scheduled maintenance. A distributed system architecture is described, including a multiplexed communication system, reliable bus controller, the use of skewed sensor arrays, and actuator interfaces. Test bed and flight evaluation program are proposed.

Analyzing Pulse-Code Modulation On A Small Computer

NASA Technical Reports Server (NTRS)

Massey, David E.

1988-01-01

System for analysis pulse-code modulation (PCM) comprises personal computer, computer program, and peripheral interface adapter on circuit board that plugs into expansion bus of computer. Functions essentially as "snapshot" PCM decommutator, which accepts and stores thousands of frames of PCM data, sifts through them repeatedly to process according to routines specified by operator. Enables faster testing and involves less equipment than older testing systems.

Software Architecture Evolution

DTIC Science & Technology

2013-12-01

system’s major components occurring via a Java Message Service message bus [69]. This architecture was designed to promote loose coupling of soft- ware...play reconfiguration of the system. The components were Java -based and platform-independent; the interfaces by which they communicated were based on...The MPCS database, a MySQL database used for storing telemetry as well as some other information, such as logs and commanding data [68]. This

Local-Area-Network Simulator

NASA Technical Reports Server (NTRS)

Gibson, Jim; Jordan, Joe; Grant, Terry

1990-01-01

Local Area Network Extensible Simulator (LANES) computer program provides method for simulating performance of high-speed local-area-network (LAN) technology. Developed as design and analysis software tool for networking computers on board proposed Space Station. Load, network, link, and physical layers of layered network architecture all modeled. Mathematically models according to different lower-layer protocols: Fiber Distributed Data Interface (FDDI) and Star*Bus. Written in FORTRAN 77.

Multisite Testing of the Discrete Address Beacon System (DABS).

DTIC Science & Technology

1981-07-01

downlink messages from an airborne distributed computer system containing , transponder in addition to performing 36 minicomputers, most of which are...the lockout function. organized into groups (or ensembles) of four computers interfaced to a local Each sensor may provide surveillance and data bus...position and velocity. Depending upon computer subsystem, which monitors the means used for scenario generation, in real time all communication and aircraft

A PC-Based Controller for Dextrous Arms

NASA Technical Reports Server (NTRS)

Fiorini, Paolo; Seraji, Homayoun; Long, Mark

1996-01-01

This paper describes the architecture and performance of a PC-based controller for 7-DOF dextrous manipulators. The computing platform is a 486-based personal computer equipped with a bus extender to access the robot Multibus controller, together with a single board computer as the graphical engine, and with a parallel I/O board to interface with a force-torque sensor mounted on the manipulator wrist.

Autonomous Cryogenics Loading Operations Simulation Software: Knowledgebase Autonomous Test Engineer

NASA Technical Reports Server (NTRS)

Wehner, Walter S., Jr.

2013-01-01

Working on the ACLO (Autonomous Cryogenics Loading Operations) project I have had the opportunity to add functionality to the physics simulation software known as KATE (Knowledgebase Autonomous Test Engineer), create a new application allowing WYSIWYG (what-you-see-is-what-you-get) creation of KATE schematic files and begin a preliminary design and implementation of a new subsystem that will provide vision services on the IHM (Integrated Health Management) bus. The functionality I added to KATE over the past few months includes a dynamic visual representation of the fluid height in a pipe based on number of gallons of fluid in the pipe and implementing the IHM bus connection within KATE. I also fixed a broken feature in the system called the Browser Display, implemented many bug fixes and made changes to the GUI (Graphical User Interface).

Resonant AC power system proof-of-concept test program

NASA Technical Reports Server (NTRS)

Wappes, Loran J.

1986-01-01

Proof-of-concept testing was performed on a 20-kHz, resonant power system breadboard from 1981 through 1985. The testing began with the evaluation of a single, 1.0-kW resonant inverter and progressed to the testing of breadboard systems with higher power levels and more capability. The final breadboard configuration tested was a 25.0-kW breadboard with six inverters providing power to three user-interface modules over a 50-meter, 20-kHz bus. The breadboard demonstrated the ability to synchronize multiple resonant inverters to power a common bus. Single-phase and three-phase 20-kHz power distribution was demonstrated. Simple conversion of 20-kHz to dc and variable-frequency ac was demonstrated as was bidirectional power flow between 20-kHz and dc. Steady state measurements of efficiency, power-factor tolerance, and conducted emissions and conducted susceptibility were made. In addition, transient responses were recorded for such conditions as start up, shut down, load changes. The results showed the 20-kHz resonant system to be a desirable technology for a spacecraft power management and distribution system with multiple users and a utility-type bus.

SEASAT study documentation

NASA Technical Reports Server (NTRS)

1974-01-01

The proposed spacecraft consists of a bus module, containing all subsystems required for support of the sensors, and a payload module containing all of the sensor equipment. The two modules are bolted together to form the spacecraft, and electrical interfaces are accomplished via mated connectors at the interface plane. This approach permits independent parallel assembly and test operations on each module up until mating for final spacecraft integration and test operations. Proposed program schedules recognize the need to refine sensor/spacecraft interfaces prior to proceeding with procurement, reflect the lead times estimated by suppliers for delivery of equipment, reflect a comprehensive test program, and provide flexibility for unanticipated problems. The spacecraft systems are described in detail along with aerospace ground equipment, ground handling equipment, the launch vehicle, imaging radar incorporation, and systems tests.

Automated Library System Specifications.

DTIC Science & Technology

1986-06-01

University), LIS (Georqetown Universitv Medical Center) 20 DiSTRI3UT!ON.. AVAILABILITY OF ABSTRACT 21 ABSTRACT SECURITY CLASSIFICATION :UNCLASSIFIED...Interface) acquisitions, patron access catalo. (Boolean search), authority Afiles, zana ~ezient reports. Serials control expected in 1985. INDIVIDUALIZATIOI

Memory interface simulator: A computer design aid

NASA Technical Reports Server (NTRS)

Taylor, D. S.; Williams, T.; Weatherbee, J. E.

1972-01-01

Results are presented of a study conducted with a digital simulation model being used in the design of the Automatically Reconfigurable Modular Multiprocessor System (ARMMS), a candidate computer system for future manned and unmanned space missions. The model simulates the activity involved as instructions are fetched from random access memory for execution in one of the system central processing units. A series of model runs measured instruction execution time under various assumptions pertaining to the CPU's and the interface between the CPU's and RAM. Design tradeoffs are presented in the following areas: Bus widths, CPU microprogram read only memory cycle time, multiple instruction fetch, and instruction mix.

Towards the formal verification of the requirements and design of a processor interface unit: HOL listings

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

This technical report contains the Higher-Order Logic (HOL) listings of the partial verification of the requirements and design for a commercially developed processor interface unit (PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault tolerant computer system. This system, the Fault Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU verification as it currently exists. Section two of this report contains general-purpose HOL theories and definitions that support the PIU verification. These include arithmetic theories dealing with inequalities and associativity, and a collection of tactics used in the PIU proofs. Section three contains the HOL listings for the completed PIU design verification. Section 4 contains the HOL listings for the partial requirements verification of the P-Port.

Redundancy management of multiple KT-70 inertial measurement units applicable to the space shuttle

NASA Technical Reports Server (NTRS)

Cook, L. J.

1975-01-01

Results of an investigation of velocity failure detection and isolation for 3 inertial measuring units (IMU) and 2 inertial measuring units (IMU) configurations are presented. The failure detection and isolation algorithm performance was highly successful and most types of velocity errors were detected and isolated. The failure detection and isolation algorithm also included attitude FDI but was not evaluated because of the lack of time and low resolution in the gimbal angle synchro outputs. The shuttle KT-70 IMUs will have dual-speed resolvers and high resolution gimbal angle readouts. It was demonstrated by these tests that a single computer utilizing a serial data bus can successfully control a redundant 3-IMU system and perform FDI.

Application of Wuhan Ionospheric Oblique Backscattering Sounding System (WIOBSS) for the investigation of midlatitude ionospheric irregularities

NASA Astrophysics Data System (ADS)

Wang, Jin; Zhou, Xiaoming; Qiao, Lei; Gong, Wanlin

2018-03-01

An upgrade of Wuhan Ionospheric Backscattering Sounding System (WIOBSS) was developed in 2015. Based on the Universal Serial Bus (USB), and a high performance FPGA, the newly designed WIOBSS has a completely digital structure, which makes it portable and flexible. Two identical WIOBSSs, which were situated at Mile (24.31°N, 103.39°E) and Puer (22.74°N, 101.05°E) respectively, were used to investigate the ionospheric irregularities. The comparisons of group distance, Doppler shift and width between Mile-Puer and Puer-Mile VHF ionospheric propagation paths indicate that the reciprocity of the irregularities is satisfied at midlatitude region. The WIOBSS is robust in the detection of ionospheric irregularities.

General-Purpose Serial Interface For Remote Control

NASA Technical Reports Server (NTRS)

Busquets, Anthony M.; Gupton, Lawrence E.

1990-01-01

Computer controls remote television camera. General-purpose controller developed to serve as interface between host computer and pan/tilt/zoom/focus functions on series of automated video cameras. Interface port based on 8251 programmable communications-interface circuit configured for tristated outputs, and connects controller system to any host computer with RS-232 input/output (I/O) port. Accepts byte-coded data from host, compares them with prestored codes in read-only memory (ROM), and closes or opens appropriate switches. Six output ports control opening and closing of as many as 48 switches. Operator controls remote television camera by speaking commands, in system including general-purpose controller.

28-Bit serial word simulator/monitor

NASA Technical Reports Server (NTRS)

Durbin, J. W.

1979-01-01

Modular interface unit transfers data at high speeds along four channels. Device expedites variable-word-length communication between computers. Operation eases exchange of bit information by automatically reformatting coded input data and status information to match requirements of output.

A novel brain-computer interface based on the rapid serial visual presentation paradigm.

PubMed

Acqualagna, Laura; Treder, Matthias Sebastian; Schreuder, Martijn; Blankertz, Benjamin

2010-01-01

Most present-day visual brain computer interfaces (BCIs) suffer from the fact that they rely on eye movements, are slow-paced, or feature a small vocabulary. As a potential remedy, we explored a novel BCI paradigm consisting of a central rapid serial visual presentation (RSVP) of the stimuli. It has a large vocabulary and realizes a BCI system based on covert non-spatial selective visual attention. In an offline study, eight participants were presented sequences of rapid bursts of symbols. Two different speeds and two different color conditions were investigated. Robust early visual and P300 components were elicited time-locked to the presentation of the target. Offline classification revealed a mean accuracy of up to 90% for selecting the correct symbol out of 30 possibilities. The results suggest that RSVP-BCI is a promising new paradigm, also for patients with oculomotor impairments.

Universal Reconfigurable Translator Module (URTM) Final Report

NASA Technical Reports Server (NTRS)

Leventhal, Edward; Machan, Roman; Jones, Rob

2009-01-01

This report describes the Universal Reconfigurable Translation Module, or URTM. The URTM was developed by Sigma Space Corporation for NASA in order to translate specific serial protocols, both logically and physically. At present, the prototype configuration has targeted MIL-STD-1553B (RT and BC), IEEE 1394b (Firewire), and ECSS-E-50-12A (SpaceWire). The objectives of this program were to study the feasibility of a configurable URTM to translate serial link data as might be used in a space-flight mission and to design, develop, document, and deliver an engineering prototype model of the URTM with a path to spaceflight. By simply connecting two of the three Physical Interface Modules (PIM) on either end of the RPTM (Reconfigurable Protocol Translator Module), the URTM then self configures via a library of interface translation functions, thereby allowing the two data links to communicate seamlessly.

Microcomputer data acquisition and control.

PubMed

East, T D

1986-01-01

In medicine and biology there are many tasks that involve routine well defined procedures. These tasks are ideal candidates for computerized data acquisition and control. As the performance of microcomputers rapidly increases and cost continues to go down the temptation to automate the laboratory becomes great. To the novice computer user the choices of hardware and software are overwhelming and sadly most of the computer sales persons are not at all familiar with real-time applications. If you want to bill your patients you have hundreds of packaged systems to choose from; however, if you want to do real-time data acquisition the choices are very limited and confusing. The purpose of this chapter is to provide the novice computer user with the basics needed to set up a real-time data acquisition system with the common microcomputers. This chapter will cover the following issues necessary to establish a real time data acquisition and control system: Analysis of the research problem: Definition of the problem; Description of data and sampling requirements; Cost/benefit analysis. Choice of Microcomputer hardware and software: Choice of microprocessor and bus structure; Choice of operating system; Choice of layered software. Digital Data Acquisition: Parallel Data Transmission; Serial Data Transmission; Hardware and software available. Analog Data Acquisition: Description of amplitude and frequency characteristics of the input signals; Sampling theorem; Specification of the analog to digital converter; Hardware and software available; Interface to the microcomputer. Microcomputer Control: Analog output; Digital output; Closed-Loop Control. Microcomputer data acquisition and control in the 21st Century--What is in the future? High speed digital medical equipment networks; Medical decision making and artificial intelligence.

Implementation Of The Configurable Fault Tolerant System Experiment On NPSAT 1

DTIC Science & Technology

2016-03-01

REPORT TYPE AND DATES COVERED Master’s thesis 4. TITLE AND SUBTITLE IMPLEMENTATION OF THE CONFIGURABLE FAULT TOLERANT SYSTEM EXPERIMENT ON NPSAT...open-source microprocessor without interlocked pipeline stages (MIPS) based processor softcore, a cached memory structure capable of accessing double...data rate type three and secure digital card memories, an interface to the main satellite bus, and XILINX’s soft error mitigation softcore. The

Design of the Bus Interface Unit for the Distributed Processor/Memory System.

DTIC Science & Technology

1976-12-01

microroutine flowchart developed. Once this had been done , a high-speed, flexible microprocessor that would be adapt- able to a hardware...routine) was translated Into microcode and provide the mnemonic code and flowchart , Chapter V summarizes and discusses actual system construction...Fig. 11. This diagram shows that the BIU is driven by Interrupt stimuli which select the beginn ing address of the appropriate microroutine rather

Crew/cargo and logistics module definition

NASA Technical Reports Server (NTRS)

1971-01-01

The logistics requirements for the space station cargo, the initial buildup, and the 90 day resupply are presented, along with the conceptual selection for the orbiter crew accommodations and the GSS logistics system. Various module configurations are outlined; structural/mechanical, environmental, temperature, voice communication, and data bus subsystems are also reviewed. Ground operations and module prelaunch and launch operations are discussed, as well as logistics system interfaces for space shuttles and stations.

Design and Analysis of an Attitude Determination and Control Subsystem (ADCS) for AFIT’s 6U Standard Bus

DTIC Science & Technology

2014-03-27

Fault Detection and Isolation GUI Graphical User Interface IGRF International Geomagnetic Reference Field IMU Inertial Measurement Unit IR infrared xv...ADCS hardware components were either commercially purchased or built in-house and include an Inertial Measurement Unit ( IMU ), external magnetometer, 4...3.2.1.3 IMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.1.4 External Magnetometer . . . . . . . . . . . . . . . . . . 48 3.2.2

The ISES: A non-intrusive medium for in-space experiments in on-board information extraction

NASA Technical Reports Server (NTRS)

Murray, Nicholas D.; Katzberg, Stephen J.; Nealy, Mike

1990-01-01

The Information Science Experiment System (ISES) represents a new approach in applying advanced systems technology and techniques to on-board information extraction in the space environment. Basically, what is proposed is a 'black box' attached to the spacecraft data bus or local area network. To the spacecraft the 'black box' appears to be just another payload requiring power, heat rejection, interfaces, adding weight, and requiring time on the data management and communication system. In reality, the 'black box' is a programmable computational resource which eavesdrops on the data network, taking and producing selectable, real-time science data back on the network. This paper will present a brief overview of the ISES Concept and will discuss issues related to applying the ISES to the polar platform and Space Station Freedom. Critical to the operation of ISES is the viability of a payload-like interface to the spacecraft data bus or local area network. Study results that address this question will be reviewed vis-a-vis the solar platform and the core space station. Also, initial results of processing science and other requirements for onboard, real-time information extraction will be presented with particular emphasis on the polar platform. Opportunities for a broader range of applications on the core space station will also be discussed.

Impedance Discontinuity Reduction Between High-Speed Differential Connectors and PCB Interfaces

NASA Technical Reports Server (NTRS)

Navidi, Sal; Agdinaoay, Rodell; Walter, Keith

2013-01-01

High-speed serial communication (i.e., Gigabit Ethernet) requires differential transmission and controlled impedances. Impedance control is essential throughout cabling, connector, and circuit board construction. An impedance discontinuity arises at the interface of a high-speed quadrax and twinax connectors and the attached printed circuit board (PCB). This discontinuity usually is lower impedance since the relative dielectric constant of the board is higher (i.e., polyimide approx. = 4) than the connector (Teflon approx. = 2.25). The discontinuity can be observed in transmit or receive eye diagrams, and can reduce the effective link margin of serial data networks. High-speed serial data network transmission improvements can be made at the connector-to-board interfaces as well as improving differential via hole impedances. The impedance discontinuity was improved by 10 percent by drilling a 20-mil (approx. = 0.5-mm) hole in between the pin of a differential connector spaced 55 mils (approx. = 1.4 mm) apart as it is attached to the PCB. The effective dielectric constant of the board can be lowered by drilling holes into the board material between the differential lines in a quadrax or twinax connector attachment points. The differential impedance is inversely proportional to the square root of the relative dielectric constant. This increases the differential impedance and thus reduces the above described impedance discontinuity. The differential via hole impedance can also be increased in the same manner. This technique can be extended to multiple smaller drilled holes as well as tapered holes (i.e., big in the middle followed by smaller ones diagonally).

Stand-alone digital data storage control system including user control interface

NASA Technical Reports Server (NTRS)

Wright, Kenneth D. (Inventor); Gray, David L. (Inventor)

1994-01-01

A storage control system includes an apparatus and method for user control of a storage interface to operate a storage medium to store data obtained by a real-time data acquisition system. Digital data received in serial format from the data acquisition system is first converted to a parallel format and then provided to the storage interface. The operation of the storage interface is controlled in accordance with instructions based on user control input from a user. Also, a user status output is displayed in accordance with storage data obtained from the storage interface. By allowing the user to control and monitor the operation of the storage interface, a stand-alone, user-controllable data storage system is provided for storing the digital data obtained by a real-time data acquisition system.

System Architecture For High Speed Sorting Of Potatoes

NASA Astrophysics Data System (ADS)

Marchant, J. A.; Onyango, C. M.; Street, M. J.

1989-03-01

This paper illustrates an industrial application of vision processing in which potatoes are sorted according to their size and shape at speeds of up to 40 objects per second. The result is a multi-processing approach built around the VME bus. A hardware unit has been designed and constructed to encode the boundary of the potatoes, to reducing the amount of data to be processed. A master 68000 processor is used to control this unit and to handle data transfers along the bus. Boundary data is passed to one of three 68010 slave processors each responsible for a line of potatoes across a conveyor belt. The slave processors calculate attributes such as shape, size and estimated weight of each potato and the master processor uses this data to operate the sorting mechanism. The system has been interfaced with a commercial grading machine and performance trials are now in progress.

General-purpose interface bus for multiuser, multitasking computer system

NASA Technical Reports Server (NTRS)

Generazio, Edward R.; Roth, Don J.; Stang, David B.

1990-01-01

The architecture of a multiuser, multitasking, virtual-memory computer system intended for the use by a medium-size research group is described. There are three central processing units (CPU) in the configuration, each with 16 MB memory, and two 474 MB hard disks attached. CPU 1 is designed for data analysis and contains an array processor for fast-Fourier transformations. In addition, CPU 1 shares display images viewed with the image processor. CPU 2 is designed for image analysis and display. CPU 3 is designed for data acquisition and contains 8 GPIB channels and an analog-to-digital conversion input/output interface with 16 channels. Up to 9 users can access the third CPU simultaneously for data acquisition. Focus is placed on the optimization of hardware interfaces and software, facilitating instrument control, data acquisition, and processing.

The third level trigger and output event unit of the UA1 data-acquisition system

NASA Astrophysics Data System (ADS)

Cittolin, S.; Demoulin, M.; Fucci, A.; Haynes, W.; Martin, B.; Porte, J. P.; Sphicas, P.

1989-12-01

The upgraded UA1 experiment utilizes twelve 3081/E emulators for its third-level trigger system. The system is interfaced to VME, and is controlled by 68000 microprocessor VME boards on the input and output. The output controller communicates with an IBM 9375 mainframe via the CERN-IBM developed VICI interface. The events selected by the emulators are output on IBM-3480 cassettes. The user interface to this system is based on a series of Macintosh personal computer connected to the VME bus. These Macs are also used for developing software for the emulators and for monitoring the entire system. The same configuration has also been used for offline event reconstruction. A description of the system, together with details of both the online and offline modes of operation and an eveluation of its performance are presented.

Towards the formal specification of the requirements and design of a processor interface unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.'

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oxoby, G.J.; Trang, Q.H.; Williams, S.H.

The advent of the personal microcomputer provides a new tool for the debugging, calibration and monitoring of small scale physics apparatus, e.g., a single detector being developed for a larger physics apparatus. With an appropriate interface these microcomputer systems provide a low cost (1/3 the cost of a comparable minicomputer system), convenient, dedicated, portable system which can be used in a fashion similar to that of portable oscilloscopes. Here, an interface between the Apple computer and CAMAC which is now being used to study the detector for a Cerenkov ring-imaging device is described. The Apple is particularly well-suited to thismore » application because of its ease of use, hi-resolution graphics, peripheral bus and documentation support.« less

A PDP-15 to industrial-14 interface at the Lewis Research Center's cyclotron

NASA Technical Reports Server (NTRS)

Kebberly, F. R.; Leonard, R. F.

1977-01-01

An interface (hardware and software) was built which permits the loading, monitoring, and control of a digital equipment industrial-14/30 programmable controller by a PDP-15 computer. The interface utilizes the serial mode for data transfer to and from the controller, so that the required hardware is essentially that of a teletype unit except for the speed of transmission. Software described here permits the user to load binary paper tape, read or load individual controller memory locations, and if desired turn controller outputs on and off directly from the computer.

Bubble memory module

NASA Technical Reports Server (NTRS)

Bohning, O. D.; Becker, F. J.

1980-01-01

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses.

Strategies for Competition Beyond Open Architecture (OA): Acquisition at the Edge of Chaos

DTIC Science & Technology

2014-11-08

critical region in which the global properties of the system take on regular behavior, such as a power-law distribution of event sizes. Such ideas are...standardization can improve system developments. For example, satellite development can be improved by using standard interfaces for the sensors...installed on the satellite bus. This allows for more adaptability within the system.1 The adaptability is a key foundation for realizing capability on demand

Computing Systems Configuration for Highly Integrated Guidance and Control Systems

DTIC Science & Technology

1988-06-01

conmmunication ear lea imlustrielaiservenant dais an projet. Cela eat renda , possible entre auies par l’adoption dene mibodologie do travai coammune, par...computed graph results to data processors for post processing, or commnicating with system I/O modules. The ESU PI- Bus interface logic includes extra ...the extra constraint checking helps to find more problems at compile time), and it is especially well- suited for large software systems written by a

Long Range Plan for Embedded Computer Systems Support. Volume II

DTIC Science & Technology

1981-10-01

interface (pilot displays and controls plus visual system), and data collection (CMAC data, bus data and simulation data). Non-real time functions include...unless adequate upfront planning is implemented, the command will be controlled by the dynamics rather than controll - ing them. The upfront planning should...or should they be called manually? What amount and type of data should the various tools pass between each other? Under what conditions and controls

A Proven Ground System Architecture for Promoting Collaboration and Common Solutions at NASA

NASA Technical Reports Server (NTRS)

Smith, Danford

2005-01-01

Requirement: Improve how NASA develops and maintains ground data systems for dozens of missions, with a couple new missions always in the development phase. Decided in 2001 on enhanced message-bus architecture. Users offered choices for major components. They plug and play because key interfaces are all the same. Can support COTS, heritage, and new software. Even the middleware can be switched. Project name: GMSEC. Goddard Mission Services Evolution Center.

Parallel processing approach to transform-based image coding

NASA Astrophysics Data System (ADS)

Normile, James O.; Wright, Dan; Chu, Ken; Yeh, Chia L.

1991-06-01

This paper describes a flexible parallel processing architecture designed for use in real time video processing. The system consists of floating point DSP processors connected to each other via fast serial links, each processor has access to a globally shared memory. A multiple bus architecture in combination with a dual ported memory allows communication with a host control processor. The system has been applied to prototyping of video compression and decompression algorithms. The decomposition of transform based algorithms for decompression into a form suitable for parallel processing is described. A technique for automatic load balancing among the processors is developed and discussed, results ar presented with image statistics and data rates. Finally techniques for accelerating the system throughput are analyzed and results from the application of one such modification described.

Webcam autofocus mechanism used as a delay line for the characterization of femtosecond pulses.

PubMed

Castro-Marín, Pablo; Kapellmann-Zafra, Gabriel; Garduño-Mejía, Jesús; Rosete-Aguilar, Martha; Román-Moreno, Carlos J

2015-08-01

In this work, we present an electromagnetic focusing mechanism (EFM), from a commercial webcam, implemented as a delay line of a femtosecond laser pulse characterization system. The characterization system consists on a second order autocorrelator based on a two-photon-absorption detection. The results presented here were performed for two different home-made femtosecond oscillators: Ti:sapph @ 820 nm and highly chirped pulses generated with an Erbium Doped Fiber @ 1550 nm. The EFM applied as a delay line represents an excellent alternative due its performance in terms of stability, resolution, and long scan range up to 3 ps. Due its low power consumption, the device can be connected through the Universal Serial Bus (USB) port. Details of components, schematics of electronic controls, and detection systems are presented.

Webcam autofocus mechanism used as a delay line for the characterization of femtosecond pulses

NASA Astrophysics Data System (ADS)

Castro-Marín, Pablo; Kapellmann-Zafra, Gabriel; Garduño-Mejía, Jesús; Rosete-Aguilar, Martha; Román-Moreno, Carlos J.

2015-08-01

In this work, we present an electromagnetic focusing mechanism (EFM), from a commercial webcam, implemented as a delay line of a femtosecond laser pulse characterization system. The characterization system consists on a second order autocorrelator based on a two-photon-absorption detection. The results presented here were performed for two different home-made femtosecond oscillators: Ti:sapph @ 820 nm and highly chirped pulses generated with an Erbium Doped Fiber @ 1550 nm. The EFM applied as a delay line represents an excellent alternative due its performance in terms of stability, resolution, and long scan range up to 3 ps. Due its low power consumption, the device can be connected through the Universal Serial Bus (USB) port. Details of components, schematics of electronic controls, and detection systems are presented.

Digital transmitter for data bus communications system

NASA Technical Reports Server (NTRS)

Proch, G. E. (Inventor)

1975-01-01

An improved digital transmitter for transmitting serial pulse code modulation (pcm) data at high bit rates over a transmission line is disclosed. When not transmitting, the transmitter features a high output impedance which prevents the transmitter from loading the transmission line. The pcm input is supplied to a logic control circuit which produces two discrete logic level signals which are supplied to an amplifier. The amplifier, which is transformer coupled to the output isolation circuitry, converts the discrete logic level signals to two high current level, ground isolated signals in the secondary windings of the coupling transformer. The latter signals are employed as inputs to the isolation circuitry which includes two series transistor pairs operating into a hybrid transformer functioning to isolate the transmitter circuitry from the transmission line.

A life scientist's gateway to distributed data management and computing: the PathPort/ToolBus framework.

PubMed

Eckart, J Dana; Sobral, Bruno W S

2003-01-01

The emergent needs of the bioinformatics community challenge current information systems. The pace of biological data generation far outstrips Moore's Law. Therefore, a gap continues to widen between the capabilities to produce biological (molecular and cell) data sets and the capability to manage and analyze these data sets. As a result, Federal investments in large data set generation produces diminishing returns in terms of the community's capabilities of understanding biology and leveraging that understanding to make scientific and technological advances that improve society. We are building an open framework to address various data management issues including data and tool interoperability, nomenclature and data communication standardization, and database integration. PathPort, short for Pathogen Portal, employs a generic, web-services based framework to deal with some of the problems identified by the bioinformatics community. The motivating research goal of a scalable system to provide data management and analysis for key pathosystems, especially relating to molecular data, has resulted in a generic framework using two major components. On the server-side, we employ web-services. On the client-side, a Java application called ToolBus acts as a client-side "bus" for contacting data and tools and viewing results through a single, consistent user interface.

Building distributed rule-based systems using the AI Bus

NASA Technical Reports Server (NTRS)

Schultz, Roger D.; Stobie, Iain C.

1990-01-01

The AI Bus software architecture was designed to support the construction of large-scale, production-quality applications in areas of high technology flux, running heterogeneous distributed environments, utilizing a mix of knowledge-based and conventional components. These goals led to its current development as a layered, object-oriented library for cooperative systems. This paper describes the concepts and design of the AI Bus and its implementation status as a library of reusable and customizable objects, structured by layers from operating system interfaces up to high-level knowledge-based agents. Each agent is a semi-autonomous process with specialized expertise, and consists of a number of knowledge sources (a knowledge base and inference engine). Inter-agent communication mechanisms are based on blackboards and Actors-style acquaintances. As a conservative first implementation, we used C++ on top of Unix, and wrapped an embedded Clips with methods for the knowledge source class. This involved designing standard protocols for communication and functions which use these protocols in rules. Embedding several CLIPS objects within a single process was an unexpected problem because of global variables, whose solution involved constructing and recompiling a C++ version of CLIPS. We are currently working on a more radical approach to incorporating CLIPS, by separating out its pattern matcher, rule and fact representations and other components as true object oriented modules.

Modernization of the NASA IRTF Telescope Control System

NASA Astrophysics Data System (ADS)

Pilger, Eric J.; Harwood, James V.; Onaka, Peter M.

1994-06-01

We describe the ongoing modernization of the NASA IR Telescope Facility Telescope Control System. A major mandate of this project is to keep the telescope available for observations throughout. Therefore, we have developed an incremental plan that will allow us to replace components of the software and hardware without shutting down the system. The current system, running under FORTH on a DEC LSI 11/23 minicomputer interfaced to a Bus and boards developed in house, will be replaced with a combination of a Sun SPARCstation running SunOS, a MicroSPARC based Single Board Computer running LynxOS, and various intelligent VME based peripheral cards. The software is based on a design philosophy originally developed by Pat Wallace for use on the Anglo Australian Telescope. This philosophy has gained wide acceptance, and is currently used in a number of observatories around the world. A key element of this philosophy is the division of the TCS into `Virtual' and `Real' parts. This will allow us to replace the higher level functions of the TCS with software running on the Sun, while still relying on the LSI 11/23 for performance of the lower level functions. Eventual transfer of lower level functions to the MicroSPARC system will then proceed incrementally through use of a Q-Bus to VME-Bus converter.

Shark: SQL and Analytics with Cost-Based Query Optimization on Coarse-Grained Distributed Memory

DTIC Science & Technology

2014-01-13

RDBMS and contains a database (often MySQL or Derby) with a namespace for tables, table metadata and partition information. Table data is stored in an...serialization/deserialization) Java interface implementations with corresponding object inspectors. The Hive driver controls the processing of queries, coordinat...native API, RDD operations are invoked through a functional interface similar to DryadLINQ [32] in Scala, Java or Python. For example, the Scala code for

Local intelligent electronic device (IED) rendering templates over limited bandwidth communication link to manage remote IED

DOEpatents

Bradetich, Ryan; Dearien, Jason A; Grussling, Barry Jakob; Remaley, Gavin

2013-11-05

The present disclosure provides systems and methods for remote device management. According to various embodiments, a local intelligent electronic device (IED) may be in communication with a remote IED via a limited bandwidth communication link, such as a serial link. The limited bandwidth communication link may not support traditional remote management interfaces. According to one embodiment, a local IED may present an operator with a management interface for a remote IED by rendering locally stored templates. The local IED may render the locally stored templates using sparse data obtained from the remote IED. According to various embodiments, the management interface may be a web client interface and/or an HTML interface. The bandwidth required to present a remote management interface may be significantly reduced by rendering locally stored templates rather than requesting an entire management interface from the remote IED. According to various embodiments, an IED may comprise an encryption transceiver.

User interface for a tele-operated robotic hand system

DOEpatents

Crawford, Anthony L

2015-03-24

Disclosed here is a user interface for a robotic hand. The user interface anchors a user's palm in a relatively stationary position and determines various angles of interest necessary for a user's finger to achieve a specific fingertip location. The user interface additionally conducts a calibration procedure to determine the user's applicable physiological dimensions. The user interface uses the applicable physiological dimensions and the specific fingertip location, and treats the user's finger as a two link three degree-of-freedom serial linkage in order to determine the angles of interest. The user interface communicates the angles of interest to a gripping-type end effector which closely mimics the range of motion and proportions of a human hand. The user interface requires minimal contact with the operator and provides distinct advantages in terms of available dexterity, work space flexibility, and adaptability to different users.

Programmable Pulse-Position-Modulation Encoder

NASA Technical Reports Server (NTRS)

Zhu, David; Farr, William

2006-01-01

A programmable pulse-position-modulation (PPM) encoder has been designed for use in testing an optical communication link. The encoder includes a programmable state machine and an electronic code book that can be updated to accommodate different PPM coding schemes. The encoder includes a field-programmable gate array (FPGA) that is programmed to step through the stored state machine and code book and that drives a custom high-speed serializer circuit board that is capable of generating subnanosecond pulses. The stored state machine and code book can be updated by means of a simple text interface through the serial port of a personal computer.

A Virtual Instrument Panel and Serial Interface for the Parr 1672 Thermometer

ERIC Educational Resources Information Center

Salter, Gail; Range, Kevin; Salter, Carl

2005-01-01

The various features of a Visual Basic Program, which implements the 1672 Parr thermometer are described. The program permits remote control of the calorimetry experiment and also provides control for the flow of data and for file storage.

General purpose PDP-11 interface processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Purtilo, J.

1982-10-01

The Z80 interface card, which for simplicity we refer to as the Zcard, is a general purpose microprocessor which is directly interfaced to the Whaley multiplexor, itself implemented on PDP-11 series computers at the University of Illinois. The Zcard provides two serial ports at EAI interface levels and contains up to 16K of local memory. The principle function of the Zcard is to serve as an interface in which the user might alter protocols, change interface characteristics (e.g. baud rate, hardware echo, or flow control), or switch between synchronous and asynchronous modes all under software control. In addition, the Zcardmore » provides extra lines for control of external devices (e.g. modem) and input of status data. In the simpliest use, the Zcard runs a program, downloaded from the PDP-11, which emulates the level EIAFB card (previously developed for the Whaley Multiplexor) for serial communication with terminals. Using no flow control, Zcard performance seems superior to that of the EIAFB card in that no characters are lost under normal use (due to the much larger buffer which the Zcard can provide). The Zcard can further distinguish itself from the EIAFB card in that flow control can be enabled by software. A more sophisticated application of the Zcard might include linking several Zcards (using a synchronous option and both of the provided ports) into a network. In this capacity, a ring topology suggests itself as the most immediate choice, although many alternate connection schemes can be envisioned. This report is intended to summarize the project as well as provide an outline for those intending to modify or program the Zcard.« less

Digital Interface Board to Control Phase and Amplitude of Four Channels

NASA Technical Reports Server (NTRS)

Smith, Amy E.; Cook, Brian M.; Khan, Abdur R.; Lux, James P.

2011-01-01

An increasing number of parts are designed with digital control interfaces, including phase shifters and variable attenuators. When designing an antenna array in which each antenna has independent amplitude and phase control, the number of digital control lines that must be set simultaneously can grow very large. Use of a parallel interface would require separate line drivers, more parts, and thus additional failure points. A convenient form of control where single-phase shifters or attenuators could be set or the whole set could be programmed with an update rate of 100 Hz is needed to solve this problem. A digital interface board with a field-programmable gate array (FPGA) can simultaneously control an essentially arbitrary number of digital control lines with a serial command interface requiring only three wires. A small set of short, high-level commands provides a simple programming interface for an external controller. Parity bits are used to validate the control commands. Output timing is controlled within the FPGA to allow for rapid update rates of the phase shifters and attenuators. This technology has been used to set and monitor eight 5-bit control signals via a serial UART (universal asynchronous receiver/transmitter) interface. The digital interface board controls the phase and amplitude of the signals for each element in the array. A host computer running Agilent VEE sends commands via serial UART connection to a Xilinx VirtexII FPGA. The commands are decoded, and either outputs are set or telemetry data is sent back to the host computer describing the status and the current phase and amplitude settings. This technology is an integral part of a closed-loop system in which the angle of arrival of an X-band uplink signal is detected and the appropriate phase shifts are applied to the Ka-band downlink signal to electronically steer the array back in the direction of the uplink signal. It will also be used in the non-beam-steering case to compensate for phase shift variations through power amplifiers. The digital interface board can be used to set four 5-bit phase shifters and four 5-bit attenuators and monitor their current settings. Additionally, it is useful outside of the closed-loop system for beamsteering alone. When the VEE program is started, it prompts the user to initialize variables (to zero) or skip initialization. After that, the program enters into a continuous loop waiting for the telemetry period to elapse or a button to be pushed. A telemetry request is sent when the telemetry period is elapsed (every five seconds). Pushing one of the set or reset buttons will send the appropriate command. When a command is sent, the interface status is returned, and the user will be notified by a pop-up window if any error has occurred. The program runs until the End Program button is depressed.

User's guide to noise data acquisition and analysis programs for HP9845: Nicolet analyzers

NASA Technical Reports Server (NTRS)

Mcgary, M. C.

1982-01-01

A software interface package was written for use with a desktop computer and two models of single channel Fast Fourier analyzers. This software features a portable measurement and analysis system with several options. Two types of interface hardware can alternately be used in conjunction with the software. Either an IEEE-488 Bus interface or a 16-bit parallel system may be used. Two types of storage medium, either tape cartridge or floppy disc can be used with the software. Five types of data may be stored, plotted, and/or printed. The data types include time histories, narrow band power spectra, and narrow band, one-third octave band, or octave band sound pressure level. The data acquisition programming includes a front panel remote control option for the FFT analyzers. Data analysis options include choice of line type and pen color for plotting.

ESTL tracking and data relay satellite /TDRSS/ simulation system

NASA Technical Reports Server (NTRS)

Kapell, M. H.

1980-01-01

The Tracking Data Relay Satellite System (TDRSS) provides single access forward and return communication links with the Shuttle/Orbiter via S-band and Ku-band frequency bands. The ESTL (Electronic Systems Test Laboratory) at Lyndon B. Johnson Space Center (JSC) utilizes a TDRS satellite simulator and critical TDRS ground hardware for test operations. To accomplish Orbiter/TDRSS relay communications performance testing in the ESTL, a satellite simulator was developed which met the specification requirements of the TDRSS channels utilized by the Orbiter. Actual TDRSS ground hardware unique to the Orbiter communication interfaces was procured from individual vendors, integrated in the ESTL, and interfaced via a data bus for control and status monitoring. This paper discusses the satellite simulation hardware in terms of early development and subsequent modifications. The TDRS ground hardware configuration and the complex computer interface requirements are reviewed. Also, special test hardware such as a radio frequency interference test generator is discussed.

Exploring system interconnection architectures with VIPACES: from direct connections to NOCs

NASA Astrophysics Data System (ADS)

Sánchez-Peña, Armando; Carballo, Pedro P.; Núñez, Antonio

2007-05-01

This paper presents a simple environment for the verification of AMBA 3 AXI systems in Verification IP (VIP) production called VIPACES (Verification Interface Primitives for the development of AXI Compliant Elements and Systems). These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his modules to the AMBA 3 AXI protocol. This topic is the main discussion in the VIPACES library. The paper focuses on comparing and contrasting the main interconnection schemes for AMBA 3 AXI as modeled by VIPACES. For assessing these results we propose a validation scenario with a particular architecture belonging to the domain of MPEG4 video decoding, which is compound by an AXI bus connecting an IDCT and other processing resources.

Toward a formal verification of a floating-point coprocessor and its composition with a central processing unit

NASA Technical Reports Server (NTRS)

Pan, Jing; Levitt, Karl N.; Cohen, Gerald C.

1991-01-01

Discussed here is work to formally specify and verify a floating point coprocessor based on the MC68881. The HOL verification system developed at Cambridge University was used. The coprocessor consists of two independent units: the bus interface unit used to communicate with the cpu and the arithmetic processing unit used to perform the actual calculation. Reasoning about the interaction and synchronization among processes using higher order logic is demonstrated.

An Investigation of DC-DC Converter Power Density Using Si and SiC MOSFETS

DTIC Science & Technology

2010-05-07

submarine or small surface combatant, volumetric constraints quickly become extremely prohibitive. Dedicating generators for high power loads takes...thermal compounds were applied to the MOSFET-heat sink interface. For the Si APT26F120B2, MG Chemicals TC-450ML thermal epoxy was used to connect the... submarines , bus converter modules must be made optimally power dense in order to decrease volumetric requirements of the modules for a rated throughput

Reconfigurable Processing Module

NASA Technical Reports Server (NTRS)

Somervill, Kevin; Hodson, Robert; Jones, Robert; Williams, John

2005-01-01

To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to the moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Application FPGA - or simply "the application" - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

MPEG-1 low-cost encoder solution

NASA Astrophysics Data System (ADS)

Grueger, Klaus; Schirrmeister, Frank; Filor, Lutz; von Reventlow, Christian; Schneider, Ulrich; Mueller, Gerriet; Sefzik, Nicolai; Fiedrich, Sven

1995-02-01

A solution for real-time compression of digital YCRCB video data to an MPEG-1 video data stream has been developed. As an additional option, motion JPEG and video telephone streams (H.261) can be generated. For MPEG-1, up to two bidirectional predicted images are supported. The required computational power for motion estimation and DCT/IDCT, memory size and memory bandwidth have been the main challenges. The design uses fast-page-mode memory accesses and requires only one single 80 ns EDO-DRAM with 256 X 16 organization for video encoding. This can be achieved only by using adequate access and coding strategies. The architecture consists of an input processing and filter unit, a memory interface, a motion estimation unit, a motion compensation unit, a DCT unit, a quantization control, a VLC unit and a bus interface. For using the available memory bandwidth by the processing tasks, a fixed schedule for memory accesses has been applied, that can be interrupted for asynchronous events. The motion estimation unit implements a highly sophisticated hierarchical search strategy based on block matching. The DCT unit uses a separated fast-DCT flowgraph realized by a switchable hardware unit for both DCT and IDCT operation. By appropriate multiplexing, only one multiplier is required for: DCT, quantization, inverse quantization, and IDCT. The VLC unit generates the video-stream up to the video sequence layer and is directly coupled with an intelligent bus-interface. Thus, the assembly of video, audio and system data can easily be performed by the host computer. Having a relatively low complexity and only small requirements for DRAM circuits, the developed solution can be applied to low-cost encoding products for consumer electronics.

Low cost open data acquisition system for biomedical applications

NASA Astrophysics Data System (ADS)

Zabolotny, Wojciech M.; Laniewski-Wollk, Przemyslaw; Zaworski, Wojciech

2005-09-01

In the biomedical applications it is often necessary to collect measurement data from different devices. It is relatively easy, if the devices are equipped with a MIB or Ethernet interface, however often they feature only the asynchronous serial link, and sometimes the measured values are available only as the analog signals. The system presented in the paper is a low cost alternative to commercially available data acquisition systems. The hardware and software architecture of the system is fully open, so it is possible to customize it for particular needs. The presented system offers various possibilities to connect it to the computer based data processing unit - e.g. using the USB or Ethernet ports. Both interfaces allow also to use many such systems in parallel to increase amount of serial and analog inputs. The open source software used in the system makes possible to process the acquired data with standard tools like MATLAB, Scilab or Octave, or with a dedicated, user supplied application.

The Unification of Space Qualified Integrated Circuits by Example of International Space Project GAMMA-400

NASA Astrophysics Data System (ADS)

Bobkov, S. G.; Serdin, O. V.; Arkhangelskiy, A. I.; Arkhangelskaja, I. V.; Suchkov, S. I.; Topchiev, N. P.

The problem of electronic component unification at the different levels (circuits, interfaces, hardware and software) used in space industry is considered. The task of computer systems for space purposes developing is discussed by example of scientific data acquisition system for space project GAMMA-400. The basic characteristics of high reliable and fault tolerant chips developed by SRISA RAS for space applicable computational systems are given. To reduce power consumption and enhance data reliability, embedded system interconnect made hierarchical: upper level is Serial RapidIO 1x or 4x with rate transfer 1.25 Gbaud; next level - SpaceWire with rate transfer up to 400 Mbaud and lower level - MIL-STD-1553B and RS232/RS485. The Ethernet 10/100 is technology interface and provided connection with the previously released modules too. Systems interconnection allows creating different redundancy systems. Designers can develop heterogeneous systems that employ the peer-to-peer networking performance of Serial RapidIO using multiprocessor clusters interconnected by SpaceWire.

Physics Bus: An Innovative Model for Public Engagement

NASA Astrophysics Data System (ADS)

Fox, Claire

The Physics Bus is about doing science for fun. It is an innovative model for science outreach whose mission is to awaken joy and excitement in physics for all ages and walks of life - especially those underserved by science enrichment. It is a mobile exhibition of upcycled appliances-reimagined by kids-that showcase captivating physics phenomena. Inside our spaceship-themed school bus, visitors will find: a microwave ionized-gas disco-party, fog rings that shoot from a wheelbarrow tire, a tv whose electron beam is controlled by a toy keyboard, and over 20 other themed exhibits. The Physics Bus serves a wide range of public in diverse locations from local neighborhoods, urban parks and rural schools, to cross-country destinations. Its approachable, friendly and relaxed environment allows for self-paced and self-directed interactions, providing a positive and engaging experience with science. We believe that this environment enriches lives and inspires people. In this presentation we will talk about the nuts and bolts that make this model work, how the project got started, and the resources that keep it going. We will talk about the advantages of being a grassroots and community-based organization, and how programs like this can best interface with universities. We will explain the benefits of focusing on direct interactions and why our model avoids ``teaching'' physics content with words. Situating our approach within a body of research on the value of informal science we will discuss our success in capturing and engaging our audience. By the end of this presentation we hope to broaden your perception of what makes a successful outreach program and encourage you to value and support alternative outreach models such as this one. In Collaboration with: Eva Luna, Cornell University; Erik Herman, Cornell University; Christopher Bell, Ithaca City School District.

Operation strategy for grid-tied DC-coupling power converter interface integrating wind/solar/battery

NASA Astrophysics Data System (ADS)

Jou, H. L.; Wu, J. C.; Lin, J. H.; Su, W. N.; Wu, T. S.; Lin, Y. T.

2017-11-01

The operation strategy for a small-capacity grid-tied DC-coupling power converter interface (GDPCI) integrating wind energy, solar energy and battery energy storage is proposed. The GDPCI is composed of a wind generator, a solar module set a battery bank, a boost DC-DC power converter (DDPC), a bidirectional DDPC power converter, an AC-DC power converter (ADPC) and a five-level DC-AC inverter (DAI). A solar module set, a wind generator and a battery bank are coupled to the common DC bus through the boost DDPC, the ADPC and the bidirectional DDPC, respectively. For verifying the performance of the GDPCI under different operation modes, computer simulation is carried out by PSIM.

Flight Computer Design for the Space Technology 5 (ST-5) Mission

NASA Technical Reports Server (NTRS)

Speer, David; Jackson, George; Raphael, Dave; Day, John H. (Technical Monitor)

2001-01-01

As part of NASA's New Millennium Program, the Space Technology 5 mission will validate a variety of technologies for nano-satellite and constellation mission applications. Included are: a miniaturized and low power X-band transponder, a constellation communication and navigation transceiver, a cold gas micro-thruster, two different variable emittance (thermal) controllers, flex cables for solar array power collection, autonomous groundbased constellation management tools, and a new CMOS ultra low-power, radiation-tolerant, +0.5 volt logic technology. The ST-5 focus is on small and low-power. A single-processor, multi-function flight computer will implement direct digital and analog interfaces to all of the other spacecraft subsystems and components. There will not be a distributed data system that uses a standardized serial bus such as MIL-STD-1553 or MIL-STD-1773. The flight software running on the single processor will be responsible for all real-time processing associated with: guidance, navigation and control, command and data handling (C&DH) including uplink/downlink, power switching and battery charge management, science data analysis and storage, intra-constellation communications, and housekeeping data collection and logging. As a nanosatellite trail-blazer for future constellations of up to 100 separate space vehicles, ST-5 will demonstrate a compact (single board), low power (5.5 watts) solution to the data acquisition, control, communications, processing and storage requirements that have traditionally required an entire network of separate circuit boards and/or avionics boxes. In addition to the New Millennium technologies, other major spacecraft subsystems include the power system electronics, a lithium-ion battery, triple-junction solar cell arrays, a science-grade magnetometer, a miniature spinning sun sensor, and a propulsion system.

Development of the Self-Powered Extravehicular Mobility Unit Extravehicular Activity Data Recorder

NASA Technical Reports Server (NTRS)

Bernard, Craig; Hill, Terry R.; Murray, Sean; Wichowski, Robert; Rosenbush, David

2012-01-01

The Self-Powered Extravehicular Mobility Unit (EMU) Extravehicular Activity (EVA) Data Recorder (SPEEDR) is a field-programmable gate array (FPGA)-based device designed to collect high-rate EMU Primary Life Support Subsystem (PLSS) data for download at a later time. During EVA, the existing EMU PLSS data downlink capability is one data packet every 2 minutes and is subject to bad packets or loss of signal. Higher-rate PLSS data is generated by the Enhanced Caution and Warning System but is not normally captured or distributed. Access to higher-rate data will increase the capability of EMU anomaly resolution team to pinpoint issues remotely, saving crew time by reducing required call-down Q&A and on-orbit diagnostic activities. With no Space Shuttle flights post Fiscal Year 2011 (FY11), and potentially limited down-mass capability, the ISS crew and ground support personnel will have to be capable of on-orbit operations to maintain, diagnose, repair, and return to service EMU hardware, possibly through 2028. Collecting high-rate EMU PLSS data during both intravehicular activity (IVA) and EVA operations will provide trending analysis for life extension and/or predictive performance. The SPEEDR concept has generated interest as a tool/technology that could be used for other International Space Station subsystems or future exploration-class space suits where hardware reliability/availability is critical and low/variable bandwidth may require store then forward methodology. Preliminary work in FY11 produced a functional prototype consisting of an FPGA evaluation board, custom memory/interface circuit board, and custom software. The SPEEDR concept includes a stand-alone battery that is recharged by a computer Universal Serial Bus (USB) port while data are being downloaded.

High-Speed Edge-Detecting Line Scan Smart Camera

NASA Technical Reports Server (NTRS)

Prokop, Norman F.

2012-01-01

A high-speed edge-detecting line scan smart camera was developed. The camera is designed to operate as a component in a NASA Glenn Research Center developed inlet shock detection system. The inlet shock is detected by projecting a laser sheet through the airflow. The shock within the airflow is the densest part and refracts the laser sheet the most in its vicinity, leaving a dark spot or shadowgraph. These spots show up as a dip or negative peak within the pixel intensity profile of an image of the projected laser sheet. The smart camera acquires and processes in real-time the linear image containing the shock shadowgraph and outputting the shock location. Previously a high-speed camera and personal computer would perform the image capture and processing to determine the shock location. This innovation consists of a linear image sensor, analog signal processing circuit, and a digital circuit that provides a numerical digital output of the shock or negative edge location. The smart camera is capable of capturing and processing linear images at over 1,000 frames per second. The edges are identified as numeric pixel values within the linear array of pixels, and the edge location information can be sent out from the circuit in a variety of ways, such as by using a microcontroller and onboard or external digital interface to include serial data such as RS-232/485, USB, Ethernet, or CAN BUS; parallel digital data; or an analog signal. The smart camera system can be integrated into a small package with a relatively small number of parts, reducing size and increasing reliability over the previous imaging system..

Development of the ISS EMU SPEEDR

NASA Technical Reports Server (NTRS)

Bernard. Craig; Hill, Terry R.

2011-01-01

The Self Powered EVA EMU Data Recorder (SPEEDR) is an FPGA (Field-programmable gate array) based device designed to collect high-rate EMU (Extravehicular Mobility Unit) PLSS (Primary Life Support Subsystem) data for download at a later time. The existing EMU PLSS data down-link capability during EVA is one data packet every 2 minutes and is subject to bad packets or loss of signal. High-rate PLSS data is generated by the ECWS (Enhanced Caution and Warning System) but is not normally captured or distributed. Access to high-rate data will increase the capability of EMU anomaly resolution team to pinpoint issues remotely, saving crew time by reducing required call-down Q&A and on-orbit diagnostic activities. With no Shuttle flights post FY11, and potentially limited down-mass capability, the ISS crew and ground support personnel will have to be capable of on-orbit operations to maintain, diagnose, repair, and return to service EMU hardware, possibly through 2028. Collecting high-rate EMU PLSS data during both IVA (Intravehicular Activity) and EVA (Extravehicular Activity) operations will provide trending analysis for life extension and/or predictive performance. The SPEEDR concept has generated interest as a tool/technology that could be used for other ISS subsystems or future exploration-class space suits where hardware reliability/availability is critical and low/variable bandwidth may require "store then forward" methodology. Preliminary work in FY11 produced a functional prototype consisting of an FPGA evaluation board, custom memory/interface circuit board, and custom software. The SPEEDR concept includes a stand-alone battery that is recharged by a computer USB (Universal Serial Bus) port while data is being downloaded.

Design and development of an automated, portable and handheld tablet personal computer-based data acquisition system for monitoring electromyography signals during rehabilitation.

PubMed

Ahamed, Nizam U; Sundaraj, Kenneth; Poo, Tarn S

2013-03-01

This article describes the design of a robust, inexpensive, easy-to-use, small, and portable online electromyography acquisition system for monitoring electromyography signals during rehabilitation. This single-channel (one-muscle) system was connected via the universal serial bus port to a programmable Windows operating system handheld tablet personal computer for storage and analysis of the data by the end user. The raw electromyography signals were amplified in order to convert them to an observable scale. The inherent noise of 50 Hz (Malaysia) from power lines electromagnetic interference was then eliminated using a single-hybrid IC notch filter. These signals were sampled by a signal processing module and converted into 24-bit digital data. An algorithm was developed and programmed to transmit the digital data to the computer, where it was reassembled and displayed in the computer using software. Finally, the following device was furnished with the graphical user interface to display the online muscle strength streaming signal in a handheld tablet personal computer. This battery-operated system was tested on the biceps brachii muscles of 20 healthy subjects, and the results were compared to those obtained with a commercial single-channel (one-muscle) electromyography acquisition system. The results obtained using the developed device when compared to those obtained from a commercially available physiological signal monitoring system for activities involving muscle contractions were found to be comparable (the comparison of various statistical parameters) between male and female subjects. In addition, the key advantage of this developed system over the conventional desktop personal computer-based acquisition systems is its portability due to the use of a tablet personal computer in which the results are accessible graphically as well as stored in text (comma-separated value) form.

A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities.

PubMed

Jafari, Ali; Buswell, Nathanael; Ghovanloo, Maysam; Mohsenin, Tinoosh

2018-02-01

This paper presents a low-power stand-alone tongue drive system (sTDS) used for individuals with severe disabilities to potentially control their environment such as computer, smartphone, and wheelchair using their voluntary tongue movements. A low-power local processor is proposed, which can perform signal processing to convert raw magnetic sensor signals to user-defined commands, on the sTDS wearable headset, rather than sending all raw data out to a PC or smartphone. The proposed sTDS significantly reduces the transmitter power consumption and subsequently increases the battery life. Assuming the sTDS user issues one command every 20 ms, the proposed local processor reduces the data volume that needs to be wirelessly transmitted by a factor of 64, from 9.6 to 0.15 kb/s. The proposed processor consists of three main blocks: serial peripheral interface bus for receiving raw data from magnetic sensors, external magnetic interference attenuation to attenuate external magnetic field from the raw magnetic signal, and a machine learning classifier for command detection. A proof-of-concept prototype sTDS has been implemented with a low-power IGLOO-nano field programmable gate array (FPGA), bluetooth low energy, battery and magnetic sensors on a headset, and tested. At clock frequency of 20 MHz, the processor takes 6.6 s and consumes 27 nJ for detecting a command with a detection accuracy of 96.9%. To further reduce power consumption, an application-specified integrated circuit processor for the sTDS is implemented at the postlayout level in 65-nm CMOS technology with 1-V power supply, and it consumes 0.43 mW, which is 10 lower than FPGA power consumption and occupies an area of only 0.016 mm.

Design of a portable, intrinsically safe multichannel acquisition system for high-resolution, real-time processing HD-sEMG.

PubMed

Barone, Umberto; Merletti, Roberto

2013-08-01

A compact and portable system for real-time, multichannel, HD-sEMG acquisition is presented. The device is based on a modular, multiboard approach for scalability and to optimize power consumption for battery operating mode. The proposed modular approach allows us to configure the number of sEMG channels from 64 to 424. A plastic-optical-fiber-based 10/100 Ethernet link is implemented on a field-programmable gate array (FPGA)-based board for real-time, safety data transmission toward a personal computer or laptop for data storage and offline analysis. The high-performance A/D conversion stage, based on 24-bit ADC, allows us to automatically serialize the samples and transmits them on a single SPI bus connecting a sequence of up to 14 ADC chips in chain mode. The prototype is configured to work with 64 channels and a sample frequency of 2.441 ksps (derived from 25-MHz clock source), corresponding to a real data throughput of 3 Mbps. The prototype was assembled to demonstrate the available features (e.g., scalability) and evaluate the expected performances. The analog front end board could be dynamically configured to acquire sEMG signals in monopolar or single differential mode by means of FPGA I/O interface. The system can acquire continuously 64 channels for up to 5 h with a lightweight battery pack of 7.5 Vdc/2200 mAh. A PC-based application was also developed, by means of the open source Qt Development Kit from Nokia, for prototype characterization, sEMG measurements, and real-time visualization of 2-D maps.

Webcam autofocus mechanism used as a delay line for the characterization of femtosecond pulses

DOE Office of Scientific and Technical Information (OSTI.GOV)

Castro-Marín, Pablo; Kapellmann-Zafra, Gabriel; Garduño-Mejía, Jesús, E-mail: jesus.garduno@ccadet.unam.mx

2015-08-15

In this work, we present an electromagnetic focusing mechanism (EFM), from a commercial webcam, implemented as a delay line of a femtosecond laser pulse characterization system. The characterization system consists on a second order autocorrelator based on a two-photon-absorption detection. The results presented here were performed for two different home-made femtosecond oscillators: Ti:sapph @ 820 nm and highly chirped pulses generated with an Erbium Doped Fiber @ 1550 nm. The EFM applied as a delay line represents an excellent alternative due its performance in terms of stability, resolution, and long scan range up to 3 ps. Due its low powermore » consumption, the device can be connected through the Universal Serial Bus (USB) port. Details of components, schematics of electronic controls, and detection systems are presented.« less

A model of serial order problems in fluent, stuttered and agrammatic speech.

PubMed

Howell, Peter

2007-10-01

Many models of speech production have attempted to explain dysfluent speech. Most models assume that the disruptions that occur when speech is dysfluent arise because the speakers make errors while planning an utterance. In this contribution, a model of the serial order of speech is described that does not make this assumption. It involves the coordination or 'interlocking' of linguistic planning and execution stages at the language-speech interface. The model is examined to determine whether it can distinguish two forms of dysfluent speech (stuttered and agrammatic speech) that are characterized by iteration and omission of whole words and parts of words.

Galileo spacecraft power management and distribution system

NASA Technical Reports Server (NTRS)

Detwiler, R. C.; Smith, R. L.

1990-01-01

The Galileo PMAD (power management and distribution system) is described, and the design drivers that established the final as-built hardware are discussed. The spacecraft is powered by two general-purpose heat-source-radioisotope thermoelectric generators. Power bus regulation is provided by a shunt regulator. Galileo PMAD distributes a 570-W beginning of mission (BOM) power source to a user complement of some 137 load elements. Extensive use of pyrotechnics requires two pyro switching subassemblies. They initiate 148 squibs which operate the 47 pyro devices on the spacecraft. Detection and correction of faults in the Galileo PMAD is an autonomous feature dictated by requirements for long life and reliability in the absence of ground-based support. Volatile computer memories in the spacecraft command and data system and attitude control system require a continuous source of backup power during all anticipated power bus fault scenarios. Power for the Jupiter Probe is conditioned, isolated, and controlled by a Probe interface subassembly. Flight performance of the spacecraft and the PMAD has been successful to date, with no major anomalies.

Massively parallel processor computer

NASA Technical Reports Server (NTRS)

Fung, L. W. (Inventor)

1983-01-01

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Solid state power controllers

NASA Technical Reports Server (NTRS)

Gibbs, R. S.

1974-01-01

Solid state power controllers (SSPC's) are to be considered for use as replacements of electromechanical relays and circuit breakers in future spacecraft and aircraft. They satisfy the combined function of both the relay and circuit breaker and can be remotely controlled by small signals, typically 10 mA, 5 to 28 v(dc). They have the advantage over conventional relay/circuit breaker systems in that they can be located near the utilization equipment and the primary ac or dc bus. The low level control, trip indication and status signals can be circuited by small gauge wire for control, computer interface, logic, electrical multiplexing, onboard testing, power management, and distribution purposes. This results in increased system versatility at appreciable weight saving and increased reliability. Conventional systems require the heavy gage load wiring and the control wiring to be routed from the bus to the load to other remote relay contacts, switches, sensors, etc. and to the circuit breaker located in the flight engineer's compartment for purposes of manual reset.

Systems definition summary. Earth Observatory Satellite system definition study (EOS)

NASA Technical Reports Server (NTRS)

1974-01-01

A standard spacecraft bus for performing a variety of earth orbit missions in the late 1970's and 1980's is defined. Emphasis is placed on a low-cost, multimission capability, benefitting from the space shuttle system. The subjects considered are as follows: (1) performance requirements, (2) internal interfaces, (3) redundancy and reliability, (4) communications and data handling module design, (5) payload data handling, (6) application of the modular design to various missions, and (7) the verification concept.

Small Business Innovation Research (SBIR) Program, FY 1994. Program Solicitation 94.1, Closing Date: 14 January 1994

DTIC Science & Technology

1994-01-01

is to design and develop a diode laser and ssociated driver circuitry with i•eh peak power, high pulse repetition frequency (PRF), and good beam...Computer modeling tools shall be used to design and optimize breadboard model of a multi-terminal high speed ring bus for flight critical applications... design , fabricate, and test a fiber optic interface device which will improve coupling of high energy, pulsed lasers into commercial fiber optics at a

Auxiliary engine digital interface unit (DIU)

NASA Technical Reports Server (NTRS)

1972-01-01

This auxiliary propulsion engine digital unit controls both the valving of the fuel and oxidizer to the engine combustion chamber and the ignition spark required for timely and efficient engine burns. In addition to this basic function, the unit is designed to manage it's own redundancy such that it is still operational after two hard circuit failures. It communicates to the data bus system several selected information points relating to the operational status of the electronics as well as the engine fuel and burning processes.

Implementing a bubble memory hierarchy system

NASA Technical Reports Server (NTRS)

Segura, R.; Nichols, C. D.

1979-01-01

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

NASA Technical Reports Server (NTRS)

Bronstein, L.; Kawamoto, Y.; Ribarich, J. J.; Scope, J. R.; Forman, B. J.; Bergman, S. G.; Reisenfeld, S.

1981-01-01

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented.

Airborne Electro-Mechanical Actuator Test Stand for Development of Prognostic Health Management Systems

DTIC Science & Technology

2010-10-01

based on a pre-defined UH-60 data format, then also computes the load and position profile information. File Profile Interface In order to test the...of the data set. Figure 13 shows a typical motion profile executed over a period of about twenty minutes. Figure 14 shows the desired ( computed ...flight. The stand is connected to the aircraft data bus and the motion profiles for the test actuators, as well as the load applied to them, are

A Signal Averager Interface between a Biomation 6500 Transient Recorder and a LSI-11 Microcomputer.

DTIC Science & Technology

1980-06-01

decode the proper bus synchronizing signals. SA data lines 1 and 2 are decoded to produce SELO L - SEL4 L which select one of four SA registers. The...J42 A > SACCI..N.. 31 is41 4--.----(~~#I)I MMELYH-[@- T~. S5 46NI INI 404 II CSkN M.3 > ____ ____47 INWO L 3CSRRD L U SEL4 L MRPLY L t5CSRWHB H OUTHB L

(Meta)Search like Google

ERIC Educational Resources Information Center

Rochkind, Jonathan

2007-01-01

The ability to search and receive results in more than one database through a single interface--or metasearch--is something many users want. Google Scholar--the search engine of specifically scholarly content--and library metasearch products like Ex Libris's MetaLib, Serials Solution's Central Search, WebFeat, and products based on MuseGlobal used…

Brain-Computer Interface application: auditory serial interface to control a two-class motor-imagery-based wheelchair.

PubMed

Ron-Angevin, Ricardo; Velasco-Álvarez, Francisco; Fernández-Rodríguez, Álvaro; Díaz-Estrella, Antonio; Blanca-Mena, María José; Vizcaíno-Martín, Francisco Javier

2017-05-30

Certain diseases affect brain areas that control the movements of the patients' body, thereby limiting their autonomy and communication capacity. Research in the field of Brain-Computer Interfaces aims to provide patients with an alternative communication channel not based on muscular activity, but on the processing of brain signals. Through these systems, subjects can control external devices such as spellers to communicate, robotic prostheses to restore limb movements, or domotic systems. The present work focus on the non-muscular control of a robotic wheelchair. A proposal to control a wheelchair through a Brain-Computer Interface based on the discrimination of only two mental tasks is presented in this study. The wheelchair displacement is performed with discrete movements. The control signals used are sensorimotor rhythms modulated through a right-hand motor imagery task or mental idle state. The peculiarity of the control system is that it is based on a serial auditory interface that provides the user with four navigation commands. The use of two mental tasks to select commands may facilitate control and reduce error rates compared to other endogenous control systems for wheelchairs. Seventeen subjects initially participated in the study; nine of them completed the three sessions of the proposed protocol. After the first calibration session, seven subjects were discarded due to a low control of their electroencephalographic signals; nine out of ten subjects controlled a virtual wheelchair during the second session; these same nine subjects achieved a medium accuracy level above 0.83 on the real wheelchair control session. The results suggest that more extensive training with the proposed control system can be an effective and safe option that will allow the displacement of a wheelchair in a controlled environment for potential users suffering from some types of motor neuron diseases.

Formed photovoltaic module busbars

DOEpatents

Rose, Douglas; Daroczi, Shan; Phu, Thomas

2015-11-10

A cell connection piece for a photovoltaic module is disclosed herein. The cell connection piece includes an interconnect bus, a plurality of bus tabs unitarily formed with the interconnect bus, and a terminal bus coupled with the interconnect bus. The plurality of bus tabs extend from the interconnect bus. The terminal bus includes a non-linear portion.

Bermuda Triangle: a subsystem of the 168/E interfacing scheme used by Group B at SLAC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oxoby, G.J.; Levinson, L.J.; Trang, Q.H.

1979-12-01

The Bermuda Triangle system is a method of interfacing several 168/E microprocessors to a central system for control of the processors and overlaying their memories. The system is a three-way interface with I/O ports to a large buffer memory, a PDP11 Unibus and a bus to the 168/E processors. Data may be transferred bidirectionally between any two ports. Two Bermuda Triangles are used, one for the program memory and one for the data memory. The program buffer memory stores the overlay programs for the 168/E, and the data buffer memory, the incoming raw data, the data portion of the overlays,more » and the outgoing processed events. This buffering is necessary since the memories of 168/E microprocessors are small compared to the main program and the amount of data being processed. The link to the computer facility is via a Unibus to IBM channel interface. A PDP11/04 controls the data flow. 7 figures, 4 tables. (RWR)« less

Thyra Abstract Interface Package

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bartlett, Roscoe A.

2005-09-01

Thrya primarily defines a set of abstract C++ class interfaces needed for the development of abstract numerical atgorithms (ANAs) such as iterative linear solvers, transient solvers all the way up to optimization. At the foundation of these interfaces are abstract C++ classes for vectors, vector spaces, linear operators and multi-vectors. Also included in the Thyra package is C++ code for creating concrete vector, vector space, linear operator, and multi-vector subclasses as well as other utilities to aid in the development of ANAs. Currently, very general and efficient concrete subclass implementations exist for serial and SPMD in-core vectors and multi-vectors. Codemore » also currently exists for testing objects and providing composite objects such as product vectors.« less

Continued Development of a Universal Network Interface Device Using the Intel 8086 and 8089 16-Bit Microprocessors.

DTIC Science & Technology

1983-12-15

7 "AD-RI38 iig CONTINUED DE VELOPMlENT OF UNIERSL NETWORK INTERFCE 1/2 DEVICE USING THE I..(U) AIR FORCE INST OF TECHD-F13 ill WRIGHT PATTERSON AFB...Protocols," IEEE Transactions on Communications, COM-28(4):433-44 (April 1980). 3. Borgsmiller, Michael. "The Serial Communications Interface Board...Interconnections," IEEE Transactions on Communications, COM-28(4): 425- 432, (April 1980). 4. I L Appendix A UNID II Data Flow Diagrams (Ref 10:26-34) This

Advancing Small Satellite Electronics Heritage for Microfluidic Biological Experiments

NASA Technical Reports Server (NTRS)

White, Bruce; Mazmanian, Edward; Tapio, Eric

2016-01-01

DLR's Eu:CROPIS (Euglena and Combined Regenerative Organic-Food Production in Space) mission, launching in 2017, will carry multiple biological payloads into a sun-synchronous orbit, including NASA Ames' PowerCell experiment. PowerCell will attempt to characterize the viability of synthetic biology at micro-g, Lunar, and Martian gravity levels. PowerCell experiment requirements demand an electronic system similar to previous microfluidic biology payloads, but with an expanded feature set. As such, the system was based on PharmaSat (Diaz-Aguado et al. 2009), a previous successful biology payload from NASA Ames, and improved upon. Newer, more miniaturized electronics allow for greater capability with a lower part count and smaller size. Two identical PowerCell enclosures will fly. Each enclosure contains two separate and identical experiments with a 48-segment optical density measurement system, grow light system, microfluidic system for nutrient delivery and waste flushing, plus thermal control and environmental sensing/housekeeping including temperature, pressure, humidity, and acceleration. Electronics consist of a single Master PCB that interfaces to the spacecraft bus and regulates power and communication, plus LED, Detector, and Valve Manifold PCBs for each experiment. To facilitate ease of reuse on future missions, experiment electronics were designed to be compatible with a standard 3U small sat form factor and power bus, or to interface with a Master power/comm PCB for use in a larger satellite as in the case of PowerCell's flight on Eu:CROPIS.

GSFC Cutting Edge Avionics Technologies for Spacecraft

NASA Technical Reports Server (NTRS)

Luers, Philip J.; Culver, Harry L.; Plante, Jeannette

1998-01-01

With the launch of NASA's first fiber optic bus on SAMPEX in 1992, GSFC has ushered in an era of new technology development and insertion into flight programs. Predating such programs the Lewis and Clark missions and the New Millenium Program, GSFC has spearheaded the drive to use cutting edge technologies on spacecraft for three reasons: to enable next generation Space and Earth Science, to shorten spacecraft development schedules, and to reduce the cost of NASA missions. The technologies developed have addressed three focus areas: standard interface components, high performance processing, and high-density packaging techniques enabling lower cost systems. To realize the benefits of standard interface components GSFC has developed and utilized radiation hardened/tolerant devices such as PCI target ASICs, Parallel Fiber Optic Data Bus terminals, MIL-STD-1773 and AS1773 transceivers, and Essential Services Node. High performance processing has been the focus of the Mongoose I and Mongoose V rad-hard 32-bit processor programs as well as the SMEX-Lite Computation Hub. High-density packaging techniques have resulted in 3-D stack DRAM packages and Chip-On-Board processes. Lower cost systems have been demonstrated by judiciously using all of our technology developments to enable "plug and play" scalable architectures. The paper will present a survey of development and insertion experiences for the above technologies, as well as future plans to enable more "better, faster, cheaper" spacecraft. Details of ongoing GSFC programs such as Ultra-Low Power electronics, Rad-Hard FPGAs, PCI master ASICs, and Next Generation Mongoose processors.

Total Library Computerization, Version 2: A DOS-Based Program from On Point, Inc., for Managing Small to Midsized Libraries.

ERIC Educational Resources Information Center

Combs, Joseph, Jr.

1995-01-01

Reviews the Total Library Computerization program, which can be used to manage small to midsized libraries. Discusses costs; operating system requirements; security features; user-interface styles; and system modules including online cataloging, circulation, serials control, acquisitions, authorities control, and interlibrary loan. (Author/JMV)

Creating Complex Repository Collections, Such as Journals, with Manakin

ERIC Educational Resources Information Center

Koenig, Jack; Mikeal, Adam

2010-01-01

Purpose: The purpose of this paper is to report on a devised method of collection organisation within a DSpace repository using a Manakin theme and descriptive metadata. Design/methodology/approach: Using a Manakin theme, a user interface for a repository collection containing the contents of a serial was created to divide the collection into…

Constructing a LabVIEW-Controlled High-Performance Liquid Chromatography (HPLC) System: An Undergraduate Instrumental Methods Exercise

ERIC Educational Resources Information Center

Smith, Eugene T.; Hill, Marc

2011-01-01

In this laboratory exercise, students develop a LabVIEW-controlled high-performance liquid chromatography system utilizing a data acquisition device, two pumps, a detector, and fraction collector. The programming experience involves a variety of methods for interface communication, including serial control, analog-to-digital conversion, and…

Design and construction of a desktop AC susceptometer using an Arduino and a Bluetooth for serial interface

NASA Astrophysics Data System (ADS)

Pérez, Israel; Ángel Hernández Cuevas, José; Trinidad Elizalde Galindo, José

2018-05-01

We designed and developed a desktop AC susceptometer for the characterization of materials. The system consists of a lock-in amplifier, an AC function generator, a couple of coils, a sample holder, a computer system with a designed software in freeware C++ code, and an Arduino card coupled to a Bluetooth module. The Arduino/Bluetooth serial interface allows the user to have a connection to almost any computer and thus avoids the problem of connectivity between the computer and the peripherals, such as the lock-in amplifier and the function generator. The Bluetooth transmitter/receiver used is a commercial device which is robust and fast. These new features reduce the size and increase the versatility of the susceptometer, for it can be used with a simple laptop. To test our instrument, we performed measurements on magnetic materials and show that the system is reliable at both room temperature and cryogenic temperatures (77 K). The instrument is suitable for any physics or engineering laboratory either for research or academic purposes.

Acquisition of Real-Time Operation Analytics for an Automated Serial Sectioning System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Madison, Jonathan D.; Underwood, O. D.; Poulter, Gregory A.

Mechanical serial sectioning is a highly repetitive technique employed in metallography for the rendering of 3D reconstructions of microstructure. While alternate techniques such as ultrasonic detection, micro-computed tomography, and focused ion beam milling have progressed much in recent years, few alternatives provide equivalent opportunities for comparatively high resolutions over significantly sized cross-sectional areas and volumes. To that end, the introduction of automated serial sectioning systems has greatly heightened repeatability and increased data collection rates while diminishing opportunity for mishandling and other user-introduced errors. Unfortunately, even among current, state-of-the-art automated serial sectioning systems, challenges in data collection have not been fullymore » eradicated. Therefore, this paper highlights two specific advances to assist in this area; a non-contact laser triangulation method for assessment of material removal rates and a newly developed graphical user interface providing real-time monitoring of experimental progress. Furthermore, both are shown to be helpful in the rapid identification of anomalies and interruptions, while also providing comparable and less error-prone measures of removal rate over the course of these long-term, challenging, and innately destructive characterization experiments.« less

Acquisition of Real-Time Operation Analytics for an Automated Serial Sectioning System

DOE PAGES

Madison, Jonathan D.; Underwood, O. D.; Poulter, Gregory A.; ...

2017-03-22

Mechanical serial sectioning is a highly repetitive technique employed in metallography for the rendering of 3D reconstructions of microstructure. While alternate techniques such as ultrasonic detection, micro-computed tomography, and focused ion beam milling have progressed much in recent years, few alternatives provide equivalent opportunities for comparatively high resolutions over significantly sized cross-sectional areas and volumes. To that end, the introduction of automated serial sectioning systems has greatly heightened repeatability and increased data collection rates while diminishing opportunity for mishandling and other user-introduced errors. Unfortunately, even among current, state-of-the-art automated serial sectioning systems, challenges in data collection have not been fullymore » eradicated. Therefore, this paper highlights two specific advances to assist in this area; a non-contact laser triangulation method for assessment of material removal rates and a newly developed graphical user interface providing real-time monitoring of experimental progress. Furthermore, both are shown to be helpful in the rapid identification of anomalies and interruptions, while also providing comparable and less error-prone measures of removal rate over the course of these long-term, challenging, and innately destructive characterization experiments.« less

Design of video interface conversion system based on FPGA

NASA Astrophysics Data System (ADS)

Zhao, Heng; Wang, Xiang-jun

2014-11-01

This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor.The current experiment shows that it can achieve high-quality video conversion with minimum board size.

Adding HDLC Framing to CCSDS Recommendations

NASA Technical Reports Server (NTRS)

Hogie, Keith; Criscuolo, Ed; Parise, Ron

2004-01-01

Current Space IP missions use High-Level Data Link Control (HDLC) framing to provide standard serial link interfaces over a space link. HDLC is the standard framing technique used by all routers over clock and data serial lines and is also the basic framing used in all Frame Relay services which are widely deployed in national and international communication networks. In late 2003 a presentation was made to CCSDS committees to initiate discussion on including HDLC in the CCSDS recommendations for space systems. This presentation will summarize the differences between variable length HDLC frames and fixed length CCSDS frames. It will also discuss where and how HDLC framing would fit into the overall CCSDS structures.

Access to CAMAC from VxWorks and UNIX in DART

DOE Office of Scientific and Technical Information (OSTI.GOV)

Streets, J.; Meadows, J.; Moore, C.

1996-02-01

All High Energy Physics experiments at Fermilab include CAMAC modules which need to be read out for each triggered event. There is also a need to access CAMAC modules for control and monitoring of the experiment. As part of the DART Project the authors have developed a package of software for CAMAC access from UNIX and VxWorks platforms, with support for several hardware interfaces. The authors report on developments for the CES CBD8210 VME to parallel CAMAC, the Hytec VSD2992 VME to serial CAMAC and Jorway 411S SCSI to parallel and serial CAMAC branch drivers, and give a summary ofmore » the timings obtained.« less

Development of a Commercially Viable, Modular Autonomous Robotic Systems for Converting any Vehicle to Autonomous Control

NASA Technical Reports Server (NTRS)

Parish, David W.; Grabbe, Robert D.; Marzwell, Neville I.

1994-01-01

A Modular Autonomous Robotic System (MARS), consisting of a modular autonomous vehicle control system that can be retrofit on to any vehicle to convert it to autonomous control and support a modular payload for multiple applications is being developed. The MARS design is scalable, reconfigurable, and cost effective due to the use of modern open system architecture design methodologies, including serial control bus technology to simplify system wiring and enhance scalability. The design is augmented with modular, object oriented (C++) software implementing a hierarchy of five levels of control including teleoperated, continuous guidepath following, periodic guidepath following, absolute position autonomous navigation, and relative position autonomous navigation. The present effort is focused on producing a system that is commercially viable for routine autonomous patrolling of known, semistructured environments, like environmental monitoring of chemical and petroleum refineries, exterior physical security and surveillance, perimeter patrolling, and intrafacility transport applications.

Partitioning problems in parallel, pipelined and distributed computing

NASA Technical Reports Server (NTRS)

Bokhari, S.

1985-01-01

The problem of optimally assigning the modules of a parallel program over the processors of a multiple computer system is addressed. A Sum-Bottleneck path algorithm is developed that permits the efficient solution of many variants of this problem under some constraints on the structure of the partitions. In particular, the following problems are solved optimally for a single-host, multiple satellite system: partitioning multiple chain structured parallel programs, multiple arbitrarily structured serial programs and single tree structured parallel programs. In addition, the problems of partitioning chain structured parallel programs across chain connected systems and across shared memory (or shared bus) systems are also solved under certain constraints. All solutions for parallel programs are equally applicable to pipelined programs. These results extend prior research in this area by explicitly taking concurrency into account and permit the efficient utilization of multiple computer architectures for a wide range of problems of practical interest.

WinTICS-24 --- A Telescope Control Interface for MS Windows

NASA Astrophysics Data System (ADS)

Hawkins, R. Lee

1995-12-01

WinTICS-24 is a telescope control system interface and observing assistant written in Visual Basic for MS Windows. It provides the ability to control a telescope and up to 3 other instruments via the serial ports on an IBM-PC compatible computer, all from one consistent user interface. In addition to telescope control, WinTICS contains an observing logbook, trouble log (which can automatically email its entries to a responsible person), lunar phase display, object database (which allows the observer to type in the name of an object and automatically slew to it), a time of minimum calculator for eclipsing binary stars, and an interface to the Guide CD-ROM for bringing up finder charts of the current telescope coordinates. Currently WinTICS supports control of DFM telescopes, but is easily adaptable to other telescopes and instrumentation.

Packet based serial link realized in FPGA dedicated for high resolution infrared image transmission

NASA Astrophysics Data System (ADS)

Bieszczad, Grzegorz

2015-05-01

In article the external digital interface specially designed for thermographic camera built in Military University of Technology is described. The aim of article is to illustrate challenges encountered during design process of thermal vision camera especially related to infrared data processing and transmission. Article explains main requirements for interface to transfer Infra-Red or Video digital data and describes the solution which we elaborated based on Low Voltage Differential Signaling (LVDS) physical layer and signaling scheme. Elaborated link for image transmission is built using FPGA integrated circuit with built-in high speed serial transceivers achieving up to 2500Gbps throughput. Image transmission is realized using proprietary packet protocol. Transmission protocol engine was described in VHDL language and tested in FPGA hardware. The link is able to transmit 1280x1024@60Hz 24bit video data using one signal pair. Link was tested to transmit thermal-vision camera picture to remote monitor. Construction of dedicated video link allows to reduce power consumption compared to solutions with ASIC based encoders and decoders realizing video links like DVI or packed based Display Port, with simultaneous reduction of wires needed to establish link to one pair. Article describes functions of modules integrated in FPGA design realizing several functions like: synchronization to video source, video stream packeting, interfacing transceiver module and dynamic clock generation for video standard conversion.

AcquiControl: Seismic Data Logger Control via iPhone

NASA Astrophysics Data System (ADS)

Golden, S.; Horkley, B.

2010-12-01

Seismic stations are often placed in remote areas, accessible only a few times per year. A typical stand-alone seismic station consists of the seismometer and a data logger, which records the data to attached disk drives or flash memory for later collection by a field crew. Even if the station uses telemetry, maintenance visits may be minimized but rarely entirely avoided. During station visits, field personnel use laptops or handheld devices to control the data logger and seismometer, check their status, and adjust their configuration if necessary. The efficiency and reliability of these on-site quality control tasks has a significant impact on the overall performance of seismic field operations. One widespread seismic data logger is the RT130 by REFTEK Inc., which is traditionally controlled through REFTEK proprietary software designed to run on Palm compatible devices. While this software functions well, compatible Palm handhelds went out of production and are getting hard to find. Also we felt, that its user interface still offered room for improvement. Therefore, we developed a new RT130 control application, named AcquiControl, which runs on Apple’s iPhone or iPod Touch, and features a redesigned, user-friendly interface. The Palm handheld communicates with the data logger through a serial cable. While this is technically also possible with the iPhone or iPod Touch, the production and licensing costs for the required custom cable so far kept us from further pursuing this path. Instead, AcquiControl makes use of the wireless networking capabilities inherent to any iPhone or iPod Touch. To wirelessly connect to an RT130 data logger, we use a wireless-to-serial “dongle” manufactured by Serialio.com, which attaches directly to the data logger’s serial port. First experiments with this setup have shown, that it is actually more convenient to use than a directly attached serial cable, especially during less than ideal environmental conditions such as present while working in the rain. AcquiControl offers a third-party alternative to interface with RT130 data loggers in the field. Currently it covers most frequently used capabilities of the older Palm software through equivalent features, with plans to add more as needed. Beyond that, the application could be easily adapted to support other data loggers than the RT130, possibly even by other manufacturers. This would give users a more uniform interface regardless of data logger model, which could become an advantage during mixed-equipment campaigns. Also, the same software could be expanded to allow the direct input of various field notes, which could be downloaded together with automatically logged configuration data to ease the preparation of seismic metadata or the building of a project-central seismic database.

Automatic Parallelization of Numerical Python Applications using the Global Arrays Toolkit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daily, Jeffrey A.; Lewis, Robert R.

2011-11-30

Global Arrays is a software system from Pacific Northwest National Laboratory that enables an efficient, portable, and parallel shared-memory programming interface to manipulate distributed dense arrays. The NumPy module is the de facto standard for numerical calculation in the Python programming language, a language whose use is growing rapidly in the scientific and engineering communities. NumPy provides a powerful N-dimensional array class as well as other scientific computing capabilities. However, like the majority of the core Python modules, NumPy is inherently serial. Using a combination of Global Arrays and NumPy, we have reimplemented NumPy as a distributed drop-in replacement calledmore » Global Arrays in NumPy (GAiN). Serial NumPy applications can become parallel, scalable GAiN applications with only minor source code changes. Scalability studies of several different GAiN applications will be presented showing the utility of developing serial NumPy codes which can later run on more capable clusters or supercomputers.« less

COM-BUS : A Southern California Subscription Bus Service

DOT National Transportation Integrated Search

1977-05-01

The evolution and operations of the COM-BUS Subscription Commuter Bus Service are documented. COM-BUS is a privately owned organization operating at a profit without any form of subsidy. COM-BUS serves approximately 2,000 commuters per day on 47 rout...

49 CFR 605.19 - Approval of school bus operations.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 7 2011-10-01 2011-10-01 false Approval of school bus operations. 605.19 Section... ADMINISTRATION, DEPARTMENT OF TRANSPORTATION SCHOOL BUS OPERATIONS School Bus Agreements § 605.19 Approval of school bus operations. (a) The Administrator will consider the comments filed by private school bus...

49 CFR 605.18 - Comments by private school bus operators.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 7 2011-10-01 2011-10-01 false Comments by private school bus operators. 605.18... ADMINISTRATION, DEPARTMENT OF TRANSPORTATION SCHOOL BUS OPERATIONS School Bus Agreements § 605.18 Comments by private school bus operators. Private school bus operators may file written comments on an applicant's...

49 CFR 605.18 - Comments by private school bus operators.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 7 2010-10-01 2010-10-01 false Comments by private school bus operators. 605.18... ADMINISTRATION, DEPARTMENT OF TRANSPORTATION SCHOOL BUS OPERATIONS School Bus Agreements § 605.18 Comments by private school bus operators. Private school bus operators may file written comments on an applicant's...

49 CFR 605.19 - Approval of school bus operations.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 7 2010-10-01 2010-10-01 false Approval of school bus operations. 605.19 Section... ADMINISTRATION, DEPARTMENT OF TRANSPORTATION SCHOOL BUS OPERATIONS School Bus Agreements § 605.19 Approval of school bus operations. (a) The Administrator will consider the comments filed by private school bus...

Shark: Fast Data Analysis Using Coarse-grained Distributed Memory

DTIC Science & Technology

2013-05-01

Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1.1 Java Objects...often MySQL or Derby) with a namespace for tables, table metadata, and par- tition information. Table data is stored in an HDFS directory, while a...saving time and space for large data sets. This is achieved with support for custom SerDe (serialization/deserialization) java interface implementations

CSI Flight Computer System and experimental test results

NASA Technical Reports Server (NTRS)

Sparks, Dean W., Jr.; Peri, F., Jr.; Schuler, P.

1993-01-01

This paper describes the CSI Computer System (CCS) and the experimental tests performed to validate its functionality. This system is comprised of two major components: the space flight qualified Excitation and Damping Subsystem (EDS) which performs controls calculations; and the Remote Interface Unit (RIU) which is used for data acquisition, transmission, and filtering. The flight-like RIU is the interface between the EDS and the sensors and actuators positioned on the particular structure under control. The EDS and RIU communicate over the MIL-STD-1553B, a space flight qualified bus. To test the CCS under realistic conditions, it was connected to the Phase-0 CSI Evolutionary Model (CEM) at NASA Langley Research Center. The following schematic shows how the CCS is connected to the CEM. Various tests were performed which validated the ability of the system to perform control/structures experiments.

Development of an automatic subsea blowout preventer stack control system using PLC based SCADA.

PubMed

Cai, Baoping; Liu, Yonghong; Liu, Zengkai; Wang, Fei; Tian, Xiaojie; Zhang, Yanzhen

2012-01-01

An extremely reliable remote control system for subsea blowout preventer stack is developed based on the off-the-shelf triple modular redundancy system. To meet a high reliability requirement, various redundancy techniques such as controller redundancy, bus redundancy and network redundancy are used to design the system hardware architecture. The control logic, human-machine interface graphical design and redundant databases are developed by using the off-the-shelf software. A series of experiments were performed in laboratory to test the subsea blowout preventer stack control system. The results showed that the tested subsea blowout preventer functions could be executed successfully. For the faults of programmable logic controllers, discrete input groups and analog input groups, the control system could give correct alarms in the human-machine interface. Copyright © 2011 ISA. Published by Elsevier Ltd. All rights reserved.

The development of an airborne instrumentation computer system for flight test

NASA Technical Reports Server (NTRS)

Bever, G. A.

1984-01-01

Instrumentation interfacing frequently requires the linking of intelligent systems together, as well as requiring the link itself to be intelligent. The airborne instrumentation computer system (AICS) was developed to address this requirement. Its small size, approximately 254 by 133 by 140 mm (10 by 51/4 by 51/2 in), standard bus, and modular board configuration give it the ability to solve instrumentation interfacing and computation problems without forcing a redesign of the entire unit. This system has been used on the F-15 aircraft digital electronic engine control (DEEC) and its follow on engine model derivative (EMD) project and in an OV-1C Mohawk aircraft stall speed warning system. The AICS is presently undergoing configuration for use on an F-104 pace aircraft and on the advanced fighter technology integration (AFTI) F-111 aircraft.

Mid Infrared Instrument cooler subsystem test facility overview

NASA Astrophysics Data System (ADS)

Moore, B.; Zan, J.; Hannah, B.; Chui, T.; Penanen, K.; Weilert, M.

2017-12-01

The Cryocooler for the Mid Infrared Instrument (MIRI) on the James Webb Space Telescope (JWST) provides cooling at 6.2K on the instrument interface. The cooler system design has been incrementally documented in previous publications [1][2][3][4][5]. It has components that traverse three primary thermal regions on JWST: Region 1, approximated by 40K; Region 2, approximated by 100K; and Region 3, which is at the allowable flight temperatures for the spacecraft bus. However, there are several sub-regions that exist in the transition between primary regions and at the heat reject interfaces of the Cooler Compressor Assembly (CCA) and Cooler Control Electronics Assembly (CCEA). The design and performance of the test facility to provide a flight representative thermal environment for acceptance testing and characterization of the complete MIRI cooler subsystem are presented.

``DMS-R, the Brain of the ISS'', 10 Years of Continuous Successful Operation in Space

NASA Astrophysics Data System (ADS)

Wolff, Bernd; Scheffers, Peter

2012-08-01

Space industries on both sides of the Atlantic were faced with a new situation of collaboration in the beginning of the 1990s.In 1995, industrial cooperation between ASTRIUM ST, Bremen and RSC-E, Moscow started aiming the outfitting of the Russian Service Module ZVEZDA for the ISS with computers. The requested equipments had to provide not only redundancy but fault tolerance and high availability. The design and development of two fault tolerant computers, (FTCs) responsible for the telemetry (Telemetry Computer: TC) and the central control (CC), as well as the man machine interface CPC were contracted to ASTRIUM ST, Bremen. The computer system is responsible e.g. for the life support system and the ISS re-boost control.In July 2000, the integration of the Russian Service Module ZVEZDA with Russian ZARYA FGB and American Node 1 bears witness for transatlantic and European cooperation.The Russian Service module ZVEZDA provides several basic functions as Avionics Control, the Environmental Control and Life Support (ECLS) in the ISS and control of the docked Automatic Transfer Vehicle (ATV) which includes re-boost of ISS. If these elementary functions fail or do not work reliable the effects for the ISS will be catastrophic with respect to Safety (manned space) and ISS mission.For that reason the responsible computer system Data Management System - Russia (DMS-R) is also called "The brain of the ISS".The Russian Service module ZVEZDA, including DMS-R, was launched on 12th of July, 2000. DMS-R was operational also during launch and docking.The talk provide information about the definition, design and development of DMS-R, the integration of DMS-R in the Russian Service module and the maintenance of the system in space. Besides the technical aspects are also the German - Russian cooperation an important subject of this speech. An outlook finalises the talk providing further development activities and application of fault tolerant systems.The importance of the DMS-R equipment for the ISS related to availability and reliability is reported in paragraph 1.2, describing a serious incident.The DMS-R architecture, consisting of two fault tolerant computers, their interconnection via MIL 1553 STD Bus and the Control Post Computer (CPC) as man- machine interface is given in figure 1. The main data transfer within the ISS and therefore also the Russian segment is managed by the MIL1553 STD bus. The focus of this script is neither the operational concept nor the fault tolerant design according the Byzantine Theorem, but the architectural embedment. One fault tolerant computer consists out of up to four fault containment regions (FCR), comparing in- and output data and deciding by majority voting whether a faulty FCR has to be isolated. For this purpose all data have to pass the so-called fault management element and are distributed to the other participants in the computer pool (FTC). Each fault containment region is connected to the avionic busses of the vehicle avionics system. In case of a faulty FCR (wrong calculation result was detected by the other FCRs or by build-in self-detection) the dedicated FCR will reset itself or will be reset by the others. The bus controller functions of the isolated FCR will be taken over according to a specific deterministic scheme from another FCR. The FTC data throughput will be maintained, the FTC operation will continue without interruption. Each FCR consists of an application CPU board (ALB), the fault management layer (FML), the avionics bus interface board (AVI) and a power supply (PSU), sharing a VME data bus.The FML is fully transparent, in terms of I/O accessibility, to the application S/W and votes the data autonomously received from the avionics busses and transmitted from the application.

A new bus lane on urban expressway with no-bay bus stop

NASA Astrophysics Data System (ADS)

Tian, Zhao; Jia, Limin

2016-01-01

The sharp increase in residents and vehicles causes heavy traffic pressure in many cities. To ease traffic congestion, it has been the common sense that we should develop public transit system. The priority of the bus appears particularly necessary with the rapid development of the public transport system. The bus lane is an important embodiment of the bus priority. Focusing on the problem of the unreasonable dedicated bus lane (DBL) under the lower ratio of buses, this paper proposed a new bus lane with limited physical length. And this bus lane can reduce the lane-changing conflict caused by the buses and cars running on roads without bus lanes. Based on the cellular automata (CA) traffic flow model and the lane-changing behavior of the vehicle including the optional lane-changing and the mandatory lane-changing, a three-lane traffic model with an isolated no-bay bus stop is proposed. The ordinary three-lane traffic without a bus lane and the cases of traffic with a DBL or the proposed bus lane are simulated, and the comparisons in the form of the fundamental diagrams are made among them. It is shown that the no-bay bus stop can act as a bottleneck on the traffic flow because of the mandatory lane-changing behavior. Under a certain ratio of the bus number to the total vehicles number, (1) the traffic with the proposed bus lane has less lane-changing conflict and can provide higher traffic capacity than the ordinary traffic without a bus lane, (2) compared with the DBL, the proposed bus lane is advantageous in easing congestion on the ordinary lanes when the traffic flow is high and can avoid unreasonable allocation of the road resources.

Development and evaluation of a Fault-Tolerant Multiprocessor (FTMP) computer. Volume 3: FTMP test and evaluation

NASA Technical Reports Server (NTRS)

Lala, J. H.; Smith, T. B., III

1983-01-01

The experimental test and evaluation of the Fault-Tolerant Multiprocessor (FTMP) is described. Major objectives of this exercise include expanding validation envelope, building confidence in the system, revealing any weaknesses in the architectural concepts and in their execution in hardware and software, and in general, stressing the hardware and software. To this end, pin-level faults were injected into one LRU of the FTMP and the FTMP response was measured in terms of fault detection, isolation, and recovery times. A total of 21,055 stuck-at-0, stuck-at-1 and invert-signal faults were injected in the CPU, memory, bus interface circuits, Bus Guardian Units, and voters and error latches. Of these, 17,418 were detected. At least 80 percent of undetected faults are estimated to be on unused pins. The multiprocessor identified all detected faults correctly and recovered successfully in each case. Total recovery time for all faults averaged a little over one second. This can be reduced to half a second by including appropriate self-tests.

Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

PubMed

Dante, V; Del Giudice, P; Mattia, M

2001-01-01

We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

Multibus-based parallel processor for simulation

NASA Technical Reports Server (NTRS)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

The New Payload Handling System for the G erman On- Orbit Verification Satellite TET with the Sensor Bus as Example for Payloads

NASA Astrophysics Data System (ADS)

Heyer, H.-V.; Föckersperger, S.; Lattner, K.; Moldenhauer, W.; Schmolke, J.; Turk, M.; Willemsen, P.; Schlicker, M.; Westerdorff, K.

2008-08-01

The technology verification satellite TET (Technologie ErprobungsTräger) is the core element of the German On-Orbit-Verification (OOV) program of new technologies and techniques. The goal of this program is the support of the German space industry and research facilities for on-orbit verification of satellite technologies. The TET satellite is a small satellite developed and built in Germany under leadership of Kayser-Threde. The satellite bus is based on the successfully operated satellite BIRD and the newly developed payload platform with the new payload handling system called NVS (Nutzlastversorgungs-system). The NVS can be detailed in three major parts: the power supply the processor boards and the I/O-interfaces. The NVS is realized via several PCBs in Europe format which are connected to each other via an integrated backplane. The payloads are connected by front connectors to the NVS. This paper describes the concept, architecture, and the hard-/software of the NVS. Phase B of this project was successfully finished last year.

Performances of multiprocessor multidisk architectures for continuous media storage

NASA Astrophysics Data System (ADS)

Gennart, Benoit A.; Messerli, Vincent; Hersch, Roger D.

1996-03-01

Multimedia interfaces increase the need for large image databases, capable of storing and reading streams of data with strict synchronicity and isochronicity requirements. In order to fulfill these requirements, we consider a parallel image server architecture which relies on arrays of intelligent disk nodes, each disk node being composed of one processor and one or more disks. This contribution analyzes through bottleneck performance evaluation and simulation the behavior of two multi-processor multi-disk architectures: a point-to-point architecture and a shared-bus architecture similar to current multiprocessor workstation architectures. We compare the two architectures on the basis of two multimedia algorithms: the compute-bound frame resizing by resampling and the data-bound disk-to-client stream transfer. The results suggest that the shared bus is a potential bottleneck despite its very high hardware throughput (400Mbytes/s) and that an architecture with addressable local memories located closely to their respective processors could partially remove this bottleneck. The point- to-point architecture is scalable and able to sustain high throughputs for simultaneous compute- bound and data-bound operations.

Shuttle bus services quality assessment Tangerang Selatan toward smart city

NASA Astrophysics Data System (ADS)

Fassa, Ferdinand; Sitorus, Fredy Jhon Philip; Adikesuma, Tri Nugraha

2017-11-01

Around the world, shuttle bus operation played the significant role to accommodate transportation for commuting bus passengers. Shuttle Bus services in cities are provided by various bus agencies with kinds of own specific purposes. For instance, at Tangerang Selatan, Indonesia, it was said that shuttle bus In Trans Bintaro is run and operated by private bus companies hire by Bintaro developer. The aim of this research is to identify factors of satisfaction of shuttle bus service in Kota Tangerang Selatan, Indonesia. Several factors are used to analyze sums of 20 parameters performance indicators of Shuttle Bus. A face to face interview using a questionnaire (N=200) was used to collect data on October and March 2017. Likert and diagram Cartesian were used to model the all the parameters. This research succeeded in finding some categories of Shuttle bus service attributes such as accessibility, comfort, and safety. Users agreed that eight indicators in shuttle bus have the excellent achievement, while three indicators on performance remain low and should receive more attention especially punctuality of the bus.

An Optimization Model for the Selection of Bus-Only Lanes in a City.

PubMed

Chen, Qun

2015-01-01

The planning of urban bus-only lane networks is an important measure to improve bus service and bus priority. To determine the effective arrangement of bus-only lanes, a bi-level programming model for urban bus lane layout is developed in this study that considers accessibility and budget constraints. The goal of the upper-level model is to minimize the total travel time, and the lower-level model is a capacity-constrained traffic assignment model that describes the passenger flow assignment on bus lines, in which the priority sequence of the transfer times is reflected in the passengers' route-choice behaviors. Using the proposed bi-level programming model, optimal bus lines are selected from a set of candidate bus lines; thus, the corresponding bus lane network on which the selected bus lines run is determined. The solution method using a genetic algorithm in the bi-level programming model is developed, and two numerical examples are investigated to demonstrate the efficacy of the proposed model.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Spotz, William F.

PyTrilinos is a set of Python interfaces to compiled Trilinos packages. This collection supports serial and parallel dense linear algebra, serial and parallel sparse linear algebra, direct and iterative linear solution techniques, algebraic and multilevel preconditioners, nonlinear solvers and continuation algorithms, eigensolvers and partitioning algorithms. Also included are a variety of related utility functions and classes, including distributed I/O, coloring algorithms and matrix generation. PyTrilinos vector objects are compatible with the popular NumPy Python package. As a Python front end to compiled libraries, PyTrilinos takes advantage of the flexibility and ease of use of Python, and the efficiency of themore » underlying C++, C and Fortran numerical kernels. This paper covers recent, previously unpublished advances in the PyTrilinos package.« less

78 FR 17995 - Agency Information Collection Activity Under OMB Review

Federal Register 2010, 2011, 2012, 2013, 2014

2013-03-25

... collections: 49 U.S.C. Section 5337--State of Good Repair Program 49 U.S.C. Section 5339--Bus and Bus... on a quarterly basis. The information submitted ensures FTA's compliance with applicable federal laws. Title: 49 U.S.C. Section 5339--Bus and Bus Facilities Program. Abstract: 49 U.S.C. 5339--Bus and Bus...

Low-power, transparent optical network interface for high bandwidth off-chip interconnects.

PubMed

Liboiron-Ladouceur, Odile; Wang, Howard; Garg, Ajay S; Bergman, Keren

2009-04-13

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

Micro Cathode Arc Thruster for PhoneSat: Development and Potential Applications

NASA Technical Reports Server (NTRS)

Gazulla, Oriol Tintore; Perez, Andres Dono; Agasid, Elwood; Uribe, Eddie; Trinh, Greenfield; Keidar, Michael; Teel, George; Haque, Samudra; Lukas, Joseph; Salas, Alberto Guillen;

Technology insertion of a COTS RAID server as an image buffer in the image chain of the Defense Mapping Agency's Digital Production System

NASA Astrophysics Data System (ADS)

Mehring, James W.; Thomas, Scott D.

1995-11-01

The Data Services Segment of the Defense Mapping Agency's Digital Production System provides a digital archive of imagery source data for use by DMA's cartographic user's. This system was developed in the mid-1980's and is currently undergoing modernization. This paper addresses the modernization of the imagery buffer function that was performed by custom hardware in the baseline system and is being replaced by a RAID Server based on commercial off the shelf (COTS) hardware. The paper briefly describes the baseline DMA image system and the modernization program, that is currently under way. Throughput benchmark measurements were made to make design configuration decisions for a commercial off the shelf (COTS) RAID Server to perform as system image buffer. The test program began with performance measurements of the RAID read and write operations between the RAID arrays and the server CPU for RAID levels 0, 5 and 0+1. Interface throughput measurements were made for the HiPPI interface between the RAID Server and the image archive and processing system as well as the client side interface between a custom interface board that provides the interface between the internal bus of the RAID Server and the Input- Output Processor (IOP) external wideband network currently in place in the DMA system to service client workstations. End to end measurements were taken from the HiPPI interface through the RAID write and read operations to the IOP output interface.

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, R.; Fischler, M.S.; Husby, D.E.

1991-01-15

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured. 11 figures.

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, Robert; Fischler, Mark S.; Husby, Donald E.

1991-01-01

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.

Traveling by Bus Instead of Car on Urban Major Roads: Safety Benefits for Vehicle Occupants, Pedestrians, and Cyclists.

PubMed

Morency, Patrick; Strauss, Jillian; Pépin, Félix; Tessier, François; Grondines, Jocelyn

2018-04-01

Some studies have estimated fatality and injury rates for bus occupants, but data was aggregated at the country level and made no distinction between bus types. Also, injured pedestrians and cyclists, as a result of bus travel, were overlooked. We compared injury rates for car and city bus occupants on specific urban major roads, as well as the cyclist and pedestrian injuries associated with car and bus travel. We selected ten bus routes along major urban arterials (in Montreal, Canada). Passenger-kilometers traveled were estimated from vehicle counts at intersections (2002-2010) and from bus passenger counts (2008). Police accident reports (2001-2010) provided injury data for all modes. Injury rates associated with car and bus travel were calculated for vehicle occupants, pedestrians, and cyclists. Injury rate ratios were also computed. The safety benefits of bus travel, defined as the number of vehicle occupant, cyclist, and pedestrian injuries saved, were estimated for each route. Overall, for all ten routes, the ratio between car and bus occupant injury rates is 3.7 (95% CI [3.4, 4.0]). The rates of pedestrian and cyclist injuries per hundred million passenger-kilometers are also significantly greater for car travel than that for bus travel: 4.1 (95% CI [3.5, 4.9]) times greater for pedestrian injuries; 5.3 (95% CI [3.8, 7.6]) times greater for cyclist injuries. Similar results were observed for fatally and severely injured vehicle occupants, cyclists, and pedestrians. At the route level, the safety benefits of bus travel increase with the difference in injury rate associated with car and bus travel but also with the amount of passenger-kilometers by bus. Results show that city bus is a safer mode than car, for vehicle occupants but also for cyclists and pedestrians traveling along these bus routes. The safety benefits of bus travel greatly vary across urban routes; this spatial variation is most likely linked to environmental factors. Understanding the safety benefits of public transit for specific transport routes is likely to provide valuable information for mobilizing city and transportation planners.

Optics Program Modified for Multithreaded Parallel Computing

NASA Technical Reports Server (NTRS)

Lou, John; Bedding, Dave; Basinger, Scott

2006-01-01

A powerful high-performance computer program for simulating and analyzing adaptive and controlled optical systems has been developed by modifying the serial version of the Modeling and Analysis for Controlled Optical Systems (MACOS) program to impart capabilities for multithreaded parallel processing on computing systems ranging from supercomputers down to Symmetric Multiprocessing (SMP) personal computers. The modifications included the incorporation of OpenMP, a portable and widely supported application interface software, that can be used to explicitly add multithreaded parallelism to an application program under a shared-memory programming model. OpenMP was applied to parallelize ray-tracing calculations, one of the major computing components in MACOS. Multithreading is also used in the diffraction propagation of light in MACOS based on pthreads [POSIX Thread, (where "POSIX" signifies a portable operating system for UNIX)]. In tests of the parallelized version of MACOS, the speedup in ray-tracing calculations was found to be linear, or proportional to the number of processors, while the speedup in diffraction calculations ranged from 50 to 60 percent, depending on the type and number of processors. The parallelized version of MACOS is portable, and, to the user, its interface is basically the same as that of the original serial version of MACOS.

Initial Performance Results on IBM POWER6

NASA Technical Reports Server (NTRS)

Saini, Subbash; Talcott, Dale; Jespersen, Dennis; Djomehri, Jahed; Jin, Haoqiang; Mehrotra, Piysuh

2008-01-01

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Propulsion system for a motor vehicle using a bidirectional energy converter

DOEpatents

Tamor, Michael Alan; Gale, Allan Roy

1999-01-01

A motor vehicle propulsion system includes an electrical energy source and a traction motor coupled to receive electrical energy from the electrical energy source. The system also has a first bus provided electrical energy by the electrical energy source and a second bus of relatively lower voltage than the first bus. In addition, the system includes an electrically-driven source of reaction gas for the electrical energy source, the source of reaction gas coupled to receive electrical energy from the first bus. Also, the system has an electrical storage device coupled to the second bus for storing electrical energy at the lower voltage. The system also includes a bidirectional energy converter coupled to convert electrical energy from the first bus to the second bus and from the second bus to the first bus.

Asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's

NASA Astrophysics Data System (ADS)

Yamauchi, Hiroyuki; Akamatsu, Hironori; Fujita, Tsutomu

1995-04-01

An asymptotically zero power charge recycling bus (CRB) architecture, featuring virtual stacking of the individual bus-capacitance into a series configuration between supply voltage and ground, has been proposed. This CRB architecture makes it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultramultibit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, the ultrahigh data rate of 25.6 Gb/s can be achieved while maintaining the power dissipation to be less than 100 mW, which corresponds to less than 10% that of the previously reported 0.9 V suppressed bus-swing scheme, at V(sub cc) = 3.6 V for the bus width of 512 b with the bus-capacitance of 14 pF per bit operating at 50 MHz.

Dynamic Bus Travel Time Prediction Models on Road with Multiple Bus Routes

PubMed Central

Bai, Cong; Peng, Zhong-Ren; Lu, Qing-Chang; Sun, Jian

2015-01-01

Accurate and real-time travel time information for buses can help passengers better plan their trips and minimize waiting times. A dynamic travel time prediction model for buses addressing the cases on road with multiple bus routes is proposed in this paper, based on support vector machines (SVMs) and Kalman filtering-based algorithm. In the proposed model, the well-trained SVM model predicts the baseline bus travel times from the historical bus trip data; the Kalman filtering-based dynamic algorithm can adjust bus travel times with the latest bus operation information and the estimated baseline travel times. The performance of the proposed dynamic model is validated with the real-world data on road with multiple bus routes in Shenzhen, China. The results show that the proposed dynamic model is feasible and applicable for bus travel time prediction and has the best prediction performance among all the five models proposed in the study in terms of prediction accuracy on road with multiple bus routes. PMID:26294903

Dynamic Bus Travel Time Prediction Models on Road with Multiple Bus Routes.

PubMed

Bai, Cong; Peng, Zhong-Ren; Lu, Qing-Chang; Sun, Jian

2015-01-01

Accurate and real-time travel time information for buses can help passengers better plan their trips and minimize waiting times. A dynamic travel time prediction model for buses addressing the cases on road with multiple bus routes is proposed in this paper, based on support vector machines (SVMs) and Kalman filtering-based algorithm. In the proposed model, the well-trained SVM model predicts the baseline bus travel times from the historical bus trip data; the Kalman filtering-based dynamic algorithm can adjust bus travel times with the latest bus operation information and the estimated baseline travel times. The performance of the proposed dynamic model is validated with the real-world data on road with multiple bus routes in Shenzhen, China. The results show that the proposed dynamic model is feasible and applicable for bus travel time prediction and has the best prediction performance among all the five models proposed in the study in terms of prediction accuracy on road with multiple bus routes.

BBIS: Beacon Bus Information System

NASA Astrophysics Data System (ADS)

Kasim, Shahreen; Hafit, Hanayanti; Pei Juin, Kong; Afizah Afif, Zehan; Hashim, Rathiah; Ruslai, Husni; Jahidin, Kamaruzzaman; Syafwan Arshad, Mohammad

2016-11-01

Lack of bus information for example bus timetable, status of the bus and messy advertisement on bulletin board at the bus stop will give negative impact to tourist. Therefore, a real-time update bus information bulletin board provides all information needed so that passengers can save their bus information searching time. Supported with Android or iOS, Beacon Bus Information System (BBIS) provides bus information between Batu Pahat and Kluang area. BBIS is a system that implements physical web technology and interaction on demand. It built on Backend-as-a-Service, a cloud solution and Firebase non relational database as data persistence backend and syncs between user client in the real-time. People walk through bus stop with smart device and do not require any application. Bluetooth Beacon is used to achieve smart device's best performance of data sharing. Intellij IDEA 15 is one of the tools that that used to develop the BBIS system. Multi-language included front end and backend supported Integration development environment (IDE) helped to speed up integration process.

75 FR 74134 - State of Good Repair Bus and Bus Facilities Discretionary Program Funds

Federal Register 2010, 2011, 2012, 2013, 2014

2010-11-30

... public agencies, private companies engaged in public transportation, or private non-profit organizations... public transportation bus fleet, infrastructure, and equipment in a state of good repair. Grantees... DEPARTMENT OF TRANSPORTATION Federal Transit Administration State of Good Repair Bus and Bus...

49 CFR 655.4 - Definitions.

Code of Federal Regulations, 2013 CFR

2013-10-01

...) Carrying a firearm for security purposes. Vehicle means a bus, electric bus, van, automobile, rail car... involved is a bus, electric bus, van, or automobile, one or more vehicles (including non-FTA funded... the public transportation vehicle involved is a rail car, trolley car, trolley bus, or vessel, the...

49 CFR 655.4 - Definitions.

Code of Federal Regulations, 2014 CFR

2014-10-01

...) Carrying a firearm for security purposes. Vehicle means a bus, electric bus, van, automobile, rail car... involved is a bus, electric bus, van, or automobile, one or more vehicles (including non-FTA funded... the public transportation vehicle involved is a rail car, trolley car, trolley bus, or vessel, the...

Human factors in technology replacement: a case study in interface design for a public transport monitoring system.

PubMed

Harper, J G; Fuller, R; Sweeney, D; Waldmann, T

1998-04-01

This paper describes ergonomic issues raised during a project to provide a replacement real-time bus route control system to a large public transport company. Task and system analyses highlighted several deficiencies in the original system architecture, the human-machine interfaces and the general approach to system management. The eventual live prototype replaced the existing original system for a trial evaluation period of several weeks. During this period a number of studies was conducted with the system users in order to measure any improvements the new system, with its ergonomic features, produced over the old. Importantly, the results confirmed that (a) general responsiveness and service quality were improved, and (b) users were more comfortable with the new design. We conclude with a number of caveats which we believe will be useful to any group addressing technology impact in a large organisation.

Ground Operations Aerospace Language (GOAL). Volume 3: Data bank

NASA Technical Reports Server (NTRS)

1973-01-01

The GOAL (Ground Operations Aerospace Language) test programming language was developed for use in ground checkout operations in a space vehicle launch environment. To insure compatibility with a maximum number of applications, a systematic and error-free method of referencing command/response (analog and digital) hardware measurements is a principle feature of the language. Central to the concept of requiring the test language to be independent of launch complex equipment and terminology is that of addressing measurements via symbolic names that have meaning directly in the hardware units being tested. To form the link from test program through test system interfaces to the units being tested the concept of a data bank has been introduced. The data bank is actually a large cross-reference table that provides pertinent hardware data such as interface unit addresses, data bus routings, or any other system values required to locate and access measurements.

Design of a ``Digital Atlas Vme Electronics'' (DAVE) module

NASA Astrophysics Data System (ADS)

Goodrick, M.; Robinson, D.; Shaw, R.; Postranecky, M.; Warren, M.

2012-01-01

ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' (``DAVE''). The unit is designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts. DAVE aims to provide exact ATLAS CTP (ATLAS Central Trigger Processor) functionality, with random trigger, simple and complex deadtime, ECR (Event Counter Reset), BCR (Bunch Counter Reset) etc. being generated to give exactly the same conditions in standalone running as experienced in combined runs. DAVE provides additional hardware and a large amount of free firmware resource to allow users to add or change functionality. The combination of the large number of individually programmable inputs and outputs in various formats, with very large external RAM and other components all connected to the FPGA, also makes DAVE a powerful and versatile FPGA utility card.

Modified Perfect Harmonics Cancellation Control of a Grid Interfaced SPV Power Generation

NASA Astrophysics Data System (ADS)

Singh, B.; Shahani, D. T.; Verma, A. K.

2015-03-01

This paper deals with a grid interfaced solar photo voltaic (SPV) power generating system with modified perfect harmonic cancellation (MPHC) control for power quality improvement in terms of mitigation of the current harmonics, power factor correction, control of point of common coupling (PCC) voltage with reactive power compensation and load balancing in a three phase distribution system. The proposed grid interfaced SPV system consists of a SPV array, a dc-dc boost converter and a voltage source converter (VSC) used for the compensation of other connected linear and nonlinear loads at PCC. The reference grid currents are estimated using MPHC method and control signals are derived by using pulse width modulation (PWM) current controller of VSC. The SPV power is fed to the common dc bus of VSC and dc-dc boost converter using maximum power point tracking (MPPT). The dc link voltage of VSC is regulated by using dc voltage proportional integral (PI) controller. The analysis of the proposed SPV power generating system is carried out under dc/ac short circuit and severe SPV-SX and SPV-TX intrusion.

76 FR 68819 - State of Good Repair Bus and Bus Facilities Discretionary Program Funds

Federal Register 2010, 2011, 2012, 2013, 2014

2011-11-07

... that are public agencies, private companies engaged in public transportation, or private non-profit... Table 1 will provide funds to help maintain the nation's public transportation bus fleet, infrastructure... DEPARTMENT OF TRANSPORTATION Federal Transit Administration State of Good Repair Bus and Bus...

Bus Training Handbook.

ERIC Educational Resources Information Center

Dorny, Audrea; Cole, ChiKay

This manual presents guidelines for teaching students with disabilities necessary skills for safe and independent travel on public buses. Six guidelines for teachers include: (1) participate in bus training; (2) use wise and intelligent judgment; (3) utilize the bus checklist; (4) know and teach bus rules; (5) know bus routes; and (6) know bus…

49 CFR 655.4 - Definitions.

Code of Federal Regulations, 2012 CFR

2012-10-01

...) Carrying a firearm for security purposes. Vehicle means a bus, electric bus, van, automobile, rail car... involved is a bus, electric bus, van, or automobile, one or more vehicles (including non-FTA funded... the mass transit vehicle involved is a rail car, trolley car, trolley bus, or vessel, the mass transit...

49 CFR 655.4 - Definitions.

Code of Federal Regulations, 2010 CFR

2010-10-01

...) Carrying a firearm for security purposes. Vehicle means a bus, electric bus, van, automobile, rail car... involved is a bus, electric bus, van, or automobile, one or more vehicles (including non-FTA funded... the mass transit vehicle involved is a rail car, trolley car, trolley bus, or vessel, the mass transit...

49 CFR 655.4 - Definitions.

Code of Federal Regulations, 2011 CFR

2011-10-01

...) Carrying a firearm for security purposes. Vehicle means a bus, electric bus, van, automobile, rail car... involved is a bus, electric bus, van, or automobile, one or more vehicles (including non-FTA funded... the mass transit vehicle involved is a rail car, trolley car, trolley bus, or vessel, the mass transit...

Forecast analysis of optical waveguide bus performance

NASA Technical Reports Server (NTRS)

Ledesma, R.; Rourke, M. D.

1979-01-01

Elements to be considered in the design of a data bus include: architecture; data rate; modulation, encoding, detection; power distribution requirements; protocol, work structure; bus reliability, maintainability; interterminal transmission medium; cost; and others specific to application. Fiber- optic data bus considerations for a 32 port transmissive star architecture, are discussed in a tutorial format. General optical-waveguide bus concepts, are reviewed. The electrical and optical performance of a 32 port transmissive star bus, and the effects of temperature on the performance of optical-waveguide buses are examined. A bibliography of pertinent references and the bus receiver test results are included.

Massachusetts Fuel Cell Bus Project: Demonstrating a Total Transit Solution for Fuel Cell Electric Buses in Boston

DOE Office of Scientific and Technical Information (OSTI.GOV)

The Federal Transit Administration's National Fuel Cell Bus Program focuses on developing commercially viable fuel cell bus technologies. Nuvera is leading the Massachusetts Fuel Cell Bus project to demonstrate a complete transit solution for fuel cell electric buses that includes one bus and an on-site hydrogen generation station for the Massachusetts Bay Transportation Authority (MBTA). A team consisting of ElDorado National, BAE Systems, and Ballard Power Systems built the fuel cell electric bus, and Nuvera is providing its PowerTap on-site hydrogen generator to provide fuel for the bus.

Electrical system architecture

DOEpatents

Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Akasam, Sivaprasad [Peoria, IL; Hoff, Brian D [East Peoria, IL

2008-07-15

An electrical system for a vehicle includes a first power source generating a first voltage level, the first power source being in electrical communication with a first bus. A second power source generates a second voltage level greater than the first voltage level, the second power source being in electrical communication with a second bus. A starter generator may be configured to provide power to at least one of the first bus and the second bus, and at least one additional power source may be configured to provide power to at least one of the first bus and the second bus. The electrical system also includes at least one power consumer in electrical communication with the first bus and at least one power consumer in electrical communication with the second bus.

School bus and children's traffic safety.

PubMed

Pan, Shu-ming; Hargarten, Stephen; Zhu, Shan-kuan

2007-08-01

There is no safer way to transport a child than a school bus. Fatal crashes involving occupants are extremely rare events in the US. In recent years, school bus transportation began to develop in China. We want to bring advanced experience on school bus safety in Western countries such as the US to developing countries. We searched the papers related to school bus safety from Medline, Chinese Scientific Journals Database and the Web of the National Highway Traffic Safety Administration (NHTSA). There were only 9 papers related to school bus safety, which showed that higher levels of safety standards on school buses, school bus-related transportation and environmental laws and injury prevention were the primary reasons for the desired outcome. Few school bus is related to deaths and injuries in the developed countries. The developing countries should make strict environmental laws and standards on school bus safety to prevent children's injury and death.

Evaluation of bus emissions generated near bus stops

NASA Astrophysics Data System (ADS)

Yu, Qian; Li, Tiezhu

2014-03-01

The purpose of this research is to demonstrate a methodology for quantification of bus emissions generated near bus stops based on the real-world on-road emissions data collected by the Portable Emission Measurement System (PEMS). Data collection was carried out on an urban diesel bus throughout a bus line under normal operation condition on four work days. Stop influence zone is defined as the area in which the normal bus driving is interrupted by bus stops. The second-by-second data were screened out within the stop influence zone. And the bus running state near a stop was classified into three driving modes, deceleration, idling, and acceleration. Then emission characteristics were analyzed for each mode. Under the idling condition, the emission rates (g s-1) were not constant all the time. The NOX emission rate decreased in the first 4-6 s while the corresponding emission rates of CO2, CO, NOX, and HC increased in the last 4 s of idling. Besides, the influence of bus stop characteristics on emissions was investigated using statistical methods. Platform type, length and location of bus stops showed significant effects on the length of the stop influence zone. However, there were no significant effects on distance-based emission factors.

TET-1- A German Microsatellite for Technology On -Orbit Verification

NASA Astrophysics Data System (ADS)

Föckersperger, S.; Lattner, K.; Kaiser, C.; Eckert, S.; Bärwald, W.; Ritzmann, S.; Mühlbauer, P.; Turk, M.; Willemsen, P.

2008-08-01

Due to the high safety standards in the space industry every new product must go through a verification process before qualifying for operation in a space system. Within the verification process the payload undergoes a series of tests which prove that it is in accordance with mission requirements in terms of function, reliability and safety. Important verification components are the qualification for use on the ground as well as the On-Orbit Verification (OOV), i.e. proof that the product is suitable for use under virtual space conditions (on-orbit). Here it is demonstrated that the product functions under conditions which cannot or can only be partially simulated on the ground. The OOV-Program of the DLR serves to bridge the gap between the product tested and qualified on the ground and the utilization of the product in space. Due to regular and short-term availability of flight opportunities industry and research facilities can verify their latest products under space conditions and demonstrate their reliability and marketability. The Technologie-Erprobungs-Tr&äger TET (Technology Experiments Carrier) comprises the core elements of the OOV Program. A programmatic requirement of the OOV Program is that a satellite bus already verified in orbit be used in the first segment of the program. An analysis of suitable satellite buses showed that a realization of the TET satellite bus based on the BIRD satellite bus fulfilled the programmatic requirements best. Kayser-Threde was selected by DLR as Prime Contractor to perform the project together with its major subcontractors Astro- und Feinwerktechnik, Berlin for the platform development and DLR-GSOC for the ground segment development. TET is now designed to be a modular and flexible micro-satellite for any orbit between 450 and 850 km altitude and inclination between 53° and SSO. With an overall mass of 120 kg TET is able to accommodate experiments of up to 50 kg. A multipurpose payload supply systemThere is significant confusion in the space industry today over the terms used to describe satellite bus architectures. Terms such as "standard bus" (or "common bus"), "modular bus" and "plug-and-play bus" are often used with little understanding of what the terms actually mean, and even less understanding of what the differences in these space architectures mean. It may seem that these terms are subtle differentiators, but in reality these terms describe radically different ways to design, build, test, and operate satellites. Furthermore, these terms imply very different business models for the acquisition, operation, and sustainment of space systems. This paper will define and describe the difference between "standard buses", "modular buses" and "plug-and-play buses"; giving examples of each kind with a cost/benefit discussion of each type. under Kayser-Threde responsibility provides the necessary interfaces to the experiments. The first TET mission is scheduled for mid of 2010. TET will be launched as piggy-back payload on any available launcher worldwide to reduce launch cost and provide maximum flexibility. Finally, TET will provide all services required by the experimenters for a one year mission operation to perform a successful OOV-mission with its technology experiments leading to an efficient access to space for German industry and institutions.

The scientific data acquisition system of the GAMMA-400 space project

NASA Astrophysics Data System (ADS)

Bobkov, S. G.; Serdin, O. V.; Gorbunov, M. S.; Arkhangelskiy, A. I.; Topchiev, N. P.

2016-02-01

The description of scientific data acquisition system (SDAS) designed by SRISA for the GAMMA-400 space project is presented. We consider the problem of different level electronics unification: the set of reliable fault-tolerant integrated circuits fabricated on Silicon-on-Insulator 0.25 mkm CMOS technology and the high-speed interfaces and reliable modules used in the space instruments. The characteristics of reliable fault-tolerant very large scale integration (VLSI) technology designed by SRISA for the developing of computation systems for space applications are considered. The scalable net structure of SDAS based on Serial RapidIO interface including real-time operating system BAGET is described too.

Automatic control of a primary electric thrust subsystem

NASA Technical Reports Server (NTRS)

Macie, T. W.; Macmedan, M. L.

1975-01-01

A concept for automatic control of the thrust subsystem has been developed by JPL and participating NASA Centers. This paper reports on progress in implementing the concept at JPL. Control of the Thrust Subsystem (TSS) is performed by the spacecraft computer command subsystem, and telemetry data is extracted by the spacecraft flight data subsystem. The Data and Control Interface Unit, an element of the TSS, provides the interface with the individual elements of the TSS. The control philosophy and implementation guidelines are presented. Control requirements are listed, and the control mechanism, including the serial digital data intercommunication system, is outlined. The paper summarizes progress to Fall 1974.

Low Cost Electroencephalographic Acquisition Amplifier to serve as Teaching and Research Tool

PubMed Central

Jain, Ankit; Kim, Insoo; Gluckman, Bruce J.

2012-01-01

We describe the development and testing of a low cost, easily constructed electroencephalographic acquisition amplifier for noninvasive Brain Computer Interface (BCI) education and research. The acquisition amplifier is constructed from newly available off-the-shelf integrated circuit components, and readily sends a 24-bit data stream via USB bus to a computer platform. We demonstrate here the hardware’s use in the analysis of a visually evoked P300 paradigm for a choose one-of-eight task. This clearly shows the applicability of this system as a low cost teaching and research tool. PMID:22254699

Flywheel Charge/Discharge Control Developed

NASA Technical Reports Server (NTRS)

Beach, Raymond.F.; Kenny, Barbara H.

2001-01-01

A control algorithm developed at the NASA Glenn Research Center will allow a flywheel energy storage system to interface with the electrical bus of a space power system. The controller allows the flywheel to operate in both charge and discharge modes. Charge mode is used to store additional energy generated by the solar arrays on the spacecraft during insolation. During charge mode, the flywheel spins up to store the additional electrical energy as rotational mechanical energy. Discharge mode is used during eclipse when the flywheel provides the power to the spacecraft. During discharge mode, the flywheel spins down to release the stored rotational energy.

New generation of telemetry systems using CCSDS packetisation - A prototype implementation

NASA Astrophysics Data System (ADS)

Sotta, J. P.; Held, K.

1988-07-01

The system described herein was developed under ESA contract to support the introduction of new telemetry standards based on the packetized telemetry data concept. These standards were derived from recommendations in the frame of work of CCSDS, an inter-Agency committee that counts among its members most European National Agencies, ESA, NASA as well as Japanese NASDA, Indian ISRO and Brazilian INPE and having as objective to facilitate cross-support for space missions. The development is based on the present generation of ESA on-board equipment (OBDH) subsystem and is fully compatible with OBDH bus interfaces and transfer protocol.

Improved Software to Browse the Serial Medical Images for Learning

PubMed Central

2017-01-01

The thousands of serial images used for medical pedagogy cannot be included in a printed book; they also cannot be efficiently handled by ordinary image viewer software. The purpose of this study was to provide browsing software to grasp serial medical images efficiently. The primary function of the newly programmed software was to select images using 3 types of interfaces: buttons or a horizontal scroll bar, a vertical scroll bar, and a checkbox. The secondary function was to show the names of the structures that had been outlined on the images. To confirm the functions of the software, 3 different types of image data of cadavers (sectioned and outlined images, volume models of the stomach, and photos of the dissected knees) were inputted. The browsing software was downloadable for free from the homepage (anatomy.co.kr) and available off-line. The data sets provided could be replaced by any developers for their educational achievements. We anticipate that the software will contribute to medical education by allowing users to browse a variety of images. PMID:28581279

Improved Software to Browse the Serial Medical Images for Learning.

PubMed

Kwon, Koojoo; Chung, Min Suk; Park, Jin Seo; Shin, Byeong Seok; Chung, Beom Sun

2017-07-01

The thousands of serial images used for medical pedagogy cannot be included in a printed book; they also cannot be efficiently handled by ordinary image viewer software. The purpose of this study was to provide browsing software to grasp serial medical images efficiently. The primary function of the newly programmed software was to select images using 3 types of interfaces: buttons or a horizontal scroll bar, a vertical scroll bar, and a checkbox. The secondary function was to show the names of the structures that had been outlined on the images. To confirm the functions of the software, 3 different types of image data of cadavers (sectioned and outlined images, volume models of the stomach, and photos of the dissected knees) were inputted. The browsing software was downloadable for free from the homepage (anatomy.co.kr) and available off-line. The data sets provided could be replaced by any developers for their educational achievements. We anticipate that the software will contribute to medical education by allowing users to browse a variety of images. © 2017 The Korean Academy of Medical Sciences.

Modeling the effect of bus stops on capacity of curb lane

NASA Astrophysics Data System (ADS)

Luo, Qingyu; Zheng, Tianyao; Wu, Wenjing; Jia, Hongfei; Li, Jin

With the increase of buses and bus lines, a negative effect on road section capacity is made by the prolonged delay and queuing time at bus stops. However, existing methods of measuring the negative effect pay little attention to different bus stop types in the curb lanes. This paper uses Gap theory and Queuing theory to build models for effect-time and potential capacity in different conditions, including curbside bus stops, bus bays with overflow and bus bays without overflow. In order to make the effect-time models accurate and reliable, two types of probabilities are introduced. One is the probability that the dwell time is less than the headway of curb lane at curbside bus stops; the other is the overflow probability at bus bays. Based on the fundamental road capacity model and effect-time models, potential capacity models of curb lane are designed. The new models are calibrated by the survey data from Changchun City, and verified by the simulation software of VISSIM. Furthermore, with different arrival rates of vehicles, the setting conditions of bus stops are researched. Results show that the potential capacity models have high precision. They can offer a reference for recognizing the effect of bus stops on the capacity of curb lane, which can provide a basis for planning, design and management of urban roads and bus stops.

Safeguards Technology Factsheet - Unattended Dual Current Monitor (UDCM)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Newell, Matthew R.

2016-04-13

The UDCM is a low-current measurement device designed to record sub-nano-amp to micro-amp currents from radiation detectors. The UDCM is a two-channel device that incorporates a Commercial-Off-The-Shelf (COTS) processor enabling both serial over USB as well as Ethernet communications. The instrument includes microSD and USB flash memory for data storage as well as a programmable High Voltage (HV) power supply for detector bias. The UDCM is packaged in the same enclosure, employs the same processor and has a similar user interface as the UMSR. A serial over USB communication line to the UDCM allows the use of existing versions ofmore » MIC software, while the Ethernet port is compatible with the new IAEA RAINSTORM communication protocol.« less

A versatile diffractive maskless lithography for single-shot and serial microfabrication.

PubMed

Jenness, Nathan J; Hill, Ryan T; Hucknall, Angus; Chilkoti, Ashutosh; Clark, Robert L

2010-05-24

We demonstrate a diffractive maskless lithographic system that is capable of rapidly performing both serial and single-shot micropatterning. Utilizing the diffractive properties of phase holograms displayed on a spatial light modulator, arbitrary intensity distributions were produced to form two and three dimensional micropatterns/structures in a variety of substrates. A straightforward graphical user interface was implemented to allow users to load templates and change patterning modes within the span of a few minutes. A minimum resolution of approximately 700 nm is demonstrated for both patterning modes, which compares favorably to the 232 nm resolution limit predicted by the Rayleigh criterion. The presented method is rapid and adaptable, allowing for the parallel fabrication of microstructures in photoresist as well as the fabrication of protein microstructures that retain functional activity.

MPI_XSTAR: MPI-based Parallelization of the XSTAR Photoionization Program

NASA Astrophysics Data System (ADS)

Danehkar, Ashkbiz; Nowak, Michael A.; Lee, Julia C.; Smith, Randall K.

2018-02-01

We describe a program for the parallel implementation of multiple runs of XSTAR, a photoionization code that is used to predict the physical properties of an ionized gas from its emission and/or absorption lines. The parallelization program, called MPI_XSTAR, has been developed and implemented in the C++ language by using the Message Passing Interface (MPI) protocol, a conventional standard of parallel computing. We have benchmarked parallel multiprocessing executions of XSTAR, using MPI_XSTAR, against a serial execution of XSTAR, in terms of the parallelization speedup and the computing resource efficiency. Our experience indicates that the parallel execution runs significantly faster than the serial execution, however, the efficiency in terms of the computing resource usage decreases with increasing the number of processors used in the parallel computing.

49 CFR 393.62 - Emergency exits for buses.

Code of Federal Regulations, 2011 CFR

2011-10-01

... (including a school bus used in interstate commerce for non-school bus operations) with a GVWR of more than 4... manufacture. (2) Each bus (including a school bus used in interstate commerce for non-school bus operations... NECESSARY FOR SAFE OPERATION Glazing and Window Construction § 393.62 Emergency exits for buses. (a) Buses...

49 CFR 393.62 - Emergency exits for buses.

Code of Federal Regulations, 2013 CFR

2013-10-01

... (including a school bus used in interstate commerce for non-school bus operations) with a GVWR of more than 4... manufacture. (2) Each bus (including a school bus used in interstate commerce for non-school bus operations... NECESSARY FOR SAFE OPERATION Glazing and Window Construction § 393.62 Emergency exits for buses. (a) Buses...

49 CFR 393.62 - Emergency exits for buses.

Code of Federal Regulations, 2014 CFR

2014-10-01

... (including a school bus used in interstate commerce for non-school bus operations) with a GVWR of more than 4... manufacture. (2) Each bus (including a school bus used in interstate commerce for non-school bus operations... NECESSARY FOR SAFE OPERATION Glazing and Window Construction § 393.62 Emergency exits for buses. (a) Buses...

49 CFR 393.62 - Emergency exits for buses.

Code of Federal Regulations, 2012 CFR

2012-10-01

... (including a school bus used in interstate commerce for non-school bus operations) with a GVWR of more than 4... manufacture. (2) Each bus (including a school bus used in interstate commerce for non-school bus operations... NECESSARY FOR SAFE OPERATION Glazing and Window Construction § 393.62 Emergency exits for buses. (a) Buses...

Electric School Bus Testing | Transportation Research | NREL

Science.gov Websites

Electric School Bus Evaluation Electric School Bus Evaluation Photo of children boarding school bus . NREL is evaluating the performance of electric and conventional school buses operated by two California school districts. Photo courtesy of School Bus Fleet Magazine NREL is evaluating the in-service

Classroom Activities in School Bus and Pedestrian Safety Education. Bulletin No. 93138.

ERIC Educational Resources Information Center

Wisconsin State Dept. of Transportation, Madison.

School bus and related pedestrian safety education is prevention-oriented so that students will learn how to avoid bus-related accidents. This manual provides lesson plans emphasizing the school bus stop, loading and unloading zones, emergency evacuation drills, and appropriate behavior on the school bus. The guide also recognizes demographic…

Emission inventory estimation of an intercity bus terminal.

PubMed

Qiu, Zhaowen; Li, Xiaoxia; Hao, Yanzhao; Deng, Shunxi; Gao, H Oliver

2016-06-01

Intercity bus terminals are hotspots of air pollution due to concentrated activities of diesel buses. In order to evaluate the bus terminals' impact on air quality, it is necessary to estimate the associated mobile emission inventories. Since the vehicles' operating condition at the bus terminal varies significantly, conventional calculation of the emissions based on average emission factors suffers the loss of accuracy. In this study, we examined a typical intercity bus terminal-the Southern City Bus Station of Xi'an, China-using a multi-scale emission model-(US EPA's MOVES model)-to quantity the vehicle emission inventory. A representative operating cycle for buses within the station is constructed. The emission inventory was then estimated using detailed inputs including vehicle ages, operating speeds, operating schedules, and operating mode distribution, as well as meteorological data (temperature and humidity). Five functional areas (bus yard, platforms, disembarking area, bus travel routes within the station, and bus entrance/exit routes) at the terminal were identified, and the bus operation cycle was established using the micro-trip cycle construction method. Results of our case study showed that switching to compressed natural gas (CNG) from diesel fuel could reduce PM2.5 and CO emissions by 85.64 and 6.21 %, respectively, in the microenvironment of the bus terminal. When CNG is used, tail pipe exhaust PM2.5 emission is significantly reduced, even less than brake wear PM2.5. The estimated bus operating cycles can also offer researchers and policy makers important information for emission evaluation in the planning and design of any typical intercity bus terminals of a similar scale.

Fault-tolerant processing system

NASA Technical Reports Server (NTRS)

Palumbo, Daniel L. (Inventor)

1996-01-01

A fault-tolerant, fiber optic interconnect, or backplane, which serves as a via for data transfer between modules. Fault tolerance algorithms are embedded in the backplane by dividing the backplane into a read bus and a write bus and placing a redundancy management unit (RMU) between the read bus and the write bus so that all data transmitted by the write bus is subjected to the fault tolerance algorithms before the data is passed for distribution to the read bus. The RMU provides both backplane control and fault tolerance.

Solar Anomalous and Magnetospheric Particle Explorer attitude control electronics box design and performance

NASA Technical Reports Server (NTRS)

Chamberlin, K.; Clagett, C.; Correll, T.; Gruner, T.; Quinn, T.; Shiflett, L.; Schnurr, R.; Wennersten, M.; Frederick, M.; Fox, S. M.

1993-01-01

The attitude Control Electronics (ACE) Box is the center of the Attitude Control Subsystem (ACS) for the Solar Anomalous and Magnetospheric Particle Explorer (SAMPEX) satellite. This unit is the single point interface for all of the Attitude Control Subsystem (ACS) related sensors and actuators. Commands and telemetry between the SAMPEX flight computer and the ACE Box are routed via a MIL-STD-1773 bus interface, through the use of an 80C85 processor. The ACE Box consists of the flowing electronic elements: power supply, momentum wheel driver, electromagnet driver, coarse sun sensor interface, digital sun sensor interface, magnetometer interface, and satellite computer interface. In addition, the ACE Box also contains an independent Safehold electronics package capable of keeping the satellite pitch axis pointing towards the sun. The ACE Box has dimensions of 24 x 31 x 8 cm, a mass of 4.3 kg, and an average power consumption of 10.5 W. This set of electronics was completely designed, developed, integrated, and tested by personnel at NASA GSFC. SAMPEX was launched on July 3, 1992, and the initial attitude acquisition was successfully accomplished via the analog Safehold electronics in the ACE Box. This acquisition scenario removed the excess body rates via magnetic control and precessed the satellite pitch axis to within 10 deg of the sun line. The performance of the SAMPEX ACS in general and the ACE Box in particular has been quite satisfactory.

Robotics research projects report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hsia, T.C.

The research results of the Robotics Research Laboratory are summarized. Areas of research include robotic control, a stand-alone vision system for industrial robots, and sensors other than vision that would be useful for image ranging, including ultrasonic and infra-red devices. One particular project involves RHINO, a 6-axis robotic arm that can be manipulated by serial transmission of ASCII command strings to its interfaced controller. (LEW)

Balloon Borne Ultraviolet Spectrometer.

DTIC Science & Technology

1978-12-28

n.c.aaary ond lden lfy by block numb.r) ultraviolet ground support equipment (GSE) spectrometers flight electronics instrumentation balloons \\ solar ...Assembly 4 Fig. 3 Solar Balloon Experiment Ass ’y 7 Fig. 4 Mechanical Interface , UV Spectrometer 8 Fig . 5 Spectrometer Body Assemb ly 10 Fig. 6...Diagram, GSE )bnitor 48 Selector and Battery Charger Fig. 25 Schematic Diagram, GSE Serial to 49 Parallel Data Converter Fig. 26 Schematic Diagram

Tests of the E-Z Reader Model: Exploring the Interface between Cognition and Eye-Movement Control

ERIC Educational Resources Information Center

Pollatsek, Alexander; Reichle, Erik D.; Rayner, Keith

2006-01-01

This paper is simultaneously a test and refinement of the E-Z Reader model and an exploration of the interrelationship between visual and language processing and eye-movements in reading. Our modeling indicates that the assumption that words in text are processed serially by skilled readers is a viable and attractive hypothesis, as it accounts not…

Analysis of real-time variables affecting children's exposure to diesel-related pollutants during school bus commutes in Los Angeles

NASA Astrophysics Data System (ADS)

Sabin, Lisa D.; Kozawa, Kathleen; Behrentz, Eduardo; Winer, Arthur M.; Fitz, Dennis R.; Pankratz, David V.; Colome, Steven D.; Fruin, Scott A.

Variables affecting children's exposure during school bus commutes were investigated using real-time measurements of black carbon (BC), particle-bound polycyclic aromatic hydrocarbons (PB-PAH) and nitrogen dioxide (NO 2) inside 3 conventional diesel school buses, a particle trap-outfitted (TO) diesel school bus and a compressed natural gas (CNG) school bus, while traveling along an urban Los Angeles Unified School District bus route. A video camera was mounted at the front of each bus to record roadway conditions ahead of the bus during each commute. The videotapes from 12 commutes, in conjunction with pollutant concentration time series, were used to determine the influence of variables such as vehicles being followed, bus type and roadway type on pollutant concentrations inside the bus. For all buses tested, the highest concentrations of BC, PB-PAH and NO 2 were observed when following a diesel school bus, especially if that bus was emitting visible exhaust. This result was important because other diesel school buses were responsible for the majority of the diesel vehicle encounters, primarily due to caravanning with each other when leaving a school at the same time. Compared with following a gasoline vehicle or no target, following a smoky diesel school bus yielded BC and PB-PAH concentrations inside the cabin 8 and 11 times higher, respectively, with windows open, and ˜1.8 times higher for both pollutants with windows closed. When other diesel vehicles were not present, pollutant concentrations were highest inside the conventional diesel buses and lowest inside the CNG bus, while the TO diesel bus exhibited intermediate concentrations. Differences in pollutant concentrations between buses were most pronounced with the bus windows closed, and were attributed to a combination of higher concentrations in the exhaust and higher exhaust gas intrusion rates for the conventional diesel buses. Conventional diesel school buses can have a double exposure impact on commuting children: first, exposures to the exhaust from other nearby diesel school buses and, second, exposure to the bus's own exhaust through "self-pollution".

275 C Downhole Microcomputer System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chris Hutchens; Hooi Miin Soo

2008-08-31

An HC11 controller IC and along with serial SRAM and ROM support ICs chip set were developed to support a data acquisition and control for extreme temperature/harsh environment conditions greater than 275 C. The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and signal processing applications and was the logical choice for a downhole controller. This extreme temperature version of the 68HC11 enables new high temperature designs and additionally allows 68HC11-based well logging tools and MWD tools to be upgraded for high temperature operation in deep gas reservoirs, The microcomputer chip consists of the microprocessormore » ALU, a small boot ROM, 4 kbyte data RAM, counter/timer unit, serial peripheral interface (SPI), asynchronous serial interface (SCI), and the A, B, C, and D parallel ports. The chip is code compatible with the single chip mode commercial 68HC11 except for the absence of the analog to digital converter system. To avoid mask programmed internal ROM, a boot program is used to load the microcomputer program from an external mask SPI ROM. A SPI RAM IC completes the chip set and allows data RAM to be added in 4 kbyte increments. The HC11 controller IC chip set is implemented in the Peregrine Semiconductor 0.5 micron Silicon-on-Sapphire (SOS) process using a custom high temperature cell library developed at Oklahoma State University. Yield data is presented for all, the HC11, SPI-RAM and ROM. The lessons learned in this project were extended to the successful development of two high temperature versions of the LEON3 and a companion 8 Kbyte SRAM, a 200 C version for the Navy and a 275 C version for the gas industry.« less

Integer programming model for optimizing bus timetable using genetic algorithm

NASA Astrophysics Data System (ADS)

Wihartiko, F. D.; Buono, A.; Silalahi, B. P.

2017-01-01

Bus timetable gave an information for passengers to ensure the availability of bus services. Timetable optimal condition happened when bus trips frequency could adapt and suit with passenger demand. In the peak time, the number of bus trips would be larger than the off-peak time. If the number of bus trips were more frequent than the optimal condition, it would make a high operating cost for bus operator. Conversely, if the number of trip was less than optimal condition, it would make a bad quality service for passengers. In this paper, the bus timetabling problem would be solved by integer programming model with modified genetic algorithm. Modification was placed in the chromosomes design, initial population recovery technique, chromosomes reconstruction and chromosomes extermination on specific generation. The result of this model gave the optimal solution with accuracy 99.1%.

Electrical system architecture having high voltage bus

DOEpatents

Hoff, Brian Douglas [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL

2011-03-22

An electrical system architecture is disclosed. The architecture has a power source configured to generate a first power, and a first bus configured to receive the first power from the power source. The architecture also has a converter configured to receive the first power from the first bus and convert the first power to a second power, wherein a voltage of the second power is greater than a voltage of the first power, and a second bus configured to receive the second power from the converter. The architecture further has a power storage device configured to receive the second power from the second bus and deliver the second power to the second bus, a propulsion motor configured to receive the second power from the second bus, and an accessory motor configured to receive the second power from the second bus.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Lijuan; Gonder, Jeff; Burton, Evan

This study evaluates the costs and benefits associated with the use of a plug-in hybrid electric bus and determines the cost effectiveness relative to a conventional bus and a hybrid electric bus. A sensitivity sweep analysis was performed over a number of a different battery sizes, charging powers, and charging stations. The net present value was calculated for each vehicle design and provided the basis for the design evaluation. In all cases, given present day economic assumptions, the conventional bus achieved the lowest net present value while the optimal plug-in hybrid electric bus scenario reached lower lifetime costs than themore » hybrid electric bus. The study also performed parameter sensitivity analysis under low market potential assumptions and high market potential assumptions. The net present value of plug-in hybrid electric bus is close to that of conventional bus.« less

Working conditions of bus drivers in the private sector and bus crashes in Kandy district, Sri Lanka: a case-control study.

PubMed

Jayatilleke, A U; Nakahara, S; Dharmaratne, S D; Jayatilleke, A C; Poudel, K C; Jimba, M

2009-04-01

To explore the effects of working conditions of private-bus drivers on bus crashes in Kandy district, Sri Lanka. A case-control study was carried out from August to September 2006. All private-bus drivers registered in Kandy district and involved in crashes reported to the police between November 2005 and April 2006 (n = 63) were selected as cases. Two control groups were included: private-bus drivers working on the same routes as the case drivers (n = 90) and private-bus drivers selected randomly from other routes of the district (n = 111). Data were collected using an anonymous self-administered questionnaire. Associations between working conditions and crashes were analysed using logistic regression. A strong association was observed between drivers' disagreements about working hours and bus crashes (matched controls, adjusted odds ratio (AOR) 5.98, 95% CI 1.02 to 34.90; unmatched controls, AOR 18.74, 95% CI 2.00 to 175.84). A significant association was also observed between low salaries (

Determination of an Optimal Commercial Data Bus Architecture for a Flight Data System

NASA Technical Reports Server (NTRS)

Crawford, Kevin; Johnson, Martin; Humphries, Rick (Technical Monitor)

2001-01-01

NASA/Marshall Space Flight Center (MSFC) is continually looking for methods to reduce cost and schedule while keeping the quality of work high. MSFC is NASA's lead center for space transportation and microgravity research. When supporting NASA's programs several decisions concerning the avionics system must be made. Usually many trade studies must be conducted to determine the best ways to meet the customer's requirements. When deciding the flight data system, one of the first trade studies normally conducted is the determination of the data bus architecture. The schedule, cost, reliability, and environments are some of the factors that are reviewed in the determination of the data bus architecture. Based on the studies, the data bus architecture could result in a proprietary data bus or a commercial data bus. The cost factor usually removes the proprietary data bus from consideration. The commercial data bus's range from Versa Module Eurocard (VME) to Compact PCI to STD 32 to PC 104. If cost, schedule and size are prime factors, VME is usually not considered. If the prime factors are cost, schedule, and size then Compact PCI, STD 32 and PC104 are the choices for the data bus architecture. MSFC's center director has funded a study from his discretionary fund to determine an optimal low cost commercial data bus architecture. The goal of the study is to functionally and environmentally test Compact PCI, STD 32 and PC 104 data bus architectures. This paper will summarize the results of the data bus architecture study.

Parallel approaches to composite production: interfaces that behave contrary to expectation.

PubMed

Frowd, Charlie D; Bruce, Vicki; Ness, Hayley; Bowie, Leslie; Paterson, Jenny; Thomson-Bogner, Claire; McIntyre, Alexander; Hancock, Peter J B

2007-04-01

This paper examines two facial composite systems that present multiple faces during construction to more closely resemble natural face processing. A 'parallel' version of PRO-fit was evaluated, which presents facial features in sets of six or twelve, and EvoFIT, a system in development, which contains a holistic face model and an evolutionary interface. The PRO-fit parallel interface turned out not to be quite as good as the 'serial' version as it appeared to interfere with holistic face processing. Composites from EvoFIT were named almost three times better than PRO-fit, but a benefit emerged under feature encoding, suggesting that recall has a greater role for EvoFIT than was previously thought. In general, an advantage was found for feature encoding, replicating a previous finding in this area, and also for a novel 'holistic' interview.

Interface-Free Area-Scalable Self-Powered Electroluminescent System Driven by Triboelectric Generator

PubMed Central

Yan Wei, Xiao; Kuang, Shuang Yang; Yang Li, Hua; Pan, Caofeng; Zhu, Guang; Wang, Zhong Lin

2015-01-01

Self-powered system that is interface-free is greatly desired for area-scalable application. Here we report a self-powered electroluminescent system that consists of a triboelectric generator (TEG) and a thin-film electroluminescent (TFEL) lamp. The TEG provides high-voltage alternating electric output, which fits in well with the needs of the TFEL lamp. Induced charges pumped onto the lamp by the TEG generate an electric field that is sufficient to excite luminescence without an electrical interface circuit. Through rational serial connection of multiple TFEL lamps, effective and area-scalable luminescence is realized. It is demonstrated that multiple types of TEGs are applicable to the self-powered system, indicating that the system can make use of diverse mechanical sources and thus has potentially broad applications in illumination, display, entertainment, indication, surveillance and many others. PMID:26338365

Design and fabrication of an angle-scanning based platform for the construction of surface plasmon resonance biosensor

NASA Astrophysics Data System (ADS)

Hu, Jiandong; Cao, Baiqiong; Wang, Shun; Li, Jianwei; Wei, Wensong; Zhao, Yuanyuan; Hu, Xinran; Zhu, Juanhua; Jiang, Min; Sun, Xiaohui; Chen, Ruipeng; Ma, Liuzheng

2016-03-01

A sensing system for an angle-scanning optical surface-plasmon-resonance (SPR) based biosensor has been designed with a laser line generator in which a P polarizer is embedded to utilize as an excitation source for producing the surface plasmon wave. In this system, the emitting beam from the laser line generator is controlled to realize the angle-scanning using a variable speed direct current (DC) motor. The light beam reflected from the prism deposited with a 50 nm Au film is then captured using the area CCD array which was controlled by a personal computer (PC) via a universal serial bus (USB) interface. The photoelectric signals from the high speed digital camera (an area CCD array) were converted by a 16 bit A/D converter before it transferred to the PC. One of the advantages of this SPR biosensing platform is greatly demonstrated by the label-free and real-time bio-molecular analysis without moving the area CCD array by following the laser line generator. It also could provide a low-cost surface plasmon resonance platform to improve the detection range in the measurement of bioanalytes. The SPR curve displayed on the PC screen promptly is formed by the effective data from the image on the area CCD array and the sensing responses of the platform to bulk refractive indices were calibrated using various concentrations of ethanol solution. These ethanol concentrations indicated with volumetric fraction of 5%, 10%, 15%, 20%, and 25%, respectively, were experimented to validate the performance of the angle-scanning optic SPR biosensing platform. As a result, the SPR sensor was capable to detect a change in the refractive index of the ethanol solution with the relative high linearity at the correlation coefficient of 0.9842. This greatly enhanced detection range is obtained from the position relationship between the laser line generator and the right-angle prism to allow direct quantification of the samples over a wide range of concentrations.

Power System Test and Verification at Satellite Level

NASA Astrophysics Data System (ADS)

Simonelli, Giulio; Mourra, Olivier; Tonicello, Ferdinando

2008-09-01

Most of the articles on Power Systems deal with the architecture and technical solutions related to the functionalities of the power system and their performances. Very few articles, if none, address integration and verification aspects of the Power System at satellite level and the related issues with the Power EGSE (Electrical Ground Support Equipment), which, also, have to support the AIT/AIV (Assembly Integration Test and Verification) program of the satellite and, eventually, the launch campaign. In the last years a more complex development and testing concept based on MDVE (Model Based Development and Verification Environment) has been introduced. In the MDVE approach the simulation software is used to simulate the Satellite environment and, in the early stages, the satellites units. This approach changed significantly the Power EGSE requirements. Power EGSEs or, better, Power SCOEs (Special Check Out Equipment) are now requested to provide the instantaneous power generated by the solar array throughout the orbit. To achieve that, the Power SCOE interfaces to the RTS (Real Time Simulator) of the MDVE. The RTS provides the instantaneous settings, which belong to that point along the orbit, to the Power SCOE so that the Power SCOE generates the instantaneous {I,V} curve of the SA (Solar Array). That means a real time test for the power system, which is even more valuable for EO (Earth Observation) satellites where the Solar Array aspect angle to the sun is rarely fixed, and the power load profile can be particularly complex (for example, in radar applications). In this article the major issues related to integration and testing of Power Systems will be discussed taking into account different power system topologies (i.e. regulated bus, unregulated bus, battery bus, based on MPPT or S3R…). Also aspects about Power System AIT I/Fs (interfaces) and Umbilical I/Fs with the launcher and the Power SCOE I/Fs will be addressed. Last but not least, protection strategy of the Power System during AIT/AIV program will also be discussed. The objective of this discussion is also to provide the Power System Engineer with a checklist of key aspects linked to the satellite AIT/AIV program, that have to be considered in the early phases of a new power system development.

Integration of a MicroCAT Propulsion System and a PhoneSat Bus into a 1.5U CubeSat

NASA Technical Reports Server (NTRS)

Agasid, Elwood Floyd; Perez, Andres Dono; Gazulla, Oriol Tintore; Trinh, Greenfield Tran; Uribe, Eddie Anthony; Keidar, Michael; Haque, Samudra; Teel, George

2014-01-01

NASA Ames Research Center and the George Washington University have developed an electric propulsion subsystem that can be integrated into the PhoneSat bus. Experimental tests have shown a reliable performance by firing three different thrusters at various frequencies in vacuum conditions. The three thrusters were controlled by a SmartPhone that was running the PhoneSat software. The subsystem is fully operational and it requires low average power to function (about 0.1 W). The interface consists of a microcontroller that sends a trigger pulses to the PPU (Plasma Processing Unit), which is responsible for the thruster operation. Frequencies ranging from 1 to 50Hz have been tested, showing a strong flexibility. A SmartPhone acts as the main user interface for the selection of commands that control the entire system. The micro cathode arc thruster MicroCAT provides a high 1(sub sp) of 3000s that allows a 4kg satellite to obtain a (delta)V of 300m/s. The system mass is only 200g with a total of volume of 200(cu cm). The propellant is based on a solid cylinder made of Titanium, which is the cathode at the same time. This simplicity in the design avoids miniaturization and manufacturing problems. The characteristics of this thruster allow an array of MicroCATs to perform attitude control and orbital correcton maneuvers that will open the door for the implementation of an extensive collection of new mission concepts and space applications for CubeSats. NASA Ames is currently working on the integration of the system to fit the thrusters and PPU inside a 1.5U CubeSat together with the PhoneSat bus into a 1.5U CubeSat. This satellite is intended to be deployed from the ISS in 2015 and test the functionality of the thrusters by spinning the satellite around its long axis and measure the rotational speed with the phone byros. This test flight will raise the TRL of the propulsion system from 5 to 7 and will be a first test for further CubeSats with propulsion systems, a key subsystem for long duration or interplanetary CubeSat missions.

77 FR 27277 - FTA Supplemental Fiscal Year 2012 Apportionments, Allocations, and Program Information

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-09

... allocates Section 5309 Bus and Bus Facilities funds to bus testing and the Fuel Cell program. Tables... Fuel Cell program. FTA will issue a supplemental notice at a later date if additional contract... allocated CA, GA, MA E2012-BUSP-018 Fuel Cell Bus Program..... $13,500,000 PA E2012-BUSP-019 Bus Testing 3...

40 CFR 85.1404 - Maintenance of records for urban bus operators; submittal of information; right of entry.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 40 Protection of Environment 19 2014-07-01 2014-07-01 false Maintenance of records for urban bus... SOURCES Urban Bus Rebuild Requirements § 85.1404 Maintenance of records for urban bus operators; submittal of information; right of entry. (a) The operator of any urban bus for which this subpart is...

40 CFR 85.1404 - Maintenance of records for urban bus operators; submittal of information; right of entry.

Code of Federal Regulations, 2012 CFR

2012-07-01

... 40 Protection of Environment 19 2012-07-01 2012-07-01 false Maintenance of records for urban bus... SOURCES Urban Bus Rebuild Requirements § 85.1404 Maintenance of records for urban bus operators; submittal of information; right of entry. (a) The operator of any urban bus for which this subpart is...

40 CFR 85.1404 - Maintenance of records for urban bus operators; submittal of information; right of entry.

Code of Federal Regulations, 2013 CFR

2013-07-01

... 40 Protection of Environment 19 2013-07-01 2013-07-01 false Maintenance of records for urban bus... SOURCES Urban Bus Rebuild Requirements § 85.1404 Maintenance of records for urban bus operators; submittal of information; right of entry. (a) The operator of any urban bus for which this subpart is...

40 CFR 85.1404 - Maintenance of records for urban bus operators; submittal of information; right of entry.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 40 Protection of Environment 18 2011-07-01 2011-07-01 false Maintenance of records for urban bus... SOURCES Urban Bus Rebuild Requirements § 85.1404 Maintenance of records for urban bus operators; submittal of information; right of entry. (a) The operator of any urban bus for which this subpart is...

Bus Stops and Pedestrian-Motor Vehicle Collisions in Lima, Peru: A Matched Case-Control Study

PubMed Central

Quistberg, D. Alex; Koepsell, Thomas D.; Johnston, Brian D.; Boyle, Linda Ng; Miranda, J. Jaime; Ebel, Beth E.

2015-01-01

Objective To evaluate the relationship between bus stop characteristics and pedestrian-motor vehicle collisions. Design Matched case-control study where the units of study were pedestrian crossing. Setting Random sample of 11 police commissaries in Lima, Peru. Data collection occurred from February, 2011 to September, 2011. Participants 97 intersection cases representing 1,134 collisions and 40 mid-block cases representing 469 collisions that occurred between October, 2010 and January, 2011 and their matched controls. Main Exposures Presence of a bus stop and specific bus stop characteristics. Main Outcome Occurrence of a pedestrian-motor vehicle collision. Results Intersections with bus stops were three times more likely to have a pedestrian-vehicle collision (OR 3.28, 95% CI 1.53-7.03), relative to intersections without bus stops. Both formal and informal bus stops were associated with a higher odds of a collision at intersections (OR 6.23, 95% CI 1.76-22.0 and OR 2.98, 1.37-6.49). At mid-block sites, bus stops on a bus-dedicated transit lane were also associated with collision risk (OR 2.36, 95% CI 1.02-5.42). All bus stops were located prior to the intersection, contrary to practices in most high income countries. Conclusions In urban Lima, the presence of a bus stop was associated with a three-fold increase in risk of a pedestrian collision. The highly competitive environment among bus companies may provide an economic incentive for risky practices such as dropping off passengers in the middle of traffic and jockeying for position with other buses. Bus stop placement should be considered to improve pedestrian safety. PMID:24357516

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Miniaturized high throughput detection system for capillary array electrophoresis on chip with integrated light emitting diode array as addressed ring-shaped light source.

PubMed

Ren, Kangning; Liang, Qionglin; Mu, Xuan; Luo, Guoan; Wang, Yiming

2009-03-07

A novel miniaturized, portable fluorescence detection system for capillary array electrophoresis (CAE) on a microfluidic chip was developed, consisting of a scanning light-emitting diode (LED) light source and a single point photoelectric sensor. Without charge coupled detector (CCD), lens, fibers and moving parts, the system was extremely simplified. Pulsed driving of the LED significantly increased the sensitivity, and greatly reduced the power consumption and photobleaching effect. The highly integrated system was robust and easy to use. All the advantages realized the concept of a portable micro-total analysis system (micro-TAS), which could work on a single universal serial bus (USB) port. Compared with traditional CAE detecting systems, the current system could scan the radial capillary array with high scanning rate. An 8-channel CAE of fluorescein isothiocyanate (FITC) labeled arginine (Arg) on chip was demonstrated with this system, resulting in a limit of detection (LOD) of 640 amol.

A design proposal of a certain missile tactical command system based on Beidou satellite communication and GPS positioning techniques

NASA Astrophysics Data System (ADS)

Ma, Jian; Hao, Yongsheng; Miao, Jian; Zhang, Jianmao

2007-11-01

This paper introduced a design proposal of tactical command system that applied to a kind of anti-tank missile carriers. The tactical command system was made up of embedded computer system based on PC104 bus, Linux operating system, digital military map, Beidou satellite communication equipments and GPS positioning equipments. The geographic coordinates was measured by the GPS receiver, the positioning data, commands and information were transmitted real-time between tactical command systems, tactical command systems and command center, by the Beidou satellite communication systems. The Beidou satellite communication equipments and GPS positioning equipments were integrated to an independent module, exchanging data with embedded computer through RS232 serial ports and USB ports. The decision support system software based on information fusion, calculates positioning data, geography information and battle field information synthetically, shows the position of allies and the position of enemy on the military map, and assesses the various threats of different enemy objects, educes a situation assessment and threat assessment.

Personal graphical communicator.

PubMed

Stephens, Michael; Barrett, Steven

2008-01-01

A device to help a child communicate was requested by an educator. The child cannot read, write, or speak but can recognize symbols and use those symbols to communicate. While this communication works, it doesn't work well in situations where another person does not know how to use the symbols to communicate. For this reason, a device was requested that could display images to a child and play a phrase when that image was chosen. To meet this need an MP3 player like device was constructed. The device stores images and Mpeg-Layer III (MP3) sound clips on a replaceable Secure Digital (SD) card. The images are displayed on a color Liquid Crystal Display (LCD) where the user is able to skip through images to find the phrase that needs to be said. Once found simply hitting the play button will play the sound clip associated with the image. The device is portable and compact for easy use. It uses Universal Serial Bus (USB) to recharge its batteries, communicate with the PC and update the firmware.

x-y-recording in transmission electron microscopy. A versatile and inexpensive interface to personal computers with application to stereology.

PubMed

Rickmann, M; Siklós, L; Joó, F; Wolff, J R

1990-09-01

An interface for IBM XT/AT-compatible computers is described which has been designed to read the actual specimen stage position of electron microscopes. The complete system consists of (i) optical incremental encoders attached to the x- and y-stage drivers of the microscope, (ii) two keypads for operator input, (iii) an interface card fitted to the bus of the personal computer, (iv) a standard configuration IBM XT (or compatible) personal computer optionally equipped with a (v) HP Graphic Language controllable colour plotter. The small size of the encoders and their connection to the stage drivers by simple ribbed belts allows an easy adaptation of the system to most electron microscopes. Operation of the interface card itself is supported by any high-level language available for personal computers. By the modular concept of these languages, the system can be customized to various applications, and no computer expertise is needed for actual operation. The present configuration offers an inexpensive attachment, which covers a wide range of applications from a simple notebook to high-resolution (200-nm) mapping of tissue. Since section coordinates can be processed in real-time, stereological estimations can be derived directly "on microscope". This is exemplified by an application in which particle numbers were determined by the disector method.

Intranet and Internet metrological workstation with photonic sensors and transmission

NASA Astrophysics Data System (ADS)

Romaniuk, Ryszard S.; Pozniak, Krzysztof T.; Dybko, Artur

1999-05-01

We describe in this paper a part of a telemetric network which consists of a workstation with photonic measurement and communication interfaces, structural fiber optic cabling (10/100BaseFX and CAN-FL), and photonic sensors with fiber optic interfaces. The station is equipped with direct photonic measurement interface and most common measuring standards converter (RS, GPIB) with fiber optic I/O CAN bus, O/E converters, LAN and modem ports. The station was connected to the Intranet (ipx/spx) and Internet (tcp/ip) with separate IP number and DNS, WINS names. Virtual measuring environment system program was written specially for such an Intranet and Internet station. The measurement system program communicated with the user via a Graphical User's Interface (GUI). The user has direct access to all functions of the measuring station system through appropriate layers of GUI: telemetric, transmission, visualization, processing, information, help and steering of the measuring system. We have carried out series of thorough simulation investigations and tests of the station using WWW subsystem of the Internet. We logged into the system through the LAN and via modem. The Internet metrological station works continuously under the address http://nms.ipe.pw.edu.pl/nms. The station and the system hear the short name NMS (from Network Measuring System).

The design and implementation of a windowing interface pinch force measurement system

NASA Astrophysics Data System (ADS)

Ho, Tze-Yee; Chen, Yuanu-Joan; Chung, Chin-Teng; Hsiao, Ming-Heng

2010-02-01

This paper presents a novel windowing interface pinch force measurement system that is basically based on an USB (Universal Series Bus) microcontroller which mainly processes the sensing data from the force sensing resistance sensors mounted on five digits. It possesses several friendly functions, such as the value and curve trace of the applied force by a hand injured patient displayed in real time on a monitoring screen, consequently, not only the physician can easily evaluate the effect of hand injury rehabilitation, but also the patients get more progressive during the hand physical therapy by interacting with the screen of pinch force measurement. In order to facilitate the pinch force measurement system and make it friendly, the detail hardware design and software programming flowchart are described in this paper. Through a series of carefully and detailed experimental tests, first of all, the relationship between the applying force and the FSR sensors are measured and verified. Later, the different type of pinch force measurements are verified by the oscilloscope and compared with the corresponding values and waveform traces in the window interface display panel to obtain the consistency. Finally, a windowing interface pinch force measurement system based on the USB microcontroller is implemented and demonstrated. The experimental results show the verification and feasibility of the designed system.

Independent Orbiter Assessment (IOA): Analysis of the DPS subsystem

NASA Technical Reports Server (NTRS)

Lowery, H. J.; Haufler, W. A.; Pietz, K. C.

1986-01-01

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis/Critical Items List (FMEA/CIL) is presented. The IOA approach features a top-down analysis of the hardware to independently determine failure modes, criticality, and potential critical items. The independent analysis results corresponding to the Orbiter Data Processing System (DPS) hardware are documented. The DPS hardware is required for performing critical functions of data acquisition, data manipulation, data display, and data transfer throughout the Orbiter. Specifically, the DPS hardware consists of the following components: Multiplexer/Demultiplexer (MDM); General Purpose Computer (GPC); Multifunction CRT Display System (MCDS); Data Buses and Data Bus Couplers (DBC); Data Bus Isolation Amplifiers (DBIA); Mass Memory Unit (MMU); and Engine Interface Unit (EIU). The IOA analysis process utilized available DPS hardware drawings and schematics for defining hardware assemblies, components, and hardware items. Each level of hardware was evaluated and analyzed for possible failure modes and effects. Criticality was assigned based upon the severity of the effect for each failure mode. Due to the extensive redundancy built into the DPS the number of critical items are few. Those identified resulted from premature operation and erroneous output of the GPCs.

Transition from lab to flight demo for model-based FLIR ATR and SAR-FLIR fusion

NASA Astrophysics Data System (ADS)

Childs, Martin B.; Carlson, Karen M.; Pujara, Neeraj

2000-08-01

Model-based automatic target recognition (ATR) using forward- looking infrared (FLIR) imagery, and using FLIR imagery combined with cues from a synthetic aperture radar (SAR) system, has been successfully demonstrated in the laboratory. For the laboratory demonstration, FLIR images, platform location, sensor data, and SAR cues were read in from files stored on computer disk. This ATR system, however, was intended to ultimately be flown in a fighter aircraft. We discuss the transition from laboratory demonstration to flight demonstration for this system. The obvious changes required were in the interfaces: the flight system must get live FLIR imagery from a sensor; it must get platform location, sensor data, and controls from the avionics computer in the aircraft via 1553 bus; and it must get SAR cues from the on-board SAR system, also via 1553 bus. Other changes included the transition to rugged hardware that would withstand the fighter aircraft environment, and the need for the system to be compact and self-contained. Unexpected as well as expected challenges were encountered. We discuss some of these challenges, how they were met, and the performance of the flight-demonstration system.

DARPA Orbital Express program: effecting a revolution in space-based systems

NASA Astrophysics Data System (ADS)

Whelan, David A.; Adler, E. A.; Wilson, Samuel B., III; Roesler, Gordon M., Jr.

2000-11-01

A primary goal of the Defense Advanced Research Projects Agency is to develop innovative, high-risk technologies with the potential of a revolutionary impact on missions of the Department of Defense. DARPA is developing a space experiment to prove the feasibility of autonomous on- orbit servicing of spacecraft. The Orbital Express program will demonstrate autonomous on-orbit refueling, as well as autonomous delivery of a small payload representing an avionics upgrade package. The maneuverability provided to spacecraft from a ready refueling infrastructure will enable radical new capabilities for the military, civil and commercial spacecraft. Module replacement has the potential to extend bus lifetimes, and to upgrade the performance of key subsystems (e.g. processors) at the pace of technology development. The Orbital Express technology development effort will include the necessary autonomy for a viable servicing infrastructure; a universal interface for docking, refueling and module transfers; and a spacecraft bus design compatible with this servicing concept. The servicer spacecraft of the future may be able to act as a host platform for microsatellites, extending their capabilities while reducing risk. An infrastructure based on Orbital Express also benefits from, and stimulates the development of, lower-cost launch strategies.

IEEE 1393 Spaceborne Fiber Optic Data Bus: A Standard Approach to On-Board Payload Data Handling Networks for the AIAA Space Technology Conference and Exposition "Partnering in the 21th Century"

NASA Technical Reports Server (NTRS)

Andrucyk, Dennis J.; Orlando, Fred J.; Chalfant, Charles H.

1999-01-01

The Spaceborne Fiber Optic Data Bus (SFODB) is the next generation in on-board data handling networks. It will do for high speed payloads what SAE 1773 has done for on-board command and telemetry systems. That is, it will significantly reduce the cost of payload development, integration and test through interface standardization. As defined in IEEE 1393, SFODB is a 1 Gb/s, fiber optic network specifically designed to support the real-time, on-board data handling requirements of remote sensing spacecraft. The network is highly reliable, fault tolerant, and capable of withstanding the rigors of launch and the harsh space environment. SFODB achieves this operational and environmental performance while maintaining the small size, light weight, and low power necessary for spaceborne applications. SFODB was developed jointly by DoD and NASA GSFC to meet the on-board data handling needs of Remote Sensing satellites. This jointly funded project produced a complete set of flight transmitters, receivers and protocol ASICS; a complete Development & Evaluation System; and, the IEEE 1393 standard.

Oxygen Generation System Laptop Bus Controller Flight Software

NASA Technical Reports Server (NTRS)

Rowe, Chad; Panter, Donna

2009-01-01

The Oxygen Generation System Laptop Bus Controller Flight Software was developed to allow the International Space Station (ISS) program to activate specific components of the Oxygen Generation System (OGS) to perform a checkout of key hardware operation in a microgravity environment, as well as to perform preventative maintenance operations of system valves during a long period of what would otherwise be hardware dormancy. The software provides direct connectivity to the OGS Firmware Controller with pre-programmed tasks operated by on-orbit astronauts to exercise OGS valves and motors. The software is used to manipulate the pump, separator, and valves to alleviate the concerns of hardware problems due to long-term inactivity and to allow for operational verification of microgravity-sensitive components early enough so that, if problems are found, they can be addressed before the hardware is required for operation on-orbit. The decision was made to use existing on-orbit IBM ThinkPad A31p laptops and MIL-STD-1553B interface cards as the hardware configuration. The software at the time of this reporting was developed and tested for use under the Windows 2000 Professional operating system to ensure compatibility with the existing on-orbit computer systems.

Devices development and techniques research for space life sciences

NASA Astrophysics Data System (ADS)

Zhang, A.; Liu, B.; Zheng, C.

The development process and the status quo of the devices and techniques for space life science in China and the main research results in this field achieved by Shanghai Institute of Technical Physics SITP CAS are reviewed concisely in this paper On the base of analyzing the requirements of devices and techniques for supporting space life science experiments and researches one designment idea of developing different intelligent modules with professional function standard interface and easy to be integrated into system is put forward and the realization method of the experiment system with intelligent distributed control based on the field bus are discussed in three hierarchies Typical sensing or control function cells with certain self-determination control data management and communication abilities are designed and developed which are called Intelligent Agents Digital hardware network system which are consisted of the distributed Agents as the intelligent node is constructed with the normative opening field bus technology The multitask and real-time control application softwares are developed in the embedded RTOS circumstance which is implanted into the system hardware and space life science experiment system platform with characteristic of multitasks multi-courses professional and instant integration will be constructed

Importance of balanced architectures in the design of high-performance imaging systems

NASA Astrophysics Data System (ADS)

Sgro, Joseph A.; Stanton, Paul C.

1999-03-01

Imaging systems employed in demanding military and industrial applications, such as automatic target recognition and computer vision, typically require real-time high-performance computing resources. While high- performances computing systems have traditionally relied on proprietary architectures and custom components, recent advances in high performance general-purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems. A common pitfall in the design of high performance imaging system, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth. The performance of standard cluster designs, for example, in which several processors share a common memory bus, is typically constrained by memory bandwidth. The symptom characteristic of this problem is failure to the performance of the system to scale as more processors are added. The problem becomes exacerbated if I/O and memory functions share the same bus. The recent introduction of microprocessors with large internal caches and high performance external memory interfaces makes it practical to design high performance imaging system with balanced computational and memory bandwidth. Real word examples of such designs will be presented, along with a discussion of adapting algorithm design to best utilize available memory bandwidth.

Replication of Space-Shuttle Computers in FPGAs and ASICs

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.

2008-01-01

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

Common Traffic Violations of Bus Drivers in Urban China: An Observational Study.

PubMed

Wang, Qiqi; Zhang, Wei; Yang, Rendong; Huang, Yuanxiu; Zhang, Lin; Ning, Peishan; Cheng, Xunjie; Schwebel, David C; Hu, Guoqing; Yao, Hongyan

2015-01-01

To report common traffic violations in bus drivers and the factors that influence those violations in urban China. We conducted an observational study to record three types of traffic violations among bus drivers in Changsha City, China: illegal stopping at bus stations, violating traffic light signals, and distracted driving. The behaviors of bus drivers on 32 routes (20% of bus routes in the city) were observed. A two-level Poisson regression examined factors that predicted bus driver violations. The incidence of illegal stopping at bus stations was 20.2%. Illegal stopping was less frequent on weekends, sunny days, and at stations with cameras, with adjusted incidence rate ratios (IRRs) of 0.81, 0.65 and 0.89, respectively. The incidence of violating traffic light signals was 2.2%, and was lower on cloudy than sunny days (adjusted IRR: 0.60). The incidence of distracted driving was 3.3%. The incidence of distracted driving was less common on cloudy days, rainy or snowy days, and foggy/windy/dusty days compared to sunny days, with adjusted IRRs of 0.54, 0.55 and 0.07, respectively. Traffic violations are common in bus drivers in urban China and they are associated with the date, weather, and presence of traffic cameras at bus station. Further studies are recommended to understand the behavioral mechanisms that may explain bus driver violations and to develop feasible prevention measures.

58. VIEW OF SIGNAL BUS SECTION NUMBER 2 LOCATED OVER ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

58. VIEW OF SIGNAL BUS SECTION NUMBER 2 LOCATED OVER THE CONTROL ROOM MEZZANINE IN THE SIGNAL POWER CONDITIONING ROOM. BUS IS A HEAVY COPPER BAR APPROXIMATELY 1/2" BY 4" WHICH CONDUCTS POWER THROUGHOUT THE POWER PLANT. BUS ARE PROTECTED BY A BRICK AND SOAPSTONE HOUSING. OPENINGS FOR INSPECTION AND ACCESS WOULD NORMALLY BE PROTECTED BY GLASS DOORS. THE BUS WOULD BE SUPPORTED ON INSULATORS WITHIN THE BRICK CHAMBER. BUS WAS REMOVED AND SALVAGED WHEN THE STATION WAS ABANDONED. THE OBJECT IN THE TOP CENTER OF THE PHOTOGRAPH IS A POTENTIAL TRANSFORMER USED TO REDUCE BUS POTENTIAL OF 2200 VOLTS TO LOW VOLTAGES SAFE FOR USE IN CONTROL ROOM CIRCUITRY. POTENTIAL TRANSFORMERS ARE PRECISION DEVICES WHICH PRODUCE AN ACCURATE LOW VOLTAGE ANALOG OF THE HIGH VOLTAGE ON THE BUS. - New York, New Haven & Hartford Railroad, Cos Cob Power Plant, Sound Shore Drive, Greenwich, Fairfield County, CT

Scalable SCPPM Decoder

NASA Technical Reports Server (NTRS)

Quir, Kevin J.; Gin, Jonathan W.; Nguyen, Danh H.; Nguyen, Huy; Nakashima, Michael A.; Moision, Bruce E.

2012-01-01

A decoder was developed that decodes a serial concatenated pulse position modulation (SCPPM) encoded information sequence. The decoder takes as input a sequence of four bit log-likelihood ratios (LLR) for each PPM slot in a codeword via a XAUI 10-Gb/s quad optical fiber interface. If the decoder is unavailable, it passes the LLRs on to the next decoder via a XAUI 10-Gb/s quad optical fiber interface. Otherwise, it decodes the sequence and outputs information bits through a 1-GB/s Ethernet UDP/IP (User Datagram Protocol/Internet Protocol) interface. The throughput for a single decoder unit is 150-Mb/s at an average of four decoding iterations; by connecting a number of decoder units in series, a decoding rate equal to that of the aggregate rate is achieved. The unit is controlled through a 1-GB/s Ethernet UDP/IP interface. This ground station decoder was developed to demonstrate a deep space optical communication link capability, and is unique in the scalable design to achieve real-time SCPP decoding at the aggregate data rate.

7. YOSEMITE VALLEY SHUTTLE BUS AT SENTINEL BRIDGE SHUTTLE BUS ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

7. YOSEMITE VALLEY SHUTTLE BUS AT SENTINEL BRIDGE SHUTTLE BUS AND PARKING LOT AREA. LOOKING WNW. GIS: N-37 40 36.2 / W-119 44 45.0 - Yosemite National Park Roads & Bridges, Yosemite Village, Mariposa County, CA

GO Bus impact analysis.

DOT National Transportation Integrated Search

2013-08-01

NJ TRANSIT launched two relatively new enhanced bus services: GO 25 serving the : Springfield Avenue corridor in 2008 and GO 28 serving the Bloomfield Avenue corridor in 2009. : As an enhanced but not full Bus Rapid Transit (BRT) service, GO Bus feat...