A chiral-based magnetic memory device without a permanent magnet

PubMed Central

Dor, Oren Ben; Yochelis, Shira; Mathew, Shinto P.; Naaman, Ron; Paltiel, Yossi

2013-01-01

Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices. PMID:23922081

A chiral-based magnetic memory device without a permanent magnet.

PubMed

Ben Dor, Oren; Yochelis, Shira; Mathew, Shinto P; Naaman, Ron; Paltiel, Yossi

2013-01-01

Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Accessing memory

DOEpatents

Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganthan, Parthasarathy

2017-09-26

A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

77 FR 22760 - Proposed Information Collection; Comment Request; Southeast Region Gulf of Mexico Electronic...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-17

... electronic logbook memory chip will be removed from the unit and downloaded at the contractor site in College Station, Texas. A new logbook memory chip will replace the removed memory chip, a process taking less than...

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Producing Silicon Carbide for Semiconductor Devices

NASA Technical Reports Server (NTRS)

Hsu, G. C.; Rohatgi, N. K.

1986-01-01

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

Voltage-Dependent Charge Storage in Cladded Zn0.56Cd0.44Se Quantum Dot MOS Capacitors for Multibit Memory Applications

NASA Astrophysics Data System (ADS)

Khan, J.; Lingalugari, M.; Al-Amoody, F.; Jain, F.

2013-11-01

As conventional memories approach scaling limitations, new storage methods must be utilized to increase Si yield and produce higher on-chip memory density. Use of II-VI Zn0.56Cd0.44Se quantum dots (QDs) is compatible with epitaxial gate insulators such as ZnS-ZnMgS. Voltage-dependent charging effects in cladded Zn0.56Cd0.44Se QDs are presented in a conventional metal-oxide-semiconductor capacitor structure. Charge storage capabilities in Si and ZnMgS QDs have been reported by various researchers; this work is focused on II-VI material Zn0.56Cd0.44Se QDs nucleated using photoassisted microwave plasma metalorganic chemical vapor deposition. Using capacitance-voltage hysteresis characterization, the multistep charging and discharging capabilities of the QDs at room temperature are presented. Three charging states are presented within a 10 V charging voltage range. These characteristics exemplify discrete charge states in the QD layer, perfect for multibit, QD-functionalized high-density memory applications. Multiple charge states with low operating voltage provide device characteristics that can be used for multibit storage by allowing varying charges to be stored in a QD layer based on the applied "write" voltage.

Spot-size converter with a SiO(2) spacer layer between tapered Si and SiON waveguides for fiber-to-chip coupling.

PubMed

Maegami, Yuriko; Takei, Ryohei; Omoda, Emiko; Amano, Takeru; Okano, Makoto; Mori, Masahiko; Kamei, Toshihiro; Sakakibara, Youichi

2015-08-10

We experimentally demonstrate low-loss and polarization-insensitive fiber-to-chip coupling spot-size converters (SSCs) comprised of a three dimensionally tapered Si wire waveguide, a SiON secondary waveguide, and a SiO(2) spacer inserted between them. Fabricated SSCs with the SiO(2) spacer exhibit fiber-to-chip coupling loss of 1.5 dB/facet for both the quasi-TE and TM modes and a small wavelength dependence in the C- and L-band regions. The SiON secondary waveguide is present only around the SSC region, which significantly suppresses the influence of the well-known N-H absorption of plasma-deposited SiON at around 1510 nm.

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

DTIC Science & Technology

2010-07-22

dependent , providing a natural bandwidth match between compute cores and the memory subsystem. • High Bandwidth Dcnsity. Waveguides crossing the chip...simulate this memory access architecture on a 2S6-core chip with a concentrated 64-node network lIsing detailed traces of high-performance embedded...memory modulcs, wc placc memory access poi nts (MAPs) around the pcriphery of the chip connected to thc nctwork. These MAPs, shown in Figure 4, contain

78 FR 49287 - Certain Flash Memory Chips and Products Containing the Same Correction to Notice of Receipt of...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-13

... INTERNATIONAL TRADE COMMISSION [Docket No 2971] Certain Flash Memory Chips and Products Containing the Same Correction to Notice of Receipt of Complaint; Solicitation of Comments Relating to the Public..., Certain Flash Memory Chips and Products Containing the Same, DN 2971; the Commission solicited comments on...

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

75 FR 82071 - In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-29

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission Decision Not To Review the ALJ'S Final... States after importation of certain flash memory chips and products containing the same by reason of...

75 FR 82071 - In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-29

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission Decision Not To Review the ALJ's Final... flash memory chips and products containing the same by reason of infringement of various claims of...

Rutger's CAM2000 chip architecture

NASA Technical Reports Server (NTRS)

Smith, Donald E.; Hall, J. Storrs; Miyake, Keith

1993-01-01

This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

PubMed

Chin, Fun-Tat; Lin, Yu-Hsien; You, Hsin-Chiang; Yang, Wen-Luh; Lin, Li-Min; Hsiao, Yu-Ping; Ko, Chum-Min; Chao, Tien-Sheng

2014-01-01

This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

Latest generation of ASICs for photodetector readout

NASA Astrophysics Data System (ADS)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Menglu; Tu, K. N., E-mail: kntu@ucla.edu; Kim, Dong Wook

Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si interposer was used between a polymer substrate and a device chip which has transistors. The interposer has no transistors. If transistors are added to the interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si interposer. The vertical connections between the interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chipmore » are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchrotron radiation tomography to compare three sets of microbumps in the test structure: microbumps under electromigration, microbumps under thermomigration, and microbumps under a constant temperature thermal annealing. The results show that the microbumps under thermomigration have the largest damage. Furthermore, simulation of temperature distribution in the test structure supports the finding of thermomigration.« less

Realization of 10 GHz minus 30dB on-chip micro-optical links with Si-Ge RF bi-polar technology

NASA Astrophysics Data System (ADS)

Ogudo, Kingsley A.; Snyman, Lukas W.; Polleux, Jean-Luc; Viana, Carlos; Tegegne, Zerihun

2014-06-01

Si Avalanche based LEDs technology has been developed in the 650 -850nm wavelength regime [1, 2]. Correspondingly, small micro-dimensioned detectors with pW/μm2 sensitivity have been developed for the same wavelength range utilizing Si-Ge detector technology with detection efficiencies of up to 0.85, and with a transition frequencies of up to 80 GHz [3] A series of on-chip optical links of 50 micron length, utilizing 650 - 850 nm propagation wavelength have been designed and realized, utilizing a Si Ge radio frequency bipolar process. Micron dimensioned optical sources, waveguides and detectors were all integrated on the same chip to form a complete optical link on-chip. Avalanche based Si LEDs (Si Av LEDs), Schottky contacting, TEOS densification strategies, silicon nitride based waveguides, and state of the art Si-Ge bipolar detector technologies were used as key design strategies. Best performances show optical coupling from source to detector of up to 10GHz and - 40dBm total optical link budget loss with a potential transition frequency coupling of up to 40GHz utilizing Si Ge based LEDs. The technology is particularly suitable for application as on-chip optical links, optical MEMS and MOEMS, as well as for optical interconnects utilizing low loss, side surface, waveguide- to-optical fiber coupling. Most particularly is one of our designed waveguide which have a good core axis alignment with the optical source and yield 10GHz -30dB on-chip micro-optical links as shown in Fig 9 (c). The technology as developed has been appropriately IP protected.

Thermal cycling reliability of Cu/SnAg double-bump flip chip assemblies for 100 μm pitch applications

NASA Astrophysics Data System (ADS)

Son, Ho-Young; Kim, Ilho; Lee, Soon-Bok; Jung, Gi-Jo; Park, Byung-Jin; Paik, Kyung-Wook

2009-01-01

A thick Cu column based double-bump flip chip structure is one of the promising alternatives for fine pitch flip chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip chip assemblies was investigated, and the failure mechanism was analyzed through the correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, T/C failures occurred at some Cu/SnAg bumps located at the edge and corner of chips. Scanning acoustic microscope analysis and scanning electron microscope observations indicated that the failure site was the Cu column/Si chip interface. It was identified by a FEA where the maximum stress concentration was located during T/C. During T/C, the Al pad between the Si chip and a Cu column bump was displaced due to thermomechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps and ultimately reduced the thermal cycling lifetime. The maximum equivalent plastic strains of some bumps at the chip edge increased with an increased number of thermal cycles. However, equivalent plastic strains of the inner bumps did not increase regardless of the number of thermal cycles. In addition, the z-directional normal plastic strain ɛ22 was determined to be compressive and was a dominant component causing the plastic deformation of Cu/SnAg double bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip and shear strains were accumulated on the Cu column bumps at the chip edge at low temperature region. Thus it was found that the Al pad at the Si chip/Cu column interface underwent thermal fatigue deformation by compressive normal strain and the contact loss by displacement failure of the Al pad, the main T/C failure mode of the Cu/SnAg flip chip assembly, then occurred at the Si chip/Cu column interface shear strain deformation during T/C.

Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

NASA Astrophysics Data System (ADS)

Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

2007-04-01

In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

The Energy Crisis

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Chip-based electronics in 2010 consumed about 10% of the world's total electric power of ˜2 TW. We have seen throughout the book that all segments, processing, memory and communication, are expected to increase their performance or bandwidth by three orders of magnitude in the decade until 2020. If this progress would be realized, the world semiconductor revenue could grow by 50-100%, and the ICT industry by 43-66% in this decade (Fig. 6.1). Progress sustained at these levels certainly depends on investments and qualified manpower, but energy has become another roadblock almost overnight. In this chapter, we touch upon the life-cycle energy of chips by assessing the energy of Si wafer manufacturing, needed to bring the chips to life, and the power efficiencies in their respective operations. An outstanding segment of power-hungry chip operations is that of operating data centers, often called server farms. Their total operating power was ˜36 GW in 2010, and we look at their evolution under the prospect of a 1,000× growth in performance by 2020. One feasible scenario is that we succeed in improving the power efficiency of Processing 1,000×, Memory 1,000×, Communication 100×, within a decade. In this case, the total required power for the world's data centers would still increase 4× to 144 GW by 2020, equivalent to 40% of the total electrical power available in all of Europe. The power prospects for mobile/wireless as well as long-line cable/radio/satellite are equally serious. Any progression by less than the factors listed above will lead to economic growth smaller than the projections given above. This demands clearly that sustainable nanoelectronics must be minimum-energy (femtojoule) electronics.

Maximizing Computational Capability with Minimal Power

DTIC Science & Technology

2009-03-01

Chip -Scale Energy and Power... and Heat Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting burden for the collection of...OpticalBench Mounting Posts Imager Chip LCDinterfaced withthecomputer P o l a r i z e r P o l a r i z e r XYZ Translator Optical Slide VMM Computational Pixel...Signal routing power / memory: ? Power does not include comm off chip (i.e. accessing memory) Power = ½ C Vdd2 f for CMOS Chip to Chip (10pF load min

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

A reliability evaluation methodology for memory chips for space applications when sample size is small

NASA Technical Reports Server (NTRS)

Chen, Y.; Nguyen, D.; Guertin, S.; Berstein, J.; White, M.; Menke, R.; Kayali, S.

2003-01-01

This paper presents a reliability evaluation methodology to obtain the statistical reliability information of memory chips for space applications when the test sample size needs to be kept small because of the high cost of the radiation hardness memories.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Blanket Gate Would Address Blocks Of Memory

NASA Technical Reports Server (NTRS)

Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

1988-01-01

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Novel memory architecture for video signal processor

NASA Astrophysics Data System (ADS)

Hung, Jen-Sheng; Lin, Chia-Hsing; Jen, Chein-Wei

1993-11-01

An on-chip memory architecture for video signal processor (VSP) is proposed. This memory structure is a two-level design for the different data locality in video applications. The upper level--Memory A provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level--Memory B provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. The needed memory size is decided by the memory usage analysis for video algorithms and the number of function units. Both levels of memory adopted a dual-port memory scheme to sustain the simultaneous read and write operations. Especially, Memory B uses multiple one-read-one-write memory banks to emulate the real multiport memory. Therefore, one can change the configuration of Memory B to several sets of memories with variable read/write ports by adjusting the bus switches. Then the numbers of read ports and write ports in proposed memory can meet requirement of data flow patterns in different video coding algorithms. We have finished the design of a prototype memory design using 1.2- micrometers SPDM SRAM technology and will fabricated it through TSMC, in Taiwan.

Chip-based molecularly imprinted monolithic capillary array columns coated GO/SiO2 for selective extraction and sensitive determination of rhodamine B in chili powder.

PubMed

Zhai, Haiyun; Huang, Lu; Chen, Zuanguang; Su, Zihao; Yuan, Kaisong; Liang, Guohuan; Pan, Yufang

2017-01-01

A novel solid-phase extraction chip embedded with array columns of molecularly imprinted polymer-coated silanized graphene oxide (GO/SiO2-MISPE) was established to detect trace rhodamine B (RB) in chili powder. GO/SiO2-MISPE monolithic columns for RB detection were prepared by optimizing the supporting substrate, template, and polymerizing monomer under mild water bath conditions. Adsorption capacity and specificity, which are critical properties for the application of the GO/SiO2-MISPE monolithic column, were investigated. GO/SiO2-MIP was examined by scanning electron microscopy (SEM) and Fourier transform-infrared spectroscopy. The recovery and the intraday and interday relative standard deviations for RB ranged from 83.7% to 88.4% and 2.5% to 4.0% and the enrichment factors were higher than 110-fold. The chip-based array columns effectively eliminated impurities in chili powder, indicating that the chip-based GO/SiO2-MISPE method was reliable for RB detection in food samples using high-performance liquid chromatography. Accordingly, this method has direct applications for monitoring potentially harmful dyes in processed food. Copyright © 2016 Elsevier Ltd. All rights reserved.

Data acquisition system issues for large experiments

NASA Astrophysics Data System (ADS)

Siskind, E. J.

2007-09-01

This talk consists of personal observations on two classes of data acquisition ("DAQ") systems for Silicon trackers in large experiments with which the author has been concerned over the last three or more years. The first half is a classic "lessons learned" recital based on experience with the high-level debug and configuration of the DAQ system for the GLAST LAT detector. The second half is concerned with a discussion of the promises and pitfalls of using modern (and future) generations of "system-on-a-chip" ("SOC") or "platform" field-programmable gate arrays ("FPGAs") in future large DAQ systems. The DAQ system pipeline for the 864k channels of Si tracker in the GLAST LAT consists of five tiers of hardware buffers which ultimately feed into the main memory of the (two-active-node) level-3 trigger processor farm. The data formats and buffer volumes of these tiers are briefly described, as well as the flow control employed between successive tiers. Lessons learned regarding data formats, buffer volumes, and flow control/data discard policy are discussed. The continued development of platform FPGAs containing large amounts of configurable logic fabric, embedded PowerPC hard processor cores, digital signal processing components, large volumes of on-chip buffer memory, and multi-gigabit serial I/O capability permits DAQ system designers to vastly increase the amount of data preprocessing that can be performed in parallel within the DAQ pipeline for detector systems in large experiments. The capabilities of some currently available FPGA families are reviewed, along with the prospects for next-generation families of announced, but not yet available, platform FPGAs. Some experience with an actual implementation is presented, and reconciliation between advertised and achievable specifications is attempted. The prospects for applying these components to space-borne Si tracker detectors are briefly discussed.

Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

NASA Astrophysics Data System (ADS)

Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

2012-11-01

We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

Hardware architecture design of a fast global motion estimation method

NASA Astrophysics Data System (ADS)

Liang, Chaobing; Sang, Hongshi; Shen, Xubang

2015-12-01

VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

NASA Technical Reports Server (NTRS)

Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

2004-01-01

A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

Siemens, Philips megaproject to yield superchip in 5 years

NASA Astrophysics Data System (ADS)

1985-02-01

The development of computer chips using complementary metal oxide semiconductor (CMOS) memory technology is described. The management planning and marketing strategy of the Philips and Siemens corporations with regard to the memory chip are discussed.

ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

NASA Astrophysics Data System (ADS)

Shao, Rui; Zhong, Sheng; Yan, Luxin

2015-12-01

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium-large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

NASA Technical Reports Server (NTRS)

1972-01-01

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Redundancy approaches in bubble domain memories

NASA Technical Reports Server (NTRS)

Almasi, G. S.; Schuster, S. E.

1972-01-01

Fabrication of integrated circuit chips to compensate for faulty memory elements is discussed. Procedure for testing chips to determine extent of redundancy and faults is described. Mathematical model to define operation is presented. Schematic circuit diagram of test equipment is provided.

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Moving Beyond 3D Hetero-Integration and Towards Monolithic Integration of Phase-Change RF Switches with SiGe BiCMOS

DTIC Science & Technology

2016-03-31

Corporation, Linthicum, Maryland *Corresponding author: Pavel.Borodulin@ngc.com Abstract: A chip -scale, highly-reconfigurable transmitter and...the technology has been used in a chip -scale, reconfigurable receiver demonstration and ongoing efforts to increase the level of performance and...circuit (RF-FPGA). It consists of a heterogeneous assembly of a SiGe BiCMOS chip with multiple 3D-integrated, low-loss, phase-change switch chiplets

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

NASA Technical Reports Server (NTRS)

Beheim, Glenn M.

2003-01-01

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were installed in water-cooled jackets, as shown. This was a severe test because the pressure-sensing chips were exposed to the hot combustion gases. Prior to the installation of the SiC pressure sensors, two high-temperature silicon sensors, installed in the same locations, did not survive a single engine run. The durability of the leadless SiC pressure sensor was demonstrated when both SiC sensors operated properly throughout the two runs that were conducted.

32-Bit-Wide Memory Tolerates Failures

NASA Technical Reports Server (NTRS)

Buskirk, Glenn A.

1990-01-01

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

75 FR 11909 - In the Matter of: Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-12

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of: Certain Flash Memory Chips and Products Containing Same; Notice of Commission Determination Not To Review an Initial..., and the [[Page 11910

Development of a TiO2/SiO2 waveguide-mode chip for an ultraviolet near-field fluorescence sensor.

PubMed

Kuroda, Chiaki; Nakai, Midori; Fujimaki, Makoto; Ohki, Yoshimichi

2018-03-19

Aimed at detecting fluorescent-labeled biological substances sensitively, a sensor that utilizes near-field light has attracted much attention. According to our calculations, a planar structure composed of two dielectric layers can enhance the electric field of UV near-field light effectively by inducing waveguide-mode (WM) resonance. The fluorescence intensity obtainable by a WM chip with an optimized structure is 5.5 times that obtainable by an optimized surface plasmon resonance chip. We confirmed the above by making a WM chip consisting of TiO 2 and SiO 2 layers on a silica glass substrate and by measuring the fluorescence intensity of a solution of quantum dots dropped on the chip.

A 1-Gigabit Memory System on a multi-Chip Module for Space Applications

NASA Technical Reports Server (NTRS)

Louie, Marianne E.; Topliffe, Douglas A.; Alkalai, Leon

1996-01-01

Current spaceborne applications desire compact, low weight, and high capacity data storage systems along with the additional requirement of radiation tolerance. This paper discusses a memory system on a multi-chip module (MCM) that is designed for space applications.

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

NASA Astrophysics Data System (ADS)

Annovi, A.; Beretta, M. M.; Calderini, G.; Crescioli, F.; Frontini, L.; Liberali, V.; Shojaii, S. R.; Stabile, A.

2017-04-01

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

NASA Astrophysics Data System (ADS)

González, Diego; Botella, Guillermo; García, Carlos; Prieto, Manuel; Tirado, Francisco

2013-12-01

This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor.

Single-Chip Microcomputer Control Of The PWM Inverter

NASA Astrophysics Data System (ADS)

Morimoto, Masayuki; Sato, Shinji; Sumito, Kiyotaka; Oshitani, Katsumi

1987-10-01

A single-chip microcomputer-based con-troller for a pulsewidth modulated 1.7 KVA inverter of an airconditioner is presented. The PWM pattern generation and the system control of the airconditioner are achieved by software of the 8-bit single-chip micro-computer. The single-chip microcomputer has the disadvantages of low processing speed and small memory capacity which can be overcome by the magnetic flux control method. The PWM pattern is generated every 90 psec. The memory capacity of the PWM look-up table is less than 2 kbytes. The simple and reliable control is realized by the software-based implementation.

On-chip photonic memory elements employing phase-change materials.

PubMed

Rios, Carlos; Hosseini, Peiman; Wright, C David; Bhaskaran, Harish; Pernice, Wolfram H P

2014-03-05

Phase-change materials integrated into nanophotonic circuits provide a flexible way to realize tunable optical components. Relying on the enormous refractive-index contrast between the amorphous and crystalline states, such materials are promising candidates for on-chip photonic memories. Nonvolatile memory operation employing arrays of microring resonators is demonstrated as a route toward all-photonic chipscale information processing. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Realization of optical multimode TSV waveguides for Si-Interposer in 3D-chip-stacks

NASA Astrophysics Data System (ADS)

Killge, S.; Charania, S.; Richter, K.; Neumann, N.; Al-Husseini, Z.; Plettemeier, D.; Bartha, J. W.

2017-05-01

Optical connectivity has the potential to outperform copper-based TSVs in terms of bandwidth at the cost of more complexity due to the required electro-optical and opto-electrical conversion. The continuously increasing demand for higher bandwidth pushes the breakeven point for a profitable operation to shorter distances. To integrate an optical communication network in a 3D-chip-stack optical through-silicon vertical VIAs (TSV) are required. While the necessary effort for the electrical/optical and vice versa conversion makes it hard to envision an on-chip optical interconnect, a chip-to-chip optical link appears practicable. In general, the interposer offers the potential advantage to realize electro-optical transceivers on affordable expense by specific, but not necessarily CMOS technology. We investigated the realization and characterization of optical interconnects as a polymer based waveguide in high aspect ratio (HAR) TSVs proved on waferlevel. To guide the optical field inside a TSV as optical-waveguide or fiber, its core has to have a higher refractive index than the surrounding material. Comparing different material / technology options it turned out that thermal grown silicon dioxide (SiO2) is a perfect candidate for the cladding (nSiO2 = 1.4525 at 850 nm). In combination with SiO2 as the adjacent polymer layer, the negative resist SU-8 is very well suited as waveguide material (nSU-8 = 1.56) for the core. Here, we present the fabrication of an optical polymer based multimode waveguide in TSVs proved on waferlevel using SU-8 as core and SiO2 as cladding. The process resulted in a defect-free filling of waveguide TSVs with SU-8 core and SiO2 cladding up to aspect ratio (AR) 20:1 and losses less than 3 dB.

Vector computer memory bank contention

NASA Technical Reports Server (NTRS)

Bailey, D. H.

1985-01-01

A number of vector supercomputers feature very large memories. Unfortunately the large capacity memory chips that are used in these computers are much slower than the fast central processing unit (CPU) circuitry. As a result, memory bank reservation times (in CPU ticks) are much longer than on previous generations of computers. A consequence of these long reservation times is that memory bank contention is sharply increased, resulting in significantly lowered performance rates. The phenomenon of memory bank contention in vector computers is analyzed using both a Markov chain model and a Monte Carlo simulation program. The results of this analysis indicate that future generations of supercomputers must either employ much faster memory chips or else feature very large numbers of independent memory banks.

Vector computer memory bank contention

NASA Technical Reports Server (NTRS)

Bailey, David H.

1987-01-01

A number of vector supercomputers feature very large memories. Unfortunately the large capacity memory chips that are used in these computers are much slower than the fast central processing unit (CPU) circuitry. As a result, memory bank reservation times (in CPU ticks) are much longer than on previous generations of computers. A consequence of these long reservation times is that memory bank contention is sharply increased, resulting in significantly lowered performance rates. The phenomenon of memory bank contention in vector computers is analyzed using both a Markov chain model and a Monte Carlo simulation program. The results of this analysis indicate that future generations of supercomputers must either employ much faster memory chips or else feature very large numbers of independent memory banks.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Murray, E.; Floether, F. F.; Cavendish Laboratory, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0HE

Fundamental to integrated photonic quantum computing is an on-chip method for routing and modulating quantum light emission. We demonstrate a hybrid integration platform consisting of arbitrarily designed waveguide circuits and single-photon sources. InAs quantum dots (QD) embedded in GaAs are bonded to a SiON waveguide chip such that the QD emission is coupled to the waveguide mode. The waveguides are SiON core embedded in a SiO{sub 2} cladding. A tuneable Mach Zehnder interferometer (MZI) modulates the emission between two output ports and can act as a path-encoded qubit preparation device. The single-photon nature of the emission was verified using themore » on-chip MZI as a beamsplitter in a Hanbury Brown and Twiss measurement.« less

On-Chip Waveguide Coupling of a Layered Semiconductor Single-Photon Source.

PubMed

Tonndorf, Philipp; Del Pozo-Zamudio, Osvaldo; Gruhler, Nico; Kern, Johannes; Schmidt, Robert; Dmitriev, Alexander I; Bakhtinov, Anatoly P; Tartakovskii, Alexander I; Pernice, Wolfram; Michaelis de Vasconcellos, Steffen; Bratschitsch, Rudolf

2017-09-13

Fully integrated quantum technology based on photons is in the focus of current research, because of its immense potential concerning performance and scalability. Ideally, the single-photon sources, the processing units, and the photon detectors are all combined on a single chip. Impressive progress has been made for on-chip quantum circuits and on-chip single-photon detection. In contrast, nonclassical light is commonly coupled onto the photonic chip from the outside, because presently only few integrated single-photon sources exist. Here, we present waveguide-coupled single-photon emitters in the layered semiconductor gallium selenide as promising on-chip sources. GaSe crystals with a thickness below 100 nm are placed on Si 3 N 4 rib or slot waveguides, resulting in a modified mode structure efficient for light coupling. Using optical excitation from within the Si 3 N 4 waveguide, we find nonclassicality of generated photons routed on the photonic chip. Thus, our work provides an easy-to-implement and robust light source for integrated quantum technology.

Single-chip microcomputer application in high-altitude balloon orientation system

NASA Technical Reports Server (NTRS)

Lim, T. S.; Ehrmann, C. H.; Allison, S. R.

1980-01-01

This paper describes the application of a single-chip microcomputer in a high-altitude balloon instrumentation system. The system, consisting of a magnetometer, a stepping motor, a microcomputer and a gray code shaft encoder, is used to provide an orientation reference to point a scientific instrument at an object in space. The single-chip microcomputer, Intel's 8748, consisting of a CPU, program memory, data memory and I/O ports, is used to control the orientation of the system.

Silicon Integrated Optics: Fabrication and Characterization

NASA Astrophysics Data System (ADS)

Shearn, Michael Joseph, II

For decades, the microelectronics industry has sought integration and miniaturization as canonized in Moore's Law, and has continued doubling transistor density about every two years. However, further miniaturization of circuit elements is creating a bandwidth problem as chip interconnect wires shrink as well. A potential solution is the creation of an on-chip optical network with low delays that would be impossible to achieve using metal buses. However, this technology requires integrating optics with silicon microelectronics. The lack of efficient silicon optical sources has stymied efforts of an all-Si optical platform. Instead, the integration of efficient emitter materials, such as III-V semiconductors, with Si photonic structures is a low-cost, CMOS-compatible alternative platform. This thesis focuses on making and measuring on-chip photonic structures suitable for on-chip optical networking. The first part of the thesis assesses processing techniques of silicon and other semiconductor materials. Plasmas for etching and surface modification are described and used to make bonded, hybrid Si/III-V structures. Additionally, a novel masking method using gallium implantation into silicon for pattern definition is characterized. The second part of the thesis focuses on demonstrations of fabricated optical structures. A dense array of silicon devices is measured, consisting of fully-etched grating couplers, low-loss waveguides and ring resonators. Finally, recent progress in the Si/III-V hybrid system is discussed. Supermode control of devices is described, which uses changing Si waveguide width to control modal overlap with the gain material. Hybrid Si/III-V, Fabry-Perot evanescent lasers are demonstrated, utilizing a CMOS-compatible process suitable for integration on in electronics platforms. Future prospects and ultimate limits of Si devices and the hybrid Si/III-V system are also considered.

Overview of emerging nonvolatile memory technologies

PubMed Central

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices. PMID:25278820

Overview of emerging nonvolatile memory technologies.

PubMed

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

Si Thermoelectric Power Generator with an Unconventional Structure

NASA Astrophysics Data System (ADS)

Sakamoto, Tatsuya; Iida, Tsutomu; Ohno, Yota; Ishikawa, Masashi; Kogo, Yasuo; Hirayama, Naomi; Arai, Koya; Nakamura, Takashi; Nishio, Keishi; Takanashi, Yoshifumi

2014-06-01

We examine the mechanical stability of an unconventional Mg2Si thermoelectric generator (TEG) structure. In this structure, the angle θ between the thermoelectric (TE) chips and the heat sink is less than 90°. We examined the tolerance to an external force of various Mg2Si TEG structures using a finite-element method (FEM) with the ANSYS code. The output power of the TEGs was also measured. First, for the FEM analysis, the mechanical properties of sintered Mg2Si TE chips, such as the bending strength and Young's modulus, were measured. Then, two-dimensional (2D) TEG models with various values of θ (90°, 75°, 60°, 45°, 30°, 15°, and 0°) were constructed in ANSYS. The x and y axes were defined as being in the horizontal and vertical directions of the substrate, respectively. In the analysis, the maximum tensile stress in the chip when a constant load was applied to the TEG model in the x direction was determined. Based on the analytical results, an appropriate structure was selected and a module fabricated. For the TEG fabrication, eight TE chips, each with dimensions of 3 mm × 3 mm × 10 mm and consisting of Sb-doped n-Mg2Si prepared by a plasma-activated sintering process, were assembled such that two chips were connected in parallel, and four pairs of these were connected in series on a footprint of 46 mm × 12 mm. The measured power generation characteristics and temperature distribution with temperature differences between 873 K and 373 K are discussed.

Resistive switching behaviors of Au/pentacene/Si-nanowire arrays/heavily doped n-type Si devices for memory applications

NASA Astrophysics Data System (ADS)

Tsao, Hou-Yen; Lin, Yow-Jon

2014-02-01

The fabrication of memory devices based on the Au/pentacene/heavily doped n-type Si (n+-Si), Au/pentacene/Si nanowires (SiNWs)/n+-Si, and Au/pentacene/H2O2-treated SiNWs/n+-Si structures and their resistive switching characteristics were reported. A pentacene memory structure using SiNW arrays as charge storage nodes was demonstrated. The Au/pentacene/SiNWs/n+-Si devices show hysteresis behavior. H2O2 treatment may lead to the hysteresis degradation. However, no hysteresis-type current-voltage characteristics were observed for Au/pentacene/n+-Si devices, indicating that the resistive switching characteristic is sensitive to SiNWs and the charge trapping effect originates from SiNWs. The concept of nanowires within the organic layer opens a promising direction for organic memory devices.

New Failure Mode of Flip-Chip Solder Joints Related to the Metallization of an Organic Substrate

NASA Astrophysics Data System (ADS)

Jang, J. W.; Yoo, S. J.; Hwang, H. I.; Yuk, S. Y.; Kim, C. K.; Kim, S. J.; Han, J. S.; An, S. H.

2015-10-01

We report a new failure phenomenon during flip-chip die attach. After reflow, flip-chip bumps were separated between the Al and Ti layers on the Si die side. This was mainly observed at the Si die corner. Transmission electron microscopy images revealed corrosion of the Al layer at the edge of the solder bump metallization. The corrosion at the metallization edge exhibited a notch shape with high stress concentration factor. The organic substrate had Cu metallization with an organic solderable preservative (OSP) coating layer, where a small amount of Cl ions were detected. A solder bump separation mechanism is suggested based on the reaction between Al and Cl, related to the flow of soldering flux. During reflow, the flux will dissolve the Cl-containing OSP layer and flow up to the Al layer on the Si die side. Then, the Cl-dissolved flux will actively react with Al, forming AlCl3. During cooling, solder bumps at the Si die corner will separate through the location of Al corrosion. This demonstrated that the chemistry of the substrate metallization can affect the thermomechanical reliability of flip-chip solder joints.

Nanophotonic rare-earth quantum memory with optically controlled retrieval

NASA Astrophysics Data System (ADS)

Zhong, Tian; Kindem, Jonathan M.; Bartholomew, John G.; Rochman, Jake; Craiciu, Ioana; Miyazono, Evan; Bettinelli, Marco; Cavalli, Enrico; Verma, Varun; Nam, Sae Woo; Marsili, Francesco; Shaw, Matthew D.; Beyer, Andrew D.; Faraon, Andrei

2017-09-01

Optical quantum memories are essential elements in quantum networks for long-distance distribution of quantum entanglement. Scalable development of quantum network nodes requires on-chip qubit storage functionality with control of the readout time. We demonstrate a high-fidelity nanophotonic quantum memory based on a mesoscopic neodymium ensemble coupled to a photonic crystal cavity. The nanocavity enables >95% spin polarization for efficient initialization of the atomic frequency comb memory and time bin-selective readout through an enhanced optical Stark shift of the comb frequencies. Our solid-state memory is integrable with other chip-scale photon source and detector devices for multiplexed quantum and classical information processing at the network nodes.

Initial Performance Results on IBM POWER6

NASA Technical Reports Server (NTRS)

Saini, Subbash; Talcott, Dale; Jespersen, Dennis; Djomehri, Jahed; Jin, Haoqiang; Mehrotra, Piysuh

2008-01-01

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Design and Implementation of an MC68020-Based Educational Computer Board

DTIC Science & Technology

1989-12-01

device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to initialize...MHz. It includes four * Static Random Access Memory (SRAM) chips which provide a storage of 32K bytes. Two Programmable Array Logic (PAL) chips...device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the this part of the Continuation Phase 2 period (Oct. 1, 06 to March 31, 07) of this project were to (a) fabricate laser-doped SiC wafers and start testing the SiC chips for individual gas species sensing under high temperature and pressure conditions and (b) demonstrate the designs and workings of a temperature probe suited for industrial power generation turbine environment. A focus of the reported work done via Kar UCF LAMP lab. is to fabricate the embedded optical phase or doped microstructures based SiC chips, namely, Chromium (C), Boron (B) and Aluminum (Al) doped 4H-SiC, andmore » to eventually deploy such laser-doped chips to enable gas species sensing under high temperature and pressure. Experimental data is provided from SiC chip optical response for various gas species such as pure N2 and mixtures of N2 and H{sub 2}, N{sub 2} and CO, N{sub 2} and CO{sub 2}, and N{sub 2} and CH{sub 4}. Another main focus of the reported work was a temperature sensor probe assembly design and initial testing. The probe transmit-receive fiber optics were designed and tested for electrically controlled alignment. This probe design was provided to overcome mechanical vibrations in typical industrial scenarios. All these goals have been achieved and are described in detail in the report.« less

Characterization of 720 and 940 MHz Oscillators with Chip Antenna for Wireless Sensors from Room Temperature to 200 and 250 deg C

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Ponchak, George E.

2011-01-01

Oscillators that operate at 720 and 940 MHz and characterized over a temperature range of 25 C to 200 C and 250 C, respectively, are presented. The oscillators are designed on alumina substrates with typical integrated circuit fabrication techniques. Cree SiC MESFETs, thin film metal-insulator-metal capacitors and spiral inductors, and Johanson miniature chip antennas make-up the circuits. The output power and phase noise are presented as a function of temperature and frequency. Index Terms MESFETS, chip antennas, oscillators SiC alumina.

Face classification using electronic synapses

NASA Astrophysics Data System (ADS)

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H.-S. Philip; Qian, He

2017-05-01

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Superhydrophobic Surface With Shape Memory Micro/Nanostructure and Its Application in Rewritable Chip for Droplet Storage.

PubMed

Lv, Tong; Cheng, Zhongjun; Zhang, Dongjie; Zhang, Enshuang; Zhao, Qianlong; Liu, Yuyan; Jiang, Lei

2016-09-21

Recently, superhydrophobic surfaces with tunable wettability have aroused much attention. Noticeably, almost all present smart performances rely on the variation of surface chemistry on static micro/nanostructure, to obtain a surface with dynamically tunable micro/nanostructure, especially that can memorize and keep different micro/nanostructures and related wettabilities, is still a challenge. Herein, by creating micro/nanostructured arrays on shape memory polymer, a superhydrophobic surface that has shape memory ability in changing and recovering its hierarchical structures and related wettabilities was reported. Meanwhile, the surface was successfully used in the rewritable functional chip for droplet storage by designing microstructure-dependent patterns, which breaks through current research that structure patterns cannot be reprogrammed. This article advances a superhydrophobic surface with shape memory hierarchical structure and the application in rewritable functional chip, which could start some fresh ideas for the development of smart superhydrophobic surface.

Face classification using electronic synapses.

PubMed

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H-S Philip; Qian, He

2017-05-12

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Biostability of an implantable glucose sensor chip

NASA Astrophysics Data System (ADS)

Fröhlich, M.; Birkholz, M.; Ehwald, K. E.; Kulse, P.; Fursenko, O.; Katzer, J.

2012-12-01

Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and Ra roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the Year 2006 Continuation Phase 2 three months period (April 1 to Sept. 30) of this project were to (a) conduct a probe elements industrial environment feasibility study and (b) fabricate embedded optical phase or microstructured SiC chips for individual gas species sensing. Specifically, SiC chips for temperature and pressure probe industrial applications were batch fabricated. Next, these chips were subject to a quality test for use in the probe sensor. A batch of the best chips for probe design were selected and subject to further tests that included sensor performance based on corrosive chemical exposure, powermore » plant soot exposure, light polarization variations, and extreme temperature soaking. Experimental data were investigated in detail to analyze these mentioned industrial parameters relevant to a power plant. Probe design was provided to overcome mechanical vibrations. All these goals have been achieved and are described in detail in the report. The other main focus of the reported work is to modify the SiC chip by fabricating an embedded optical phase or microstructures within the chip to enable gas species sensing under high temperature and pressure. This has been done in the Kar UCF Lab. using a laser-based system whose design and operation is explained. Experimental data from the embedded optical phase-based chip for changing temperatures is provided and shown to be isolated from gas pressure and species. These design and experimentation results are summarized to give positive conclusions on the proposed high temperature high pressure gas species detection optical sensor technology.« less

A 1-1/2-level on-chip-decoding bubble memory chip design

NASA Technical Reports Server (NTRS)

Chen, T. T.

1975-01-01

Design includes multi-channel replicator which can reduce chip-writing requirement, selective annihilating switch which can effectively annihilate bubbles with minimum delay, and modified transfer switch which can be used as selective steering-type decoder.

Coupling of erbium dopants to yttrium orthosilicate photonic crystal cavities for on-chip optical quantum memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miyazono, Evan; Zhong, Tian; Craiciu, Ioana

Erbium dopants in crystals exhibit highly coherent optical transitions well suited for solid-state optical quantum memories operating in the telecom band. Here, we demonstrate coupling of erbium dopant ions in yttrium orthosilicate to a photonic crystal cavity fabricated directly in the host crystal using focused ion beam milling. The coupling leads to reduction of the photoluminescence lifetime and enhancement of the optical depth in microns-long devices, which will enable on-chip quantum memories.

Stress analysis of ultra-thin silicon chip-on-foil electronic assembly under bending

NASA Astrophysics Data System (ADS)

Wacker, Nicoleta; Richter, Harald; Hoang, Tu; Gazdzicki, Pawel; Schulze, Mathias; Angelopoulos, Evangelos A.; Hassan, Mahadi-Ul; Burghartz, Joachim N.

2014-09-01

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness \\leqslant 20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the built-in devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chip's edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

NASA Astrophysics Data System (ADS)

Yang, Chen; Liu, LeiBo; Yin, ShouYi; Wei, ShaoJun

2014-12-01

The computational capability of a coarse-grained reconfigurable array (CGRA) can be significantly restrained due to data and context memory bandwidth bottlenecks. Traditionally, two methods have been used to resolve this problem. One method loads the context into the CGRA at run time. This method occupies very small on-chip memory but induces very large latency, which leads to low computational efficiency. The other method adopts a multi-context structure. This method loads the context into the on-chip context memory at the boot phase. Broadcasting the pointer of a set of contexts changes the hardware configuration on a cycle-by-cycle basis. The size of the context memory induces a large area overhead in multi-context structures, which results in major restrictions on application complexity. This paper proposes a Predictable Context Cache (PCC) architecture to address the above context issues by buffering the context inside a CGRA. In this architecture, context is dynamically transferred into the CGRA. Utilizing a PCC significantly reduces the on-chip context memory and the complexity of the applications running on the CGRA is no longer restricted by the size of the on-chip context memory. Data preloading is the most frequently used approach to hide input data latency and speed up the data transmission process for the data bandwidth issue. Rather than fundamentally reducing the amount of input data, the transferred data and computations are processed in parallel. However, the data preloading method cannot work efficiently because data transmission becomes the critical path as the reconfigurable array scale increases. This paper also presents a Hierarchical Data Memory (HDM) architecture as a solution to the efficiency problem. In this architecture, high internal bandwidth is provided to buffer both reused input data and intermediate data. The HDM architecture relieves the external memory from the data transfer burden so that the performance is significantly improved. As a result of using PCC and HDM, experiments running mainstream video decoding programs achieved performance improvements of 13.57%-19.48% when there was a reasonable memory size. Therefore, 1080p@35.7fps for H.264 high profile video decoding can be achieved on PCC and HDM architecture when utilizing a 200 MHz working frequency. Further, the size of the on-chip context memory no longer restricted complex applications, which were efficiently executed on the PCC and HDM architecture.

A dual-docking microfluidic cell migration assay (D2-Chip) for testing neutrophil chemotaxis and the memory effect.

PubMed

Yang, Ke; Wu, Jiandong; Xu, Guoqing; Xie, Dongxue; Peretz-Soroka, Hagit; Santos, Susy; Alexander, Murray; Zhu, Ling; Zhang, Michael; Liu, Yong; Lin, Francis

2017-04-18

Chemotaxis is a classic mechanism for guiding cell migration and an important topic in both fundamental cell biology and health sciences. Neutrophils are a widely used model to study eukaryotic cell migration and neutrophil chemotaxis itself can lead to protective or harmful immune actions to the body. While much has been learnt from past research about how neutrophils effectively navigate through a chemoattractant gradient, many interesting questions remain unclear. For example, while it is tempting to model neutrophil chemotaxis using the well-established biased random walk theory, the experimental proof was challenged by the cell's highly persistent migrating nature. A special experimental design is required to test the key predictions from the random walk model. Another question that has interested the cell migration community for decades concerns the existence of chemotactic memory and its underlying mechanism. Although chemotactic memory has been suggested in various studies, a clear quantitative experimental demonstration will improve our understanding of the migratory memory effect. Motivated by these questions, we developed a microfluidic cell migration assay (so-called dual-docking chip or D 2 -Chip) that can test both the biased random walk model and the memory effect for neutrophil chemotaxis on a single chip enabled by multi-region gradient generation and dual-region cell alignment. Our results provide experimental support for the biased random walk model and chemotactic memory for neutrophil chemotaxis. Quantitative data analyses provide new insights into neutrophil chemotaxis and memory by making connections to entropic disorder, cell morphology and oscillating migratory response.

Fabrication of silicon nanowires based on-chip micro-supercapacitor

NASA Astrophysics Data System (ADS)

Soam, Ankur; Arya, Nitin; Singh, Aniruddh; Dusane, Rajiv

2017-06-01

An on-chip micro-supercapacitor (μ-SC) based on Silicon nanowires (SiNWs) has been developed by Hot-wire chemical vapor process. First, finger patterned electrodes of Al were made on a silicon nitride coated Si wafer and SiNWs were then grown selectively on the Al electrodes. μ-SC performance has been tested in an ionic electrolyte and a capacitance of 13 μF/cm2 has been obtained by the μ-SC. The resulted μ-SC can be exploited to store the harvesting energy in micro-electro-mechanical-systems and coupled with battery for peak power leveling. Low temperature growth of SiNWs at 350 °C makes it suitable for prospective flexible electronics applications.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Monolithic integration of a silica AWG and Ge photodiodes on Si photonic platform for one-chip WDM receiver.

PubMed

Nishi, Hidetaka; Tsuchizawa, Tai; Kou, Rai; Shinojima, Hiroyuki; Yamada, Takashi; Kimura, Hideaki; Ishikawa, Yasuhiko; Wada, Kazumi; Yamada, Koji

2012-04-09

On the silicon (Si) photonic platform, we monolithically integrated a silica-based arrayed-waveguide grating (AWG) and germanium (Ge) photodiodes (PDs) using low-temperature fabrication technology. We confirmed demultiplexing by the AWG, optical-electrical signal conversion by Ge PDs, and high-speed signal detection at all channels. In addition, we mounted a multichannel transimpedance amplifier/limiting amplifier (TIA/LA) circuit on the fabricated AWG-PD device using flip-chip bonding technology. The results show the promising potential of our Si photonic platform as a photonics-electronics convergence.

Simulation and Measurement of Absorbed Dose from 137 Cs Gammas Using a Si Timepix Detector

NASA Technical Reports Server (NTRS)

Stoffle, Nicholas; Pinsky, Lawrence; Empl, Anton; Semones, Edward

2011-01-01

The TimePix readout chip is a hybrid pixel detector with over 65k independent pixel elements. Each pixel contains its own circuitry for charge collection, counting logic, and readout. When coupled with a Silicon detector layer, the Timepix chip is capable of measuring the charge, and thus energy, deposited in the Silicon. Measurements using a NIST traceable 137Cs gamma source have been made at Johnson Space Center using such a Si Timepix detector, and this data is compared to simulations of energy deposition in the Si layer carried out using FLUKA.

Odor-enriched environment rescues long-term social memory, but does not improve olfaction in social isolated adult mice.

PubMed

Gusmão, Isabela D; Monteiro, Brisa M M; Cornélio, Guilherme O S; Fonseca, Cristina S; Moraes, Márcio F D; Pereira, Grace S

2012-03-17

Prolonged permanence of animals under social isolation (SI) arouses a variety of psychological symptoms like aggression, stress, anxiety and depression. However, short-term SI is commonly used to evaluate social memory. Interestingly, the social memory cannot be accessed with delays higher than 30min in SI mice. Our hypothesis is that SI with intermediate duration, like one week (1w), impairs the long-term storage of new social information (S-LTM), without affecting anxiety or other types of memories, because the SI compromises the olfactory function of the animal. Our results demonstrated that SI impaired S-LTM, without affecting other kinds of memory or anxiety. In addition, the SI increased the latency in the buried-food finding task, but did not affect the habituation or the discrimination of odors. Next, we postulated that if continuous input to the olfactory system is fundamental for the maintenance of the olfactory function and social memory persistence, isolated mice under odor-enriched environment (OEE) should behave like group-housed (GH) animals. In fact, the OEE prevented the S-LTM deficit imposed by the SI. However, OEE did not restore the SI mice olfaction to the GH mice level. Our results suggest that SI modulates olfaction and social memory persistence, probably, by independent mechanisms. We also showed for the first time that OEE rescued S-LTM in SI mice through a mechanism not necessarily involved with olfaction. Copyright © 2011 Elsevier B.V. All rights reserved.

Thermal management of LEDs: package to system

NASA Astrophysics Data System (ADS)

Arik, Mehmet; Becker, Charles A.; Weaver, Stanton E.; Petroski, James

2004-01-01

Light emitting diodes, LEDs, historically have been used for indicators and produced low amounts of heat. The introduction of high brightness LEDs with white light and monochromatic colors have led to a movement towards general illumination. The increased electrical currents used to drive the LEDs have focused more attention on the thermal paths in the developments of LED power packaging. The luminous efficiency of LEDs is soon expected to reach over 80 lumens/W, this is approximately 6 times the efficiency of a conventional incandescent tungsten bulb. Thermal management for the solid-state lighting applications is a key design parameter for both package and system level. Package and system level thermal management is discussed in separate sections. Effect of chip packages on junction to board thermal resistance was compared for both SiC and Sapphire chips. The higher thermal conductivity of the SiC chip provided about 2 times better thermal performance than the latter, while the under-filled Sapphire chip package can only catch the SiC chip performance. Later, system level thermal management was studied based on established numerical models for a conceptual solid-state lighting system. A conceptual LED illumination system was chosen and CFD models were created to determine the availability and limitations of passive air-cooling.

Thin hybrid pixel assembly with backside compensation layer on ROIC

NASA Astrophysics Data System (ADS)

Bates, R.; Buttar, C.; McMullen, T.; Cunningham, L.; Ashby, J.; Doherty, F.; Gray, C.; Pares, G.; Vignoud, L.; Kholti, B.; Vahanen, S.

2017-01-01

The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m2. For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of -175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.

Enriched environment increases neurogenesis and improves social memory persistence in socially isolated adult mice.

PubMed

Monteiro, Brisa M M; Moreira, Fabrício A; Massensini, André R; Moraes, Márcio F D; Pereira, Grace S

2014-02-01

Social memory consists of the information necessary to identify and recognize cospecifics and is essential to many forms of social interaction. Social memory persistence is strongly modulated by the animal's experiences. We have shown in previous studies that social isolation (SI) in adulthood impairs social memory persistence and that an enriched environment (EE) prevents this impairment. However, the mechanisms involved in the effects of SI and EE on social memory persistence remain unknown. We hypothesized that the mechanism by which SI and EE affect social memory persistence is through their modulation of neurogenesis. To investigate this hypothesis, adult mice were submitted to 7 days of one of the following conditions: group-housing in a standard (GH) or enriched environment (GH+EE); social isolation in standard (SI) or enriched environment (SI+EE). We observed an increase in the number of newborn neurons in the dentate gyrus of the hippocampus (DG) and glomerular layer of the olfactory bulb (OB) in both GH+EE and SI+EE mice. However, this increase of newborn neurons in the granule cell layer of the OB was restricted to the GH+EE group. Furthermore, both SI and SI+EE groups showed less neurogenesis in the mitral layer of the OB. Interestingly, the performance of the SI mice in the buried food-finding task was inferior to that of the GH mice. To further analyze whether increased neurogenesis is in fact the mechanism by which the EE improves social memory persistence in SI mice, we administered the mitotic inhibitor AraC or saline directly into the lateral ventricles of the SI+EE mice. We found that the AraC treatment decreased cell proliferation in both the DG and OB, and impaired social memory persistence in the SI+EE mice. Taken together, our results strongly suggest that neurogenesis is what supports social memory persistence in socially isolated mice. © 2013 Wiley Periodicals, Inc.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology.« less

Error correcting code with chip kill capability and power saving enhancement

DOEpatents

Gara, Alan G [Mount Kisco, NY; Chen, Dong [Croton On Husdon, NY; Coteus, Paul W [Yorktown Heights, NY; Flynn, William T [Rochester, MN; Marcella, James A [Rochester, MN; Takken, Todd [Brewster, NY; Trager, Barry M [Yorktown Heights, NY; Winograd, Shmuel [Scarsdale, NY

2011-08-30

A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

Towards Terabit Memories

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet little data on their energy/b. As a read-out memory with unparalleled retention and lifetime, the ROM with electron-beam direct-write-lithography (Chap. 8) should be considered for its projected 2D density of 250 Gb/cm², a very small read energy of 0.1 μW/Gb/s. The lithography write-speed 10 ms/Terabit makes this ROM a serious contentender for the optimum in non-volatile, tamper-proof storage.

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Designing a VMEbus FDDI adapter card

NASA Astrophysics Data System (ADS)

Venkataraman, Raman

1992-03-01

This paper presents a system architecture for a VMEbus FDDI adapter card containing a node core, FDDI block, frame buffer memory and system interface unit. Most of the functions of the PHY and MAC layers of FDDI are implemented with National's FDDI chip set and the SMT implementation is simplified with a low cost microcontroller. The factors that influence the system bus bandwidth utilization and FDDI bandwidth utilization are the data path and frame buffer memory architecture. The VRAM based frame buffer memory has two sections - - LLC frame memory and SMT frame memory. Each section with an independent serial access memory (SAM) port provides an independent access after the initial data transfer cycle on the main port and hence, the throughput is maximized on each port of the memory. The SAM port simplifies the system bus master DMA design and the VMEbus interface can be designed with low-cost off-the-shelf interface chips.

Packaging Technologies for 500C SiC Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2013-01-01

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

Extreme temperature robust optical sensor designs and fault-tolerant signal processing

DOEpatents

Riza, Nabeel Agha [Oviedo, FL; Perez, Frank [Tujunga, CA

2012-01-17

Silicon Carbide (SiC) probe designs for extreme temperature and pressure sensing uses a single crystal SiC optical chip encased in a sintered SiC material probe. The SiC chip may be protected for high temperature only use or exposed for both temperature and pressure sensing. Hybrid signal processing techniques allow fault-tolerant extreme temperature sensing. Wavelength peak-to-peak (or null-to-null) collective spectrum spread measurement to detect wavelength peak/null shift measurement forms a coarse-fine temperature measurement using broadband spectrum monitoring. The SiC probe frontend acts as a stable emissivity Black-body radiator and monitoring the shift in radiation spectrum enables a pyrometer. This application combines all-SiC pyrometry with thick SiC etalon laser interferometry within a free-spectral range to form a coarse-fine temperature measurement sensor. RF notch filtering techniques improve the sensitivity of the temperature measurement where fine spectral shift or spectrum measurements are needed to deduce temperature.

Switching kinetics of SiC resistive memory for harsh environments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Morgan, K. A., E-mail: kam2g11@soton.ac.uk; Huang, R.; Groot, C. H. de

2015-07-15

Cu/a-SiC/Au resistive memory cells are measured using voltage pulses and exhibit the highest R{sub OFF}/R{sub ON} ratio recorded for any resistive memory. The switching kinetics are investigated and fitted to a numerical model, using thermal conductivity and resistivity properties of the dielectric. The SET mechanism of the Cu/a-SiC/Au memory cells is found to be due to ionic motion without joule heating contributions, whereas the RESET mechanism is found to be due to thermally assisted ionic motion. The conductive filament diameter is extracted to be around 4nm. The high thermal conductivity and resistivity for the Cu/a-SiC/Au memory cells result in slowmore » switching but with high thermal reliability and stability, showing potential for use in harsh environments. Radiation properties of SiC memory cells are investigated. No change was seen in DC sweep or pulsed switching nor in conductive mechanisms, up to 2Mrad(Si) using {sup 60}Co gamma irradiation.« less

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

Neuron array with plastic synapses and programmable dendrites.

PubMed

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Chips of Hope: Neuro-Electronic Hybrids for Brain Repair

NASA Astrophysics Data System (ADS)

Ben-Jacob, Eshel

2010-03-01

The field of Neuro-Electronic Hybrids kicked off 30 years ago when researchers in the US first tweaked the technology of recording and stimulation of networks of live neurons grown in a Petri dish and interfaced with a computer via an array of electrodes. Since then, many researchers have searched for ways to imprint in neural networks new ``memories" without erasing old ones. I will describe our new generation of Neuro-Electronic Hybrids and how we succeeded to turn them into the first learning Neurochips - memory and information processing chips made of live neurons. To imprint multiple memories in our new chip we used chemical stimulation at specific locations that were selected by analyzing the networks activity in real time according to our new information encoding principle. Currently we develop new-generation of neuro chips using special carbon nano tubes (CNT). These electrodes enable to engineer the networks topology and efficient electrical interfacing with the neurons. This advance bears the promise to pave the way for building a new experimental platform for testing new drugs and developing new methods for neural networks repair and regeneration. Looking into the future, the development brings us a step closer towards the dream of Brain Repair by implementable Neuro-Electronic hybrid chips.

Ge-Photodetectors for Si-Based Optoelectronic Integration

PubMed Central

Wang, Jian; Lee, Sungjoo

2011-01-01

High speed photodetectors are a key building block, which allow a large wavelength range of detection from 850 nm to telecommunication standards at optical fiber band passes of 1.3–1.55 μm. Such devices are key components in several applications such as local area networks, board to board, chip to chip and intrachip interconnects. Recent technological achievements in growth of high quality SiGe/Ge films on Si wafers have opened up the possibility of low cost Ge-based photodetectors for near infrared communication bands and high resolution spectral imaging with high quantum efficiencies. In this review article, the recent progress in the development and integration of Ge-photodetectors on Si-based photonics will be comprehensively reviewed, along with remaining technological issues to be overcome and future research trends. PMID:22346598

Phase Equilibria of the Sn-Ni-Si Ternary System and Interfacial Reactions in Sn-(Cu)/Ni-Si Couples

NASA Astrophysics Data System (ADS)

Fang, Gu; Chen, Chih-chi

2015-07-01

Interfacial reactions in Sn/Ni-4.5 wt.%Si and Sn-Cu/Ni-4.5 wt.%Si couples at 250°C, and Sn-Ni-Si ternary phase equilibria at 250°C were investigated in this study. Ni-Si alloys, which are nonmagnetic, can be regarded as a diffusion barrier layer material in flip chip packaging. Solder/Ni-4.5 wt.%Si interfacial reactions are crucial to the reliability of soldered joints. Phase equilibria information is essential for development of solder/Ni-Si materials. No ternary compound is present in the Sn-Ni-Si ternary system at 250°C. Extended solubility of Si in the phases Ni3Sn2 and Ni3Sn is 3.8 and 6.1 at.%, respectively. As more Si dissolves in these phases their lattice constants decrease. No noticeable ternary solubility is observed for the other intermetallics. Interfacial reactions in solder/Ni-4.5 wt.%Si are similar to those for solder/Ni. Si does not alter the reaction phases. No Si solubility in the reaction phases was detected, although rates of growth of the reaction phases were reduced. Because the alloy Ni-4.5 wt.%Si reacts more slowly with solders than pure Ni, the Ni-4.5 wt.%Si alloy could be a potential new diffusion barrier layer material for flip chip packaging.

Quantifying data retention of perpendicular spin-transfer-torque magnetic random access memory chips using an effective thermal stability factor method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Thomas, Luc, E-mail: luc.thomas@headway.com; Jan, Guenole; Le, Son

The thermal stability of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) devices is investigated at chip level. Experimental data are analyzed in the framework of the Néel-Brown model including distributions of the thermal stability factor Δ. We show that in the low error rate regime important for applications, the effect of distributions of Δ can be described by a single quantity, the effective thermal stability factor Δ{sub eff}, which encompasses both the median and the standard deviation of the distributions. Data retention of memory chips can be assessed accurately by measuring Δ{sub eff} as a function of device diameter andmore » temperature. We apply this method to show that 54 nm devices based on our perpendicular STT-MRAM design meet our 10 year data retention target up to 120 °C.« less

The role of EEPROM devices in upcoming ISDN applications

NASA Astrophysics Data System (ADS)

Nette, Herbert L.

1991-02-01

Integrated Services Digital Network (ISDN) equipments are rapidly becoming a major market for semiconductor chips. Although at first glance this growing market appears to be geared at logic chips, nonvolatile memories represent important support chips and will become a significant segment of this market. Challenges in these applications consist in operating EEPROMs at lower voltages and lower power and embedding them on ever more complex communications processor chips.

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier's law of heat conduction at steady-state

NASA Astrophysics Data System (ADS)

Wu, Chia-Yu; Huang, Yin-Hsien; Wu, Hsin-Han; Hsieh, Tsung-Eong

2018-06-01

Fourier's law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (κ's) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (RTBR's) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2×2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and RTBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and RTBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-κ value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays.

Update on Development of SiC Multi-Chip Power Modules

NASA Technical Reports Server (NTRS)

Lostetter, Alexander; Cilio, Edgar; Mitchell, Gavin; Schupbach, Roberto

2008-01-01

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Progress on TSV technology for Medipix3RX chip

NASA Astrophysics Data System (ADS)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Fritzsch, T.; Zoschke, K.; Graafsma, H.

2017-12-01

The progress of Through Silicon Via (TSV) technology for Medipix3RX chip done at DESY is presented here. The goal of this development is to replace the wire bonds in X-ray detectors with TSVs, in order to reduce the dead area between detectors. We obtained the first working chips assembled together with Si based sensors for X-ray detection. The 3D integration technology, including TSV, Re-distribution layer deposition, bump bonding to the Si sensor and bump bonding to the carrier PCB, was done by Fraunhofer Institute IZM in Berlin. After assembly, the module was successfully tested by recording background radiation and making X-ray images of small objects. The active area of the Medipix3RX chip is 14.1 mm×14.1 mm or 256×256 pixels. During TSV processing, the Medipix3RX chip was thinned from 775 μm original thickness, to 130 μm. The diameter of the vias is 40 μm, and the pitch between the vias is 120 μm. A liner filling approach was used to contact the TSV with the RDL on the backside of the Medipix3RX readout chip.

K-Band Si/SiGe HBT MMIC Amplifiers Using Lumped Passive Components with a Micromachined Structure

NASA Technical Reports Server (NTRS)

Lu, Liang-Hung; Rieh, Jae-Sung; Bhattacharya, Pallab; Katechi, Linda P. B.; Croke, E. T.; Ponchak, George E.; Alterovitz, Samuel A.

2000-01-01

Using Si/SiGe heterojunction bipolar transistors with a maximum oscillation frequency of 52 GHz and a novel structure for passive components, a two-stage K-band lumped-element amplifier has been designed and fabricated on high-resistivity Si substrates. The chip size including biasing and RF chokes is 0.92 x 0.67 sq mm.

Nanophotonic rare-earth quantum memory with optically controlled retrieval.

PubMed

Zhong, Tian; Kindem, Jonathan M; Bartholomew, John G; Rochman, Jake; Craiciu, Ioana; Miyazono, Evan; Bettinelli, Marco; Cavalli, Enrico; Verma, Varun; Nam, Sae Woo; Marsili, Francesco; Shaw, Matthew D; Beyer, Andrew D; Faraon, Andrei

2017-09-29

Optical quantum memories are essential elements in quantum networks for long-distance distribution of quantum entanglement. Scalable development of quantum network nodes requires on-chip qubit storage functionality with control of the readout time. We demonstrate a high-fidelity nanophotonic quantum memory based on a mesoscopic neodymium ensemble coupled to a photonic crystal cavity. The nanocavity enables >95% spin polarization for efficient initialization of the atomic frequency comb memory and time bin-selective readout through an enhanced optical Stark shift of the comb frequencies. Our solid-state memory is integrable with other chip-scale photon source and detector devices for multiplexed quantum and classical information processing at the network nodes. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Si-based optical I/O for optical memory interface

NASA Astrophysics Data System (ADS)

Ha, Kyoungho; Shin, Dongjae; Byun, Hyunil; Cho, Kwansik; Na, Kyoungwon; Ji, Hochul; Pyo, Junghyung; Hong, Seokyong; Lee, Kwanghyun; Lee, Beomseok; Shin, Yong-hwack; Kim, Junghye; Kim, Seong-gu; Joe, Insung; Suh, Sungdong; Choi, Sanghoon; Han, Sangdeok; Park, Yoondong; Choi, Hanmei; Kuh, Bongjin; Kim, Kichul; Choi, Jinwoo; Park, Sujin; Kim, Hyeunsu; Kim, Kiho; Choi, Jinyong; Lee, Hyunjoo; Yang, Sujin; Park, Sungho; Lee, Minwoo; Cho, Minchang; Kim, Saebyeol; Jeong, Taejin; Hyun, Seokhun; Cho, Cheongryong; Kim, Jeong-kyoum; Yoon, Hong-gu; Nam, Jeongsik; Kwon, Hyukjoon; Lee, Hocheol; Choi, Junghwan; Jang, Sungjin; Choi, Joosun; Chung, Chilhee

2012-01-01

Optical interconnects may provide solutions to the capacity-bandwidth trade-off of recent memory interface systems. For cost-effective optical memory interfaces, Samsung Electronics has been developing silicon photonics platforms on memory-compatible bulk-Si 300-mm wafers. The waveguide of 0.6 dB/mm propagation loss, vertical grating coupler of 2.7 dB coupling loss, modulator of 10 Gbps speed, and Ge/Si photodiode of 12.5 Gbps bandwidth have been achieved on the bulk-Si platform. 2x6.4 Gbps electrical driver circuits have been also fabricated using a CMOS process.

Josephson-CMOS Hybrid Memories

DTIC Science & Technology

2007-04-25

threshold voltage. The subthreshold behavior is critical for dynamic circuits since it determines the static power and retention time of a dynamic memory...results of subthreshold behaviors for different temperatures are shown in Fig. 2.9, the simulated results con- firm the analysis above. Also, experimental...0.5-26.5 GHz 25 dB gain), but they are not on-chip because they comsume so much power (9 W) that you cannot afford to build them on chip. [52] Another

Multichannel detection of ionic currents through two nanopores fabricated on integrated Si3N4 membranes.

PubMed

Yanagi, Itaru; Akahori, Rena; Aoki, Mayu; Harada, Kunio; Takeda, Ken-Ichi

2016-08-16

Integration of solid-state nanopores and multichannel detection of signals from each nanopore are effective measures for realizing high-throughput nanopore sensors. In the present study, we demonstrated fabrication of Si3N4 membrane arrays and the simultaneous measurement of ionic currents through two nanopores formed in two adjacent membranes. Membranes with thicknesses as low as 6.4 nm and small nanopores with diameters of less than 2 nm could be fabricated using the poly-Si sacrificial-layer process and multilevel pulse-voltage injection. Using the fabricated nanopore membranes, we successfully achieved simultaneous detection of clear ionic-current blockades when single-stranded short homopolymers (poly(dA)60) passed through two nanopores. In addition, we investigated the signal crosstalk and leakage current among separated chambers. When two nanopores were isolated on the front surface of the membrane, there was no signal crosstalk or leakage current between the chambers. However, when two nanopores were isolated on the backside of the Si substrate, signal crosstalk and leakage current were observed owing to high-capacitance coupling between the chambers and electrolysis of water on the surface of the Si substrate. The signal crosstalk and leakage current could be suppressed by oxidizing the exposed Si surface in the membrane chip. Finally, the observed ionic-current blockade when poly(dA)60 passed through the nanopore in the oxidized chip was approximately half of that observed in the non-oxidized chip.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Hardware/software codesign for embedded RISC core

NASA Astrophysics Data System (ADS)

Liu, Peng

2001-12-01

This paper describes hardware/software codesign method of the extendible embedded RISC core VIRGO, which based on MIPS-I instruction set architecture. VIRGO is described by Verilog hardware description language that has five-stage pipeline with shared 32-bit cache/memory interface, and it is controlled by distributed control scheme. Every pipeline stage has one small controller, which controls the pipeline stage status and cooperation among the pipeline phase. Since description use high level language and structure is distributed, VIRGO core has highly extension that can meet the requirements of application. We take look at the high-definition television MPEG2 MPHL decoder chip, constructed the hardware/software codesign virtual prototyping machine that can research on VIRGO core instruction set architecture, and system on chip memory size requirements, and system on chip software, etc. We also can evaluate the system on chip design and RISC instruction set based on the virtual prototyping machine platform.

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths

PubMed Central

Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

2015-01-01

The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p+-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I–V ) curves combined with the temperature dependence of the I–V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole–Frenkel (P–F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM. PMID:26508086

a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths.

PubMed

Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

2015-10-28

The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p(+)-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I-V) curves combined with the temperature dependence of the I-V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole-Frenkel (P-F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM.

Light coupling and distribution for Si3N4/SiO2 integrated multichannel single-mode sensing system

NASA Astrophysics Data System (ADS)

Kaźmierczak, Andrzej; Dortu, Fabian; Schrevens, Olivier; Giannone, Domenico; Bouville, David; Cassan, Eric; Gylfason, Kristinn B.; Sohlström, Hans; Sanchez, Benito; Griol, Amadeu; Hill, Daniel

2009-01-01

We present an efficient and highly alignment-tolerant light coupling and distribution system for a multichannel Si3N4/SiO2 single-mode photonics sensing chip. The design of the input and output couplers and the distribution splitters is discussed. Examples of multichannel data obtained with the system are given.

High density Schottky barrier IRCCD sensors for SWIR applications at intermediate temperature

NASA Technical Reports Server (NTRS)

Elabd, H.; Villani, T. S.; Tower, J. R.

1982-01-01

Monolithic 32 x 64 and 64 x 1:128 palladium silicide (Pd2Si) interline transfer infrared charge coupled devices (IRCCDs) sensitive in the 1 to 3.5 micron spectral band were developed. This silicon imager exhibits a low response nonuniformity of typically 0.2 to 1.6% rms, and was operated in the temperature range between 40 to 140 K. Spectral response measurements of test Pd2Si p-type Si devices yield quantum efficiencies of 7.9% at 1.25 microns, 5.6% at 1.65 microns 2.2% at 2.22 microns. Improvement in quantum efficiency is expected by optimizing the different structural parameters of the Pd2Si detectors. The spectral response of the Pd2Si detectors fit a modified Fowler emission model. The measured photo-electric barrier height for the Pd2Si detectors is 0.34 eV and the measured quantum efficiency coefficient, C1, is 19%/eV. The dark current level of Pd2Si Schottky barrier focal plane arrays (FPAs) is sufficiently low to enable operation at intermediate temperatures at TV frame rates. Typical dark current level measured at 120 K on the FPA is 2 nA/sq cm. The operating temperature of the Pd2Si FPA is compatible with passive cooler performance. In addition, high density Pd2Si Schottky barrier FPAs are manufactured with high yield and therefore represent an economical approach to short wavelength IR imaging. A Pd2Si Schottky barrier image sensor for push-broom multispectral imaging in the 1.25, 1.65, and 2.22 micron bands is being studied. The sensor will have two line arrays (dual band capability) of 512 detectors each, with 30 micron center-to-center detector spacing. The device will be suitable for chip-to-chip abutment, thus providing the capability to produce large, multiple chip focal planes with contiguous, in-line sensors.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

Chip PCR. I. Surface passivation of microfabricated silicon-glass chips for PCR.

PubMed Central

Shoffner, M A; Cheng, J; Hvichia, G E; Kricka, L J; Wilding, P

1996-01-01

The microreaction volumes of PCR chips (a microfabricated silicon chip bonded to a piece of flat glass to form a PCR reaction chamber) create a relatively high surface to volume ratio that increases the significance of the surface chemistry in the polymerase chain reaction (PCR). We investigated several surface passivations in an attempt to identify 'PCR friendly' surfaces and used those surfaces to obtain amplifications comparable with those obtained in conventional PCR amplification systems using polyethylene tubes. Surface passivations by a silanization procedure followed by a coating of a selected protein or polynucleotide and the deposition of a nitride or oxide layer onto the silicon surface were investigated. Native silicon was found to be an inhibitor of PCR and amplification in an untreated PCR chip (i.e. native slicon) had a high failure rate. A silicon nitride (Si(3)N(4) reaction surface also resulted in consistent inhibition of PCR. Passivating the PCR chip using a silanizing agent followed by a polymer treatment resulted in good amplification. However, amplification yields were inconsistent and were not always comparable with PCR in a conventional tube. An oxidized silicon (SiO(2) surface gave consistent amplifications comparable with reactions performed in a conventional PCR tube. PMID:8628665

Self-transducing silicon nanowire electromechanical systems at room temperature.

PubMed

He, Rongrui; Feng, X L; Roukes, M L; Yang, Peidong

2008-06-01

Electronic readout of the motions of genuinely nanoscale mechanical devices at room temperature imposes an important challenge for the integration and application of nanoelectromechanical systems (NEMS). Here, we report the first experiments on piezoresistively transduced very high frequency Si nanowire (SiNW) resonators with on-chip electronic actuation at room temperature. We have demonstrated that, for very thin (~90 nm down to ~30 nm) SiNWs, their time-varying strain can be exploited for self-transducing the devices' resonant motions at frequencies as high as approximately 100 MHz. The strain of wire elongation, which is only second-order in doubly clamped structures, enables efficient displacement transducer because of the enhanced piezoresistance effect in these SiNWs. This intrinsically integrated transducer is uniquely suited for a class of very thin wires and beams where metallization and multilayer complex patterning on devices become impractical. The 30 nm thin SiNW NEMS offer exceptional mass sensitivities in the subzeptogram range. This demonstration makes it promising to advance toward NEMS sensors based on ultrathin and even molecular-scale SiNWs, and their monolithic integration with microelectronics on the same chip.

Active counter electrode in a-SiC electrochemical metallization memory

NASA Astrophysics Data System (ADS)

Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

2017-08-01

Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

Charging/discharging behavior and mechanism of silicon quantum dots embedded in amorphous silicon carbide films

NASA Astrophysics Data System (ADS)

Wen, Xixing; Zeng, Xiangbin; Zheng, Wenjun; Liao, Wugang; Feng, Feng

2015-01-01

The charging/discharging behavior of Si quantum dots (QDs) embedded in amorphous silicon carbide (a-SiCx) was investigated based on the Al/insulating layer/Si QDs embedded in a-SiCx/SiO2/p-Si (metal-insulator-quantum dots-oxide-silicon) multilayer structure by capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. Transmission electron microscopy and Raman scattering spectroscopy measurements reveal the microstructure and distribution of Si QDs. The occurrence and shift of conductance peaks indicate the carrier transfer and the charging/discharging behavior of Si QDs. The multilayer structure shows a large memory window of 5.2 eV at ±8 V sweeping voltage. Analysis of the C-V and G-V results allows a quantification of the Coulomb charging energy and the trapped charge density associated with the charging/discharging behavior. It is found that the memory window is related to the size effect, and Si QDs with large size or low Coulomb charging energy can trap two or more electrons by changing the charging voltage. Meanwhile, the estimated lower potential barrier height between Si QD and a-SiCx, and the lower Coulomb charging energy of Si QDs could enhance the charging and discharging effect of Si QDs and lead to an enlarged memory window. Further studies of the charging/discharging mechanism of Si QDs embedded in a-SiCx can promote the application of Si QDs in low-power consumption semiconductor memory devices.

Intranasal siRNA administration reveals IGF2 deficiency contributes to impaired cognition in Fragile X syndrome mice

PubMed Central

Pardo, Marta; Cheng, Yuyan; Velmeshev, Dmitry; Magistri, Marco; Martinez, Ana; Faghihi, Mohammad A.; Jope, Richard S.; Beurel, Eleonore

2017-01-01

Molecular mechanisms underlying learning and memory remain imprecisely understood, and restorative interventions are lacking. We report that intranasal administration of siRNAs can be used to identify targets important in cognitive processes and to improve genetically impaired learning and memory. In mice modeling the intellectual deficiency of Fragile X syndrome, intranasally administered siRNA targeting glycogen synthase kinase-3β (GSK3β), histone deacetylase-1 (HDAC1), HDAC2, or HDAC3 diminished cognitive impairments. In WT mice, intranasally administered brain-derived neurotrophic factor (BDNF) siRNA or HDAC4 siRNA impaired learning and memory, which was partially due to reduced insulin-like growth factor-2 (IGF2) levels because the BDNF siRNA– or HDAC4 siRNA–induced cognitive impairments were ameliorated by intranasal IGF2 administration. In Fmr1–/– mice, hippocampal IGF2 was deficient, and learning and memory impairments were ameliorated by IGF2 intranasal administration. Therefore intranasal siRNA administration is an effective means to identify mechanisms regulating cognition and to modulate therapeutic targets. PMID:28352664

Intranasal siRNA administration reveals IGF2 deficiency contributes to impaired cognition in Fragile X syndrome mice.

PubMed

Pardo, Marta; Cheng, Yuyan; Velmeshev, Dmitry; Magistri, Marco; Eldar-Finkelman, Hagit; Martinez, Ana; Faghihi, Mohammad A; Jope, Richard S; Beurel, Eleonore

2017-03-23

Molecular mechanisms underlying learning and memory remain imprecisely understood, and restorative interventions are lacking. We report that intranasal administration of siRNAs can be used to identify targets important in cognitive processes and to improve genetically impaired learning and memory. In mice modeling the intellectual deficiency of Fragile X syndrome, intranasally administered siRNA targeting glycogen synthase kinase-3β (GSK3β), histone deacetylase-1 (HDAC1), HDAC2, or HDAC3 diminished cognitive impairments. In WT mice, intranasally administered brain-derived neurotrophic factor (BDNF) siRNA or HDAC4 siRNA impaired learning and memory, which was partially due to reduced insulin-like growth factor-2 (IGF2) levels because the BDNF siRNA- or HDAC4 siRNA-induced cognitive impairments were ameliorated by intranasal IGF2 administration. In Fmr1 -/- mice, hippocampal IGF2 was deficient, and learning and memory impairments were ameliorated by IGF2 intranasal administration. Therefore intranasal siRNA administration is an effective means to identify mechanisms regulating cognition and to modulate therapeutic targets.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology. The goals of the second six months of this project were to conduct high temperature sensing tests using the test chamber and optical sensing instrument designs developed in the first part of the project. In addition, a Phase I goal was to develop the basic processing theory and physics for the proposed first sensor experimentation and data processing. All these goals have been achieved and are described in detail. Both optical experimental design process and sensed temperature are provided. In addition, photographs of the fabricated SiC optical chips after deployment in the high temperature test chamber are shown from a material study point-of-view.« less

On-chip frame memory reduction using a high-compression-ratio codec in the overdrives of liquid-crystal displays

NASA Astrophysics Data System (ADS)

Wang, Jun; Min, Kyeong-Yuk; Chong, Jong-Wha

2010-11-01

Overdrive is commonly used to reduce the liquid-crystal response time and motion blur in liquid-crystal displays (LCDs). However, overdrive requires a large frame memory in order to store the previous frame for reference. In this paper, a high-compression-ratio codec is presented to compress the image data stored in the on-chip frame memory so that only 1 Mbit of on-chip memory is required in the LCD overdrives of mobile devices. The proposed algorithm further compresses the color bitmaps and representative values (RVs) resulting from the block truncation coding (BTC). The color bitmaps are represented by a luminance bitmap, which is further reduced and reconstructed using median filter interpolation in the decoder, while the RVs are compressed using adaptive quantization coding (AQC). Interpolation and AQC can provide three-level compression, which leads to 16 combinations. Using a rate-distortion analysis, we select the three optimal schemes to compress the image data for video graphics array (VGA), wide-VGA LCD, and standard-definitionTV applications. Our simulation results demonstrate that the proposed schemes outperform interpolation BTC both in PSNR (by 1.479 to 2.205 dB) and in subjective visual quality.

DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.

PubMed

Zhou, Xichuan; Li, Shengli; Tang, Fang; Hu, Shengdong; Lin, Zhi; Zhang, Lei

2017-07-18

Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to begin laying the foundations for both the SiC front-end optical chip fabrication techniques for high pressure gas species sensing as well as the design, assembly, and test of a portable high pressure high temperature calibration test cell chamber for introducing gas species. This calibration cell will be used in the remaining months for proposed first stage high pressure high temperature gas species sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for themore » mechanical elements as well as the optical systems are provided. Photographs of the fabricated calibration test chamber cell, the optical sensor setup with the calibration cell, the SiC sample chip holder, and relevant signal processing mathematics are provided. Initial experimental data from both the optical sensor and fabricated test gas species SiC chips is provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature high pressure gas species detection optical sensor technology.« less

Polydimethylsiloxane SlipChip for mammalian cell culture applications.

PubMed

Chang, Chia-Wen; Peng, Chien-Chung; Liao, Wei-Hao; Tung, Yi-Chung

2015-11-07

This paper reports a polydimethylsiloxane (PDMS) SlipChip for in vitro cell culture applications, multiple-treatment assays, cell co-cultures, and cytokine detection assays. The PDMS SlipChip is composed of two PDMS layers with microfluidic channels on each surface that are separated by a thin silicone fluid (Si-fluid) layer. The integration of Si-fluid enables the two PDMS layers to be slid to different positions; therefore, the channel patterns can be re-arranged for various applications. The SlipChip design significantly reduces the complexity of sample handling, transportation, and treatment processes. To apply the developed SlipChip for cell culture applications, human lung adenocarcinoma epithelial cells (A549) and lung fibroblasts (MRC-5) were cultured to examine the biocompatibility of the developed PDMS SlipChip. Moreover, embryonic pluripotent stem cells (ES-D3) were also cultured in the device to evaluate the retention of their stemness in the device. The experimental results show that cell morphology, viability and proliferation are not affected when the cells are cultured in the SlipChip, indicating that the device is highly compatible with mammalian cell culture. In addition, the stemness of the ES-D3 cells was highly retained after they were cultured in the device, suggesting the feasibility of using the SlipChip for stem cell research. Various cell experiments, such as simultaneous triple staining of cells and co-culture of MRC-5 with A549 cells, were also performed to demonstrate the functionalities of the PDMS SlipChip. Furthermore, we used a cytokine detection assay to evaluate the effect of endotoxin (lipopolysaccharides, LPS) treatment on the cytokine secretion of A549 cells using the SlipChip. The developed PDMS SlipChip provides a straightforward and effective platform for various on-chip in vitro cell cultures and consequent analysis, which is promising for a number of cell biology studies and biomedical applications.

Chip-scale white flip-chip light-emitting diode containing indium phosphide/zinc selenide quantum dots

NASA Astrophysics Data System (ADS)

Fan, Bingfeng; Yan, Linchao; Lao, Yuqin; Ma, Yanfei; Chen, Zimin; Ma, Xuejin; Zhuo, Yi; Pei, Yanli; Wang, Gang

2017-08-01

A method for preparing a quantum dot (QD)-white light-emitting diode (WLED) is reported. Holes were etched in the SiO2 layer deposited on the sapphire substrate of the flip-chip LED by inductively coupled plasma, and these holes were then filled with QDs. An ultraviolet-curable resin was then spin-coated on top of the QD-containing SiO2 layer, and the resin was cured to act as a protecting layer. The reflective sidewall structure minimized sidelight leakage. The fabrication of the QD-WLED is simple in preparation and compatible with traditional LED processes, which was the minimum size of the WLED chip-scale integrated package. InP/ZnS core-shell QDs were used as the converter in the WLED. A blue light-emitting diode with a flip-chip structure was used as the excitation source. The QD-WLED exhibited color temperatures from 5900 to 6400 K and Commission Internationale De L'Elcairage color coordinates from (0.315, 0.325) to (0.325, 0.317), under drive currents from 100 to 400 mA. The QD-WLED exhibited stable optoelectronic properties.

Fiber-chip edge coupler with large mode size for silicon photonic wire waveguides.

PubMed

Papes, Martin; Cheben, Pavel; Benedikovic, Daniel; Schmid, Jens H; Pond, James; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, Gonzalo; Ye, Winnie N; Xu, Dan-Xia; Janz, Siegfried; Dado, Milan; Vašinek, Vladimír

2016-03-07

Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO 2 upper cladding thin high-index Si 3 N 4 layers. The Si 3 N 4 layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

A thin film approach for SiC-derived graphene as an on-chip electrode for supercapacitors

NASA Astrophysics Data System (ADS)

Ahmed, Mohsin; Khawaja, Mohamad; Notarianni, Marco; Wang, Bei; Goding, Dayle; Gupta, Bharati; Boeckl, John J.; Takshi, Arash; Motta, Nunzio; Saddow, Stephen E.; Iacopi, Francesca

2015-10-01

We designed a nickel-assisted process to obtain graphene with sheet resistance as low as 80 Ω square-1 from silicon carbide films on Si wafers with highly enhanced surface area. The silicon carbide film acts as both a template and source of graphitic carbon, while, simultaneously, the nickel induces porosity on the surface of the film by forming silicides during the annealing process which are subsequently removed. As stand-alone electrodes in supercapacitors, these transfer-free graphene-on-chip samples show a typical double-layer supercapacitive behaviour with gravimetric capacitance of up to 65 F g-1. This work is the first attempt to produce graphene with high surface area from silicon carbide thin films for energy storage at the wafer-level and may open numerous opportunities for on-chip integrated energy storage applications.

A thin film approach for SiC-derived graphene as an on-chip electrode for supercapacitors.

PubMed

Ahmed, Mohsin; Khawaja, Mohamad; Notarianni, Marco; Wang, Bei; Goding, Dayle; Gupta, Bharati; Boeckl, John J; Takshi, Arash; Motta, Nunzio; Saddow, Stephen E; Iacopi, Francesca

2015-10-30

We designed a nickel-assisted process to obtain graphene with sheet resistance as low as 80 Ω square(-1) from silicon carbide films on Si wafers with highly enhanced surface area. The silicon carbide film acts as both a template and source of graphitic carbon, while, simultaneously, the nickel induces porosity on the surface of the film by forming silicides during the annealing process which are subsequently removed. As stand-alone electrodes in supercapacitors, these transfer-free graphene-on-chip samples show a typical double-layer supercapacitive behaviour with gravimetric capacitance of up to 65 F g(-1). This work is the first attempt to produce graphene with high surface area from silicon carbide thin films for energy storage at the wafer-level and may open numerous opportunities for on-chip integrated energy storage applications.

High Density Schottky Barrier Infrared Charge-Coupled Device (IRCCD) Sensors For Short Wavelength Infrared (SWIR) Applications At Intermediate Temperature

NASA Astrophysics Data System (ADS)

Elabd, H.; Villani, T. S.; Tower, J. R.

1982-11-01

Monolithic 32 x 64 and 64 x 128 palladium silicide (Pd2Si) interline transfer IRCCDs sensitive in the 1-3.5 pm spectral band have been developed. This silicon imager exhibits a low response nonuniformity of typically 0.2-1.6% rms, and has been operated in the temperature range between 40-140K. Spectral response measurements of test Pd2Si p-type Si devices yield quantum efficiencies of 7.9% at 1.25 μm, 5.6% at 1.65 μm and 2.2% at 2.22 μm. Improvement in quantum efficiency is expected by optimizing the different structural parameters of the Pd2Si detectors. The spectral response of the Pd2Si detectors fit a modified Fowler emission model. The measured photo-electric barrier height for the Pd2Si detector is ≍0.34 eV and the measured quantum efficiency coefficient, C1, is 19%/eV. The dark current level of Pd2Si Schottky barrier focal plane arrays (FPAs) is sufficiently low to enable operation at intermediate tem-peratures at TV frame rates. Typical dark current level measured at 120K on the FPA is 2 nA/cm2. The Pd2Si Schottky barrier imaging technology has been developed for satellite sensing of earth resources. The operating temperature of the Pd2Si FPA is compatible with passive cooler performance. In addition, high density Pd2Si Schottky barrier FPAs are manufactured with high yield and therefore represent an economical approach to short wavelength IR imaging. A Pd2Si Schottky barrier image sensor for push-broom multispectral imaging in the 1.25, 1.65, and 2.22 μm bands is being studied. The sensor will have two line arrays (dual band capability) of 512 detectors each, with 30 μm center-to-center detector spacing. The device will be suitable for chip-to-chip abutment, thus providing the capability to produce large, multiple chip focal planes with contiguous, in-line sensors.

High-speed high-resolution epifluorescence imaging system using CCD sensor and digital storage for neurobiological research

NASA Astrophysics Data System (ADS)

Takashima, Ichiro; Kajiwara, Riichi; Murano, Kiyo; Iijima, Toshio; Morinaka, Yasuhiro; Komobuchi, Hiroyoshi

2001-04-01

We have designed and built a high-speed CCD imaging system for monitoring neural activity in an exposed animal cortex stained with a voltage-sensitive dye. Two types of custom-made CCD sensors were developed for this system. The type I chip has a resolution of 2664 (H) X 1200 (V) pixels and a wide imaging area of 28.1 X 13.8 mm, while the type II chip has 1776 X 1626 pixels and an active imaging area of 20.4 X 18.7 mm. The CCD arrays were constructed with multiple output amplifiers in order to accelerate the readout rate. The two chips were divided into either 24 (I) or 16 (II) distinct areas that were driven in parallel. The parallel CCD outputs were digitized by 12-bit A/D converters and then stored in the frame memory. The frame memory was constructed with synchronous DRAM modules, which provided a capacity of 128 MB per channel. On-chip and on-memory binning methods were incorporated into the system, e.g., this enabled us to capture 444 X 200 pixel-images for periods of 36 seconds at a rate of 500 frames/second. This system was successfully used to visualize neural activity in the cortices of rats, guinea pigs, and monkeys.

Light emission from silicon: Some perspectives and applications

NASA Astrophysics Data System (ADS)

Fiory, A. T.; Ravindra, N. M.

2003-10-01

Research on efficient light emission from silicon devices is moving toward leading-edge advances in components for nano-optoelectronics and related areas. A silicon laser is being eagerly sought and may be at hand soon. A key advantage is in the use of silicon-based materials and processing, thereby using high yield and low-cost fabrication techniques. Anticipated applications include an optical emitter for integrated optical circuits, logic, memory, and interconnects; electro-optic isolators; massively parallel optical interconnects and cross connects for integrated circuit chips; lightwave components; high-power discrete and array emitters; and optoelectronic nanocell arrays for detecting biological and chemical agents. The new technical approaches resolve a basic issue with native interband electro-optical emission from bulk Si, which competes with nonradiative phonon- and defect-mediated pathways for electron-hole recombination. Some of the new ways to enhance optical emission efficiency in Si diode devices rely on carrier confinement, including defect and strain engineering in the bulk material. Others use Si nanocrystallites, nanowires, and alloying with Ge and crystal strain methods to achieve the carrier confinement required to boost radiative recombination efficiency. Another approach draws on the considerable progress that has been made in high-efficiency, solar-cell design and uses the reciprocity between photo- and light-emitting diodes. Important advances are also being made with silicon-oxide materials containing optically active rare-earth impurities.

New Surface-Enhanced Raman Sensing Chip Designed for On-Site Detection of Active Ricin in Complex Matrices Based on Specific Depurination.

PubMed

Tang, Ji-Jun; Sun, Jie-Fang; Lui, Rui; Zhang, Zong-Mian; Liu, Jing-Fu; Xie, Jian-Wei

2016-01-27

Quick and accurate on-site detection of active ricin has very important realistic significance in view of national security and defense. In this paper, optimized single-stranded oligodeoxynucleotides named poly(21dA), which function as a depurination substrate of active ricin, were screened and chemically attached on gold nanoparticles (AuNPs, ∼100 nm) via the Au-S bond [poly(21dA)-AuNPs]. Subsequently, poly(21dA)-AuNPs were assembled on a dihydrogen lipoic-acid-modified Si wafer (SH-Si), thus forming the specific surface-enhanced Raman spectroscopy (SERS) chip [poly(21dA)-AuNPs@SH-Si] for depurination of active ricin. Under optimized conditions, active ricin could specifically hydrolyze multiple adenines from poly(21dA) on the chip. This depurination-induced composition change could be conveniently monitored by measuring the distinct attenuation of the SERS signature corresponding to adenine. To improve sensitivity of this method, a silver nanoshell was deposited on post-reacted poly(21dA)-AuNPs, which lowered the limit of detection to 8.9 ng mL(-1). The utility of this well-controlled SERS chip was successfully demonstrated in food and biological matrices spiked with different concentrations of active ricin, thus showing to be very promising assay for reliable and rapid on-site detection of active ricin.

Nanoelectromechanical Chip (NELMEC) Combination of Nanoelectronics and Microfluidics to Diagnose Epithelial and Mesenchymal Circulating Tumor Cells from Leukocytes.

PubMed

Hosseini, Seied Ali; Abdolahad, Mohammad; Zanganeh, Somayeh; Dahmardeh, Mahyar; Gharooni, Milad; Abiri, Hamed; Alikhani, Alireza; Mohajerzadeh, Shams; Mashinchian, Omid

2016-02-17

An integrated nano-electromechanical chip (NELMEC) has been developed for the label-free distinguishing of both epithelial and mesenchymal circulating tumor cells (ECTCs and MCTCs, respectively) from white blood cells (WBCs). This nanoelectronic microfluidic chip fabricated by silicon micromachining can trap large single cells (>12 µm) at the opening of the analysis microchannel arrays. The nature of the captured cells is detected using silicon nanograss (SiNG) electrodes patterned at the entrance of the channels. There is an observable difference between the membrane capacitance of the ECTCs and MCTCs and that of WBCs (measured using SiNG electrodes), which is the key indication for our diagnosis. The NELMEC chip not only solves the problem of the size overlap between CTCs and WBCs but also detects MCTCs without the need for any markers or tagging processes, which has been an important problem in previously reported CTC detection systems. The great conductivity of the gold-coated SiNG nanocontacts as well as their safe penetration into the membrane of captured cells, facilitate a precise and direct signal extraction to distinguish the type of captured cell. The results achieved from epithelial (MCF-7) and mesenchymal (MDA-MB231) breast cancer cells circulated in unprocessed blood suggest the significant applications for these diagnostic abilities of NELMEC. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

76 FR 79215 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-12-21

... 1930, as amended, 19 U.S.C. 1337, on behalf of Elpida Memory, Inc. of Tokyo, Japan and Elpida Memory... of investigation shall be served: (a) The complainants are: Elpida Memory, Inc., Sumitomo Seimei Yaesu Bldg. 3F, 2-1 Yaesu 2-chome, Chuo-ku, Tokyo 104-0028, Japan. Elpida Memory (USA) Inc., 1175 Sonora...

Fabrication of magnetic bubble memory overlay

NASA Technical Reports Server (NTRS)

1973-01-01

Self-contained magnetic bubble memory overlay is fabricated by process that employs epitaxial deposition to form multi-layered complex of magnetically active components on single chip. Overlay fabrication comprises three metal deposition steps followed by subtractive etch.

An optofluidic approach for gold nanoprobes based-cancer theranostics

NASA Astrophysics Data System (ADS)

Panwar, Nishtha; Song, Peiyi; Yang, Chengbin; Yong, Ken-Tye; Tjin, Swee Chuan

2017-02-01

Suppression of overexpressed gene mutations in cancer cells through RNA interference (RNAi) technique is a therapeutically effective modality for oncogene silencing. In general, transfection agent is needed for siRNA delivery. Also, it is a tedious and time consuming process to analyze the gene transfection using current conventional flow cytometry systems and commercially available transfection kits. Therefore, there are two urgent challenges that we need to address for understanding and real time monitoring the delivery of siRNA to cancer cells more effectively. One, nontoxic, biocompatible and stable non-viral transfection agents need to be developed and investigated for gene delivery in cancer cells. Two, new, portable optofluidic methods need to be engineered for determining the transfection efficiency of the nanoformulation in real time. First, we demonstrate the feasibility of using gold nanorods (AuNRs) as nanoprobes for the delivery of Interleukin-8 (IL-8) siRNA in a pancreatic cancer cell line- MiaPaCa-2. An optimum ratio of 10:1 for the AuNRs-siRNA nanoformulation required for efficient loading has been experimentally determined. Promising transfection rates (≈88%) of the nanoprobe-assisted gene delivery are quantified by flow cytometry and fluorescence imaging, which are higher than the commercial control, Oligofectamine. The excellent gene knockdown performance (over 81%) of the proposed model support in vivo trials for RNAi-based cancer theranostics. In addition to cancer theranostics, our nanoprobe combination can be also applied for disease outbreak monitoring like MERS. Second, we present an optical fiber-integrated microfluidic chip that utilizes simple hydrodynamic and optical setups for miniaturized on-chip flow cytometry. The chip provides a powerful and convenient tool to quantitatively determine the siRNA transfection into cancer cells without using bulky flow cytometer. These studies outline the role of AuNRs as potential non-viral gene delivery vehicles, and their suitability for microfluidics-based lab-on-chip flow cytometry applications.

Self-Compliant Bipolar Resistive Switching in SiN-Based Resistive Switching Memory

PubMed Central

Kim, Sungjun; Chang, Yao-Feng; Kim, Min-Hwi; Kim, Tae-Hyeon; Kim, Yoon; Park, Byung-Gook

2017-01-01

Here, we present evidence of self-compliant and self-rectifying bipolar resistive switching behavior in Ni/SiNx/n+ Si and Ni/SiNx/n++ Si resistive-switching random access memory devices. The Ni/SiNx/n++ Si device’s Si bottom electrode had a higher dopant concentration (As ion > 1019 cm−3) than the Ni/SiNx/n+ Si device; both unipolar and bipolar resistive switching behaviors were observed for the higher dopant concentration device owing to a large current overshoot. Conversely, for the device with the lower dopant concentration (As ion < 1018 cm−3), self-rectification and self-compliance were achieved owing to the series resistance of the Si bottom electrode. PMID:28772819

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

CMOS imager for pointing and tracking applications

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

NASA Astrophysics Data System (ADS)

Ahmad, Salleh; Fleury, Julien; de la Taille, Christophe; Seguin-Moreau, Nathalie; Dulucq, Frederic; Martin-Chassard, Gisele; Callier, Stephane; Thienpont, Damien; Raux, Ludovic

2015-06-01

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

Evaluation of 1.5-T Cell Flash Memory Total Ionizing Dose Response

NASA Astrophysics Data System (ADS)

Clark, Lawrence T.; Holbert, Keith E.; Adams, James W.; Navale, Harshad; Anderson, Blake C.

2015-12-01

Flash memory is an essential part of systems used in harsh environments, experienced by both terrestrial and aerospace TID applications. This paper presents studies of COTS flash memory TID hardness. While there is substantial literature on flash memory TID response, this work focuses for the first time on 1.5 transistor per cell flash memory. The experimental results show hardness varying from about 100 krad(Si) to over 250 krad(Si) depending on the usage model. We explore the circuit and device aspects of the results, based on the extensive reliability literature for this flash memory type. Failure modes indicate both device damage and circuit marginalities. Sector erase failure limits, but read only operation allows TID exceeding 200 krad(Si). The failures are analyzed by type.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deptuch, Gregory; Hoff, James; Jindariani, Sergo

Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available and speed performance must be improved over previous systems while maintaining a comparable number of patterns. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology. The firstmore » step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. In this paper, we present the results from extensive performance studies of the protoVIPRAM00 chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3D stacking. We also present performance boundary characterization of the chip under extreme conditions.« less

An Automatic Baseline Regulation in a Highly Integrated Receiver Chip for JUNO

NASA Astrophysics Data System (ADS)

Muralidharan, P.; Zambanini, A.; Karagounis, M.; Grewing, C.; Liebau, D.; Nielinger, D.; Robens, M.; Kruth, A.; Peters, C.; Parkalian, N.; Yegin, U.; van Waasen, S.

2017-09-01

This paper describes the data processing unit and an automatic baseline regulation of a highly integrated readout chip (Vulcan) for JUNO. The chip collects data continuously at 1 Gsamples/sec. The Primary data processing which is performed in the integrated circuit can aid to reduce the memory and data processing efforts in the subsequent stages. In addition, a baseline regulator compensating a shift in the baseline is described.

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

A convenient method of manufacturing liquid-gated MoS2 field effect transistors

NASA Astrophysics Data System (ADS)

Lin, Kabin; Yuan, Zhishan; Yu, Yu; Li, Kun; Li, Zhongwu; Sha, Jingjie; Li, Tie; Chen, Yunfei

2017-10-01

In this paper, we present a simple and convenient method of manufacturing liquid-gated MoS2 field effect transistors (FETs). A Si3N4 chip is firstly fabricated by the semiconductor manufacturing process, then the mechanical exfoliation MoS2 is transferred onto the Si3N4 chip and is connected with the gold electrodes by depositing platinum to construct the MoS2 FETs. The liquid-gated is formed by injecting 0.1 M NaCl solution into reservoir to contact the back side of the Si3N4. Our measured results show that the contact properties between MoS2 and electrodes are in well condition and the liquid-gated MoS2 FETs have a high mobility that can reach up to 109 cm2 V-1 s-1.

75 FR 32803 - Notice of Issuance of Final Determination Concerning a GTX Mobile+ Hand Held Computer

Federal Register 2010, 2011, 2012, 2013, 2014

2010-06-09

... Programmable Read-Only Memory (``PROM'') chip, substantially transformed the PROM into a U.S. article. The... parts (such as various connectors and an Electronically Erasable Programmable Read Only Memory, or...

78 FR 53159 - Certain Semiconductor Chips With Dram Circuitry, and Modules and Products Containing Same: Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-28

... instituted this investigation on December 21, 2011, based on a complaint filed by Elpida Memory, Inc., of Tokyo, Japan, and Elpida Memory (USA) Inc. of Sunnyvale, California (collectively, ``Elpida''). 76 FR...

Nonvolatile memory with Co-SiO2 core-shell nanocrystals as charge storage nodes in floating gate

NASA Astrophysics Data System (ADS)

Liu, Hai; Ferrer, Domingo A.; Ferdousi, Fahmida; Banerjee, Sanjay K.

2009-11-01

In this letter, we reported nanocrystal floating gate memory with Co-SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co-SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance.

A 16K-bit static IIL RAM with 25-ns access time

NASA Astrophysics Data System (ADS)

Inabe, Y.; Hayashi, T.; Kawarada, K.; Miwa, H.; Ogiue, K.

1982-04-01

A 16,384 x 1-bit RAM with 25-ns access time, 600-mW power dissipation, and 33 sq mm chip size has been developed. Excellent speed-power performance with high packing density has been achieved by an oxide isolation technology in conjunction with novel ECL circuit techniques and IIL flip-flop memory cells, 980 sq microns (35 x 28 microns) in cell size. Development results have shown that IIL flip-flop memory cell is a trump card for assuring achievement of a high-performance large-capacity bipolar RAM, in the above 16K-bit/chip area.

Binary synaptic connections based on memory switching in a-Si:H for artificial neural networks

NASA Technical Reports Server (NTRS)

Thakoor, A. P.; Lamb, J. L.; Moopenn, A.; Khanna, S. K.

1987-01-01

A scheme for nonvolatile associative electronic memory storage with high information storage density is proposed which is based on neural network models and which uses a matrix of two-terminal passive interconnections (synapses). It is noted that the massive parallelism in the architecture would require the ON state of a synaptic connection to be unusually weak (highly resistive). Memory switching using a-Si:H along with ballast resistors patterned from amorphous Ge-metal alloys is investigated for a binary programmable read only memory matrix. The fabrication of a 1600 synapse test array of uniform connection strengths and a-Si:H switching elements is discussed.

77 FR 33240 - Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-05

... viewed on the Commission's electronic docket (EDIS) at http://edis.usitc.gov . Hearing-impaired persons... December 21, 2011, based on a complaint filed by Elpida Memory, Inc. of Tokyo, Japan and Elpida Memory (USA...

Optically Addressable, Ferroelectric Memory With NDRO

NASA Technical Reports Server (NTRS)

Thakoor, Sarita

1994-01-01

For readout, memory cells addressed via on-chip semiconductor lasers. Proposed thin-film ferroelectric memory device features nonvolatile storage, optically addressable, nondestructive readout (NDRO) with fast access, and low vulnerability to damage by ionizing radiation. Polarization switched during recording and erasure, but not during readout. As result, readout would not destroy contents of memory, and operating life in specific "read-intensive" applications increased up to estimated 10 to the 16th power cycles.

RAM Technology Study.

DTIC Science & Technology

1980-01-03

characteristics. 4 2 Example of MOS scaling. 18 3 RAM chip area comparison. 31 4 Summary of RAM switching response. 34 5 Summary of RAM power dissipation...array to retain the data after power is removed (volatility). The level of chip complexity is that of the most complex arrays in current production and is...4) ..4 L) . C U ~~~~ -- -- t 0 -, 4 4 . . Data in the Read-Only-Memory is defined by the metallization pattern during chip fabrication. The stored

PECVD based silicon oxynitride thin films for nano photonic on chip interconnects applications.

PubMed

Sharma, Satinder K; Barthwal, Sumit; Singh, Vikram; Kumar, Anuj; Dwivedi, Prabhat K; Prasad, B; Kumar, Dinesh

2013-01-01

Thin silicon oxynitride (SiO(x)N(y)) films were deposited by low temperature (~300°C) plasma enhanced chemical vapour deposition (PECVD), using SiH(4), N(2)O, NH(3) precursor of the flow rate 25, 100, 30 sccm and subjected to the post deposition annealing (PDA) treatment at 400°C and 600°C for nano optical/photonics on chip interconnects applications. AFM result reveals the variation of roughness from 60.9 Å to 23.4 Å after PDA treatment with respect to the as-deposited films, favourable surface topography for integrated waveguide applications. A model of decrease in island height with the effect of PDA treatment is proposed in support of AFM results. Raman spectroscopy and FTIR measurements are performed in order to define the change in crystallite and chemical bonding of as-deposited as well as PDA treated samples. These outcomes endorsed to the densification of SiO(x)N(y) thin films, due to decrease in Si-N and Si-O bonds strain, as well the O-H, N-H bonds with in oxynitride network. The increase in refractive index and PL intensity of as deposited SiO(x)N(y) thin films to the PDA treated films at 400°C and 600°C are observed. The significant shift of PL spectra peak positions indicate the change in cluster size as the result of PDA treatment, which influence the optical properties of thin films. It might be due to out diffusion of hydrogen containing species from silicon oxynitride films after PDA treatment. In this way, the structural and optical, feasibility of SiO(x)N(y) films are demonstrated in order to obtain high quality thin films for nano optical/photonics on chip interconnects applications. Copyright © 2012 Elsevier Ltd. All rights reserved.

Micromirror structure actuated by TiNi shape memory thin films

NASA Astrophysics Data System (ADS)

Fu, Y. Q.; Luo, J. K.; Hu, M.; Du, H. J.; Flewitt, A. J.; Milne, W. I.

2005-10-01

TiNi films were deposited by co-sputtering TiNi and Ti targets. Results from differential scanning calorimetry and curvature measurement revealed martensitic transformation and shape memory effect upon heating and cooling. Two types of TiNi/Si micromirror structures with a Si mirror cap (40 µm thick) and TiNi/Si actuation beams were designed and fabricated. For the first design, a V-shaped cantilever based on the TiNi/Si bimorph structure was used as the actuation mechanism for the micromirror. In the second design, three elbow-shaped Si beams with TiNi electrodes were used as the arms to actuate the mirror. The TiNi/Si microbeams were flat at room temperature and bent up by applying voltage in the TiNi electrodes (due to phase transformation and shape memory effect), thus causing changes in angles of the micromirror.

3D Stacked Memory Final Report CRADA No. TC-0494-93

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernhardt, A.; Beene, G.

TI and LLNL demonstrated: (1) a process for the fabrication of 3-D memory using stacked DRAM chips, and (2) a fast prototyping process for 3-D stacks and MCMs. The metallization to route the chip pads to the sides of the die was carried out in a single high-speed masking step. The mask was not the usual physical one in glass and chrome, but was simply a computer file used to control the laser patterning process. Changes in either chip or customer circuit-board pad layout were easily and inexpensively accommodated, so that prototyping was a natural consequence of the laser patterningmore » process. As in the current TI process, a dielectric layer was added to the wafer, and vias to the chip I/0 pads were formed. All of the steps in Texas Instruments earlier process that were required to gold bump the pads were eliminated, significantly reducing fabrication cost and complexity. Pads were created on the sides of ·the die, which became pads on the side of the stack. In order to extend the process to accommodate non-memory devices with substantially greater I/0 than is required for DRAMs, pads were patterned on two sides of the memory stacks as a proof of principle. Stacking and bonding were done using modifications of the current TI process. After stacking and bonding, the pads on the sides of the dice were connected by application of a polyimide insulator film with laser ablation of the polyimide to form contacts to the pads. Then metallization was accomplished in the same manner as on the individual die.« less

Architectural Techniques For Managing Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making themmore » a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.« less

76 FR 72214 - Certain Semiconductor Chips with DRAM Circuitry, and Modules and Products Containing Same Receipt...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-11-22

...://edis.usitc.gov . Hearing-impaired persons are advised that information on this matter can be obtained... Commission has received a complaint filed on behalf of Elpida Memory, Inc. and Elpida Memory (USA) Inc. on...

High performance SONOS flash memory with in-situ silicon nanocrystals embedded in silicon nitride charge trapping layer

NASA Astrophysics Data System (ADS)

Lim, Jae-Gab; Yang, Seung-Dong; Yun, Ho-Jin; Jung, Jun-Kyo; Park, Jung-Hyun; Lim, Chan; Cho, Gyu-seok; Park, Seong-gye; Huh, Chul; Lee, Hi-Deok; Lee, Ga-Won

2018-02-01

In this paper, SONOS-type flash memory device with highly improved charge-trapping efficiency is suggested by using silicon nanocrystals (Si-NCs) embedded in silicon nitride (SiNX) charge trapping layer. The Si-NCs were in-situ grown by PECVD without additional post annealing process. The fabricated device shows high program/erase speed and retention property which is suitable for multi-level cell (MLC) application. Excellent performance and reliability for MLC are demonstrated with large memory window of ∼8.5 V and superior retention characteristics of 7% charge loss for 10 years. High resolution transmission electron microscopy image confirms the Si-NC formation and the size is around 1-2 nm which can be verified again in X-ray photoelectron spectroscopy (XPS) where pure Si bonds increase. Besides, XPS analysis implies that more nitrogen atoms make stable bonds at the regular lattice point. Photoluminescence spectra results also illustrate that Si-NCs formation in SiNx is an effective method to form deep trap states.

Fault Tolerant Cache Schemes

NASA Astrophysics Data System (ADS)

Tu, H.-Yu.; Tasneem, Sarah

Most of modern microprocessors employ on—chip cache memories to meet the memory bandwidth demand. These caches are now occupying a greater real es tate of chip area. Also, continuous down scaling of transistors increases the possi bility of defects in the cache area which already starts to occupies more than 50% of chip area. For this reason, various techniques have been proposed to tolerate defects in cache blocks. These techniques can be classified into three different cat egories, namely, cache line disabling, replacement with spare block, and decoder reconfiguration without spare blocks. This chapter examines each of those fault tol erant techniques with a fixed typical size and organization of L1 cache, through extended simulation using SPEC2000 benchmark on individual techniques. The de sign and characteristics of each technique are summarized with a view to evaluate the scheme. We then present our simulation results and comparative study of the three different methods.

Fault Tolerant Characteristics of Artificial Neural Network Electronic Hardware

NASA Technical Reports Server (NTRS)

Zee, Frank

1995-01-01

The fault tolerant characteristics of analog-VLSI artificial neural network (with 32 neurons and 532 synapses) chips are studied by exposing them to high energy electrons, high energy protons, and gamma ionizing radiations under biased and unbiased conditions. The biased chips became nonfunctional after receiving a cumulative dose of less than 20 krads, while the unbiased chips only started to show degradation with a cumulative dose of over 100 krads. As the total radiation dose increased, all the components demonstrated graceful degradation. The analog sigmoidal function of the neuron became steeper (increase in gain), current leakage from the synapses progressively shifted the sigmoidal curve, and the digital memory of the synapses and the memory addressing circuits began to gradually fail. From these radiation experiments, we can learn how to modify certain designs of the neural network electronic hardware without using radiation-hardening techniques to increase its reliability and fault tolerance.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Investigation of the development of optically controlled memory elements on the basis of multilayer semiconductor-dielectric structures

NASA Astrophysics Data System (ADS)

Plotnikov, A. F.; Seleznev, V. N.

The possibility of reverse optical recording in MNOS structures of Me-Si3N4-SiO2-Si type is investigated. Charge-transfer processes in traps under the effect of electric pulses are examined, and attention is given to the application of laser switching and photoelectric reading techniques to such structures. The principal energetic and temporal characteristics of such optical memories are examined, and the organization of a high-capacity (greater than 100-million bits) optical memory is discussed.

In Situ Investigation of Electrochemically Mediated Surface-Initiated Atom Transfer Radical Polymerization by Electrochemical Surface Plasmon Resonance.

PubMed

Chen, Daqun; Hu, Weihua

2017-04-18

Electrochemically mediated atom transfer radical polymerization (eATRP) initiates/controls the controlled/living ATRP chain propagation process by electrochemically generating (regenerating) the activator (lower-oxidation-state metal complex) from deactivator (higher-oxidation-state metal complex). Despite successful demonstrations in both of the homogeneous polymerization and heterogeneous systems (namely, surface-initiated ATRP, SI-ATRP), the eATRP process itself has never been in situ investigated, and important information regarding this process remains unrevealed. In this work, we report the first investigation of the electrochemically mediated SI-ATRP (eSI-ATRP) by rationally combining the electrochemical technique with real-time surface plasmon resonance (SPR). In the experiment, the potential of a SPR gold chip modified by the self-assembled monolayer of the ATRP initiator was controlled to electrochemically reduce the deactivator to activator to initiate the SI-ATRP, and the whole process was simultaneously monitored by SPR with a high time resolution of 0.1 s. It is found that it is feasible to electrochemically trigger/control the SI-ATRP and the polymerization rate is correlated to the potential applied to the gold chip. This work reveals important kinetic information for eSI-ATRP and offers a powerful platform for in situ investigation of such complicated processes.

Computer Algorithms and Architectures for Three-Dimensional Eddy-Current Nondestructive Evaluation. Volume 3. Chapters 6-11

DTIC Science & Technology

1989-01-20

addressable memory can be loaded or off- loaded as the number crunching continues. Modem VLSI processors can often process data faster than today’s...Available DSP Chips Texas Instruments was one of the first serious manufacturers of DSP chips. With the Texas Instruments TMS310 DSP chip, modem , voice...Can handle double presicion data types. Texas Instruments TMS32010 T’s first-generation DSP design: a fixed-point DSP that has found its way into modem

Programmable Direct-Memory-Access Controller

NASA Technical Reports Server (NTRS)

Hendry, David F.

1990-01-01

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

Ultra-dense magnetoresistive mass memory

NASA Technical Reports Server (NTRS)

Daughton, J. M.; Sinclair, R.; Dupuis, T.; Brown, J.

1992-01-01

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Forming-free performance of a-SiN x :H-based resistive switching memory obtained by oxygen plasma treatment.

PubMed

Zhang, Xinxin; Ma, Zhongyuan; Zhang, Hui; Liu, Jian; Yang, Huafeng; Sun, Yang; Tan, Dinwen; Li, Wei; Xu, Ling; Chen, Kuiji; Feng, Duan

2018-06-15

An a-SiN x -based resistive random access memory (RRAM) device with a forming-free characteristic has significant potentials for the industrialization of the next-generation memories. We demonstrate that a forming-free a-SiN x O y RRAM device can be achieved by an oxygen plasma treatment of ultra-thin a-SiN x :H films. Electron spin resonance spectroscopy reveals that Si dangling bonds with a high density (10 19 cm -3 ) are distributed in the initial state, which exist in the forms of Si 2 N≡Si·, SiO 2 ≡Si·, O 3 ≡Si·, and N 3 ≡Si·. X-ray photoelectron spectroscopy and temperature-dependent current analyses reveal that the silicon dangling bonds induced by the oxygen plasma treatment and external electric field contribute to the low resistance state (LRS). For the high resistance state (HRS), the rupture of the silicon dangling bond pathway is attributed to the partial passivation of Si dangling bonds by H + and O 2- . Both LRS and HRS transmissions obey the hopping conduction model. The proposed oxygen plasma treatment, introduced to generate a high density of Si dangling bonds in the SiN x O y :H films, provides a new approach to forming-free RRAM devices.

Forming-free performance of a-SiN x :H-based resistive switching memory obtained by oxygen plasma treatment

NASA Astrophysics Data System (ADS)

Zhang, Xinxin; Ma, Zhongyuan; Zhang, Hui; Liu, Jian; Yang, Huafeng; Sun, Yang; Tan, Dinwen; Li, Wei; Xu, Ling; Chen, Kuiji; Feng, Duan

2018-06-01

An a-SiN x -based resistive random access memory (RRAM) device with a forming-free characteristic has significant potentials for the industrialization of the next-generation memories. We demonstrate that a forming-free a-SiN x O y RRAM device can be achieved by an oxygen plasma treatment of ultra-thin a-SiN x :H films. Electron spin resonance spectroscopy reveals that Si dangling bonds with a high density (1019 cm‑3) are distributed in the initial state, which exist in the forms of Si2N≡Si·, SiO2≡Si·, O3≡Si·, and N3≡Si·. X-ray photoelectron spectroscopy and temperature-dependent current analyses reveal that the silicon dangling bonds induced by the oxygen plasma treatment and external electric field contribute to the low resistance state (LRS). For the high resistance state (HRS), the rupture of the silicon dangling bond pathway is attributed to the partial passivation of Si dangling bonds by H+ and O2‑. Both LRS and HRS transmissions obey the hopping conduction model. The proposed oxygen plasma treatment, introduced to generate a high density of Si dangling bonds in the SiN x O y :H films, provides a new approach to forming-free RRAM devices.

Measurements with Si and GaAs pixel detectors bonded to photon counting readout chips

NASA Astrophysics Data System (ADS)

Schwarz, C.; Campbell, M.; Goeppert, R.; Ludwig, J.; Mikulec, B.; Runge, K.; Smith, K. M.; Snoeys, W.

2001-06-01

Detectors fabricated with SI-GaAs and Si bulk material were bonded to Photon Counting Chips (PCC), developed in the framework of the MEDIPIX Collaboration. The PCC consists of a matrix of 64×64 identical square pixels (170 μm×170 μm) with a 15-bit counter in each cell. We investigated the imaging properties of these detector systems under exposure of a dental X-ray tube at room temperature. The image homogeneity and the mean count rate were determined via flood exposure images and compared. Exposures for GaAs detectors exhibit a 3 times larger spread in count rate per image in comparison to Si detectors. This also results in a 3 times worse signal to noise ratio. IV-characteristics and X-ray images at different values of the detectors bias voltage were also taken and show a 30 times higher leakage current for GaAs. The Si detector is fully active beginning from 70 V, whereas the GaAs detector does not reach full charge collection. The presampling modulation transfer function of both assembly types was measured via slit images and gives a spatial resolution of 4.3 lp/mm for both detector systems.

Miniaturized tool for optogenetics based on an LED and an optical fiber interfaced by a silicon housing.

PubMed

Schwaerzle, M; Elmlinger, P; Paul, O; Ruther, P

2014-01-01

This paper reports on the design, simulation, fabrication and characterization of a tool for optogenetic experiments based on a light emitting diode (LED). A minimized silicon (Si) interface houses the LED and aligns it to an optical fiber. With a Si housing size of 550×500×380 μm(3) and an electrical interconnection of the LED by a highly flexible polyimide (PI) ribbon cable is the system very variable. PI cables and Si housings are fabricated using established microsystem technologies. A 270×220×50 μm(3) bare LED chip is flip-chip-bonded onto the PI cable. The Si housing is adhesively attached to the PI cable, thereby hosting the LED in a recess. An opposite recess guides the optical fiber with a diameter of 125 μm. An aperture in-between restricts the emitted LED light to the fiber core. The optical fiber is adhesively fixed into the Si housing recess. An optical output intensity at the fiber end facet of 1.71 mW/mm(2) was achieved at a duty cycle of 10 % and a driving current of 30 mA.

Hybrid integration of laser source on silicon photonic integrated circuit for low-cost interferometry medical device

NASA Astrophysics Data System (ADS)

Duperron, Matthieu; Carroll, Lee; Rensing, Marc; Collins, Sean; Zhao, Yan; Li, Yanlu; Baets, Roel; O'Brien, Peter

2017-02-01

The cost-effective integration of laser sources on Silicon Photonic Integrated Circuits (Si-PICs) is a key challenge to realizing the full potential of on-chip photonic solutions for telecommunication and medical applications. Hybrid integration can offer a route to high-yield solutions, using only known-good laser-chips, and simple freespace micro-optics to transport light from a discrete laser-diode to a grating-coupler on the Si-PIC. In this work, we describe a passively assembled micro-optical bench (MOB) for the hybrid integration of a 1550nm 20MHz linewidth laser-diode on a Si-PIC, developed for an on-chip interferometer based medical device. A dual-lens MOB design minimizes aberrations in the laser spot transported to the standard grating-coupler (15 μm x 12 μm) on the Si-PIC, and facilitates the inclusion of a sub-millimeter latched-garnet optical-isolator. The 20dB suppression from the isolator helps ensure the high-frequency stability of the laser-diode, while the high thermal conductivity of the AlN submount (300/W=m.°C), and the close integration of a micro-bead thermistor, ensure the stable and efficient thermo-electric cooling of the laser-diode, which helps minimise low-frequency drift during the approximately 15s of operation needed for the point-of-care measurement. The dual-lens MOB is compatible with cost-effective passively-aligned mass-production, and can be optimised for alternative PIC-based applications.

A design of Si-based nanoplasmonic structure as an antenna and reception amplifier for visible light communication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, J. H.; Lin, Z. Y.; Liu, P.

2014-10-21

Visible light communication has been widely investigated due to its larger bandwidth and higher bit rate, and it can combine with the indoor illumination system that makes it more convenient to carry out. Receiving and processing the visible light signal on chip request for nanophotonics devices performing well. However, conventional optical device cannot be used for light-on-chip integration at subwavelength dimensions due to the diffraction limit. Herein, we propose a design of Si-based nanoplasmonic structure as an antenna and reception amplifier for visible light communication based on the interaction between Si nanoparticle and Au nanorod. This device integrates the uniquemore » scattering property of high-refractive index dielectric Si nanoparticles, whose scattering spectrum is dependent on the particle size, with the localized surface plasmon resonance of Au nanorod. We calculated the spectra collected by plane detector and near field distribution of nanostructure, and theoretically demonstrate that the proposed device can act as good receiver, amplifier and superlens during the visible light signal receiving and processing. Besides, unlike some other designs of nanoantenna devices focused less on how to detect the signals, our hybrid nanoantenna can realize the transfer between the scattering source and the detector effectively by Au nanorod waveguides. These findings suggest that the designed nanoplasmonic structure is expected to be used in on-chip nanophotonics as antenna, spectral splitter and demultiplexer for visible light communication.« less

Forming-free and self-rectifying resistive switching of the simple Pt/TaOx/n-Si structure for access device-free high-density memory application

NASA Astrophysics Data System (ADS)

Gao, Shuang; Zeng, Fei; Li, Fan; Wang, Minjuan; Mao, Haijun; Wang, Guangyue; Song, Cheng; Pan, Feng

2015-03-01

The search for self-rectifying resistive memories has aroused great attention due to their potential in high-density memory applications without additional access devices. Here we report the forming-free and self-rectifying bipolar resistive switching behavior of a simple Pt/TaOx/n-Si tri-layer structure. The forming-free phenomenon is attributed to the generation of a large amount of oxygen vacancies, in a TaOx region that is in close proximity to the TaOx/n-Si interface, via out-diffusion of oxygen ions from TaOx to n-Si. A maximum rectification ratio of ~6 × 102 is obtained when the Pt/TaOx/n-Si devices stay in a low resistance state, which originates from the existence of a Schottky barrier between the formed oxygen vacancy filament and the n-Si electrode. More importantly, numerical simulation reveals that the self-rectifying behavior itself can guarantee a maximum crossbar size of 212 × 212 (~44 kbit) on the premise of 10% read margin. Moreover, satisfactory switching uniformity and retention performance are observed based on this simple tri-layer structure. All of these results demonstrate the great potential of this simple Pt/TaOx/n-Si tri-layer structure for access device-free high-density memory applications.The search for self-rectifying resistive memories has aroused great attention due to their potential in high-density memory applications without additional access devices. Here we report the forming-free and self-rectifying bipolar resistive switching behavior of a simple Pt/TaOx/n-Si tri-layer structure. The forming-free phenomenon is attributed to the generation of a large amount of oxygen vacancies, in a TaOx region that is in close proximity to the TaOx/n-Si interface, via out-diffusion of oxygen ions from TaOx to n-Si. A maximum rectification ratio of ~6 × 102 is obtained when the Pt/TaOx/n-Si devices stay in a low resistance state, which originates from the existence of a Schottky barrier between the formed oxygen vacancy filament and the n-Si electrode. More importantly, numerical simulation reveals that the self-rectifying behavior itself can guarantee a maximum crossbar size of 212 × 212 (~44 kbit) on the premise of 10% read margin. Moreover, satisfactory switching uniformity and retention performance are observed based on this simple tri-layer structure. All of these results demonstrate the great potential of this simple Pt/TaOx/n-Si tri-layer structure for access device-free high-density memory applications. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr06406b

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 2: The optimization of material-device parameters for application in bubble domain memory elements for spacecraft data recorders

NASA Technical Reports Server (NTRS)

Besser, P. J.

1976-01-01

Bubble domain materials and devices are discussed. One of the materials development goals was a materials system suitable for operation of 16 micrometer period bubble domain devices at 150 kHz over the temperature range -10 C to +60 C. Several material compositions and hard bubble suppression techniques were characterized and the most promising candidates were evaluated in device structures. The technique of pulsed laser stroboscopic microscopy was used to characterize bubble dynamic properties and device performance at 150 kHz. Techniques for large area LPE film growth were developed as a separate task. Device studies included detector optimization, passive replicator design and test and on-chip bridge evaluation. As a technology demonstration an 8 chip memory cell was designed, tested and delivered. The memory elements used in the cell were 10 kilobit serial registers.

Fault-tolerant computer study. [logic designs for building block circuits

NASA Technical Reports Server (NTRS)

Rennels, D. A.; Avizienis, A. A.; Ercegovac, M. D.

1981-01-01

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.

Key Technologies of Phone Storage Forensics Based on ARM Architecture

NASA Astrophysics Data System (ADS)

Zhang, Jianghan; Che, Shengbing

2018-03-01

Smart phones are mainly running Android, IOS and Windows Phone three mobile platform operating systems. The android smart phone has the best market shares and its processor chips are almost ARM software architecture. The chips memory address mapping mechanism of ARM software architecture is different with x86 software architecture. To forensics to android mart phone, we need to understand three key technologies: memory data acquisition, the conversion mechanism from virtual address to the physical address, and find the system’s key data. This article presents a viable solution which does not rely on the operating system API for a complete solution to these three issues.

Protection of data carriers using secure optical codes

NASA Astrophysics Data System (ADS)

Peters, John A.; Schilling, Andreas; Staub, René; Tompkin, Wayne R.

2006-02-01

Smartcard technologies, combined with biometric-enabled access control systems, are required for many high-security government ID card programs. However, recent field trials with some of the most secure biometric systems have indicated that smartcards are still vulnerable to well equipped and highly motivated counterfeiters. In this paper, we present the Kinegram Secure Memory Technology which not only provides a first-level visual verification procedure, but also reinforces the existing chip-based security measures. This security concept involves the use of securely-coded data (stored in an optically variable device) which communicates with the encoded hashed information stored in the chip memory via a smartcard reader device.

‘Chip-olate’ and dry-film resists for efficient fabrication, singulation and sealing of microfluidic chips

NASA Astrophysics Data System (ADS)

Temiz, Yuksel; Delamarche, Emmanuel

2014-09-01

This paper describes a technique for high-throughput fabrication and efficient singulation of chips having closed microfluidic structures and takes advantage of dry-film resists (DFRs) for efficient sealing of capillary systems. The technique is illustrated using 4-inch Si/SiO2 wafers. Wafers carrying open microfluidic structures are partially diced to about half of their thickness. Treatments such as surface cleaning are done at wafer-level, then the structures are sealed using low-temperature (45 °C) lamination of a DFR that is pre-patterned using a craft cutter, and ready-to-use chips are finally separated manually like a chocolate bar by applying a small force (≤ 4 N). We further show that some DFRs have low auto-fluorescence at wavelengths typically used for common fluorescent dyes and that mechanical properties of some DFRs allow for the lamination of 200 μm wide microfluidic structures with negligible sagging (~1 μm). The hydrophilicity (advancing contact angle of ~60°) of the DFR supports autonomous capillary-driven flow without the need for additional surface treatment of the microfluidic chips. Flow rates from 1 to 5 µL min-1 are generated using different geometries of channels and capillary pumps. In addition, the ‘chip-olate’ technique is compatible with the patterning of capture antibodies on DFR for use in immunoassays. We believe this technique to be applicable to the fabrication of a wide range of microfluidic and lab-on-a-chip devices and to offer a viable alternative to many labor-intensive processes that are currently based on wafer bonding techniques or on the molding of poly(dimethylsiloxane) (PDMS) layers.

Silicon-nitride/oxynitride wavelength demultiplexer and resonators for quantum photonics

NASA Astrophysics Data System (ADS)

Lim, Soon Thor; Gandhi, Alagappan; Ong, Jun Rong; Ang, Thomas; Png, Ching Eng; Lu, Ding; Ang, Norman Soo Seng; Teo, Ee Jin; Teng, Jinghua

2018-02-01

SiOxNy shows promises for bright emitters of single photons. We successfully fabricated ultra-low-loss SiOxNy waveguide and AWG with low insertion loss <1dB and <3dB total loss (<2dB on-chip loss and <1dB coupling loss) at 1310nm.

Quantum cascade lasers grown on silicon.

PubMed

Nguyen-Van, Hoang; Baranov, Alexei N; Loghmari, Zeineb; Cerutti, Laurent; Rodriguez, Jean-Baptiste; Tournet, Julie; Narcy, Gregoire; Boissier, Guilhem; Patriarche, Gilles; Bahriz, Michael; Tournié, Eric; Teissier, Roland

2018-05-08

Technological platforms offering efficient integration of III-V semiconductor lasers with silicon electronics are eagerly awaited by industry. The availability of optoelectronic circuits combining III-V light sources with Si-based photonic and electronic components in a single chip will enable, in particular, the development of ultra-compact spectroscopic systems for mass scale applications. The first circuits of such type were fabricated using heterogeneous integration of semiconductor lasers by bonding the III-V chips onto silicon substrates. Direct epitaxial growth of interband III-V laser diodes on silicon substrates has also been reported, whereas intersubband emitters grown on Si have not yet been demonstrated. We report the first quantum cascade lasers (QCLs) directly grown on a silicon substrate. These InAs/AlSb QCLs grown on Si exhibit high performances, comparable with those of the devices fabricated on their native InAs substrate. The lasers emit near 11 µm, the longest emission wavelength of any laser integrated on Si. Given the wavelength range reachable with InAs/AlSb QCLs, these results open the way to the development of a wide variety of integrated sensors.

Luminescence properties of Ca{sub 14}Mg{sub 2}(SiO{sub 4}){sub 8}:Eu{sup 2+} from various Eu{sup 2+} sites for white-light-emitting diodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Jia, E-mail: zhangjia@hytc.edu.cn; Jiang, Cheng

2014-12-15

Ca{sub 14}Mg{sub 2}(SiO{sub 4}){sub 8}:Eu{sup 2+} phosphors were synthesized by solid-state reaction method, and their luminescence properties were investigated. In the emission spectra, several overlapping emission bands originating from various Eu{sup 2+} sites were found. Eu{sup 2+} in Ca{sub 14}Mg{sub 2}(SiO{sub 4}){sub 8} exhibits green emission around 506 nm, and the sample doped with 0.1 mol% Eu{sup 2+} shows the strongest brightness under 365 nm excitation with the quantum efficiency of 63.6%. In the excitation spectra, strong and broad excitation bands from 250 to 450 nm were observed, which could well match with the emission wavelength of the light-emitting diodemore » chip. The fabrication test on the InGaN chip indicates the Ca{sub 14}Mg{sub 2}(SiO{sub 4}){sub 8}:Eu{sup 2+} phosphor could be promising candidate for white light-emitting diodes.« less

A CMOS ASIC Design for SiPM Arrays

PubMed Central

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2012-01-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

Stacked Fresnel Zone Plates for High Energy X-rays

NASA Astrophysics Data System (ADS)

Snigireva, Irina; Snigirev, Anatoly; Vaughan, Gavin; Di Michiel, Marco; Kohn, Viktor; Yunkin, Vyacheslav; Grigoriev, Maxim

2007-01-01

A stacking technique was developed in order to increase focusing efficiency of Fresnel zone plates (FZP) at high energies. Two identical Si chips each of which containing 9 FZPs were used for stacking. Alignment of the chips was achieved by on-line observation of the moiré pattern. The formation of moiré patterns was studied theoretically and experimentally at different experimental conditions. To provide the desired stability Si-chips were bonded together with slow solidification speed epoxy glue. A technique of angular alignment in order to compensate a linear displacement in the process of gluing was proposed. Two sets of stacked FZPs were experimentally tested to focus 15 and 50 keV x rays. The gain in the efficiency by factor 2.5 was demonstrated at 15 keV. The focal spot of 1.8 μm vertically and 14 μm horizontally with 35% efficiency was measured at 50 keV. Forecast for the stacking of nanofocusing FZPs was discussed.

Hard X-ray focusing by stacked Fresnel zone plates

NASA Astrophysics Data System (ADS)

Snigireva, Irina; Snigirev, Anatoly; Kohn, Viktor; Yunkin, Vyacheslav; Grigoriev, Maxim; Kuznetsov, Serguei; Vaughan, Gavin; Di Michiel, Marco

2007-09-01

Stacking technique was developed in order to increase focusing efficiency of Fresnel zone plates at high energies. Two identical Si chips each of which containing Fresnel zone plates were used for stacking. Alignment of the chips was achieved by on-line observation of the moiré pattern from the two zone plates. The formation of moiré patterns was studied theoretically and experimentally at different experimental conditions. To provide the desired stability Si-chips with zone plates were bonded together with slow solidification speed epoxy glue. Technique of angular alignment in order to compensate a linear displacement in the process of gluing was proposed. Two sets of stacked FZPs were produced and experimentally tested to focus 15 and 50 keV X-rays. Gain in the efficiency by factor 2.5 was demonstrated at 15 keV. Focal spot of 1.8 μm vertically and 14 μm horizontally with 35% efficiency was measured at 50 keV. Forecast for the stacking of nanofocusing Fresnel zone plates was discussed.

CMOS compatible on-chip telecom-band to mid-infrared supercontinuum generation in dispersion-engineered reverse strip/slot hybrid Si3N4 waveguide

NASA Astrophysics Data System (ADS)

Hui, Zhanqiang; Zhang, Lingxuan; Zhang, Wenfu

2018-01-01

A silicon nitride (Si3N4)-based reverse strip/slot hybrid waveguide with single vertical silica slot is proposed to acquire extremely low and flat chromatic dispersion profile. This is achieved by design and optimization of the geometrical structural parameters of the reverse hybrid waveguide. The flat dispersion varying between ±10 ps/(nm.km) is obtained over 610 nm bandwidth. Both the effective area and nonlinear coefficient of the waveguide across the entire spectral range of interest are investigated. This led to design of an on-chip supercontinuum (SC) source with -30 dB bandwidth of 2996 nm covering from 1.209 to 4.205 μm. Furthermore, we discuss the output signal spectral and temporal characteristic as a function of the pump power. Our waveguide design offers a CMOS compatible, low-cost/high yield (no photolithography or lift-off processes are necessary) on-chip SC source for near- and mid-infrared nonlinear applications.

Radiation Hardening of Digital Color CMOS Camera-on-a-Chip Building Blocks for Multi-MGy Total Ionizing Dose Environments

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Rolando, Sébastien; Corbière, Franck; Rizzolo, Serena; Chabane, Aziouz; Girard, Sylvain; Baer, Jérémy; Estribeau, Magali; Magnan, Pierre; Paillet, Philippe; Van Uffelen, Marco; Mont Casellas, Laura; Scott, Robin; Gaillardin, Marc; Marcandella, Claude; Marcelot, Olivier; Allanche, Timothé

2017-01-01

The Total Ionizing Dose (TID) hardness of digital color Camera-on-a-Chip (CoC) building blocks is explored in the Multi-MGy range using 60Co gamma-ray irradiations. The performances of the following CoC subcomponents are studied: radiation hardened (RH) pixel and photodiode designs, RH readout chain, Color Filter Arrays (CFA) and column RH Analog-to-Digital Converters (ADC). Several radiation hardness improvements are reported (on the readout chain and on dark current). CFAs and ADCs degradations appear to be very weak at the maximum TID of 6 MGy(SiO2), 600 Mrad. In the end, this study demonstrates the feasibility of a MGy rad-hard CMOS color digital camera-on-a-chip, illustrated by a color image captured after 6 MGy(SiO2) with no obvious degradation. An original dark current reduction mechanism in irradiated CMOS Image Sensors is also reported and discussed.

Luminescent properties of Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} and its potential application in white light emitting diodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zhijun, E-mail: wangzhijunmail@yahoo.com.cn; Li, Panlai; Li, Ting

2013-06-01

Graphical abstract: Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} phosphor can be effectively excited by an ultraviolet and near-ultraviolet light, and produce a bright blue emission centered at 436 nm. The CIE chromaticity coordinations (x, y) of Na{sub 2}CaSiO{sub 4}:Eu{sup 2+}(NSCE)/Li{sub 2}SrSiO{sub 4}:Eu{sup 2+}(LSSE) vary with the molar ratio of the two constituents. When NSCE/LSSE is 1:3, the CIE chromaticity coordination is (0.332, 0.346), which is close to that of the natural sunlight (0.33, 0.33). The results indicate that Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} may be a promising blue phosphor for UV chip-based multi-phosphor converted white light emitting diodes. Highlights: ► Na{sub 2}CaSiO{sub 4}:Eu{supmore » 2+} shows the blue emission with a peak at 436 nm and broad excitation band in the UV/n-UV range. ► White light with CIE coordinates (0.332, 0.346) is generated by mixing the blue phosphor with the Li{sub 2}SrSiO{sub 4}:Eu{sup 2+} yellow phosphor. ► Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} would be a promising blue phosphor candidate for UV chip-based multi-phosphor converted white LEDs. - Abstract: A novel blue phosphor Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} is synthesized by a high temperature solid-state reaction, and its luminescent properties are systematically studied. Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} can be effectively excited by the 354 nm radiation, and create blue emission (436 nm). The emission intensity of Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} is influenced by the Eu{sup 2+} doping content, and the optimal doping content is 1.5%, and the concentration quenching mechanism of Eu{sup 2+} in Na{sub 2}CaSiO{sub 4} can be attributed to the multipolar interaction. The white light with CIE coordinates (0.332, 0.346) is generated by mixing the blue phosphor Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} with the yellow phosphor Li{sub 2}SrSiO{sub 4}:Eu{sup 2+}. The results indicate that Na{sub 2}CaSiO{sub 4}:Eu{sup 2+} may be a potential blue emitting phosphor for UV chip-based multi-phosphor converted white light emitting diodes.« less

Wide memory window in graphene oxide charge storage nodes

NASA Astrophysics Data System (ADS)

Wang, Shuai; Pu, Jing; Chan, Daniel S. H.; Cho, Byung Jin; Loh, Kian Ping

2010-04-01

Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of -5-14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.

Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.

PubMed

Kim, Seung-Yoon; Park, Jong Kyung; Hwang, Wan Sik; Lee, Seung-Jun; Lee, Ki-Hong; Pyi, Seung Ho; Cho, Byung Jin

2016-05-01

We investigated the dependence of grain size on the performance of a polycrystalline silicon (poly-Si) channel TFT for application to 3D NAND Flash memory devices. It has been found that the device performance and memory characteristics are strongly affected by the grain size of the poly-Si channel. Higher on-state current, faster program speed, and poor endurance/reliability properties are observed when the poly-Si grain size is large. These are mainly attributed to the different local electric field induced by an oxide valley at the interface between the poly-Si channel and the gate oxide. In addition, the trap density at the gate oxide interface was successfully measured using a charge pumping method by the separation between the gate oxide interface traps and traps at the grain boundaries in the poly-Si channel. The poly-Si channel with larger grain size has lower interface trap density.

Controllable Switching Filaments Prepared via Tunable and Well-Defined Single Truncated Conical Nanopore Structures for Fast and Scalable SiOx Memory.

PubMed

Kwon, Soonbang; Jang, Seonghoon; Choi, Jae-Wan; Choi, Sanghyeon; Jang, Sukjae; Kim, Tae-Wook; Wang, Gunuk

2017-12-13

The controllability of switching conductive filaments is one of the central issues in the development of reliable metal-oxide resistive memory because the random dynamic nature and formation of the filaments pose an obstacle to desirable switching performance. Here, we introduce a simple and novel approach to control and form a single silicon nanocrystal (Si-NC) filament for use in SiO x memory devices. The filament is formed with a confined vertical nanoscale gap by using a well-defined single vertical truncated conical nanopore (StcNP) structure. The physical dimensions of the Si-NC filaments such as number, size, and length, which have a significant influence on the switching properties, can be simply engineered by the breakdown of an Au wire through different StcNP structures. In particular, we demonstrate that the designed SiO x memory junction with a StcNP of pore depth of ∼75 nm and a bottom diameter of ∼10 nm exhibited a switching speed of up to 6 ns for both set and reset process, significantly faster than reported SiO x memory devices. The device also exhibited a high ON-OFF ratio, multistate storage ability, acceptable endurance, and retention stability. The influence of the physical dimensions of the StcNP on the switching features is discussed based on the simulated temperature profiles of the Au wire and the nanogap size generated inside the StcNP structure during electromigration.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, Anthony F.; Malba, Vincent

1999-01-01

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

A Very Low Cost BCH Decoder for High Immunity of On-Chip Memories

NASA Astrophysics Data System (ADS)

Seo, Haejun; Han, Sehwan; Heo, Yoonseok; Cho, Taewon

BCH(Bose-Chaudhuri-Hoquenbhem) code, a type of block codes-cyclic codes, has very strong error-correcting ability which is vital for performing the error protection on the memory system. BCH code has many kinds of dual algorithms, PGZ(Pererson-Gorenstein-Zierler) algorithm out of them is advantageous in view of correcting the errors through the simple calculation in t value. However, this is problematic when this becomes 0 (divided by zero) in case ν ≠ t. In this paper, the circuit would be simplified by suggesting the multi-mode hardware architecture in preparation that v were 0~3. First, production cost would be less thanks to the smaller number of gates. Second, lessening power consumption could lengthen the recharging period. The very low cost and simple datapath make our design a good choice in small-footprint SoC(System on Chip) as ECC(Error Correction Code/Circuit) in memory system.

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Novel electrochemical nickel metallization in silicon impedance engineering for mixed-signal system-on-chip crosstalk isolation

NASA Astrophysics Data System (ADS)

Zhang, Xi

One of the major challenges for single chip radio frequency integrated circuits (RFIC's) built on Si is the RE crosstalk through the Si substrate. Noise from switching transient in digital circuits can be transmitted through Si substrate and degrades the performance of analog circuit elements. A highly conductive moat or Faraday cage type structure of through-the-wafer thickness in the Si substrate was demonstrated to be effective in shielding electromagnetic interference thereby reducing RE cross-talk in high performance mixed signal integrated circuits. Such a structure incorporated into the p- Si substrate was realized by electroless Ni metallization over selected regions with ultra-high-aspect-ratio macropores that was etched electrochemically in p- Si substrates. The metallization process was conducted by immersing the macroporous Si sample in an alkaline aqueous solution containing Ni2+ without a reducing agent. It was found that working at slightly elevated temperature, Ni 2+ was rapidly reduced and deposited in the macropores. During the wet chemical process, conformal metallization on the pore wall was achieved. The entire porous Si skeleton was gradually replaced by Ni along the extended duration of immersion. In a p-/p+ epi Si substrate used for high performance digital CMOS, the suppression of crosstalk by the arrayed metallic Ni via structure fabricated from the front p side was significant that the crosstalk went down to the noise floor of the conventional measurement instruments. The process and mechanism of forming such a Ni structure over the original Si were studied. Theoretical computation relevant to the process was carried out to show a good consistency with the experiments.

Optical interconnection networks for high-performance computing systems

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr; Bergman, Keren

2012-04-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

NASA Astrophysics Data System (ADS)

Choi, Shinhyun; Tan, Scott H.; Li, Zefan; Kim, Yunjo; Choi, Chanyeol; Chen, Pai-Yu; Yeon, Hanwool; Yu, Shimeng; Kim, Jeehwan

2018-01-01

Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on—formation of filaments in an amorphous medium—is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

A VLSI VAX chip set

NASA Astrophysics Data System (ADS)

Johnson, W. N.; Herrick, W. V.; Grundmann, W. J.

1984-10-01

For the first time, VLSI technology is used to compress the full functinality and comparable performance of the VAX 11/780 super-minicomputer into a 1.2 M transistor microprocessor chip set. There was no subsetting of the 304 instruction set and the 17 data types, nor reduction in hardware support for the 4 Gbyte virtual memory management architecture. The chipset supports an integral 8 kbyte memory cache, a 13.3 Mbyte/s system bus, and sophisticated multiprocessing. High performance is achieved through microcode optimizations afforded by the large control store, tightly coupled address and data caches, the use of internal and external 32 bit datapaths, the extensive aplication of both microlevel and macrolevel pipelining, and the use of specialized hardware assists.

Design and DSP implementation of star image acquisition and star point fast acquiring and tracking

NASA Astrophysics Data System (ADS)

Zhou, Guohui; Wang, Xiaodong; Hao, Zhihang

2006-02-01

Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper, the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing, a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design, the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory, DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme, DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us, the data in five expanded windows including stars are moved into the internal memory of DSP, and in 1.6ms, five star coordinates are achieved in the star tracking stage.

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Section 1: Interfacial reactions and grain growth in ferroelectric SrBi{sub 2}Ta{sub 2}O (SBT) thin films on Si substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dickerson, B.D.; Zhang, X.; Desu, S.B.

1997-04-01

Much of the cost of traditional infrared cameras based on narrow-bandgap photoelectric semiconductors comes from the cryogenic cooling systems required to achieve high detectivity. Detectivity is inversely proportional to noise. Generation-recombination noise in photoelectric detectors increases roughly exponentially with temperature, but thermal noise in photoelectric detectors increases only linearly with temperature. Therefore `thermal detectors perform far better at room temperature than 8-14 {mu}m photon detectors.` Although potentially more affordable, uncooled pyroelectric cameras are less sensitive than cryogenic photoelectric cameras. One way to improve the sensitivity to cost ratio is to deposit ferroelectric pixels with good electrical properties directly on mass-produced,more » image-processing chips. `Good` properties include a strong temperature dependence of the remanent polarization, P{sub r}, or the relative dielectric constant, {epsilon}{sub r}, for sensitive operation in pyroelectric or dielectric mode, respectively, below or above the Curie temperature, which is 320 C for SBT. When incident infrared radiation is chopped, small oscillations in pixel temperature produce pyroelectric or dielectric alternating currents. The sensitivity of ferroelectric thermal detectors depends strongly on pixel microstructure, since P{sub r} and {epsilon}{sub r} increase with grain size during annealing. To manufacture SBT pixels on Si chips, acceptable SBT grain growth must be achieved at the lowest possible oxygen annealing temperature, to avoid damaging the Si chip below. Therefore current technical progress describes how grain size, reaction layer thickness, and electrical properties develop during the annealing of SBT pixels deposited on Si.« less

Effects of Interfacial Fluorination on Performance Enhancement of High-k-Based Charge Trap Flash Memory

NASA Astrophysics Data System (ADS)

Wang, Chenjie; Huo, Zongliang; Liu, Ziyu; Liu, Yu; Cui, Yanxiang; Wang, Yumei; Li, Fanghua; Liu, Ming

2013-07-01

The effects of interfacial fluorination on the metal/Al2O3/HfO2/SiO2/Si (MAHOS) memory structure have been investigated. By comparing MAHOS memories with and without interfacial fluorination, it was identified that the deterioration of the performance and reliability of MAHOS memories is mainly due to the formation of an interfacial layer that generates excess oxygen vacancies at the interface. Interfacial fluorination suppresses the growth of the interfacial layer, which is confirmed by X-ray photoelectron spectroscopy depth profile analysis, increases enhanced program/erase efficiency, and improves data retention characteristics. Moreover, it was observed that fluorination at the SiO-HfO interface achieves a more effective performance enhancement than that at the HfO-AlO interface.

Detecting a single molecule using a micropore-nanopore hybrid chip

PubMed Central

2013-01-01

Nanopore-based DNA sequencing and biomolecule sensing have attracted more and more attention. In this work, novel sensing devices were built on the basis of the chips containing nanopore arrays in polycarbonate (PC) membranes and micropores in Si3N4 films. Using the integrated chips, the transmembrane ionic current induced by biomolecule's translocation was recorded and analyzed, which suggested that the detected current did not change linearly as commonly expected with increasing biomolecule concentration. On the other hand, detailed translocation information (such as translocation gesture) was also extracted from the discrete current blockages in basic current curves. These results indicated that the nanofluidic device based on the chips integrated by micropores and nanopores possessed comparative potentials in biomolecule sensing. PMID:24261484

Detecting a single molecule using a micropore-nanopore hybrid chip.

PubMed

Liu, Lei; Zhu, Lizhong; Ni, Zhonghua; Chen, Yunfei

2013-11-21

Nanopore-based DNA sequencing and biomolecule sensing have attracted more and more attention. In this work, novel sensing devices were built on the basis of the chips containing nanopore arrays in polycarbonate (PC) membranes and micropores in Si3N4 films. Using the integrated chips, the transmembrane ionic current induced by biomolecule's translocation was recorded and analyzed, which suggested that the detected current did not change linearly as commonly expected with increasing biomolecule concentration. On the other hand, detailed translocation information (such as translocation gesture) was also extracted from the discrete current blockages in basic current curves. These results indicated that the nanofluidic device based on the chips integrated by micropores and nanopores possessed comparative potentials in biomolecule sensing.

SiGe:C Heterojunction Bipolar Transistors: From Materials Research to Chip Fabrication

NASA Astrophysics Data System (ADS)

Ruecker, H.; Heinemann, B.; Knoll, D.; Ehwald, K.-E.

Incorporation of substitutional carbon ( ~10^20 cm^-3) into the SiGe region of a heterojunction bipolar transistor (HBT) strongly reduces boron diffusion during device processing. We describe the physical mechanism behind the suppression of B diffusion in C-rich Si and SiGe, and explain how the increased thermal stability of doping profiles in SiGe:C HBTs can be used to improve device performance. Manufacturability of SiGe:C HBTs with transit frequencies of 100 GHz and maximum oscillation frequencies of 130 GHz is demonstrated in a BiCMOS technology capable of fabricating integrated circuits for radio frequencies with high yield.

Micropumps, microvalves, and micromixers within PCR microfluidic chips: Advances and trends.

PubMed

Zhang, Chunsun; Xing, Da; Li, Yuyuan

2007-01-01

This review surveys the advances of microvalves, micropumps, and micromixers within PCR microfluidic chips over the past ten years. First, the types of microvalves in PCR chips are discussed, including active and passive microvalves. The active microvalves are subdivided into mechanical (thermopneumatic and shape memory alloy), non-mechanical (hydrogel, sol-gel, paraffin, and ice), and external (modular built-in, pneumatic, and non-pneumatic) microvalves. The passive microvalves also include mechanical (in-line polymerized gel and passive plug) and non-mechanical (hydrophobic) microvalves. The review then discusses mechanical (piezoelectric, pneumatic, and thermopneumatic) and non-mechanical (electrokinetic, magnetohydrodynamic, electrochemical, acoustic-wave, surface tension and capillary, and ferrofluidic magnetic) micropumps in PCR chips. Next, different micromixers within PCR chips are presented, including passive (Y/T-type flow, recirculation flow, and drop) and active (electrokinetically-driven, acoustically-driven, magnetohydrodynamical-driven, microvalves/pumps) micromixers. Finally, general discussions on microvalves, micropumps, and micromixers for PCR chips are given. The microvalve/micropump/micromixers allow high levels of PCR chip integration and analytical throughput.

Membrane-on-a-chip: microstructured silicon/silicon-dioxide chips for high-throughput screening of membrane transport and viral membrane fusion.

PubMed

Kusters, Ilja; van Oijen, Antoine M; Driessen, Arnold J M

2014-04-22

Screening of transport processes across biological membranes is hindered by the challenge to establish fragile supported lipid bilayers and the difficulty to determine at which side of the membrane reactants reside. Here, we present a method for the generation of suspended lipid bilayers with physiological relevant lipid compositions on microstructured Si/SiO2 chips that allow for high-throughput screening of both membrane transport and viral membrane fusion. Simultaneous observation of hundreds of single-membrane channels yields statistical information revealing population heterogeneities of the pore assembly and conductance of the bacterial toxin α-hemolysin (αHL). The influence of lipid composition and ionic strength on αHL pore formation was investigated at the single-channel level, resolving features of the pore-assembly pathway. Pore formation is inhibited by a specific antibody, demonstrating the applicability of the platform for drug screening of bacterial toxins and cell-penetrating agents. Furthermore, fusion of H3N2 influenza viruses with suspended lipid bilayers can be observed directly using a specialized chip architecture. The presented micropore arrays are compatible with fluorescence readout from below using an air objective, thus allowing high-throughput screening of membrane transport in multiwell formats in analogy to plate readers.

A free-running, time-based readout method for particle detectors

NASA Astrophysics Data System (ADS)

Goerres, A.; Bugalho, R.; Di Francesco, A.; Gastón, C.; Gonçalves, F.; Mazza, G.; Mignone, M.; Di Pietro, V.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; da Silva, J. C.; Silva, R.; Stockmanns, T.; Varela, J.; Veckalns, V.; Wheadon, R.

2014-03-01

For the EndoTOFPET-US experiment, the TOFPET ASIC has been developed as a front-end chip to read out data from silicon photomultipliers (SiPM) [1]. It introduces a time of flight information into the measurement of a PET scanner and hence reduces radiation exposure of the patient [2]. The chip is designed to work with a high event rate up to 100 kHz and a time resolution of 50 ps LSB. Using two threshold levels, it can measure the leading edge of the event pulse precisely while successfully suppressing dark counts from the SiPM. This also enables a time over threshold determination, leading to a charge measurement of the signal's pulse. The same, time-based concept is chosen for the PASTA chip used in the PANDA experiment. This high-energy particle detector contains sub-systems for specific measurement goals. The innermost of these is the Micro Vertex Detector, a silicon-based tracking system. The PASTA chip's approach is much like the TOFPET ASIC with some differences. The most significant ones are a changed amplifying part for different input signals as well as protection for radiation effects of the high-radiation environment. Apart from that, the simple and general concept combined with a small area and low power consumption support the choice for using this approach.

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

NASA Technical Reports Server (NTRS)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Tunable MOEMS Fabry-Perot interferometer for miniaturized spectral sensing in near-infrared

NASA Astrophysics Data System (ADS)

Rissanen, A.; Mannila, R.; Tuohiniemi, M.; Akujärvi, A.; Antila, J.

2014-03-01

This paper presents a novel MOEMS Fabry-Perot interferometer (FPI) process platform for the range of 800 - 1050 nm. Simulation results including design and optimization of device properties in terms of transmission peak width, tuning range and electrical properties are discussed. Process flow for the device fabrication is presented, with overall process integration and backend dicing steps resulting in successful fabrication yield. The mirrors of the FPI consist of LPCVD (low-pressure chemical vapor) deposited polySi-SiN λ/4-thin film Bragg reflectors, with the air gap formed by sacrificial SiO2 etching in HF vapor. Silicon substrate below the optical aperture is removed by inductively coupled plasma (ICP) etching to ensure transmission in the visible - near infra-red (NIR), which is below silicon transmission range. The characterized optical properties of the chips are compared to the simulated values. Achieved optical aperture diameter size enables utilization of the chips in both imaging as well as single-point spectral sensors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Fault tolerance issues in nanoelectronics

NASA Astrophysics Data System (ADS)

Spagocci, S. M.

The astonishing success story of microelectronics cannot go on indefinitely. In fact, once devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected to impair their behaviour. Fault tolerant techniques will then be required. The aim of this thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient error rates for a selection of nanoelectronic gates, based upon quantum cellular automata and single electron devices, in which the electrostatic interaction between electrons is used to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional techniques are found to be unsuitable. A new technique, in which the voting approach of triple modular redundancy (TMR) is extended by cascading TMR units composed of nanogate clusters, is proposed and generalised to other voting approaches. For memory chips, an error correcting code approach is found to be suitable. Various codes are considered and a lookup table approach is proposed for encoding and decoding. We are then able to give estimations for the redundancy level to be provided on nanochips, so as to make their mean time between failures acceptable. It is found that, for logic chips, space redundancies up to a few tens are required, if mean times between failures have to be of the order of a few years. Space redundancy can also be traded for time redundancy. As for memory chips, mean times between failures of the order of a few years are found to imply both space and time redundancies of the order of ten.

Resistance Switching Memory Characteristics of Si/CaF2/CdF2 Quantum-Well Structures Grown on Metal (CoSi2) Layer

NASA Astrophysics Data System (ADS)

Denda, Junya; Uryu, Kazuya; Watanabe, Masahiro

2013-04-01

A novel scheme of resistance switching random access memory (ReRAM) devices fabricated using Si/CaF2/CdF2/CaF2/Si quantum-well structures grown on metal CoSi2 layer formed on a Si substrate has been proposed, and embryonic write/erase memory operation has been demonstrated at room temperature. It has been found that the oxide-mediated epitaxy (OME) technique for forming the CoSi2 layer on Si dramatically improves the stability and reproducibility of the current-voltage (I-V) curve. This technology involves 10-nm-thick Co layer deposition on a protective oxide prepared by boiling in a peroxide-based solution followed by annealing at 550 °C for 30 min for silicidation in ultrahigh vacuum. A switching voltage of lower than 1 V, a peak current density of 32 kA/cm2, and an ON/OFF ratio of 10 have been observed for the sample with the thickness sequence of 0.9/0.9/2.5/0.9/5.0 nm for the respective layers in the Si/CaF2/CdF2/CaF2/Si structure. Results of surface morphology analysis suggest that the grain size of crystal islands with flat surfaces strongly affects the quality of device characteristics.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

NASA Electronic Parts and Packaging (NEPP) Program - Update

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Sampson, Michael J.

2010-01-01

This slide presentation reviews the goals and mission of the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs. The program has been supporting NASA for over 20 years. The focus is on the reliability aspects of electronic devices. In this work the program also supports the electronics industry. There are several areas that the program is involved in: Memories, systems on a chip (SOCs), data conversion devices, power MOSFETS, power converters, scaled CMOS, capacitors, linear devices, fiber optics, and other electronics such as sensors, cryogenic and SiGe that are used in space systems. Each of these area are reviewed with the work that is being done in reliability and effects of radiation on these technologies.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Test results for SEU and SEL immune memory circuits

NASA Technical Reports Server (NTRS)

Wiseman, D.; Canaris, J.; Whitaker, S.; Gambles, J.; Arave, K.; Arave, L.

1993-01-01

Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

Novel duplex vapor: Electrochemical method for silicon solar cells. [chemical reactor for a silicon sodium reaction system

NASA Technical Reports Server (NTRS)

Nanis, L.; Sanjurjo, A.; Sancier, K.

1979-01-01

The scaled up chemical reactor for a SiF4-Na reaction system is examined for increased reaction rate and production rate. The reaction system which now produces 5 kg batches of mixed Si and NaF is evaluated. The reactor design is described along with an analysis of the increased capacity of the Na chip feeder. The reactor procedure is discussed and Si coalescence in the reaction products is diagnosed.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, A.F.; Malba, V.

1999-08-03

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

Non-Volatile High Speed & Low Power Charge Trapping Devices

NASA Astrophysics Data System (ADS)

Kim, Moon Kyung; Tiwari, Sandip

2007-06-01

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO2/SiO2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO2/SiO2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ˜0.44 eV for the write process and ˜0.47 eV for the erase process in SiO2/SiO2 structural device which is somewhat more efficient than those of SONOS structure memory.

Comparative experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet flip-chip and top-emitting LEDs

NASA Astrophysics Data System (ADS)

Liu, Mengling; Zhou, Shengjun; Liu, Xingtong; Gao, Yilin; Ding, Xinghuo

2018-03-01

Experimental and simulation studies of high-power AlGaN-based 353 nm ultraviolet (UV) flip-chip (FC) and top-emitting (TE) light-emitting diodes (LEDs) are performed here. To improve the optical and electrical properties of ultraviolet LEDs, we fabricate high-power FC-UV LEDs with Ta2O5/SiO2 distributed Bragg reflectors (DBRs) and a strip-shaped SiO2 current blocking layer (CBL). The reflectance of fourteen pairs of Ta2O5/SiO2 DBRs is 96.4% at 353 nm. The strip-shaped SiO2 CBL underneath the strip-shaped p-electrode can prevent the current concentrating in regions immediately adjacent to the p-electrode where the overlying opaque p-electrode metal layer absorbs the emitted UV light. Moreover, two-level metallization electrodes are used to improve current spreading. Our numerical results show that FC-UV LED has a more favorable current spreading uniformity than TE-UV LED. The light output power of 353 nm FC-UV LED was 23.22 mW at 350 mA, which is 24.7% higher than that of TE-UV LED.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

NASA Technical Reports Server (NTRS)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

High Temperature Performance of a SiC MESFET Based Oscillator

NASA Technical Reports Server (NTRS)

Schwartz, Zachary D.; Ponchak, George E.

2005-01-01

A hybrid, UHF-Band differential oscillator based on 10 w SiC RF Power Metal Semiconductor Field Effect Transistor (MESFET) has been designed, fabricated and characterized through 475 C. Circuit is fabricated on an alumina substrate with thin film spiral inductors, chip capacitors, chip resistors, and wire bonds for all crossovers and interconnectors. The oscillator delivers 15.7 dBm at 515 MHz into a 50 Ohm load at 125 C with a DC to RF conversion efficiency of 2,8%. After tuning the load impedance, the oscillator delivers 18.8 dBm at 610 MHz at 200 C with a DC to RF conversion efficiency of 5.8%. Finally, by tuning the load and bias conditions, the oscillator delivers 4.9 dBm at 453 MHz at 475 C.

The Effect of SiC Polytypes on the Heat Distribution Efficiency of a Phase Change Memory.

NASA Astrophysics Data System (ADS)

Aziz, M. S.; Mohammed, Z.; Alip, R. I.

2018-03-01

The amorphous to crystalline transition of germanium-antimony-tellurium (GST) using three types of silicon carbide’s structure as a heating element was investigated. Simulation was done using COMSOL Multiphysic 5.0 software with separate heater structure. Silicon carbide (SiC) has three types of structure; 3C-SiC, 4H-SiC and 6H-SiC. These structures have a different thermal conductivity. The temperature of GST and phase transition of GST can be obtained from the simulation. The temperature of GST when using 3C-SiC, 4H-SiC and 6H-SiC are 467K, 466K and 460K, respectively. The phase transition of GST from amorphous to crystalline state for three type of SiC’s structure can be determined in this simulation. Based on the result, the thermal conductivity of SiC can affecting the temperature of GST and changed of phase change memory (PCM).

Improved charge trapping properties by embedded graphene oxide quantum-dots for flash memory application

NASA Astrophysics Data System (ADS)

Jia, Xinlei; Yan, Xiaobing; Wang, Hong; Yang, Tao; Zhou, Zhenyu; Zhao, Jianhui

2018-06-01

In this work, we have investigated two kinds of charge trapping memory devices with Pd/Al2O3/ZnO/SiO2/p-Si and Pd/Al2O3/ZnO/graphene oxide quantum-dots (GOQDs)/ZnO/SiO2/p-Si structure. Compared with the single ZnO sample, the memory window of the ZnO-GOQDs-ZnO sample reaches a larger value (more than doubled) of 2.7 V under the sweeping gate voltage ± 7 V, indicating a better charge storage capability and the significant charge trapping effects by embedding the GOQDs trapping layer. The ZnO-GOQDs-ZnO devices have better date retention properties with the high and low capacitances loss of ˜ 1.1 and ˜ 6.9%, respectively, as well as planar density of the trapped charges of 1.48 × 1012 cm- 2. It is proposed that the GOQDs play an important role in the outstanding memory characteristics due to the deep quantum potential wells and the discrete distribution of the GOQDs. The long date retention time might have resulted from the high potential barrier which suppressed both the back tunneling and the leakage current. Intercalating GOQDs in the memory device is a promising method to realize large memory window, low-power consumption and excellent retention properties.

Photoresponse and photo-induced memory effect in the organic field-effect transistor based on AlOX nanoparticles at the interface of semiconductor/dielectric

NASA Astrophysics Data System (ADS)

Cheng, Yunfei; Wang, Wu

2017-10-01

In this work, the photoresponse and photo-induced memory effect were demonstrated in an organic field-effect transistor (OFET) with semiconductor pentacene and SiO2 as the active and gate dielectric layers, respectively. By inserting AlOX nanoparticles (NPs) at the interface of pentacene/SiO2, obvious enhancing photoresponse was obtained in the OFET with the maximum responsivity and photosensitivity of about 15 A/W and 100, respectively. Moreover, the stable photoinduced memory effect was achieved in the OFET, attributing to the photogenerated electrons captured by the interface traps of the AlOX NPs/SiO2.

Camera-on-a-Chip

NASA Technical Reports Server (NTRS)

1999-01-01

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

Lift-off process with bi-layer photoresist patterns for conformal-coated superhydrophilic pulsed plasma chemical vapor deposition-SiOx on SiCx for lab-on-a-chip applications

NASA Astrophysics Data System (ADS)

Konishi, Satoshi; Nakagami, Chise; Kobayashi, Taizo; Tonomura, Wataru; Kaizuma, Yoshihiro

2015-04-01

In this work, a lift-off process with bi-layer photoresist patterns was applied to the formation of hydrophobic/hydrophilic micropatterns on practical polymer substrates used in healthcare diagnostic commercial products. The bi-layer photoresist patterns with undercut structures made it possible to peel the conformal-coated silicon oxide (SiOx) films from substrates. SiOx and silicon carbide (SiCx) layers were deposited by pulsed plasma chemical vapor deposition (PPCVD) method which can form roughened surfaces to enhance hydrophilicity of SiOx and hydrophobicity of SiCx. Microfluidic applications using hydrophobic/hydrophilic patterns were also demonstrated on low-cost substrates such as poly(ethylene terephthalate) (PET) and paper films.

Instrument Records And Plays Back Acceleration Signals

NASA Technical Reports Server (NTRS)

Bozeman, Richard J.

1994-01-01

Small, battery-powered, hand-held instrument feeds power to accelerometer and records time-varying component of output for 15 seconds in analog form. No power needed to maintain content of memory; memory chip removed after recording and stored indefinitely. Recorded signal plays back at any time up to several years later. Principal advantages: compactness, portability, and low cost.

Integration of image capture and processing: beyond single-chip digital camera

NASA Astrophysics Data System (ADS)

Lim, SukHwan; El Gamal, Abbas

2001-05-01

An important trend in the design of digital cameras is the integration of capture and processing onto a single CMOS chip. Although integrating the components of a digital camera system onto a single chip significantly reduces system size and power, it does not fully exploit the potential advantages of integration. We argue that a key advantage of integration is the ability to exploit the high speed imaging capability of CMOS image senor to enable new applications such as multiple capture for enhancing dynamic range and to improve the performance of existing applications such as optical flow estimation. Conventional digital cameras operate at low frame rates and it would be too costly, if not infeasible, to operate their chips at high frame rates. Integration solves this problem. The idea is to capture images at much higher frame rates than he standard frame rate, process the high frame rate data on chip, and output the video sequence and the application specific data at standard frame rate. This idea is applied to optical flow estimation, where significant performance improvements are demonstrate over methods using standard frame rate sequences. We then investigate the constraints on memory size and processing power that can be integrated with a CMOS image sensor in a 0.18 micrometers process and below. We show that enough memory and processing power can be integrated to be able to not only perform the functions of a conventional camera system but also to perform applications such as real time optical flow estimation.

A 16X16 Discrete Cosine Transform Chip

NASA Astrophysics Data System (ADS)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

Solar particle induced upsets in the TDRS-1 attitude control system RAM during the October 1989 solar particle events

NASA Astrophysics Data System (ADS)

Croley, D. R.; Garrett, H. B.; Murphy, G. B.; Garrard, T. L.

1995-10-01

The three large solar particle events, beginning on October 19, 1989 and lasting approximately six days, were characterized by high fluences of solar protons and heavy ions at 1 AU. During these events, an abnormally large number of upsets (243) were observed in the random access memory of the attitude control system (ACS) control processing electronics (CPE) on-board the geosynchronous TDRS-1 (Telemetry and Data Relay Satellite). The RAR I unit affected was composed of eight Fairchild 93L422 memory chips. The Galileo spacecraft, launched on October 18, 1989 (one day prior to the solar particle events) observed the fluxes of heavy ions experienced by TDRS-1. Two solid-state detector telescopes on-board Galileo designed to measure heavy ion species and energy, were turned on during time periods within each of the three separate events. The heavy ion data have been modeled and the time history of the events reconstructed to estimate heavy ion fluences. These fluences were converted to effective LET spectra after transport through the estimated shielding distribution around the TDRS-1 ACS system. The number of single event upsets (SEU) expected was calculated by integrating the measured cross section for the Fairchild 93L422 memory chip with average effective LET spectrum. The expected number of heavy ion induced SEUs calculated was 176. GOES-7 proton data, observed during the solar particle events, were used to estimate the number of proton-induced SEUs by integrating the proton fluence spectrum incident on the memory chips, with the two-parameter Bendel cross section for proton SEUs.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Industry Study, Electronics Industry, Spring 2009

DTIC Science & Technology

2009-01-01

Toshiba, Samsung , and NEC.7 The microprocessor is a central processing unit containing hundreds of millions of transistors and logic to perform...business with an 11.7% market share followed closely by Samsung with a 10.3% market share.40 Intel is the leader in the production of microprocessors...while Samsung is the leading memory chip producer. Other US chip manufacturers include Texas Instruments (TI), Advanced Micro Devices (AMD), Micron

Study of self-compliance behaviors and internal filament characteristics in intrinsic SiO{sub x}-based resistive switching memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, Yao-Feng, E-mail: yfchang@utexas.edu; Zhou, Fei; Chen, Ying-Chen

2016-01-18

Self-compliance characteristics and reliability optimization are investigated in intrinsic unipolar silicon oxide (SiO{sub x})-based resistive switching (RS) memory using TiW/SiO{sub x}/TiW device structures. The program window (difference between SET voltage and RESET voltage) is dependent on external series resistance, demonstrating that the SET process is due to a voltage-triggered mechanism. The program window has been optimized for program/erase disturbance immunity and reliability for circuit-level applications. The SET and RESET transitions have also been characterized using a dynamic conductivity method, which distinguishes the self-compliance behavior due to an internal series resistance effect (filament) in SiO{sub x}-based RS memory. By using amore » conceptual “filament/resistive gap (GAP)” model of the conductive filament and a proton exchange model with appropriate assumptions, the internal filament resistance and GAP resistance can be estimated for high- and low-resistance states (HRS and LRS), and are found to be independent of external series resistance. Our experimental results not only provide insights into potential reliability issues but also help to clarify the switching mechanisms and device operating characteristics of SiO{sub x}-based RS memory.« less

Way for LEEPL technology to succeed in memory device application

NASA Astrophysics Data System (ADS)

Kim, In-Sung; Woo, Sang-Gyun; Cho, Han-Ku; Han, Woo-Sung; Moon, Joo-Tae

2004-05-01

Lithography for 65nm-node device is drawing a lot of attentions these days especially because lithography solution for this node is not clear and even tool makers tend to wait for the consensus in lithography roadmap to avoid the risk of erroneous amount of investment. Recently proposed concept of low energy electron-beam proximity-projection lithography (LEEPL)1,2 technology has already released its first production machine in 2003, which is being expected to cover the design rule down to 65nm-node and even smaller3. Although production of semiconductor device has been pursuing optical lithography, without any optical technology that is proved as a convincing solution for 65nm node and below, we need to take account of all the candidates. So we made an investigation on LEEPL technology and evaluated beta and first production tool to see the feasibility of printing sub-70nm resolution and of optic-first mix-and-match overlay from a chip maker"s point of view. Two different kinds of stencil masks were fabricated for the evaluation, which are fabricated in SiC and Si membrane. The former mask is for sparse contact holes(C/H) and the latter for dense C/Hs. Beta-tool showed a good resolving power of sub-70nm sparse C/Hs of SRAM with negligibly small proximity effect. It implies that LEEPL does not require much effort for proximity correction comparing to that required in optical lithography, which is one of the biggest issues in low-k1. LEEPL also showed a good capability of optic-first mix-and-match overlay correction and this is the most stringent and important functionality for optic-first mix-and-match application. However random intra-membrane image placement(IP) error that is a little bit larger than the requirement for sub-70nm node was observed, which is interpreted to come from the larger stress of 100MPa in 3X3mm2 dry-etched SiC unit membrane. For dense C/Hs, we failed, to the contrary, to obtain any good quality of stencil masks for DRAM cell patterns because of e-beam proximity effect which is unavoidable in the reversed order of front-side forward direct writing and back-side later membrane formation. Pros and cons of LEEPL technology are discussed based on the evaluation results and estimation from the memory device standpoint. We also propose a novel concept of stencil mask that can be helpful in memory device application.

Direct printing of miniscule aluminum alloy droplets and 3D structures by StarJet technology

NASA Astrophysics Data System (ADS)

Gerdes, B.; Zengerle, R.; Koltay, P.; Riegger, L.

2018-07-01

Drop-on demand printing of molten metal droplets could be used for prototyping 3D objects as a promising alternative to laser melting technologies. However, to date, only few printheads have been investigated for this purpose, and they used only a limited range of materials. The pneumatically actuated StarJet technology enables the direct and non-contact printing of molten metal microdroplets from metal melts at high temperatures. StarJet printheads utilize nozzle chips featuring a star-shaped orifice geometry that leads to formation of droplets inside the nozzle with high precision. In this paper, we present a novel StarJet printhead for printing aluminum (Al) alloys featuring a hybrid design with a ceramic reservoir for the molten metal and an outer shell fabricated from stainless steel. The micro machined nozzle chip is made from silicon carbide (SiC). This printhead can be operated at up to 950 °C, and is capable of printing high melting point metals like Al alloys in standard laboratory conditions. In this work, an aluminum–silicon alloy that features 12% silicon (AlSi12) is printed. The printhead, nozzle, and peripheral actuation system are optimized for stable generation of AlSi12 droplets with high monodispersity, low angular deviation, and miniaturized droplet diameters. As a result, a stable drop-on-demand printing of droplets exhibiting diameters of d droplet  =  702 µm  ±  1% is demonstrated at 5 Hz with a low angular deviation of 0.3°, when a nozzle chip with 500 µm orifice diameter is used. Furthermore, AlSi12 droplets featuring d droplet  =  176 µm  ±  7% are printed when using a nozzle chip with an orifice diameter of 130 µm. Moreover, we present directly printed objects from molten Al alloy droplets, such as high aspect ratio, free-standing walls (aspect ratio 12:1), and directly printed, flexible springs, to demonstrate the principle of 3D printing with molten metal droplets.

Deterministic Aperiodic Structures for on-chip Nanophotonics and Nanoplasmonics Device Applications

DTIC Science & Technology

2013-04-01

the origin of the superior field enhancement and localization observed in several aperiodic plasmonic structures. Due to the ...removed by hot acetone bath, resulting in the Si nano-hole master . The Si master is first treated with a silanizing agent to reduce the adhesion of ...arrays needs to be utilized, as illustrated in Figs. 7(a-d). The nanodot master fabrication proceeds

The Longwave Silicon Chip - Integrated Plasma-Photonics in Group IV And III-V Semiconductors

DTIC Science & Technology

2013-10-01

infrared applications; SiGeSn heterostructure photonics; group IV plasmonics with silicides , germanicides, doped Si, Ge or GeSn; Franz-Keldysh...SPP waveguide in which localized silicide or germanicide “conductors” are introduced to give local plasmonic confinement. Therefore, guided-wave...reconfigurable integrated optoelectronics, electro-optical logic in silicon, silicides for group IV plasmonics, reviews of third-order nonlinear optical

Metal-ferroelectric-metal capacitor based persistent memory for electronic product code class-1 generation-2 uhf passive radio-frequency identification tag

NASA Astrophysics Data System (ADS)

Yoon, Bongno; Sung, Man Young; Yeon, Sujin; Oh, Hyun S.; Kwon, Yoonjoo; Kim, Chuljin; Kim, Kyung-Ho

2009-03-01

With the circuits using metal-ferroelectric-metal (MFM) capacitor, rf operational signal properties are almost the same or superior to those of polysilicon-insulator-polysilicon, metal-insulator-metal, and metal-oxide-semiconductor (MOS) capacitors. In electronic product code global class-1 generation-2 uhf radio-frequency identification (RFID) protocols, the MFM can play a crucial role in satisfying the specifications of the inventoried flag's persistence times (Tpt) for each session (S0-S3, SL). In this paper, we propose and design a new MFM capacitor based memory scheme of which persistence time for S1 flag is measured at 2.2 s as well as indefinite for S2, S3, and SL flags during the period of power-on. A ferroelectric random access memory embedded RFID tag chip is fabricated with an industry-standard complementary MOS process. The chip size is around 500×500 μm2 and the measured power consumption is about 10 μW.

MIL-STD-1553B Marconi LSI chip set in a remote terminal application

NASA Astrophysics Data System (ADS)

Dimarino, A.

1982-11-01

Marconi Avionics is utilizing the MIL-STD-1553B LSI Chip Set in the SCADC Air Data Computer application to perform all of the required remote terminal MIL-STD-1553B protocol functions. Basic components of the RTU are the dual redundant chip set, CT3231 Transceivers, 256 x 16 RAM and a Z8002 microprocessor. Basic transfers are to/from the RAM command of the bus controller or Z8002 processor. During transfers from the processor to the RAM, the chip set busy bit is set for a period not exceeding 250 microseconds. When the transfer is complete, the busy bit is released and transfers to the data bus occur on command. The LSI Chip Set word count lines are used to locate each data word in the local memory and 4 mode codes are used in the application: reset remote terminal, transmit status word, transmitter shut-down, and override transmitter shutdown.

Si-Sb-Te materials for phase change memory applications.

PubMed

Rao, Feng; Song, Zhitang; Ren, Kun; Zhou, Xilin; Cheng, Yan; Wu, Liangcai; Liu, Bo

2011-04-08

Si-Sb-Te materials including Te-rich Si₂Sb₂Te₆ and Si(x)Sb₂Te₃ with different Si contents have been systemically studied with the aim of finding the most suitable Si-Sb-Te composition for phase change random access memory (PCRAM) use. Si(x)Sb₂Te₃ shows better thermal stability than Ge₂Sb₂Te₅ or Si₂Sb₂Te₆ in that Si(x)Sb₂Te₃ does not have serious Te separation under high annealing temperature. As Si content increases, the data retention ability of Si(x)Sb₂Te₃ improves. The 10 years retention temperature for Si₃Sb₂Te₃ film is ~393 K, which meets the long-term data storage requirements of automotive electronics. In addition, Si richer Si(x)Sb₂Te₃ films also show improvement on thickness change upon annealing and adhesion on SiO₂ substrate compared to those of Ge₂Sb₂Te₅ or Si₂Sb₂Te₆ films. However, the electrical performance of PCRAM cells based on Si(x)Sb₂Te₃ films with x > 3.5 becomes worse in terms of stable and long-term operations. Si(x)Sb₂Te₃ materials with 3 < x < 3.5 are proved to be suitable for PCRAM use to ensure good overall performance.

Wavelength dispersion characteristics of integrated silicon avalanche LEDs: potential applications in futuristic on-chip micro- and nano-biosensors

NASA Astrophysics Data System (ADS)

Okhai, Timothy A.; Snyman, Lukas W.; Polleux, Jean-Luc

2016-02-01

Si Av LEDs are easily integrated in on-chip integrated circuitry. They have high modulation frequencies into the GHz range and can be fabricated to sub-micron dimensions. Due to subsurface light generation in the silicon device itself, and the high refractive index differences between silicon and the device environment, the exiting light radiation has interesting dispersion characteristics. Three junction micro p+-np+ Silicon Avalanche based Light Emitting Devices (Si Av LEDs) have been analyzed in terms of dispersion characteristics, generally resulting in different wavelengths of light (colors) being emitted at different angles and solid angles from the surfaces of these devices. The emission wavelength is in the 450 - 850 nm range. The devices are of micron dimension and operate at 8 - 10V, 1μA - 2mA. The emission spot sizes are about 1 micron square. Emission intensities are up to 500 nW.μm-2. The observed dispersion characteristics range from 0.05 degrees per nm per degree at emission angle of 5 degrees, to 0.15 degrees per nm at emission angles of 30 degrees. It is believed that the dispersion characteristics can find interesting and futuristic on-chip electro-optic applications involving particularly a ranging from on chip micro optical wavelength dispersers, communication de-multiplexers, and novel bio-sensor applications. All of these could penetrate into the nanoscale dimensions.

Ultrahigh-speed Si-integrated on-chip laser with tailored dynamic characteristics

NASA Astrophysics Data System (ADS)

Park, Gyeong Cheol; Xue, Weiqi; Piels, Molly; Zibar, Darko; Mørk, Jesper; Semenova, Elizaveta; Chung, Il-Sug

2016-12-01

For on-chip interconnects, an ideal light source should have an ultralow energy consumption per bandwidth (operating en-ergy) as well as sufficient output power for error-free detection. Nanocavity lasers have been considered the most ideal for smaller operating energy. However, they have a challenge in obtaining a sufficient output power. Here, as an alternative, we propose an ultrahigh-speed microcavity laser structure, based on a vertical cavity with a high-contrast grating (HCG) mirror for transverse magnetic (TM) polarisation. By using the TM HCG, a very small mode volume and an un-pumped compact optical feedback structure can be realised, which together tailor the frequency response function for achieving a very high speed at low injection currents. Furthermore, light can be emitted laterally into a Si waveguide. From an 1.54-μm optically-pumped laser, a 3-dB frequency of 27 GHz was obtained at a pumping level corresponding to sub-mA. Using measured 3-dB frequen-cies and calculated equivalent currents, the modulation current efficiency factor (MCEF) is estimated to be 42.1 GHz/mA1/2, which is superior among microcavity lasers. This shows a high potential for a very high speed at low injection currents or avery small heat generation at high bitrates, which are highly desirable for both on-chip and off-chip applications.

Superior Sensitivity of Copper-Based Plasmonic Biosensors.

PubMed

Stebunov, Yury V; Yakubovsky, Dmitry I; Fedyanin, Dmitry Yu; Arsenin, Aleksey V; Volkov, Valentyn S

2018-04-17

Plasmonic biosensing has been demonstrated to be a powerful technique for quantitative determination of molecular analytes and kinetic analysis of biochemical reactions. However, interfaces of most plasmonic biosensors are made of noble metals, such as gold and silver, which are not compatible with industrial production technologies. This greatly limits biosensing applications beyond biochemical and pharmaceutical research. Here, we propose and investigate copper-based biosensor chips fully fabricated with a standard complementary metal-oxide-semiconductor (CMOS) process. The protection of thin copper films from oxidation is achieved with SiO 2 and Al 2 O 3 dielectric films deposited onto the metal surface. In addition, the deposition of dielectric films with thicknesses of only several tens of nanometers significantly improves the biosensing sensitivity, owing to better localization of electromagnetic field above the biosensing surface. According to surface plasmon resonance (SPR) measurements, the copper biosensor chips coated with thin films of SiO 2 (25 nm) and Al 2 O 3 (15 nm) show 55% and 75% higher sensitivity to refractive index changes, respectively, in comparison to pure gold sensor chips. To test biomolecule immobilization, the copper-dielectric biosensor chips are coated with graphene oxide linking layers and used for the selective analysis of oligonucleotide hybridization. The proposed plasmonic biosensors make SPR technology more affordable for various applications and provide the basis for compact biosensors integrated with modern electronic devices.

Multiple core computer processor with globally-accessible local memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shalf, John; Donofrio, David; Oliker, Leonid

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality ofmore » processor cores.« less

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

NiMnGa/Si Shape Memory Bimorph Nanoactuation

NASA Astrophysics Data System (ADS)

Lambrecht, Franziska; Lay, Christian; Aseguinolaza, Iván R.; Chernenko, Volodymyr; Kohl, Manfred

2016-12-01

The size dependences of thermal bimorph and shape memory effect of nanoscale shape memory alloy (SMA)/Si bimorph actuators are investigated in situ in a scanning electron microscope and by finite element simulations. By combining silicon nanomachining and magnetron sputtering, freestanding NiMnGa/Si bimorph cantilever structures with film/substrate thickness of 200/250 nm and decreasing lateral dimensions are fabricated. Electrical resistance and mechanical beam bending tests upon direct Joule heating demonstrate martensitic phase transformation and reversible thermal bimorph effect, respectively. Corresponding characteristics are strongly affected by the large temperature gradient in the order of 50 K/µm forming along the nano bimorph cantilever upon electro-thermal actuation, which, in addition, depends on the size-dependent heat conductivity in the Si nano layer. Furthermore, the martensitic transformation temperatures show a size-dependent decrease by about 40 K for decreasing lateral dimensions down to 200 nm. The effects of heating temperature and stress distribution on the nanoactuation performance are analyzed by finite element simulations revealing thickness ratio of SMA/Si of 90/250 nm to achieve an optimum SME. Differential thermal expansion and thermo-elastic effects are discriminated by comparative measurements and simulations on Ni/Si bimorph reference actuators.

Three-terminal resistive switching memory in a transparent vertical-configuration device

NASA Astrophysics Data System (ADS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

Packaging of a large capacity magnetic bubble domain spacecraft recorder

NASA Technical Reports Server (NTRS)

Becker, F. J.; Stermer, R. L.

1977-01-01

A Solid State Spacecraft Data Recorder (SSDR), based on bubble domain technology, having a storage capacity of 10 to the 8th power bits, was designed and is being tested. The recorder consists of two memory modules each having 32 cells, each cell containing sixteen 100 kilobit serial bubble memory chips. The memory modules are interconnected to a Drive and Control Unit (DCU) module containing four microprocessors, 500 integrated circuits, a RAM core memory and two PROM's. The two memory modules and DCU are housed in individual machined aluminum frames, are stacked in brick fashion and through bolted to a base plate assembly which also houses the power supply.

Processing-in-Memory Enabled Graphics Processors for 3D Rendering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xie, Chenhao; Song, Shuaiwen; Wang, Jing

2017-02-06

The performance of 3D rendering of Graphics Processing Unit that convents 3D vector stream into 2D frame with 3D image effects significantly impact users’ gaming experience on modern computer systems. Due to the high texture throughput in 3D rendering, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D stacked memory systems such as Hybrid Memory Cube (HMC) provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Based on the observation that texel fetches significantly impact off-chip memory traffic, we propose two architectural designs to enable Processing-In-Memory based GPUmore » for efficient 3D rendering.« less

CHIP/Stub1 regulates the Warburg effect by promoting degradation of PKM2 in ovarian carcinoma.

PubMed

Shang, Y; He, J; Wang, Y; Feng, Q; Zhang, Y; Guo, J; Li, J; Li, S; Wang, Y; Yan, G; Ren, F; Shi, Y; Xu, J; Zeps, N; Zhai, Y; He, D; Chang, Z

2017-07-20

Tumor cells preferentially adopt aerobic glycolysis for their energy supply, a phenomenon known as the Warburg effect. It remains a matter of debate as to how the Warburg effect is regulated during tumor progression. Here, we show that CHIP (carboxyl terminus of Hsc70-interacting protein), a U-box E3 ligase, suppresses tumor progression in ovarian carcinomas by inhibiting aerobic glycolysis. While CHIP is downregulated in ovarian carcinoma, induced expression of CHIP results in significant inhibition of the tumor growth examined by in vitro and in vivo experiments. Reciprocally, depletion of CHIP leads to promotion of tumor growth. By a SiLAD proteomics analysis, we identified pyruvate kinase isoenzyme M2 (PKM2), a critical regulator of glycolysis in tumors, as a target that CHIP mediated for degradation. Accordingly, we show that CHIP regulates PKM2 protein stability and thereafter the energy metabolic processes. Depletion or knockout of CHIP increased the glycolytic products in both tumor and mouse embryonic fibroblast cells. Simultaneously, we observed that CHIP expression inversely correlated with PKM2 levels in human ovarian carcinomas. This study reveals a mechanism that the Warburg effect is regulated by CHIP through its function as an E3 ligase, which mediates the degradation of PKM2 during tumor progression. Our findings shed new light into understanding of ovarian carcinomas and may provide a new therapeutic strategy for ovarian cancer.

Silver flip chip interconnect technology and solid state bonding

NASA Astrophysics Data System (ADS)

Sha, Chu-Hsuan

In this dissertation, fluxless transient liquid phase (TLP) bonding and solid state bonding between thermal expansion mismatch materials have been developed using Ag-In binary systems, pure Au, Ag, and Cu-Ag composite. In contrast to the conventional soldering process, fluxless bonding technique eliminates any corrosion and contamination problems caused by flux. Without flux, it is possible to fabricate high quality joints in large bonding areas where the flux is difficult to clean entirely. High quality joints are crucial to bonding thermal expansion mismatch materials since shear stress develops in the bonded pair. Stress concentration at voids in joints could increases breakage probability. In addition, intermetallic compound (IMC) formation between solder and underbump metallurgy (UBM) is essential for interconnect joint formation in conventional soldering process. However, the interface between IMC and solder is shown to be the weak interface that tends to break first during thermal cycling and drop tests. In our solid state bonding technique, there is no IMC involved in the bonding between Au to Au, Ag and Cu, and Ag and Au. All the reliability issues related to IMC or IMC growth is not our concern. To sum up, ductile bonding media, such as Ag or Au, and proper metallic layered structure are utilized in this research to produce high quality joints. The research starts with developing a low temperature fluxless bonding process using electroplated Ag/In/Ag multilayer structures between Si chip and 304 stainless steel (304SS) substrate. Because the outer thin Ag layer effectively protects inner In layer from oxidation, In layer dissolves Ag layer and joints to Ag layer on the to-be-bonded Si chip when temperature reaches the reflow temperature of 166ºC. Joints consist of mainly Ag-rich Ag-In solid solution and Ag2In. Using this fluxless bonding technique, two 304SS substrates can be bonded together as well. From the high magnification SEM images taken at cross-section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active (front) side is connected to the package using a large number of tiny solder joints, which provide mechanical support, electrical connection, and heat conduction. For chip-to-package level interconnects, a challenge is the severe mismatch in coefficient of thermal expansion (CTE) between chips and package substrates. The interconnect material thus needs to be compliant to deal with the CTE mismatch. At present, nearly all flip-chip interconnects in electronic industries are made of lead-free Sn-based solders. Soft solders are chosen due to high ductility, low yield strength, relatively low melting temperature, and reasonably good electrical and thermal conductivities. In the never ending scaling down trend, more and more transistors are placed on the same Si chip size. This results in larger pin-out numbers and smaller solder joints. According to International Technology Roadmap for Semiconductors (ITRS), by 2018, the pitch in flip-chip interconnects will become smaller than 70mum for high performance applications. Two problems occur. The first is increase in shear strain. The aspect ratio of flip-chip joints is constrained to 0.7 because it goes through molten phase in the reflow process. Therefore, smaller joints become shorter as well, resulting in larger shear strain arising from CTE mismatch between Si chips and package substrates. The second is increase in stress in the joints. Since intermetallic (IMC) thickness in the joint does not scale down with joint size, ratio of IMC thickness to joint height increases. This further enlarges the shear stress because the IMC does not deform as the soft solder does to accommodate CTE mismatch. In this research, the smallest dimension we achieve for Ag flip chip interconnect joint is 15mum in diameter. The ten advantages of Ag flip chip interconnect technology can be identified as (a) High electrical conductivity, 7.7 times of that of Pb-free solders, (b) High thermal conductivity, 5.2 times of that of Pb-free solders, (c) Completely fluxless, (d) No IMCs; all reliability issues associated with IMC and IMC growth do not exist, (e) Ag is very ductile and can manage CTE mismatch between chips and packages, (f) Ag joints can sustain at very high operation temperature because Ag has high melting temperature of 961°C, (g) No molten phase involved; the bump can better keep its shape and geometry, (h) No molten phase involved; bridging of adjacent bumps is less likely to occur, i. Aspect ratio of bumps can be made greater than 1, (j) The size of the bumps is only limited by the lithographic process. Cu-Ag composite flip chip interconnect joints is developed based on three reasons. The first is lower material cost. The second is to strengthen the columns because the yield strength of Cu is 6 times of that of Ag. The third is to avoid possible Ag migration between Ag electrodes under voltage at temperatures above 250°C. This Cu-Ag composite design presents a solution in the path to the scale down roadmap.

Progress in ion torrent semiconductor chip based sequencing.

PubMed

Merriman, Barry; Rothberg, Jonathan M

2012-12-01

In order for next-generation sequencing to become widely used as a diagnostic in the healthcare industry, sequencing instrumentation will need to be mass produced with a high degree of quality and economy. One way to achieve this is to recast DNA sequencing in a format that fully leverages the manufacturing base created for computer chips, complementary metal-oxide semiconductor chip fabrication, which is the current pinnacle of large scale, high quality, low-cost manufacturing of high technology. To achieve this, ideally the entire sensory apparatus of the sequencer would be embodied in a standard semiconductor chip, manufactured in the same fab facilities used for logic and memory chips. Recently, such a sequencing chip, and the associated sequencing platform, has been developed and commercialized by Ion Torrent, a division of Life Technologies, Inc. Here we provide an overview of this semiconductor chip based sequencing technology, and summarize the progress made since its commercial introduction. We described in detail the progress in chip scaling, sequencing throughput, read length, and accuracy. We also summarize the enhancements in the associated platform, including sample preparation, data processing, and engagement of the broader development community through open source and crowdsourcing initiatives. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Coated Porous Si for High Performance On-Chip Supercapacitors

NASA Astrophysics Data System (ADS)

Grigoras, K.; Keskinen, J.; Grönberg, L.; Ahopelto, J.; Prunnila, M.

2014-11-01

High performance porous Si based supercapacitor electrodes are demonstrated. High power density and stability is provided by ultra-thin TiN coating of the porous Si matrix. The TiN layer is deposited by atomic layer deposition (ALD), which provides sufficient conformality to reach the bottom of the high aspect ratio pores. Our porous Si supercapacitor devices exhibit almost ideal double layer capacitor characteristic with electrode volumetric capacitance of 7.3 F/cm3. Several orders of magnitude increase in power and energy density is obtained comparing to uncoated porous silicon electrodes. Good stability of devices is confirmed performing several thousands of charge/discharge cycles.

GaAs/AlGaAs core multishell nanowire-based light-emitting diodes on Si.

PubMed

Tomioka, Katsuhiro; Motohisa, Junichi; Hara, Shinjiroh; Hiruma, Kenji; Fukui, Takashi

2010-05-12

We report on integration of GaAs nanowire-based light-emitting-diodes (NW-LEDs) on Si substrate by selective-area metalorganic vapor phase epitaxy. The vertically aligned GaAs/AlGaAs core-multishell nanowires with radial p-n junction and NW-LED array were directly fabricated on Si. The threshold current for electroluminescence (EL) was 0.5 mA (current density was approximately 0.4 A/cm(2)), and the EL intensity superlinearly increased with increasing current injections indicating superluminescence behavior. The technology described in this letter could help open new possibilities for monolithic- and on-chip integration of III-V NWs on Si.

Self-imagination can enhance memory in individuals with schizophrenia.

PubMed

Raffard, Stéphane; Bortolon, Catherine; Burca, Mariana; Novara, Caroline; Gely-Nargeot, Marie-Christine; Capdevielle, Delphine; Van der Linden, Martial

2016-01-01

Previous research has demonstrated that self-referential strategies can be applied to improve memory in various memory- impaired populations. However, little is known regarding the relative effectiveness of self-referential strategies in schizophrenia patients. The main aim of this study was to assess the effectiveness of a new self-referential strategy known as self- imagination (SI) on a free recall task. Twenty schizophrenia patients and 20 healthy controls intentionally encoded words under five instructions: superficial processing, semantic processing, semantic self-referential processing, episodic self-referential processing and semantic self- imagining. Other measures included depression, psychotic symptoms and cognitive measures. We found a SI effect in memory as self- imagining resulted in better performance in memory retrieval than semantic and superficial encoding in schizophrenia patients. The memory boost for self-referenced information in comparison to semantic processing was not found for other self-referential strategies. In addition no relationship between clinical variables and free recall performances was found. In controls, the SI condition did not result in better performance. The three self-referential strategies yielded better free recall than both superficial and semantic encoding. This study provides evidence of the clinical utility of self-imagining as a mnemonic strategy in schizophrenia patients.

Distributed trace using central performance counter memory

DOEpatents

Satterfield, David L; Sexton, James C

2013-10-22

A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Distributed trace using central performance counter memory

DOEpatents

Satterfield, David L.; Sexton, James C.

2013-01-22

A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

PICSiP: new system-in-package technology using a high bandwidth photonic interconnection layer for converged microsystems

NASA Astrophysics Data System (ADS)

Tekin, Tolga; Töpper, Michael; Reichl, Herbert

2009-05-01

Technological frontiers between semiconductor technology, packaging, and system design are disappearing. Scaling down geometries [1] alone does not provide improvement of performance, less power, smaller size, and lower cost. It will require "More than Moore" [2] through the tighter integration of system level components at the package level. System-in-Package (SiP) will deliver the efficient use of three dimensions (3D) through innovation in packaging and interconnect technology. A key bottleneck to the implementation of high-performance microelectronic systems, including SiP, is the lack of lowlatency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk [3]. Obviously, the incentive for the use of photonics to overcome the challenges and leverage low-latency and highbandwidth communication will enable the vision of optical computing within next generation architectures. Supercomputers of today offer sustained performance of more than petaflops, which can be increased by utilizing optical interconnects. Next generation computing architectures are needed with ultra low power consumption; ultra high performance with novel interconnection technologies. In this paper we will discuss a CMOS compatible underlying technology to enable next generation optical computing architectures. By introducing a new optical layer within the 3D SiP, the development of converged microsystems, deployment for next generation optical computing architecture will be leveraged.

A novel digital image sensor with row wise gain compensation for Hyper Spectral Imager (HySI) application

NASA Astrophysics Data System (ADS)

Lin, Shengmin; Lin, Chi-Pin; Wang, Weng-Lyang; Hsiao, Feng-Ke; Sikora, Robert

2009-08-01

A 256x512 element digital image sensor has been developed which has a large pixel size, slow scan and low power consumption for Hyper Spectral Imager (HySI) applications. The device is a mixed mode, silicon on chip (SOC) IC. It combines analog circuitry, digital circuitry and optical sensor circuitry into a single chip. This chip integrates a 256x512 active pixel sensor array, a programming gain amplifier (PGA) for row wise gain setting, I2C interface, SRAM, 12 bit analog to digital convertor (ADC), voltage regulator, low voltage differential signal (LVDS) and timing generator. The device can be used for 256 pixels of spatial resolution and 512 bands of spectral resolution ranged from 400 nm to 950 nm in wavelength. In row wise gain readout mode, one can set a different gain on each row of the photo detector by storing the gain setting data on the SRAM thru the I2C interface. This unique row wise gain setting can be used to compensate the silicon spectral response non-uniformity problem. Due to this unique function, the device is suitable for hyper-spectral imager applications. The HySI camera located on-board the Chandrayaan-1 satellite, was successfully launched to the moon on Oct. 22, 2008. The device is currently mapping the moon and sending back excellent images of the moon surface. The device design and the moon image data will be presented in the paper.

A CMOS wireless biomolecular sensing system-on-chip based on polysilicon nanowire technology.

PubMed

Huang, C-W; Huang, Y-J; Yen, P-W; Tsai, H-H; Liao, H-H; Juang, Y-Z; Lu, S-S; Lin, C-T

2013-11-21

As developments of modern societies, an on-field and personalized diagnosis has become important for disease prevention and proper treatment. To address this need, in this work, a polysilicon nanowire (poly-Si NW) based biosensor system-on-chip (bio-SSoC) is designed and fabricated by a 0.35 μm 2-Poly-4-Metal (2P4M) complementary metal-oxide-semiconductor (CMOS) process provided by a commercialized semiconductor foundry. Because of the advantages of CMOS system-on-chip (SoC) technologies, the poly-Si NW biosensor is integrated with a chopper differential-difference amplifier (DDA) based analog-front-end (AFE), a successive approximation analog-to-digital converter (SAR ADC), and a microcontroller to have better sensing capabilities than a traditional Si NW discrete measuring system. In addition, an on-off key (OOK) wireless transceiver is also integrated to form a wireless bio-SSoC technology. This is pioneering work to harness the momentum of CMOS integrated technology into emerging bio-diagnosis technologies. This integrated technology is experimentally examined to have a label-free and low-concentration biomolecular detection for both Hepatitis B Virus DNA (10 fM) and cardiac troponin I protein (3.2 pM). Based on this work, the implemented wireless bio-SSoC has demonstrated a good biomolecular sensing characteristic and a potential for low-cost and mobile applications. As a consequence, this developed technology can be a promising candidate for on-field and personalized applications in biomedical diagnosis.

Designing an Electronics Data Package for Printed Circuit Boards (PCBs)

DTIC Science & Technology

2013-08-01

finished PCB flatness deviation should be less than 0.010 inches per inch. 4  The minimum copper wall thickness of plated-thru holes should be...Memory Card International Association)  IPC-6015 MCM-L (Multi-Chip Module – Laminated )  IPC-6016 HDI (High Density Interconnect)  IPC-6018...Interconnect ICT In Circuit Tester IPC Association Connecting Electronics Industries MCM-L Multi-Chip Module – Laminated MIL Military NEMA National

TMS-induced neural noise in sensory cortex interferes with short-term memory storage in prefrontal cortex.

PubMed

Bancroft, Tyler D; Hogeveen, Jeremy; Hockley, William E; Servos, Philip

2014-01-01

In a previous study, Harris et al. (2002) found disruption of vibrotactile short-term memory after applying single-pulse transcranial magnetic stimulation (TMS) to primary somatosensory cortex (SI) early in the maintenance period, and suggested that this demonstrated a role for SI in vibrotactile memory storage. While such a role is compatible with recent suggestions that sensory cortex is the storage substrate for working memory, it stands in contrast to a relatively large body of evidence from human EEG and single-cell recording in primates that instead points to prefrontal cortex as the storage substrate for vibrotactile memory. In the present study, we use computational methods to demonstrate how Harris et al.'s results can be reproduced by TMS-induced activity in sensory cortex and subsequent feedforward interference with memory traces stored in prefrontal cortex, thereby reconciling discordant findings in the tactile memory literature.

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs).

PubMed

Moradi, Saber; Qiao, Ning; Stefanini, Fabio; Indiveri, Giacomo

2018-02-01

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

Red/blue-shift dual-directional regulation of α-(Ca, Sr)2SiO4:Eu(2+) phosphors resulting from the incorporation content of Eu(2+)/Sr(2+) ions.

PubMed

Lu, Zhijuan; Mao, Zhiyong; Chen, Jingjing; Wang, Dajian

2015-09-21

In this work, tunable emission from green to red and the inverse tuning from red to green in α-(Ca, Sr)2SiO4:Eu(2+) phosphors were demonstrated magically by varying the incorporation content of Eu(2+) and Sr(2+) ions, respectively. The tunable emission properties and the tuning mechanism of red-shift resulting from the Eu(2+) content as well as that of blue-shift induced by the Sr(2+) content were investigated in detail. As a result of fine-controlling the incorporation content of Eu(2+), the emission peak red-shifts from 541 nm to 640 nm. On the other hand, the emission peak inversely blue-shifts from 640 nm to 546 nm through fine-adjusting the incorporation content of Sr(2+). The excellent tuning characteristics for α-(Ca, Sr)2SiO4:Eu(2+) phosphors presented in this work exhibited their various application prospects in solid-state lighting combining with a blue chip or a near-UV chip.

A low switching voltage organic-on-inorganic heterojunction memory element utilizing a conductive polymer fuse on a doped silicon substrate

NASA Astrophysics Data System (ADS)

Smith, Shawn; Forrest, Stephen R.

2004-06-01

We present a simple, nonvolatile, write-once-read-many-times (WORM) memory device utilizing an organic-on-inorganic heterojunction (OI-HJ) diode with a conductive polymer fuse consisting of polyethylene dioxythiophene:polysterene sulfonic acid (PEDOT:PSS) forming one side of the rectifying junction. Current transients are used to change the fuse from a conducting to a nonconducting state to record a logical "1" or "0", while the nonlinearity of the OI-HJ allows for passive matrix memory addressing. The device switches at 2 and 4 V for 50 nm thick PEDOT:PSS films on p-type Si and n-type Si, respectively. This is significantly lower than the switching voltage used in PEDOT:PSS/p-i-n Si memory elements [J. Appl Phys. 94, 7811 (2003)]. The switching results in a permanent reduction of forward-bias current by approximately five orders of magnitude. These results suggest that the OI-HJ structure has potential for use in low-cost passive matrix WORM memories for archival storage applications.

High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

2015-01-01

Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horowitz, Kelsey A; Bench Reese, Samantha R; Remo, Timothy W

This brochure, published as an annual research highlight of the Clean Energy Manufacturing Analysis Center (CEMAC), summarizes CEMAC analysis of silicon carbide (SiC) power electronics for variable frequency motor drives. The key finding presented is that variations in manufacturing expertise, yields, and access to existing facilities impact regional costs and manufacturing location decisions for SiC ingots, wafers, chips, and power modules more than do core country-specific factors such as labor and electricity costs.

1 GHz, 200 C, SiC MESFET Clapp Oscillator

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Schwartz, Zachary D.

2005-01-01

A SiC Clapp oscillator frabricated on an alumina substrate with chip capacitors and spiral inductors is designed for high temperature operation at 1 gigahertz. The oscillator operated from 30 to 200 C with an output power of 21.8 dBm at 1 gigahertz and 200 C. The efficiency at 200 C is 15 percent. The frequency variation over the temperature range is less than 0.5 percent.

Constructing polyamidoamine dendrons from poly(poly(ethylene glycol) monomethacrylate) brushes grafted from planar silicon hydride surfaces for biomedical applications

NASA Astrophysics Data System (ADS)

Liu, Xiang; Zheng, Hong-Ning; Yan, Qin; Wang, Cuie; Ma, Yin-Zhou; Tang, Yan-Chun; Xiao, Shou-Jun

2011-06-01

A facile approach was established to construct polyamidoamine (PAMAM) dendrons from polymer brushes of poly(poly(ethylene glycol) monomethacrylate) (Si-g-P(PEGMA-OH)) grafted from a planar silicon hydride surface. First the Si-g-P(PEGMA-OH) brushes were grown via surface-initiated atom transfer radical polymerization with robust Si-C links on silicon surfaces. The side-chain hydroxyl groups of Si-g-P(PEGMA-OH) were chlorinated with thionyl chloride and further chlorines were substituted with amino groups of ethylenediamine, giving terminal primary amines. Borrowing the solution synthesis approach, we constructed second and third generations of PAMAM dendrons on-chip by surface-initiated alternative growth of two monomers, methyl acrylate and ethylenediamine. Two applications of silicon-based PAMAM dendrons were shown: the dense amino groups were activated via a cross-linker, N-succinimidyl-6-maleimidylhexanoate, to capture a free-thiol-carrying peptide of oxytocin and the third generation of PAMAM dendrons was used as a platform to on-chip synthesize a three amino acid peptide of Arg-Gly-Asp (RGD). The above conclusions were mainly derived from a home-built multiple transmission-reflection infrared spectroscopy, and complemented by X-ray photoelectron spectroscopy, UV-Vis spectroscopy and matrix-assisted laser desorption/ionization-time of flight-mass spectrometry.

Highly uniform and reliable resistive switching characteristics of a Ni/WOx/p+-Si memory device

NASA Astrophysics Data System (ADS)

Kim, Tae-Hyeon; Kim, Sungjun; Kim, Hyungjin; Kim, Min-Hwi; Bang, Suhyun; Cho, Seongjae; Park, Byung-Gook

2018-02-01

In this paper, we investigate the resistive switching behavior of a bipolar resistive random-access memory (RRAM) in a Ni/WOx/p+-Si RRAM with CMOS compatibility. Highly unifrom and reliable bipolar resistive switching characteristics are observed by a DC voltage sweeping and its switching mechanism can be explained by SCLC model. As a result, the possibility of metal-insulator-silicon (MIS) structural WOx-based RRAM's application to Si-based 1D (diode)-1R (RRAM) or 1T (transistor)-1R (RRAM) structure is demonstrated.

Physics of self-aligned assembly at room temperature

NASA Astrophysics Data System (ADS)

Dubey, V.; Beyne, E.; Derakhshandeh, J.; De Wolf, I.

2018-01-01

Self-aligned assembly, making use of capillary forces, is considered as an alternative to active alignment during thermo-compression bonding of Si chips in the 3D heterogeneous integration process. Various process parameters affect the alignment accuracy of the chip over the patterned binding site on a substrate/carrier wafer. This paper discusses the chip motion due to wetting and capillary force using a transient coupled physics model for the two regimes (that is, wetting regime and damped oscillatory regime) in the temporal domain. Using the transient model, the effect of the volume of the liquid and the placement accuracy of the chip on the alignment force is studied. The capillary time (that is, the time it takes for the chip to reach its mean position) for the chip is directly proportional to the placement offset and inversely proportional to the viscosity. The time constant of the harmonic oscillations is directly proportional to the gap between the chips due to the volume of the fluid. The predicted behavior from transient simulations is next experimentally validated and it is confirmed that the liquid volume and the initial placement affect the final alignment accuracy of the top chip on the bottom substrate. With statistical experimental data, we demonstrate an alignment accuracy reaching <1 μm.

Quantum confinement effects in lithographic sub-5 nm Silicon nanowire fets and integration of si nanograting fet biosensors

NASA Astrophysics Data System (ADS)

Trivedi, Krutarth B.

In recent years, widespread accessibility to reliable nanofabrication techniques such as high resolution electron beam lithography as well as development of innovative techniques such as nanoimprint lithography and chemically grown nano-materials like carbon nanotubes and graphene have spurred a boom in many fields of research involving nanoscale features and devices. The breadth of fields in which nanoscale features represent a new paradigm is staggering. Scaling down device dimensions to nanoscale enables non-classical quantum behavior and allows for interaction with similarly sized natural materials, like proteins and DNA, as never before, affording an unprecedented level of performance and control and fostering a seemingly boundless array of unique applications. Much of the research effort has been directed toward understanding such interactions to leverage the potential of nanoscale devices to enhance electronic and medical technology. In keeping with the spirit of application based research, my graduate research career has spanned the development of nanoimprint techniques and devices for novel applications, demonstration and study of sub-5 nm Si nanowire FETs exhibiting tangible performance enhancement over conventional MOSFETs, and development of an integrated Si nanograting FET based biosensor and related framework. The following dissertation details my work in fabrication of sub-5 nm Si nanowire FETs and characterization of quantum confinement effects in charge transport of FETs with 2D and 1D channel geometry, fabrication and characterization of schottky contact Si nanograting FET sensors, integration of miniaturized Si nanograting FET biosensors into Chip-in-Strip(c) packaging, development of an automated microfluidic sensing system, and investigation of electrochemical considerations in the Si nanograting FET biosensor gate stack followed by development of a novel patent-pending strategy for a lithographically patterned on-chip gate electrode.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

SiC Multi-Chip Power Modules as Power-System Building Blocks

NASA Technical Reports Server (NTRS)

Lostetter, Alexander; Franks, Steven

2007-01-01

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Sub-GHz-resolution C-band Nyquist-filtering interleaver on a high-index-contrast photonic integrated circuit.

PubMed

Zhuang, Leimeng; Zhu, Chen; Corcoran, Bill; Burla, Maurizio; Roeloffzen, Chris G H; Leinse, Arne; Schröder, Jochen; Lowery, Arthur J

2016-03-21

Modern optical communications rely on high-resolution, high-bandwidth filtering to maximize the data-carrying capacity of fiber-optic networks. Such filtering typically requires high-speed, power-hungry digital processes in the electrical domain. Passive optical filters currently provide high bandwidths with low power consumption, but at the expense of resolution. Here, we present a passive filter chip that functions as an optical Nyquist-filtering interleaver featuring sub-GHz resolution and a near-rectangular passband with 8% roll-off. This performance is highly promising for high-spectral-efficiency Nyquist wavelength division multiplexed (N-WDM) optical super-channels. The chip provides a simple two-ring-resonator-assisted Mach-Zehnder interferometer, which has a sub-cm² footprint owing to the high-index-contrast Si₃N₄/SiO₂ waveguide, while manifests low wavelength-dependency enabling C-band (> 4 THz) coverage with more than 160 effective free spectral ranges of 25 GHz. This device is anticipated to be a critical building block for spectrally-efficient, chip-scale transceivers and ROADMs for N-WDM super-channels in next-generation optical communication networks.

A novel approach of high speed scratching on silicon wafers at nanoscale depths of cut

PubMed Central

Zhang, Zhenyu; Guo, Dongming; Wang, Bo; Kang, Renke; Zhang, Bi

2015-01-01

In this study, a novel approach of high speed scratching is carried out on silicon (Si) wafers at nanoscale depths of cut to investigate the fundamental mechanisms in wafering of solar cells. The scratching is conducted on a Si wafer of 150 mm diameter with an ultraprecision grinder at a speed of 8.4 to 15 m/s. Single-point diamonds of a tip radius of 174, 324, and 786 nm, respectively, are used in the study. The study finds that at the onset of chip formation, an amorphous layer is formed at the topmost of the residual scratch, followed by the pristine crystalline lattice beneath. This is different from the previous findings in low speed scratching and high speed grinding, in which there is an amorphous layer at the top and a damaged layer underneath. The final width and depth of the residual scratch at the onset of chip formation measured vary from 288 to 316 nm, and from 49 to 62 nm, respectively. High pressure phases are absent from the scratch at the onset of either chip or crack formation. PMID:26548771

Associative Memories for Supercomputers

DTIC Science & Technology

1992-12-01

the Si/PLZT technology. Finally, the associative memory system design is presented. 14. SUBJECT TERMS IS NUMBER OF PAGES 60 Memory, Associative Memory...Hybrid lens design ...................................................................... 3 3. ASSOCIATIVE MEMORY STUDY...of California, san Diego 1. OBJECTIVES Our objective during the funding period, July 14 1989 to January 13 1991, was to design and study the

Advanced Silicon Photonic Device Architectures for Optical Communications: Proposals and Demonstrations

NASA Astrophysics Data System (ADS)

Sacher, Wesley David

Photonic integrated circuits implemented on silicon (Si) hold the potential for densely integrated electro-optic and passive devices manufactured by the high-volume fabrication and sophisticated assembly processes used for complementary metal-oxide-semiconductor (CMOS) electronics. However, high index contrast Si photonics has a number of functional limitations. In this thesis, several devices are proposed, designed, and experimentally demonstrated to overcome challenges in the areas of resonant modulation, waveguide loss, fiber-to-chip coupling, and polarization control. The devices were fabricated using foundry services at IBM and A*STAR Institute of Microelectronics (IME). First, we describe coupling modulated microrings, in which the coupler between a microring and the bus waveguide is modulated. The device circumvents the modulation bandwidth vs. resonator linewidth trade-off of conventional intracavity modulated microrings. We demonstrate a Si coupling modulated microring with a small-signal modulation response free of the parasitic resonator linewidth limitations at frequencies up to about 6x the linewidth. Comparisons of eye diagrams show that coupling modulation achieved data rates > 2x the rate attainable with intracavity modulation. Second, we demonstrate a silicon nitride (Si3N4)-on-Si photonic platform with independent Si3N4 and Si waveguides and taper transitions to couple light between the layers. The platform combines the excellent passive waveguide properties of Si3N4 and the compatibility of Si waveguides with electro-optic devices. Within the platform, we propose and demonstrate dual-level, Si3N 4-on-Si, fiber-to-chip grating couplers that simultaneously have wide bandwidths and high coupling efficiencies. Conventional Si and Si3N 4 grating couplers suffer from a trade-off between bandwidth and coupling efficiency. The dual-level grating coupler achieved a peak coupling efficiency of -1.3 dB and a 1-dB bandwidth of 80 nm, a record for the coupling efficiency-bandwidth product. Finally, we describe polarization rotator-splitters and controllers based on mode conversion between the fundamental transverse magnetic polarized mode and a high order transverse electric polarized mode in vertically asymmetric waveguides. We demonstrate the first polarization rotator-splitters and controllers that are fully compatible with standard active Si photonic platforms and extend the concept to our Si3N4-on-Si photonic platform.

Processing and Characterization of NiTi Shape Memory Alloy Particle Reinforced Sn-In Solders

DTIC Science & Technology

2006-12-01

solders generally operate at a high homologous temperature. Thermally induced grain growth, mechanical stress-induced grain growth and recrystallization ...the number of I/O connects available for flip chip as compared to the wirebond chip For interconnection and packaging, Pb-Sn and eutectic 63Sn...lower melting point is desired. The maximum use temperature for this alloy is around 120°C due to the fact that the eutectic reaction happened at

Chip architecture - A revolution brewing

NASA Astrophysics Data System (ADS)

Guterl, F.

1983-07-01

Techniques being explored by microchip designers and manufacturers to both speed up memory access and instruction execution while protecting memory are discussed. Attention is given to hardwiring control logic, pipelining for parallel processing, devising orthogonal instruction sets for interchangeable instruction fields, and the development of hardware for implementation of virtual memory and multiuser systems to provide memory management and protection. The inclusion of microcode in mainframes eliminated logic circuits that control timing and gating of the CPU. However, improvements in memory architecture have reduced access time to below that needed for instruction execution. Hardwiring the functions as a virtual memory enhances memory protection. Parallelism involves a redundant architecture, which allows identical operations to be performed simultaneously, and can be directed with microcode to avoid abortion of intermediate instructions once on set of instructions has been completed.

Built-in self-repair of VLSI memories employing neural nets

NASA Astrophysics Data System (ADS)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Fault-Tolerant, Real-Time, Multi-Core Computer System

NASA Technical Reports Server (NTRS)

Gostelow, Kim P.

2012-01-01

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts.

Role of Al2O3 thin layer on improving the resistive switching properties of Ta5Si3-based conductive bridge random accesses memory device

NASA Astrophysics Data System (ADS)

Kumar, Dayanand; Aluguri, Rakesh; Chand, Umesh; Tseng, Tseung-Yuen

2018-04-01

Ta5Si3-based conductive bridge random access memory (CBRAM) devices have been investigated to improve their resistive switching characteristics for their application in future nonvolatile memory technology. Changes in the switching characteristics by the addition of a thin Al2O3 layer of different thicknesses at the bottom electrode interface of a Ta5Si3-based CBRAM devices have been studied. The double-layer device with a 1 nm Al2O3 layer has shown improved resistive switching characteristics over the single layer one with a high on/off resistance ratio of 102, high endurance of more than 104 cycles, and good retention for more than 105 s at the temperature of 130 °C. The higher thermal conductivity of Al2O3 over Ta5Si3 has been attributed to the enhanced switching properties of the double-layer devices.

Push-broom imaging spectrometer based on planar lightwave circuit MZI array

NASA Astrophysics Data System (ADS)

Yang, Minyue; Li, Mingyu; He, Jian-Jun

2017-05-01

We propose a large aperture static imaging spectrometer (LASIS) based on planar lightwave circuit (PLC) MZI array. The imaging spectrometer works in the push-broom mode with the spectrum performed by interferometry. While the satellite/aircraft is orbiting, the same source, seen from the satellite/aircraft, moves across the aperture and enters different MZIs, while adjacent sources enter adjacent MZIs at the same time. The on-chip spectrometer consists of 256 input mode converters, followed by 256 MZIs with linearly increasing optical path delays and a detector array. Multiple chips are stick together to form the 2D image surface and receive light from the imaging lens. Two MZI arrays are proposed, one works in wavelength ranging from 500nm to 900nm with SiON(refractive index 1.6) waveguides and another ranging from 1100nm to 1700nm with SOI platform. To meet the requirements of imaging spectrometer applications, we choose large cross-section ridge waveguide to achieve polarization insensitive, maintain single mode propagation in broad spectrum and increase production tolerance. The SiON on-chip spectrometer has a spectral resolution of 80cm-1 with a footprint of 17×15mm2 and the SOI based on-chip spectrometer has a resolution of 38cm-1 with a size of 22×19mm2. The spectral and space resolution of the imaging spectrometer can be further improved by simply adding more MZIs. The on-chip waveguide MZI array based Fourier transform imaging spectrometer can provide a highly compact solution for remote sensing on unmanned aerial vehicles or satellites with advantages of small size, light weight, no moving parts and large input aperture.

Silicon photonics devices for metro applications

NASA Astrophysics Data System (ADS)

Fukuda, H.; Kikuchi, K.; Jizodo, M.; Kawamura, Y.; Takeda, K.; Honda, K.

2017-01-01

Digital coherent technology is considered an attractive way of realizing both high-speed metro links and long distance transmissions. In metro areas, there is a strong demand for a smaller, faster transceiver module. This demand is mainly driven by the rapidly increasing data center interconnection traffic, where transmission capacity per faceplane is a key feature. Therefore, optical integration technology is desired. Since compensation in digital coherent technology is performed in the electrical or digital domain, users can deal with those optics performances that are not compensated for digitally. This means using a new material that cannot provide perfect characteristics but that is suitable for miniaturization and integration is possible. Silicon photonics (SiPh) is considered an attractive technology that would enable the significant miniaturization of optical circuits and be capable of optical integration with high manufacturability. While SiPh-based devices have begun to be deployed for very short or short reach links on the basis of direct detection technology, their digital coherent applications have recently been investigated in view of their integration capability. This paper describes recent progress on SiPh-based integrated optical devices for high-speed digital coherent transceivers targeting metro links. An optical modulator and receiver with related circuits have been integrated into a single SiPh chip. TEC-free operation under non-hermetic conditions and the direct attachment of optical fibers have both been realized. Very thin and small packaging with sufficient performance has been demonstrated by using the SiPh chip co-packaged with high-speed ICs.

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

An amorphous silicon photodiode microfluidic chip to detect nanomolar quantities of HIV-1 virion infectivity factor.

PubMed

Vistas, Cláudia R; Soares, Sandra S; Rodrigues, Rogério M M; Chu, Virginia; Conde, João P; Ferreira, Guilherme N M

2014-08-07

A hydrogenated amorphous silicon (a-Si:H) photosensor was explored for the quantitative detection of a HIV-1 virion infectivity factor (Vif) at a detection limit in the single nanomolar range. The a-Si:H photosensor was coupled with a microfluidic channel that was functionalized with a recombinant single chain variable fragment antibody. The biosensor selectively recognizes HIV-1 Vif from human cell extracts.

Polarized electroluminescence from edge-emission organic light emitting devices

NASA Astrophysics Data System (ADS)

Ran, G. Z.; Jiang, D. F.

2011-01-01

We report the experimental observation and measurement of the polarized electroluminescence from an edge-emission Si based- organic light emitting device (OLED) with a Sm/Au or Sm/Ag cathode. Light collected from the OLED edge comes from the scattering of the surface plasmon polaritons (SPPs) at the device boundary. This experiment shows that such Si-OLED can be an electrically excited SPP source on a silicon chip for optical interconnect based on SPPs.

Lab-on-chip components for molecular detection

NASA Astrophysics Data System (ADS)

Adam, Tijjani; Dhahi, Th S.; Mohammed, Mohammed; Hashim, U.; Noriman, N. Z.; Dahham, Omar S.

2017-09-01

We successfully fabricated Lab on chip components and integrated for possible use in biomedical application. The sensor was fabricated by using conventional photolithography method integrated with PDMS micro channels for smooth delivery of sample to the sensing domain. The sensor was silanized and aminated with 3-Aminopropyl triethoxysilane (APTES) to functionalize the surface with biomolecules and create molecular binding chemistry. The resulting Si-O-Si- components were functionalized with oligonucleotides probe of HPV, which interacted with the single stranded HPV DNA target to create a field across on the device. The fabrication, immobilization and hybridization processes were characterized with current voltage (I-V) characterization (KEITHLEY, 6487). The sensor show selectivity for the HPV DNA target in a linear range from concentration 0.1 nM to 1 µM. This strategy presented a simple, rapid and sensitive platform for HPV detection and would become a powerful tool for pathogenic microorganisms screening in clinical diagnosis.

Non-duplicate polarization-diversity 8 × 8 Si-wire PILOSS switch integrated with polarization splitter-rotators.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2017-05-15

We demonstrate a fully integrated polarization-diversity 8 × 8 thermo-optic Si-wire switch that uses only a single path-independent insertion loss (PILOSS) switch matrix. All input/output ports of the PILOSS switch matrix are uniquely assigned for polarization diversity without switch duplication. To integrate polarization splitter-rotators on a chip, we propose a compact path-length-equalized polarization-diversity switch configuration. Polarization-dependent loss (PDL) and differential group delay (DGD) are minimized. The 8 × 8 switch is fabricated by the CMOS-compatible fabrication process on 300-mm diameter wafer and additional etching of upper cladding after dicing. The chip size is 7 × 10.5 mm 2 . A PDL of 2 dB and a DGD of 1.5 ps are achieved. The crosstalk in the worst-case scenario is -20 dB in the full C-band.

Ultrashort pulse laser dicing of thin Si wafers: the influence of laser-induced periodic surface structures on the backside breaking strength

NASA Astrophysics Data System (ADS)

Domke, Matthias; Egle, Bernadette; Piredda, Giovanni; Stroj, Sandra; Fasching, Gernot; Bodea, Marius; Schwarz, Elisabeth

2016-11-01

High power electronic chips are usually fabricated on about 50 µm thin Si wafers to improve heat dissipation. At these chip thicknesses mechanical dicing becomes challenging. Chippings may occur at the cutting edges, which reduce the mechanical stability of the die. Thermal load changes could then lead to sudden chip failure. Ultrashort pulsed lasers are a promising tool to improve the cutting quality, because thermal side effects can be reduced to a minimum. However, laser-induced periodic surface structures occur at the sidewalls and at the trench bottom during scribing. The goal of this study was to investigate the influence of these periodic structures on the backside breaking strength of the die. An ultrafast laser with a pulse duration of 380 fs and a wavelength of 1040 nm was used to cut a wafer into single chips. The pulse energy and the number of scans was varied. The cuts in the wafer were investigated using transmitted light microscopy, the sidewalls of the cut chips were investigated using scanning electron and confocal microscopy, and the breaking strength was evaluated using the 3-point bending test. The results indicated that periodic holes with a distance of about 20-30 µm were formed at the bottom of the trench, if the number of scans was set too low to completely cut the wafer; the wafer was only perforated. Mechanical breaking of the bridges caused 5 µm deep kerfs in the sidewall. These kerfs reduced the breaking strength at the backside of the chip to about 300 MPa. As the number of scans was increased, the bridges were ablated and the wafer was cut completely. Periodic structures were observed on the sidewall; the roughness was below 1 µm. The surface roughness remained on a constant level even when the number of scans was doubled. However, the periodic structures on the sidewall seemed to vanish and the probability to remove local flaws increases with the number of scans. As a consequence, the breaking strength was increased to about 700 MPa.

28Silicon Irradiation Impairs Contextual Fear Memory in B6D2F1 Mice.

PubMed

Raber, Jacob; Marzulla, Tessa; Stewart, Blair; Kronenberg, Amy; Turker, Mitchell S

2015-06-01

The space radiation environment consists of multiple species of charged particles, including (28)Si, (48)Ti and protons that may impact cognition, but their damaging effects have been poorly defined. In mouse studies, C57Bl6/J homozygous wild-type mice and genetic mutant mice on a C57Bl6/J background have typically been used for assessing effects of space radiation on cognition. In contrast, little is known about the radiation response of mice on a heterozygous background. Therefore, in the current study we tested the effects of (28)Si, (48)Ti and proton radiation on hippocampus-dependent contextual fear memory and hippocampus-independent cued fear memory in C57Bl6/J × DBA2/J F1 (B6D2F1) mice three months after irradiation. Contextual fear memory was impaired at a 1.6 Gy dose of (28)Si radiation, but not cued fear memory. (48)Ti or proton irradiation did not affect either type of memory. Based on earlier space radiation cognitive data in C57Bl6/J mice, these data highlight the importance of including different genetic backgrounds in studies aimed at assessing cognitive changes after exposure to space radiation.

Waveform digitization for high resolution timing detectors with silicon photomultipliers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ronzhin, A.; Albrow, M. G.; Los, S.

2012-03-01

The results of time resolution studies with silicon photomultipliers (SiPMs) read out with high bandwidth constant fraction discrimination electronics were presented earlier [1-3]. Here we describe the application of fast waveform digitization readout based on the DRS4 chip [4], a switched capacitor array (SCA) produced by the Paul Scherrer Institute, to further our goal of developing high time resolution detectors based on SiPMs. The influence of the SiPM signal shape on the time resolution was investigated. Different algorithms to obtain the best time resolution are described, and test beam results are presented.

Ring resonator based narrow-linewidth semiconductor lasers

NASA Technical Reports Server (NTRS)

Ksendzov, Alexander (Inventor)

2005-01-01

The present invention is a method and apparatus for using ring resonators to produce narrow linewidth hybrid semiconductor lasers. According to one embodiment of the present invention, the narrow linewidths are produced by combining the semiconductor gain chip with a narrow pass band external feedback element. The semi conductor laser is produced using a ring resonator which, combined with a Bragg grating, acts as the external feedback element. According to another embodiment of the present invention, the proposed integrated optics ring resonator is based on plasma enhanced chemical vapor deposition (PECVD) SiO.sub.2 /SiON/SiO.sub.2 waveguide technology.

Language Classification using N-grams Accelerated by FPGA-based Bloom Filters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacob, A; Gokhale, M

N-Gram (n-character sequences in text documents) counting is a well-established technique used in classifying the language of text in a document. In this paper, n-gram processing is accelerated through the use of reconfigurable hardware on the XtremeData XD1000 system. Our design employs parallelism at multiple levels, with parallel Bloom Filters accessing on-chip RAM, parallel language classifiers, and parallel document processing. In contrast to another hardware implementation (HAIL algorithm) that uses off-chip SRAM for lookup, our highly scalable implementation uses only on-chip memory blocks. Our implementation of end-to-end language classification runs at 85x comparable software and 1.45x the competing hardware design.

Temperature effects on metal-alumina-nitride-oxide-silicon memory operations

NASA Astrophysics Data System (ADS)

Padovani, Andrea; Larcher, Luca; Heh, Dawei; Bersuker, Gennadi; Della Marca, Vincenzo; Pavan, Paolo

2010-05-01

We present a detailed investigation of temperature effects on the operation of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. We show that not only retention but also program and erase operations are affected significantly by temperature. Using a large set of experimental data and simulations on a variety of TANOS stacks, we show that the temperature dependence of TANOS program and erase operations can be explained by accounting for that the alumina dielectric constant increases by 20%-25% over a 125 K temperature range.

Size-dependent single electron transfer and semi-metal-to-insulator transitions in molecular metal oxide electronics

NASA Astrophysics Data System (ADS)

Balliou, Angelika; Bouroushian, Mirtat; Douvas, Antonios M.; Skoulatakis, George; Kennou, Stella; Glezos, Nikos

2018-07-01

All-inorganic self-arranged molecular transition metal oxide hyperstructures based on polyoxometalate molecules (POMs) are fabricated and tested as electronically tunable components in emerging electronic devices. POM hyperstructures reveal great potential as charging nodes of tunable charging level for molecular memories and as enhancers of interfacial electron/hole injection for photovoltaic stacks. STM, UPS, UV–vis spectroscopy and AFM measurements show that this functionality stems from the films’ ability to structurally tune their HOMO–LUMO levels and electron localization length at room temperature. By adapting POM nanocluster size in solution, self-doping and current modulation of four orders of magnitude is monitored on a single nanocluster on SiO2 at voltages as low as 3 Volt. Structurally driven insulator-to-semi-metal transitions and size-dependent current regulation through single electron tunneling are demonstrated and examined with respect to the stereochemical and electronic structure of the molecular entities. This extends the value of self-assembly as a tool for correlation length and electronic properties tuning and demonstrate POM hyperstructures’ plausibility for on-chip molecular electronics operative at room temperature.

Size-dependent single electron transfer and semi-metal-to-insulator transitions in molecular metal oxide electronics.

PubMed

Balliou, Angelika; Bouroushian, Mirtat; Douvas, Antonios M; Skoulatakis, George; Kennou, Stella; Glezos, Nikos

2018-07-06

All-inorganic self-arranged molecular transition metal oxide hyperstructures based on polyoxometalate molecules (POMs) are fabricated and tested as electronically tunable components in emerging electronic devices. POM hyperstructures reveal great potential as charging nodes of tunable charging level for molecular memories and as enhancers of interfacial electron/hole injection for photovoltaic stacks. STM, UPS, UV-vis spectroscopy and AFM measurements show that this functionality stems from the films' ability to structurally tune their HOMO-LUMO levels and electron localization length at room temperature. By adapting POM nanocluster size in solution, self-doping and current modulation of four orders of magnitude is monitored on a single nanocluster on SiO 2 at voltages as low as 3 Volt. Structurally driven insulator-to-semi-metal transitions and size-dependent current regulation through single electron tunneling are demonstrated and examined with respect to the stereochemical and electronic structure of the molecular entities. This extends the value of self-assembly as a tool for correlation length and electronic properties tuning and demonstrate POM hyperstructures' plausibility for on-chip molecular electronics operative at room temperature.

Nanophotonic photon echo memory based on rare-earth-doped crystals

NASA Astrophysics Data System (ADS)

Zhong, Tian; Kindem, Jonathan; Miyazono, Evan; Faraon, Andrei; Caltech nano quantum optics Team

2015-03-01

Rare earth ions (REIs) are promising candidates for implementing solid-state quantum memories and quantum repeater devices. Their high spectral stability and long coherence times make REIs a good choice for integration in an on-chip quantum nano-photonic platform. We report the coupling of the 883 nm transition of Neodymium (Nd) to a Yttrium orthosilicate (YSO) photonic crystal nano-beam resonator, achieving Purcell enhanced spontaneous emission by 21 times and increased optical absorption. Photon echoes were observed in nano-beams of different doping concentrations, yielding optical coherence times T2 up to 80 μs that are comparable to unprocessed bulk samples. This indicates the remarkable coherence properties of Nd are preserved during nanofabrication, therefore opening the possibility of efficient on-chip optical quantum memories. The nano-resonator with mode volume of 1 . 6(λ / n) 3 was fabricated using focused ion beam, and a quality factor of 3200 was measured. Purcell enhanced absorption of 80% by an ensemble of ~ 1 × 106 ions in the resonator was measured, which fulfills the cavity impedance matching condition that is necessary to achieve quantum storage of photons with unity efficiency.

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

PubMed

Cho, Hwasuk; Son, Hyunwoo; Seong, Kihwan; Kim, Byungsub; Park, Hong-June; Sim, Jae-Yoon

2018-02-01

This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine. The IC is fabricated using 28-nm CMOS process and is verified in a three-layer network of encoder-decoder pair for training and recovery of images with two-dimensional pixels. With a dataset of 50 digits, the IC shows a normalized root mean square error of 0.078. Measured energy efficiencies are 4.46 pJ per synaptic operation for inference and 19.26 pJ per synaptic weight update for learning, respectively. The learning performance is also estimated by simulations if the proposed hardware architecture is extended to apply to a batch training of 60 000 MNIST datasets.

Memory and Spin Injection Devices Involving Half Metals

DOE PAGES

Shaughnessy, M.; Snow, Ryan; Damewood, L.; ...

2011-01-01

We suggest memory and spin injection devices fabricated with half-metallic materials and based on the anomalous Hall effect. Schematic diagrams of the memory chips, in thin film and bulk crystal form, are presented. Spin injection devices made in thin film form are also suggested. These devices do not need any external magnetic field but make use of their own magnetization. Only a gate voltage is needed. The carriers are 100% spin polarized. Memory devices may potentially be smaller, faster, and less volatile than existing ones, and the injection devices may be much smaller and more efficient than existing spin injectionmore » devices.« less

Internal filament modulation in low-dielectric gap design for built-in selector-less resistive switching memory application

NASA Astrophysics Data System (ADS)

Chen, Ying-Chen; Lin, Chih-Yang; Huang, Hui-Chun; Kim, Sungjun; Fowler, Burt; Chang, Yao-Feng; Wu, Xiaohan; Xu, Gaobo; Chang, Ting-Chang; Lee, Jack C.

2018-02-01

Sneak path current is a severe hindrance for the application of high-density resistive random-access memory (RRAM) array designs. In this work, we demonstrate nonlinear (NL) resistive switching characteristics of a HfO x /SiO x -based stacking structure as a realization for selector-less RRAM devices. The NL characteristic was obtained and designed by optimizing the internal filament location with a low effective dielectric constant in the HfO x /SiO x structure. The stacking HfO x /SiO x -based RRAM device as the one-resistor-only memory cell is applicable without needing an additional selector device to solve the sneak path issue with a switching voltage of ~1 V, which is desirable for low-power operating in built-in nonlinearity crossbar array configurations.

Electrical properties of a light-addressable microelectrode chip with high electrode density for extracellular stimulation and recording of excitable cells.

PubMed

Bucher, V; Brunner, B; Leibrock, C; Schubert, M; Nisch, W

2001-05-01

A light-addressable microelectrode chip with 3600 TiN electrodes was fabricated. Amorphous silicon (a-Si:H) serves as a photo conductor. The electrodes on the chip are addressed by a laser spot and electrical properties of the system are determined. DC measurements show a dark to bright dynamic of 10(6)-10(7). The AC impedance dynamic @ 1 kHz/100 mV and thus the signal-to-noise-ratio is determined to 60. This value is quite sufficient for electrophysiological measurements. For the first time, recordings from cardiac myocytes are reported using the principle of light-addressing. Measurements were done with a standard laser scan microscope (Zeiss LSM 410).

On-chip Mach-Zehnder interferometer for OCT systems

NASA Astrophysics Data System (ADS)

van Leeuwen, Ton G.; Akca, Imran B.; Angelou, Nikolaos; Weiss, Nicolas; Hoekman, Marcel; Leinse, Arne; Heideman, Rene G.

2018-04-01

By using integrated optics, it is possible to reduce the size and cost of a bulky optical coherence tomography (OCT) system. One of the OCT components that can be implemented on-chip is the interferometer. In this work, we present the design and characterization of a Mach-Zehnder interferometer consisting of the wavelength-independent splitters and an on-chip reference arm. The Si3N4 was chosen as the material platform as it can provide low losses while keeping the device size small. The device was characterized by using a home-built swept source OCT system. A sensitivity value of 83 dB, an axial resolution of 15.2 μm (in air) and a depth range of 2.5 mm (in air) were all obtained.

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

DTIC Science & Technology

2004-01-01

VCSEL requires placing the array far enough as to overlap the entire footprint of the signal beam in order to record the hologram. Therefore, these...hologram that self-focuses, due to phase -conjugation, on the array of detectors in the chip. VC A 10 m m 10 mm 18mm 16mm SEL RRAY OPTICAL MEMORY LOGIC...the VCSEL array , the chip and the optical material, and the requirements they have to meet for their use in the OPGA system. Section

Active matrix-based collection of airborne analytes: an analyte recording chip providing exposure history and finger print.

PubMed

Fang, Jun; Park, Se-Chul; Schlag, Leslie; Stauden, Thomas; Pezoldt, Jörg; Jacobs, Heiko O

2014-12-03

In the field of sensors that target the detection of airborne analytes, Corona/lens-based-collection provides a new path to achieve a high sensitivity. An active-matrix-based analyte collection approach referred to as "airborne analyte memory chip/recorder" is demonstrated, which takes and stores airborne analytes in a matrix to provide an exposure history for off-site analysis. © 2014 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Persistent Neuronal Firing in Primary Somatosensory Cortex in the Absence of Working Memory of Trial-Specific Features of the Sample Stimuli in a Haptic Working Memory Task

ERIC Educational Resources Information Center

Wang, Liping; Li, Xianchun; Hsiao, Steven S.; Bodner, Mark; Lenz, Fred; Zhou, Yong-Di

2012-01-01

Previous studies suggested that primary somatosensory (SI) neurons in well-trained monkeys participated in the haptic-haptic unimodal delayed matching-to-sample (DMS) task. In this study, 585 SI neurons were recorded in monkeys performing a task that was identical to that in the previous studies but without requiring discrimination and active…

A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories

DTIC Science & Technology

1989-02-01

frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form factors. The hardware consists of...generality for rendering curved surfaces, volume data, objects dcscri id with Constructive Solid Geometry, for rendering scenes using the radiosity ...f.aces and for computing a spherical radiosity lighting model (see Section 7.6). Custom Memory Chips \\ 208 bits x 128 pixels - Renderer Board ix p o a

The storage system of PCM based on random access file system

NASA Astrophysics Data System (ADS)

Han, Wenbing; Chen, Xiaogang; Zhou, Mi; Li, Shunfen; Li, Gezi; Song, Zhitang

2016-10-01

Emerging memory technologies such as Phase change memory (PCM) tend to offer fast, random access to persistent storage with better scalability. It's a hot topic of academic and industrial research to establish PCM in storage hierarchy to narrow the performance gap. However, the existing file systems do not perform well with the emerging PCM storage, which access storage medium via a slow, block-based interface. In this paper, we propose a novel file system, RAFS, to bring about good performance of PCM, which is built in the embedded platform. We attach PCM chips to the memory bus and build RAFS on the physical address space. In the proposed file system, we simplify traditional system architecture to eliminate block-related operations and layers. Furthermore, we adopt memory mapping and bypassed page cache to reduce copy overhead between the process address space and storage device. XIP mechanisms are also supported in RAFS. To the best of our knowledge, we are among the first to implement file system on real PCM chips. We have analyzed and evaluated its performance with IOZONE benchmark tools. Our experimental results show that the RAFS on PCM outperforms Ext4fs on SDRAM with small record lengths. Based on DRAM, RAFS is significantly faster than Ext4fs by 18% to 250%.

Si-rich SiNx based Kerr switch enables optical data conversion up to 12 Gbit/s

PubMed Central

Lin, Gong-Ru; Su, Sheng-Pin; Wu, Chung-Lun; Lin, Yung-Hsiang; Huang, Bo-Ji; Wang, Huai-Yung; Tsai, Cheng-Ting; Wu, Chih-I; Chi, Yu-Chieh

2015-01-01

Silicon photonic interconnection on chip is the emerging issue for next-generation integrated circuits. With the Si-rich SiNx micro-ring based optical Kerr switch, we demonstrate for the first time the wavelength and format conversion of optical on-off-keying data with a bit-rate of 12 Gbit/s. The field-resonant nonlinear Kerr effect enhances the transient refractive index change when coupling the optical data-stream into the micro-ring through the bus waveguide. This effectively red-shifts the notched dip wavelength to cause the format preserved or inversed conversion of data carried by the on-resonant or off-resonant probe, respectively. The Si quantum dots doped Si-rich SiNx strengthens its nonlinear Kerr coefficient by two-orders of magnitude higher than that of bulk Si or Si3N4. The wavelength-converted and cross-amplitude-modulated probe data-stream at up to 12-Gbit/s through the Si-rich SiNx micro-ring with penalty of −7 dB on transmission has shown very promising applicability to all-optical communication networks. PMID:25923653

Si-rich SiNx based Kerr switch enables optical data conversion up to 12 Gbit/s.

PubMed

Lin, Gong-Ru; Su, Sheng-Pin; Wu, Chung-Lun; Lin, Yung-Hsiang; Huang, Bo-Ji; Wang, Huai-Yung; Tsai, Cheng-Ting; Wu, Chih-I; Chi, Yu-Chieh

2015-04-29

Silicon photonic interconnection on chip is the emerging issue for next-generation integrated circuits. With the Si-rich SiNx micro-ring based optical Kerr switch, we demonstrate for the first time the wavelength and format conversion of optical on-off-keying data with a bit-rate of 12 Gbit/s. The field-resonant nonlinear Kerr effect enhances the transient refractive index change when coupling the optical data-stream into the micro-ring through the bus waveguide. This effectively red-shifts the notched dip wavelength to cause the format preserved or inversed conversion of data carried by the on-resonant or off-resonant probe, respectively. The Si quantum dots doped Si-rich SiNx strengthens its nonlinear Kerr coefficient by two-orders of magnitude higher than that of bulk Si or Si3N4. The wavelength-converted and cross-amplitude-modulated probe data-stream at up to 12-Gbit/s through the Si-rich SiNx micro-ring with penalty of -7 dB on transmission has shown very promising applicability to all-optical communication networks.

Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

NASA Astrophysics Data System (ADS)

Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; Del Giudice, Paolo

2015-10-01

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a ‘basin’ of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases.

Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems.

PubMed

Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; del Giudice, Paolo

2015-10-14

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a 'basin' of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases.

77 FR 58473 - Minimum Technical Standards for Class II Gaming Systems and Equipment

Federal Register 2010, 2011, 2012, 2013, 2014

2012-09-21

... as printed advertising material that cannot be validated directly by a voucher system. Critical... on that component. EPROM. Erasable Programmable Read Only Memory--a non-volatile storage chip or...

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Silicon-based silicon–germanium–tin heterostructure photonics

PubMed Central

Soref, Richard

2014-01-01

The wavelength range that extends from 1550 to 5000 nm is a new regime of operation for Si-based photonic and opto-electronic integrated circuits. To actualize the new chips, heterostructure active devices employing the ternary SiGeSn alloy are proposed in this paper. Foundry-based monolithic integration is described. Opportunities and challenges abound in creating laser diodes, optical amplifiers, light-emitting diodes, photodetectors, modulators, switches and a host of high-performance passive infrared waveguided components. PMID:24567479

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu

2012-01-01

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Suspended mid-infrared fiber-to-chip grating couplers for SiGe waveguides

NASA Astrophysics Data System (ADS)

Favreau, Julien; Durantin, Cédric; Fédéli, Jean-Marc; Boutami, Salim; Duan, Guang-Hua

2016-03-01

Silicon photonics has taken great importance owing to the applications in optical communications, ranging from short reach to long haul. Originally dedicated to telecom wavelengths, silicon photonics is heading toward circuits handling with a broader spectrum, especially in the short and mid-infrared (MIR) range. This trend is due to potential applications in chemical sensing, spectroscopy and defense in the 2-10 μm range. We previously reported the development of a MIR photonic platform based on buried SiGe/Si waveguide with propagation losses between 1 and 2 dB/cm. However the low index contrast of the platform makes the design of efficient grating couplers very challenging. In order to achieve a high fiber-to-chip efficiency, we propose a novel grating coupler structure, in which the grating is locally suspended in air. The grating has been designed with a FDTD software. To achieve high efficiency, suspended structure thicknesses have been jointly optimized with the grating parameters, namely the fill factor, the period and the grating etch depth. Using the Efficient Global Optimization (EGO) method we obtained a configuration where the fiber-to-waveguide efficiency is above 57 %. Moreover the optical transition between the suspended and the buried SiGe waveguide has been carefully designed by using an Eigenmode Expansion software. Transition efficiency as high as 86 % is achieved.

Study of in-situ formation of Fe-Mn-Si shape memory alloy welding seam by laser welding with filler powder

NASA Astrophysics Data System (ADS)

Ju, Heng; Lin, Chengxin; Liu, Zhijie; Zhang, Jiaqi

2018-08-01

To reduce the residual stresses and improve the mechanical properties of laser weldments, produced with the restrained mixing uniform design method, a Fe-Mn-Si shape memory alloy (SMA) welding seam was formed inside the 304 stainless steel by laser welding with powder filling. The mass fraction, shape memory effect, and phase composition of the welding seam was measured by SEM-EDS (photometric analyser), bending recovery method, and XRD, respectively. An optical microscope was used to observe the microstructure of the Fe-Mn-Si SMA welding seam by solid solution and pre-deformation treatment. Meanwhile, the mechanical properties (residual stress distribution, tensile strength, microhardness and fatigue strength) of the laser welded specimen with an Fe-Mn-Si SMA welding seam (experimental material) and a 304 stainless steel welding seam (contrast material) were measured by a tensile testing machine hole drilling method and full cycle bending fatigue test. The results show that Fe15Mn5Si12Cr6Ni SMA welding seam was formed in situ with shape memory effect and stress-induced γ → ε martensite phase transformation characteristic. The residual stress of the experimental material is lower than that of the contrast material. The former has larger tensile strength, longer elongation and higher microhardness than the latter has. The experimental material and contrast material possess 249 and 136 bending fatigue cycles at the strain of 6%, respectively. The mechanisms by which mechanical properties of the experimental material are strengthened includes (1) release of the residual stress inside the Fe-Mn-Si SMA welding seam due to the stress-induced γ → ε martensite phase transformation and (2) energy absorption and plastic slip restraint due to the deformations in martensite and reverse phase transformation.

Polarized photoluminescence of nc-Si–SiO{sub x} nanostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Michailovska, E. V.; Indutnyi, I. Z.; Shepeliavyi, P. E.

2016-01-15

The effect of photoluminescence polarization memory in nc-Si–SiO{sub x} light-emitting structures containing Si nanoparticles (nc-Si) in an oxide matrix is for the first time studied. The polarization properties of continuous and porous nanostructures passivated in HF vapors (or solutions) are studied. It is established that the polarization memory effect is manifested only after treatment of the structures in HF. The effect is also accompanied by a shift of the photoluminescence peak to shorter wavelengths and by a substantial increase in the photoluminescence intensity. It is found that, in anisotropic nc-Si–SiO{sub x} samples produced by oblique deposition in vacuum, the degreemore » of linear photoluminescence polarization in the sample plane exhibits a noticeable orientation dependence and correlates with the orientation of SiO{sub x} nanocolumns forming the structure of the porous layer. These effects are attributed to the transformation of symmetrically shaped Si nanoparticles into asymmetric elongated nc-Si particles upon etching in HF. In continuous layers, nc-Si particles are oriented randomly, whereas in porous structures, their preferential orientation coincides with the orientation of oxide nanocolumns.« less

Iridium Interfacial Stack - IrIS

NASA Technical Reports Server (NTRS)

Spry, David

2012-01-01

Iridium Interfacial Stack (IrIS) is the sputter deposition of high-purity tantalum silicide (TaSi2-400 nm)/platinum (Pt-200 nm)/iridium (Ir-200 nm)/platinum (Pt-200 nm) in an ultra-high vacuum system followed by a 600 C anneal in nitrogen for 30 minutes. IrIS simultaneously acts as both a bond metal and a diffusion barrier. This bondable metallization that also acts as a diffusion barrier can prevent oxygen from air and gold from the wire-bond from infiltrating silicon carbide (SiC) monolithically integrated circuits (ICs) operating above 500 C in air for over 1,000 hours. This TaSi2/Pt/Ir/Pt metallization is easily bonded for electrical connection to off-chip circuitry and does not require extra anneals or masking steps. There are two ways that IrIS can be used in SiC ICs for applications above 500 C: it can be put directly on a SiC ohmic contact metal, such as Ti, or be used as a bond metal residing on top of an interconnect metal. For simplicity, only the use as a bond metal is discussed. The layer thickness ratio of TaSi2 to the first Pt layer deposited thereon should be 2:1. This will allow Si from the TaSi2 to react with the Pt to form Pt2Si during the 600 C anneal carried out after all layers have been deposited. The Ir layer does not readily form a silicide at 600 C, and thereby prevents the Si from migrating into the top-most Pt layer during future anneals and high-temperature IC operation. The second (i.e., top-most) deposited Pt layer needs to be about 200 nm to enable easy wire bonding. The thickness of 200 nm for Ir was chosen for initial experiments; further optimization of the Ir layer thickness may be possible via further experimentation. Ir itself is not easily wire-bonded because of its hardness and much higher melting point than Pt. Below the iridium layer, the TaSi2 and Pt react and form desired Pt2Si during the post-deposition anneal while above the iridium layer remains pure Pt as desired to facilitate easy and strong wire-bonding to the SiC chip circuitry.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Highly efficient on-chip direct electronic-plasmonic transducers

NASA Astrophysics Data System (ADS)

Du, Wei; Wang, Tao; Chu, Hong-Son; Nijhuis, Christian A.

2017-10-01

Photonic elements can carry information with a capacity exceeding 1,000 times that of electronic components, but, due to the optical diffraction limit, these elements are large and difficult to integrate with modern-day nanoelectronics or upcoming packages, such as three-dimensional integrated circuits or stacked high-bandwidth memories1-3. Surface plasmon polaritons can be confined to subwavelength dimensions and can carry information at high speeds (>100 THz)4-6. To combine the small dimensions of nanoelectronics with the fast operating speed of optics via plasmonics, on-chip electronic-plasmonic transducers that directly convert electrical signals into plasmonic signals (and vice versa) are required. Here, we report electronic-plasmonic transducers based on metal-insulator-metal tunnel junctions coupled to plasmonic waveguides with high-efficiency on-chip generation, manipulation and readout of plasmons. These junctions can be readily integrated into existing technologies, and we thus believe that they are promising for applications in on-chip integrated plasmonic circuits.

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.

PubMed

Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck

2011-12-01

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

High-speed and on-chip graphene blackbody emitters for optical communications by remote heat transfer.

PubMed

Miyoshi, Yusuke; Fukazawa, Yusuke; Amasaka, Yuya; Reckmann, Robin; Yokoi, Tomoya; Ishida, Kazuki; Kawahara, Kenji; Ago, Hiroki; Maki, Hideyuki

2018-03-29

High-speed light emitters integrated on silicon chips can enable novel architectures for silicon-based optoelectronics, such as on-chip optical interconnects, and silicon photonics. However, conventional light sources based on compound semiconductors face major challenges for their integration with a silicon-based platform because of their difficulty of direct growth on a silicon substrate. Here we report ultra-high-speed (100-ps response time), highly integrated graphene-based on-silicon-chip blackbody emitters in the near-infrared region including telecommunication wavelength. Their emission responses are strongly affected by the graphene contact with the substrate depending on the number of graphene layers. The ultra-high-speed emission can be understood by remote quantum thermal transport via surface polar phonons of the substrates. We demonstrated real-time optical communications, integrated two-dimensional array emitters, capped emitters operable in air, and the direct coupling of optical fibers to the emitters. These emitters can open new routes to on-Si-chip, small footprint, and high-speed emitters for highly integrated optoelectronics and silicon photonics.

Silicon carbide transparent chips for compact atomic sensors

NASA Astrophysics Data System (ADS)

Huet, L.; Ammar, M.; Morvan, E.; Sarazin, N.; Pocholle, J.-P.; Reichel, J.; Guerlin, C.; Schwartz, S.

2017-11-01

Atom chips [1] are an efficient tool for trapping, cooling and manipulating cold atoms, which could open the way to a new generation of compact atomic sensors addressing space applications. This is in particular due to the fact that they can achieve strong magnetic field gradients near the chip surface, hence strong atomic confinement at moderate electrical power. However, this advantage usually comes at the price of reducing the optical access to the atoms, which are confined very close to the chip surface. We will report at the conference experimental investigations showing how these limits could be pushed farther by using an atom chip made of a gold microcircuit deposited on a single-crystal Silicon Carbide (SiC) substrate [2]. With a band gap energy value of about 3.2 eV at room temperature, the latter material is transparent at 780nm, potentially restoring quasi full optical access to the atoms. Moreover, it combines a very high electrical resistivity with a very high thermal conductivity, making it a good candidate for supporting wires with large currents without the need of any additional electrical insulation layer [3].

Interface traps and quantum size effects on the retention time in nanoscale memory devices

PubMed Central

2013-01-01

Based on the analysis of Poisson equation, an analytical surface potential model including interface charge density for nanocrystalline (NC) germanium (Ge) memory devices with p-type silicon substrate has been proposed. Thus, the effects of Pb defects at Si(110)/SiO2, Si(111)/SiO2, and Si(100)/SiO2 interfaces on the retention time have been calculated after quantum size effects have been considered. The results show that the interface trap density has a large effect on the electric field across the tunneling oxide layer and leakage current. This letter demonstrates that the retention time firstly increases with the decrease in diameter of NC Ge and then rapidly decreases with the diameter when it is a few nanometers. This implies that the interface defects, its energy distribution, and the NC size should be seriously considered in the aim to improve the retention time from different technological processes. The experimental data reported in the literature support the theoretical expectation. PMID:23984827

SiC Integrated Circuits for Power Device Drivers Able to Operate in Harsh Environments

NASA Astrophysics Data System (ADS)

Godignon, P.; Alexandru, M.; Banu, V.; Montserrat, J.; Jorda, X.; Vellvehi, M.; Schmidt, B.; Michel, P.; Millan, J.

2014-08-01

The currently developed SiC electronic devices are more robust to high temperature operation and radiation exposure damage than correspondingly rated Si ones. In order to integrate the existent SiC high power and high temperature electronics into more complex systems, a SiC integrated circuit (IC) technology capable of operation at temperatures substantially above the conventional ones is required. Therefore, this paper is a step towards the development of ICs-control electronics that have to attend the harsh environment power applications. Concretely, we present the development of SiC MESFET-based digital circuitry, able to integrate gate driver for SiC power devices. Furthermore, a planar lateral power MESFET is developed with the aim of its co-integration on the same chip with the previously mentioned SiC digital ICs technology. And finally, experimental results on SiC Schottky-gated devices irradiated with protons and electrons are presented. This development is based on the Tungsten-Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo.

Narrow bandgap semiconducting silicides: Intrinsic infrared detectors on a silicon chip

NASA Technical Reports Server (NTRS)

Mahan, John E.

1989-01-01

Polycrystalline thin films of CrSi2, LaSi2, and ReSi2 were grown on silicon substrates. Normal incidence optical transmittance and reflectance measurements were made as a function of wavelength. It was demonstrated that LaSi2 is a metallic conductor, but that CrSi2 and ReSi2 are, in fact, narrow bandgap semiconductors. For CrSi2, the complex index of refraction was determined by computer analysis of the optical data. From the imaginary part, the optical absorption coefficient was determined as a function of photon energy. It was shown that CrSi2 possesses an indirect forbidden energy gap of slightly less than 0.31 eV, and yet it is a very strong absorber of light above the absorption edge. On the other hand, the ReSi2 films exhibit an absorption edge in the vicinity of 0.2 eV. Measurements of the thermal activation energy of resistivity for ReSi2 indicate a bandgap of 0.18 eV. It is concluded that the semiconducting silicides merit further investigation for development as new silicon-compatible infrared detector materials.

Photoisomerization-induced manipulation of single-electron tunneling for novel Si-based optical memory.

PubMed

Hayakawa, Ryoma; Higashiguchi, Kenji; Matsuda, Kenji; Chikyow, Toyohiro; Wakayama, Yutaka

2013-11-13

We demonstrated optical manipulation of single-electron tunneling (SET) by photoisomerization of diarylethene molecules in a metal-insulator-semiconductor (MIS) structure. Stress is placed on the fact that device operation is realized in the practical device configuration of MIS structure and that it is not achieved in structures based on nanogap electrodes and scanning probe techniques. Namely, this is a basic memory device configuration that has the potential for large-scale integration. In our device, the threshold voltage of SET was clearly modulated as a reversible change in the molecular orbital induced by photoisomerization, indicating that diarylethene molecules worked as optically controllable quantum dots. These findings will allow the integration of photonic functionality into current Si-based memory devices, which is a unique feature of organic molecules that is unobtainable with inorganic materials. Our proposed device therefore has enormous potential for providing a breakthrough in Si technology.

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-10-01

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

Tailored surface-enhanced Raman nanopillar arrays fabricated by laser-assisted replication for biomolecular detection using organic semiconductor lasers.

PubMed

Liu, Xin; Lebedkin, Sergei; Besser, Heino; Pfleging, Wilhelm; Prinz, Stephan; Wissmann, Markus; Schwab, Patrick M; Nazarenko, Irina; Guttmann, Markus; Kappes, Manfred M; Lemmer, Uli

2015-01-27

Organic semiconductor distributed feedback (DFB) lasers are of interest as external or chip-integrated excitation sources in the visible spectral range for miniaturized Raman-on-chip biomolecular detection systems. However, the inherently limited excitation power of such lasers as well as oftentimes low analyte concentrations requires efficient Raman detection schemes. We present an approach using surface-enhanced Raman scattering (SERS) substrates, which has the potential to significantly improve the sensitivity of on-chip Raman detection systems. Instead of lithographically fabricated Au/Ag-coated periodic nanostructures on Si/SiO2 wafers, which can provide large SERS enhancements but are expensive and time-consuming to fabricate, we use low-cost and large-area SERS substrates made via laser-assisted nanoreplication. These substrates comprise gold-coated cyclic olefin copolymer (COC) nanopillar arrays, which show an estimated SERS enhancement factor of up to ∼ 10(7). The effect of the nanopillar diameter (60-260 nm) and interpillar spacing (10-190 nm) on the local electromagnetic field enhancement is studied by finite-difference-time-domain (FDTD) modeling. The favorable SERS detection capability of this setup is verified by using rhodamine 6G and adenosine as analytes and an organic semiconductor DFB laser with an emission wavelength of 631.4 nm as the external fiber-coupled excitation source.

640 X 480 MOS PtSi IR sensor

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1991-12-01

The design of a 1st and 2nd generation 640(H) X 480(V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. Measured performance characteristics for Gen 1 devices are presented along with calculated performance for the Gen 2 design. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non- interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS170 operation) resulting in a form of 'electronic shutter,' or variable exposure control. The pixel size of 24-micrometers X 24-micrometers results in a fill factor of 38% for 1.5-micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

78 FR 75362 - Notice of Issuance of Final Determination Concerning Docave Computer Software

Federal Register 2010, 2011, 2012, 2013, 2014

2013-12-11

... in whole or in part of materials from another country or instrumentality, it has been substantially... programming of a foreign PROM (Programmable Read-Only Memory chip) in the United States substantially...

75 FR 44989 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-30

... following respondents: NVIDIA Corporation of Santa Clara, California; Asustek Computer, Inc. of Taipei... exclusion order and cease- and-desist orders against respondents NVIDIA Corp.; Hewlett-Packard Co.; ASUS...

Smart substrates: Making multi-chip modules smarter

NASA Astrophysics Data System (ADS)

Wunsch, T. F.; Treece, R. K.

1995-05-01

A novel multi-chip module (MCM) design and manufacturing methodology which utilizes active CMOS circuits in what is normally a passive substrate realizes the 'smart substrate' for use in highly testable, high reliability MCMS. The active devices are used to test the bare substrate, diagnose assembly errors or integrated circuit (IC) failures that require rework, and improve the testability of the final MCM assembly. A static random access memory (SRAM) MCM has been designed and fabricated in Sandia Microelectronics Development Laboratory in order to demonstrate the technical feasibility of this concept and to examine design and manufacturing issues which will ultimately determine the economic viability of this approach. The smart substrate memory MCM represents a first in MCM packaging. At the time the first modules were fabricated, no other company or MCM vendor had incorporated active devices in the substrate to improve manufacturability and testability, and thereby improve MCM reliability and reduce cost.

Threshold switching in SiGeAsTeN chalcogenide glass prepared by As ion implantation into sputtered SiGeTeN film

NASA Astrophysics Data System (ADS)

Liu, Guangyu; Wu, Liangcai; Song, Zhitang; Liu, Yan; Li, Tao; Zhang, Sifan; Song, Sannian; Feng, Songlin

2017-12-01

A memory cell composed of a selector device and a storage device is the basic unit of phase change memory. The threshold switching effect, main principle of selectors, is a universal phenomenon in chalcogenide glasses. In this work, we put forward a safe and controllable method to prepare a SiGeAsTeN chalcogenide film by implanting As ions into sputtered SiGeTeN films. For the SiGeAsTeN material, the phase structure maintains the amorphous state, even at high temperature, indicating that no phase transition occurs for this chalcogenide-based material. The electrical test results show that the SiGeAsTeN-based devices exhibit good threshold switching characteristics and the switching voltage decreases with the increasing As content. The decrease in valence alternation pairs, reducing trap state density, may be the physical mechanism for lower switch-on voltage, which makes the SiGeAsTeN material more applicable in selector devices through component optimization.

Evidences for vertical charge dipole formation in charge-trapping memories and its impact on reliability

NASA Astrophysics Data System (ADS)

Padovani, Andrea; Arreghini, Antonio; Vandelli, Luca; Larcher, Luca; bosch, Geert Van den; Houdt, Jan Van

2012-07-01

We demonstrate the formation of a vertical charge dipole in the nitride layer of TaN/Al2O3/Si3N4/SiO2/Si memories and use dedicated experiments and device simulations to investigate its dependence on program and erase conditions. We show that the polarity of the dipole depends on the program/erase operation sequence and demonstrate that it is at the origin of the charge losses observed during retention. This dipole severely affects the retention of mildly programmed and erased states, representing a serious reliability concern especially for multi-level applications.

E3 ligase CHIP and Hsc70 regulate Kv1.5 protein expression and function in mammalian cells.

PubMed

Li, Peili; Kurata, Yasutaka; Maharani, Nani; Mahati, Endang; Higaki, Katsumi; Hasegawa, Akira; Shirayoshi, Yasuaki; Yoshida, Akio; Kondo, Tatehito; Kurozawa, Youichi; Yamamoto, Kazuhiro; Ninomiya, Haruaki; Hisatome, Ichiro

2015-09-01

Kv1.5 confers ultra-rapid delayed-rectifier potassium channel current (IKur) which contributes to repolarization of the atrial action potential. Kv1.5 proteins, degraded via the ubiquitin-proteasome pathway, decreased in some atrial fibrillation patients. Carboxyl-terminus heat shock cognate 70-interacting protein (CHIP), an E3 ubiquitin ligase, is known to ubiquitinate short-lived proteins. Here, we investigated the roles of CHIP in Kv1.5 degradation to provide insights into the mechanisms of Kv1.5 decreases and treatments targeting Kv1.5 for atrial fibrillation. Coexpression of CHIP with Kv1.5 in HEK293 cells increased Kv1.5 protein ubiquitination and decreased the protein level. Immunofluorescence revealed decreases of Kv1.5 proteins in the endoplasmic reticulum and on the cell membrane. A siRNA against CHIP suppressed Kv1.5 protein ubiquitination and increased its protein level. CHIP mutants, lacking either the N-terminal tetratricopeptide region domain or the C-terminal U-box domain, failed to exert these effects on Kv1.5 proteins. Immunoprecipitation showed that CHIP formed complexes with Kv1.5 proteins and heat shock cognate protein 70 (Hsc70). Effects of Hsc70 on Kv1.5 were similar to CHIP by altering interaction of CHIP with Kv1.5 protein. Coexpression of CHIP and Hsc70 with Kv1.5 additionally enhanced Kv1.5 ubiquitination. Kv1.5 currents were decreased by overexpression of CHIP or Hsc70 but were increased by knockdown of CHIP or Hsc70 in HEK 293 cells stably expressing Kv1.5. These effects of CHIP and Hsc70 were also observed on endogenous Kv1.5 in HL-1 mouse cardiomyocytes, decreasing IKur and prolonging action potential duration. These results indicate that CHIP decreases the Kv1.5 protein level and functional channel by facilitating its degradation in concert with chaperone Hsc70. Copyright © 2015 Elsevier Ltd. All rights reserved.

GaN-on-Si blue/white LEDs: epitaxy, chip, and package

NASA Astrophysics Data System (ADS)

Qian, Sun; Wei, Yan; Meixin, Feng; Zengcheng, Li; Bo, Feng; Hanmin, Zhao; Hui, Yang

2016-04-01

The dream of epitaxially integrating III-nitride semiconductors on large diameter silicon is being fulfilled through the joint R&D efforts of academia and industry, which is driven by the great potential of GaN-on-silicon technology in improving the efficiency yet at a much reduced manufacturing cost for solid state lighting and power electronics. It is very challenging to grow high quality GaN on Si substrates because of the huge mismatch in the coefficient of thermal expansion (CTE) and the large mismatch in lattice constant between GaN and silicon, often causing a micro-crack network and a high density of threading dislocations (TDs) in the GaN film. Al-composition graded AlGaN/AlN buffer layers have been utilized to not only build up a compressive strain during the high temperature growth for compensating the tensile stress generated during the cool down, but also filter out the TDs to achieve crack-free high-quality n-GaN film on Si substrates, with an X-ray rocking curve linewidth below 300 arcsec for both (0002) and (101¯2) diffractions. Upon the GaN-on-Si templates, prior to the deposition of p-AlGaN and p-GaN layers, high quality InGaN/GaN multiple quantum wells (MQWs) are overgrown with well-engineered V-defects intentionally incorporated to shield the TDs as non-radiative recombination centers and to enhance the hole injection into the MQWs through the via-like structures. The as-grown GaN-on-Si LED wafers are processed into vertical structure thin film LED chips with a reflective p-electrode and the N-face surface roughened after the removal of the epitaxial Si(111) substrates, to enhance the light extraction efficiency. We have commercialized GaN-on-Si LEDs with an average efficacy of 150-160 lm/W for 1mm2 LED chips at an injection current of 350 mA, which have passed the 10000-h LM80 reliability test. The as-produced GaN-on-Si LEDs featured with a single-side uniform emission and a nearly Lambertian distribution can adopt the wafer-level phosphor coating procedure, and are suitable for directional lighting, camera flash, streetlighting, automotive headlamps, and otherlighting applications. Project supported financially by the National Natural Science Foundation of China (Nos. 61522407, 61534007, 61404156), the National High Technology Research and Development Program of China (No. 2015AA03A102), the Science & Technology Program of Jiangsu Province (Nos. BA2015099, BE2012063), the Suzhou Science & Technology Program (No. ZXG2013042), and the Recruitment Program of Global Experts (1000 Youth Talents Plan). Project also supported technically by Nano-X from SINANO, CAS

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.

2000-01-01

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

Video Bandwidth Compression System.

DTIC Science & Technology

1980-08-01

scaling function, located between the inverse DPCM and inverse transform , on the decoder matrix multiplier chips. 1"V1 T.. ---- i.13 SECURITY...Bit Unpacker and Inverse DPCM Slave Sync Board 15 e. Inverse DPCM Loop Boards 15 f. Inverse Transform Board 16 g. Composite Video Output Board 16...36 a. Display Refresh Memory 36 (1) Memory Section 37 (2) Timing and Control 39 b. Bit Unpacker and Inverse DPCM 40 c. Inverse Transform Processor 43

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Investigation of multilayer WS2 flakes as charge trapping stack layers in non-volatile memories

NASA Astrophysics Data System (ADS)

Wang, Hong; Ren, Deliang; Lu, Chao; Yan, Xiaobing

2018-06-01

In this study, the non-volatile flash memory devices utilize tungsten sulfide flakes as the charge trapping stack layers were fabricated. The sandwiched structure of Pd/ZHO/WS2/ZHO/WS2/SiO2/Si manifests a memory window of 2.26 V and a high density of trapped charges 4.88 × 1012/cm2 under a ±5 V gate sweeping voltage. Moreover, the data retention results of as-fabricated non-volatile memories demonstrate that the high and low capacitance states are enhanced by 3.81% and 3.11%, respectively, after a measurement duration of 1.20 × 104 s. These remarkable achievements are probably attributed to the defects and band gap of WS2 flakes. Besides, the proposed memory fabrication is not only compatible with CMOS manufacturing processes but also gets rid of the high-temperature annealing process. Overall, this proposed non-volatile memory is highly attractive for low voltage, long data retention applications.

Partition resampling and extrapolation averaging: approximation methods for quantifying gene expression in large numbers of short oligonucleotide arrays.

PubMed

Goldstein, Darlene R

2006-10-01

Studies of gene expression using high-density short oligonucleotide arrays have become a standard in a variety of biological contexts. Of the expression measures that have been proposed to quantify expression in these arrays, multi-chip-based measures have been shown to perform well. As gene expression studies increase in size, however, utilizing multi-chip expression measures is more challenging in terms of computing memory requirements and time. A strategic alternative to exact multi-chip quantification on a full large chip set is to approximate expression values based on subsets of chips. This paper introduces an extrapolation method, Extrapolation Averaging (EA), and a resampling method, Partition Resampling (PR), to approximate expression in large studies. An examination of properties indicates that subset-based methods can perform well compared with exact expression quantification. The focus is on short oligonucleotide chips, but the same ideas apply equally well to any array type for which expression is quantified using an entire set of arrays, rather than for only a single array at a time. Software implementing Partition Resampling and Extrapolation Averaging is under development as an R package for the BioConductor project.

Sub-micro-liter Electrochemical Single-Nucleotide-Polymorphism Detector for Lab-on-a-Chip System

NASA Astrophysics Data System (ADS)

Tanaka, Hiroyuki; Fiorini, Paolo; Peeters, Sara; Majeed, Bivragh; Sterken, Tom; de Beeck, Maaike Op; Hayashi, Miho; Yaku, Hidenobu; Yamashita, Ichiro

2012-04-01

A sub-micro-liter single-nucleotide-polymorphism (SNP) detector for lab-on-a-chip applications is developed. This detector enables a fast, sensitive, and selective SNP detection directly from human blood. The detector is fabricated on a Si substrate by a standard complementary metal oxide semiconductor/micro electro mechanical systems (CMOS/MEMS) process and Polydimethylsiloxane (PDMS) molding. Stable and reproducible measurements are obtained by implementing an on-chip Ag/AgCl electrode and encapsulating the detector. The detector senses the presence of SNPs by measuring the concentration of pyrophosphoric acid generated during selective DNA amplification. A 0.5-µL-volume detector enabled the successful performance of the typing of a SNP within the ABO gene using human blood. The measured sensitivity is 566 pA/µM.

Low-Yellowing Phosphor-in-Glass for High-Power Chip-on-board White LEDs by Optimizing a Low-Melting Sn-P-F-O Glass Matrix.

PubMed

Yoon, Hee Chang; Yoshihiro, Kouhara; Yoo, Heeyeon; Lee, Seung Woo; Oh, Ji Hye; Do, Young Rag

2018-05-09

We introduce a low-melting-point (MP) Sn-P-F-O glass ceramic material into the phosphor-in-glass (PIG) material to realize an 'on-chip' chip-on-board (COB) type of phosphor-converted (pc) white light-emitting diode (WLED) with green (BaSr) 2 SiO 4 :Eu 2+ and red (SrCa)AlSiN 3 :Eu 2+ (SCASN) phosphors. The optimum Sn-P-F-O-based ceramic components can be sintered into the glass phase with a facile one-step heating process at 285 °C for 1 min. Specifically, these soft-fabrication conditions can be optimized to minimize the degradation of the luminescent properties of the red SCASN phosphor as well as the green silicate phosphor in PIG-based white COB-type pc-LEDs owing to the low thermal loss of the phosphors at low fabrication temperatures below 300 °C. Moreover, the constituents of the COB package, in this case the wire bonding and plastic exterior, can be preserved simultaneously from thermal damage. That is, the low sintering temperature of the glass ceramic encapsulant is a very important factor to realize excellent optical qualities of white COB LEDs. The optical performances of low-MP Sn-P-F-O-based PIG on-chip COB-type pc-WLEDs exhibit low yellowing phenomena, good luminous efficacy of 70.9-86.0 lm/W, excellent color rendering index of 94-97 with correlated color temperatures from 2700 to 10000 K, and good long-term stability.

Formation of SiGe nanocrystals embedded in Al2O3 for the application of write-once-read-many-times memory

NASA Astrophysics Data System (ADS)

Wu, Min-Lin; Wu, Yung-Hsien; Lin, Chia-Chun; Chen, Lun-Lun

2012-10-01

The structure of SiGe nanocrystals embedded in Al2O3 formed by sequential deposition of Al2O3/Si/Ge/Al2O3 and a subsequent annealing was confirmed by transmission electron microscopy and energy dispersive spectroscopy (EDS), and its application for write-once-read-many-times (WORM) memory devices was explored in this study. By applying a -10 V pulse for 1 s, a large amount of holes injected from Si substrate are stored in the nanocrystals and consequently, the current at +1.5 V increases by a factor of 104 as compared to that of the initial state. Even with a smaller -5 V pulse for 1 μs, a sufficiently large current ratio of 36 can still be obtained, verifying the low power operation. Since holes are stored in nanocrystals which are isolated from Si substrate by Al2O3 with good integrity and correspond to a large valence band offset with respect to Al2O3, desirable read endurance up to 105 cycles and excellent retention over 100 yr are achieved. Combining these promising characteristics, WORM memory devices are appropriate for high-performance archival storage applications.

Cavity-Free, Matrix-Addressable Quantum Dot Architecture for On-Chip Optical Switching

DTIC Science & Technology

2013-04-01

or photo-induced bleaching. Given their intrinsically low IEP (~3, close to that of SiO2) they are ideal candidates for our electrostatic self...are currently investigating usage of our method on substrates with high IEPs such as Al2O3, Si3N4, and ITO. By using nanoparticle emitters with...intrinsically high IEPs , such as MgO nanocubes and ZnO nanocrystals, we can expand the range of applicability of our self-assembly technique. Personnel

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy

NASA Astrophysics Data System (ADS)

Gajek, M.; Nowak, J. J.; Sun, J. Z.; Trouilloud, P. L.; O'Sullivan, E. J.; Abraham, D. W.; Gaidis, M. C.; Hu, G.; Brown, S.; Zhu, Y.; Robertazzi, R. P.; Gallagher, W. J.; Worledge, D. C.

2012-03-01

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising emerging non-volatile memory technologies. MRAM has so far been demonstrated with a unique combination of density, speed, and non-volatility in a single chip, however, without the capability to replace any single mainstream memory. In this paper, we demonstrate the basic physics of spin torque switching in 20 nm diameter magnetic tunnel junctions with perpendicular magnetic anisotropy materials. This deep scaling capability clearly indicates the STT MRAM device itself may be suitable for integration at much higher densities than previously proven.

Citalopram Ameliorates Synaptic Plasticity Deficits in Different Cognition-Associated Brain Regions Induced by Social Isolation in Middle-Aged Rats.

PubMed

Gong, Wei-Gang; Wang, Yan-Juan; Zhou, Hong; Li, Xiao-Li; Bai, Feng; Ren, Qing-Guo; Zhang, Zhi-Jun

2017-04-01

Our previous experiments demonstrated that social isolation (SI) caused AD-like tau hyperphosphorylation and spatial memory deficits in middle-aged rats. However, the underlying mechanisms of SI-induced spatial memory deficits remain elusive. Middle-aged rats (10 months) were group or isolation reared for 8 weeks. Following the initial 4-week period of rearing, citalopram (10 mg/kg i.p.) was administered for 28 days. Then, pathophysiological changes were assessed by performing behavioral, biochemical, and pathological analyses. We found that SI could cause cognitive dysfunction and decrease synaptic protein (synaptophysin or PSD93) expression in different brain regions associated with cognition, such as the prefrontal cortex, dorsal hippocampus, ventral hippocampus, amygdala, and caudal putamen, but not in the entorhinal cortex or posterior cingulate. Citalopram could significantly improve learning and memory and partially restore synaptophysin or PSD93 expression in the prefrontal cortex, hippocampus, and amygdala in SI rats. Moreover, SI decreased the number of dendritic spines in the prefrontal cortex, dorsal hippocampus, and ventral hippocampus, which could be reversed by citalopram. Furthermore, SI reduced the levels of BDNF, serine-473-phosphorylated Akt (active form), and serine-9-phosphorylated GSK-3β (inactive form) with no significant changes in the levels of total GSK-3β and Akt in the dorsal hippocampus, but not in the posterior cingulate. Our results suggest that decreased synaptic plasticity in cognition-associated regions might contribute to SI-induced cognitive deficits, and citalopram could ameliorate these deficits by promoting synaptic plasticity mainly in the prefrontal cortex, dorsal hippocampus, and ventral hippocampus. The BDNF/Akt/GSK-3β pathway plays an important role in regulating synaptic plasticity in SI rats.

Storage Media for Microcomputers.

ERIC Educational Resources Information Center

Trautman, Rodes

1983-01-01

Reviews computer storage devices designed to provide additional memory for microcomputers--chips, floppy disks, hard disks, optical disks--and describes how secondary storage is used (file transfer, formatting, ingredients of incompatibility); disk/controller/software triplet; magnetic tape backup; storage volatility; disk emulator; and…

OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers

NASA Astrophysics Data System (ADS)

Kimura, Keiji; Mase, Masayoshi; Mikami, Hiroki; Miyamoto, Takamichi; Shirako, Jun; Kasahara, Hironori

OSCAR (Optimally Scheduled Advanced Multiprocessor) API has been designed for real-time embedded low-power multicores to generate parallel programs for various multicores from different vendors by using the OSCAR parallelizing compiler. The OSCAR API has been developed by Waseda University in collaboration with Fujitsu Laboratory, Hitachi, NEC, Panasonic, Renesas Technology, and Toshiba in an METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." By using the OSCAR API as an interface between the OSCAR compiler and backend compilers, the OSCAR compiler enables hierarchical multigrain parallel processing with memory optimization under capacity restriction for cache memory, local memory, distributed shared memory, and on-chip/off-chip shared memory; data transfer using a DMA controller; and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating for various embedded multicores. In addition, a parallelized program automatically generated by the OSCAR compiler with OSCAR API can be compiled by the ordinary OpenMP compilers since the OSCAR API is designed on a subset of the OpenMP. This paper describes the OSCAR API and its compatibility with the OSCAR compiler by showing code examples. Performance evaluations of the OSCAR compiler and the OSCAR API are carried out using an IBM Power5+ workstation, an IBM Power6 high-end SMP server, and a newly developed consumer electronics multicore chip RP2 by Renesas, Hitachi and Waseda. From the results of scalability evaluation, it is found that on an average, the OSCAR compiler with the OSCAR API can exploit 5.8 times speedup over the sequential execution on the Power5+ workstation with eight cores and 2.9 times speedup on RP2 with four cores, respectively. In addition, the OSCAR compiler can accelerate an IBM XL Fortran compiler up to 3.3 times on the Power6 SMP server. Due to low-power optimization on RP2, the OSCAR compiler with the OSCAR API achieves a maximum power reduction of 84% in the real-time execution mode.

High-throughput screening platform for engineered nanoparticle-mediated genotoxicity using CometChip technology.

PubMed

Watson, Christa; Ge, Jing; Cohen, Joel; Pyrgiotakis, Georgios; Engelward, Bevin P; Demokritou, Philip

2014-03-25

The likelihood of intentional and unintentional engineered nanoparticle (ENP) exposure has dramatically increased due to the use of nanoenabled products. Indeed, ENPs have been incorporated in many useful products and have enhanced our way of life. However, there are many unanswered questions about the consequences of nanoparticle exposures, in particular, with regard to their potential to damage the genome and thus potentially promote cancer. In this study, we present a high-throughput screening assay based upon the recently developed CometChip technology, which enables evaluation of single-stranded DNA breaks, abasic sites, and alkali-sensitive sites in cells exposed to ENPs. The strategic microfabricated, 96-well design and automated processing improves efficiency, reduces processing time, and suppresses user bias in comparison to the standard comet assay. We evaluated the versatility of this assay by screening five industrially relevant ENP exposures (SiO2, ZnO, Fe2O3, Ag, and CeO2) on both suspension human lymphoblastoid (TK6) and adherent Chinese hamster ovary (H9T3) cell lines. MTT and CyQuant NF assays were employed to assess cellular viability and proliferation after ENP exposure. Exposure to ENPs at a dose range of 5, 10, and 20 μg/mL induced dose-dependent increases in DNA damage and cytotoxicity. Genotoxicity profiles of ZnO>Ag>Fe2O3>CeO2>SiO2 in TK6 cells at 4 h and Ag>Fe2O3>ZnO>CeO2>SiO2 in H9T3 cells at 24 h were observed. The presented CometChip platform enabled efficient and reliable measurement of ENP-mediated DNA damage, therefore demonstrating the efficacy of this powerful tool in nanogenotoxicity studies.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the second six months of the Phase 2 of this project were to conduct first time experimental studies using optical designs and some initial hardware developed in the first 6 months of Phase 2. One focus is to modify the SiC chip optical properties to enable gas species sensing with a specific gas species under high temperature and pressure. The goal was to acquire sensing test data using two example inert and safe gases and show gas discrimination abilities. A high pressure gas mixing chamber was to be designed and assembled to achieve the mentioned gas sensingmore » needs. Another goal was to initiate high temperature probe design by developing and testing a probe design that leads to accurately measuring the thickness of the deployed SiC sensor chip to enable accurate overall sensor system design. The third goal of this phase of the project was to test the SiC chip under high pressure conditions using the earlier designed calibration cell to enable it to act as a pressure sensor when doing gas detection. In this case, experiments using a controlled pressure system were to deliver repeatable pressure measurement data. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the optical systems are provided. Photographs or schematics of the fabricated hardware are provided. Experimental data from the three optical sensor systems (i.e., Thickness, pressure, and gas species) is provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature high pressure gas species detection optical sensor technology.« less

A 16 x 16-pixel retinal-prosthesis vision chip with in-pixel digital image processing in a frequency domain by use of a pulse-frequency-modulation photosensor

NASA Astrophysics Data System (ADS)

Kagawa, Keiichiro; Furumiya, Tetsuo; Ng, David C.; Uehara, Akihiro; Ohta, Jun; Nunoshita, Masahiro

2004-06-01

We are exploring the application of pulse-frequency-modulation (PFM) photosensor to retinal prosthesis for the blind because behavior of PFM photosensors is similar to retinal ganglion cells, from which visual data are transmitted from the retina toward the brain. We have developed retinal-prosthesis vision chips that reshape the output pulses of the PFM photosensor to biphasic current pulses suitable for electric stimulation of retinal cells. In this paper, we introduce image-processing functions to the pixel circuits. We have designed a 16x16-pixel retinal-prosthesis vision chip with several kinds of in-pixel digital image processing such as edge enhancement, edge detection, and low-pass filtering. This chip is a prototype demonstrator of the retinal prosthesis vision chip applicable to in-vitro experiments. By utilizing the feature of PFM photosensor, we propose a new scheme to implement the above image processing in a frequency domain by digital circuitry. Intensity of incident light is converted to a 1-bit data stream by a PFM photosensor, and then image processing is executed by a 1-bit image processor based on joint and annihilation of pulses. The retinal prosthesis vision chip is composed of four blocks: a pixels array block, a row-parallel stimulation current amplifiers array block, a decoder block, and a base current generators block. All blocks except PFM photosensors and stimulation current amplifiers are embodied as digital circuitry. This fact contributes to robustness against noises and fluctuation of power lines. With our vision chip, we can control photosensitivity and intensity and durations of stimulus biphasic currents, which are necessary for retinal prosthesis vision chip. The designed dynamic range is more than 100 dB. The amplitude of the stimulus current is given by a base current, which is common for all pixels, multiplied by a value in an amplitude memory of pixel. Base currents of the negative and positive pulses are common for the all pixels, and they are set in a linear manner. Otherwise, the value in the amplitude memory of the pixel is presented in an exponential manner to cover the wide range. The stimulus currents are put out column by column by scanning. The pixel size is 240um x 240um. Each pixel has a bonding pad on which stimulus electrode is to be formed. We will show the experimental results of the test chip.

Testing Methods for Integrated Circuit Chips.

DTIC Science & Technology

1986-03-27

DWf <I IAV ~IMi MORY OUT LOGIC~~ IPOGRAM ASYC S’E4i E...* 16o, CO% T ROL CO%TROL 32 Figure 2 . 14 VLSI Tester Block Diagram. registers, memory and test...neral-pIurpos’ processor wi th standard bus- inte-rfaco se-rves as,- th- test control Ii’r and ( 2 ) a c-ustom VLSI test Controller inti-rfacing direc(_t1...Engineering 2 WTWTY ABSTRACT Provision for the functional testing of fabricated VLSI chips frequently involves as much design effort as the orig- _ inal

The Asian Semiconductor Industry and It’s Potential Impacts to U.S. National Security. Electronics Industry Study

DTIC Science & Technology

2007-01-01

late 1980s, Korean firms began to compete globally on memory chips, with Samsung earning a sales profit in 1987 (Pecht, 1997, p. 10; Mathews, 2000, p...competitive in the 1990s (Lee, 1997, p. 41). Singapore, Malaysia and China have since developed significant chip industries (Beane, 1997, p. 9; Pecht...sales in parentheses): #2 Samsung ($19.7B), #5 Toshiba ($9.8B), #6 TSMC ($9.7B), #7 Hynix ($8.0B) and #8 Renesas ($7.9B) (McGrath, 2007, p. 3

Ultralow power switching in a silicon-rich SiNy/SiNx double-layer resistive memory device.

PubMed

Kim, Sungjun; Chang, Yao-Feng; Kim, Min-Hwi; Bang, Suhyun; Kim, Tae-Hyeon; Chen, Ying-Chen; Lee, Jong-Ho; Park, Byung-Gook

2017-07-26

Here we demonstrate low-power resistive switching in a Ni/SiN y /SiN x /p ++ -Si device by proposing a double-layered structure (SiN y /SiN x ), where the two SiN layers have different trap densities. The LRS was measured to be as low as 1 nA at a voltage of 1 V, because the SiN x layer maintains insulating properties for the LRS. The single-layered device suffers from uncontrollability of the conducting path, accompanied by the inherent randomness of switching parameters, weak immunity to breakdown during the reset process, and a high operating current. On the other hand, for a double-layered device, the effective conducting path in each layer, which can determine the operating current, can be well controlled by the I CC during the initial forming and set processes. A one-step forming and progressive reset process is observed for a low-power mode, which differs from the high-power switching mode that shows a two-step forming and reset process. Moreover, nonlinear behavior in the LRS, whose origin can be attributed to the P-F conduction and F-N tunneling driven by abundant traps in the silicon-rich SiN x layer, would be beneficial for next-generation nonvolatile memory applications by using a conventional passive SiN x layer as an active dielectric.

Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction Transistor Measured

NASA Technical Reports Server (NTRS)

Niedra, Janis M.

2006-01-01

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter voltage (V(sub BE)) characteristic for thermometry. The V(sub BE) was measured as a function of the base current (I(sub B)) at selected temperatures (T), all at a fixed collector current (I(sub C)) and under very low duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat the chip, but same I(sub C) pulse height, the chip temperature was identified by matching the V(sub BE) to the thermometry curves. From the measured average power, the chip-to-case thermal resistance could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however, does not support this.

Oxygen Isotopes and Origin of Opal in an Antarctic Ureilite

NASA Astrophysics Data System (ADS)

Downes, H.; Beard, A. D.; Franchi, I. A.; Greenwood, R. C.

2016-08-01

Fragments of opal (SiO2.nH2O) in several internal chips of a single Antarctic polymict ureilite meteorite Elephant Moraine (EET) 83309 have been studied by NanoSIMS to determine their oxygen isotope compositions and hence constrain their origin.

Dynamically programmable cache

NASA Astrophysics Data System (ADS)

Nakkar, Mouna; Harding, John A.; Schwartz, David A.; Franzon, Paul D.; Conte, Thomas

1998-10-01

Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).

Chip-scale sensor system integration for portable health monitoring.

PubMed

Jokerst, Nan M; Brooke, Martin A; Cho, Sang-Yeon; Shang, Allan B

2007-12-01

The revolution in integrated circuits over the past 50 yr has produced inexpensive computing and communications systems that are powerful and portable. The technologies for these integrated chip-scale sensing systems, which will be miniature, lightweight, and portable, are emerging with the integration of sensors with electronics, optical systems, micromachines, microfluidics, and the integration of chemical and biological materials (soft/wet material integration with traditional dry/hard semiconductor materials). Hence, we stand at a threshold for health monitoring technology that promises to provide wearable biochemical sensing systems that are comfortable, inauspicious, wireless, and battery-operated, yet that continuously monitor health status, and can transmit compressed data signals at regular intervals, or alarm conditions immediately. In this paper, we explore recent results in chip-scale sensor integration technology for health monitoring. The development of inexpensive chip-scale biochemical optical sensors, such as microresonators, that are customizable for high sensitivity coupled with rapid prototyping will be discussed. Ground-breaking work in the integration of chip-scale optical systems to support these optical sensors will be highlighted, and the development of inexpensive Si complementary metal-oxide semiconductor circuitry (which makes up the vast majority of computational systems today) for signal processing and wireless communication with local receivers that lie directly on the chip-scale sensor head itself will be examined.

Vertically Integrated MEMS SOI Composite Porous Silicon-Crystalline Silicon Cantilever-Array Sensors: Concept for Continuous Sensing of Explosives and Warfare Agents

NASA Astrophysics Data System (ADS)

Stolyarova, Sara; Shemesh, Ariel; Aharon, Oren; Cohen, Omer; Gal, Lior; Eichen, Yoav; Nemirovsky, Yael

This study focuses on arrays of cantilevers made of crystalline silicon (c-Si), using SOI wafers as the starting material and using bulk micromachining. The arrays are subsequently transformed into composite porous silicon-crystalline silicon cantilevers, using a unique vapor phase process tailored for providing a thin surface layer of porous silicon on one side only. This results in asymmetric cantilever arrays, with one side providing nano-structured porous large surface, which can be further coated with polymers, thus providing additional sensing capabilities and enhanced sensing. The c-Si cantilevers are vertically integrated with a bottom silicon die with electrodes allowing electrostatic actuation. Flip Chip bonding is used for the vertical integration. The readout is provided by a sensitive Capacitance to Digital Converter. The fabrication, processing and characterization results are reported. The reported study is aimed towards achieving miniature cantilever chips with integrated readout for sensing explosives and chemical warfare agents in the field.

Improvement of Bipolar Switching Properties of Gd:SiOx RRAM Devices on Indium Tin Oxide Electrode by Low-Temperature Supercritical CO2 Treatment.

PubMed

Chen, Kai-Huang; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Liang, Shu-Ping; Young, Tai-Fa; Syu, Yong-En; Sze, Simon M

2016-12-01

Bipolar switching resistance behaviors of the Gd:SiO2 resistive random access memory (RRAM) devices on indium tin oxide electrode by the low-temperature supercritical CO2-treated technology were investigated. For physical and electrical measurement results obtained, the improvement on oxygen qualities, properties of indium tin oxide electrode, and operation current of the Gd:SiO2 RRAM devices were also observed. In addition, the initial metallic filament-forming model analyses and conduction transferred mechanism in switching resistance properties of the RRAM devices were verified and explained. Finally, the electrical reliability and retention properties of the Gd:SiO2 RRAM devices for low-resistance state (LRS)/high-resistance state (HRS) in different switching cycles were also measured for applications in nonvolatile random memory devices.

Magnetic Bubble Memories for Data Collection in Sounding Rockets,

DTIC Science & Technology

1982-01-29

generate interest in bubbles as a mass storage device for micro - processor based equipment, manufacturers have come up with a variety of diversified...absence of a bubble represents a Ŕ". With diameters on the order of I to 5 micro -meters, these bubbles are so small that extremely tiny chips can hold...methods of transfer: polled I/O, interrupt driven I/O, and direct memory access (DMA). The first two methods require tho host processor be involved

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 4, Appendix C

NASA Technical Reports Server (NTRS)

Klute, A.

1979-01-01

The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Statistical analysis data is supplied along with write pulse width, read cycle time, write cycle time, and chip enable time data.

Space Qualified High Speed Reed Solomon Encoder

NASA Technical Reports Server (NTRS)

Gambles, Jody W.; Winkert, Tom

1993-01-01

This paper reports a Class S CCSDS recommendation Reed Solomon encoder circuit baselined for several NASA programs. The chip is fabricated using United Technologies Microelectronics Center's UTE-R radiation-hardened gate array family, contains 64,000 p-n transistor pairs, and operates at a sustained output data rate of 200 MBits/s. The chip features a pin selectable message interleave depth of from 1 to 8 and supports output block lengths of 33 to 255 bytes. The UTE-R process is reported to produce parts that are radiation hardened to 16 Rads (Si) total dose and 1.0(exp -10) errors/bit-day.

Electromigration in solder joints and solder lines

NASA Astrophysics Data System (ADS)

Gan, H.; Choi, W. J.; Xu, G.; Tu, K. N.

2002-06-01

Electromigration may affect the reliability of flip-chip solder joints. Eutectic solder is a two-phase alloy, so its electromigration behavior is different from that in aluminum or copper interconnects. In addition, a flipchip solder joint has a built-in currentcrowding configuration to enhance electromigration failure. To better understand electromigration in SnPb and lead-free solder alloys, the authors prepared solder lines in v-grooves etched on Si (001). This article discusses the results of those tests and compares the electromigration failure modes of eutectic SnPb and SnAgCu flip-chip solder joints along with the mean-timeto-failure.

Simultaneous nanocalorimetry and fast XRD measurements to study the silicide formation in Pd/a-Si bilayers.

PubMed

Molina-Ruiz, Manel; Ferrando-Villalba, Pablo; Rodríguez-Tinoco, Cristian; Garcia, Gemma; Rodríguez-Viejo, Javier; Peral, Inma; Lopeandía, Aitor F

2015-05-01

The use of a membrane-based chip nanocalorimeter in a powder diffraction beamline is described. Simultaneous wide-angle X-ray scattering and scanning nanocalorimetric measurements are performed on a thin-film stack of palladium/amorphous silicon (Pd/a-Si) at heating rates from 0.1 to 10 K s(-1). The nanocalorimeter works under a power-compensation scheme previously developed by the authors. Kinetic and structural information of the consumed and created phases can be obtained from the combined techniques. The formation of Pd2Si produces a broad calorimetric peak that contains overlapping individual processes. It is shown that Pd consumption precedes the formation of the crystalline Pd2Si phase and that the crystallite size depends on the heating rate of the experiment.

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bender, Michael A.; Berry, Jonathan W.; Hammond, Simon D.

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” andmore » if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.« less

Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

PubMed Central

Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; del Giudice, Paolo

2015-01-01

Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a ‘basin’ of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases. PMID:26463272

Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements

NASA Astrophysics Data System (ADS)

Hayakawa, Hitoshi; Ogawa, Makoto; Shibata, Tadashi

2005-04-01

A very large scale integrated circuit (VLSI) architecture for a multiple-instruction-stream multiple-data-stream (MIMD) associative processor has been proposed. The processor employs an architecture that enables seamless switching from associative operations to arithmetic operations. The MIMD element is convertible to a regular central processing unit (CPU) while maintaining its high performance as an associative processor. Therefore, the MIMD associative processor can perform not only on-chip perception, i.e., searching for the vector most similar to an input vector throughout the on-chip cache memory, but also arithmetic and logic operations similar to those in ordinary CPUs, both simultaneously in parallel processing. Three key technologies have been developed to generate the MIMD element: associative-operation-and-arithmetic-operation switchable calculation units, a versatile register control scheme within the MIMD element for flexible operations, and a short instruction set for minimizing the memory size for program storage. Key circuit blocks were designed and fabricated using 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. As a result, the full-featured MIMD element is estimated to be 3 mm2, showing the feasibility of an 8-parallel-MIMD-element associative processor in a single chip of 5 mm× 5 mm.

High Sensitivity and High Detection Specificity of Gold-Nanoparticle-Grafted Nanostructured Silicon Mass Spectrometry for Glucose Analysis.

PubMed

Tsao, Chia-Wen; Yang, Zhi-Jie

2015-10-14

Desorption/ionization on silicon (DIOS) is a high-performance matrix-free mass spectrometry (MS) analysis method that involves using silicon nanostructures as a matrix for MS desorption/ionization. In this study, gold nanoparticles grafted onto a nanostructured silicon (AuNPs-nSi) surface were demonstrated as a DIOS-MS analysis approach with high sensitivity and high detection specificity for glucose detection. A glucose sample deposited on the AuNPs-nSi surface was directly catalyzed to negatively charged gluconic acid molecules on a single AuNPs-nSi chip for MS analysis. The AuNPs-nSi surface was fabricated using two electroless deposition steps and one electroless etching step. The effects of the electroless fabrication parameters on the glucose detection efficiency were evaluated. Practical application of AuNPs-nSi MS glucose analysis in urine samples was also demonstrated in this study.

High-performance, low-voltage electroosmotic pumps with molecularly thin silicon nanomembranes

PubMed Central

Snyder, Jessica L.; Getpreecharsawas, Jirachai; Fang, David Z.; Gaborski, Thomas R.; Striemer, Christopher C.; Fauchet, Philippe M.; Borkholder, David A.; McGrath, James L.

2013-01-01

We have developed electroosmotic pumps (EOPs) fabricated from 15-nm-thick porous nanocrystalline silicon (pnc-Si) membranes. Ultrathin pnc-Si membranes enable high electroosmotic flow per unit voltage. We demonstrate that electroosmosis theory compares well with the observed pnc-Si flow rates. We attribute the high flow rates to high electrical fields present across the 15-nm span of the membrane. Surface modifications, such as plasma oxidation or silanization, can influence the electroosmotic flow rates through pnc-Si membranes by alteration of the zeta potential of the material. A prototype EOP that uses pnc-Si membranes and Ag/AgCl electrodes was shown to pump microliter per minute-range flow through a 0.5-mm-diameter capillary tubing with as low as 250 mV of applied voltage. This silicon-based platform enables straightforward integration of low-voltage, on-chip EOPs into portable microfluidic devices with low back pressures. PMID:24167263

Integration of GaAs-based VCSEL array on SiN platform with HCG reflectors for WDM applications

NASA Astrophysics Data System (ADS)

Kumari, Sulakshna; Gustavsson, Johan S.; Wang, Ruijun; Haglund, Emanuel P.; Westbergh, Petter; Sanchez, Dorian; Haglund, Erik; Haglund, Åsa; Bengtsson, Jörgen; Le Thomas, Nicolas; Roelkens, Gunther; Larsson, Anders; Baets, Roel

2015-02-01

We present a GaAs-based VCSEL structure, BCB bonded to a Si3N4 waveguide circuit, where one DBR is substituted by a free-standing Si3N4 high-contrast-grating (HCG) reflector realized in the Si3N4 waveguide layer. This design enables solutions for on-chip spectroscopic sensing, and the dense integration of 850-nm WDM data communication transmitters where individual channel wavelengths are set by varying the HCG parameters. RCWA shows that a 300nm-thick Si3N4 HCG with 800nm period and 40% duty cycle reflects strongly (<99%) over a 75nm wavelength range around 850nm. A design with a standing-optical-field minimum at the III-V/airgap interface maximizes the HCG's influence on the VCSEL wavelength, allowing for a 15-nm-wide wavelength setting range with low threshold gain (<1000 cm-1).

Micromirror structure based on TiNi shape memory thin films

NASA Astrophysics Data System (ADS)

Fu, Yong Qing; Hu, Min; Du, Hejun; Luo, Jack; Flewitt, Andrew J.; Milne, William I.

2005-02-01

TiNi films were deposited on silicon by co-sputtering TiNi target and a separate Ti target at a temperature of 450°C. Results from differential scanning calorimeter, in-situ X-ray diffraction and curvature measurement revealed clearly martensitic transformation upon heating and cooling. Two types of TiNi/Si optical micromirror structures with a Si mirror cap (20 micron thick) and TiNi/Si actuation beams were designed and fabricated. For the first design, three elbow shaped Si beams with TiNi electrodes were used as the arms to actuate the mirror. In the second design, a V-shaped cantilever based on TiNi/Si bimorph beams was used as the actuation mechanism for micromirror. TiNi electrodes were patterned and wet-etched in a solutions of HF:HNO3:H2O (1:1:20) with an etch rate of 0.6 μm/min. The TiNi/Si microbeams were flat at room temperature, and bent up with applying voltage in TiNi electrodes (due to phase transformation and shape memory effect), thus causing the changes in angles of micromirror.

Nonvolatile and Cryogenic-compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Nonvolatile and Cryogenic-Compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Note: A component-level frequency tunable isolator for vibration-sensitive chips using SMA beams.

PubMed

Zhang, Xiaoyong; Ding, Xin; Wu, Di; Qi, Junlei; Wang, Ruixin; Lu, Siwei; Yan, Xiaojun

2016-06-01

This note presents a component-level frequency tunable isolator for vibration-sensitive chips. The isolator employed 8 U-shaped shape memory alloy (SMA) beams to support an isolation island (used for mounting chips). Due to the temperature-induced Young's modulus variation of SMA, the system stiffness of the isolator can be controlled through heating the SMA beams. In such a way, the natural frequency of the isolator can be tuned. A prototype was fabricated to evaluate the concept. The test results show that the natural frequency of the isolator can be tuned in the range of 64 Hz-97 Hz by applying different heating strategies. Moreover, resonant vibration can be suppressed significantly (the transmissibility decreases about 65% near the resonant frequency) using a real-time tuning method.

Channel length dependence of field-effect mobility of c-axis-aligned crystalline In-Ga-Zn-O field-effect transistors

NASA Astrophysics Data System (ADS)

Matsuda, Shinpei; Kikuchi, Erumu; Yamane, Yasumasa; Okazaki, Yutaka; Yamazaki, Shunpei

2015-04-01

Field-effect transistors (FETs) with c-axis-aligned crystalline In-Ga-Zn-O (CAAC-IGZO) active layers have extremely low off-state leakage current. Exploiting this feature, we investigated the application of CAAC-IGZO FETs to LSI memories. A high on-state current is required for the high-speed operation of these LSI memories. The field-effect mobility μFE of a CAAC-IGZO FET is relatively low compared with the electron mobility of single-crystal Si (sc-Si). In this study, we measured and calculated the channel length L dependence of μFE for CAAC-IGZO and sc-Si FETs. For CAAC-IGZO FETs, μFE remains almost constant, particularly when L is longer than 0.3 µm, whereas that of sc-Si FETs decreases markedly as L shortens. Thus, the μFE difference between both FET types is reduced by miniaturization. This difference in μFE behavior is attributed to the different susceptibilities of electrons to phonon scattering. On the basis of this result and the extremely low off-state leakage current of CAAC-IGZO FETs, we expect high-speed LSI memories with low power consumption.

Unlabeled multi tumor marker detection system based on bioinitiated light addressable potentiometric sensor.

PubMed

Jia, Yun-Fang; Gao, Chun-Ying; He, Jia; Feng, Dao-Fu; Xing, Ke-Li; Wu, Ming; Liu, Yang; Cai, Wen-Sheng; Feng, Xi-Zeng

2012-08-21

Multi biomarkers' assays are of great significance in clinical diagnosis. A label-free multi tumor markers' parallel detection system was proposed based on a light addressable potentiometric sensor (LAPS). Arrayed LAPS chips with basic structure of Si(3)N(4)-SiO(2)-Si were prepared on silicon wafers, and the label-free parallel detection system for this component was developed with user friendly controlling interfaces. Then the l-3,4-dihydroxyphenyl-alanine (L-Dopa) hydrochloric solution was used to initiate the surface of LAPS. The L-Dopa immobilization state was investigated by the theoretical calculation. L-Dopa initiated LAPS' chip was biofunctionalized respectively by the antigens and antibodies of four tumor markers, α-fetoprotein (AFP), carcinoembryonic antigen (CEA), cancer antigen 19-9 (CA19-9) and Ferritin. Then unlabeled antibodies and antigens of these four biomarkers were detected by the proposed detection systems. Furthermore physical and measuring principles in this system were described, and qualitative understanding for experimental data were given. The measured response ranges were compared with their clinical cutoff values, and sensitivities were calculated by OriginLab. The results indicate that this bioinitiated LAPS based label-free detection system may offer a new choice for the realization of unlabeled multi tumor markers' clinical assay.

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

NASA Astrophysics Data System (ADS)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

PubMed Central

Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Priya, Shashank

2015-01-01

We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~106 s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology. PMID:25683062

Sequential roles of primary somatosensory cortex and posterior parietal cortex in tactile-visual cross-modal working memory: a single-pulse transcranial magnetic stimulation (spTMS) study.

PubMed

Ku, Yixuan; Zhao, Di; Hao, Ning; Hu, Yi; Bodner, Mark; Zhou, Yong-Di

2015-01-01

Both monkey neurophysiological and human EEG studies have shown that association cortices, as well as primary sensory cortical areas, play an essential role in sequential neural processes underlying cross-modal working memory. The present study aims to further examine causal and sequential roles of the primary sensory cortex and association cortex in cross-modal working memory. Individual MRI-based single-pulse transcranial magnetic stimulation (spTMS) was applied to bilateral primary somatosensory cortices (SI) and the contralateral posterior parietal cortex (PPC), while participants were performing a tactile-visual cross-modal delayed matching-to-sample task. Time points of spTMS were 300 ms, 600 ms, 900 ms after the onset of the tactile sample stimulus in the task. The accuracy of task performance and reaction time were significantly impaired when spTMS was applied to the contralateral SI at 300 ms. Significant impairment on performance accuracy was also observed when the contralateral PPC was stimulated at 600 ms. SI and PPC play sequential and distinct roles in neural processes of cross-modal associations and working memory. Copyright © 2015 Elsevier Inc. All rights reserved.

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

PubMed

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

2016-07-25

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

Silicon-based horizontal nanoplasmonic slot waveguides for on-chip integration.

PubMed

Zhu, Shiyang; Liow, T Y; Lo, G Q; Kwong, D L

2011-04-25

Horizontal metal/insulator/Si/insulator/metal nanoplasmonic slot waveguide (PWG), which is inserted in a conventional Si wire waveguide, is fabricated using the standard Si-CMOS technology. A thin insulator between the metal and the Si core plays a key role: it not only increases the propagation distance as the theoretical prediction, but also prevents metal diffusion and/or metal-Si reaction. Cu-PWGs with the Si core width of ~134-21 nm and ~12-nm-thick SiO2 on each side exhibit a relatively low propagation loss of ~0.37-0.63 dB/µm around the telecommunication wavelength of 1550 nm, which is ~2.6 times smaller than the Al-counterparts. A simple tapered coupler can provide an effective coupling between the PWG and the conventional Si wire waveguide. The coupling efficiency as high as ~0.1-0.4 dB per facet is measured. The PWG allows a sharp bending. The pure bending loss of a Cu-PWG direct 90° bend is measured to be ~0.6-1.0 dB. These results indicate the potential for seamless integration of various functional nanoplasmonic devices in existing Si electronic photonic integrated circuits (Si-EPICs).

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

High Density Memory Based on Quantum Device Technology

NASA Technical Reports Server (NTRS)

vanderWagt, Paul; Frazier, Gary; Tang, Hao

1995-01-01

We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.

Electronic shift register memory based on molecular electron-transfer reactions

NASA Technical Reports Server (NTRS)

Hopfield, J. J.; Onuchic, Jose Nelson; Beratan, David N.

1989-01-01

The design of a shift register memory at the molecular level is described in detail. The memory elements are based on a chain of electron-transfer molecules incorporated on a very large scale integrated (VLSI) substrate, and the information is shifted by photoinduced electron-transfer reactions. The design requirements for such a system are discussed, and several realistic strategies for synthesizing these systems are presented. The immediate advantage of such a hybrid molecular/VLSI device would arise from the possible information storage density. The prospect of considerable savings of energy per bit processed also exists. This molecular shift register memory element design solves the conceptual problems associated with integrating molecular size components with larger (micron) size features on a chip.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Optical pumping of deep traps in AlGaN/GaN-on-Si HEMTs using an on-chip Schottky-on-heterojunction light-emitting diode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Baikui; Tang, Xi; Chen, Kevin J., E-mail: eekjchen@ust.hk

2015-03-02

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoH-LED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The de-trapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance R{sub on} and/or threshold voltage V{sub th} of the HEMT. The results show that the recovery processes ofmore » both dynamic R{sub on} and threshold voltage V{sub th} of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs.« less

Novel 3D micromirror for miniature optical bio-robe SiOB assembly

NASA Astrophysics Data System (ADS)

Singh, Janak; Xu, Yingshun; Premachandran, C. S.; Jason, Teo Hui Siang; Chen, Nanguang

2008-02-01

This article presents design and development of a novel 3D micromirror for large deflection scanning application in invivo optical coherence tomography (OCT) bio-imaging probe. Overall mirror chip size is critical to reduce the diameter of the probe; however, mirror plate itself should not be less than 500 μm as smaller size means reducing the amount of light collected after scattering for OCT imaging. In this study, mirror chip sizes of 1 × 1 mm2 and 1.5 × 1.5 mm2 were developed with respectively 400 and 500 micrometer diameter mirror plates. The design includes electro thermal excitation mechanism in the same plane as mirror plate to achieve 3D free space scanning. Larger deflection requires longer actuators, which usually increase the overall size of the chip. To accommodate longer actuators and keep overall chip size same curved beam actuators are designed and integrated for micromirror scanning. Typical length of the actuators was 800 micrometer, which provided up to 17 degrees deflection. Deep reactive ion etching (DRIE) process module was used extensively to etch high aspect ratio structures and keep the total mirror chip size small.

In situ monitoring using Lab on Chip devices, with particular reference to dissolved silica.

NASA Astrophysics Data System (ADS)

Turner, G. S. C.; Loucaides, S.; Slavik, G. J.; Owsianka, D. R.; Beaton, A.; Nightingale, A.; Mowlem, M. C.

2016-02-01

In situ sensors are attractive alternatives to discrete sampling of natural waters, offering the potential for sustained long term monitoring and eliminating the need for sample handling. This can reduce sample contamination and degradation. In addition, sensors can be clustered into multi-parameter observatories and networked to provide both spatial and time series coverage. High resolution, low cost, and long term monitoring are the biggest advantages of these technologies to oceanographers. Microfluidic technology miniaturises bench-top assay systems into portable devices, known as a `lab on a chip' (LOC). The principle advantages of this technology are low power consumption, simplicity, speed, and stability without compromising on quality (accuracy, precision, selectivity, sensitivity). We have successfully demonstrated in situ sensors based on this technology for the measurement of pH, nitrate and nitrite. Dissolved silica (dSi) is an important macro-nutrient supporting a major fraction of oceanic primary production carried out by diatoms. The biogeochemical Si cycle is undergoing significant modifications due to human activities, which affects availability of dSi, and consequently primary production. Monitoring dSi concentrations is therefore critical in increasing our understanding of the biogeochemical Si cycle to predict and manage anthropogenic perturbations. The standard bench top air segmented flow technique utilising the reduction of silicomolybdic acid with spectrophotometric detection has been miniaturised into a LOC system; the target limit of detection is 1 nM, with ± 5% accuracy and 3% precision. Results from the assay optimisation are presented along with reagent shelf life to demonstrate the robustness of the chemistry. Laboratory trials of the sensor using ideal solutions and environmental samples in environmentally relevant conditions (temperature, pressure) are discussed, along with an overview of our current LOC analytical capabilities.

Circuit quantum electrodynamics architecture for gate-defined quantum dots in silicon

NASA Astrophysics Data System (ADS)

Mi, X.; Cady, J. V.; Zajac, D. M.; Stehlik, J.; Edge, L. F.; Petta, J. R.

2017-01-01

We demonstrate a hybrid device architecture where the charge states in a double quantum dot (DQD) formed in a Si/SiGe heterostructure are read out using an on-chip superconducting microwave cavity. A quality factor Q = 5400 is achieved by selectively etching away regions of the quantum well and by reducing photon losses through low-pass filtering of the gate bias lines. Homodyne measurements of the cavity transmission reveal DQD charge stability diagrams and a charge-cavity coupling rate g c / 2 π = 23 MHz. These measurements indicate that electrons trapped in a Si DQD can be effectively coupled to microwave photons, potentially enabling coherent electron-photon interactions in silicon.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Effects of AAV-mediated knockdown of nNOS and GPx-1 gene expression in rat hippocampus after traumatic brain injury.

PubMed

Boone, Deborah R; Leek, Jeanna M; Falduto, Michael T; Torres, Karen E O; Sell, Stacy L; Parsley, Margaret A; Cowart, Jeremy C; Uchida, Tatsuo; Micci, Maria-Adelaide; DeWitt, Douglas S; Prough, Donald S; Hellmich, Helen L

2017-01-01

Virally mediated RNA interference (RNAi) to knock down injury-induced genes could improve functional outcome after traumatic brain injury (TBI); however, little is known about the consequences of gene knockdown on downstream cell signaling pathways and how RNAi influences neurodegeneration and behavior. Here, we assessed the effects of adeno-associated virus (AAV) siRNA vectors that target two genes with opposing roles in TBI pathogenesis: the allegedly detrimental neuronal nitric oxide synthase (nNOS) and the potentially protective glutathione peroxidase 1 (GPx-1). In rat hippocampal progenitor cells, three siRNAs that target different regions of each gene (nNOS, GPx-1) effectively knocked down gene expression. However, in vivo, in our rat model of fluid percussion brain injury, the consequences of AAV-siRNA were variable. One nNOS siRNA vector significantly reduced the number of degenerating hippocampal neurons and showed a tendency to improve working memory. GPx-1 siRNA treatment did not alter TBI-induced neurodegeneration or working memory deficits. Nevertheless, microarray analysis of laser captured, virus-infected neurons showed that knockdown of nNOS or GPx-1 was specific and had broad effects on downstream genes. Since nNOS knockdown only modestly ameliorated TBI-induced working memory deficits, despite widespread genomic changes, manipulating expression levels of single genes may not be sufficient to alter functional outcome after TBI.

Formation of SiGe nanocrystals embedded in Al{sub 2}O{sub 3} for the application of write-once-read-many-times memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Min-Lin; Wu, Yung-Hsien; Lin, Chia-Chun

2012-10-15

The structure of SiGe nanocrystals embedded in Al{sub 2}O{sub 3} formed by sequential deposition of Al{sub 2}O{sub 3}/Si/Ge/Al{sub 2}O{sub 3} and a subsequent annealing was confirmed by transmission electron microscopy and energy dispersive spectroscopy (EDS), and its application for write-once-read-many-times (WORM) memory devices was explored in this study. By applying a -10 V pulse for 1 s, a large amount of holes injected from Si substrate are stored in the nanocrystals and consequently, the current at +1.5 V increases by a factor of 10{sup 4} as compared to that of the initial state. Even with a smaller -5 V pulsemore » for 1 {mu}s, a sufficiently large current ratio of 36 can still be obtained, verifying the low power operation. Since holes are stored in nanocrystals which are isolated from Si substrate by Al{sub 2}O{sub 3} with good integrity and correspond to a large valence band offset with respect to Al{sub 2}O{sub 3}, desirable read endurance up to 10{sup 5} cycles and excellent retention over 100 yr are achieved. Combining these promising characteristics, WORM memory devices are appropriate for high-performance archival storage applications.« less

Resistive switching mechanism in the one diode-one resistor memory based on p+-Si/n-ZnO heterostructure revealed by in-situ TEM

NASA Astrophysics Data System (ADS)

Zhang, Lei; Zhu, Liang; Li, Xiaomei; Xu, Zhi; Wang, Wenlong; Bai, Xuedong

2017-03-01

One diode-one resistor (1D1R) memory is an effective architecture to suppress the crosstalk interference, realizing the crossbar network integration of resistive random access memory (RRAM). Herein, we designed a p+-Si/n-ZnO heterostructure with 1D1R function. Compared with the conventional multilayer 1D1R devices, the structure and fabrication technique can be largely simplified. The real-time imaging of formation/rupture process of conductive filament (CF) process demonstrated the RS mechanism by in-situ transmission electron microscopy (TEM). Meanwhile, we observed that the formed CF is only confined to the outside of depletion region of Si/ZnO pn junction, and the formation of CF does not degrade the diode performance, which allows the coexistence of RS and rectifying behaviors, revealing the 1D1R switching model. Furthermore, it has been confirmed that the CF is consisting of the oxygen vacancy by in-situ TEM characterization.

Capacitorless 1T-DRAM on crystallized poly-Si TFT.

PubMed

Kim, Min Soo; Cho, Won Ju

2011-07-01

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

A Manufacturing Cost and Supply Chain Analysis of SiC Power Electronics Applicable to Medium-Voltage Motor Drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horowitz, Kelsey; Remo, Timothy; Reese, Samantha

Wide bandgap (WBG) semiconductor devices are increasingly being considered for use in certain power electronics applications, where they can improve efficiency, performance, footprint, and, potentially, total system cost compared to systems using traditional silicon (Si) devices. Silicon carbide (SiC) devices in particular -- which are currently more mature than other WBG devices -- are poised for growth in the coming years. Today, the manufacturing of SiC wafers is concentrated in the United States, and chip production is split roughly equally between the United States, Japan, and Europe. Established contract manufacturers located throughout Asia typically carry out manufacturing of WBG powermore » modules. We seek to understand how global manufacturing of SiC components may evolve over time by illustrating the regional cost drivers along the supply chain and providing an overview of other factors that influence where manufacturing is sited. We conduct this analysis for a particular case study where SiC devices are used in a medium-voltage motor drive.« less

Simultaneous ultra-long data retention and low power based on Ge10Sb90/SiO2 multilayer thin films

NASA Astrophysics Data System (ADS)

You, Haipeng; Hu, Yifeng; Zhu, Xiaoqin; Zou, Hua; Song, Sannian; Song, Zhitang

2018-02-01

In this article, Ge10Sb90/SiO2 multilayer thin films were prepared to improve thermal stability and data retention for phase change memory. Compared with Ge10Sb90 monolayer thin film, Ge10Sb90 (1 nm)/SiO2 (9 nm) multilayer thin film had higher crystallization temperature and resistance contrast between amorphous and crystalline states. Annealed Ge10Sb90 (1 nm)/SiO2 (9 nm) had uniform grain with the size of 15.71 nm. After annealing, the root-mean-square surface roughness for Ge10Sb90 (1 nm)/SiO2 (9 nm) thin film increased slightly from 0.45 to 0.53 nm. The amorphization time for Ge10Sb90 (1 nm)/SiO2 (9 nm) thin film (2.29 ns) is shorter than Ge2Sb2Te5 (3.56 ns). The threshold voltage of a cell based on Ge10Sb90 (1 nm)/SiO2 (9 nm) (3.57 V) was smaller than GST (4.18 V). The results indicated that Ge10Sb90/SiO2 was a promising phase change thin film with high thermal ability and low power consumption for phase change memory application.

A novel yellow-emitting SrAlSi{sub 4}N{sub 7}:Ce{sup 3+} phosphor for solid state lighting: Synthesis, electronic structure and photoluminescence properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ruan, Jian; Laboratory of Glasses and Nanostructured Functional Materials, 122 Luoshi Road, Wuhan, Hubei 430070; Xie, Rong-Jun, E-mail: Xie.Rong-Jun@nims.go.jp

2013-12-15

Ce{sup 3+}-doped and Ce{sup 3+}/Li{sup +}-codoped SrAlSi{sub 4}N{sub 7} phosphors were synthesized by gas pressure sintering of powder mixtures of Sr{sub 3}N{sub 2}, AlN, α-Si{sub 3}N{sub 4}, CeN and Li{sub 3}N. The phase purity, electronic crystal structure, photoluminescence properties of SrAlSi{sub 4}N{sub 7}:Ce{sup 3+}(Ce{sup 3+}/Li{sup +}) were investigated in this work. The band structure calculated by the DMol{sup 3} code shows that SrAlSi{sub 4}N{sub 7} has a direct band gap of 3.87 eV. The single crystal analysis of Ce{sup 3+}-doped SrAlSi{sub 4}N{sub 7} indicates a disordered Si/Al distribution and nitrogen vacnacy defects. SrAlSi{sub 4}N{sub 7} was identified as a majormore » phase of the fired powders, and Sr{sub 5}Al{sub 5}Si{sub 21}N{sub 35}O{sub 2} and AlN as minor phases. Both Ce{sup 3+} and Ce{sup 3+}/Li{sup +} doped SrAlSi{sub 4}N{sub 7} phosphors can be efficiently excited by near-UV or blue light and show a broadband yellow emission peaking around 565 nm. A highest external quantum efficiency of 38.3% under the 450 nm excitation was observed for the Ce{sup 3+}/Li{sup +}-doped SrAlSi{sub 4}N{sub 7} (5 mol%). A white light LED lamp with color temperature of 6300 K and color rendering index of Ra=78 was achieved by combining Sr{sub 0.97}Al{sub 1.03}Si{sub 3.997}N/94/maccounttest14=t0005{sub 1}8193 {sub 7}:Ce{sup 3+}{sub 0.03} with a commercial blue InGaN chip. It indicates that SrAlSi{sub 4}N{sub 7}:Ce{sup 3+} is a promising yellow emitting down-conversion phosphor for white LEDs. - Graphical abstract: One-phosphor converted white light-emitting diode (LED) was fabricated by combining a blue LED chip and a yellow-emitting SrAlSi4N7:Ce{sup 3+} phosphor (see inset), which has the color rendering index of 78 and color temperature of 6300 K. - Highlights: • We reported a new yellow nitride phosphor suitable for solid state lighting. • We solved the crystal structure and evidenced a disordered Si/Al distribution. • We fabricated a high color rendering white LEDs by using a single SrAlSi4N7:Ce.« less

640 X 480 PtSi MOS infrared imager

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1992-09-01

The design and performance of a 640 (H) X 480 (V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. The imager achieves an NEDT equals 0.10 K at 30 Hz frame rates with f/1.5 optics (300 K background). The MOS design provides a measured saturation level of 1.5 X 10(superscript 6) electrons (5 V bias) and a noise floor of 300 rms electrons per pixel. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non-interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS 170 operation) resulting in `electronic shutter' variable exposure control. The pixel size of 24 micrometers X 24 micrometers results in a fill factor of 38% for 1.5 micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

InP on SOI devices for optical communication and optical network on chip

NASA Astrophysics Data System (ADS)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

On-chip broadband ultra-compact optical couplers and polarization splitters based on off-centered and non-symmetric slotted Si-wire waveguides

NASA Astrophysics Data System (ADS)

Haldar, Raktim; Mishra, V.; Dutt, Avik; Varshney, Shailendra K.

2016-10-01

In this work, we propose novel schemes to design on-chip ultra-compact optical directional couplers (DC) and broadband polarization beam splitters (PBS) based on off-centered and asymmetric dielectric slot waveguides, respectively. Slot dimensions and positions are optimized to achieve maximum coupling coefficients between two symmetric and non-symmetric slotted Si wire waveguides through overlap integral method. We observe >88% of enhancement in the coupling coefficients when the size-optimized slots are placed in optimal positions, with respect to the same waveguides with no slot. When the waveguides are parallel, in that case, a coupling length as short as 1.73 μm is accomplished for TM mode with the off-centered and optimized slots. This scheme enables us to design optical DC with very small footprint, L c ∼ 0.9 μm in the presence of S-bends. We also report a compact (L c ∼ 1.1 μm) on-chip broadband PBS with hybrid slots. Extinction ratios of 13 dB and 22.3 dB are realized with very low insertion loss (0.055 dB and 0.008 dB) for TM and TE modes at 1.55 μm, respectively. The designed PBS exhibits a bandwidth of 78 nm for the TM mode (C-and partial L-bands) and >100 nm for the TE mode (S + C + L wavelength bands). Such on-chip devices can be used to design compact photonic interconnects and quantum information processing units efficiently. We have also investigated the fabrication tolerances of the proposed devices and described the fabrication steps to realize such hybrid devices. Our results are in good agreement with 3D FDTD simulations.

Design and Characterization of a Sensorized Microfluidic Cell-Culture System with Electro-Thermal Micro-Pumps and Sensors for Cell Adhesion, Oxygen, and pH on a Glass Chip.

PubMed

Bonk, Sebastian M; Stubbe, Marco; Buehler, Sebastian M; Tautorat, Carsten; Baumann, Werner; Klinkenberg, Ernst-Dieter; Gimsa, Jan

2015-07-30

We combined a multi-sensor glass-chip with a microfluidic channel grid for the characterization of cellular behavior. The grid was imprinted in poly-dimethyl-siloxane. Mouse-embryonal/fetal calvaria fibroblasts (MC3T3-E1) were used as a model system. Thin-film platinum (Pt) sensors for respiration (amperometric oxygen electrode), acidification (potentiometric pH electrodes) and cell adhesion (interdigitated-electrodes structures, IDES) allowed us to monitor cell-physiological parameters as well as the cell-spreading behavior. Two on-chip electro-thermal micro-pumps (ETμPs) permitted the induction of medium flow in the system, e.g., for medium mixing and drug delivery. The glass-wafer technology ensured the microscopic observability of the on-chip cell culture. Connecting Pt structures were passivated by a 1.2 μm layer of silicon nitride (Si3N4). Thin Si3N4 layers (20 nm or 60 nm) were used as the sensitive material of the pH electrodes. These electrodes showed a linear behavior in the pH range from 4 to 9, with a sensitivity of up to 39 mV per pH step. The oxygen sensors were circular Pt electrodes with a sensor area of 78.5 μm(2). Their sensitivity was 100 pA per 1% oxygen increase in the range from 0% to 21% oxygen (air saturated). Two different IDES geometries with 30- and 50-μm finger spacings showed comparable sensitivities in detecting the proliferation rate of MC3T3 cells. These cells were cultured for 11 days in vitro to test the biocompatibility, microfluidics and electric sensors of our system under standard laboratory conditions.

Performance of defect-tolerant set-associative cache memories

NASA Technical Reports Server (NTRS)

Frenzel, J. F.

1991-01-01

The increased use of on-chip cache memories has led researchers to investigate their performance in the presence of manufacturing defects. Several techniques for yield improvement are discussed and results are presented which indicate that set-associativity may be used to provide defect tolerance as well as improve the cache performance. Tradeoffs between several cache organizations and replacement strategies are investigated and it is shown that token-based replacement may be a suitable alternative to the widely-used LRU strategy.

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

DTIC Science & Technology

2007-06-01

requires a significant deviation from previous work. For instance, we find that using the relaxed input replication model from Reunion incurs a...Circuit Width Delay Count CRC-16 16 6.65 754 CRC- SDLC -16 16 6.10 888 CRC-32 16 7.28 2260 CRC-32 32 8.60 4240 Table 1. FO4 delay and transistor count for...the operation of our proposed system is the same in all other respects. 4.4 Compatibility Across Memory Consis- tency Models The memory consistency

Using Ant Colony Optimization for Routing in VLSI Chips

NASA Astrophysics Data System (ADS)

Arora, Tamanna; Moses, Melanie

2009-04-01

Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. A frequent problem in the design of such high performance and high density VLSI layouts is that of routing wires that connect such large numbers of components. Most wire-routing problems are computationally hard. The quality of any routing algorithm is judged by the extent to which it satisfies routing constraints and design objectives. Some of the broader design objectives include minimizing total routed wire length, and minimizing total capacitance induced in the chip, both of which serve to minimize power consumed by the chip. Ant Colony Optimization algorithms (ACO) provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We found that ACO algorithms were able to successfully incorporate multiple constraints and route interconnects on suite of benchmark chips. On an average, the algorithm routed with total wire length 5.5% less than other established routing algorithms.

Long-term memory color investigation: culture effect and experimental setting factors.

PubMed

Zhu, Yuteng; Luo, Ming Ronnier; Fischer, Sebastian; Bodrogi, Peter; Khanh, Tran Quoc

2017-10-01

Memory colors generated continuous interest in the color community. Previous studies focused on reflecting color chips and color samples in real scenes or on monitors. The cognitive effect of culture was rarely considered. In this paper, we performed a comprehensive investigation of the long-term memory colors of 26 familiar objects using the asymmetric color matching method among Chinese and German observers on a display. Three experiments were conducted to evaluate the variations introduced by culture, context-based gray image, and initial matching color. Memory colors of important objects were collected and representative memory colors were quantified in terms of CIELAB L * , a * , and b * values. The intra- and inter-observer variations were analyzed by mean-color-difference-from-mean values and chromatic ellipses. The effects of different cultural groups and experimental settings were also shown.

A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy

NASA Astrophysics Data System (ADS)

Han, Runze; Shen, Wensheng; Huang, Peng; Zhou, Zheng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

2018-04-01

A novel ternary content addressable memory (TCAM) design based on resistive random access memory (RRAM) is presented. Each TCAM cell consists of two parallel RRAM to both store and search for ternary data. The cell size of the proposed design is 8F2, enable a ∼60× cell area reduction compared with the conventional static random access memory (SRAM) based implementation. Simulation results also show that the search delay and energy consumption of the proposed design at the 64-bit word search are 2 ps and 0.18 fJ/bit/search respectively at 22 nm technology node, where significant improvements are achieved compared to previous works. The desired characteristics of RRAM for implementation of the high performance TCAM search chip are also discussed.

Integrated Vertical Bloch Line (VBL) memory

NASA Technical Reports Server (NTRS)

Katti, R. R.; Wu, J. C.; Stadler, H. L.

1991-01-01

Vertical Bloch Line (VBL) Memory is a recently conceived, integrated, solid state, block access, VLSI memory which offers the potential of 1 Gbit/sq cm areal storage density, data rates of hundreds of megabits/sec, and submillisecond average access time simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBLs are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of BVL pairs are used to store binary information. At present, efforts are being directed at developing a single chip memory using 25 Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. The current design architecture, functional elements, and supercomputer simulation results are described which are used to assist the design process.

Microstructures, Martensitic Transformation, and Mechanical Behavior of Rapidly Solidified Ti-Ni-Hf and Ti-Ni-Si Shape Memory Alloys

NASA Astrophysics Data System (ADS)

Han, X. L.; Song, K. K.; Zhang, L. M.; Xing, H.; Sarac, B.; Spieckermann, F.; Maity, T.; Mühlbacher, M.; Wang, L.; Kaban, I.; Eckert, J.

2018-03-01

In this work, the microstructure and mechanical properties of rapidly solidified Ti50- x/2Ni50- x/2Hf x ( x = 0, 2, 4, 6, 8, 10, and 12 at.%) and Ti50- y/2Ni50- y/2Si y ( y = 1, 2, 3, 5, 7, and 10 at.%) shape memory alloys (SMAs) were investigated. The sequence of the phase formation and transformations in dependence on the chemical composition is established. Rapidly solidified Ti-Ni-Hf or Ti-Ni-Si SMAs are found to show relatively high yield strength and large ductility for specific Hf or Si concentrations, which is due to the gradual disappearance of the phase transformation from austenite to twinned martensite and the predominance of the phase transformation from twinned martensite to detwinned martensite during deformation as well as to the refinement of dendrites and the precipitation of brittle intermetallic compounds.

Nitrided SrTiO3 as charge-trapping layer for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Huang, X. D.; Lai, P. T.; Liu, L.; Xu, J. P.

2011-06-01

Charge-trapping characteristics of SrTiO3 with and without nitrogen incorporation were investigated based on Al/Al2O3/SrTiO3/SiO2/Si (MONOS) capacitors. A Ti-silicate interlayer at the SrTiO3/SiO2 interface was confirmed by x-ray photoelectron spectroscopy and transmission electron microscopy. Compared with the MONOS capacitor with SrTiO3 as charge-trapping layer (CTL), the one with nitrided SrTiO3 showed a larger memory window (8.4 V at ±10 V sweeping voltage), higher P/E speeds (1.8 V at 1 ms +8 V) and better retention properties (charge loss of 38% after 104 s), due to the nitrided SrTiO3 film exhibiting higher dielectric constant, higher deep-level traps induced by nitrogen incorporation, and suppressed formation of Ti silicate between the CTL and SiO2 by nitrogen passivation.

A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor

DTIC Science & Technology

2015-07-21

biosensor. The insets show a magnified view of the SiNW channel region (W = 55 nm). ( c ) Photograph of the biosensor chip fabricated via a top-down method...of the SiNW FET is 147 mV/decade. (b) VT and ( c ) ISINW at different pH levels; these values were extracted from Fig. 2a. VT was extracted using the...function of pH level in the hybrid biosensor. The extracted current change is 5.5 × 105 (=5.74 decade per pH). ( c ) Transient response of IMOSFET while

Midinfrared wavelength conversion in hydrogenated amorphous silicon waveguides

NASA Astrophysics Data System (ADS)

Wang, Jiang; Wang, Zhaolu; Huang, Nan; Han, Jing; Li, Yongfang; Liu, Hongjun

2017-10-01

Midinfrared (MIR) wavelength conversion based on degenerate four-wave mixing is theoretically investigated in hydrogenated amorphous silicon (a-Si:H) waveguides. The broadband phase mismatch is achieved in the normal group-velocity dispersion regime. The conversion bandwidth is extended to 900 nm, and conversion efficiency of up to -14 dB with a pump power of 70 mW in a 2-mm long a-Si:H rib waveguides is obtained. This low-power on-chip wavelength converter will have potential for application in a wide range of MIR nonlinear optic devices.

Electronic p-Chip-Based System for Identification of Glass Slides and Tissue Cassettes in Histopathology Laboratories.

PubMed

Mandecki, Wlodek; Qian, Jay; Gedzberg, Katie; Gruda, Maryanne; Rodriguez, Efrain Frank; Nesbitt, Leslie; Riben, Michael

2018-01-01

The tagging system is based on a small, electronic, wireless, laser-light-activated microtransponder named "p-Chip." The p-Chip is a silicon integrated circuit, the size of which is 600 μm × 600 μm × 100 μm. Each p-Chip contains a unique identification code stored within its electronic memory that can be retrieved with a custom reader. These features allow the p-Chip to be used as an unobtrusive and scarcely noticeable ID tag on glass slides and tissue cassettes. The system is comprised of p-Chip-tagged sample carriers, a dedicated benchtop p-Chip ID reader that can accommodate both objects, and an additional reader (the Wand), with an adapter for reading IDs of glass slides stored vertically in drawers. On slides, p-Chips are attached with adhesive to the center of the short edge, and on cassettes - embedded directly into the plastic. ID readout is performed by bringing the reader to the proximity of the chip. Standard histopathology laboratory protocols were used for testing. Very good ID reading efficiency was observed for both glass slides and cassettes. When processed slides are stored in vertical filing drawers, p-Chips remain readable without the need to remove them from the storage location, thereby improving the speed of searches in collections. On the cassettes, the ID continues to be readable through a thin layer of paraffin. Both slides and tissue cassettes can be read with the same reader, reducing the need for redundant equipment. The p-Chip is stable to all chemical challenges commonly used in the histopathology laboratory, tolerates temperature extremes, and remains durable in long-term storage. The technology is compatible with laboratory information management systems software systems. The p-Chip system is very well suited for identification of glass slides and cassettes in the histopathology laboratory.

Electronic p-Chip-Based System for Identification of Glass Slides and Tissue Cassettes in Histopathology Laboratories

PubMed Central

Mandecki, Wlodek; Qian, Jay; Gedzberg, Katie; Gruda, Maryanne; Rodriguez, Efrain “Frank”; Nesbitt, Leslie; Riben, Michael

2018-01-01

Background: The tagging system is based on a small, electronic, wireless, laser-light-activated microtransponder named “p-Chip.” The p-Chip is a silicon integrated circuit, the size of which is 600 μm × 600 μm × 100 μm. Each p-Chip contains a unique identification code stored within its electronic memory that can be retrieved with a custom reader. These features allow the p-Chip to be used as an unobtrusive and scarcely noticeable ID tag on glass slides and tissue cassettes. Methods: The system is comprised of p-Chip-tagged sample carriers, a dedicated benchtop p-Chip ID reader that can accommodate both objects, and an additional reader (the Wand), with an adapter for reading IDs of glass slides stored vertically in drawers. On slides, p-Chips are attached with adhesive to the center of the short edge, and on cassettes – embedded directly into the plastic. ID readout is performed by bringing the reader to the proximity of the chip. Standard histopathology laboratory protocols were used for testing. Results: Very good ID reading efficiency was observed for both glass slides and cassettes. When processed slides are stored in vertical filing drawers, p-Chips remain readable without the need to remove them from the storage location, thereby improving the speed of searches in collections. On the cassettes, the ID continues to be readable through a thin layer of paraffin. Both slides and tissue cassettes can be read with the same reader, reducing the need for redundant equipment. Conclusions: The p-Chip is stable to all chemical challenges commonly used in the histopathology laboratory, tolerates temperature extremes, and remains durable in long-term storage. The technology is compatible with laboratory information management systems software systems. The p-Chip system is very well suited for identification of glass slides and cassettes in the histopathology laboratory. PMID:29692946

Achievement of two logical states through a polymer/silicon interface for organic-inorganic hybrid memory

NASA Astrophysics Data System (ADS)

Chen, Jianhui; Chen, Bingbing; Shen, Yanjiao; Guo, Jianxin; Liu, Baoting; Dai, Xiuhong; Xu, Ying; Mai, Yaohua

2017-11-01

A hysteresis loop of minority carrier lifetime vs voltage is found in polystyrenesulfonate (PSS)/Si organic-inorganic hybrid heterojunctions, implying an interfacial memory effect. Capacitance-voltage and conductance-voltage hysteresis loops are observed and reveal a memory window. A switchable interface state, which can be controlled by charge transfer based on an electrochemical oxidation/deoxidation process, is suggested to be responsible for this hysteresis effect. We perform first-principle total-energy calculations on the influence of external electric fields and electrons or holes, which are injected into interface states on the adsorption energy of PSS on Si. It is demonstrated that the dependence of the interface adsorption energy difference on the electric field is the origin of this two-state switching. These results offer a concept of organic-inorganic hybrid interface memory being optically or electrically readable, low-cost, and compatible with the flexible organic electronics.

Data Movement Dominates: Advanced Memory Technology to Address the Real Exascale Power Problem

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bergman, Keren

Energy is the fundamental barrier to Exascale supercomputing and is dominated by the cost of moving data from one point to another, not computation. Similarly, performance is dominated by data movement, not computation. The solution to this problem requires three critical technologies: 3D integration, optical chip-to-chip communication, and a new communication model. The central goal of the Sandia led "Data Movement Dominates" project aimed to develop memory systems and new architectures based on these technologies that have the potential to lower the cost of local memory accesses by orders of magnitude and provide substantially more bandwidth. Only through these transformationalmore » advances can future systems reach the goals of Exascale computing with a manageable power budgets. The Sandia led team included co-PIs from Columbia University, Lawrence Berkeley Lab, and the University of Maryland. The Columbia effort of Data Movement Dominates focused on developing a physically accurate simulation environment and experimental verification for optically-connected memory (OCM) systems that can enable continued performance scaling through high-bandwidth capacity, energy-efficient bit-rate transparency, and time-of-flight latency. With OCM, memory device parallelism and total capacity can scale to match future high-performance computing requirements without sacrificing data-movement efficiency. When we consider systems with integrated photonics, links to memory can be seamlessly integrated with the interconnection network-in a sense, memory becomes a primary aspect of the interconnection network. At the core of the Columbia effort, toward expanding our understanding of OCM enabled computing we have created an integrated modeling and simulation environment that uniquely integrates the physical behavior of the optical layer. The PhoenxSim suite of design and software tools developed under this effort has enabled the co-design of and performance evaluation photonics-enabled OCM architectures on Exascale computing systems.« less

Mechanism-Based FE Simulation of Tool Wear in Diamond Drilling of SiCp/Al Composites.

PubMed

Xiang, Junfeng; Pang, Siqin; Xie, Lijing; Gao, Feinong; Hu, Xin; Yi, Jie; Hu, Fang

2018-02-07

The aim of this work is to analyze the micro mechanisms underlying the wear of macroscale tools during diamond machining of SiC p /Al6063 composites and to develop the mechanism-based diamond wear model in relation to the dominant wear behaviors. During drilling, high volume fraction SiC p /Al6063 composites containing Cu, the dominant wear mechanisms of diamond tool involve thermodynamically activated physicochemical wear due to diamond-graphite transformation catalyzed by Cu in air atmosphere and mechanically driven abrasive wear due to high-frequency scrape of hard SiC reinforcement on tool surface. An analytical diamond wear model, coupling Usui abrasive wear model and Arrhenius extended graphitization wear model was proposed and implemented through a user-defined subroutine for tool wear estimates. Tool wear estimate in diamond drilling of SiC p /Al6063 composites was achieved by incorporating the combined abrasive-chemical tool wear subroutine into the coupled thermomechanical FE model of 3D drilling. The developed drilling FE model for reproducing diamond tool wear was validated for feasibility and reliability by comparing numerically simulated tool wear morphology and experimentally observed results after drilling a hole using brazed polycrystalline diamond (PCD) and chemical vapor deposition (CVD) diamond coated tools. A fairly good agreement of experimental and simulated results in cutting forces, chip and tool wear morphologies demonstrates that the developed 3D drilling FE model, combined with a subroutine for diamond tool wear estimate can provide a more accurate analysis not only in cutting forces and chip shape but also in tool wear behavior during drilling SiC p /Al6063 composites. Once validated and calibrated, the developed diamond tool wear model in conjunction with other machining FE models can be easily extended to the investigation of tool wear evolution with various diamond tool geometries and other machining processes in cutting different workpiece materials.

Mechanism-Based FE Simulation of Tool Wear in Diamond Drilling of SiCp/Al Composites

PubMed Central

Xiang, Junfeng; Pang, Siqin; Xie, Lijing; Gao, Feinong; Hu, Xin; Yi, Jie; Hu, Fang

2018-01-01

The aim of this work is to analyze the micro mechanisms underlying the wear of macroscale tools during diamond machining of SiCp/Al6063 composites and to develop the mechanism-based diamond wear model in relation to the dominant wear behaviors. During drilling, high volume fraction SiCp/Al6063 composites containing Cu, the dominant wear mechanisms of diamond tool involve thermodynamically activated physicochemical wear due to diamond-graphite transformation catalyzed by Cu in air atmosphere and mechanically driven abrasive wear due to high-frequency scrape of hard SiC reinforcement on tool surface. An analytical diamond wear model, coupling Usui abrasive wear model and Arrhenius extended graphitization wear model was proposed and implemented through a user-defined subroutine for tool wear estimates. Tool wear estimate in diamond drilling of SiCp/Al6063 composites was achieved by incorporating the combined abrasive-chemical tool wear subroutine into the coupled thermomechanical FE model of 3D drilling. The developed drilling FE model for reproducing diamond tool wear was validated for feasibility and reliability by comparing numerically simulated tool wear morphology and experimentally observed results after drilling a hole using brazed polycrystalline diamond (PCD) and chemical vapor deposition (CVD) diamond coated tools. A fairly good agreement of experimental and simulated results in cutting forces, chip and tool wear morphologies demonstrates that the developed 3D drilling FE model, combined with a subroutine for diamond tool wear estimate can provide a more accurate analysis not only in cutting forces and chip shape but also in tool wear behavior during drilling SiCp/Al6063 composites. Once validated and calibrated, the developed diamond tool wear model in conjunction with other machining FE models can be easily extended to the investigation of tool wear evolution with various diamond tool geometries and other machining processes in cutting different workpiece materials. PMID:29414839

An Overview of Wide Bandgap Silicon Carbide Sensors and Electronics Development at NASA Glenn Research Center

NASA Technical Reports Server (NTRS)

Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Okojie, Robert S.; Chen, Liangyu; Spry, D.; Trunek, A.

2007-01-01

A brief overview is presented of the sensors and electronics development work ongoing at NASA Glenn Research Center which is intended to meet the needs of future aerospace applications. Three major technology areas are discussed: 1) high temperature SiC electronics, 2) SiC gas sensor technology development, and 3) packaging of harsh environment devices. Highlights of this work include world-record operation of SiC electronic devices including 500?C JFET transistor operation with excellent properties, atomically flat SiC gas sensors integrated with an on-chip temperature detector/heater, and operation of a packaged AC amplifier. A description of the state-of-the-art is given for each topic. It is concluded that significant progress has been made and that given recent advancements the development of high temperature smart sensors is envisioned.

Manufacturing Methods and Technology for Digital Fault Isolation for Printed Circuit Boards.

DTIC Science & Technology

1979-08-25

microprocessors and support chips, ROMs, RAMs, UARTs , etc. They also include rules for busses and memory testing. The special rules for test points emphasize...I 8). UART .. ...................................................... I 9). SAT...0.0 I ( 8). UART ...................................................... 0.0O S 9). SAT

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

DOE PAGES

Bender, Michael A.; Berry, Jonathan W.; Hammond, Simon D.; ...

2017-01-03

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” andmore » if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.« less

Mechanical characterization of poly-SiGe layers for CMOS-MEMS integrated application

NASA Astrophysics Data System (ADS)

Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; Puers, Robert; De Wolf, Ingrid

2010-01-01

Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups.

High Stability Induced by the TiN/Ti Interlayer in Three-Dimensional Si/Ge Nanorod Arrays as Anode in Micro Lithium Ion Battery.

PubMed

Yue, Chuang; Yu, Yingjian; Wu, Zhenguo; Sun, Shibo; He, Xu; Li, Juntao; Zhao, Libo; Wu, Suntao; Li, Jing; Kang, Junyong; Lin, Liwei

2016-03-01

Three-dimensional (3D) Si/Ge-based micro/nano batteries are promising lab-on-chip power supply sources because of the good process compatibility with integrated circuits and Micro/Nano-Electro-Mechanical System technologies. In this work, the effective interlayer of TiN/Ti thin films were introduced to coat around the 3D Si nanorod (NR) arrays before the amorphous Ge layer deposition as anode in micro/nano lithium ion batteries, thus the superior cycling stability was realized by reason for the restriction of Si activation in this unique 3D matchlike Si/TiN/Ti/Ge NR array electrode. Moreover, the volume expansion properties after the repeated lithium-ion insertion/extraction were experimentally investigated to evidence the superior stability of this unique multilayered Si composite electrode. The demonstration of this wafer-scale, cost-effective, and Si-compatible fabrication for anodes in Li-ion micro/nano batteries provides new routes to configurate more efficient 3D energy storage systems for micro/nano smart semiconductor devices.

The Impact on Space Radiation Requirements and Effects on ASIMS

NASA Technical Reports Server (NTRS)

Barnes, C.; Johnston, A.; Swift, G.

1995-01-01

The evolution of highly miniaturized electronic and mechanical systems will be accompanied by new problems and issues regarding the radiation response of these systems in the space environment. In this paper we discuss some of the more prominent radiation problems brought about by miniaturization. For example, autonomous micro-spacecraft will require large amounts of high density memory, most likely in the form of stacked, multichip modules of DRAM's, that must tolerate the radiation environment. However, advanced DRAM's (16 to 256 Mbit) are quite susceptible to radiation, particularly single event effects, and even exhibit new radiation phenomena that were not a problem for older, less dense memory chips. Another important trend in micro-spacecraft electronics is toward the use of low-voltage microelectronic systems that consume less power. However, the reduction in operating voltage also caries with it an increased susceptibility to radiation. In the case of application specific integrated microcircuits (ASIM's), advanced devices of this type, such as high density field programmable gate arrays (FPGA's) exhibit new single event effects (SEE), such as single particle reprogramming of anti-fuse links. New advanced bipolar circuits have been shown recently to degrade more rapidly in the low dose rate space environment than in the typical laboratory total dose radiation test used to qualify such devices. Thus total dose testing of these parts is no longer an appropriately conservative measure to be used for hardness assurance. We also note that the functionality of micromechanical Si-based devices may be altered due to the radiation-induced deposition of charge in the oxide passivation layers.

Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

NASA Astrophysics Data System (ADS)

Seiler, David G.

1997-10-01

A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Summary of workshop on the application of VLSI for robotic sensing

NASA Technical Reports Server (NTRS)

Brooks, T.; Wilcox, B.

1984-01-01

It was one of the objectives of the considered workshop to identify near, mid, and far-term applications of VLSI for robotic sensing and sensor data preprocessing. The workshop was also to indicate areas in which VLSI technology can provide immediate and future payoffs. A third objective is related to the promotion of dialog and collaborative efforts between research communities, industry, and government. The workshop was held on March 24-25, 1983. Conclusions and recommendations are discussed. Attention is given to the need for a pixel correction chip, an image sensor with 10,000 dynamic range, VLSI enhanced architectures, the need for a high-density serpentine memory, an LSI-tactile sensing program, an analog-signal preprocessor chip, a smart strain gage, a protective proximity envelope, a VLSI-proximity sensor program, a robot-net chip, and aspects of silicon micromechanics.

Fabrication of Cantilever-Bump Type Si Probe Card

NASA Astrophysics Data System (ADS)

Park, Jeong-Yong; Lee, Dong-Seok; Kim, Dong-Kwon; Lee, Jong-Hyun

2000-12-01

Probe card is most important part in the test system which selects the good or bad chip of integrated circuit (IC) chips. Silicon vertical probe card is able to test multiple semiconductor chips simultaneously. We presented cantilever-bump type vertical probe card. It was fabricated by dry etching using RIE(reactive ion etching) technique and porous silicon micromachining using silicon direct bonded (SDB) wafer. Cantilevers and bumps were fabricated by isotropic etching using RIE@. 3-dimensional structures were formed by porous silicon micromachining technique using SDB wafer. Contact resistance of fabricated probe card was less than 2 Ω and its life time was more than 200,000 turns. The process used in this work is very simple and reproducible, which has good controllability in the tip dimension and spacing. It is expected that the fabricated probe card can reduce testing time, can promote productivity and enables burn-in test.

Evaluation of a Programmable Voltage-Controlled MEMS Oscillator, Type SiT3701, Over a Wide Temperature Range

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Semiconductor chips based on MEMS (Micro-Electro-Mechanical Systems) technology, such as sensors, transducers, and actuators, are becoming widely used in today s electronics due to their high performance, low power consumption, tolerance to shock and vibration, and immunity to electro-static discharge. In addition, the MEMS fabrication process allows for the miniaturization of individual chips as well as the integration of various electronic circuits into one module, such as system-on-a-chip. These measures would simplify overall system design, reduce parts count and interface, improve reliability, and reduce cost; and they would meet requirements of systems destined for use in space exploration missions. In this work, the performance of a recently-developed MEMS voltage-controlled oscillator was evaluated under a wide temperature range. Operation of this new commercial-off-the-shelf (COTS) device was also assessed under thermal cycling to address some operational conditions of the space environment

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

Improved light extraction efficiency of GaN-based flip-chip light-emitting diodes with an antireflective interface layer

NASA Astrophysics Data System (ADS)

Wu, Dongxue; Ma, Ping; Liu, Boting; Zhang, Shuo; Wang, Junxi; Li, Jinmin

2016-05-01

GaN-based flip-chip light-emitting diodes (FC-LEDs) grown on nanopatterned sapphire substrates (NPSS) are fabricated using self-assembled SiO2 nanospheres as masks during inductively coupled plasma etching. By controlling the pattern spacing, epitaxial GaN can be grown from the top or bottom of patterns to obtain two different GaN/substrate interfaces. The optoelectronic characteristics of FC-LED chips with different GaN/sapphire interfaces are studied. The FC-LED with an antireflective interface layer consisting of a NPSS with GaN in the pattern spacings demonstrates better optical properties than the FC-LED with an interface embedded with air voids. Our study indicates that the two types of FC-LEDs grown on NPSS show higher crystal quality and improved electrical and optical characteristics compared with those of FC-LEDs grown on conventional planar sapphire substrates.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

NASA Astrophysics Data System (ADS)

Tokel, Onur; Turnalı, Ahmet; Makey, Ghaith; Elahi, Parviz; ćolakoǧlu, Tahir; Ergeçen, Emre; Yavuz, Ã.-zgün; Hübner, René; Zolfaghari Borra, Mona; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ã.-mer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3, with untapped potential for mid-infrared optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow the fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realized with techniques like reactive ion etching. Embedded optical elements7, electronic devices and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1-µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has an optical index different to that in unmodified parts, enabling the creation of numerous photonic devices. Optionally, these parts can be chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface—that is, `in-chip'—microstructures for microfluidic cooling of chips, vias, micro-electro-mechanical systems, photovoltaic applications and photonic devices that match or surpass corresponding state-of-the-art device performances.

Feasibility study of current pulse induced 2-bit/4-state multilevel programming in phase-change memory

NASA Astrophysics Data System (ADS)

Liu, Yan; Fan, Xi; Chen, Houpeng; Wang, Yueqing; Liu, Bo; Song, Zhitang; Feng, Songlin

2017-08-01

In this brief, multilevel data storage for phase-change memory (PCM) has attracted more attention in the memory market to implement high capacity memory system and reduce cost-per-bit. In this work, we present a universal programing method of SET stair-case current pulse in PCM cells, which can exploit the optimum programing scheme to achieve 2-bit/ 4state resistance-level with equal logarithm interval. SET stair-case waveform can be optimized by TCAD real time simulation to realize multilevel data storage efficiently in an arbitrary phase change material. Experimental results from 1 k-bit PCM test-chip have validated the proposed multilevel programing scheme. This multilevel programming scheme has improved the information storage density, robustness of resistance-level, energy efficient and avoiding process complexity.

Coherent spin control of a nanocavity-enhanced qubit in diamond

DOE PAGES

Li, Luozhou; Lu, Ming; Schroder, Tim; ...

2015-01-28

A central aim of quantum information processing is the efficient entanglement of multiple stationary quantum memories via photons. Among solid-state systems, the nitrogen-vacancy centre in diamond has emerged as an excellent optically addressable memory with second-scale electron spin coherence times. Recently, quantum entanglement and teleportation have been shown between two nitrogen-vacancy memories, but scaling to larger networks requires more efficient spin-photon interfaces such as optical resonators. Here we report such nitrogen-vacancy nanocavity systems in strong Purcell regime with optical quality factors approaching 10,000 and electron spin coherence times exceeding 200 µs using a silicon hard-mask fabrication process. This spin-photon interfacemore » is integrated with on-chip microwave striplines for coherent spin control, providing an efficient quantum memory for quantum networks.« less

Scalable quantum memory in the ultrastrong coupling regime.

PubMed

Kyaw, T H; Felicetti, S; Romero, G; Solano, E; Kwek, L-C

2015-03-02

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances.

Scalable quantum memory in the ultrastrong coupling regime

PubMed Central

Kyaw, T. H.; Felicetti, S.; Romero, G.; Solano, E.; Kwek, L.-C.

2015-01-01

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances. PMID:25727251

A memory module for experimental data handling

NASA Astrophysics Data System (ADS)

De Blois, J.

1985-02-01

A compact CAMAC memory module for experimental data handling was developed to eliminate the need of direct memory access in computer controlled measurements. When using autonomous controllers it also makes measurements more independent of the program and enlarges the available space for programs in the memory of the micro-computer. The memory module has three modes of operation: an increment-, a list- and a fifo mode. This is achieved by connecting the main parts, being: the memory (MEM), the fifo buffer (FIFO), the address buffer (BUF), two counters (AUX and ADDR) and a readout register (ROR), by an internal 24-bit databus. The time needed for databus operations is 1 μs, for measuring cycles as well as for CAMAC cycles. The FIFO provides temporary data storage during CAMAC cycles and separates the memory part from the application part. The memory is variable from 1 to 64K (24 bits) by using different types of memory chips. The application part, which forms 1/3 of the module, will be specially designed for each application and is added to the memory chian internal connector. The memory unit will be used in Mössbauer experiments and in thermal neutron scattering experiments.

Optical reset modulation in the SiO2/Cu conductive-bridge resistive memory stack

NASA Astrophysics Data System (ADS)

Kawashima, T.; Zhou, Y.; Yew, K. S.; Ang, D. S.

2017-09-01

We show that the negative photoconductivity property of the nanoscale filamentary breakdown path in the SiO2 electrolyte of the SiO2/Cu conductive bridge resistive random access memory (CBRAM) stack is affected by the number of positive-voltage sweeps applied to the Cu electrode (with respect to a non-metal counter electrode). The path's photo-response to white light, of a given intensity, is suppressed with an increasing number of applied positive-voltage sweeps. When this occurs, the path may only be disrupted by the light of a higher intensity. It is further shown that the loss of the path's photosensitivity to the light of a given intensity can be recovered using a negative-voltage sweep (which eliminates the path), followed by the reformation of the path by a positive-voltage sweep. The above behavior is, however, not seen in the SiO2/Si stack (which involves a non-metal Si electrode), suggesting that the photo-response modulation effect is related to the Cu electrode. The demonstrated reversible electrical modulation of the path's photo-response may afford greater flexibility in the electro-optical control of the CBRAM device.

Integration and High-Temperature Characterization of Ferroelectric Vanadium-Doped Bismuth Titanate Thin Films on Silicon Carbide

NASA Astrophysics Data System (ADS)

Ekström, Mattias; Khartsev, Sergiy; Östling, Mikael; Zetterling, Carl-Mikael

2017-07-01

4H-SiC electronics can operate at high temperature (HT), e.g., 300°C to 500°C, for extended times. Systems using sensors and amplifiers that operate at HT would benefit from microcontrollers which can also operate at HT. Microcontrollers require nonvolatile memory (NVM) for computer programs. In this work, we demonstrate the possibility of integrating ferroelectric vanadium-doped bismuth titanate (BiTV) thin films on 4H-SiC for HT memory applications, with BiTV ferroelectric capacitors providing memory functionality. Film deposition was achieved by laser ablation on Pt (111)/TiO2/4H-SiC substrates, with magnetron-sputtered Pt used as bottom electrode and thermally evaporated Au as upper contacts. Film characterization by x-ray diffraction analysis revealed predominately (117) orientation. P- E hysteresis loops measured at room temperature showed maximum 2 P r of 48 μC/cm2, large enough for wide read margins. P- E loops were measurable up to 450°C, with losses limiting measurements above 450°C. The phase-transition temperature was determined to be about 660°C from the discontinuity in dielectric permittivity, close to what is achieved for ceramics. These BiTV ferroelectric capacitors demonstrate potential for use in HT NVM applications for SiC digital electronics.

Temperature dependent evolution of wrinkled single-crystal silicon ribbons on shape memory polymers.

PubMed

Wang, Yu; Yu, Kai; Qi, H Jerry; Xiao, Jianliang

2017-10-25

Shape memory polymers (SMPs) can remember two or more distinct shapes, and thus can have a lot of potential applications. This paper presents combined experimental and theoretical studies on the wrinkling of single-crystal Si ribbons on SMPs and the temperature dependent evolution. Using the shape memory effect of heat responsive SMPs, this study provides a method to build wavy forms of single-crystal silicon thin films on top of SMP substrates. Silicon ribbons obtained from a Si-on-insulator (SOI) wafer are released and transferred onto the surface of programmed SMPs. Then such bilayer systems are recovered at different temperatures, yielding well-defined, wavy profiles of Si ribbons. The wavy profiles are shown to evolve with time, and the evolution behavior strongly depends on the recovery temperature. At relatively low recovery temperatures, both wrinkle wavelength and amplitude increase with time as evolution progresses. Finite element analysis (FEA) accounting for the thermomechanical behavior of SMPs is conducted to study the wrinkling of Si ribbons on SMPs, which shows good agreement with experiment. Merging of wrinkles is observed in FEA, which could explain the increase of wrinkle wavelength observed in the experiment. This study can have important implications for smart stretchable electronics, wrinkling mechanics, stimuli-responsive surface engineering, and advanced manufacturing.

A CAM-based LZ data compression IC

NASA Technical Reports Server (NTRS)

Winters, K.; Bode, R.; Schneider, E.

1993-01-01

A custom CMOS processor is introduced that implements the Data Compression Lempel-Ziv (DCLZ) standard, a variation of the LZ2 Algorithm. This component presently achieves a sustained compression and decompression rate of 10 megabytes/second by employing an on-chip content-addressable memory for string table storage.

An Adaptive Insertion and Promotion Policy for Partitioned Shared Caches

NASA Astrophysics Data System (ADS)

Mahrom, Norfadila; Liebelt, Michael; Raof, Rafikha Aliana A.; Daud, Shuhaizar; Hafizah Ghazali, Nur

2018-03-01

Cache replacement policies in chip multiprocessors (CMP) have been investigated extensively and proven able to enhance shared cache management. However, competition among multiple processors executing different threads that require simultaneous access to a shared memory may cause cache contention and memory coherence problems on the chip. These issues also exist due to some drawbacks of the commonly used Least Recently Used (LRU) policy employed in multiprocessor systems, which are because of the cache lines residing in the cache longer than required. In image processing analysis of for example extra pulmonary tuberculosis (TB), an accurate diagnosis for tissue specimen is required. Therefore, a fast and reliable shared memory management system to execute algorithms for processing vast amount of specimen image is needed. In this paper, the effects of the cache replacement policy in a partitioned shared cache are investigated. The goal is to quantify whether better performance can be achieved by using less complex replacement strategies. This paper proposes a Middle Insertion 2 Positions Promotion (MI2PP) policy to eliminate cache misses that could adversely affect the access patterns and the throughput of the processors in the system. The policy employs a static predefined insertion point, near distance promotion, and the concept of ownership in the eviction policy to effectively improve cache thrashing and to avoid resource stealing among the processors.

The Potato Chip Really Does Look Like Elvis! Neural Hallmarks of Conceptual Processing Associated with Finding Novel Shapes Subjectively Meaningful

PubMed Central

Federmeier, Kara D.; Paller, Ken A.

2012-01-01

Clouds and inkblots often compellingly resemble something else—faces, animals, or other identifiable objects. Here, we investigated illusions of meaning produced by novel visual shapes. Individuals found some shapes meaningful and others meaningless, with considerable variability among individuals in these subjective categorizations. Repetition for shapes endorsed as meaningful produced conceptual priming in a priming test along with concurrent activity reductions in cortical regions associated with conceptual processing of real objects. Subjectively meaningless shapes elicited robust activity in the same brain areas, but activity was not influenced by repetition. Thus, all shapes were conceptually evaluated, but stable conceptual representations supported neural priming for meaningful shapes only. During a recognition memory test, performance was associated with increased frontoparietal activity, regardless of meaningfulness. In contrast, neural conceptual priming effects for meaningful shapes occurred during both priming and recognition testing. These different patterns of brain activation as a function of stimulus repetition, type of memory test, and subjective meaningfulness underscore the distinctive neural bases of conceptual fluency versus episodic memory retrieval. Finding meaning in ambiguous stimuli appears to depend on conceptual evaluation and cortical processing events similar to those typically observed for known objects. To the brain, the vaguely Elvis-like potato chip truly can provide a substitute for the King himself. PMID:22079921

Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

PubMed

Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

2017-02-15

An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si₃N₄) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si₃N₄ and the LN-Si₃N₄ waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

Dorsolateral prefrontal cortex bridges bilateral primary somatosensory cortices during cross-modal working memory.

PubMed

Zhao, Di; Ku, Yixuan

2018-05-01

Neural activity in the dorsolateral prefrontal cortex (DLPFC) has been suggested to integrate information from distinct sensory areas. However, how the DLPFC interacts with the bilateral primary somatosensory cortices (SIs) in tactile-visual cross-modal working memory has not yet been established. In the present study, we applied single-pulse transcranial magnetic stimulation (sp-TMS) over the contralateral DLPFC and bilateral SIs of human participants at various time points, while they performed a tactile-visual delayed matching-to-sample task with a 2-second delay. sp-TMS over the contralateral DLPFC or the contralateral SI at either an sensory encoding stage [i.e. 100 ms after the onset of a vibrotactile sample stimulus (200-ms duration)] or an early maintenance stage (i.e. 300 ms after the onset), significantly impaired the accuracy of task performance; sp-TMS over the contralateral DLPFC or the ipsilateral SI at a late maintenance stage (1600 ms and 1900 ms) also significantly disrupted the performance. Furthermore, at 300 ms after the onset of the vibrotactile sample stimulus, there was a significant correlation between the deteriorating effects of sp-TMS over the contralateral SI and the contralateral DLPFC. These results imply that the DLPFC and the bilateral SIs play causal roles at distinctive stages during cross-modal working memory, while the contralateral DLPFC communicates with the contralateral SI in the early delay, and cooperates with the ipsilateral SI in the late delay. Copyright © 2018 Elsevier B.V. All rights reserved.

Sulforaphane Upregulates the Heat Shock Protein Co-Chaperone CHIP and Clears Amyloid-β and Tau in a Mouse Model of Alzheimer's Disease.

PubMed

Lee, Siyoung; Choi, Bo-Ryoung; Kim, Jisung; LaFerla, Frank M; Park, Jung Han Yoon; Han, Jung-Soo; Lee, Ki Won; Kim, Jiyoung

2018-04-30

Sulforaphane is an herbal isothiocyanate enriched in cruciferous vegetables. Here, the authors investigate whether sulforaphane modulates the production of amyloid-β (Aβ) and tau, the two main pathological factors in Alzheimer's disease (AD). A triple transgenic mouse model of AD (3 × Tg-AD) is used to study the effect of sulforaphane. Oral gavage of sulforaphane reduces protein levels of monomeric and polymeric forms of Aβ as well as tau and phosphorylated tau in 3 × Tg-AD mice. However, sulforaphane treatment do not affect mRNA expression of amyloid precursor protein or tau. As previous studies show that Aβ and tau metabolism are influenced by a heat shock protein (HSP) co-chaperone, C-terminus of HSP70-interacting protein (CHIP), the authors examine whether sulforaphane can modulate CHIP. The authors find that sulforaphane treatment increase levels of CHIP and HSP70. Furthermore, observations of CHIP-deficient primary neurons derived from 3 × Tg-AD mice suggest that sulforaphane treatment increase CHIP level and clear the accumulation of Aβ and tau. Finally, sulforaphane ameliorated memory deficits in 3 × Tg-AD mice as reveal by novel object/location recognition tests and contextual fear conditioning tests. These results demonstrate that sulforaphane treatment upregulates CHIP and has the potential to decrease the accumulation of Aβ and tau in patients with AD. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

An 81.6 μW FastICA processor for epileptic seizure detection.

PubMed

Yang, Chia-Hsiang; Shih, Yi-Hsin; Chiueh, Herming

2015-02-01

To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 mm(2). The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 μW at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 × computation speedup are achieved. The performance of the chip was verified by human dataset.

Conductive bridge random access memory characteristics of SiCN based transparent device due to indium diffusion

NASA Astrophysics Data System (ADS)

Kumar, Dayanand; Aluguri, Rakesh; Chand, Umesh; Tseng, Tseung-Yuen

2018-03-01

In this work, the transparent bipolar resistive switching characteristics of a SiCN-based ITO/SiCN/AZO structure due to In diffusion from ITO is studied. The SiCN based device is found to be 80% transparent in the visible wavelength region. This device, with AZO as both top and bottom electrodes, does not show any RRAM property due to deposition of the high quality O2-free SiCN film. Replacing the AZO top electrode with ITO in this device results in good resistive switching (RS) characteristics with a high on/off ratio and long retention. Replacing the SiCN film with ZrO2 also results in excellent RS characteristics due to the formation of an oxygen vacancies filament inside the ZrO2 film. A resistance ratio of on/off is found to be higher in the SiCN based device compared to that of the ZrO2 device. Diffusion of In from ITO into the SiCN film on application of high positive voltage during forming can be attributed to the occurrence of RS in the device, which is confirmed by the analyses of energy dispersive spectroscopy and secondary-ion mass spectrometry. This study shows a pathway for the fabrication of CBRAM based transparent devices for non-volatile memory application.

Thermal conductivity measurement of amorphous dielectric multilayers for phase-change memory power reduction

NASA Astrophysics Data System (ADS)

Fong, S. W.; Sood, A.; Chen, L.; Kumari, N.; Asheghi, M.; Goodson, K. E.; Gibson, G. A.; Wong, H.-S. P.

2016-07-01

In this work, we investigate the temperature-dependent thermal conductivities of few nanometer thick alternating stacks of amorphous dielectrics, specifically SiO2/Al2O3 and SiO2/Si3N4. Experiments using steady-state Joule-heating and electrical thermometry, while using a micro-miniature refrigerator over a wide temperature range (100-500 K), show that amorphous thin-film multilayer SiO2/Si3N4 and SiO2/Al2O3 exhibit through-plane room temperature effective thermal conductivities of about 1.14 and 0.48 W/(m × K), respectively. In the case of SiO2/Al2O3, the reduced conductivity is attributed to lowered film density (7.03 → 5.44 × 1028 m-3 for SiO2 and 10.2 → 8.27 × 1028 m-3 for Al2O3) caused by atomic layer deposition of thin-films as well as a small, finite, and repeating thermal boundary resistance (TBR) of 1.5 m2 K/GW between dielectric layers. Molecular dynamics simulations reveal that vibrational mismatch between amorphous oxide layers is small, and that the TBR between layers is largely due to imperfect interfaces. Finally, the impact of using this multilayer dielectric in a dash-type phase-change memory device is studied using finite-element simulations.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Heterogeneous Integration for Reduced Phase Noise and Improved Reliability of Semiconductor Lasers

NASA Astrophysics Data System (ADS)

Srinivasan, Sudharsanan

Significant savings in cost, power and space are possible in existing optical data transmission networks, sensors and metrology equipment through photonic integration. Photonic integration can be broadly classified into two categories, hybrid and monolithic integration. The former involves assembling multiple single functionality optical devices together into a single package including any optical coupling and/or electronic connections. On the other hand monolithic integration assembles many devices or optical functionalities on a single chip so that all the optical connections are on chip and require no external alignment. This provides a substantial improvement in reliability and simplifies testing. Monolithic integration has been demonstrated on both indium phosphide (InP) and silicon (Si) substrates. Integration on larger 300mm Si substrates can further bring down the cost and has been a major area of research in recent years. Furthermore, with increasing interest from industry, the hybrid silicon platform is emerging as a new technology for integrating various active and passive optical elements on a single chip. This is both in the interest of bringing down manufacturing cost through scaling along with continued improvement in performance and to produce multi-functional photonic integrated circuits (PIC). The goal of this work is twofold. First, we show four laser demonstrations that use the hybrid silicon platform to lower phase noise due to spontaneous emission, based on the following two techniques, viz. confinement factor reduction and negative optical feedback. The first two demonstrations are of mode-locked lasers and the next two are of tunable lasers. Some of the key results include; (a) 14dB white frequency noise reduction of a 20GHz radio-frequency (RF) signal from a harmonically mode-locked long cavity laser with greater than 55dB supermode noise suppression, (b) 8dB white frequency noise reduction from a colliding pulse mode-locked laser by reducing the number of quantum wells and a further 6dB noise reduction using coherent photon seeding from long on-chip coupled cavity, (c) linewidth reduction of a tunable laser down to 160kHz using negative optical feedback from coupled ring resonator mirrors, and (d) linewidth reduction of a widely tunable laser down to 50kHz using on-chip coupled cavity feedback effect. Second, we present the results of a reliability study conducted to investigate the influence of molecular wafer bonding between Si and InP on the lifetime of distributed feedback lasers, a common laser source used in optical communication. No degradation in lasing threshold or slope efficiency was observed after aging the lasers for 5000hrs at 70°C and 2500hrs at 85°C. However, among the three chosen bonding interface layer options, the devices with an interface superlattice layer showed a higher yield for lasers and lower dark current values in the on-chip monitor photodiodes after aging.

Metal-organic molecular device for non-volatile memory storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Radha, B., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in; Sagade, Abhay A.; Kulkarni, G. U., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in

Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organicmore » complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.« less