Development of microcontroller-based acquisition and processing unit for fiber optic vibration sensor

NASA Astrophysics Data System (ADS)

Suryadi; Puranto, P.; Adinanta, H.; Waluyo, T. B.; Priambodo, P. S.

2017-04-01

Microcontroller based acquisition and processing unit (MAPU) has been developed to measure vibration signal from fiber optic vibration sensor. The MAPU utilizes a 32-bit ARM microcontroller to perform acquisition and processing of the input signal. The input signal is acquired with 12 bit ADC and processed using FFT method to extract frequency information. Stability of MAPU is characterized by supplying a constant input signal at 500 Hz for 29 hours and shows a stable operation. To characterize the frequency response, input signal is swapped from 20 to 1000 Hz with 20 Hz interval. The characterization result shows that MAPU can detect input signal from 20 to 1000 Hz with minimum signal of 4 mV RMS. The experiment has been set that utilizes the MAPU with singlemode-multimode-singlemode (SMS) fiber optic sensor to detect vibration which is induced by a transducer in a wooden platform. The experimental result indicates that vibration signal from 20 to 600 Hz has been successfully detected. Due to the limitation of the vibration source used in the experiment, vibration signal above 600 Hz is undetected.

A scalable SIMD digital signal processor for high-quality multifunctional printer systems

NASA Astrophysics Data System (ADS)

Kang, Hyeong-Ju; Choi, Yongwoo; Kim, Kimo; Park, In-Cheol; Kim, Jung-Wook; Lee, Eul-Hwan; Gahang, Goo-Soo

2005-01-01

This paper describes a high-performance scalable SIMD digital signal processor (DSP) developed for multifunctional printer systems. The DSP supports a variable number of datapaths to cover a wide range of performance and maintain a RISC-like pipeline structure. Many special instructions suitable for image processing algorithms are included in the DSP. Quad/dual instructions are introduced for 8-bit or 16-bit data, and bit-field extraction/insertion instructions are supported to process various data types. Conditional instructions are supported to deal with complex relative conditions efficiently. In addition, an intelligent DMA block is integrated to align data in the course of data reading. Experimental results show that the proposed DSP outperforms a high-end printer-system DSP by at least two times.

Optical domain analog to digital conversion methods and apparatus

DOEpatents

Vawter, Gregory A

2014-05-13

Methods and apparatus for optical analog to digital conversion are disclosed. An optical signal is converted by mapping the optical analog signal onto a wavelength modulated optical beam, passing the mapped beam through interferometers to generate analog bit representation signals, and converting the analog bit representation signals into an optical digital signal. A photodiode receives an optical analog signal, a wavelength modulated laser coupled to the photodiode maps the optical analog signal to a wavelength modulated optical beam, interferometers produce an analog bit representation signal from the mapped wavelength modulated optical beam, and sample and threshold circuits corresponding to the interferometers produce a digital bit signal from the analog bit representation signal.

Digital phased array beamforming using single-bit delta-sigma conversion with non-uniform oversampling.

PubMed

Kozak, M; Karaman, M

2001-07-01

Digital beamforming based on oversampled delta-sigma (delta sigma) analog-to-digital (A/D) conversion can reduce the overall cost, size, and power consumption of phased array front-end processing. The signal resampling involved in dynamic delta sigma beamforming, however, disrupts synchronization between the modulators and demodulator, causing significant degradation in the signal-to-noise ratio. As a solution to this, we have explored a new digital beamforming approach based on non-uniform oversampling delta sigma A/D conversion. Using this approach, the echo signals received by the transducer array are sampled at time instants determined by the beamforming timing and then digitized by single-bit delta sigma A/D conversion prior to the coherent beam summation. The timing information involves a non-uniform sampling scheme employing different clocks at each array channel. The delta sigma coded beamsums obtained by adding the delayed 1-bit coded RF echo signals are then processed through a decimation filter to produce final beamforming outputs. The performance and validity of the proposed beamforming approach are assessed by means of emulations using experimental raw RF data.

Radioastronomic signal processing cores for the SKA radio telescope

NASA Astrophysics Data System (ADS)

Comorett, G.; Chiarucc, S.; Belli, C.

Modern radio telescopes require the processing of wideband signals, with sample rates from tens of MHz to tens of GHz, and are composed from hundreds up to a million of individual antennas. Digital signal processing of these signals include digital receivers (the digital equivalent of the heterodyne receiver), beamformers, channelizers, spectrometers. FPGAs present the advantage of providing a relatively low power consumption, relative to GPUs or dedicated computers, a wide signal data path, and high interconnectivity. Efficient algorithms have been developed for these applications. Here we will review some of the signal processing cores developed for the SKA telescope. The LFAA beamformer/channelizer architecture is based on an oversampling channelizer, where the channelizer output sampling rate and channel spacing can be set independently. This is useful where an overlap between adjacent channels is required to provide an uniform spectral coverage. The architecture allows for an efficient and distributed channelization scheme, with a final resolution corresponding to a million of spectral channels, minimum leakage and high out-of-band rejection. An optimized filter design procedure is used to provide an equiripple response with a very large number of spectral channels. A wideband digital receiver has been designed in order to select the processed bandwidth of the SKA Mid receiver. The receiver extracts a 2.5 MHz bandwidth form a 14 GHz input bandwidth. The design allows for non-integer ratios between the input and output sampling rates, with a resource usage comparable to that of a conventional decimating digital receiver. Finally, some considerations on quantization of radioastronomic signals are presented. Due to the stochastic nature of the signal, quantization using few data bits is possible. Good accuracies and dynamic range are possible even with 2-3 bits, but the nonlinearity in the correlation process must be corrected in post-processing. With at least 6 bits it is possible to have a very linear response of the instrument, with nonlinear terms below 80 dB, providing the signal amplitude is kept within bounds.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Modeste Nguimdo, Romain, E-mail: Romain.Nguimdo@vub.ac.be; Tchitnga, Robert; Woafo, Paul

We numerically investigate the possibility of using a coupling to increase the complexity in simplest chaotic two-component electronic circuits operating at high frequency. We subsequently show that complex behaviors generated in such coupled systems, together with the post-processing are suitable for generating bit-streams which pass all the NIST tests for randomness. The electronic circuit is built up by unidirectionally coupling three two-component (one active and one passive) oscillators in a ring configuration through resistances. It turns out that, with such a coupling, high chaotic signals can be obtained. By extracting points at fixed interval of 10 ns (corresponding to a bitmore » rate of 100 Mb/s) on such chaotic signals, each point being simultaneously converted in 16-bits (or 8-bits), we find that the binary sequence constructed by including the 10(or 2) least significant bits pass statistical tests of randomness, meaning that bit-streams with random properties can be achieved with an overall bit rate up to 10×100 Mb/s =1Gbit/s (or 2×100 Mb/s =200 Megabit/s). Moreover, by varying the bias voltages, we also investigate the parameter range for which more complex signals can be obtained. Besides being simple to implement, the two-component electronic circuit setup is very cheap as compared to optical and electro-optical systems.« less

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications

PubMed Central

Park, Keunyeol; Song, Minkyu

2018-01-01

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm2 with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency. PMID:29495273

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications.

PubMed

Park, Keunyeol; Song, Minkyu; Kim, Soo Youn

2018-02-24

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm² with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

Preserving privacy of online digital physiological signals using blind and reversible steganography.

PubMed

Shiu, Hung-Jr; Lin, Bor-Sing; Huang, Chien-Hung; Chiang, Pei-Ying; Lei, Chin-Laung

2017-11-01

Physiological signals such as electrocardiograms (ECG) and electromyograms (EMG) are widely used to diagnose diseases. Presently, the Internet offers numerous cloud storage services which enable digital physiological signals to be uploaded for convenient access and use. Numerous online databases of medical signals have been built. The data in them must be processed in a manner that preserves patients' confidentiality. A reversible error-correcting-coding strategy will be adopted to transform digital physiological signals into a new bit-stream that uses a matrix in which is embedded the Hamming code to pass secret messages or private information. The shared keys are the matrix and the version of the Hamming code. An online open database, the MIT-BIH arrhythmia database, was used to test the proposed algorithms. The time-complexity, capacity and robustness are evaluated. Comparisons of several evaluations subject to related work are also proposed. This work proposes a reversible, low-payload steganographic scheme for preserving the privacy of physiological signals. An (n,  m)-hamming code is used to insert (n - m) secret bits into n bits of a cover signal. The number of embedded bits per modification is higher than in comparable methods, and the computational power is efficient and the scheme is secure. Unlike other Hamming-code based schemes, the proposed scheme is both reversible and blind. Copyright © 2017 Elsevier B.V. All rights reserved.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Olama, Mohammed M; Matalgah, Mustafa M; Bobrek, Miljko

Traditional encryption techniques require packet overhead, produce processing time delay, and suffer from severe quality of service deterioration due to fades and interference in wireless channels. These issues reduce the effective transmission data rate (throughput) considerably in wireless communications, where data rate with limited bandwidth is the main constraint. In this paper, performance evaluation analyses are conducted for an integrated signaling-encryption mechanism that is secure and enables improved throughput and probability of bit-error in wireless channels. This mechanism eliminates the drawbacks stated herein by encrypting only a small portion of an entire transmitted frame, while the rest is not subjectmore » to traditional encryption but goes through a signaling process (designed transformation) with the plaintext of the portion selected for encryption. We also propose to incorporate error correction coding solely on the small encrypted portion of the data to drastically improve the overall bit-error rate performance while not noticeably increasing the required bit-rate. We focus on validating the signaling-encryption mechanism utilizing Hamming and convolutional error correction coding by conducting an end-to-end system-level simulation-based study. The average probability of bit-error and throughput of the encryption mechanism are evaluated over standard Gaussian and Rayleigh fading-type channels and compared to the ones of the conventional advanced encryption standard (AES).« less

VLSI for High-Speed Digital Signal Processing

DTIC Science & Technology

1994-09-30

particular, the design, layout and fab - rication of integrated circuits. The primary project for this grant has been the design and implementation of a...targeted at 33.36 dB, and PSNR (dB) Rate ( bpp ) the FRSBC algorithm, targeted at 0.5 bits/pixel, respec- Filter FDSBC FRSBC FDSBC FRSBC tively. The filter...to mean square error d by as shown in Fig. 6, is used, yielding a total of 16 subbands. 255’ The rates, in bits per pixel ( bpp ), and the peak signal

Binary/Analog CCD Correlator Development.

DTIC Science & Technology

1981-07-01

architecture , design and performance of a general purpose, 1,024-stage, programmable transversal filter implemented in CCD/NMOS technology is described. The device features programmability of the reference signal, the filter length and weighting coefficient resolution. Off-ship circuitry is minimized by incorporating both analog and digital support circuitry, on-chip. This results in a monolithic analog signal processing system that has the flexibility to be operated in nine programmable configurations, from 1,024-stages by 1-bit, to 128-stages by 8-bits. The versatility

Rounding Technique for High-Speed Digital Signal Processing

NASA Technical Reports Server (NTRS)

Wechsler, E. R.

1983-01-01

Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.

A 14-bit 40-MHz analog front end for CCD application

NASA Astrophysics Data System (ADS)

Jingyu, Wang; Zhangming, Zhu; Shubin, Liu

2016-06-01

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8 × 4.8 mm2 and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit. Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033), the National High-Tech Program of China (No. 2013AA014103), and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302).

A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application

NASA Astrophysics Data System (ADS)

Roy, Sounak; Banerjee, Swapna

2018-03-01

This paper presents the design and implementation of a pipeline Analog-to-Digital Converter (ADC) for superheterodyne receiver application. Several enhancement techniques have been applied in implementing the ADC, in order to relax the target specifications of its building blocks. The concepts of time interleaving and double sampling have been used simultaneously to enhance the sampling speed and to reduce the number of amplifiers used in the ADC. Removal of a front end sample-and-hold amplifier is possible by employing dynamic comparators with switched capacitor based comparison of input signal and reference voltage. Each module of the ADC comprises two 2.5-bit stages followed by two 1.5-bit stages and a 3-bit flash stage. Four such pipeline ADC modules are time interleaved using two pairs of non-overlapping clock signals. These two pairs of clock signals are in phase quadrature with each other. Hence the term quadrature parallel pipeline ADC has been used. These configurations ensure that the entire ADC contains only eight operational-trans-conductance amplifiers. The ADC is implemented in a 0.18-μm CMOS process and supply voltage of 1.8 V. The proto-type is tested at sampling frequencies of 50 and 75 MSPS producing an Effective Number of Bits (ENOB) of 6.86- and 6.11-bits respectively. At peak sampling speed, the core ADC consumes only 65 mW of power.

A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application

NASA Astrophysics Data System (ADS)

Roy, Sounak; Banerjee, Swapna

2018-06-01

This paper presents the design and implementation of a pipeline Analog-to-Digital Converter (ADC) for superheterodyne receiver application. Several enhancement techniques have been applied in implementing the ADC, in order to relax the target specifications of its building blocks. The concepts of time interleaving and double sampling have been used simultaneously to enhance the sampling speed and to reduce the number of amplifiers used in the ADC. Removal of a front end sample-and-hold amplifier is possible by employing dynamic comparators with switched capacitor based comparison of input signal and reference voltage. Each module of the ADC comprises two 2.5-bit stages followed by two 1.5-bit stages and a 3-bit flash stage. Four such pipeline ADC modules are time interleaved using two pairs of non-overlapping clock signals. These two pairs of clock signals are in phase quadrature with each other. Hence the term quadrature parallel pipeline ADC has been used. These configurations ensure that the entire ADC contains only eight operational-trans-conductance amplifiers. The ADC is implemented in a 0.18-μm CMOS process and supply voltage of 1.8 V. The proto-type is tested at sampling frequencies of 50 and 75 MSPS producing an Effective Number of Bits (ENOB) of 6.86- and 6.11-bits respectively. At peak sampling speed, the core ADC consumes only 65 mW of power.

Chaos based encryption system for encrypting electroencephalogram signals.

PubMed

Lin, Chin-Feng; Shih, Shun-Han; Zhu, Jin-De

2014-05-01

In the paper, we use the Microsoft Visual Studio Development Kit and C# programming language to implement a chaos-based electroencephalogram (EEG) encryption system involving three encryption levels. A chaos logic map, initial value, and bifurcation parameter for the map were used to generate Level I chaos-based EEG encryption bit streams. Two encryption-level parameters were added to these elements to generate Level II chaos-based EEG encryption bit streams. An additional chaotic map and chaotic address index assignment process was used to implement the Level III chaos-based EEG encryption system. Eight 16-channel EEG Vue signals were tested using the encryption system. The encryption was the most rapid and robust in the Level III system. The test yielded superior encryption results, and when the correct deciphering parameter was applied, the EEG signals were completely recovered. However, an input parameter error (e.g., a 0.00001 % initial point error) causes chaotic encryption bit streams, preventing the recovery of 16-channel EEG Vue signals.

Robust High-Capacity Audio Watermarking Based on FFT Amplitude Modification

NASA Astrophysics Data System (ADS)

Fallahpour, Mehdi; Megías, David

This paper proposes a novel robust audio watermarking algorithm to embed data and extract it in a bit-exact manner based on changing the magnitudes of the FFT spectrum. The key point is selecting a frequency band for embedding based on the comparison between the original and the MP3 compressed/decompressed signal and on a suitable scaling factor. The experimental results show that the method has a very high capacity (about 5kbps), without significant perceptual distortion (ODG about -0.25) and provides robustness against common audio signal processing such as added noise, filtering and MPEG compression (MP3). Furthermore, the proposed method has a larger capacity (number of embedded bits to number of host bits rate) than recent image data hiding methods.

Experimental demonstration of real-time adaptively modulated DDO-OFDM systems with a high spectral efficiency up to 5.76bit/s/Hz transmission over SMF links.

PubMed

Chen, Ming; He, Jing; Tang, Jin; Wu, Xian; Chen, Lin

2014-07-28

In this paper, a FPGAs-based real-time adaptively modulated 256/64/16QAM-encoded base-band OFDM transceiver with a high spectral efficiency up to 5.76bit/s/Hz is successfully developed, and experimentally demonstrated in a simple intensity-modulated direct-detection optical communication system. Experimental results show that it is feasible to transmit a raw signal bit rate of 7.19Gbps adaptively modulated real-time optical OFDM signal over 20km and 50km single mode fibers (SMFs). The performance comparison between real-time and off-line digital signal processing is performed, and the results show that there is a negligible power penalty. In addition, to obtain the best transmission performance, direct-current (DC) bias voltage for MZM and launch power into optical fiber links are explored in the real-time optical OFDM systems.

Modular error embedding

DOEpatents

Sandford, II, Maxwell T.; Handel, Theodore G.; Ettinger, J. Mark

1999-01-01

A method of embedding auxiliary information into the digital representation of host data containing noise in the low-order bits. The method applies to digital data representing analog signals, for example digital images. The method reduces the error introduced by other methods that replace the low-order bits with auxiliary information. By a substantially reverse process, the embedded auxiliary data can be retrieved easily by an authorized user through use of a digital key. The modular error embedding method includes a process to permute the order in which the host data values are processed. The method doubles the amount of auxiliary information that can be added to host data values, in comparison with bit-replacement methods for high bit-rate coding. The invention preserves human perception of the meaning and content of the host data, permitting the addition of auxiliary data in the amount of 50% or greater of the original host data.

NbN A/D Conversion of IR Focal Plane Sensor Signal at 10 K

NASA Technical Reports Server (NTRS)

Eaton, L.; Durand, D.; Sandell, R.; Spargo, J.; Krabach, T.

1994-01-01

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.

Methodology and method and apparatus for signaling with capacity optimized constellations

NASA Technical Reports Server (NTRS)

Barsoum, Maged F. (Inventor); Jones, Christopher R. (Inventor)

2011-01-01

Communication systems having transmitter, includes a coder configured to receive user bits and output encoded bits at an expanded output encoded bit rate, a mapper configured to map encoded bits to symbols in a symbol constellation, a modulator configured to generate a signal for transmission via the communication channel using symbols generated by the mapper. In addition, the receiver includes a demodulator configured to demodulate the received signal via the communication channel, a demapper configured to estimate likelihoods from the demodulated signal, a decoder that is configured to estimate decoded bits from the likelihoods generated by the demapper. Furthermore, the symbol constellation is a capacity optimized geometrically spaced symbol constellation that provides a given capacity at a reduced signal-to-noise ratio compared to a signal constellation that maximizes d.sub.min.

Digital Ratiometer

NASA Technical Reports Server (NTRS)

Beer, R.

1985-01-01

Small, low-cost comparator with 24-bit-precision yields ratio signal from pair of analog or digital input signals. Arithmetic logic chips (bit-slice) sample two 24-bit analog-to-digital converters approximately once every millisecond and accumulate them in two 24-bit registers. Approach readily modified to arbitrary precision.

Two-dimensional signal processing using a morphological filter for holographic memory

NASA Astrophysics Data System (ADS)

Kondo, Yo; Shigaki, Yusuke; Yamamoto, Manabu

2012-03-01

Today, along with the wider use of high-speed information networks and multimedia, it is increasingly necessary to have higher-density and higher-transfer-rate storage devices. Therefore, research and development into holographic memories with three-dimensional storage areas is being carried out to realize next-generation large-capacity memories. However, in holographic memories, interference between bits, which affect the detection characteristics, occurs as a result of aberrations such as the deviation of a wavefront in an optical system. In this study, we pay particular attention to the nonlinear factors that cause bit errors, where filters with a Volterra equalizer and the morphologies are investigated as a means of signal processing.

Real-time Nyquist signaling with dynamic precision and flexible non-integer oversampling.

PubMed

Schmogrow, R; Meyer, M; Schindler, P C; Nebendahl, B; Dreschmann, M; Meyer, J; Josten, A; Hillerkuss, D; Ben-Ezra, S; Becker, J; Koos, C; Freude, W; Leuthold, J

2014-01-13

We demonstrate two efficient processing techniques for Nyquist signals, namely computation of signals using dynamic precision as well as arbitrary rational oversampling factors. With these techniques along with massively parallel processing it becomes possible to generate and receive high data rate Nyquist signals with flexible symbol rates and bandwidths, a feature which is highly desirable for novel flexgrid networks. We achieved maximum bit rates of 252 Gbit/s in real-time.

LDPC-PPM Coding Scheme for Optical Communication

NASA Technical Reports Server (NTRS)

Barsoum, Maged; Moision, Bruce; Divsalar, Dariush; Fitz, Michael

2009-01-01

In a proposed coding-and-modulation/demodulation-and-decoding scheme for a free-space optical communication system, an error-correcting code of the low-density parity-check (LDPC) type would be concatenated with a modulation code that consists of a mapping of bits to pulse-position-modulation (PPM) symbols. Hence, the scheme is denoted LDPC-PPM. This scheme could be considered a competitor of a related prior scheme in which an outer convolutional error-correcting code is concatenated with an interleaving operation, a bit-accumulation operation, and a PPM inner code. Both the prior and present schemes can be characterized as serially concatenated pulse-position modulation (SCPPM) coding schemes. Figure 1 represents a free-space optical communication system based on either the present LDPC-PPM scheme or the prior SCPPM scheme. At the transmitting terminal, the original data (u) are processed by an encoder into blocks of bits (a), and the encoded data are mapped to PPM of an optical signal (c). For the purpose of design and analysis, the optical channel in which the PPM signal propagates is modeled as a Poisson point process. At the receiving terminal, the arriving optical signal (y) is demodulated to obtain an estimate (a^) of the coded data, which is then processed by a decoder to obtain an estimate (u^) of the original data.

Bit-1 is an essential regulator of myogenic differentiation

PubMed Central

Griffiths, Genevieve S.; Doe, Jinger; Jijiwa, Mayumi; Van Ry, Pam; Cruz, Vivian; de la Vega, Michelle; Ramos, Joe W.; Burkin, Dean J.; Matter, Michelle L.

2015-01-01

Muscle differentiation requires a complex signaling cascade that leads to the production of multinucleated myofibers. Genes regulating the intrinsic mitochondrial apoptotic pathway also function in controlling cell differentiation. How such signaling pathways are regulated during differentiation is not fully understood. Bit-1 (also known as PTRH2) mutations in humans cause infantile-onset multisystem disease with muscle weakness. We demonstrate here that Bit-1 controls skeletal myogenesis through a caspase-mediated signaling pathway. Bit-1-null mice exhibit a myopathy with hypotrophic myofibers. Bit-1-null myoblasts prematurely express muscle-specific proteins. Similarly, knockdown of Bit-1 expression in C2C12 myoblasts promotes early differentiation, whereas overexpression delays differentiation. In wild-type mice, Bit-1 levels increase during differentiation. Bit-1-null myoblasts exhibited increased levels of caspase 9 and caspase 3 without increased apoptosis. Bit-1 re-expression partially rescued differentiation. In Bit-1-null muscle, Bcl-2 levels are reduced, suggesting that Bcl-2-mediated inhibition of caspase 9 and caspase 3 is decreased. Bcl-2 re-expression rescued Bit-1-mediated early differentiation in Bit-1-null myoblasts and C2C12 cells with knockdown of Bit-1 expression. These results support an unanticipated yet essential role for Bit-1 in controlling myogenesis through regulation of Bcl-2. PMID:25770104

Ciliates learn to diagnose and correct classical error syndromes in mating strategies

PubMed Central

Clark, Kevin B.

2013-01-01

Preconjugal ciliates learn classical repetition error-correction codes to safeguard mating messages and replies from corruption by “rivals” and local ambient noise. Because individual cells behave as memory channels with Szilárd engine attributes, these coding schemes also might be used to limit, diagnose, and correct mating-signal errors due to noisy intracellular information processing. The present study, therefore, assessed whether heterotrich ciliates effect fault-tolerant signal planning and execution by modifying engine performance, and consequently entropy content of codes, during mock cell–cell communication. Socially meaningful serial vibrations emitted from an ambiguous artificial source initiated ciliate behavioral signaling performances known to advertise mating fitness with varying courtship strategies. Microbes, employing calcium-dependent Hebbian-like decision making, learned to diagnose then correct error syndromes by recursively matching Boltzmann entropies between signal planning and execution stages via “power” or “refrigeration” cycles. All eight serial contraction and reversal strategies incurred errors in entropy magnitude by the execution stage of processing. Absolute errors, however, subtended expected threshold values for single bit-flip errors in three-bit replies, indicating coding schemes protected information content throughout signal production. Ciliate preparedness for vibrations selectively and significantly affected the magnitude and valence of Szilárd engine performance during modal and non-modal strategy corrective cycles. But entropy fidelity for all replies mainly improved across learning trials as refinements in engine efficiency. Fidelity neared maximum levels for only modal signals coded in resilient three-bit repetition error-correction sequences. Together, these findings demonstrate microbes can elevate survival/reproductive success by learning to implement classical fault-tolerant information processing in social contexts. PMID:23966987

Performance Analysis for Channel Estimation With 1-Bit ADC and Unknown Quantization Threshold

NASA Astrophysics Data System (ADS)

Stein, Manuel S.; Bar, Shahar; Nossek, Josef A.; Tabrikian, Joseph

2018-05-01

In this work, the problem of signal parameter estimation from measurements acquired by a low-complexity analog-to-digital converter (ADC) with $1$-bit output resolution and an unknown quantization threshold is considered. Single-comparator ADCs are energy-efficient and can be operated at ultra-high sampling rates. For analysis of such systems, a fixed and known quantization threshold is usually assumed. In the symmetric case, i.e., zero hard-limiting offset, it is known that in the low signal-to-noise ratio (SNR) regime the signal processing performance degrades moderately by ${2}/{\\pi}$ ($-1.96$ dB) when comparing to an ideal $\\infty$-bit converter. Due to hardware imperfections, low-complexity $1$-bit ADCs will in practice exhibit an unknown threshold different from zero. Therefore, we study the accuracy which can be obtained with receive data processed by a hard-limiter with unknown quantization level by using asymptotically optimal channel estimation algorithms. To characterize the estimation performance of these nonlinear algorithms, we employ analytic error expressions for different setups while modeling the offset as a nuisance parameter. In the low SNR regime, we establish the necessary condition for a vanishing loss due to missing offset knowledge at the receiver. As an application, we consider the estimation of single-input single-output wireless channels with inter-symbol interference and validate our analysis by comparing the analytic and experimental performance of the studied estimation algorithms. Finally, we comment on the extension to multiple-input multiple-output channel models.

Universal Decoder for PPM of any Order

NASA Technical Reports Server (NTRS)

Moision, Bruce E.

2010-01-01

A recently developed algorithm for demodulation and decoding of a pulse-position- modulation (PPM) signal is suitable as a basis for designing a single hardware decoding apparatus to be capable of handling any PPM order. Hence, this algorithm offers advantages of greater flexibility and lower cost, in comparison with prior such algorithms, which necessitate the use of a distinct hardware implementation for each PPM order. In addition, in comparison with the prior algorithms, the present algorithm entails less complexity in decoding at large orders. An unavoidably lengthy presentation of background information, including definitions of terms, is prerequisite to a meaningful summary of this development. As an aid to understanding, the figure illustrates the relevant processes of coding, modulation, propagation, demodulation, and decoding. An M-ary PPM signal has M time slots per symbol period. A pulse (signifying 1) is transmitted during one of the time slots; no pulse (signifying 0) is transmitted during the other time slots. The information intended to be conveyed from the transmitting end to the receiving end of a radio or optical communication channel is a K-bit vector u. This vector is encoded by an (N,K) binary error-correcting code, producing an N-bit vector a. In turn, the vector a is subdivided into blocks of m = log2(M) bits and each such block is mapped to an M-ary PPM symbol. The resultant coding/modulation scheme can be regarded as equivalent to a nonlinear binary code. The binary vector of PPM symbols, x is transmitted over a Poisson channel, such that there is obtained, at the receiver, a Poisson-distributed photon count characterized by a mean background count nb during no-pulse time slots and a mean signal-plus-background count of ns+nb during a pulse time slot. In the receiver, demodulation of the signal is effected in an iterative soft decoding process that involves consideration of relationships among photon counts and conditional likelihoods of m-bit vectors of coded bits. Inasmuch as the likelihoods of all the m-bit vectors of coded bits mapping to the same PPM symbol are correlated, the best performance is obtained when the joint mbit conditional likelihoods are utilized. Unfortunately, the complexity of decoding, measured in the number of operations per bit, grows exponentially with m, and can thus become prohibitively expensive for large PPM orders. For a system required to handle multiple PPM orders, the cost is even higher because it is necessary to have separate decoding hardware for each order. This concludes the prerequisite background information. In the present algorithm, the decoding process as described above is modified by, among other things, introduction of an lbit marginalizer sub-algorithm. The term "l-bit marginalizer" signifies that instead of m-bit conditional likelihoods, the decoder computes l-bit conditional likelihoods, where l is fixed. Fixing l, regardless of the value of m, makes it possible to use a single hardware implementation for any PPM order. One could minimize the decoding complexity and obtain an especially simple design by fixing l at 1, but this would entail some loss of performance. An intermediate solution is to fix l at some value, greater than 1, that may be less than or greater than m. This solution makes it possible to obtain the desired flexibility to handle any PPM order while compromising between complexity and loss of performance.

640-Gbit/s fast physical random number generation using a broadband chaotic semiconductor laser

NASA Astrophysics Data System (ADS)

Zhang, Limeng; Pan, Biwei; Chen, Guangcan; Guo, Lu; Lu, Dan; Zhao, Lingjuan; Wang, Wei

2017-04-01

An ultra-fast physical random number generator is demonstrated utilizing a photonic integrated device based broadband chaotic source with a simple post data processing method. The compact chaotic source is implemented by using a monolithic integrated dual-mode amplified feedback laser (AFL) with self-injection, where a robust chaotic signal with RF frequency coverage of above 50 GHz and flatness of ±3.6 dB is generated. By using 4-least significant bits (LSBs) retaining from the 8-bit digitization of the chaotic waveform, random sequences with a bit-rate up to 640 Gbit/s (160 GS/s × 4 bits) are realized. The generated random bits have passed each of the fifteen NIST statistics tests (NIST SP800-22), indicating its randomness for practical applications.

A novel frame-level constant-distortion bit allocation for smooth H.264/AVC video quality

NASA Astrophysics Data System (ADS)

Liu, Li; Zhuang, Xinhua

2009-01-01

It is known that quality fluctuation has a major negative effect on visual perception. In previous work, we introduced a constant-distortion bit allocation method [1] for H.263+ encoder. However, the method in [1] can not be adapted to the newest H.264/AVC encoder directly as the well-known chicken-egg dilemma resulted from the rate-distortion optimization (RDO) decision process. To solve this problem, we propose a new two stage constant-distortion bit allocation (CDBA) algorithm with enhanced rate control for H.264/AVC encoder. In stage-1, the algorithm performs RD optimization process with a constant quantization QP. Based on prediction residual signals from stage-1 and target distortion for smooth video quality purpose, the frame-level bit target is allocated by using a close-form approximations of ratedistortion relationship similar to [1], and a fast stage-2 encoding process is performed with enhanced basic unit rate control. Experimental results show that, compared with original rate control algorithm provided by H.264/AVC reference software JM12.1, the proposed constant-distortion frame-level bit allocation scheme reduces quality fluctuation and delivers much smoother PSNR on all testing sequences.

Digital Signal Processing For Low Bit Rate TV Image Codecs

NASA Astrophysics Data System (ADS)

Rao, K. R.

1987-06-01

In view of the 56 KBPS digital switched network services and the ISDN, low bit rate codecs for providing real time full motion color video are under various stages of development. Some companies have already brought the codecs into the market. They are being used by industry and some Federal Agencies for video teleconferencing. In general, these codecs have various features such as multiplexing audio and data, high resolution graphics, encryption, error detection and correction, self diagnostics, freezeframe, split video, text overlay etc. To transmit the original color video on a 56 KBPS network requires bit rate reduction of the order of 1400:1. Such a large scale bandwidth compression can be realized only by implementing a number of sophisticated,digital signal processing techniques. This paper provides an overview of such techniques and outlines the newer concepts that are being investigated. Before resorting to the data compression techniques, various preprocessing operations such as noise filtering, composite-component transformation and horizontal and vertical blanking interval removal are to be implemented. Invariably spatio-temporal subsampling is achieved by appropriate filtering. Transform and/or prediction coupled with motion estimation and strengthened by adaptive features are some of the tools in the arsenal of the data reduction methods. Other essential blocks in the system are quantizer, bit allocation, buffer, multiplexer, channel coding etc.

Averaging of phase noise in PSK signals by an opto-electrical feed-forward circuit

NASA Astrophysics Data System (ADS)

Inoue, K.; Ohta, M.

2013-10-01

This paper proposes an opto-electrical feed-forward circuit that reduces phase noise in binary PSK signals by averaging the noise. Random and independent phase noise is averaged over several bit slots by externally modulating a phase-fluctuating PSK signal with feed-forward signal obtained from signal processing of the outputs of delay interferometers. The simulation results demonstrate a reduction in the phase noise.

Multi-channel time-reversal receivers for multi and 1-bit implementations

DOEpatents

Candy, James V.; Chambers, David H.; Guidry, Brian L.; Poggio, Andrew J.; Robbins, Christopher L.

2008-12-09

A communication system for transmitting a signal through a channel medium comprising digitizing the signal, time-reversing the digitized signal, and transmitting the signal through the channel medium. In one embodiment a transmitter is adapted to transmit the signal, a multiplicity of receivers are adapted to receive the signal, a digitizer digitizes the signal, and a time-reversal signal processor is adapted to time-reverse the digitized signal. An embodiment of the present invention includes multi bit implementations. Another embodiment of the present invention includes 1-bit implementations. Another embodiment of the present invention includes a multiplicity of receivers used in the step of transmitting the signal through the channel medium.

Real-time implementation of second generation of audio multilevel information coding

NASA Astrophysics Data System (ADS)

Ali, Murtaza; Tewfik, Ahmed H.; Viswanathan, V.

1994-03-01

This paper describes real-time implementation of a novel wavelet- based audio compression method. This method is based on the discrete wavelet (DWT) representation of signals. A bit allocation procedure is used to allocate bits to the transform coefficients in an adaptive fashion. The bit allocation procedure has been designed to take advantage of the masking effect in human hearing. The procedure minimizes the number of bits required to represent each frame of audio signals at a fixed distortion level. The real-time implementation provides almost transparent compression of monophonic CD quality audio signals (samples at 44.1 KHz and quantized using 16 bits/sample) at bit rates of 64-78 Kbits/sec. Our implementation uses two ASPI Elf boards, each of which is built around a TI TMS230C31 DSP chip. The time required for encoding of a mono CD signal is about 92 percent of real time and that for decoding about 61 percent.

Compact FPGA-based beamformer using oversampled 1-bit A/D converters.

PubMed

Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

2005-05-01

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

Signal chain for the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS)

NASA Technical Reports Server (NTRS)

Bunn, James S., Jr.

1988-01-01

The AVIRIS instrument has a separate dedicated analog signal processing chain for each of its four spectrometers. The signal chains amplify low-level focal-plane line array signals (5 to 10 mV full-scale span) in the presence of larger multiplexing signals (approx 150 mV) providing the data handling system a ten-bit digital word (for each spectrometer) each 1.3 microns. This signal chain provides automatic correction for the line array dark signal nonuniformity (which can approach the full-scale signal span).

Signal chain for the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS)

NASA Technical Reports Server (NTRS)

Bunn, James S., Jr.

1987-01-01

The AVIRIS instrument has a separate dedicated analog signal processing chain for each of its four spectrometers. The signal chains amplify low-level focal-plane line array signals (5 to 10 mV full-scale span) in the presence of larger multiplexing signals (approx 150 mV) providing the data handling system a ten-bit digital word (for each spectrometer) each 1.3 microns. This signal chain provides automatic correction for the line array dark signal nonuniformity (which can approach the full-scale signal span).

Hybrid spread spectrum radio system

DOEpatents

Smith, Stephen F.; Dress, William B.

2010-02-02

Systems and methods are described for hybrid spread spectrum radio systems. A method includes modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control an amplification circuit that provides a gain to the signal. Another method includes: modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control a fast hopping frequency synthesizer; and fast frequency hopping the signal with the fast hopping frequency synthesizer, wherein multiple frequency hops occur within a single data-bit time.

Analog Signal Correlating Using an Analog-Based Signal Conditioning Front End

NASA Technical Reports Server (NTRS)

Prokop, Norman; Krasowski, Michael

2013-01-01

This innovation is capable of correlating two analog signals by using an analog-based signal conditioning front end to hard-limit the analog signals through adaptive thresholding into a binary bit stream, then performing the correlation using a Hamming "similarity" calculator function embedded in a one-bit digital correlator (OBDC). By converting the analog signal into a bit stream, the calculation of the correlation function is simplified, and less hardware resources are needed. This binary representation allows the hardware to move from a DSP where instructions are performed serially, into digital logic where calculations can be performed in parallel, greatly speeding up calculations.

A bunch to bucket phase detector for the RHIC LLRF upgrade platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, K.S.; Harvey, M.; Hayes, T.

2011-03-28

As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overallmore » LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array (FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more. The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.« less

Hardware multiplier processor

DOEpatents

Pierce, Paul E.

1986-01-01

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Hardware multiplier processor

DOEpatents

Pierce, P.E.

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

S-EMG signal compression based on domain transformation and spectral shape dynamic bit allocation

PubMed Central

2014-01-01

Background Surface electromyographic (S-EMG) signal processing has been emerging in the past few years due to its non-invasive assessment of muscle function and structure and because of the fast growing rate of digital technology which brings about new solutions and applications. Factors such as sampling rate, quantization word length, number of channels and experiment duration can lead to a potentially large volume of data. Efficient transmission and/or storage of S-EMG signals are actually a research issue. That is the aim of this work. Methods This paper presents an algorithm for the data compression of surface electromyographic (S-EMG) signals recorded during isometric contractions protocol and during dynamic experimental protocols such as the cycling activity. The proposed algorithm is based on discrete wavelet transform to proceed spectral decomposition and de-correlation, on a dynamic bit allocation procedure to code the wavelets transformed coefficients, and on an entropy coding to minimize the remaining redundancy and to pack all data. The bit allocation scheme is based on mathematical decreasing spectral shape models, which indicates a shorter digital word length to code high frequency wavelets transformed coefficients. Four bit allocation spectral shape methods were implemented and compared: decreasing exponential spectral shape, decreasing linear spectral shape, decreasing square-root spectral shape and rotated hyperbolic tangent spectral shape. Results The proposed method is demonstrated and evaluated for an isometric protocol and for a dynamic protocol using a real S-EMG signal data bank. Objective performance evaluations metrics are presented. In addition, comparisons with other encoders proposed in scientific literature are shown. Conclusions The decreasing bit allocation shape applied to the quantized wavelet coefficients combined with arithmetic coding results is an efficient procedure. The performance comparisons of the proposed S-EMG data compression algorithm with the established techniques found in scientific literature have shown promising results. PMID:24571620

Simplified OMEGA receivers

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1974-01-01

The details are presented of methods for providing OMEGA navigational information including the receiver problem at the antenna and informational display and housekeeping systems based on some 4 bit data processing concepts. Topics discussed include the problem of limiters, zero crossing detectors, signal envelopes, internal timing circuits, phase counters, lane position displays, signal integrators, and software mapping problems.

A Modified Differential Coherent Bit Synchronization Algorithm for BeiDou Weak Signals with Large Frequency Deviation.

PubMed

Han, Zhifeng; Liu, Jianye; Li, Rongbing; Zeng, Qinghua; Wang, Yi

2017-07-04

BeiDou system navigation messages are modulated with a secondary NH (Neumann-Hoffman) code of 1 kbps, where frequent bit transitions limit the coherent integration time to 1 millisecond. Therefore, a bit synchronization algorithm is necessary to obtain bit edges and NH code phases. In order to realize bit synchronization for BeiDou weak signals with large frequency deviation, a bit synchronization algorithm based on differential coherent and maximum likelihood is proposed. Firstly, a differential coherent approach is used to remove the effect of frequency deviation, and the differential delay time is set to be a multiple of bit cycle to remove the influence of NH code. Secondly, the maximum likelihood function detection is used to improve the detection probability of weak signals. Finally, Monte Carlo simulations are conducted to analyze the detection performance of the proposed algorithm compared with a traditional algorithm under the CN0s of 20~40 dB-Hz and different frequency deviations. The results show that the proposed algorithm outperforms the traditional method with a frequency deviation of 50 Hz. This algorithm can remove the effect of BeiDou NH code effectively and weaken the influence of frequency deviation. To confirm the feasibility of the proposed algorithm, real data tests are conducted. The proposed algorithm is suitable for BeiDou weak signal bit synchronization with large frequency deviation.

CMOS Bit-Stream Band-Pass Beamforming

DTIC Science & Technology

2016-03-31

unlimited. with direct IF sampling, most of the signal processing, including digital down-conversion ( DDC ), is carried out in the digital domain, and I/Q...level digitized signals are directly processed without decimation filtering for I/Q DDC and phase shifting. This novel BSP approach replaces bulky...positive feedback. The resonator center frequency of fs/4 (260MHz) simplifies the design of DDC . 4b tunable capacitors adjust the center frequency

Frequency domain laser velocimeter signal processor: A new signal processing scheme

NASA Technical Reports Server (NTRS)

Meyers, James F.; Clemmons, James I., Jr.

1987-01-01

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a smart instrument that is able to configure itself, based on the characteristics of the input signals, for optimum measurement accuracy. The signal processor is composed of a high-speed 2-bit transient recorder for signal capture and a combination of adaptive digital filters with energy and/or zero crossing detection signal processing. The system is designed to accept signals with frequencies up to 100 MHz with standard deviations up to 20 percent of the average signal frequency. Results from comparative simulation studies indicate measurement accuracies 2.5 times better than with a high-speed burst counter, from signals with as few as 150 photons per burst.

Serial data correlator/code translator

NASA Technical Reports Server (NTRS)

Morgan, L. E. (Inventor)

1982-01-01

A system for analyzing asynchronous signals containing bits of information for ensuring the validity of said signals, by sampling each bit of information a plurality of times, and feeding the sampled pieces of bits of information into a sequence controlled is described. The sequence controller has a plurality of maps or programs through which the sampled pieces of bits are stepped so as to identify the particular bit of information and determine the validity and phase of the bit. The step in which the sequence controller is clocked is controlled by a storage register. A data decoder decodes the information fed out of the storage register and feeds such information to shift registers for storage.

A mixed signal ECG processing platform with an adaptive sampling ADC for portable monitoring applications.

PubMed

Kim, Hyejung; Van Hoof, Chris; Yazicioglu, Refet Firat

2011-01-01

This paper describes a mixed-signal ECG processing platform with an 12-bit ADC architecture that can adapt its sampling rate according to the input signals rate of change. This enables the sampling of ECG signals with significantly reduced data rate without loss of information. The presented adaptive sampling scheme reduces the ADC power consumption, enables the processing of ECG signals with lower power consumption, and reduces the power consumption of the radio while streaming the ECG signals. The test results show that running a CWT-based R peak detection algorithm using the adaptively sampled ECG signals consumes only 45.6 μW and it leads to 36% less overall system power consumption.

Shuttle bit rate synchronizer. [signal to noise ratios and error analysis

NASA Technical Reports Server (NTRS)

Huey, D. C.; Fultz, G. L.

1974-01-01

A shuttle bit rate synchronizer brassboard unit was designed, fabricated, and tested, which meets or exceeds the contractual specifications. The bit rate synchronizer operates at signal-to-noise ratios (in a bit rate bandwidth) down to -5 dB while exhibiting less than 0.6 dB bit error rate degradation. The mean acquisition time was measured to be less than 2 seconds. The synchronizer is designed around a digital data transition tracking loop whose phase and data detectors are integrate-and-dump filters matched to the Manchester encoded bits specified. It meets the reliability (no adjustments or tweaking) and versatility (multiple bit rates) of the shuttle S-band communication system through an implementation which is all digital after the initial stage of analog AGC and A/D conversion.

Downhole telemetry system

DOEpatents

Normann, R.A.; Kadlec, E.R.

1994-11-08

A downhole telemetry system is described for optically communicating to the surface operating parameters of a drill bit during ongoing drilling operations. The downhole telemetry system includes sensors mounted with a drill bit for monitoring at least one operating parameter of the drill bit and generating a signal representative thereof. The downhole telemetry system includes means for transforming and optically communicating the signal to the surface as well as means at the surface for producing a visual display of the optically communicated operating parameters of the drill bit. 7 figs.

Downhole telemetry system

DOEpatents

Normann, Randy A.; Kadlec, Emil R.

1994-01-01

A downhole telemetry system is described for optically communicating to the surface operating parameters of a drill bit during ongoing drilling operations. The downhole telemetry system includes sensors mounted with a drill bit for monitoring at least one operating parameter of the drill bit and generating a signal representative thereof. The downhole telemetry system includes means for transforming and optically communicating the signal to the surface as well as means at the surface for producing a visual display of the optically communicated operating parameters of the drill bit.

Selective data segment monitoring system. [using shift registers

NASA Technical Reports Server (NTRS)

Wirth, M. N. (Inventor)

1976-01-01

High speed data monitoring apparatus is described for displaying the bit pattern of a selected portion of a block of transmitted data comprising a shift register for receiving the transmitted data and for temporarily containing the consecutive data bits. A programmable sync detector for monitoring the contents of the shift register and for generating a sync signal when the shift register contains a predetermined sync code is included. A counter is described for counting the data bits input to the shift register after the sync signal is generated and for generating a count complete signal when a selected number of data bits have been input to the register. A data storage device is used for storing the contents of the shift register at the time the count complete signal is generated.

Secure Communication via a Recycling of Attenuated Classical Signals

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, IV, Amos M.

We describe a simple method of interleaving a classical and quantum signal in a secure communication system at a single wavelength. The system transmits data encrypted via a one-time pad on a classical signal and produces a single-photon reflection of the encrypted signal. This attenuated signal can be used to observe eavesdroppers and produce fresh secret bits. The system can be secured against eavesdroppers, detect simple tampering or classical bit errors, produces more secret bits than it consumes, and does not require any entanglement or complex wavelength division multiplexing, thus, making continuous secure two-way communication via one-time pads practical.

Secure Communication via a Recycling of Attenuated Classical Signals

DOE PAGES

Smith, IV, Amos M.

2017-01-12

We describe a simple method of interleaving a classical and quantum signal in a secure communication system at a single wavelength. The system transmits data encrypted via a one-time pad on a classical signal and produces a single-photon reflection of the encrypted signal. This attenuated signal can be used to observe eavesdroppers and produce fresh secret bits. The system can be secured against eavesdroppers, detect simple tampering or classical bit errors, produces more secret bits than it consumes, and does not require any entanglement or complex wavelength division multiplexing, thus, making continuous secure two-way communication via one-time pads practical.

Coherent detection and digital signal processing for fiber optic communications

NASA Astrophysics Data System (ADS)

Ip, Ezra

The drive towards higher spectral efficiency in optical fiber systems has generated renewed interest in coherent detection. We review different detection methods, including noncoherent, differentially coherent, and coherent detection, as well as hybrid detection methods. We compare the modulation methods that are enabled and their respective performances in a linear regime. An important system parameter is the number of degrees of freedom (DOF) utilized in transmission. Polarization-multiplexed quadrature-amplitude modulation maximizes spectral efficiency and power efficiency as it uses all four available DOF contained in the two field quadratures in the two polarizations. Dual-polarization homodyne or heterodyne downconversion are linear processes that can fully recover the received signal field in these four DOF. When downconverted signals are sampled at the Nyquist rate, compensation of transmission impairments can be performed using digital signal processing (DSP). Software based receivers benefit from the robustness of DSP, flexibility in design, and ease of adaptation to time-varying channels. Linear impairments, including chromatic dispersion (CD) and polarization-mode dispersion (PMD), can be compensated quasi-exactly using finite impulse response filters. In practical systems, sampling the received signal at 3/2 times the symbol rate is sufficient to enable an arbitrary amount of CD and PMD to be compensated for a sufficiently long equalizer whose tap length scales linearly with transmission distance. Depending on the transmitted constellation and the target bit error rate, the analog-to-digital converter (ADC) should have around 5 to 6 bits of resolution. Digital coherent receivers are naturally suited for the implementation of feedforward carrier recovery, which has superior linewidth tolerance than phase-locked loops, and does not suffer from feedback delay constraints. Differential bit encoding can be used to prevent catastrophic receiver failure due to cycle slips. In systems where nonlinear effects are concentrated mostly at fiber locations with small accumulated dispersion, nonlinear phase de-rotation is a low-complexity algorithm that can partially mitigate nonlinear effects. For systems with arbitrary dispersion maps, however, backpropagation is the only universal technique that can jointly compensate dispersion and fiber nonlinearity. Backpropagation requires solving the nonlinear Schrodinger equation at the receiver, and has high computational cost. Backpropagation is most effective when dispersion compensation fibers are removed, and when signal processing is performed at three times oversampling. Backpropagation can improve system performance and increase transmission distance. With anticipated advances in analog-to-digital converters and integrated circuit technology, DSP-based coherent receivers at bit rates up to 100 Gb/s should become practical in the near future.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

Navigation Using Orthogonal Frequency Division Multiplexed Signals of Opportunity

DTIC Science & Technology

2007-09-01

transmits a 32,767 bit pseudo -random “short” code that repeats 37.5 times per second. Since the pseudo -random bit pattern and modulation scheme are... correlation process takes two “ sample windows,” both of which are ν = 16 samples wide and are spaced N = 64 samples apart, and compares them. When the...technique in (3.4) is a necessary step in order to get a more accurate estimate of the sample shift from the symbol boundary correlator in (3.1). Figure

A compact presentation of DSN array telemetry performance

NASA Technical Reports Server (NTRS)

Greenhall, C. A.

1982-01-01

The telemetry performance of an arrayed receiver system, including radio losses, is often given by a family of curves giving bit error rate vs bit SNR, with tracking loop SNR at one receiver held constant along each curve. This study shows how to process this information into a more compact, useful format in which the minimal total signal power and optimal carrier suppression, for a given fixed bit error rate, are plotted vs data rate. Examples for baseband-only combining are given. When appropriate dimensionless variables are used for plotting, receiver arrays with different numbers of antennas and different threshold tracking loop bandwidths look much alike, and a universal curve for optimal carrier suppression emerges.

On-chip integratable all-optical quantizer using strong cross-phase modulation in a silicon-organic hybrid slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Sang, Xinzhu; Wang, Kuiru; Wu, Qiang; Yan, Binbin; Li, Feng; Zhou, Xian; Zhong, Kangping; Zhou, Guiyao; Yu, Chongxiu; Farrell, Gerald; Lu, Chao; Yaw Tam, Hwa; Wai, P. K. A.

2016-01-01

High performance all-optical quantizer based on silicon waveguide is believed to have significant applications in photonic integratable optical communication links, optical interconnection networks, and real-time signal processing systems. In this paper, we propose an integratable all-optical quantizer for on-chip and low power consumption all-optical analog-to-digital converters. The quantization is realized by the strong cross-phase modulation and interference in a silicon-organic hybrid (SOH) slot waveguide based Mach-Zehnder interferometer. By carefully designing the dimension of the SOH waveguide, large nonlinear coefficients up to 16,000 and 18,069 W−1/m for the pump and probe signals can be obtained respectively, along with a low pulse walk-off parameter of 66.7 fs/mm, and all-normal dispersion in the wavelength regime considered. Simulation results show that the phase shift of the probe signal can reach 8π at a low pump pulse peak power of 206 mW and propagation length of 5 mm such that a 4-bit all-optical quantizer can be realized. The corresponding signal-to-noise ratio is 23.42 dB and effective number of bit is 3.89-bit. PMID:26777054

Effect of atmospheric turbulence on the bit error probability of a space to ground near infrared laser communications link using binary pulse position modulation and an avalanche photodiode detector

NASA Technical Reports Server (NTRS)

Safren, H. G.

1987-01-01

The effect of atmospheric turbulence on the bit error rate of a space-to-ground near infrared laser communications link is investigated, for a link using binary pulse position modulation and an avalanche photodiode detector. Formulas are presented for the mean and variance of the bit error rate as a function of signal strength. Because these formulas require numerical integration, they are of limited practical use. Approximate formulas are derived which are easy to compute and sufficiently accurate for system feasibility studies, as shown by numerical comparison with the exact formulas. A very simple formula is derived for the bit error rate as a function of signal strength, which requires only the evaluation of an error function. It is shown by numerical calculations that, for realistic values of the system parameters, the increase in the bit error rate due to turbulence does not exceed about thirty percent for signal strengths of four hundred photons per bit or less. The increase in signal strength required to maintain an error rate of one in 10 million is about one or two tenths of a db.

All-optical clock recovery, photonic balancing, and saturated asymmetric filtering for fiber optic communication systems

NASA Astrophysics Data System (ADS)

Parsons, Earl Ryan

In this dissertation I investigated a multi-channel and multi-bit rate all-optical clock recovery device. This device, a birefringent Fabry-Perot resonator, had previously been demonstrated to simultaneously recover the clock signal from 10 wavelength channels operating at 10 Gb/s and one channel at 40 Gb/s. Similar to clock signals recovered from a conventional Fabry-Perot resonator, the clock signal from the birefringent resonator suffers from a bit pattern effect. I investigated this bit pattern effect for birefringent resonators numerically and experimentally and found that the bit pattern effect is less prominent than for clock signals from a conventional Fabry-Perot resonator. I also demonstrated photonic balancing which is an all-optical alternative to electrical balanced detection for phase shift keyed signals. An RZ-DPSK data signal was demodulated using a delay interferometer. The two logically opposite outputs from the delay interferometer then counter-propagated in a saturated SOA. This process created a differential signal which used all the signal power present in two consecutive symbols. I showed that this scheme could provide an optical alternative to electrical balanced detection by reducing the required OSNR by 3 dB. I also show how this method can provide amplitude regeneration to a signal after modulation format conversion. In this case an RZ-DPSK signal was converted to an amplitude modulation signal by the delay interferometer. The resulting amplitude modulated signal is degraded by both the amplitude noise and the phase noise of the original signal. The two logically opposite outputs from the delay interferometer again counter-propagated in a saturated SOA. Through limiting amplification and noise modulation this scheme provided amplitude regeneration and improved the Q-factor of the demodulated signal by 3.5 dB. Finally I investigated how SPM provided by the SOA can provide a method to reduce the in-band noise of a communication signal. The marks, which represented data, experienced a spectral shift due to SPM while the spaces, which consisted of noise, did not. A bandpass filter placed after the SOA then selected the signal and filtered out what was originally in-band noise. The receiver sensitivity was improved by 3 dB.

Accurate estimation of camera shot noise in the real-time

NASA Astrophysics Data System (ADS)

Cheremkhin, Pavel A.; Evtikhiev, Nikolay N.; Krasnov, Vitaly V.; Rodin, Vladislav G.; Starikov, Rostislav S.

2017-10-01

Nowadays digital cameras are essential parts of various technological processes and daily tasks. They are widely used in optics and photonics, astronomy, biology and other various fields of science and technology such as control systems and video-surveillance monitoring. One of the main information limitations of photo- and videocameras are noises of photosensor pixels. Camera's photosensor noise can be divided into random and pattern components. Temporal noise includes random noise component while spatial noise includes pattern noise component. Temporal noise can be divided into signal-dependent shot noise and signal-nondependent dark temporal noise. For measurement of camera noise characteristics, the most widely used methods are standards (for example, EMVA Standard 1288). It allows precise shot and dark temporal noise measurement but difficult in implementation and time-consuming. Earlier we proposed method for measurement of temporal noise of photo- and videocameras. It is based on the automatic segmentation of nonuniform targets (ASNT). Only two frames are sufficient for noise measurement with the modified method. In this paper, we registered frames and estimated shot and dark temporal noises of cameras consistently in the real-time. The modified ASNT method is used. Estimation was performed for the cameras: consumer photocamera Canon EOS 400D (CMOS, 10.1 MP, 12 bit ADC), scientific camera MegaPlus II ES11000 (CCD, 10.7 MP, 12 bit ADC), industrial camera PixeLink PL-B781F (CMOS, 6.6 MP, 10 bit ADC) and video-surveillance camera Watec LCL-902C (CCD, 0.47 MP, external 8 bit ADC). Experimental dependencies of temporal noise on signal value are in good agreement with fitted curves based on a Poisson distribution excluding areas near saturation. Time of registering and processing of frames used for temporal noise estimation was measured. Using standard computer, frames were registered and processed during a fraction of second to several seconds only. Also the accuracy of the obtained temporal noise values was estimated.

Compressed sensing system considerations for ECG and EMG wireless biosensors.

PubMed

Dixon, Anna M R; Allstot, Emily G; Gangopadhyay, Daibashish; Allstot, David J

2012-04-01

Compressed sensing (CS) is an emerging signal processing paradigm that enables sub-Nyquist processing of sparse signals such as electrocardiogram (ECG) and electromyogram (EMG) biosignals. Consequently, it can be applied to biosignal acquisition systems to reduce the data rate to realize ultra-low-power performance. CS is compared to conventional and adaptive sampling techniques and several system-level design considerations are presented for CS acquisition systems including sparsity and compression limits, thresholding techniques, encoder bit-precision requirements, and signal recovery algorithms. Simulation studies show that compression factors greater than 16X are achievable for ECG and EMG signals with signal-to-quantization noise ratios greater than 60 dB.

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

NASA Astrophysics Data System (ADS)

Bugiel, Sz.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kuczynska, M.; Moron, J.; Swientek, K.; Szumlak, T.

2016-02-01

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

Design of MOEMS adjustable optical delay line to reduce link set-up time in a tera-bit/s optical interconnection network.

PubMed

Jing, Wencai; Zhang, Yimo; Zhou, Ge

2002-07-15

A new structure for bit synchronization in a tera-bit/s optical interconnection network has been designed using micro-electro-mechanical system (MEMS) technique. Link multiplexing has been adopted to reduce data packet communication latency. To eliminate link set-up time, adjustable optical delay lines (AODLs) have been adopted to shift the phases of the distributed optical clock signals for bit synchronization. By changing the optical path distance of the optical clock signal, the phase of the clock signal can be shifted at a very high resolution. A phase-shift resolution of 0.1 ps can be easily achieved with 30-microm alternation of the optical path length in vacuum.

Generation of Custom DSP Transform IP Cores: Case Study Walsh-Hadamard Transform

DTIC Science & Technology

2002-09-01

mathematics and hardware design What I know: Finite state machine Pipelining Systolic array … What I know: Linear algebra Digital signal processing...state machine Pipelining Systolic array … What I know: Linear algebra Digital signal processing Adaptive filter theory … A math guy A hardware engineer...Synthesis Technology Libary Bit-width (8) HF factor (1,2,3,6) VF factor (1,2,4, ... 32) Xilinx FPGA Place&Route Xilinx FPGA Place&Route Performance

The application of digital signal processing techniques to a teleoperator radar system

NASA Technical Reports Server (NTRS)

Pujol, A.

1982-01-01

A digital signal processing system was studied for the determination of the spectral frequency distribution of echo signals from a teleoperator radar system. The system consisted of a sample and hold circuit, an analog to digital converter, a digital filter, and a Fast Fourier Transform. The system is interfaced to a 16 bit microprocessor. The microprocessor is programmed to control the complete digital signal processing. The digital filtering and Fast Fourier Transform functions are implemented by a S2815 digital filter/utility peripheral chip and a S2814A Fast Fourier Transform chip. The S2815 initially simulates a low-pass Butterworth filter with later expansion to complete filter circuit (bandpass and highpass) synthesizing.

Interferometric architectures based All-Optical logic design methods and their implementations

NASA Astrophysics Data System (ADS)

Singh, Karamdeep; Kaur, Gurmeet

2015-06-01

All-Optical Signal Processing is an emerging technology which can avoid costly Optical-electronic-optical (O-E-O) conversions which are usually compulsory in traditional Electronic Signal Processing systems, thus greatly enhancing operating bit rate with some added advantages such as electro-magnetic interference immunity and low power consumption etc. In order to implement complex signal processing tasks All-Optical logic gates are required as backbone elements. This review describes the advances in the field of All-Optical logic design methods based on interferometric architectures such as Mach-Zehnder Interferometer (MZI), Sagnac Interferometers and Ultrafast Non-Linear Interferometer (UNI). All-Optical logic implementations for realization of arithmetic and signal processing applications based on each interferometric arrangement are also presented in a categorized manner.

Threshold detection in an on-off binary communications channel with atmospheric scintillation

NASA Technical Reports Server (NTRS)

Webb, W. E.; Marino, J. T., Jr.

1974-01-01

The optimum detection threshold in an on-off binary optical communications system operating in the presence of atmospheric turbulence was investigated assuming a poisson detection process and log normal scintillation. The dependence of the probability of bit error on log amplitude variance and received signal strength was analyzed and semi-emperical relationships to predict the optimum detection threshold derived. On the basis of this analysis a piecewise linear model for an adaptive threshold detection system is presented. Bit error probabilities for non-optimum threshold detection system were also investigated.

Threshold detection in an on-off binary communications channel with atmospheric scintillation

NASA Technical Reports Server (NTRS)

Webb, W. E.

1975-01-01

The optimum detection threshold in an on-off binary optical communications system operating in the presence of atmospheric turbulence was investigated assuming a poisson detection process and log normal scintillation. The dependence of the probability of bit error on log amplitude variance and received signal strength was analyzed and semi-empirical relationships to predict the optimum detection threshold derived. On the basis of this analysis a piecewise linear model for an adaptive threshold detection system is presented. The bit error probabilities for nonoptimum threshold detection systems were also investigated.

Method and apparatus for a single channel digital communications system. [synchronization of received PCM signal by digital correlation with reference signal

NASA Technical Reports Server (NTRS)

Couvillon, L. A., Jr.; Carl, C.; Goldstein, R. M.; Posner, E. C.; Green, R. R. (Inventor)

1973-01-01

A method and apparatus are described for synchronizing a received PCM communications signal without requiring a separate synchronizing channel. The technique provides digital correlation of the received signal with a reference signal, first with its unmodulated subcarrier and then with a bit sync code modulated subcarrier, where the code sequence length is equal in duration to each data bit.

Method of recording bioelectrical signals using a capacitive coupling

NASA Astrophysics Data System (ADS)

Simon, V. A.; Gerasimov, V. A.; Kostrin, D. K.; Selivanov, L. M.; Uhov, A. A.

2017-11-01

In this article a technique for the bioelectrical signals acquisition by means of the capacitive sensors is described. A feedback loop for the ultra-high impedance biasing of the input instrumentation amplifier, which provides receiving of the electrical cardiac signal (ECS) through a capacitive coupling, is proposed. The mains 50/60 Hz noise is suppressed by a narrow-band stop filter with an independent notch frequency and quality factor tuning. Filter output is attached to a ΣΔ analog-to-digital converter (ADC), which acquires the filtered signal with a 24-bit resolution. Signal processing board is connected through universal serial bus interface to a personal computer, where ECS in a digital form is recorded and processed.

Design of a dataway processor for a parallel image signal processing system

NASA Astrophysics Data System (ADS)

Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

1995-04-01

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

Design of replica bit line control circuit to optimize power for SRAM

NASA Astrophysics Data System (ADS)

Pengjun, Wang; Keji, Zhou; Huihong, Zhang; Daohui, Gong

2016-12-01

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the National Natural Science Foundation of China (Nos. 61274132, 61234002, 61474068), and the K. C. Wong Magna Fund in Ningbo University.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

10 Gb/s operation of photonic crystal silicon optical modulators.

PubMed

Nguyen, Hong C; Sakai, Yuya; Shinkawa, Mizuki; Ishikura, Norihiro; Baba, Toshihiko

2011-07-04

We report the first experimental demonstration of 10 Gb/s modulation in a photonic crystal silicon optical modulator. The device consists of a 200 μm-long SiO2-clad photonic crystal waveguide, with an embedded p-n junction, incorporated into an asymmetric Mach-Zehnder interferometer. The device is integrated on a SOI chip and fabricated by CMOS-compatible processes. With the bias voltage set at 0 V, we measure a V(π)L < 0.056 V∙cm. Optical modulation is demonstrated by electrically driving the device with a 2(31) - 1 bit non-return-to-zero pseudo-random bit sequence signal. An open eye pattern is observed at bitrates of 10 Gb/s and 2 Gb/s, with and without pre-emphasis of the drive signal, respectively.

Research on the output bit error rate of 2DPSK signal based on stochastic resonance theory

NASA Astrophysics Data System (ADS)

Yan, Daqin; Wang, Fuzhong; Wang, Shuo

2017-12-01

Binary differential phase-shift keying (2DPSK) signal is mainly used for high speed data transmission. However, the bit error rate of digital signal receiver is high in the case of wicked channel environment. In view of this situation, a novel method based on stochastic resonance (SR) is proposed, which is aimed to reduce the bit error rate of 2DPSK signal by coherent demodulation receiving. According to the theory of SR, a nonlinear receiver model is established, which is used to receive 2DPSK signal under small signal-to-noise ratio (SNR) circumstances (between -15 dB and 5 dB), and compared with the conventional demodulation method. The experimental results demonstrate that when the input SNR is in the range of -15 dB to 5 dB, the output bit error rate of nonlinear system model based on SR has a significant decline compared to the conventional model. It could reduce 86.15% when the input SNR equals -7 dB. Meanwhile, the peak value of the output signal spectrum is 4.25 times as that of the conventional model. Consequently, the output signal of the system is more likely to be detected and the accuracy can be greatly improved.

Optical communication with semiconductor laser diodes

NASA Technical Reports Server (NTRS)

Davidson, F.

1988-01-01

Slot timing recovery in a direct detection optical PPM communication system can be achieved by processing the photodetector waveform with a nonlinear device whose output forms the input to a phase lock group. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The rms phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (lambda = 834 nm) and a silicon avalanche photodiode (APD) photodetector and used Q=4 PPM signaling operated at a source data rate of 25 megabits/second. The mathematical model developed to characterize system performance is shown to be in good agreement with actual performance measurements. The use of the recovered slot clock in the receiver resulted in no degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10 to the minus 6 power at received signal energies corresponding to an average of less than 60 detected photons per information bit.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

Functional description of signal processing in the Rogue GPS receiver

NASA Technical Reports Server (NTRS)

Thomas, J. B.

1988-01-01

Over the past year, two Rogue GPS prototype receivers have been assembled and successfully subjected to a variety of laboratory and field tests. A functional description is presented of signal processing in the Rogue receiver, tracing the signal from RF input to the output values of group delay, phase, and data bits. The receiver can track up to eight satellites, without time multiplexing among satellites or channels, simultaneously measuring both group delay and phase for each of three channels (L1-C/A, L1-P, L2-P). The Rogue signal processing described requires generation of the code for all three channels. Receiver functional design, which emphasized accuracy, reliability, flexibility, and dynamic capability, is summarized. A detailed functional description of signal processing is presented, including C/A-channel and P-channel processing, carrier-aided averaging of group delays, checks for cycle slips, acquistion, and distinctive features.

A high-efficiency real-time digital signal averager for time-of-flight mass spectrometry.

PubMed

Wang, Yinan; Xu, Hui; Li, Qingjiang; Li, Nan; Huang, Zhengxu; Zhou, Zhen; Liu, Husheng; Sun, Zhaolin; Xu, Xin; Yu, Hongqi; Liu, Haijun; Li, David D-U; Wang, Xi; Dong, Xiuzhen; Gao, Wei

2013-05-30

Analog-to-digital converter (ADC)-based acquisition systems are widely applied in time-of-flight mass spectrometers (TOFMS) due to their ability to record the signal intensity of all ions within the same pulse. However, the acquisition system raises the requirement for data throughput, along with increasing the conversion rate and resolution of the ADC. It is therefore of considerable interest to develop a high-performance real-time acquisition system, which can relieve the limitation of data throughput. We present in this work a high-efficiency real-time digital signal averager, consisting of a signal conditioner, a data conversion module and a signal processing module. Two optimization strategies are implemented using field programmable gate arrays (FPGAs) to enhance the efficiency of the real-time processing. A pipeline procedure is used to reduce the time consumption of the accumulation strategy. To realize continuous data transfer, a high-efficiency transmission strategy is developed, based on a ping-pong procedure. The digital signal averager features good responsiveness, analog bandwidth and dynamic performance. The optimal effective number of bits reaches 6.7 bits. For a 32 µs record length, the averager can realize 100% efficiency with an extraction frequency below 31.23 kHz by modifying the number of accumulation steps. In unit time, the averager yields superior signal-to-noise ratio (SNR) compared with data accumulation in a computer. The digital signal averager is combined with a vacuum ultraviolet single-photon ionization time-of-flight mass spectrometer (VUV-SPI-TOFMS). The efficiency of the real-time processing is tested by analyzing the volatile organic compounds (VOCs) from ordinary printed materials. In these experiments, 22 kinds of compounds are detected, and the dynamic range exceeds 3 orders of magnitude. Copyright © 2013 John Wiley & Sons, Ltd.

The design of preamplifier and ADC circuit base on weak e-optical signal

NASA Astrophysics Data System (ADS)

Fen, Leng; Ying-ping, Yang; Ya-nan, Yu; Xiao-ying, Xu

2011-02-01

Combined with the demand of the process of weak e-optical signal in QPD detection system, the article introduced the circuit principle of deigning preamplifier and ADC circuit with I/V conversion, instrumentation amplifier, low-pass filter and 16-bit A/D transformation. At the same time the article discussed the circuit's noise suppression and isolation according to the characteristics of the weak signal, and gave the method of software rectification. Finally, tested the weak signal with keithley2000, and got a good effect.

Embedded neural recording with TinyOS-based wireless-enabled processor modules.

PubMed

Farshchi, Shahin; Pesterev, Aleksey; Nuyujukian, Paul; Guenterberg, Eric; Mody, Istvan; Judy, Jack W

2010-04-01

To create a wireless neural recording system that can benefit from the continuous advancements being made in embedded microcontroller and communications technologies, an embedded-system-based architecture for wireless neural recording has been designed, fabricated, and tested. The system consists of commercial-off-the-shelf wireless-enabled processor modules (motes) for communicating the neural signals, and a back-end database server and client application for archiving and browsing the neural signals. A neural-signal-acquisition application has been developed to enable the mote to either acquire neural signals at a rate of 4000 12-bit samples per second, or detect and transmit spike heights and widths sampled at a rate of 16670 12-bit samples per second on a single channel. The motes acquire neural signals via a custom low-noise neural-signal amplifier with adjustable gain and high-pass corner frequency that has been designed, and fabricated in a 1.5-microm CMOS process. In addition to browsing acquired neural data, the client application enables the user to remotely toggle modes of operation (real-time or spike-only), as well as amplifier gain and high-pass corner frequency.

Improvement in airborne position measurements based on an ultrasonic linear-period-modulated wave by 1-bit signal processing

NASA Astrophysics Data System (ADS)

Thong-un, Natee; Hirata, Shinnosuke; Kurosawa, Minoru K.

2015-07-01

In this paper, we describe an expansion of the airborne ultrasonic systems for object localization in the three-dimensional spaces of navigation. A system, which revises the microphone arrangement and algorithm, can expand the object-position measurement from +90° in a previous method up to +180° for both the elevation and azimuth angles. The proposed system consists of a sound source and four acoustical receivers. Moreover, the system is designed to utilize low-cost devices, and low-cost computation relying on 1-bit signal processing is used to support the real-time application on a field-programmable gate array (FPGA). An object location is identified using spherical coordinates. A spherical object, which has a curved surface, is considered a target for this system. The transmit pulse to the target is a linear-period-modulated ultrasonic wave with a chirp rate of 50-20 kHz. Statistical evaluation of this work is the experimental investigation under repeatability.

A simulation analysis of phase processing circuitry in the Ohio University Omega receiver prototype

NASA Technical Reports Server (NTRS)

Palkovic, R. A.

1975-01-01

A FORTRAN IV simulation study of the all-digital phase-processing circuitry is described. A digital phase-lock loop (DPLL) forms the heart of the Omega navigation receiver prototype, and through the DPLL, the phase of the 10.2 KHz Omega signal was estimated when the true signal phase is contaminated with noise. The DPLL uses a frequency synthesizer as the reference oscillator. The synthesizer is composed of synchronous rate multipliers (SRM's) driven by a temperature-compensated crystal oscillator, and the use of the SRM's in this application introduces phase jitter which degrades system performance. Simulation of the frequency synthesizer discussed was to analyze the circuits on a bit-by-bit level in order to evaluate the overall design, to see easily the effects of proposed design changes prior to actual breadboarding, to determine the optimum integration time for the DPLL in an environment typical of general aviation conditions, and to quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.

Physical layer one-time-pad data encryption through synchronized semiconductor laser networks

NASA Astrophysics Data System (ADS)

Argyris, Apostolos; Pikasis, Evangelos; Syvridis, Dimitris

2016-02-01

Semiconductor lasers (SL) have been proven to be a key device in the generation of ultrafast true random bit streams. Their potential to emit chaotic signals under conditions with desirable statistics, establish them as a low cost solution to cover various needs, from large volume key generation to real-time encrypted communications. Usually, only undemanding post-processing is needed to convert the acquired analog timeseries to digital sequences that pass all established tests of randomness. A novel architecture that can generate and exploit these true random sequences is through a fiber network in which the nodes are semiconductor lasers that are coupled and synchronized to central hub laser. In this work we show experimentally that laser nodes in such a star network topology can synchronize with each other through complex broadband signals that are the seed to true random bit sequences (TRBS) generated at several Gb/s. The potential for each node to access real-time generated and synchronized with the rest of the nodes random bit streams, through the fiber optic network, allows to implement an one-time-pad encryption protocol that mixes the synchronized true random bit sequence with real data at Gb/s rates. Forward-error correction methods are used to reduce the errors in the TRBS and the final error rate at the data decoding level. An appropriate selection in the sampling methodology and properties, as well as in the physical properties of the chaotic seed signal through which network locks in synchronization, allows an error free performance.

DFT algorithms for bit-serial GaAs array processor architectures

NASA Technical Reports Server (NTRS)

Mcmillan, Gary B.

1988-01-01

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Electrophoresis gel image processing and analysis using the KODAK 1D software.

PubMed

Pizzonia, J

2001-06-01

The present article reports on the performance of the KODAK 1D Image Analysis Software for the acquisition of information from electrophoresis experiments and highlights the utility of several mathematical functions for subsequent image processing, analysis, and presentation. Digital images of Coomassie-stained polyacrylamide protein gels containing molecular weight standards and ethidium bromide stained agarose gels containing DNA mass standards are acquired using the KODAK Electrophoresis Documentation and Analysis System 290 (EDAS 290). The KODAK 1D software is used to optimize lane and band identification using features such as isomolecular weight lines. Mathematical functions for mass standard representation are presented, and two methods for estimation of unknown band mass are compared. Given the progressive transition of electrophoresis data acquisition and daily reporting in peer-reviewed journals to digital formats ranging from 8-bit systems such as EDAS 290 to more expensive 16-bit systems, the utility of algorithms such as Gaussian modeling, which can correct geometric aberrations such as clipping due to signal saturation common at lower bit depth levels, is discussed. Finally, image-processing tools that can facilitate image preparation for presentation are demonstrated.

Random access codes and nonlocal resources

NASA Astrophysics Data System (ADS)

Chaturvedi, Anubhav; Pawlowski, Marcin; Horodecki, Karol

2017-08-01

This work explores the notion of inter-convertibility between a cryptographic primitive: the random access code (RAC) and bipartite no-signaling nonlocal resources. To this end we introduce two generalizations of the Popescu-Rohrlich box (PR) and investigate their relation with the corresponding RACs. The first generalization is based on the number of Alice's input bits; we refer to it as the Bn-box. We show that the no-signaling condition imposes an equivalence between the Bn-box and the (n →1 ) RAC (encoding of n input bits to 1 bit of message). As an application we show that (n -1 ) PRs supplemented with one bit communication are necessary and sufficient to win a (n →1 ) RAC with certainty. Furthermore, we present a signaling instant of a perfectly working (n →1 ) RAC which cannot simulate the Bn-box, thus showing that it is weaker than its no-signaling counterpart. For the second generalization we replace Alice's input bits with d its (d -leveled classical systems); we call this the Bnd-box. In this case the no-signaling condition is not enough to enforce an equivalence between the Bnd-box and (n →1 ,d ) RAC (encoding of n input d its to 1 d it of message); i.e., while the Bnd-box can win a (n →1 ,d ) RAC with certainty, not all no-signaling instances of a (n →1 ,d ) RAC can simulate the Bnd-box. We use resource inequalities to quantitatively capture these results.

Radio Astronomy Software Defined Receiver Project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, Bogdan; Leech, Marcus; Oxley, Paul

The paper describes a Radio Astronomy Software Defined Receiver (RASDR) that is currently under development. RASDR is targeted for use by amateurs and small institutions where cost is a primary consideration. The receiver will operate from HF thru 2.8 GHz. Front-end components such as preamps, block down-converters and pre-select bandpass filters are outside the scope of this development and will be provided by the user. The receiver includes RF amplifiers and attenuators, synthesized LOs, quadrature down converters, dual 8 bit ADCs and a Signal Processor that provides firmware processing of the digital bit stream. RASDR will interface to a usermore » s PC via a USB or higher speed Ethernet LAN connection. The PC will run software that provides processing of the bit stream, a graphical user interface, as well as data analysis and storage. Software should support MAC OS, Windows and Linux platforms and will focus on such radio astronomy applications as total power measurements, pulsar detection, and spectral line studies.« less

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Measuring the electric activity of chick embryos heart through 16 bit audio card monitored by the Goldwavetm software

NASA Astrophysics Data System (ADS)

Silva, Dilson; Cortez, Celia Martins

2015-12-01

In the present work we used a high-resolution, low-cost apparatus capable of detecting waves fit inside the sound bandwidth, and the software package GoldwaveTM for graphical display, processing and monitoring the signals, to study aspects of the electric heart activity of early avian embryos, specifically at the 18th Hamburger & Hamilton stage of the embryo development. The species used was the domestic chick (Gallus gallus), and we carried out 23 experiments in which cardiographic spectra of QRS complex waves representing the propagation of depolarization waves through ventricles was recorded using microprobes and reference electrodes directly on the embryos. The results show that technique using 16 bit audio card monitored by the GoldwaveTM software was efficient to study signal aspects of heart electric activity of early avian embryos.

Modal processing for acoustic communications in shallow water experiment.

PubMed

Morozov, Andrey K; Preisig, James C; Papp, Joseph

2008-09-01

Acoustical array data from the Shallow Water Acoustics experiment was processed to show the feasibility of broadband mode decomposition as a preprocessing method to reduce the effective channel delay spread and concentrate received signal energy in a small number of independent channels. The data were collected by a vertical array designed at the Woods Hole Oceanographic Institution. Phase-shift Keying (PSK) m-sequence modulated signals with different carrier frequencies were transmitted at a distance 19.2 km from the array. Even during a strong internal waves activity a low bit error rate was achieved.

Reduction of Phase Ambiguity in an Offset-QPSK Receiver

NASA Technical Reports Server (NTRS)

Berner, Jeff; Kinman, Peter

2004-01-01

Proposed modifications of an offset-quadri-phase-shift keying (offset-QPSK) transmitter and receiver would reduce the amount of signal processing that must be done in the receiver to resolve the QPSK fourfold phase ambiguity. Resolution of the phase ambiguity is necessary in order to synchronize, with the received carrier signal, the signal generated by a local oscillator in a carrier-tracking loop in the receiver. Without resolution of the fourfold phase ambiguity, the loop could lock to any of four possible phase points, only one of which has the proper phase relationship with the carrier. The proposal applies, more specifically, to an offset-QPSK receiver that contains a carrier-tracking loop like that shown in Figure 1. This carrier-tracking loop does not resolve or reduce the phase ambiguity. A carrier-tracking loop of a different design optimized for the reception of offset QPSK could reduce the phase ambiguity from fourfold to twofold, but would be more complex. Alternatively, one could resolve the fourfold phase ambiguity by use of differential coding in the transmitter, at a cost of reduced power efficiency. The proposed modifications would make it possible to reduce the fourfold phase ambiguity to twofold, with no loss in power efficiency and only relatively simple additional signal-processing steps in the transmitter and receiver. The twofold phase ambiguity would then be resolved by use of a unique synchronization word, as is commonly done in binary phase-shift keying (BPSK). Although the mathematical and signal-processing principles underlying the modifications are too complex to explain in detail here, the modifications themselves would be relatively simple and are best described with the help of simple block diagrams (see Figure 2). In the transmitter, one would add a unit that would periodically invert bits going into the QPSK modulator; in the receiver, one would add a unit that would effect different but corresponding inversions of bits coming out of the QPSK demodulator. The net effect of all the inversions would be that depending on which lock point the carrier-tracking loop had selected, all the output bits would be either inverted or non-inverted together; hence, the ambiguity would be reduced from fourfold to twofold, as desired.

Energy-efficient human body communication receiver chipset using wideband signaling scheme.

PubMed

Song, Seong-Jun; Cho, Namjun; Kim, Sunyoung; Yoo, Hoi-Jun

2007-01-01

This paper presents an energy-efficient wideband signaling receiver for communication channels using the human body as a data transmission medium. The wideband signaling scheme with the direct-coupled interface provides the energy-efficient transmission of multimedia data around the human body. The wideband signaling receiver incorporates with a receiver AFE exploiting wideband symmetric triggering technique and an all-digital CDR circuit with quadratic sampling technique. The AFE operates at 10-Mb/s data rate with input sensitivity of -27dBm and the operational bandwidth of 200-MHz. The CDR recovers clock and data of 2-Mb/s at a bit error rate of 10(-7). The receiver chipset consumes only 5-mW from a 1-V supply, thereby achieving the bit energy of 2.5-nJ/bit.

Computer modeling and design analysis of a bit rate discrimination circuit based dual-rate burst mode receiver

NASA Astrophysics Data System (ADS)

Kota, Sriharsha; Patel, Jigesh; Ghillino, Enrico; Richards, Dwight

2011-01-01

In this paper, we demonstrate a computer model for simulating a dual-rate burst mode receiver that can readily distinguish bit rates of 1.25Gbit/s and 10.3Gbit/s and demodulate the data bursts with large power variations of above 5dB. To our knowledge, this is the first such model to demodulate data bursts of different bit rates without using any external control signal such as a reset signal or a bit rate select signal. The model is based on a burst-mode bit rate discrimination circuit (B-BDC) and makes use of a unique preamble sequence attached to each burst to separate out the data bursts with different bit rates. Here, the model is implemented using a combination of the optical system simulation suite OptSimTM, and the electrical simulation engine SPICE. The reaction time of the burst mode receiver model is about 7ns, which corresponds to less than 8 preamble bits for the bit rate of 1.25Gbps. We believe, having an accurate and robust simulation model for high speed burst mode transmission in GE-PON systems, is indispensable and tremendously speeds up the ongoing research in the area, saving a lot of time and effort involved in carrying out the laboratory experiments, while providing flexibility in the optimization of various system parameters for better performance of the receiver as a whole. Furthermore, we also study the effects of burst specifications like the length of preamble sequence, and other receiver design parameters on the reaction time of the receiver.

Global navigation satellite system receiver for weak signals under all dynamic conditions

NASA Astrophysics Data System (ADS)

Ziedan, Nesreen Ibrahim

The ability of the Global Navigation Satellite System (GNSS) receiver to work under weak signal and various dynamic conditions is required in some applications. For example, to provide a positioning capability in wireless devices, or orbit determination of Geostationary and high Earth orbit satellites. This dissertation develops Global Positioning System (GPS) receiver algorithms for such applications. Fifteen algorithms are developed for the GPS C/A signal. They cover all the receiver main functions, which include acquisition, fine acquisition, bit synchronization, code and carrier tracking, and navigation message decoding. They are integrated together, and they can be used in any software GPS receiver. They also can be modified to fit any other GPS or GNSS signals. The algorithms have new capabilities. The processing and memory requirements are considered in the design to allow the algorithms to fit the limited resources of some applications; they do not require any assisting information. Weak signals can be acquired in the presence of strong interfering signals and under high dynamic conditions. The fine acquisition, bit synchronization, and tracking algorithms are based on the Viterbi algorithm and Extended Kalman filter approaches. The tracking algorithms capabilities increase the time to lose lock. They have the ability to adaptively change the integration length and the code delay separation. More than one code delay separation can be used in the same time. Large tracking errors can be detected and then corrected by a re-initialization and an acquisition-like algorithms. Detecting the navigation message is needed to increase the coherent integration; decoding it is needed to calculate the navigation solution. The decoding algorithm utilizes the message structure to enable its decoding for signals with high Bit Error Rate. The algorithms are demonstrated using simulated GPS C/A code signals, and TCXO clocks. The results have shown the algorithms ability to reliably work with 15 dB-Hz signals and acceleration over 6 g.

Bit Grooming: statistically accurate precision-preserving quantization with compression, evaluated in the netCDF Operators (NCO, v4.4.8+)

NASA Astrophysics Data System (ADS)

Zender, Charles S.

2016-09-01

Geoscientific models and measurements generate false precision (scientifically meaningless data bits) that wastes storage space. False precision can mislead (by implying noise is signal) and be scientifically pointless, especially for measurements. By contrast, lossy compression can be both economical (save space) and heuristic (clarify data limitations) without compromising the scientific integrity of data. Data quantization can thus be appropriate regardless of whether space limitations are a concern. We introduce, implement, and characterize a new lossy compression scheme suitable for IEEE floating-point data. Our new Bit Grooming algorithm alternately shaves (to zero) and sets (to one) the least significant bits of consecutive values to preserve a desired precision. This is a symmetric, two-sided variant of an algorithm sometimes called Bit Shaving that quantizes values solely by zeroing bits. Our variation eliminates the artificial low bias produced by always zeroing bits, and makes Bit Grooming more suitable for arrays and multi-dimensional fields whose mean statistics are important. Bit Grooming relies on standard lossless compression to achieve the actual reduction in storage space, so we tested Bit Grooming by applying the DEFLATE compression algorithm to bit-groomed and full-precision climate data stored in netCDF3, netCDF4, HDF4, and HDF5 formats. Bit Grooming reduces the storage space required by initially uncompressed and compressed climate data by 25-80 and 5-65 %, respectively, for single-precision values (the most common case for climate data) quantized to retain 1-5 decimal digits of precision. The potential reduction is greater for double-precision datasets. When used aggressively (i.e., preserving only 1-2 digits), Bit Grooming produces storage reductions comparable to other quantization techniques such as Linear Packing. Unlike Linear Packing, whose guaranteed precision rapidly degrades within the relatively narrow dynamic range of values that it can compress, Bit Grooming guarantees the specified precision throughout the full floating-point range. Data quantization by Bit Grooming is irreversible (i.e., lossy) yet transparent, meaning that no extra processing is required by data users/readers. Hence Bit Grooming can easily reduce data storage volume without sacrificing scientific precision or imposing extra burdens on users.

Robust watermark technique using masking and Hermite transform.

PubMed

Coronel, Sandra L Gomez; Ramírez, Boris Escalante; Mosqueda, Marco A Acevedo

2016-01-01

The following paper evaluates a watermark algorithm designed for digital images by using a perceptive mask and a normalization process, thus preventing human eye detection, as well as ensuring its robustness against common processing and geometric attacks. The Hermite transform is employed because it allows a perfect reconstruction of the image, while incorporating human visual system properties; moreover, it is based on the Gaussian functions derivates. The applied watermark represents information of the digital image proprietor. The extraction process is blind, because it does not require the original image. The following techniques were utilized in the evaluation of the algorithm: peak signal-to-noise ratio, the structural similarity index average, the normalized crossed correlation, and bit error rate. Several watermark extraction tests were performed, with against geometric and common processing attacks. It allowed us to identify how many bits in the watermark can be modified for its adequate extraction.

Hybrid spread spectrum radio system

DOEpatents

Smith, Stephen F [London, TN; Dress, William B [Camas, WA

2010-02-09

Systems and methods are described for hybrid spread spectrum radio systems. A method, includes receiving a hybrid spread spectrum signal including: fast frequency hopping demodulating and direct sequence demodulating a direct sequence spread spectrum signal, wherein multiple frequency hops occur within a single data-bit time and each bit is represented by chip transmissions at multiple frequencies.

BIT BY BIT: A Game Simulating Natural Language Processing in Computers

ERIC Educational Resources Information Center

Kato, Taichi; Arakawa, Chuichi

2008-01-01

BIT BY BIT is an encryption game that is designed to improve students' understanding of natural language processing in computers. Participants encode clear words into binary code using an encryption key and exchange them in the game. BIT BY BIT enables participants who do not understand the concept of binary numbers to perform the process of…

Digital signal processing the Tevatron BPM signals

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cancelo, G.; James, E.; Wolbers, S.

2005-05-01

The Beam Position Monitor (TeV BPM) readout system at Fermilab's Tevatron has been updated and is currently being commissioned. The new BPMs use new analog and digital hardware to achieve better beam position measurement resolution. The new system reads signals from both ends of the existing directional stripline pickups to provide simultaneous proton and antiproton measurements. The signals provided by the two ends of the BPM pickups are processed by analog band-pass filters and sampled by 14-bit ADCs at 74.3MHz. A crucial part of this work has been the design of digital filters that process the signal. This paper describesmore » the digital processing and estimation techniques used to optimize the beam position measurement. The BPM electronics must operate in narrow-band and wide-band modes to enable measurements of closed-orbit and turn-by-turn positions. The filtering and timing conditions of the signals are tuned accordingly for the operational modes. The analysis and the optimized result for each mode are presented.« less

A customizable system for real-time image processing using the Blackfin DSProcessor and the MicroC/OS-II real-time kernel

NASA Astrophysics Data System (ADS)

Coffey, Stephen; Connell, Joseph

2005-06-01

This paper presents a development platform for real-time image processing based on the ADSP-BF533 Blackfin processor and the MicroC/OS-II real-time operating system (RTOS). MicroC/OS-II is a completely portable, ROMable, pre-emptive, real-time kernel. The Blackfin Digital Signal Processors (DSPs), incorporating the Analog Devices/Intel Micro Signal Architecture (MSA), are a broad family of 16-bit fixed-point products with a dual Multiply Accumulate (MAC) core. In addition, they have a rich instruction set with variable instruction length and both DSP and MCU functionality thus making them ideal for media based applications. Using the MicroC/OS-II for task scheduling and management, the proposed system can capture and process raw RGB data from any standard 8-bit greyscale image sensor in soft real-time and then display the processed result using a simple PC graphical user interface (GUI). Additionally, the GUI allows configuration of the image capture rate and the system and core DSP clock rates thereby allowing connectivity to a selection of image sensors and memory devices. The GUI also allows selection from a set of image processing algorithms based in the embedded operating system.

Recurrent neural network approach to quantum signal: coherent state restoration for continuous-variable quantum key distribution

NASA Astrophysics Data System (ADS)

Lu, Weizhao; Huang, Chunhui; Hou, Kun; Shi, Liting; Zhao, Huihui; Li, Zhengmei; Qiu, Jianfeng

2018-05-01

In continuous-variable quantum key distribution (CV-QKD), weak signal carrying information transmits from Alice to Bob; during this process it is easily influenced by unknown noise which reduces signal-to-noise ratio, and strongly impacts reliability and stability of the communication. Recurrent quantum neural network (RQNN) is an artificial neural network model which can perform stochastic filtering without any prior knowledge of the signal and noise. In this paper, a modified RQNN algorithm with expectation maximization algorithm is proposed to process the signal in CV-QKD, which follows the basic rule of quantum mechanics. After RQNN, noise power decreases about 15 dBm, coherent signal recognition rate of RQNN is 96%, quantum bit error rate (QBER) drops to 4%, which is 6.9% lower than original QBER, and channel capacity is notably enlarged.

All-optical simultaneous multichannel quadrature phase shift keying signal regeneration based on phase-sensitive amplification

NASA Astrophysics Data System (ADS)

Wang, Hongxiang; Wang, Qi; Bai, Lin; Ji, Yuefeng

2018-01-01

A scheme is proposed to realize the all-optical phase regeneration of four-channel quadrature phase shift keying (QPSK) signal based on phase-sensitive amplification. By utilizing conjugate pump and common pump in a highly nonlinear optical fiber, degenerate four-wave mixing process is observed, and QPSK signals are regenerated. The number of waves is reduced to decrease the cross talk caused by undesired nonlinear interaction during the coherent superposition process. In addition, to avoid the effect of overlapping frequency, frequency spans between pumps and signals are set to be nonintegral multiples. Optical signal-to-noise ratio improvement is validated by bit error rate measurements. Compared with single-channel regeneration, multichannel regeneration brings 0.4-dB OSNR penalty when the value of BER is 10-3, which shows the cross talk in regeneration process is negligible.

Sleep stage classification with low complexity and low bit rate.

PubMed

Virkkala, Jussi; Värri, Alpo; Hasan, Joel; Himanen, Sari-Leena; Müller, Kiti

2009-01-01

Standard sleep stage classification is based on visual analysis of central (usually also frontal and occipital) EEG, two-channel EOG, and submental EMG signals. The process is complex, using multiple electrodes, and is usually based on relatively high (200-500 Hz) sampling rates. Also at least 12 bit analog to digital conversion is recommended (with 16 bit storage) resulting in total bit rate of at least 12.8 kbit/s. This is not a problem for in-house laboratory sleep studies, but in the case of online wireless self-applicable ambulatory sleep studies, lower complexity and lower bit rates are preferred. In this study we further developed earlier single channel facial EMG/EOG/EEG-based automatic sleep stage classification. An algorithm with a simple decision tree separated 30 s epochs into wakefulness, SREM, S1/S2 and SWS using 18-45 Hz beta power and 0.5-6 Hz amplitude. Improvements included low complexity recursive digital filtering. We also evaluated the effects of a reduced sampling rate, reduced number of quantization steps and reduced dynamic range on the sleep data of 132 training and 131 testing subjects. With the studied algorithm, it was possible to reduce the sampling rate to 50 Hz (having a low pass filter at 90 Hz), and the dynamic range to 244 microV, with an 8 bit resolution resulting in a bit rate of 0.4 kbit/s. Facial electrodes and a low bit rate enables the use of smaller devices for sleep stage classification in home environments.

Origami mechanologic.

PubMed

Treml, Benjamin; Gillman, Andrew; Buskohl, Philip; Vaia, Richard

2018-06-18

Robots autonomously interact with their environment through a continual sense-decide-respond control loop. Most commonly, the decide step occurs in a central processing unit; however, the stiffness mismatch between rigid electronics and the compliant bodies of soft robots can impede integration of these systems. We develop a framework for programmable mechanical computation embedded into the structure of soft robots that can augment conventional digital electronic control schemes. Using an origami waterbomb as an experimental platform, we demonstrate a 1-bit mechanical storage device that writes, erases, and rewrites itself in response to a time-varying environmental signal. Further, we show that mechanical coupling between connected origami units can be used to program the behavior of a mechanical bit, produce logic gates such as AND, OR, and three input majority gates, and transmit signals between mechanologic gates. Embedded mechanologic provides a route to add autonomy and intelligence in soft robots and machines. Copyright © 2018 the Author(s). Published by PNAS.

Integrated test system of infrared and laser data based on USB 3.0

NASA Astrophysics Data System (ADS)

Fu, Hui Quan; Tang, Lin Bo; Zhang, Chao; Zhao, Bao Jun; Li, Mao Wen

2017-07-01

Based on USB3.0, this paper presents the design method of an integrated test system for both infrared image data and laser signal data processing module. The core of the design is FPGA logic control, the design uses dual-chip DDR3 SDRAM to achieve high-speed laser data cache, and receive parallel LVDS image data through serial-to-parallel conversion chip, and it achieves high-speed data communication between the system and host computer through the USB3.0 bus. The experimental results show that the developed PC software realizes the real-time display of 14-bit LVDS original image after 14-to-8 bit conversion and JPEG2000 compressed image after decompression in software, and can realize the real-time display of the acquired laser signal data. The correctness of the test system design is verified, indicating that the interface link is normal.

Design of a reversible single precision floating point subtractor.

PubMed

Anantha Lakshmi, Av; Sudha, Gf

2014-01-04

In recent years, Reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation which is the main requirement in the low power digital circuit design. It has wide applications like low power CMOS design, Nano-technology, Digital signal processing, Communication, DNA computing and Optical computing. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition/subtraction to be the most used floating-point operation. However, few designs exist on efficient reversible BCD subtractors but no work on reversible floating point subtractor. In this paper, it is proposed to present an efficient reversible single precision floating-point subtractor. The proposed design requires reversible designs of an 8-bit and a 24-bit comparator unit, an 8-bit and a 24-bit subtractor, and a normalization unit. For normalization, a 24-bit Reversible Leading Zero Detector and a 24-bit reversible shift register is implemented to shift the mantissas. To realize a reversible 1-bit comparator, in this paper, two new 3x3 reversible gates are proposed The proposed reversible 1-bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor count and the number of garbage outputs. The proposed work is analysed in terms of number of reversible gates, garbage outputs, constant inputs and quantum costs. Using these modules, an efficient design of a reversible single precision floating point subtractor is proposed. Proposed circuits have been simulated using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3. The total on-chip power consumed by the proposed 32-bit reversible floating point subtractor is 0.410 W.

Time of flight system on a chip

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas P. (Inventor)

2006-01-01

A CMOS time-of-flight TOF system-on-a-chip SoC for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators CFDs and a Time-to-Digital Converter TDC. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).

Multi-rate, real time image compression for images dominated by point sources

NASA Technical Reports Server (NTRS)

Huber, A. Kris; Budge, Scott E.; Harris, Richard W.

1993-01-01

An image compression system recently developed for compression of digital images dominated by point sources is presented. Encoding consists of minimum-mean removal, vector quantization, adaptive threshold truncation, and modified Huffman encoding. Simulations are presented showing that the peaks corresponding to point sources can be transmitted losslessly for low signal-to-noise ratios (SNR) and high point source densities while maintaining a reduced output bit rate. Encoding and decoding hardware has been built and tested which processes 552,960 12-bit pixels per second at compression rates of 10:1 and 4:1. Simulation results are presented for the 10:1 case only.

50 Mbps free space direct detection laser diode optical communication system with Q = 4 PPM signaling

NASA Technical Reports Server (NTRS)

Sun, Xiaoli; Davidson, Frederic; Field, Christopher

1990-01-01

A 50 Mbps direct detection optical communication system for use in an intersatellite link was constructed with an AlGaAs laser diode transmitter and a silicon avalanche photodiode photodetector. The system used a Q = 4 PPM format. The receiver consisted of a maximum likelihood PPM detector and a timing recovery subsystem. The PPM slot clock was recovered at the receiver by using a transition detector followed by a PLL. The PPM word clock was recovered by using a second PLL whose input was derived from the presence of back-to-back PPM pulses contained in the received random PPM pulse sequences. The system achieved a bit error rate of 0.000001 at less than 50 detected signal photons/information bit. The receiver was capable of acquiring and maintaining slot and word synchronization for received signal levels greater than 20 photons/information bit, at which the receiver bit error rate was about 0.01.

Low-power, high-speed 1-bit inexact Full Adder cell designs applicable to low-energy image processing

NASA Astrophysics Data System (ADS)

Zareei, Zahra; Navi, Keivan; Keshavarziyan, Peiman

2018-03-01

In this paper, three novel low-power and high-speed 1-bit inexact Full Adder cell designs are presented based on current mode logic in 32 nm carbon nanotube field effect transistor technology for the first time. The circuit-level figures of merits, i.e. power, delay and power-delay product as well as application-level metric such as error distance, are considered to assess the efficiency of the proposed cells over their counterparts. The effect of voltage scaling and temperature variation on the proposed cells is studied using HSPICE tool. Moreover, using MATLAB tool, the peak signal to noise ratio of the proposed cells is evaluated in an image-processing application referred to as motion detector. Simulation results confirm the efficiency of the proposed cells.

An adaptive DPCM encoder for NTSC composite video signals

NASA Astrophysics Data System (ADS)

Cox, N. R.

An adaptive DPCM algorithm is proposed for encoding digitized National Television Systems Committee (NTSC) color video signals. This algorithm essentially predicts picture contours in the composite signal without resorting to component separation. Preliminary subjective and objective tests performed on an experimental encoder/simulator indicate that high quality color pictures can be encoded at 4.0 bits/pel or 42.95 Mbit/s. This requires the use of a 4/8 bit dual-word-length coder and buffer memory. Such a system might be useful in certain short hop applications if both large-signal and small-signal responses can be preserved.

Design of frequency-encoded data-based optical master-slave-JK flip-flop using polarization switch

NASA Astrophysics Data System (ADS)

Mandal, Sumana; Mandal, Dhoumendra; Mandal, Mrinal Kanti; Garai, Sisir Kumar

2017-06-01

An optical data processing and communication system provides enormous potential bandwidth and a very high processing speed, and it can fulfill the demands of the present generation. For an optical computing system, several data processing units that work in the optical domain are essential. Memory elements are undoubtedly essential to storing any information. Optical flip-flops can store one bit of optical information. From these flip-flop registers, counters can be developed. Here, the authors proposed an optical master-slave (MS)-JK flip-flop with the help of two-input and three-input optical NAND gates. Optical NAND gates have been developed using semiconductor optical amplifiers (SOAs). The nonlinear polarization switching property of an SOA has been exploited here, and it acts as a polarization switch in the proposed scheme. A frequency encoding technique is adopted for representing data. A specific frequency of an optical signal represents a binary data bit. This technique of data representation is helpful because frequency is the fundamental property of a signal, and it remains unaltered during reflection, refraction, absorption, etc. throughout the data propagation. The simulated results enhance the admissibility of the scheme.

A 13.56-mbps pulse delay modulation based transceiver for simultaneous near-field data and power transmission.

PubMed

Kiani, Mehdi; Ghovanloo, Maysam

2015-02-01

A fully-integrated near-field wireless transceiver has been presented for simultaneous data and power transmission across inductive links, which operates based on pulse delay modulation (PDM) technique. PDM is a low-power carrier-less modulation scheme that offers wide bandwidth along with robustness against strong power carrier interference, which makes it suitable for implantable neuroprosthetic devices, such as retinal implants. To transmit each bit, a pattern of narrow pulses are generated at the same frequency of the power carrier across the transmitter (Tx) data coil with specific time delays to initiate decaying ringing across the tuned receiver (Rx) data coil. This ringing shifts the zero-crossing times of the undesired power carrier interference on the Rx data coil, resulting in a phase shift between the signals across Rx power and data coils, from which the data bit stream can be recovered. A PDM transceiver prototype was fabricated in a 0.35- μm standard CMOS process, occupying 1.6 mm(2). The transceiver achieved a measured 13.56 Mbps data rate with a raw bit error rate (BER) of 4.3×10(-7) at 10 mm distance between figure-8 data coils, despite a signal-to-interference ratio (SIR) of -18.5 dB across the Rx data coil. At the same time, a class-D power amplifier, operating at 13.56 MHz, delivered 42 mW of regulated power across a separate pair of high-Q power coils, aligned with the data coils. The PDM data Tx and Rx power consumptions were 960 pJ/bit and 162 pJ/bit, respectively, at 1.8 V supply voltage.

Spread spectrum communication link using surface wave devices

NASA Technical Reports Server (NTRS)

Hunsinger, B. J.; Fugit, B. B.

1971-01-01

A fast lock-up, 8-MHz bandwidth 8,000 bit per second data rate spread spectrum communication link breadboard is described that is implemented using surface wave devices as the primary signal generators and signal processing elements. It uses surface wave tapped delay lines in the transmitter to generate the signals and in the receiver to detect them. The breadboard provides a measured processing gain for Gaussian noise of 31.5 dB which is within one dB of the theoretical optimum. This development demonstrates that spread spectrum receivers implemented with surface wave devices have sensitivities and complexities comparable to those of serial correlation receivers, but synchronization search times which are two to three orders of magnitude smaller.

Method and apparatus for analog signal conditioner for high speed, digital x-ray spectrometer

DOEpatents

Warburton, William K.; Hubbard, Bradley

1999-01-01

A signal processing system which accepts input from an x-ray detector-preamplifier and produces a signal of reduced dynamic range for subsequent analog-to-digital conversion. The system conditions the input signal to reduce the number of bits required in the analog-to-digital converter by removing that part of the input signal which varies only slowly in time and retaining the amplitude of the pulses which carry information about the x-rays absorbed by the detector. The parameters controlling the signal conditioner's operation can be readily supplied in digital form, allowing it to be integrated into a feedback loop as part of a larger digital x-ray spectroscopy system.

Investigation of digital encoding techniques for television transmission

NASA Technical Reports Server (NTRS)

Schilling, D. L.

1983-01-01

Composite color television signals are sampled at four times the color subcarrier and transformed using intraframe two dimensional Walsh functions. It is shown that by properly sampling a composite color signal and employing a Walsh transform the YIQ time signals which sum to produce the composite color signal can be represented, in the transform domain, by three component signals in space. By suitably zonal quantizing the transform coefficients, the YIQ signals can be processed independently to achieve data compression and obtain the same results as component coding. Computer simulations of three bandwidth compressors operating at 1.09, 1.53 and 1.8 bits/ sample are presented. The above results can also be applied to the PAL color system.

Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes. Part 3; The Map and Related Decoding Algirithms

NASA Technical Reports Server (NTRS)

Lin, Shu; Fossorier, Marc

1998-01-01

In a coded communication system with equiprobable signaling, MLD minimizes the word error probability and delivers the most likely codeword associated with the corresponding received sequence. This decoding has two drawbacks. First, minimization of the word error probability is not equivalent to minimization of the bit error probability. Therefore, MLD becomes suboptimum with respect to the bit error probability. Second, MLD delivers a hard-decision estimate of the received sequence, so that information is lost between the input and output of the ML decoder. This information is important in coded schemes where the decoded sequence is further processed, such as concatenated coding schemes, multi-stage and iterative decoding schemes. In this chapter, we first present a decoding algorithm which both minimizes bit error probability, and provides the corresponding soft information at the output of the decoder. This algorithm is referred to as the MAP (maximum aposteriori probability) decoding algorithm.

Synthesis and evaluation of phase detectors for active bit synchronizers

NASA Technical Reports Server (NTRS)

Mcbride, A. L.

1974-01-01

Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.

ASIC For Complex Fixed-Point Arithmetic

NASA Technical Reports Server (NTRS)

Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

1995-01-01

Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

Fundamental trade-offs between information flow in single cells and cellular populations.

PubMed

Suderman, Ryan; Bachman, John A; Smith, Adam; Sorger, Peter K; Deeds, Eric J

2017-05-30

Signal transduction networks allow eukaryotic cells to make decisions based on information about intracellular state and the environment. Biochemical noise significantly diminishes the fidelity of signaling: networks examined to date seem to transmit less than 1 bit of information. It is unclear how networks that control critical cell-fate decisions (e.g., cell division and apoptosis) can function with such low levels of information transfer. Here, we use theory, experiments, and numerical analysis to demonstrate an inherent trade-off between the information transferred in individual cells and the information available to control population-level responses. Noise in receptor-mediated apoptosis reduces information transfer to approximately 1 bit at the single-cell level but allows 3-4 bits of information to be transmitted at the population level. For processes such as eukaryotic chemotaxis, in which single cells are the functional unit, we find high levels of information transmission at a single-cell level. Thus, low levels of information transfer are unlikely to represent a physical limit. Instead, we propose that signaling networks exploit noise at the single-cell level to increase population-level information transfer, allowing extracellular ligands, whose levels are also subject to noise, to incrementally regulate phenotypic changes. This is particularly critical for discrete changes in fate (e.g., life vs. death) for which the key variable is the fraction of cells engaged. Our findings provide a framework for rationalizing the high levels of noise in metazoan signaling networks and have implications for the development of drugs that target these networks in the treatment of cancer and other diseases.

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P. K. A.

2014-01-01

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W−1/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems. PMID:25417847

Self-recovery fragile watermarking algorithm based on SPHIT

NASA Astrophysics Data System (ADS)

Xin, Li Ping

2015-12-01

A fragile watermark algorithm is proposed, based on SPIHT coding, which can recover the primary image itself. The novelty of the algorithm is that it can tamper location and Self-restoration. The recovery has been very good effect. The first, utilizing the zero-tree structure, the algorithm compresses and encodes the image itself, and then gained self correlative watermark data, so as to greatly reduce the quantity of embedding watermark. Then the watermark data is encoded by error correcting code, and the check bits and watermark bits are scrambled and embedded to enhance the recovery ability. At the same time, by embedding watermark into the latter two bit place of gray level image's bit-plane code, the image after embedded watermark can gain nicer visual effect. The experiment results show that the proposed algorithm may not only detect various processing such as noise adding, cropping, and filtering, but also recover tampered image and realize blind-detection. Peak signal-to-noise ratios of the watermark image were higher than other similar algorithm. The attack capability of the algorithm was enhanced.

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide.

PubMed

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P K A

2014-11-24

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W(-1)/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems.

An Efficient Method for Image and Audio Steganography using Least Significant Bit (LSB) Substitution

NASA Astrophysics Data System (ADS)

Chadha, Ankit; Satam, Neha; Sood, Rakshak; Bade, Dattatray

2013-09-01

In order to improve the data hiding in all types of multimedia data formats such as image and audio and to make hidden message imperceptible, a novel method for steganography is introduced in this paper. It is based on Least Significant Bit (LSB) manipulation and inclusion of redundant noise as secret key in the message. This method is applied to data hiding in images. For data hiding in audio, Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) both are used. All the results displayed prove to be time-efficient and effective. Also the algorithm is tested for various numbers of bits. For those values of bits, Mean Square Error (MSE) and Peak-Signal-to-Noise-Ratio (PSNR) are calculated and plotted. Experimental results show that the stego-image is visually indistinguishable from the original cover-image when n<=4, because of better PSNR which is achieved by this technique. The final results obtained after steganography process does not reveal presence of any hidden message, thus qualifying the criteria of imperceptible message.

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units.

PubMed

Rath, N; Kato, S; Levesque, J P; Mauel, M E; Navratil, G A; Peng, Q

2014-04-01

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

Bit Grooming: Statistically accurate precision-preserving quantization with compression, evaluated in the netCDF operators (NCO, v4.4.8+)

DOE PAGES

Zender, Charles S.

2016-09-19

Geoscientific models and measurements generate false precision (scientifically meaningless data bits) that wastes storage space. False precision can mislead (by implying noise is signal) and be scientifically pointless, especially for measurements. By contrast, lossy compression can be both economical (save space) and heuristic (clarify data limitations) without compromising the scientific integrity of data. Data quantization can thus be appropriate regardless of whether space limitations are a concern. We introduce, implement, and characterize a new lossy compression scheme suitable for IEEE floating-point data. Our new Bit Grooming algorithm alternately shaves (to zero) and sets (to one) the least significant bits ofmore » consecutive values to preserve a desired precision. This is a symmetric, two-sided variant of an algorithm sometimes called Bit Shaving that quantizes values solely by zeroing bits. Our variation eliminates the artificial low bias produced by always zeroing bits, and makes Bit Grooming more suitable for arrays and multi-dimensional fields whose mean statistics are important. Bit Grooming relies on standard lossless compression to achieve the actual reduction in storage space, so we tested Bit Grooming by applying the DEFLATE compression algorithm to bit-groomed and full-precision climate data stored in netCDF3, netCDF4, HDF4, and HDF5 formats. Bit Grooming reduces the storage space required by initially uncompressed and compressed climate data by 25–80 and 5–65 %, respectively, for single-precision values (the most common case for climate data) quantized to retain 1–5 decimal digits of precision. The potential reduction is greater for double-precision datasets. When used aggressively (i.e., preserving only 1–2 digits), Bit Grooming produces storage reductions comparable to other quantization techniques such as Linear Packing. Unlike Linear Packing, whose guaranteed precision rapidly degrades within the relatively narrow dynamic range of values that it can compress, Bit Grooming guarantees the specified precision throughout the full floating-point range. Data quantization by Bit Grooming is irreversible (i.e., lossy) yet transparent, meaning that no extra processing is required by data users/readers. Hence Bit Grooming can easily reduce data storage volume without sacrificing scientific precision or imposing extra burdens on users.« less

SignalPlant: an open signal processing software platform.

PubMed

Plesinger, F; Jurco, J; Halamek, J; Jurak, P

2016-07-01

The growing technical standard of acquisition systems allows the acquisition of large records, often reaching gigabytes or more in size as is the case with whole-day electroencephalograph (EEG) recordings, for example. Although current 64-bit software for signal processing is able to process (e.g. filter, analyze, etc) such data, visual inspection and labeling will probably suffer from rather long latency during the rendering of large portions of recorded signals. For this reason, we have developed SignalPlant-a stand-alone application for signal inspection, labeling and processing. The main motivation was to supply investigators with a tool allowing fast and interactive work with large multichannel records produced by EEG, electrocardiograph and similar devices. The rendering latency was compared with EEGLAB and proves significantly faster when displaying an image from a large number of samples (e.g. 163-times faster for 75  ×  10(6) samples). The presented SignalPlant software is available free and does not depend on any other computation software. Furthermore, it can be extended with plugins by third parties ensuring its adaptability to future research tasks and new data formats.

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

Miniaturized module for the wireless transmission of measurements with Bluetooth.

PubMed

Roth, H; Schwaibold, M; Moor, C; Schöchlin, J; Bolz, A

2002-01-01

The wiring of patients for obtaining medical measurements has many disadvantages. In order to limit these, a miniaturized module was developed which digitalizes analog signals and sends the signal wirelessly to the receiver using Bluetooth. Bluetooth is especially suitable for this application because distances of up to 10 m are possible with low power consumption and robust transmission with encryption. The module consists of a Bluetooth chip, which is initialized in such a way by a microcontroller that connections from other bluetooth receivers can be accepted. The signals are then transmitted to the distant end. The maximum bit rate of the 23 mm x 30 mm module is 73.5 kBit/s. At 4.7 kBit/s, the current consumption is 12 mA.

Multi-channel imaging cytometry with a single detector

NASA Astrophysics Data System (ADS)

Locknar, Sarah; Barton, John; Entwistle, Mark; Carver, Gary; Johnson, Robert

2018-02-01

Multi-channel microscopy and multi-channel flow cytometry generate high bit data streams. Multiple channels (both spectral and spatial) are important in diagnosing diseased tissue and identifying individual cells. Omega Optical has developed techniques for mapping multiple channels into the time domain for detection by a single high gain, high bandwidth detector. This approach is based on pulsed laser excitation and a serial array of optical fibers coated with spectral reflectors such that up to 15 wavelength bins are sequentially detected by a single-element detector within 2.5 μs. Our multichannel microscopy system uses firmware running on dedicated DSP and FPGA chips to synchronize the laser, scanning mirrors, and sampling clock. The signals are digitized by an NI board into 14 bits at 60MHz - allowing for 232 by 174 pixel fields in up to 15 channels with 10x over sampling. Our multi-channel imaging cytometry design adds channels for forward scattering and back scattering to the fluorescence spectral channels. All channels are detected within the 2.5 μs - which is compatible with fast cytometry. Going forward, we plan to digitize at 16 bits with an A-toD chip attached to a custom board. Processing these digital signals in custom firmware would allow an on-board graphics processing unit to display imaging flow cytometry data over configurable scanning line lengths. The scatter channels can be used to trigger data buffering when a cell is present in the beam. This approach enables a low cost mechanically robust imaging cytometer.

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

NASA Astrophysics Data System (ADS)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

Nonlinearity-aware 200  Gbit/s DMT transmission for C-band short-reach optical interconnects with a single packaged electro-absorption modulated laser.

PubMed

Zhang, Lu; Hong, Xuezhi; Pang, Xiaodan; Ozolins, Oskars; Udalcovs, Aleksejs; Schatz, Richard; Guo, Changjian; Zhang, Junwei; Nordwall, Fredrik; Engenhardt, Klaus M; Westergren, Urban; Popov, Sergei; Jacobsen, Gunnar; Xiao, Shilin; Hu, Weisheng; Chen, Jiajia

2018-01-15

We experimentally demonstrate the transmission of a 200 Gbit/s discrete multitone (DMT) at the soft forward error correction limit in an intensity-modulation direct-detection system with a single C-band packaged distributed feedback laser and traveling-wave electro absorption modulator (DFB-TWEAM), digital-to-analog converter and photodiode. The bit-power loaded DMT signal is transmitted over 1.6 km standard single-mode fiber with a net rate of 166.7 Gbit/s, achieving an effective electrical spectrum efficiency of 4.93 bit/s/Hz. Meanwhile, net rates of 174.2 Gbit/s and 179.5 Gbit/s are also demonstrated over 0.8 km SSMF and in an optical back-to-back case, respectively. The feature of the packaged DFB-TWEAM is presented. The nonlinearity-aware digital signal processing algorithm for channel equalization is mathematically described, which improves the signal-to-noise ratio up to 3.5 dB.

Development of signal processing system of avalanche photo diode for space observations by Astro-H

NASA Astrophysics Data System (ADS)

Ohno, M.; Goto, K.; Hanabata, Y.; Takahashi, H.; Fukazawa, Y.; Yoshino, M.; Saito, T.; Nakamori, T.; Kataoka, J.; Sasano, M.; Torii, S.; Uchiyama, H.; Nakazawa, K.; Watanabe, S.; Kokubun, M.; Ohta, M.; Sato, T.; Takahashi, T.; Tajima, H.

2013-01-01

Astro-H is the sixth Japanese X-ray space observatory which will be launched in 2014. Two of onboard instruments of Astro-H, Hard X-ray Imager and Soft Gamma-ray Detector are surrounded by many number of large Bismuth Germanate (Bi4Ge3O12; BGO) scintillators. Optimum readout system of scintillation lights from these BGOs are essential to reduce the background signals and achieve high performance for main detectors because most of gamma-rays from out of field-of-view of main detectors or radio-isotopes produced inside them due to activation can be eliminated by anti-coincidence technique using BGO signals. We apply Avalanche Photo Diode (APD) for light sensor of these BGO detectors since their compactness and high quantum efficiency make it easy to design such large number of BGO detector system. For signal processing from APDs, digital filter and other trigger logics on the Field-Programmable Gate Array (FPGA) is used instead of discrete analog circuits due to limitation of circuit implementation area on spacecraft. For efficient observations, we have to achieve as low threshold of anti-coincidence signal as possible by utilizing the digital filtering. In addition, such anti-coincident signals should be sent to the main detector within 5 μs to make it in time to veto the A-D conversion. Considering this requirement and constraint from logic size of FPGA, we adopt two types of filter, 8 delay taps filter with only 2 bit precision coefficient and 16 delay taps filter with 8 bit precision coefficient. The data after former simple filter provides anti-coincidence signal quickly in orbit, and the latter filter is used for detail analysis after the data is down-linked.

A study of FM threshold extension techniques

NASA Technical Reports Server (NTRS)

Arndt, G. D.; Loch, F. J.

1972-01-01

The characteristics of three postdetection threshold extension techniques are evaluated with respect to the ability of such techniques to improve the performance of a phase lock loop demodulator. These techniques include impulse-noise elimination, signal correlation for the detection of impulse noise, and delta modulation signal processing. Experimental results from signal to noise ratio data and bit error rate data indicate that a 2- to 3-decibel threshold extension is readily achievable by using the various techniques. This threshold improvement is in addition to the threshold extension that is usually achieved through the use of a phase lock loop demodulator.

On the Mutual Information of Multi-hop Acoustic Sensors Network in Underwater Wireless Communication

DTIC Science & Technology

2014-05-01

DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. The University of the District of Columbia Computer Science and Informati Briana Lowe Wellman Washington...financial support throughout my Master’s study and research. Also, I would like to acknowledge the Faculty of the Electrical and Computer Engineering...received bits are in error, and then compute the bit-error-rate as the number of bit errors divided by the total number of bits in the transmitted signal

Method and apparatus for analog signal conditioner for high speed, digital x-ray spectrometer

DOEpatents

Warburton, W.K.; Hubbard, B.

1999-02-09

A signal processing system which accepts input from an x-ray detector-preamplifier and produces a signal of reduced dynamic range for subsequent analog-to-digital conversion is disclosed. The system conditions the input signal to reduce the number of bits required in the analog-to-digital converter by removing that part of the input signal which varies only slowly in time and retaining the amplitude of the pulses which carry information about the x-rays absorbed by the detector. The parameters controlling the signal conditioner`s operation can be readily supplied in digital form, allowing it to be integrated into a feedback loop as part of a larger digital x-ray spectroscopy system. 13 figs.

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate ( C'' or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability bymore » using DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate (``C`` or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability by usingmore » DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

A Compressed Sensing Based Ultra-Wideband Communication System

DTIC Science & Technology

2009-06-01

principle, most of the processing at the receiver can be moved to the transmitter—where energy consumption and computation are sufficient for many advanced...extended to continuous time signals. We use ∗ to denote the convolution process in a linear time-invariant (LTI) system. Assume that there is an analog...Filter Channel Low Rate A/D Processing Sparse Bit Sequence UWB Pulse Generator α̂ Waves)(RadioGHz 5 MHz125 θ Ψ Φ y θ̂ 1 ˆ arg min s.t. yθ

Hydraulic impulse generator and frequency sweep mechanism for borehole applications

DOEpatents

Kolle, Jack J.; Marvin, Mark H.; Theimer, Kenneth J.

2006-11-21

This invention discloses a valve that generates a hydraulic negative pressure pulse and a frequency modulator for the creation of a powerful, broadband swept impulse seismic signal at the drill bit during drilling operations. The signal can be received at monitoring points on the surface or underground locations using geophones. The time required for the seismic signal to travel from the source to the receiver directly and via reflections is used to calculate seismic velocity and other formation properties near the source and between the source and receiver. This information can be used for vertical seismic profiling of formations drilled, to check the location of the bit, or to detect the presence of abnormal pore pressure ahead of the bit. The hydraulic negative pressure pulse can also be used to enhance drilling and production of wells.

Inter-track interference mitigation with two-dimensional variable equalizer for bit patterned media recording

NASA Astrophysics Data System (ADS)

Wang, Yao; Vijaya Kumar, B. V. K.

2017-05-01

The increased track density in bit patterned media recording (BPMR) causes increased inter-track interference (ITI), which degrades the bit error rate (BER) performance. In order to mitigate the effect of the ITI, signals from multiple tracks can be equalized by a 2D equalizer with 1D target. Usually, the 2D fixed equalizer coefficients are obtained by using a pseudo-random bit sequence (PRBS) for training. In this study, a 2D variable equalizer is proposed, where various sets of 2D equalizer coefficients are predetermined and stored for different ITI patterns besides the usual PRBS training. For data detection, as the ITI patterns are unknown in the first global iteration, the main and adjacent tracks are equalized with the conventional 2D fixed equalizer, detected with Bahl-Cocke-Jelinek-Raviv (BCJR) detector and decoded with low-density parity-check (LDPC) decoder. Then using the estimated bit information from main and adjacent tracks, the ITI pattern for each island of the main track can be estimated and the corresponding 2D variable equalizers are used to better equalize the bits on the main track. This process is executed iteratively by feeding back the main track information. Simulation results indicate that for both single-track and two-track detection, the proposed 2D variable equalizer can achieve better BER and frame error rate (FER) compared to that with the 2D fixed equalizer.

Pulse transmission receiver with higher-order time derivative pulse generator

DOEpatents

Dress, Jr., William B.; Smith, Stephen F.

2003-08-12

Systems and methods for pulse-transmission low-power communication modes are disclosed. A pulse transmission receiver includes: a front-end amplification/processing circuit; a synchronization circuit coupled to the front-end amplification/processing circuit; a clock coupled to the synchronization circuit; a trigger signal generator coupled to the clock; and at least one higher-order time derivative pulse generator coupled to the trigger signal generator. The systems and methods significantly reduce lower-frequency emissions from pulse transmission spread-spectrum communication modes, which reduces potentially harmful interference to existing radio frequency services and users and also simultaneously permit transmission of multiple data bits by utilizing specific pulse shapes.

Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

PubMed

Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

2011-06-06

We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

Integrated unaligned resonant modulator tuning

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zortman, William A.; Lentine, Anthony L.

Methods and systems for tuning a resonant modulator are disclosed. One method includes receiving a carrier signal modulated by the resonant modulator with a stream of data having an approximately equal number of high and low bits, determining an average power of the modulated carrier signal, comparing the average power to a predetermined threshold, and operating a tuning device coupled to the resonant modulator based on the comparison of the average power and the predetermined threshold. One system includes an input structure, a plurality of processing elements, and a digital control element. The input structure is configured to receive, frommore » the resonant modulator, a modulated carrier signal. The plurality of processing elements are configured to determine an average power of the modulated carrier signal. The digital control element is configured to operate a tuning device coupled to the resonant modulator based on the average power of the modulated carrier signal.« less

Delta modulation

NASA Technical Reports Server (NTRS)

Schilling, D. L.

1971-01-01

The conclusions of the design research of the song adaptive delta modulator are presented for source encoding voice signals. The variation of output SNR vs input signal power/when 8, 9, and 10 bit internal arithmetic is employed. Voice intelligibility tapes to test the 10-bit system are used. An analysis of a delta modulator is also presented designed to minimize the in-band rms error. This is accomplished by frequency shaping the error signal in the modulator prior to hard limiting. The result is a significant increase in the output SNR measured after low pass filtering.

Dispersion and dispersion slope compensation impact on high channel bit rate optical signal transmission degradation

NASA Astrophysics Data System (ADS)

Hamidine, Mahamadou; Yuan, Xiuhua

2011-11-01

In this article a numerical simulation is carried out on a single channel optical transmission system with channel bit rate greater than 40 Gb/s to investigate optical signal degradation due to the impact of dispersion and dispersion slope of both transmitting and dispersion compensating fibers. By independently varying the input signal power and the dispersion slope of both transmitting and dispersion compensating fibers of an optical link utilizing a channel bit rate of 86 Gb/s, a good quality factor (Q factor) is obtained with a dispersion slope compensation ratio change of +/-10% for a faithful transmission. With this ratio change a minimum Q factor of 16 dB is obtained in the presence of amplifier noise figure of 5 dB and fiber nonlinearities effects at input signal power of 5 dBm and 3 spans of 100 km standard single mode fiber with a dispersion (D) value of 17 ps/nm.km.

Error control techniques for satellite and space communications

NASA Technical Reports Server (NTRS)

Costello, Daniel J., Jr.

1991-01-01

Shannon's capacity bound shows that coding can achieve large reductions in the required signal to noise ratio per information bit (E sub b/N sub 0 where E sub b is the energy per bit and (N sub 0)/2 is the double sided noise density) in comparison to uncoded schemes. For bandwidth efficiencies of 2 bit/sym or greater, these improvements were obtained through the use of Trellis Coded Modulation and Block Coded Modulation. A method of obtaining these high efficiencies using multidimensional Multiple Phase Shift Keying (MPSK) and Quadrature Amplitude Modulation (QAM) signal sets with trellis coding is described. These schemes have advantages in decoding speed, phase transparency, and coding gain in comparison to other trellis coding schemes. Finally, a general parity check equation for rotationally invariant trellis codes is introduced from which non-linear codes for two dimensional MPSK and QAM signal sets are found. These codes are fully transparent to all rotations of the signal set.

An overview of Space Communication Artificial Intelligence for Link Evaluation Terminal (SCAILET) Project

NASA Technical Reports Server (NTRS)

Shahidi, Anoosh K.; Schlegelmilch, Richard F.; Petrik, Edward J.; Walters, Jerry L.

1991-01-01

A software application to assist end-users of the link evaluation terminal (LET) for satellite communications is being developed. This software application incorporates artificial intelligence (AI) techniques and will be deployed as an interface to LET. The high burst rate (HBR) LET provides 30 GHz transmitting/20 GHz receiving (220/110 Mbps) capability for wideband communications technology experiments with the Advanced Communications Technology Satellite (ACTS). The HBR LET can monitor and evaluate the integrity of the HBR communications uplink and downlink to the ACTS satellite. The uplink HBR transmission is performed by bursting the bit-pattern as a modulated signal to the satellite. The HBR LET can determine the bit error rate (BER) under various atmospheric conditions by comparing the transmitted bit pattern with the received bit pattern. An algorithm for power augmentation will be applied to enhance the system's BER performance at reduced signal strength caused by adverse conditions.

Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

NASA Astrophysics Data System (ADS)

Xue, F.; Gao, W.; Duan, Y.; Zheng, R.; Hu, Y.

2018-02-01

This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using Vcm-based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 V supply. The chip occupies a core area of only 0.58 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 66.7 dB and a peak spurious-free dynamic range (SFDR) of 78.6 dB at 10 MS/s sampling rate and consumes 10 mW. The figure of merit (FOM) of the proposed ADC is 0.56 pJ/conversion-step.

Reconfigurable data path processor

NASA Technical Reports Server (NTRS)

Donohoe, Gregory (Inventor)

2005-01-01

A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.

Novel multireceiver communication systems configurations based on optimal estimation theory

NASA Technical Reports Server (NTRS)

Kumar, Rajendra

1992-01-01

A novel multireceiver configuration for carrier arraying and/or signal arraying is presented. The proposed configuration is obtained by formulating the carrier and/or signal arraying problem as an optimal estimation problem, and it consists of two stages. The first stage optimally estimates various phase processes received at different receivers with coupled phase-locked loops wherein the individual loops acquire and track their respective receivers' phase processes but are aided by each other in an optimal manner via LF error signals. The proposed configuration results in the minimization of the the effective radio loss at the combiner output, and thus maximization of energy per bit to noise power spectral density ratio is achieved. A novel adaptive algorithm for the estimator of the signal model parameters when these are not known a priori is also presented.

Designed cell consortia as fragrance-programmable analog-to-digital converters.

PubMed

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

UWB communication receiver feedback loop

DOEpatents

Spiridon, Alex; Benzel, Dave; Dowla, Farid U.; Nekoogar, Faranak; Rosenbury, Erwin T.

2007-12-04

A novel technique and structure that maximizes the extraction of information from reference pulses for UWB-TR receivers is introduced. The scheme efficiently processes an incoming signal to suppress different types of UWB as well as non-UWB interference prior to signal detection. Such a method and system adds a feedback loop mechanism to enhance the signal-to-noise ratio of reference pulses in a conventional TR receiver. Moreover, sampling the second order statistical function such as, for example, the autocorrelation function (ACF) of the received signal and matching it to the ACF samples of the original pulses for each transmitted bit provides a more robust UWB communications method and system in the presence of channel distortions.

Spline-based high-accuracy piecewise-polynomial phase-to-sinusoid amplitude converters.

PubMed

Petrinović, Davor; Brezović, Marko

2011-04-01

We propose a method for direct digital frequency synthesis (DDS) using a cubic spline piecewise-polynomial model for a phase-to-sinusoid amplitude converter (PSAC). This method offers maximum smoothness of the output signal. Closed-form expressions for the cubic polynomial coefficients are derived in the spectral domain and the performance analysis of the model is given in the time and frequency domains. We derive the closed-form performance bounds of such DDS using conventional metrics: rms and maximum absolute errors (MAE) and maximum spurious free dynamic range (SFDR) measured in the discrete time domain. The main advantages of the proposed PSAC are its simplicity, analytical tractability, and inherent numerical stability for high table resolutions. Detailed guidelines for a fixed-point implementation are given, based on the algebraic analysis of all quantization effects. The results are verified on 81 PSAC configurations with the output resolutions from 5 to 41 bits by using a bit-exact simulation. The VHDL implementation of a high-accuracy DDS based on the proposed PSAC with 28-bit input phase word and 32-bit output value achieves SFDR of its digital output signal between 180 and 207 dB, with a signal-to-noise ratio of 192 dB. Its implementation requires only one 18 kB block RAM and three 18-bit embedded multipliers in a typical field-programmable gate array (FPGA) device. © 2011 IEEE

Random numbers from vacuum fluctuations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Yicheng; Kurtsiefer, Christian, E-mail: christian.kurtsiefer@gmail.com; Center for Quantum Technologies, National University of Singapore, 3 Science Drive 2, Singapore 117543

2016-07-25

We implement a quantum random number generator based on a balanced homodyne measurement of vacuum fluctuations of the electromagnetic field. The digitized signal is directly processed with a fast randomness extraction scheme based on a linear feedback shift register. The random bit stream is continuously read in a computer at a rate of about 480 Mbit/s and passes an extended test suite for random numbers.

Space-Time Processing for Tactical Mobile Ad Hoc Networks

DTIC Science & Technology

2009-08-01

the results for the standard 8 bits per pixel ( bpp ) 512512 Lena image [3] with a transmission rate of 0.375 bpp . To compare the image quality, we...use peak-signal-to-noise ratio (PSNR), defined as  DE 2255 log10PSNR  (dB) (2) where 255 is due to the 8 bpp image

High-gain 1.3  μm GaInNAs semiconductor optical amplifier with enhanced temperature stability for all-optical signal processing at 10  Gb/s.

PubMed

Fitsios, D; Giannoulis, G; Korpijärvi, V-M; Viheriälä, J; Laakso, A; Iliadis, N; Dris, S; Spyropoulou, M; Avramopoulos, H; Kanellos, G T; Pleros, N; Guina, M

2015-01-01

We report on the complete experimental evaluation of a GaInNAs/GaAs (dilute nitride) semiconductor optical amplifier that operates at 1.3 μm and exhibits 28 dB gain and a gain recovery time of 100 ps. Successful wavelength conversion operation is demonstrated using pseudorandom bit sequence 2⁷-1 non-return-to-zero bit streams at 5 and 10  Gb/s, yielding error-free performance and showing feasibility for implementation in various signal processing functionalities. The operational credentials of the device are analyzed in various operational regimes, while its nonlinear performance is examined in terms of four-wave mixing. Moreover, characterization results reveal enhanced temperature stability with almost no gain variation around the 1320 nm region for a temperature range from 20°C to 50°C. The operational characteristics of the device, along with the cost and energy benefits of dilute nitride technology, make it very attractive for application in optical access networks and dense photonic integrated circuits.

Signal design study for shuttle/TDRSS Ku-band uplink

NASA Technical Reports Server (NTRS)

1976-01-01

The adequacy of the signal design approach chosen for the TDRSS/orbiter uplink was evaluated. Critical functions and/or components associated with the baseline design were identified, and design alternatives were developed for those areas considered high risk. A detailed set of RF and signal processing performance specifications for the orbiter hardware associated with the TDRSS/orbiter Ku band uplink was analyzed. Performances of a detailed design of the PN despreader, the PSK carrier synchronization loop, and the symbol synchronizer are identified. The performance of the downlink signal by means of computer simulation to obtain a realistic determination of bit error rate degradations was studied. The three channel PM downlink signal was detailed by means of analysis and computer simulation.

Equipment for the Transient Capture of Chaotic Microwave Signals

DTIC Science & Technology

2017-09-14

estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the... times are needed and over-sampling by a factor of 8 is required so that the effective number of bits can be increased from the actual bit resolution... time acquisition of transient signals with analog bandwidths up to 70 GHz for one channel, and 30 GHz for two channels.. Training Opportunities

High range free space optic transmission using new dual diffuser modulation technique

NASA Astrophysics Data System (ADS)

Rahman, A. K.; Julai, N.; Jusoh, M.; Rashidi, C. B. M.; Aljunid, S. A.; Anuar, M. S.; Talib, M. F.; Zamhari, Nurdiani; Sahari, S. k.; Tamrin, K. F.; Jong, Rudiyanto P.; Zaidel, D. N. A.; Mohtadzar, N. A. A.; Sharip, M. R. M.; Samat, Y. S.

2017-11-01

Free space optical communication fsoc is vulnerable with fluctuating atmospheric. This paper focus analyzes the finding of new technique dual diffuser modulation (ddm) to mitigate the atmospheric turbulence effect. The performance of fsoc under the presence of atmospheric turbulence will cause the laser beam keens to (a) beam wander, (b) beam spreading and (c) scintillation. The most deteriorate the fsoc is scintillation where it affected the wavefront cause to fluctuating signal and ultimately receiver can turn into saturate or loss signal. Ddm approach enhances the detecting bit `1' and bit `0' and improves the power received to combat with turbulence effect. The performance focus on signal-to-noise (snr) and bit error rate (ber) where the numerical result shows that the ddm technique able to improves the range where estimated approximately 40% improvement under weak turbulence and 80% under strong turbulence.

Digital pulse processing for planar TlBr detectors

NASA Astrophysics Data System (ADS)

Nakhostin, M.; Hitomi, K.; Ishii, K.; Kikuchi, Y.

2010-04-01

We report on a digital pulse processing algorithm for correction of charge trapping in the planar TlBr detectors. The algorithm is performed on the signals digitized at the preamplifier stage. The algorithm is very simple and is implemented with little computational effort. By using a digitizer with a sampling rate of 250 MSample/s and 8 bit resolution, an energy resolution of 6.5% is achieved at 511 keV with a 0.7 mm thick detector.

Audiovisual signal compression: the 64/P codecs

NASA Astrophysics Data System (ADS)

Jayant, Nikil S.

1996-02-01

Video codecs operating at integral multiples of 64 kbps are well-known in visual communications technology as p * 64 systems (p equals 1 to 24). Originally developed as a class of ITU standards, these codecs have served as core technology for videoconferencing, and they have also influenced the MPEG standards for addressable video. Video compression in the above systems is provided by motion compensation followed by discrete cosine transform -- quantization of the residual signal. Notwithstanding the promise of higher bit rates in emerging generations of networks and storage devices, there is a continuing need for facile audiovisual communications over voice band and wireless modems. Consequently, video compression at bit rates lower than 64 kbps is a widely-sought capability. In particular, video codecs operating at rates in the neighborhood of 64, 32, 16, and 8 kbps seem to have great practical value, being matched respectively to the transmission capacities of basic rate ISDN (64 kbps), and voiceband modems that represent high (32 kbps), medium (16 kbps) and low- end (8 kbps) grades in current modem technology. The purpose of this talk is to describe the state of video technology at these transmission rates, without getting too literal about the specific speeds mentioned above. In other words, we expect codecs designed for non- submultiples of 64 kbps, such as 56 kbps or 19.2 kbps, as well as for sub-multiples of 64 kbps, depending on varying constraints on modem rate and the transmission rate needed for the voice-coding part of the audiovisual communications link. The MPEG-4 video standards process is a natural platform on which to examine current capabilities in sub-ISDN rate video coding, and we shall draw appropriately from this process in describing video codec performance. Inherent in this summary is a reinforcement of motion compensation and DCT as viable building blocks of video compression systems, although there is a need for improving signal quality even in the very best of these systems. In a related part of our talk, we discuss the role of preprocessing and postprocessing subsystems which serve to enhance the performance of an otherwise standard codec. Examples of these (sometimes proprietary) subsystems are automatic face-tracking prior to the coding of a head-and-shoulders scene, and adaptive postfiltering after conventional decoding, to reduce generic classes of artifacts in low bit rate video. The talk concludes with a summary of technology targets and research directions. We discuss targets in terms of four fundamental parameters of coder performance: quality, bit rate, delay and complexity; and we emphasize the need for measuring and maximizing the composite quality of the audiovisual signal. In discussing research directions, we examine progress and opportunities in two fundamental approaches for bit rate reduction: removal of statistical redundancy and reduction of perceptual irrelevancy; we speculate on the value of techniques such as analysis-by-synthesis that have proved to be quite valuable in speech coding, and we examine the prospect of integrating speech and image processing for developing next-generation technology for audiovisual communications.

An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection.

PubMed

Perelman, Yevgeny; Ginosar, Ran

2007-01-01

A mixed-signal front-end processor for multichannel neuronal recording is described. It receives 12 differential-input channels of implanted recording electrodes. A programmable cutoff High Pass Filter (HPF) blocks dc and low-frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency Local Field Potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF, in a range of 8-13 kHz. Amplifier offsets are compensated by 5-bit calibration digital-to-analog converters (DACs). The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into 10-bit digital form, and streamed out over a serial digital bus at up to 8 Mbps. A threshold filter suppresses inactive portions of the signal and emits only spike segments of programmable length. A prototype has been fabricated on a 0.35-microm CMOS process and tested successfully, demonstrating a 3-microV noise level. Special interface system incorporating an embedded CPU core in a programmable logic device accompanied by real-time software has been developed to allow connectivity to a computer host.

Pseudo Asynchronous Level Crossing adc for ecg Signal Acquisition.

PubMed

Marisa, T; Niederhauser, T; Haeberlin, A; Wildhaber, R A; Vogel, R; Goette, J; Jacomet, M

2017-02-07

A new pseudo asynchronous level crossing analogue-to-digital converter (adc) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing adc designs, the proposed design has no digital-to-analogue converter (dac) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed adc was implemented in [Formula: see text] complementary metal-oxide-semiconductor (cmos) technology, the hardware occupies a chip area of 0.0372 mm 2 and operates from a supply voltage of [Formula: see text] to [Formula: see text]. The adc's power consumption is as low as 0.6 μW with signal bandwidth from [Formula: see text] to [Formula: see text] and achieves an equivalent number of bits (enob) of up to 8 bits.

A versatile microprocessor-controlled hybrid receiver. [with firmware control for operation over large frequency uncertainty

NASA Technical Reports Server (NTRS)

Grant, T. L.

1978-01-01

A hybrid receiver has been designed for the Galileo Project. The receiver, located on the Galileo Orbiter, will autonomously acquire and track signals from the first atmospheric probe of Jupiter as well as demodulate, bit-synchronize, and buffer the telemetry data. The receiver has a conventional RF and LF front end but performs multiple functions digitally under firmware control. It will be a self-acquiring receiver that operates under a large frequency uncertainty; it can accommodate different modulation types, bit rates, and other parameter changes via reprogramming. A breadboard receiver and test set demonstrate a preliminary version of the sequential detection process and verify the hypothesis that a fading channel does not reduce the probability of detection.

Note: optical receiver system for 152-channel magnetoencephalography.

PubMed

Kim, Jin-Mok; Kwon, Hyukchan; Yu, Kwon-kyu; Lee, Yong-Ho; Kim, Kiwoong

2014-11-01

An optical receiver system composing 13 serial data restore/synchronizer modules and a single module combiner converted optical 32-bit serial data into 32-bit synchronous parallel data for a computer to acquire 152-channel magnetoencephalography (MEG) signals. A serial data restore/synchronizer module identified 32-bit channel-voltage bits from 48-bit streaming serial data, and then consecutively reproduced 13 times of 32-bit serial data, acting in a synchronous clock. After selecting a single among 13 reproduced data in each module, a module combiner converted it into 32-bit parallel data, which were carried to 32-port digital input board in a computer. When the receiver system together with optical transmitters were applied to 152-channel superconducting quantum interference device sensors, this MEG system maintained a field noise level of 3 fT/√Hz @ 100 Hz at a sample rate of 1 kSample/s per channel.

A fast combination calibration of foreground and background for pipelined ADCs

NASA Astrophysics Data System (ADS)

Kexu, Sun; Lenian, He

2012-06-01

This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters (MDACs). The considered calibration technique takes the advantages of both foreground and background calibration schemes. In this combination calibration algorithm, a novel parallel background calibration with signal-shifted correlation is proposed, and its calibration cycle is very short. The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC. The high convergence speed of this background calibration is achieved by three means. First, a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code. Second, before correlating the signal, it is shifted according to the input signal so that the correlation error converges quickly. Finally, the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants. Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2 × 221 conversions.

A simple encoding method for Sigma-Delta ADC based biopotential acquisition systems.

PubMed

Guerrero, Federico N; Spinelli, Enrique M

2017-10-01

Sigma Delta analogue-to-digital converters allow acquiring the full dynamic range of biomedical signals at the electrodes, resulting in less complex hardware and increased measurement robustness. However, the increased data size per sample (typically 24 bits) demands the transmission of extremely large volumes of data across the isolation barrier, thus increasing power consumption on the patient side. This problem is accentuated when a large number of channels is used as in current 128-256 electrodes biopotential acquisition systems, that usually opt for an optic fibre link to the computer. An analogous problem occurs for simpler low-power acquisition platforms that transmit data through a wireless link to a computing platform. In this paper, a low-complexity encoding method is presented to decrease sample data size without losses, while preserving the full DC-coupled signal. The method achieved a 2.3 average compression ratio evaluated over an ECG and EMG signal bank acquired with equipment based on Sigma-Delta converters. It demands a very low processing load: a C language implementation is presented that resulted in an 110 clock cycles average execution on an 8-bit microcontroller.

An ultra low-power front-end IC for wearable health monitoring system.

PubMed

Yu-Pin Hsu; Zemin Liu; Hella, Mona M

2016-08-01

This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

Tunable all-optical signal regenerator with a semiconductor optical amplifier and a Sagnac loop: principles of operation

NASA Astrophysics Data System (ADS)

Granot, Er'el; Zaibel, Reuven; Narkiss, Niv; Ben-Ezra, Shalva; Chayet, Haim; Shahar, Nir; Sternklar, Shmuel; Tsadka, Sagie; Prucnal, Paul R.

2005-12-01

In this paper we investigate the wavelength conversion and regeneration properties of a tunable all-optical signal regenerator (TASR). In the TASR, the wavelength conversion is done by a semiconductor optical amplifier, which is incorporated in an asymmetric Sagnac loop (ASL). We demonstrate both theoretically and experimentally that the ASL regenerates the incident signal's bit pattern, reduces its noise, increases the extinction ratio (which in many aspects is equivalent to noise reduction) and improves its bit-error rate. We also demonstrate the general behavior of the TASR with a numerical simulation.

Practical quantum key distribution protocol without monitoring signal disturbance.

PubMed

Sasaki, Toshihiko; Yamamoto, Yoshihisa; Koashi, Masato

2014-05-22

Quantum cryptography exploits the fundamental laws of quantum mechanics to provide a secure way to exchange private information. Such an exchange requires a common random bit sequence, called a key, to be shared secretly between the sender and the receiver. The basic idea behind quantum key distribution (QKD) has widely been understood as the property that any attempt to distinguish encoded quantum states causes a disturbance in the signal. As a result, implementation of a QKD protocol involves an estimation of the experimental parameters influenced by the eavesdropper's intervention, which is achieved by randomly sampling the signal. If the estimation of many parameters with high precision is required, the portion of the signal that is sacrificed increases, thus decreasing the efficiency of the protocol. Here we propose a QKD protocol based on an entirely different principle. The sender encodes a bit sequence onto non-orthogonal quantum states and the receiver randomly dictates how a single bit should be calculated from the sequence. The eavesdropper, who is unable to learn the whole of the sequence, cannot guess the bit value correctly. An achievable rate of secure key distribution is calculated by considering complementary choices between quantum measurements of two conjugate observables. We found that a practical implementation using a laser pulse train achieves a key rate comparable to a decoy-state QKD protocol, an often-used technique for lasers. It also has a better tolerance of bit errors and of finite-sized-key effects. We anticipate that this finding will give new insight into how the probabilistic nature of quantum mechanics can be related to secure communication, and will facilitate the simple and efficient use of conventional lasers for QKD.

Performance of the unique-word-reverse-modulation type demodulator for mobile satellite communications

NASA Technical Reports Server (NTRS)

Dohi, Tomohiro; Nitta, Kazumasa; Ueda, Takashi

1993-01-01

This paper proposes a new type of coherent demodulator, the unique-word (UW)-reverse-modulation type demodulator, for burst signal controlled by voice operated transmitter (VOX) in mobile satellite communication channels. The demodulator has three individual circuits: a pre-detection signal combiner, a pre-detection UW detector, and a UW-reverse-modulation type demodulator. The pre-detection signal combiner combines signal sequences received by two antennas and improves bit energy-to-noise power density ratio (E(sub b)/N(sub 0)) 2.5 dB to yield 10(exp -3) average bit error rate (BER) when carrier power-to-multipath power ratio (CMR) is 15 dB. The pre-detection UW detector improves UW detection probability when the frequency offset is large. The UW-reverse-modulation type demodulator realizes a maximum pull-in frequency of 3.9 kHz, the pull-in time is 2.4 seconds and frequency error is less than 20 Hz. The performances of this demodulator are confirmed through computer simulations and its effect is clarified in real-time experiments at a bit rate of 16.8 kbps using a digital signal processor (DSP).

Perceptually tuned low-bit-rate video codec for ATM networks

NASA Astrophysics Data System (ADS)

Chou, Chun-Hsien

1996-02-01

In order to maintain high visual quality in transmitting low bit-rate video signals over asynchronous transfer mode (ATM) networks, a layered coding scheme that incorporates the human visual system (HVS), motion compensation (MC), and conditional replenishment (CR) is presented in this paper. An empirical perceptual model is proposed to estimate the spatio- temporal just-noticeable distortion (STJND) profile for each frame, by which perceptually important (PI) prediction-error signals can be located. Because of the limited channel capacity of the base layer, only coded data of motion vectors, the PI signals within a small strip of the prediction-error image and, if there are remaining bits, the PI signals outside the strip are transmitted by the cells of the base-layer channel. The rest of the coded data are transmitted by the second-layer cells which may be lost due to channel error or network congestion. Simulation results show that visual quality of the reconstructed CIF sequence is acceptable when the capacity of the base-layer channel is allocated with 2 multiplied by 64 kbps and the cells of the second layer are all lost.

High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving

NASA Astrophysics Data System (ADS)

Onizawa, Naoya; Hanyu, Takahiro; Gaudet, Vincent C.

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90nm CMOS technology, at a comparable BER.

Two-stage optical recording: photoinduced birefringence and surface-mediated bits storage in bisazo-containing copolymers towards ultrahigh data memory.

PubMed

Hu, Yanlei; Wu, Dong; Li, Jiawen; Huang, Wenhao; Chu, Jiaru

2016-10-03

Ultrahigh density data storage is in high demand in the current age of big data and thus motivates many innovative storage technologies. Femtosecond laser induced multi-dimensional optical data storage is an appealing method to fulfill the demand of ultrahigh storage capacity. Here we report a femtosecond laser induced two-stage optical storage in bisazobenzene copolymer films by manipulating the recording energies. Different mechanisms can be selected for specified memory use: two-photon isomerization (TPI) and laser induced surface deformation. Giant birefringence can be generated by TPI and brings about high signal-to-noise ratio (>20 dB) multi-dimensional reversible storage. Polarization-dependent surface deformation arises when increasing the recording energy, which not only facilitates the multi-level storage by black bits (dots), but also enhances the bits' readout signal and storing stability. This facile bits recording method, which enables completely different recording mechanisms in an identical storage medium, paves the way for sustainable big data storage.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

Real-Time Prediction of Temperature Elevation During Robotic Bone Drilling Using the Torque Signal.

PubMed

Feldmann, Arne; Gavaghan, Kate; Stebinger, Manuel; Williamson, Tom; Weber, Stefan; Zysset, Philippe

2017-09-01

Bone drilling is a surgical procedure commonly required in many surgical fields, particularly orthopedics, dentistry and head and neck surgeries. While the long-term effects of thermal bone necrosis are unknown, the thermal damage to nerves in spinal or otolaryngological surgeries might lead to partial paralysis. Previous models to predict the temperature elevation have been suggested, but were not validated or have the disadvantages of computation time and complexity which does not allow real time predictions. Within this study, an analytical temperature prediction model is proposed which uses the torque signal of the drilling process to model the heat production of the drill bit. A simple Green's disk source function is used to solve the three dimensional heat equation along the drilling axis. Additionally, an extensive experimental study was carried out to validate the model. A custom CNC-setup with a load cell and a thermal camera was used to measure the axial drilling torque and force as well as temperature elevations. Bones with different sets of bone volume fraction were drilled with two drill bits ([Formula: see text]1.8 mm and [Formula: see text]2.5 mm) and repeated eight times. The model was calibrated with 5 of 40 measurements and successfully validated with the rest of the data ([Formula: see text]C). It was also found that the temperature elevation can be predicted using only the torque signal of the drilling process. In the future, the model could be used to monitor and control the drilling process of surgeries close to vulnerable structures.

Convergent optical wired and wireless long-reach access network using high spectral-efficient modulation.

PubMed

Chow, C W; Lin, Y H

2012-04-09

To provide broadband services in a single and low cost perform, the convergent optical wired and wireless access network is promising. Here, we propose and demonstrate a convergent optical wired and wireless long-reach access networks based on orthogonal wavelength division multiplexing (WDM). Both the baseband signal and the radio-over-fiber (ROF) signal are multiplexed and de-multiplexed in optical domain, hence it is simple and the operation speed is not limited by the electronic bottleneck caused by the digital signal processing (DSP). Error-free de-multiplexing and down-conversion can be achieved for all the signals after 60 km (long-reach) fiber transmission. The scalability of the system for higher bit-rate (60 GHz) is also simulated and discussed.

Experimental quantum key distribution with simulated ground-to-satellite photon losses and processing limitations

NASA Astrophysics Data System (ADS)

Bourgoin, Jean-Philippe; Gigov, Nikolay; Higgins, Brendon L.; Yan, Zhizhong; Meyer-Scott, Evan; Khandani, Amir K.; Lütkenhaus, Norbert; Jennewein, Thomas

2015-11-01

Quantum key distribution (QKD) has the potential to improve communications security by offering cryptographic keys whose security relies on the fundamental properties of quantum physics. The use of a trusted quantum receiver on an orbiting satellite is the most practical near-term solution to the challenge of achieving long-distance (global-scale) QKD, currently limited to a few hundred kilometers on the ground. This scenario presents unique challenges, such as high photon losses and restricted classical data transmission and processing power due to the limitations of a typical satellite platform. Here we demonstrate the feasibility of such a system by implementing a QKD protocol, with optical transmission and full post-processing, in the high-loss regime using minimized computing hardware at the receiver. Employing weak coherent pulses with decoy states, we demonstrate the production of secure key bits at up to 56.5 dB of photon loss. We further illustrate the feasibility of a satellite uplink by generating a secure key while experimentally emulating the varying losses predicted for realistic low-Earth-orbit satellite passes at 600 km altitude. With a 76 MHz source and including finite-size analysis, we extract 3374 bits of a secure key from the best pass. We also illustrate the potential benefit of combining multiple passes together: while one suboptimal "upper-quartile" pass produces no finite-sized key with our source, the combination of three such passes allows us to extract 165 bits of a secure key. Alternatively, we find that by increasing the signal rate to 300 MHz it would be possible to extract 21 570 bits of a secure finite-sized key in just a single upper-quartile pass.

Building a Library for Microelectronics Verification with Topological Constraints

DTIC Science & Technology

2017-03-01

Tables 1d, 3b); 1-bit full adder cell (Fig. 1), respectively. Table 5. Frequency distributions for the genus of logically equivalent circuit...Figure 1 shows that switching signal pairs produces logically- equivalent topologies of the 1-bit full adder cell with three values of the genus (g = 3 [1...case], 4, 5, 6). Figure 1. Frequency distribution for logically equivalent circuit topologies of the 1-bit full adder cell (2048) in Table 1(e

Efficient Signal, Code, and Receiver Designs for MIMO Communication Systems

DTIC Science & Technology

2003-06-01

167 5-31 Concatenation of a tilted-QAM inner code with an LDPC outer code with a two component iterative soft-decision decoder. . . . . . . . . 168 5...for AWGN channels has long been studied. There are well-known soft-decision codes like the turbo codes and LDPC codes that can approach capacity to...bits) low density parity check ( LDPC ) code 1. 2. The coded bits are randomly interleaved so that bits nearby go through different sub-channels, and are

The Random Telegraph Signal Behavior of Intermittently Stuck Bits in SDRAMs

NASA Astrophysics Data System (ADS)

Chugg, Andrew Michael; Burnell, Andrew J.; Duncan, Peter H.; Parker, Sarah; Ward, Jonathan J.

2009-12-01

This paper reports behavior analogous to the Random Telegraph Signal (RTS) seen in the leakage currents from radiation induced hot pixels in Charge Coupled Devices (CCDs), but in the context of stuck bits in Synchronous Dynamic Random Access Memories (SDRAMs). Our analysis suggests that pseudo-random sticking and unsticking of the SDRAM bits is due to thermally induced fluctuations in leakage current through displacement damage complexes in depletion regions that were created by high-energy neutron and proton interactions. It is shown that the number of observed stuck bits increases exponentially with temperature, due to the general increase in the leakage currents through the damage centers with temperature. Nevertheless, some stuck bits are seen to pseudo-randomly stick and unstick in the context of a continuously rising trend of temperature, thus demonstrating that their damage centers can exist in multiple widely spaced, discrete levels of leakage current, which is highly consistent with RTS. This implies that these intermittently stuck bits (ISBs) are a displacement damage phenomenon and are unrelated to microdose issues, which is confirmed by the observation that they also occur in unbiased irradiation. Finally, we note that observed variations in the periodicity of the sticking and unsticking behavior on several timescales is most readily explained by multiple leakage current pathways through displacement damage complexes spontaneously and independently opening and closing under the influence of thermal vibrations.

High resolution A/D conversion based on piecewise conversion at lower resolution

DOEpatents

Terwilliger, Steve [Albuquerque, NM

2012-06-05

Piecewise conversion of an analog input signal is performed utilizing a plurality of relatively lower bit resolution A/D conversions. The results of this piecewise conversion are interpreted to achieve a relatively higher bit resolution A/D conversion without sampling frequency penalty.

Deterring watermark collusion attacks using signal processing techniques

NASA Astrophysics Data System (ADS)

Lemma, Aweke N.; van der Veen, Michiel

2007-02-01

Collusion attack is a malicious watermark removal attack in which the hacker has access to multiple copies of the same content with different watermarks and tries to remove the watermark using averaging. In the literature, several solutions to collusion attacks have been reported. The main stream solutions aim at designing watermark codes that are inherently resistant to collusion attacks. The other approaches propose signal processing based solutions that aim at modifying the watermarked signals in such a way that averaging multiple copies of the content leads to a significant degradation of the content quality. In this paper, we present signal processing based technique that may be deployed for deterring collusion attacks. We formulate the problem in the context of electronic music distribution where the content is generally available in the compressed domain. Thus, we first extend the collusion resistance principles to bit stream signals and secondly present experimental based analysis to estimate a bound on the maximum number of modified versions of a content that satisfy good perceptibility requirement on one hand and destructive averaging property on the other hand.

Bit-1 Mediates Integrin-dependent Cell Survival through Activation of the NFκB Pathway*

PubMed Central

Griffiths, Genevieve S.; Grundl, Melanie; Leychenko, Anna; Reiter, Silke; Young-Robbins, Shirley S.; Sulzmaier, Florian J.; Caliva, Maisel J.; Ramos, Joe W.; Matter, Michelle L.

2011-01-01

Loss of properly regulated cell death and cell survival pathways can contribute to the development of cancer and cancer metastasis. Cell survival signals are modulated by many different receptors, including integrins. Bit-1 is an effector of anoikis (cell death due to loss of attachment) in suspended cells. The anoikis function of Bit-1 can be counteracted by integrin-mediated cell attachment. Here, we explored integrin regulation of Bit-1 in adherent cells. We show that knockdown of endogenous Bit-1 in adherent cells decreased cell survival and re-expression of Bit-1 abrogated this effect. Furthermore, reduction of Bit-1 promoted both staurosporine and serum-deprivation induced apoptosis. Indeed knockdown of Bit-1 in these cells led to increased apoptosis as determined by caspase-3 activation and positive TUNEL staining. Bit-1 expression protected cells from apoptosis by increasing phospho-IκB levels and subsequently bcl-2 gene transcription. Protection from apoptosis under serum-free conditions correlated with bcl-2 transcription and Bcl-2 protein expression. Finally, Bit-1-mediated regulation of bcl-2 was dependent on focal adhesion kinase, PI3K, and AKT. Thus, we have elucidated an integrin-controlled pathway in which Bit-1 is, in part, responsible for the survival effects of cell-ECM interactions. PMID:21383007

Optical signal processing for a smart vehicle lighting system using a-SiCH technology

NASA Astrophysics Data System (ADS)

Vieira, M. A.; Vieira, M.; Vieira, P.; Louro, P.

2017-05-01

We propose the use of Visible Light Communication (VLC) for vehicle safety applications, creating a smart vehicle lighting system that combines the functions of illumination and signaling, communications, and positioning. The feasibility of VLC is demonstrated by employing trichromatic Red-Green-Blue (RGB) LEDs as transmitters, since they offer the possibility of Wavelength Division Multiplexing (WDM), which can greatly increase the transmission data rate, when using SiC double p-i-n receivers to encode/decode the information. Trichromatic RGB Light Emitting Diodes (LED)s (RGB-LED) are used together for illumination proposes (headlamps) and individually, each chip, to transmit the driving range distance and data information. An on-off code is used to transmit the data. Free space is the transmission medium. The receivers consist of two stacked amorphous a-H:SiC cells. They combine the simultaneous demultiplexing operation with the photodetection and self-amplification. The proposed coding is based on SiC technology. Multiple Input Multi Output (MIMO) architecture is used. For data transmission, we propose the use of two headlights based on commercially available modulated white RGB-LEDs. For data receiving and decoding we use three a-SiC:H double pin/pin optical processors symmetrically distributed at the vehicle tail Moreover, we present a way to achieve vehicular communication using the parity bits. A representation with a 4 bit original string color message and the transmitted 7 bit string, the encoding and decoding accurate positional information processes and the design of SiC navigation system are discussed and tested. A visible multilateration method estimates the drive distance range by using the decoded information received from several non-collinear transmitters.

Burst-mode optical label processor with ultralow power consumption.

PubMed

Ibrahim, Salah; Nakahara, Tatsushi; Ishikawa, Hiroshi; Takahashi, Ryo

2016-04-04

A novel label processor subsystem for 100-Gbps (25-Gbps × 4λs) burst-mode optical packets is developed, in which a highly energy-efficient method is pursued for extracting and interfacing the ultrafast packet-label to a CMOS-based processor where label recognition takes place. The method involves performing serial-to-parallel conversion for the label bits on a bit-by-bit basis by using an optoelectronic converter that is operated with a set of optical triggers generated in a burst-mode manner upon packet arrival. Here we present three key achievements that enabled a significant reduction in the total power consumption and latency of the whole subsystem; 1) based on a novel operation mechanism for providing amplification with bit-level selectivity, an optical trigger pulse generator, that consumes power for a very short duration upon packet arrival, is proposed and experimentally demonstrated, 2) the energy of optical triggers needed by the optoelectronic serial-to-parallel converter is reduced by utilizing a negative-polarity signal while employing an enhanced conversion scheme entitled the discharge-or-hold scheme, 3) the necessary optical trigger energy is further cut down by half by coupling the triggers through the chip's backside, whereas a novel lens-free packaging method is developed to enable a low-cost alignment process that works with simple visual observation.

Waveguide-type optical circuits for recognition of optical 8QAM-coded label

NASA Astrophysics Data System (ADS)

Surenkhorol, Tumendemberel; Kishikawa, Hiroki; Goto, Nobuo; Gonchigsumlaa, Khishigjargal

2017-10-01

Optical signal processing is expected to be applied in network nodes. In photonic routers, label recognition is one of the important functions. We have studied different kinds of label recognition methods so far for on-off keying, binary phase-shift keying, quadrature phase-shift keying, and 16 quadrature amplitude modulation-coded labels. We propose a method based on waveguide circuits to recognize an optical eight quadrature amplitude modulation (8QAM)-coded label by simple passive optical signal processing. The recognition of the proposed method is theoretically analyzed and numerically simulated by the finite difference beam propagation method. The noise tolerance is discussed, and bit-error rate against optical signal-to-noise ratio is evaluated. The scalability of the proposed method is also discussed theoretically for two-symbol length 8QAM-coded labels.

Video on phone lines: technology and applications

NASA Astrophysics Data System (ADS)

Hsing, T. Russell

1996-03-01

Recent advances in communications signal processing and VLSI technology are fostering tremendous interest in transmitting high-speed digital data over ordinary telephone lines at bit rates substantially above the ISDN Basic Access rate (144 Kbit/s). Two new technologies, high-bit-rate digital subscriber lines and asymmetric digital subscriber lines promise transmission over most of the embedded loop plant at 1.544 Mbit/s and beyond. Stimulated by these research promises and rapid advances on video coding techniques and the standards activity, information networks around the globe are now exploring possible business opportunities of offering quality video services (such as distant learning, telemedicine, and telecommuting etc.) through this high-speed digital transport capability in the copper loop plant. Visual communications for residential customers have become more feasible than ever both technically and economically.

Fronthaul evolution: From CPRI to Ethernet

NASA Astrophysics Data System (ADS)

Gomes, Nathan J.; Chanclou, Philippe; Turnbull, Peter; Magee, Anthony; Jungnickel, Volker

2015-12-01

It is proposed that using Ethernet in the fronthaul, between base station baseband unit (BBU) pools and remote radio heads (RRHs), can bring a number of advantages, from use of lower-cost equipment, shared use of infrastructure with fixed access networks, to obtaining statistical multiplexing and optimised performance through probe-based monitoring and software-defined networking. However, a number of challenges exist: ultra-high-bit-rate requirements from the transport of increased bandwidth radio streams for multiple antennas in future mobile networks, and low latency and jitter to meet delay requirements and the demands of joint processing. A new fronthaul functional division is proposed which can alleviate the most demanding bit-rate requirements by transport of baseband signals instead of sampled radio waveforms, and enable statistical multiplexing gains. Delay and synchronisation issues remain to be solved.

A multi-channel low-power system-on-chip for single-unit recording and narrowband wireless transmission of neural signal.

PubMed

Bonfanti, A; Ceravolo, M; Zambra, G; Gusmeroli, R; Spinelli, A S; Lacaita, A L; Angotzi, G N; Baranauskas, G; Fadiga, L

2010-01-01

This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole system is designed to work with 64 channels demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. A digital data compression, based on the detection of action potentials and storage of correspondent waveforms, allows the use of a 1.25-Mbit/s binary FSK wireless transmission. This moderate bit-rate and a low frequency deviation, Manchester-coded modulation are crucial for exploiting a narrowband wireless link and an efficient embeddable antenna. The chip is realized in a 0.35- εm CMOS process with a power consumption of 105 εW per channel (269 εW per channel with an extended transmission range of 4 m) and an area of 3.1 × 2.7 mm(2). The transmitted signal is captured by a digital TV tuner and demodulated by a wideband phase-locked loop (PLL), and then sent to a PC via an FPGA module. The system has been tested for electrical specifications and its functionality verified in in-vivo neural recording experiments.

Optimal space communications techniques. [using digital and phase locked systems for signal processing

NASA Technical Reports Server (NTRS)

Schilling, D. L.

1974-01-01

Digital multiplication of two waveforms using delta modulation (DM) is discussed. It is shown that while conventional multiplication of two N bit words requires N2 complexity, multiplication using DM requires complexity which increases linearly with N. Bounds on the signal-to-quantization noise ratio (SNR) resulting from this multiplication are determined and compared with the SNR obtained using standard multiplication techniques. The phase locked loop (PLL) system, consisting of a phase detector, voltage controlled oscillator, and a linear loop filter, is discussed in terms of its design and system advantages. Areas requiring further research are identified.

Equalization of nonlinear transmission impairments by maximum-likelihood-sequence estimation in digital coherent receivers.

PubMed

Khairuzzaman, Md; Zhang, Chao; Igarashi, Koji; Katoh, Kazuhiro; Kikuchi, Kazuro

2010-03-01

We describe a successful introduction of maximum-likelihood-sequence estimation (MLSE) into digital coherent receivers together with finite-impulse response (FIR) filters in order to equalize both linear and nonlinear fiber impairments. The MLSE equalizer based on the Viterbi algorithm is implemented in the offline digital signal processing (DSP) core. We transmit 20-Gbit/s quadrature phase-shift keying (QPSK) signals through a 200-km-long standard single-mode fiber. The bit-error rate performance shows that the MLSE equalizer outperforms the conventional adaptive FIR filter, especially when nonlinear impairments are predominant.

Phase locked loop synchronization for direct detection optical PPM communication systems

NASA Technical Reports Server (NTRS)

Chen, C. C.; Gardner, C. S.

1985-01-01

Receiver timing synchronization of an optical pulse position modulation (PPM) communication system can be achieved using a phase locked loop (PLL) if the photodetector output is properly processed. The synchronization performance is shown to improve with increasing signal power and decreasing loop bandwidth. Bit error rate (BER) of the PLL synchronized PPM system is analyzed and compared to that for the perfectly synchronized system. It is shown that the increase in signal power needed to compensate for the imperfect synchronization is small (less than 0.1 dB) for loop bandwidths less than 0.1% of the slot frequency.

Secure chaotic transmission of electrocardiography signals with acousto-optic modulation under profiled beam propagation.

PubMed

Almehmadi, Fares S; Chatterjee, Monish R

2015-01-10

Electrocardiography (ECG) signals are used for both medical purposes and identifying individuals. It is often necessary to encrypt this highly sensitive information before it is transmitted over any channel. A closed-loop acousto-optic hybrid device acting as a chaotic modulator is applied to ECG signals to achieve this encryption. Recently improved modeling of this approach using profiled optical beams has shown it to be very sensitive to key parameters that characterize the encryption and decryption process, exhibiting its potential for secure transmission of analog and digital signals. Here the encryption and decryption is demonstrated for ECG signals, both analog and digital versions, illustrating strong encryption without significant distortion. Performance analysis pertinent to both analog and digital transmission of the ECG waveform is also carried out using output signal-to-noise, signal-to-distortion, and bit-error-rate measures relative to the key parameters and presence of channel noise in the system.

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.

PubMed

Adimulam, Mahesh Kumar; Divya, A; Tejaswi, K; Srinivas, M B

2017-07-01

A low power Programmable Analog Front End (PAFE) for biopotential measurements is presented in this paper. The PAFE circuit processes electrocardiogram (ECG), electromyography (EMG) and electroencephalogram (EEG) signals with higher accuracy. It consists mainly of improved transconductance programmable gain instrumentational amplifier (PGIA), programmable high pass filter (PHPF), and second order low pass filter (SLPF). A 15-bit programmable 5-stage successive approximation analog-to-digital converter (SAR-ADC) is implemented for improving the performance, whose power consumption is reduced due to multiple stages and by OTA/Comparator sharing technique between the stages. The power consumption is further reduced by operating the analog portion of PAFE on 0.5V supply voltage and digital portion on 0.3V supply voltage generated internally through a voltage regulator. The proposed low power PAFE has been fabricated in 180nm standard CMOS process. The performance parameters of PAFE in 15-bit mode are found to be, gain of 31-70 dB, input referred noise of 1.15 μVrms, CMRR of 110 dB, PSRR of 104 dB, and signal-to-noise distortion ratio (SNDR) of 83.5dB. The power consumption of the design is 1.1 μW @ 0.5 V supply voltage and it occupies a core silicon area of 1.2 mm 2 .

Digital PCM bit synchronizer and detector

NASA Astrophysics Data System (ADS)

Moghazy, A. E.; Maral, G.; Blanchard, A.

1980-08-01

A theoretical analysis of a digital self-bit synchronizer and detector is presented and supported by the implementation of an experimental model that utilizes standard TTL logic circuits. This synchronizer is based on the generation of spectral line components by nonlinear filtering of the received bit stream, and extracting the line by a digital phase-locked loop (DPLL). The extracted reference signal instructs a digital matched filter (DMF) data detector. This realization features a short acquisition time and an all-digital structure.

Code division multiple access signaling for modulated reflector technology

DOEpatents

Briles, Scott D [Los Alamos, NM

2012-05-01

A method and apparatus for utilizing code division multiple access in modulated reflectance transmissions comprises the steps of generating a phase-modulated reflectance data bit stream; modifying the modulated reflectance data bit stream; providing the modified modulated reflectance data bit stream to a switch that connects an antenna to an infinite impedance in the event a "+1" is to be sent, or connects the antenna to ground in the event a "0" or a "-1" is to be sent.

Polarization chaos and random bit generation in nonlinear fiber optics induced by a time-delayed counter-propagating feedback loop.

PubMed

Morosi, J; Berti, N; Akrout, A; Picozzi, A; Guasoni, M; Fatome, J

2018-01-22

In this manuscript, we experimentally and numerically investigate the chaotic dynamics of the state-of-polarization in a nonlinear optical fiber due to the cross-interaction between an incident signal and its intense backward replica generated at the fiber-end through an amplified reflective delayed loop. Thanks to the cross-polarization interaction between the two-delayed counter-propagating waves, the output polarization exhibits fast temporal chaotic dynamics, which enable a powerful scrambling process with moving speeds up to 600-krad/s. The performance of this all-optical scrambler was then evaluated on a 10-Gbit/s On/Off Keying telecom signal achieving an error-free transmission. We also describe how these temporal and chaotic polarization fluctuations can be exploited as an all-optical random number generator. To this aim, a billion-bit sequence was experimentally generated and successfully confronted to the dieharder benchmarking statistic tools. Our experimental analysis are supported by numerical simulations based on the resolution of counter-propagating coupled nonlinear propagation equations that confirm the observed behaviors.

Bit-rate transparent DPSK demodulation scheme based on injection locking FP-LD

NASA Astrophysics Data System (ADS)

Feng, Hanlin; Xiao, Shilin; Yi, Lilin; Zhou, Zhao; Yang, Pei; Shi, Jie

2013-05-01

We propose and demonstrate a bit-rate transparent differential phase shift-keying (DPSK) demodulation scheme based on injection locking multiple-quantum-well (MQW) strained InGaAsP FP-LD. By utilizing frequency deviation generated by phase modulation and unstable injection locking state with Fabry-Perot laser diode (FP-LD), DPSK to polarization shift-keying (PolSK) and PolSK to intensity modulation (IM) format conversions are realized. We analyze bit error rate (BER) performance of this demodulation scheme. Experimental results show that different longitude modes, bit rates and seeding power have influences on demodulation performance. We achieve error free DPSK signal demodulation under various bit rates of 10 Gbit/s, 5 Gbit/s, 2.5 Gbit/s and 1.25 Gbit/s with the same demodulation setting.

Minimal-post-processing 320-Gbps true random bit generation using physical white chaos.

PubMed

Wang, Anbang; Wang, Longsheng; Li, Pu; Wang, Yuncai

2017-02-20

Chaotic external-cavity semiconductor laser (ECL) is a promising entropy source for generation of high-speed physical random bits or digital keys. The rate and randomness is unfortunately limited by laser relaxation oscillation and external-cavity resonance, and is usually improved by complicated post processing. Here, we propose using a physical broadband white chaos generated by optical heterodyning of two ECLs as entropy source to construct high-speed random bit generation (RBG) with minimal post processing. The optical heterodyne chaos not only has a white spectrum without signature of relaxation oscillation and external-cavity resonance but also has a symmetric amplitude distribution. Thus, after quantization with a multi-bit analog-digital-convertor (ADC), random bits can be obtained by extracting several least significant bits (LSBs) without any other processing. In experiments, a white chaos with a 3-dB bandwidth of 16.7 GHz is generated. Its entropy rate is estimated as 16 Gbps by single-bit quantization which means a spectrum efficiency of 96%. With quantization using an 8-bit ADC, 320-Gbps physical RBG is achieved by directly extracting 4 LSBs at 80-GHz sampling rate.

Demodulation Algorithms for the Ofdm Signals in the Time- and Frequency-Scattering Channels

NASA Astrophysics Data System (ADS)

Bochkov, G. N.; Gorokhov, K. V.; Kolobkov, A. V.

2016-06-01

We consider a method based on the generalized maximum-likelihood rule for solving the problem of reception of the signals with orthogonal frequency division multiplexing of their harmonic components (OFDM signals) in the time- and frequency-scattering channels. The coherent and incoherent demodulators effectively using the time scattering due to the fast fading of the signal are developed. Using computer simulation, we performed comparative analysis of the proposed algorithms and well-known signal-reception algorithms with equalizers. The proposed symbolby-symbol detector with decision feedback and restriction of the number of searched variants is shown to have the best bit-error-rate performance. It is shown that under conditions of the limited accuracy of estimating the communication-channel parameters, the incoherent OFDMsignal detectors with differential phase-shift keying can ensure a better bit-error-rate performance compared with the coherent OFDM-signal detectors with absolute phase-shift keying.

Performance of correlation receivers in the presence of impulse noise.

NASA Technical Reports Server (NTRS)

Moore, J. D.; Houts, R. C.

1972-01-01

An impulse noise model, which assumes that each noise burst contains a randomly weighted version of a basic waveform, is used to derive the performance equations for a correlation receiver. The expected number of bit errors per noise burst is expressed as a function of the average signal energy, signal-set correlation coefficient, bit time, noise-weighting-factor variance and probability density function, and a time range function which depends on the crosscorrelation of the signal-set basis functions and the noise waveform. Unlike the performance results for additive white Gaussian noise, it is shown that the error performance for impulse noise is affected by the choice of signal-set basis function, and that Orthogonal signaling is not equivalent to On-Off signaling with the same average energy. Furthermore, it is demonstrated that the correlation-receiver error performance can be improved by inserting a properly specified nonlinear device prior to the receiver input.

Realisation and robustness evaluation of a blind spatial domain watermarking technique

NASA Astrophysics Data System (ADS)

Parah, Shabir A.; Sheikh, Javaid A.; Assad, Umer I.; Bhat, Ghulam M.

2017-04-01

A blind digital image watermarking scheme based on spatial domain is presented and investigated in this paper. The watermark has been embedded in intermediate significant bit planes besides the least significant bit plane at the address locations determined by pseudorandom address vector (PAV). The watermark embedding using PAV makes it difficult for an adversary to locate the watermark and hence adds to security of the system. The scheme has been evaluated to ascertain the spatial locations that are robust to various image processing and geometric attacks JPEG compression, additive white Gaussian noise, salt and pepper noise, filtering and rotation. The experimental results obtained, reveal an interesting fact, that, for all the above mentioned attacks, other than rotation, higher the bit plane in which watermark is embedded more robust the system. Further, the perceptual quality of the watermarked images obtained in the proposed system has been compared with some state-of-art watermarking techniques. The proposed technique outperforms the techniques under comparison, even if compared with the worst case peak signal-to-noise ratio obtained in our scheme.

Omega flight-test data reduction sequence. [computer programs for reduction of navigation data

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1974-01-01

Computer programs for Omega data conversion, summary, and preparation for distribution are presented. Program logic and sample data formats are included, along with operational instructions for each program. Flight data (or data collected in flight format in the laboratory) is provided by the Ohio University Omega receiver base in the form of 6-bit binary words representing the phase of an Omega station with respect to the receiver's local clock. All eight Omega stations are measured in each 10-second Omega time frame. In addition, an event-marker bit and a time-slot D synchronizing bit are recorded. Program FDCON is used to remove data from the flight recorder tape and place it on data-processing cards for later use. Program FDSUM provides for computer plotting of selected LOP's, for single-station phase plots, and for printout of basic signal statistics for each Omega channel. Mean phase and standard deviation are printed, along with data from which a phase distribution can be plotted for each Omega station. Program DACOP simply copies the Omega data deck a controlled number of times, for distribution to users.

Experimental Demonstration of Long-Range Underwater Acoustic Communication Using a Vertical Sensor Array

PubMed Central

Zhao, Anbang; Zeng, Caigao; Hui, Juan; Ma, Lin; Bi, Xuejie

2017-01-01

This paper proposes a composite channel virtual time reversal mirror (CCVTRM) for vertical sensor array (VSA) processing and applies it to long-range underwater acoustic (UWA) communication in shallow water. Because of weak signal-to-noise ratio (SNR), it is unable to accurately estimate the channel impulse response of each sensor of the VSA, thus the traditional passive time reversal mirror (PTRM) cannot perform well in long-range UWA communication in shallow water. However, CCVTRM only needs to estimate the composite channel of the VSA to accomplish time reversal mirror (TRM), which can effectively mitigate the inter-symbol interference (ISI) and reduce the bit error rate (BER). In addition, the calculation of CCVTRM is simpler than traditional PTRM. An UWA communication experiment using a VSA of 12 sensors was conducted in the South China Sea. The experiment achieves a very low BER communication at communication rate of 66.7 bit/s over an 80 km range. The results of the sea trial demonstrate that CCVTRM is feasible and can be applied to long-range UWA communication in shallow water. PMID:28653976

Universal sensor interface module (USIM)

NASA Astrophysics Data System (ADS)

King, Don; Torres, A.; Wynn, John

1999-01-01

A universal sensor interface model (USIM) is being developed by the Raytheon-TI Systems Company for use with fields of unattended distributed sensors. In its production configuration, the USIM will be a multichip module consisting of a set of common modules. The common module USIM set consists of (1) a sensor adapter interface (SAI) module, (2) digital signal processor (DSP) and associated memory module, and (3) a RF transceiver model. The multispectral sensor interface is designed around a low-power A/D converted, whose input/output interface consists of: -8 buffered, sampled inputs from various devices including environmental, acoustic seismic and magnetic sensors. The eight sensor inputs are each high-impedance, low- capacitance, differential amplifiers. The inputs are ideally suited for interface with discrete or MEMS sensors, since the differential input will allow direct connection with high-impedance bridge sensors and capacitance voltage sources. Each amplifier is connected to a 22-bit (Delta) (Sigma) A/D converter to enable simultaneous samples. The low power (Delta) (Sigma) converter provides 22-bit resolution at sample frequencies up to 142 hertz (used for magnetic sensors) and 16-bit resolution at frequencies up to 1168 hertz (used for acoustic and seismic sensors). The video interface module is based around the TMS320C5410 DSP. It can provide sensor array addressing, video data input, data calibration and correction. The processor module is based upon a MPC555. It will be used for mode control, synchronization of complex sensors, sensor signal processing, array processing, target classification and tracking. Many functions of the A/D, DSP and transceiver can be powered down by using variable clock speeds under software command or chip power switches. They can be returned to intermediate or full operation by DSP command. Power management may be based on the USIM's internal timer, command from the USIM transceiver, or by sleep mode processing management. The low power detection mode is implemented by monitoring any of the sensor analog outputs at lower sample rates for detection over a software controllable threshold.

Improved P300 speller performance using electrocorticography, spectral features, and natural language processing.

PubMed

Speier, William; Fried, Itzhak; Pouratian, Nader

2013-07-01

The P300 speller is a system designed to restore communication to patients with advanced neuromuscular disorders. This study was designed to explore the potential improvement from using electrocorticography (ECoG) compared to the more traditional usage of electroencephalography (EEG). We tested the P300 speller on two epilepsy patients with temporary subdural electrode arrays over the occipital and temporal lobes respectively. We then performed offline analysis to determine the accuracy and bit rate of the system and integrated spectral features into the classifier and used a natural language processing (NLP) algorithm to further improve the results. The subject with the occipital grid achieved an accuracy of 82.77% and a bit rate of 41.02, which improved to 96.31% and 49.47 respectively using a language model and spectral features. The temporal grid patient achieved an accuracy of 59.03% and a bit rate of 18.26 with an improvement to 75.81% and 27.05 respectively using a language model and spectral features. Spatial analysis of the individual electrodes showed best performance using signals generated and recorded near the occipital pole. Using ECoG and integrating language information and spectral features can improve the bit rate of a P300 speller system. This improvement is sensitive to the electrode placement and likely depends on visually evoked potentials. This study shows that there can be an improvement in BCI performance when using ECoG, but that it is sensitive to the electrode location. Copyright © 2013 International Federation of Clinical Neurophysiology. Published by Elsevier Ireland Ltd. All rights reserved.

Digital audio watermarking using moment-preserving thresholding

NASA Astrophysics Data System (ADS)

Choi, DooSeop; Jung, Hae Kyung; Choi, Hyuk; Kim, Taejeong

2007-09-01

The Moment-Preserving Thresholding technique for digital images has been used in digital image processing for decades, especially in image binarization and image compression. Its main strength lies in that the binary values that the MPT produces as a result, called representative values, are usually unaffected when the signal being thresholded goes through a signal processing operation. The two representative values in MPT together with the threshold value are obtained by solving the system of the preservation equations for the first, second, and third moment. Relying on this robustness of the representative values to various signal processing attacks considered in the watermarking context, this paper proposes a new watermarking scheme for audio signals. The watermark is embedded in the root-sum-square (RSS) of the two representative values of each signal block using the quantization technique. As a result, the RSS values are modified by scaling the signal according to the watermark bit sequence under the constraint of inaudibility relative to the human psycho-acoustic model. We also address and suggest solutions to the problem of synchronization and power scaling attacks. Experimental results show that the proposed scheme maintains high audio quality and robustness to various attacks including MP3 compression, re-sampling, jittering, and, DA/AD conversion.

Channel modeling, signal processing and coding for perpendicular magnetic recording

NASA Astrophysics Data System (ADS)

Wu, Zheng

With the increasing areal density in magnetic recording systems, perpendicular recording has replaced longitudinal recording to overcome the superparamagnetic limit. Studies on perpendicular recording channels including aspects of channel modeling, signal processing and coding techniques are presented in this dissertation. To optimize a high density perpendicular magnetic recording system, one needs to know the tradeoffs between various components of the system including the read/write transducers, the magnetic medium, and the read channel. We extend the work by Chaichanavong on the parameter optimization for systems via design curves. Different signal processing and coding techniques are studied. Information-theoretic tools are utilized to determine the acceptable region for the channel parameters when optimal detection and linear coding techniques are used. Our results show that a considerable gain can be achieved by the optimal detection and coding techniques. The read-write process in perpendicular magnetic recording channels includes a number of nonlinear effects. Nonlinear transition shift (NLTS) is one of them. The signal distortion induced by NLTS can be reduced by write precompensation during data recording. We numerically evaluate the effect of NLTS on the read-back signal and examine the effectiveness of several write precompensation schemes in combating NLTS in a channel characterized by both transition jitter noise and additive white Gaussian electronics noise. We also present an analytical method to estimate the bit-error-rate and use it to help determine the optimal write precompensation values in multi-level precompensation schemes. We propose a mean-adjusted pattern-dependent noise predictive (PDNP) detection algorithm for use on the channel with NLTS. We show that this detector can offer significant improvements in bit-error-rate (BER) compared to conventional Viterbi and PDNP detectors. Moreover, the system performance can be further improved by combining the new detector with a simple write precompensation scheme. Soft-decision decoding for algebraic codes can improve performance for magnetic recording systems. In this dissertation, we propose two soft-decision decoding methods for tensor-product parity codes. We also present a list decoding algorithm for generalized error locating codes.

Progress of the Swedish-Australian research collaboration on uncooled smart IR sensors

NASA Astrophysics Data System (ADS)

Liddiard, Kevin C.; Ringh, Ulf; Jansson, Christer; Reinhold, Olaf

1998-10-01

Progress is reported on the development of uncooled microbolometer IR focal plane detector arrays (IRFPDA) under a research collaboration between the Swedish Defence Research Establishment (FOA), and the Defence Science and Technology Organization (DSTO), Australia. The paper describes current focal plane detector arrays designed by Electro-optic Sensor Design (EOSD) for readout circuits developed by FOA. The readouts are fabricated in 0.8 micrometer CMOS, and have a novel signal conditioning and 16 bit parallel ADC design. The arrays are post-processed at DSTO on wafers supplied by FOA. During the past year array processing has been carried out at a new microengineering facility at DSTO, Salisbury, South Australia. A number of small format 16 X 16 arrays have been delivered to FOA for evaluation, and imaging has been demonstrated with these arrays. A 320 X 240 readout with 320 parallel 16 bit ADCs has been developed and IRFPDAs for this readout have been fabricated and are currently being evaluated.

Performance Bounds on Two Concatenated, Interleaved Codes

NASA Technical Reports Server (NTRS)

Moision, Bruce; Dolinar, Samuel

2010-01-01

A method has been developed of computing bounds on the performance of a code comprised of two linear binary codes generated by two encoders serially concatenated through an interleaver. Originally intended for use in evaluating the performances of some codes proposed for deep-space communication links, the method can also be used in evaluating the performances of short-block-length codes in other applications. The method applies, more specifically, to a communication system in which following processes take place: At the transmitter, the original binary information that one seeks to transmit is first processed by an encoder into an outer code (Co) characterized by, among other things, a pair of numbers (n,k), where n (n > k)is the total number of code bits associated with k information bits and n k bits are used for correcting or at least detecting errors. Next, the outer code is processed through either a block or a convolutional interleaver. In the block interleaver, the words of the outer code are processed in blocks of I words. In the convolutional interleaver, the interleaving operation is performed bit-wise in N rows with delays that are multiples of B bits. The output of the interleaver is processed through a second encoder to obtain an inner code (Ci) characterized by (ni,ki). The output of the inner code is transmitted over an additive-white-Gaussian- noise channel characterized by a symbol signal-to-noise ratio (SNR) Es/No and a bit SNR Eb/No. At the receiver, an inner decoder generates estimates of bits. Depending on whether a block or a convolutional interleaver is used at the transmitter, the sequence of estimated bits is processed through a block or a convolutional de-interleaver, respectively, to obtain estimates of code words. Then the estimates of the code words are processed through an outer decoder, which generates estimates of the original information along with flags indicating which estimates are presumed to be correct and which are found to be erroneous. From the perspective of the present method, the topic of major interest is the performance of the communication system as quantified in the word-error rate and the undetected-error rate as functions of the SNRs and the total latency of the interleaver and inner code. The method is embodied in equations that describe bounds on these functions. Throughout the derivation of the equations that embody the method, it is assumed that the decoder for the outer code corrects any error pattern of t or fewer errors, detects any error pattern of s or fewer errors, may detect some error patterns of more than s errors, and does not correct any patterns of more than t errors. Because a mathematically complete description of the equations that embody the method and of the derivation of the equations would greatly exceed the space available for this article, it must suffice to summarize by reporting that the derivation includes consideration of several complex issues, including relationships between latency and memory requirements for block and convolutional codes, burst error statistics, enumeration of error-event intersections, and effects of different interleaving depths. In a demonstration, the method was used to calculate bounds on the performances of several communication systems, each based on serial concatenation of a (63,56) expurgated Hamming code with a convolutional inner code through a convolutional interleaver. The bounds calculated by use of the method were compared with results of numerical simulations of performances of the systems to show the regions where the bounds are tight (see figure).

Enabling high grayscale resolution displays and accurate response time measurements on conventional computers.

PubMed

Li, Xiangrui; Lu, Zhong-Lin

2012-02-29

Display systems based on conventional computer graphics cards are capable of generating images with 8-bit gray level resolution. However, most experiments in vision research require displays with more than 12 bits of luminance resolution. Several solutions are available. Bit++ (1) and DataPixx (2) use the Digital Visual Interface (DVI) output from graphics cards and high resolution (14 or 16-bit) digital-to-analog converters to drive analog display devices. The VideoSwitcher (3) described here combines analog video signals from the red and blue channels of graphics cards with different weights using a passive resister network (4) and an active circuit to deliver identical video signals to the three channels of color monitors. The method provides an inexpensive way to enable high-resolution monochromatic displays using conventional graphics cards and analog monitors. It can also provide trigger signals that can be used to mark stimulus onsets, making it easy to synchronize visual displays with physiological recordings or response time measurements. Although computer keyboards and mice are frequently used in measuring response times (RT), the accuracy of these measurements is quite low. The RTbox is a specialized hardware and software solution for accurate RT measurements. Connected to the host computer through a USB connection, the driver of the RTbox is compatible with all conventional operating systems. It uses a microprocessor and high-resolution clock to record the identities and timing of button events, which are buffered until the host computer retrieves them. The recorded button events are not affected by potential timing uncertainties or biases associated with data transmission and processing in the host computer. The asynchronous storage greatly simplifies the design of user programs. Several methods are available to synchronize the clocks of the RTbox and the host computer. The RTbox can also receive external triggers and be used to measure RT with respect to external events. Both VideoSwitcher and RTbox are available for users to purchase. The relevant information and many demonstration programs can be found at http://lobes.usc.edu/.

Digital Hardware Architecture Implementation

DTIC Science & Technology

1993-02-15

of micro - MOTOROLA 63.7 50MHZ 64 BIT 2092 N/A processors during quarterly re- INTEL 42 50MHz 64 BIT 1092 N/A views and monthly reports. The 186o XP...27 3.2.1 Signal Processor (SP) Analysis...31 3.2.1.11 MasPar Software Statements ........................................................ 32 3.2.2 Data Processor

Design for minimum energy in interstellar communication

NASA Astrophysics Data System (ADS)

Messerschmitt, David G.

2015-02-01

Microwave digital communication at interstellar distances is the foundation of extraterrestrial civilization (SETI and METI) communication of information-bearing signals. Large distances demand large transmitted power and/or large antennas, while the propagation is transparent over a wide bandwidth. Recognizing a fundamental tradeoff, reduced energy delivered to the receiver at the expense of wide bandwidth (the opposite of terrestrial objectives) is advantageous. Wide bandwidth also results in simpler design and implementation, allowing circumvention of dispersion and scattering arising in the interstellar medium and motion effects and obviating any related processing. The minimum energy delivered to the receiver per bit of information is determined by cosmic microwave background alone. By mapping a single bit onto a carrier burst, the Morse code invented for the telegraph in 1836 comes closer to this minimum energy than approaches used in modern terrestrial radio. Rather than the terrestrial approach of adding phases and amplitudes increases information capacity while minimizing bandwidth, adding multiple time-frequency locations for carrier bursts increases capacity while minimizing energy per information bit. The resulting location code is simple and yet can approach the minimum energy as bandwidth is expanded. It is consistent with easy discovery, since carrier bursts are energetic and straightforward modifications to post-detection pattern recognition can identify burst patterns. Time and frequency coherence constraints leading to simple signal discovery are addressed, and observations of the interstellar medium by transmitter and receiver constrain the burst parameters and limit the search scope.

Method and apparatus for communicating computer data from one point to another over a communications medium

DOEpatents

Arneson, Michael R [Chippewa Falls, WI; Bowman, Terrance L [Sumner, WA; Cornett, Frank N [Chippewa Falls, WI; DeRyckere, John F [Eau Claire, WI; Hillert, Brian T [Chippewa Falls, WI; Jenkins, Philip N [Eau Claire, WI; Ma, Nan [Chippewa Falls, WI; Placek, Joseph M [Chippewa Falls, WI; Ruesch, Rodney [Eau Claire, WI; Thorson, Gregory M [Altoona, WI

2007-07-24

The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.

Détection homodyne pour mémoires holographiques à stockage bit à bit

NASA Astrophysics Data System (ADS)

Maire, G.; Pauliat, G.; Roosen, G.

2006-10-01

Les mémoires holographiques à stockage bit à bit sont une alternative intéressante à l'approche holographique conventionnelle par pages de données du fait de leur architecture optique simplifiée. Nous proposons et validons ici une procédure de lecture adaptée à de telles mémoires et basée sur une détection homodyne de l'amplitude diffractée par les hologrammes. Ceci permet d'augmenter la quantité de signal utile détecté et s'avère donc prometteur pour accroître le taux de transfert de données de ces mémoires.

Bit selection using field drilling data and mathematical investigation

NASA Astrophysics Data System (ADS)

Momeni, M. S.; Ridha, S.; Hosseini, S. J.; Meyghani, B.; Emamian, S. S.

2018-03-01

A drilling process will not be complete without the usage of a drill bit. Therefore, bit selection is considered to be an important task in drilling optimization process. To select a bit is considered as an important issue in planning and designing a well. This is simply because the cost of drilling bit in total cost is quite high. Thus, to perform this task, aback propagation ANN Model is developed. This is done by training the model using several wells and it is done by the usage of drilling bit records from offset wells. In this project, two models are developed by the usage of the ANN. One is to find predicted IADC bit code and one is to find Predicted ROP. Stage 1 was to find the IADC bit code by using all the given filed data. The output is the Targeted IADC bit code. Stage 2 was to find the Predicted ROP values using the gained IADC bit code in Stage 1. Next is Stage 3 where the Predicted ROP value is used back again in the data set to gain Predicted IADC bit code value. The output is the Predicted IADC bit code. Thus, at the end, there are two models that give the Predicted ROP values and Predicted IADC bit code values.

Optimization of an optically implemented on-board FDMA demultiplexer

NASA Technical Reports Server (NTRS)

Fargnoli, J.; Riddle, L.

1991-01-01

Performance of a 30 GHz frequency division multiple access (FDMA) uplink to a processing satellite is modelled for the case where the onboard demultiplexer is implemented optically. Included in the performance model are the effects of adjacent channel interference, intersymbol interference, and spurious signals associated with the optical implementation. Demultiplexer parameters are optimized to provide the minimum bit error probability at a given bandwidth efficiency when filtered QPSK modulation is employed.

Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Editor)

1992-01-01

The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

Large-N in Volcano Settings: Volcanosri

NASA Astrophysics Data System (ADS)

Lees, J. M.; Song, W.; Xing, G.; Vick, S.; Phillips, D.

2014-12-01

We seek a paradigm shift in the approach we take on volcano monitoring where the compromise from high fidelity to large numbers of sensors is used to increase coverage and resolution. Accessibility, danger and the risk of equipment loss requires that we develop systems that are independent and inexpensive. Furthermore, rather than simply record data on hard disk for later analysis we desire a system that will work autonomously, capitalizing on wireless technology and in field network analysis. To this end we are currently producing a low cost seismic array which will incorporate, at the very basic level, seismological tools for first cut analysis of a volcano in crises mode. At the advanced end we expect to perform tomographic inversions in the network in near real time. Geophone (4 Hz) sensors connected to a low cost recording system will be installed on an active volcano where triggering earthquake location and velocity analysis will take place independent of human interaction. Stations are designed to be inexpensive and possibly disposable. In one of the first implementations the seismic nodes consist of an Arduino Due processor board with an attached Seismic Shield. The Arduino Due processor board contains an Atmel SAM3X8E ARM Cortex-M3 CPU. This 32 bit 84 MHz processor can filter and perform coarse seismic event detection on a 1600 sample signal in fewer than 200 milliseconds. The Seismic Shield contains a GPS module, 900 MHz high power mesh network radio, SD card, seismic amplifier, and 24 bit ADC. External sensors can be attached to either this 24-bit ADC or to the internal multichannel 12 bit ADC contained on the Arduino Due processor board. This allows the node to support attachment of multiple sensors. By utilizing a high-speed 32 bit processor complex signal processing tasks can be performed simultaneously on multiple sensors. Using a 10 W solar panel, second system being developed can run autonomously and collect data on 3 channels at 100Hz for 6 months with the installed 16Gb SD card. Initial designs and test results will be presented and discussed.

Experimental validation of wireless communication with chaos.

PubMed

Ren, Hai-Peng; Bai, Chao; Liu, Jian; Baptista, Murilo S; Grebogi, Celso

2016-08-01

The constraints of a wireless physical media, such as multi-path propagation and complex ambient noises, prevent information from being communicated at low bit error rate. Surprisingly, it has only recently been shown that, from a theoretical perspective, chaotic signals are optimal for communication. It maximises the receiver signal-to-noise performance, consequently minimizing the bit error rate. This work demonstrates numerically and experimentally that chaotic systems can in fact be used to create a reliable and efficient wireless communication system. Toward this goal, we propose an impulsive control method to generate chaotic wave signals that encode arbitrary binary information signals and an integration logic together with the match filter capable of decreasing the noise effect over a wireless channel. The experimental validation is conducted by inputting the signals generated by an electronic transmitting circuit to an electronic circuit that emulates a wireless channel, where the signals travel along three different paths. The output signal is decoded by an electronic receiver, after passing through a match filter.

Experimental validation of wireless communication with chaos

NASA Astrophysics Data System (ADS)

Ren, Hai-Peng; Bai, Chao; Liu, Jian; Baptista, Murilo S.; Grebogi, Celso

2016-08-01

The constraints of a wireless physical media, such as multi-path propagation and complex ambient noises, prevent information from being communicated at low bit error rate. Surprisingly, it has only recently been shown that, from a theoretical perspective, chaotic signals are optimal for communication. It maximises the receiver signal-to-noise performance, consequently minimizing the bit error rate. This work demonstrates numerically and experimentally that chaotic systems can in fact be used to create a reliable and efficient wireless communication system. Toward this goal, we propose an impulsive control method to generate chaotic wave signals that encode arbitrary binary information signals and an integration logic together with the match filter capable of decreasing the noise effect over a wireless channel. The experimental validation is conducted by inputting the signals generated by an electronic transmitting circuit to an electronic circuit that emulates a wireless channel, where the signals travel along three different paths. The output signal is decoded by an electronic receiver, after passing through a match filter.

Experimental validation of wireless communication with chaos

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ren, Hai-Peng; Bai, Chao; Liu, Jian

The constraints of a wireless physical media, such as multi-path propagation and complex ambient noises, prevent information from being communicated at low bit error rate. Surprisingly, it has only recently been shown that, from a theoretical perspective, chaotic signals are optimal for communication. It maximises the receiver signal-to-noise performance, consequently minimizing the bit error rate. This work demonstrates numerically and experimentally that chaotic systems can in fact be used to create a reliable and efficient wireless communication system. Toward this goal, we propose an impulsive control method to generate chaotic wave signals that encode arbitrary binary information signals and anmore » integration logic together with the match filter capable of decreasing the noise effect over a wireless channel. The experimental validation is conducted by inputting the signals generated by an electronic transmitting circuit to an electronic circuit that emulates a wireless channel, where the signals travel along three different paths. The output signal is decoded by an electronic receiver, after passing through a match filter.« less

A software reconfigurable optical multiband UWB system utilizing a bit-loading combined with adaptive LDPC code rate scheme

NASA Astrophysics Data System (ADS)

He, Jing; Dai, Min; Chen, Qinghui; Deng, Rui; Xiang, Changqing; Chen, Lin

2017-07-01

In this paper, an effective bit-loading combined with adaptive LDPC code rate algorithm is proposed and investigated in software reconfigurable multiband UWB over fiber system. To compensate the power fading and chromatic dispersion for the high frequency of multiband OFDM UWB signal transmission over standard single mode fiber (SSMF), a Mach-Zehnder modulator (MZM) with negative chirp parameter is utilized. In addition, the negative power penalty of -1 dB for 128 QAM multiband OFDM UWB signal are measured at the hard-decision forward error correction (HD-FEC) limitation of 3.8 × 10-3 after 50 km SSMF transmission. The experimental results show that, compared to the fixed coding scheme with the code rate of 75%, the signal-to-noise (SNR) is improved by 2.79 dB for 128 QAM multiband OFDM UWB system after 100 km SSMF transmission using ALCR algorithm. Moreover, by employing bit-loading combined with ALCR algorithm, the bit error rate (BER) performance of system can be further promoted effectively. The simulation results present that, at the HD-FEC limitation, the value of Q factor is improved by 3.93 dB at the SNR of 19.5 dB over 100 km SSMF transmission, compared to the fixed modulation with uncoded scheme at the same spectrum efficiency (SE).

Low latency counter event indication

DOEpatents

Gara, Alan G [Mount Kisco, NY; Salapura, Valentina [Chappaqua, NY

2008-09-16

A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

Low latency counter event indication

DOEpatents

Gara, Alan G.; Salapura, Valentina

2010-08-24

A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

Multiple speed expandable bit synchronizer

NASA Technical Reports Server (NTRS)

Bundinger, J. M.

1979-01-01

A multiple speed bit synchronizer was designed for installation in an inertial navigation system data decoder to extract non-return-to-zero level data and clock signal from biphase level data. The circuit automatically senses one of four pre-determined biphase data rates and synchronizes the proper clock rate to the data. Through a simple expansion of the basic design, synchronization of more than four binarily related data rates can be accomplished. The design provides an easily adaptable, low cost, low power alternative to external bit synchronizers with additional savings in size and weight.

Multi-aperture digital coherent combining for free-space optical communication receivers.

PubMed

Geisler, David J; Yarnall, Timothy M; Stevens, Mark L; Schieler, Curt M; Robinson, Bryan S; Hamilton, Scott A

2016-06-13

Space-to-ground optical communication systems can benefit from reducing the size, weight, and power profiles of space terminals. One way of reducing the required power-aperture product on a space platform is to implement effective, but costly, single-aperture ground terminals with large collection areas. In contrast, we present a ground terminal receiver architecture in which many small less-expensive apertures are efficiently combined to create a large effective aperture while maintaining excellent receiver sensitivity. This is accomplished via coherent detection behind each aperture followed by digitization. The digitized signals are then combined in a digital signal processing chain. Experimental results demonstrate lossless coherent combining of four lasercom signals, at power levels below 0.1 photons/bit/aperture.

Pulse Shaped Constant Envelope 8-PSK Modulation Study

NASA Technical Reports Server (NTRS)

Tao, Jianping; Horan, Sheila

1997-01-01

This report provides simulation results for constant envelope pulse shaped 8 Level Phase Shift Keying (8 PSK) modulation for end to end system performance. In order to increase bandwidth utilization, pulse shaping is applied to signals before they are modulated. This report provides simulation results of power spectra and measurement of bit errors produced by pulse shaping in a non-linear channel with Additive White Gaussian Noise (AWGN). The pulse shaping filters can placed before (Type B) or after (Type A) signals are modulated. Three kinds of baseband filters, 5th order Butterworth, 3rd order Bessel and Square-Root Raised Cosine with different BTs or roll off factors, are utilized in the simulations. The simulations were performed on a Signal Processing Worksystem (SPW).

All-optical wavelength conversion for mode division multiplexed superchannels.

PubMed

Gong, Jiaxin; Xu, Jing; Luo, Ming; Li, Xiang; Qiu, Ying; Yang, Qi; Zhang, Xinliang; Yu, Shaohua

2016-04-18

We report in this work the first all-optical wavelength conversion (AOWC) of a mode division multiplexed (MDM) superchannel consisting of 2N modes by dividing the superchannel into N single-mode (SM) tributaries, wavelength converting N SM signals using well developed SM-AOWC techniques, and finally combining the N SM tributaries back to an MDM superchannel at the converted wavelength, inspired by the idea of using SM filtering techniques to filter multimode signals in astronomy. The conversions between multimode and SM are realized by 3D laser-writing photonic lanterns and SM-AOWCs are realized based on polarization insensitive four wave mixing (FWM) configuration in N semiconductor optical amplifiers (SOAs). As a proof of concept demonstration, the conversion of a 6-mode MDM superchannel with each mode modulated with orthogonal frequency division multiplexed (OFDM) quadrature phase-shift keying (QPSK)/16 quadrature amplitude modulation (QAM) signals is demonstrated in this work, indicating that the scheme is transparent to data format, polarization and compatible with multi-carrier signals. Data integrity of the converted superchannel has been verified by using coherent detection and digital signal processing (DSP). Bit error rates (BERs) below the forward error correction (FEC) hard limit (3.8 × 10^-3) have been obtained for QPSK modulation at a net bitrate of 104.2 Gbit/s and BERs below the soft decision FEC threshold (1.98 × 10^-2) have been achieved for 16-QAM format, giving a total aggregate bit rate of 185.8 Gbit/s when taking 20% coding overhead into account. Add and drop functionalities that usually come along with wavelength conversion in flexible network nodes have also been demonstrated. The working conditions of the SOAs, especially the pump and signal power levels, are critical for the quality of the converted signal and have been thoroughly discussed. The impact of imbalanced FWM conversion efficiency among different SM tributaries has also been analyzed. This work illustrates a promising way to perform all-optical signal processing for MDM superchannels.

A bandwidth efficient coding scheme for the Hubble Space Telescope

NASA Technical Reports Server (NTRS)

Pietrobon, Steven S.; Costello, Daniel J., Jr.

1991-01-01

As a demonstration of the performance capabilities of trellis codes using multidimensional signal sets, a Viterbi decoder was designed. The choice of code was based on two factors. The first factor was its application as a possible replacement for the coding scheme currently used on the Hubble Space Telescope (HST). The HST at present uses the rate 1/3 nu = 6 (with 2 (exp nu) = 64 states) convolutional code with Binary Phase Shift Keying (BPSK) modulation. With the modulator restricted to a 3 Msym/s, this implies a data rate of only 1 Mbit/s, since the bandwidth efficiency K = 1/3 bit/sym. This is a very bandwidth inefficient scheme, although the system has the advantage of simplicity and large coding gain. The basic requirement from NASA was for a scheme that has as large a K as possible. Since a satellite channel was being used, 8PSK modulation was selected. This allows a K of between 2 and 3 bit/sym. The next influencing factor was INTELSAT's intention of transmitting the SONET 155.52 Mbit/s standard data rate over the 72 MHz transponders on its satellites. This requires a bandwidth efficiency of around 2.5 bit/sym. A Reed-Solomon block code is used as an outer code to give very low bit error rates (BER). A 16 state rate 5/6, 2.5 bit/sym, 4D-8PSK trellis code was selected. This code has reasonable complexity and has a coding gain of 4.8 dB compared to uncoded 8PSK (2). This trellis code also has the advantage that it is 45 deg rotationally invariant. This means that the decoder needs only to synchronize to one of the two naturally mapped 8PSK signals in the signal set.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

PubMed

Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

2015-08-01

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

Experimental realization of a CMOS-compatible optical directed priority encoder using cascaded micro-ring resonators

NASA Astrophysics Data System (ADS)

Xiao, Huifu; Li, Dezhao; Liu, Zilong; Han, Xu; Chen, Wenping; Zhao, Ting; Tian, Yonghui; Yang, Jianhong

2018-03-01

In this paper, we propose and experimentally demonstrate an integrated optical device that can implement the logical function of priority encoding from a 4-bit electrical signal to a 2-bit optical signal. For the proof of concept, the thermo-optic modulation scheme is adopted to tune each micro-ring resonator (MRR). A monochromatic light with the working wavelength is coupled into the input port of the device through a lensed fiber, and the four input electrical logic signals regarded as pending encode signals are applied to the micro-heaters above four MRRs to control the working states of the optical switches. The encoding results are directed to the output ports in the form of light. At last, the logical function of priority encoding with an operation speed of 10 Kbps is demonstrated successfully.

Experimental investigation of polarization insensitivity and cascadability with semiconductor optical amplifier-based differential phase-shift keyed wavelength converter

NASA Astrophysics Data System (ADS)

Mao, Yaya; Wu, Chongqing; Liu, Bo; Ullah, Rahat; Tian, Feng

2017-12-01

We experimentally investigate the polarization insensitivity and cascadability of an all-optical wavelength converter for differential phase-shift keyed (DPSK) signals for the first time. The proposed wavelength converter is composed of a one-bit delay interferometer demodulation stage followed by a single semiconductor optical amplifier. The impact of input DPSK signal polarization fluctuation on receiver sensitivity for the converted signal is carried out. It is found that this scheme is almost insensitive to the state of polarization of the input DPSK signal. Furthermore, the cascadability of the converter is demonstrated in a two-path recirculating loop. Error-free transmission is achieved with 20 stage cascaded wavelength conversions over 2800 km, where the power penalty is <3.4 dB at bit error rate of 10-9.

High-resolution LCOS microdisplay with sub-kHz frame rate for high performance, high precision 3D sensor

NASA Astrophysics Data System (ADS)

Lazarev, Grigory; Bonifer, Stefanie; Engel, Philip; Höhne, Daniel; Notni, Gunther

2017-06-01

We report about the implementation of the liquid crystal on silicon (LCOS) microdisplay with 1920 by 1080 resolution and 720 Hz frame rate. The driving solution is FPGA-based. The input signal is converted from the ultrahigh-resolution HDMI 2.0 signal into HD frames, which follow with the specified 720 Hz frame rate. Alternatively the signal is generated directly on the FPGA with built-in pattern generator. The display is showing switching times below 1.5 ms for the selected working temperature. The bit depth of the addressed image achieves 8 bit within each frame. The microdisplay is used in the fringe projection-based 3D sensing system, implemented by Fraunhofer IOF.

Low-cost TDRSS communications for NASA's long duration balloon project

NASA Technical Reports Server (NTRS)

Israel, David J.

1993-01-01

A new transponder and RF ground support equipment for the NASA Tracking and Data Relay Satellite System (TDRSS) intended to support long duration scientific balloon flights in Antarctica are described. The new balloon class transponder features a highly integrated spread spectrum receiver design based on programmable charge coupled device (CCD) correlators and digital signal processing chips. The correlator chip is a Lincoln Labs 4ABC with four CCD channels. The balloon transponder is capable of reporting an estimate of its input bit error rate using digital signal processing. The TDRSS user RF test set is based on a set of RF ground support equipment capable of providing both the RF communications and direct control and monitoring necessary for transponder testing and a two-way RF link for preflight testing.

An alternative design for a sparse distributed memory

NASA Technical Reports Server (NTRS)

Jaeckel, Louis A.

1989-01-01

A new design for a Sparse Distributed Memory, called the selected-coordinate design, is described. As in the original design, there are a large number of memory locations, each of which may be activated by many different addresses (binary vectors) in a very large address space. Each memory location is defined by specifying ten selected coordinates (bit positions in the address vectors) and a set of corresponding assigned values, consisting of one bit for each selected coordinate. A memory location is activated by an address if, for all ten of the locations's selected coordinates, the corresponding bits in the address vector match the respective assigned value bits, regardless of the other bits in the address vector. Some comparative memory capacity and signal-to-noise ratio estimates for the both the new and original designs are given. A few possible hardware embodiments of the new design are described.

Energy-signal quality trade-offs in a WiMAX mobile station with a booster amplifier

NASA Astrophysics Data System (ADS)

Suherman; Mubarakah, N.; Wiranata, O.; Kasim, S. T.

2018-02-01

Worldwide Interoperability for Microwave Access (WiMAX) is a broadband wireless access technology that is able to provide high bit rate mobile internet services. Battery endurance remains a problem in current mobile communication. On the other hand, signal quality determines the successful run of the mobile applications. Energy consumption optimization cannot sacrifice the signal level required by the application to run smoothly. On the contrary, the application should consider battery life time. This paper examines the tradeoffs between energy and signal quality in WiMAX subscriber station by adjusting signal level using a booster amplifier. Simulation evaluations show that an increment of 0.00000104% energy consumption on using amplifier adaptively produces 16.411% signal to noise ratio (SNR) increment and 10.7% bit error rate (BER) decrement. By keeping the amplifier turned on, energy consumption increases up to 0.00000136%, causing the SNR rises to 17.2638% and BER drops to 11.13%. The evaluated application is video streaming, other application may behave differently.

Characterization of impulse noise and analysis of its effect upon correlation receivers

NASA Technical Reports Server (NTRS)

Houts, R. C.; Moore, J. D.

1971-01-01

A noise model is formulated to describe the impulse noise in many digital systems. A simplified model, which assumes that each noise burst contains a randomly weighted version of the same basic waveform, is used to derive the performance equations for a correlation receiver. The expected number of bit errors per noise burst is expressed as a function of the average signal energy, signal-set correlation coefficient, bit time, noise-weighting-factor variance and probability density function, and a time range function which depends on the crosscorrelation of the signal-set basis functions and the noise waveform. A procedure is established for extending the results for the simplified noise model to the general model. Unlike the performance results for Gaussian noise, it is shown that for impulse noise the error performance is affected by the choice of signal-set basis functions and that Orthogonal signaling is not equivalent to On-Off signaling with the same average energy.

White balance tester with color sensor for industrial applications

NASA Astrophysics Data System (ADS)

Chen, Jiasheng; Zhu, XiaoSong

1996-12-01

The white balance tester is an instrument that adjusts the white balance for color TVs, monitors, and PC displays. We have designed a new white balance tester for use directly at the production line. It picks up the R (Red), G (Green), and B (Blue) signals for the screen using color sensors, compares the signals with the data previously stored in the internal memory, displays their differences with LED bars in the compare mode or displays x y Y, u v Y, JND (just noticeable difference) as well as correlated color temperature in the numerical mode. A built-in TV signal generator sets the luminance of the adjusting screen to the brightness of the reference white screen automatically. A 16-bit single chip microcomputer processes the measured values and controls the output levels of the TV signal generator.

Signal Processing Equipment and Techniques for Use in Measuring Ocean Acoustic Multipath Structures

DTIC Science & Technology

1983-12-01

Demodulator 3.4 Digital Demodulator 3.4.1 Number of Bits in the Input A/D Converter Quantization Effects The Demodulator Output Filter Effects of... power caused by ignoring cross spectral term a) First order Butterworth filter b) Second order Butterworth filter 48 3.4 Ordering of e...spectrum 59 3.7 Multiplying D/A Converter input and output spectra a) Input b) Output 60 3.8 Demodulator output spectrum prior to filtering 63

Mathematical modeling of PDC bit drilling process based on a single-cutter mechanics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojtanowicz, A.K.; Kuru, E.

1993-12-01

An analytical development of a new mechanistic drilling model for polycrystalline diamond compact (PDC) bits is presented. The derivation accounts for static balance of forces acting on a single PDC cutter and is based on assumed similarity between bit and cutter. The model is fully explicit with physical meanings given to all constants and functions. Three equations constitute the mathematical model: torque, drilling rate, and bit life. The equations comprise cutter`s geometry, rock properties drilling parameters, and four empirical constants. The constants are used to match the model to a PDC drilling process. Also presented are qualitative and predictive verificationsmore » of the model. Qualitative verification shows that the model`s response to drilling process variables is similar to the behavior of full-size PDC bits. However, accuracy of the model`s predictions of PDC bit performance is limited primarily by imprecision of bit-dull evaluation. The verification study is based upon the reported laboratory drilling and field drilling tests as well as field data collected by the authors.« less

Development of a compact and cost effective multi-input digital signal processing system

NASA Astrophysics Data System (ADS)

Darvish-Molla, Sahar; Chin, Kenrick; Prestwich, William V.; Byun, Soo Hyun

2018-01-01

A prototype digital signal processing system (DSP) was developed using a microcontroller interfaced with a 12-bit sampling ADC, which offers a considerably inexpensive solution for processing multiple detectors with high throughput. After digitization of the incoming pulses, in order to maximize the output counting rate, a simple algorithm was employed for pulse height analysis. Moreover, an algorithm aiming at the real-time pulse pile-up deconvolution was implemented. The system was tested using a NaI(Tl) detector in comparison with a traditional analogue and commercial digital systems for a variety of count rates. The performance of the prototype system was consistently superior to the analogue and the commercial digital systems up to the input count rate of 61 kcps while was slightly inferior to the commercial digital system but still superior to the analogue system in the higher input rates. Considering overall cost, size and flexibility, this custom made multi-input digital signal processing system (MMI-DSP) was the best reliable choice for the purpose of the 2D microdosimetric data collection, or for any measurement in which simultaneous multi-data collection is required.

Seismic While Drilling Case Study in Shengli Oilfield, Eastern China

NASA Astrophysics Data System (ADS)

Wang, L.; Liu, H.; Tong, S.; Zou, Z.

2015-12-01

Seismic while drilling (SWD) is a promising borehole seismic technique with reduction of drilling risk, cost savings and increased efficiency. To evaluate the technical and economic benefits of this new technique, we carried out SWD survey at well G130 in Shengli Oilfield of Eastern China. Well G130 is an evaluation well, located in Dongying depression at depth more than 3500m. We used an array of portable seismometers to record the surface SWD-data, during the whole drilling progress. The pilot signal was being recorded continuously, by an accelerometer mounted on the top of the drill string. There were also two seismometers buried in the drill yard, one near diesel engine and another near derrick. All the data was being recorded continuously. According to mud logging data, we have processed and analyzed all the data. It demonstrates the drill yard noise is the primary noise among the whole surface wavefield and its dominant frequency is about 20Hz. Crosscorrelation of surface signal with the pilot signal shows its SNR is severely low and there is no any obvious event of drill-bit signals. Fortunately, the autocorrelation of the pilot signal shows clear BHA multiple and drill string multiple. The period of drill string multiple can be used for establishing the reference time (so-called zero time). We identified and removed different noises from the surface SWD-data, taking advantages of wavefield analysis. The drill-bit signal was retrieved from surface SWD-data, using seismic interferometry. And a reverse vertical seismic profile (RVSP) data set for the continuous drilling depth was established. The subsurface images derived from these data compare well with the corresponding images of 3D surface seismic survey cross the well.

A rigorous analysis of digital pre-emphasis and DAC resolution for interleaved DAC Nyquist-WDM signal generation in high-speed coherent optical transmission systems

NASA Astrophysics Data System (ADS)

Weng, Yi; Wang, Junyi; He, Xuan; Pan, Zhongqi

2018-02-01

The Nyquist spectral shaping techniques facilitate a promising solution to enhance spectral efficiency (SE) and further reduce the cost-per-bit in high-speed wavelength-division multiplexing (WDM) transmission systems. Hypothetically, any Nyquist WDM signals with arbitrary shapes can be generated by the use of the digital signal processing (DSP) based electrical filters (E-filter). Nonetheless, in actual 100G/ 200G coherent systems, the performance as well as DSP complexity are increasingly restricted by cost and power consumption. Henceforward it is indispensable to optimize DSP to accomplish the preferred performance at the least complexity. In this paper, we systematically investigated the minimum requirements and challenges of Nyquist WDM signal generation, particularly for higher-order modulation formats, including 16 quadrature amplitude modulation (QAM) or 64QAM. A variety of interrelated parameters, such as channel spacing and roll-off factor, have been evaluated to optimize the requirements of the digital-to-analog converter (DAC) resolution and transmitter E-filter bandwidth. The impact of spectral pre-emphasis has been predominantly enhanced via the proposed interleaved DAC architecture by at least 4%, and hence reducing the required optical signal to noise ratio (OSNR) at a bit error rate (BER) of 10-3 by over 0.45 dB at a channel spacing of 1.05 symbol rate and an optimized roll-off factor of 0.1. Furthermore, the requirements of sampling rate for different types of super-Gaussian E-filters are discussed for 64QAM Nyquist WDM transmission systems. Finally, the impact of the non-50% duty cycle error between sub-DACs upon the quality of the generated signals for the interleaved DAC structure has been analyzed.

Improved convolutional coding

NASA Technical Reports Server (NTRS)

Doland, G. D.

1970-01-01

Convolutional coding, used to upgrade digital data transmission under adverse signal conditions, has been improved by a method which ensures data transitions, permitting bit synchronizer operation at lower signal levels. Method also increases decoding ability by removing ambiguous condition.

Towards High Density 3-D Memory in Diamond

NASA Astrophysics Data System (ADS)

Henshaw, Jacob; Dhomkar, Siddharth; Meriles, Carlos; Jayakumar, Harishankar

The nitrogen-vacancy (NV) center in diamond is presently the focus of widespread attention for applications ranging from quantum information processing to nanoscale metrology. Of great utility is the ability to optically initialize the NV charge state, which has an immediate impact on the center's light emission properties. Here, we use two-color microscopy in NV-rich, type-1b diamond to demonstrate fluorescence-encoded long-term storage of classical information. As a proof of principle, we write, reset, and rewrite various patterns with 2-D binary bit density comparable to present DVD-ROM technology. The strong fluorescence signal originating from the diffraction-limited bit volume allows us to transition from binary to multi-valued encoding, which translates into a significant storage capacity boost. Finally, we show that our technique preserves information written on different planes of the diamond crystal and thus serves as a platform for three-dimensional storage. Substantial enhancement in the bit density could be achieved with the aid of super resolution microscopy techniques already employed to discriminate between NVs with sub-diffraction, nanometer accuracy, a regime where the storage capacity could exceed 1017 bytes/cm3 We acknowledge support from the National Science Foundation through Grant NSF-1314205.

Classical-processing and quantum-processing signal separation methods for qubit uncoupling

NASA Astrophysics Data System (ADS)

Deville, Yannick; Deville, Alain

2012-12-01

The Blind Source Separation problem consists in estimating a set of unknown source signals from their measured combinations. It was only investigated in a non-quantum framework up to now. We propose its first quantum extensions. We thus introduce the Quantum Source Separation field, investigating both its blind and non-blind configurations. More precisely, we show how to retrieve individual quantum bits (qubits) only from the global state resulting from their undesired coupling. We consider cylindrical-symmetry Heisenberg coupling, which e.g. occurs when two electron spins interact through exchange. We first propose several qubit uncoupling methods which typically measure repeatedly the coupled quantum states resulting from individual qubits preparations, and which then statistically process the classical data provided by these measurements. Numerical tests prove the effectiveness of these methods. We then derive a combination of quantum gates for performing qubit uncoupling, thus avoiding repeated qubit preparations and irreversible measurements.

Low frequency noise elimination technique for 24-bit Σ-Δ data acquisition systems.

PubMed

Qu, Shao-Bo; Robert, Olivier; Lognonné, Philippe; Zhou, Ze-Bing; Yang, Shan-Qing

2015-03-01

Low frequency 1/f noise is one of the key limiting factors of high precision measurement instruments. In this paper, digital correlated double sampling is implemented to reduce the offset and low frequency 1/f noise of a data acquisition system with 24-bit sigma delta (Σ-Δ) analog to digital converter (ADC). The input voltage is modulated by cross-coupled switches, which are synchronized to the sampling clock, and converted into digital signal by ADC. By using a proper switch frequency, the unwanted parasitic signal frequencies generated by the switches are avoided. The noise elimination processing is made through the principle of digital correlated double sampling, which is equivalent to a time shifted subtraction for the sampled voltage. The low frequency 1/f noise spectrum density of the data acquisition system is reduced to be flat down to the measurement frequency lower limit, which is about 0.0001 Hz in this paper. The noise spectrum density is eliminated by more than 60 dB at 0.0001 Hz, with a residual noise floor of (9 ± 2) nV/Hz(1/2) which is limited by the intrinsic white noise floor of the ADC above its corner frequency.

KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

NASA Astrophysics Data System (ADS)

Briggl, K.; Dorn, M.; Hagdorn, R.; Harion, T.; Schultz-Coulon, H. C.; Shen, W.

2014-02-01

KLauS is an ASIC produced in the AMS 0.35 μm SiGe process to read out the charge signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with sub-nanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL test beam program.

An inexpensive digital tape recorder suitable for neurophysiological signals.

PubMed

Lamb, T D

1985-10-01

Modifications are described which convert an inexpensive 'Digital Audio Processor' (Sony PCM-701ES), together with a video cassette recorder, into a high performance digital tape recorder, with two analog channels of 16 bit resolution and DC-20 kHz bandwidth. A further modification is described which optionally provides four additional 1-bit digital channels by sacrificing the least significant four bits of one analog channel. If required two additional high quality analog channels may be obtained by use of one of the new video cassette recorders (such as the Sony SL-HF100) which incorporate a pair of FM tracks.

Phase-modulated radio over fiber multimode links.

PubMed

Gasulla, Ivana; Capmany, José

2012-05-21

We present the first experimental demonstration of a phase-modulated MMF link implementing high-frequency digital transmission in a cost-effective solution based on direct detection. Successful subcarrier transmission of QPSK, 16-QAM and 64-QAM data channels for bit rates up to 120 Mb/s through a 5 km MMF link is achieved over the microwave region comprised between 6 and 20 GHz. The overall capacity of the proposed approach can be further increased by properly accommodating more passband channels in the operative frequency range determined by the phase-to-intensity conversion process provided by the dispersive nature of the optical fiber. In this sense, our results show the possibility of achieving an aggregate bit rate per length product of 144 Gb/s · km and confirm, in consequence, the possibility of broadband phase-modulated radio over fiber transmission through MMF links suitable for multichannel SCM signal distribution.

Josephson 4 K-bit cache memory design for a prototype signal processor. I - General overview

NASA Astrophysics Data System (ADS)

Henkels, W. H.; Geppert, L. M.; Kadlec, J.; Epperlein, P. W.; Beha, H.

1985-09-01

In the early stages of thg Josephson computer project conducted at an American computer company, it was recognized that a very fast cache memory was needed to complement Josephson logic. A subnanosecond access time memory was implemented experimentally on the basis of a 2.5-micron Pb-alloy technology. It was then decided to switch over to a Nb-base-electrode technology with the objective to alleviate problems with the long-term reliability and aging of Pb-based junctions. The present paper provides a general overview of the status of a 4 x 1 K-bit Josephson cache design employing a 2.5-micron Nb-edge-junction technology. Attention is given to the fabrication process and its implications, aspects of circuit design methodology, an overview of system environment and chip components, design changes and status, and various difficulties and uncertainties.

Demonstration of an optical directed half-subtracter using integrated silicon photonic circuits.

PubMed

Liu, Zilong; Zhao, Yongpeng; Xiao, Huifu; Deng, Lin; Meng, Yinghao; Guo, Xiaonan; Liu, Guipeng; Tian, Yonghui; Yang, Jianhong

2018-04-01

An integrated silicon photonic circuit consisting of two silicon microring resonators (MRRs) is proposed and experimentally demonstrated for the purpose of half-subtraction operation. The thermo-optic modulation scheme is employed to modulate the MRRs due to its relatively simple fabrication process. The high and low levels of the electrical pulse signal are utilized to define logic 1 and 0 in the electrical domain, respectively, and the high and low levels of the optical power represent logic 1 and 0 in the optical domain, respectively. Two electrical pulse sequences regarded as the operands are applied to the corresponding micro-heaters fabricated on the top of the MRRs to achieve their dynamic modulations. The final operation results of bit-wise borrow and difference are obtained at their corresponding output ports in the form of light. At last, the subtraction operation of two bits with the operation speed of 10 kbps is demonstrated successfully.

A novel speech watermarking algorithm by line spectrum pair modification

NASA Astrophysics Data System (ADS)

Zhang, Qian; Yang, Senbin; Chen, Guang; Zhou, Jun

2011-10-01

To explore digital watermarking specifically suitable for the speech domain, this paper experimentally investigates the properties of line spectrum pair (LSP) parameters firstly. The results show that the differences between contiguous LSPs are robust against common signal processing operations and small modifications of LSPs are imperceptible to the human auditory system (HAS). According to these conclusions, three contiguous LSPs of a speech frame are selected to embed a watermark bit. The middle LSP is slightly altered to modify the differences of these LSPs when embedding watermark. Correspondingly, the watermark is extracted by comparing these differences. The proposed algorithm's transparency is adjustable to meet the needs of different applications. The algorithm has good robustness against additive noise, quantization, amplitude scale and MP3 compression attacks, for the bit error rate (BER) is less than 5%. In addition, the algorithm allows a relatively low capacity, which approximates to 50 bps.

Experimental demonstration of multiuser communication in deep water using time reversal.

PubMed

Shimura, T; Ochi, H; Song, H C

2013-10-01

Multiuser communication is demonstrated using experimental data (450-550 Hz) collected in deep water, south of Japan. The multiple users are spatially distributed either in depth or range while a 114-m long, 20-element vertical array (i.e., base station) is deployed to around the sound channel axis (~1000 m). First, signals received separately from ranges of 150 km and 180 km at various depths are combined asynchronously to generate multiuser communication sequences for subsequent processing, achieving an aggregate data rate of 300 bits/s for up to three users. Adaptive time reversal is employed to separate collided packets at the base station, followed by a single channel decision feedback equalizer. Then it is demonstrated that two users separated by 3 km in range at ~1000 m depth can transmit information simultaneously to the base station at ~500 km range with an aggregate data rate of 200 bits/s.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

NASA Astrophysics Data System (ADS)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

Closed-loop motor control using high-speed fiber optics

NASA Technical Reports Server (NTRS)

Dawson, Reginald (Inventor); Rodriquiz, Dagobert (Inventor)

1991-01-01

A closed-loop control system for controlling the operation of one or more servo motors or other controllable devices is described. The system employs a fiber optics link immune to electromagnetic interference, for transmission of control signals from a controller or controllers at a remote station to the power electronics located in proximity to the motors or other devices at the local station. At the remote station the electrical control signals are time-multiplexed, converted to a formatted serial bit stream, and converted to light signals for transmission over a single fiber of the fiber optics link. At the local station, the received optical signals are reconstructed as electrical control signals for the controlled motors or other devices. At the local station, an encoder sensor linked to the driven device generates encoded feedback signals which provide information as to a condition of the controlled device. The encoded signals are placed in a formatted serial bit stream, multiplexed, and transmitted as optical signals over a second fiber of the fiber optic link which closes the control loop of the closed-loop motor controller. The encoded optical signals received at the remote station are demultiplexed, reconstructed and coupled to the controller(s) as electrical feedback signals.

Intra Frame Coding In Advanced Video Coding Standard (H.264) to Obtain Consistent PSNR and Reduce Bit Rate for Diagonal Down Left Mode Using Gaussian Pulse

NASA Astrophysics Data System (ADS)

Manjanaik, N.; Parameshachari, B. D.; Hanumanthappa, S. N.; Banu, Reshma

2017-08-01

Intra prediction process of H.264 video coding standard used to code first frame i.e. Intra frame of video to obtain good coding efficiency compare to previous video coding standard series. More benefit of intra frame coding is to reduce spatial pixel redundancy with in current frame, reduces computational complexity and provides better rate distortion performance. To code Intra frame it use existing process Rate Distortion Optimization (RDO) method. This method increases computational complexity, increases in bit rate and reduces picture quality so it is difficult to implement in real time applications, so the many researcher has been developed fast mode decision algorithm for coding of intra frame. The previous work carried on Intra frame coding in H.264 standard using fast decision mode intra prediction algorithm based on different techniques was achieved increased in bit rate, degradation of picture quality(PSNR) for different quantization parameters. Many previous approaches of fast mode decision algorithms on intra frame coding achieved only reduction of computational complexity or it save encoding time and limitation was increase in bit rate with loss of quality of picture. In order to avoid increase in bit rate and loss of picture quality a better approach was developed. In this paper developed a better approach i.e. Gaussian pulse for Intra frame coding using diagonal down left intra prediction mode to achieve higher coding efficiency in terms of PSNR and bitrate. In proposed method Gaussian pulse is multiplied with each 4x4 frequency domain coefficients of 4x4 sub macro block of macro block of current frame before quantization process. Multiplication of Gaussian pulse for each 4x4 integer transformed coefficients at macro block levels scales the information of the coefficients in a reversible manner. The resulting signal would turn abstract. Frequency samples are abstract in a known and controllable manner without intermixing of coefficients, it avoids picture getting bad hit for higher values of quantization parameters. The proposed work was implemented using MATLAB and JM 18.6 reference software. The proposed work measure the performance parameters PSNR, bit rate and compression of intra frame of yuv video sequences in QCIF resolution under different values of quantization parameter with Gaussian value for diagonal down left intra prediction mode. The simulation results of proposed algorithm are tabulated and compared with previous algorithm i.e. Tian et al method. The proposed algorithm achieved reduced in bit rate averagely 30.98% and maintain consistent picture quality for QCIF sequences compared to previous algorithm i.e. Tian et al method.

A low-noise low-power EEG acquisition node for scalable brain-machine interfaces

NASA Astrophysics Data System (ADS)

Sullivan, Thomas J.; Deiss, Stephen R.; Cauwenberghs, Gert; Jung, Tzyy-Ping

2007-05-01

Electroencephalograph (EEG) recording systems offer a versatile, noninvasive window on the brain's spatio-temporal activity for many neuroscience and clinical applications. Our research aims at improving the spatial resolution and mobility of EEG recording by reducing the form factor, power drain and signal fanout of the EEG acquisition node in a scalable sensor array architecture. We present such a node integrated onto a dimesized circuit board that contains a sensor's complete signal processing front-end, including amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. The circuit's low power consumption of 423 μW supports EEG systems with hundreds of electrodes to operate from small batteries for many hours. Coupling between the bit-serial output and the highly sensitive analog input due to dense integration of analog and digital functions on the circuit board results in a deterministic noise component in the output, larger than the intrinsic sensor and circuit noise. With software correction of this noise contribution, the system achieves an input-referred noise of 0.277 μVrms in the signal band of 1 to 100 Hz, comparable to the best medical-grade systems in use. A chain of seven nodes using EEG dry electrodes created in micro-electrical-mechanical system (MEMS) technology is demonstrated in a real-world setting.

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Simultaneous wavelength conversion of ASK and DPSK signals based on four-wave-mixing in dispersion engineered silicon waveguides.

PubMed

Xu, Lin; Ophir, Noam; Menard, Michael; Lau, Ryan Kin Wah; Turner-Foster, Amy C; Foster, Mark A; Lipson, Michal; Gaeta, Alexander L; Bergman, Keren

2011-06-20

We experimentally demonstrate four-wave-mixing (FWM)-based continuous wavelength conversion of optical differential-phase-shift-keyed (DPSK) signals with large wavelength conversion ranges as well as simultaneous wavelength conversion of dual-wavelength channels with mixed modulation formats in 1.1-cm-long dispersion-engineered silicon waveguides. We first validate up to 100-nm wavelength conversion range for 10-Gb/s DPSK signals, showcasing the capability to perform phase-preserving operations at high bit rates in chip-scale devices over wide conversion ranges. We further validate the wavelength conversion of dual-wavelength channels modulated with 10-Gb/s packetized phase-shift-keyed (PSK) and amplitude-shift-keyed (ASK) signals; demonstrate simultaneous operation on multiple channels with mixed formats in chip-scale devices. For both configurations, we measure the spectral and temporal responses and evaluate the performances using bit-error-rate (BER) measurements.

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barhen, Jacob; Kerekes, Ryan A; ST Charles, Jesse Lee

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlationmore » processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core performs the matrix-vector multiplications, where the nominal matrix size is 256x256. The system clock is 125MHz. At each clock cycle, 128K multiply-and-add operations per second (OPS) are carried out, which yields a peak performance of 16 TeraOPS. IBM Cell Broadband Engine. The Cell processor is the extraordinary resulting product of 5 years of sustained, intensive R&D collaboration (involving over $400M investment) between IBM, Sony, and Toshiba. Its architecture comprises one multithreaded 64-bit PowerPC processor element (PPE) with VMX capabilities and two levels of globally coherent cache, and 8 synergistic processor elements (SPEs). Each SPE consists of a processor (SPU) designed for streaming workloads, local memory, and a globally coherent direct memory access (DMA) engine. Computations are performed in 128-bit wide single instruction multiple data streams (SIMD). An integrated high-bandwidth element interconnect bus (EIB) connects the nine processors and their ports to external memory and to system I/O. The Applied Software Engineering Research (ASER) Group at the ORNL is applying the Cell to a variety of text and image analysis applications. Research on Cell-equipped PlayStation3 (PS3) consoles has led to the development of a correlation-based image recognition engine that enables a single PS3 to process images at more than 10X the speed of state-of-the-art single-core processors. NVIDIA Graphics Processing Units. The ASER group is also employing the latest NVIDIA graphical processing units (GPUs) to accelerate clustering of thousands of text documents using recently developed clustering algorithms such as document flocking and affinity propagation.« less

A Wearable Healthcare System With a 13.7 μA Noise Tolerant ECG Processor.

PubMed

Izumi, Shintaro; Yamashita, Ken; Nakano, Masanao; Kawaguchi, Hiroshi; Kimura, Hiromitsu; Marumoto, Kyoji; Fuchikami, Takaaki; Fujimori, Yoshikazu; Nakajima, Hiroshi; Shiga, Toshikazu; Yoshimoto, Masahiko

2015-10-01

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

Design of an anti-Rician-fading modem for mobile satellite communication systems

NASA Technical Reports Server (NTRS)

Kojima, Toshiharu; Ishizu, Fumio; Miyake, Makoto; Murakami, Keishi; Fujino, Tadashi

1995-01-01

To design a demodulator applicable to mobile satellite communication systems using differential phase shift keying modulation, we have developed key technologies including an anti-Rician-fading demodulation scheme, an initial acquisition scheme, automatic gain control (AGC), automatic frequency control (AFC), and bit timing recovery (BTR). Using these technologies, we have developed one-chip digital signal processor (DSP) modem for mobile terminal, which is compact, of light weight, and of low power consumption. Results of performance test show that the developed DSP modem achieves good performance in terms of bit error ratio in mobile satellite communication environment, i.e., Rician fading channel. It is also shown that the initial acquisition scheme acquires received signal rapidly even if the carrier-to-noise power ratio (CNR) of the received signal is considerably low.

DarkBit: a GAMBIT module for computing dark matter observables and likelihoods

NASA Astrophysics Data System (ADS)

Bringmann, Torsten; Conrad, Jan; Cornell, Jonathan M.; Dal, Lars A.; Edsjö, Joakim; Farmer, Ben; Kahlhoefer, Felix; Kvellestad, Anders; Putze, Antje; Savage, Christopher; Scott, Pat; Weniger, Christoph; White, Martin; Wild, Sebastian

2017-12-01

We introduce DarkBit, an advanced software code for computing dark matter constraints on various extensions to the Standard Model of particle physics, comprising both new native code and interfaces to external packages. This release includes a dedicated signal yield calculator for gamma-ray observations, which significantly extends current tools by implementing a cascade-decay Monte Carlo, as well as a dedicated likelihood calculator for current and future experiments ( gamLike). This provides a general solution for studying complex particle physics models that predict dark matter annihilation to a multitude of final states. We also supply a direct detection package that models a large range of direct detection experiments ( DDCalc), and that provides the corresponding likelihoods for arbitrary combinations of spin-independent and spin-dependent scattering processes. Finally, we provide custom relic density routines along with interfaces to DarkSUSY, micrOMEGAs, and the neutrino telescope likelihood package nulike. DarkBit is written in the framework of the Global And Modular Beyond the Standard Model Inference Tool ( GAMBIT), providing seamless integration into a comprehensive statistical fitting framework that allows users to explore new models with both particle and astrophysics constraints, and a consistent treatment of systematic uncertainties. In this paper we describe its main functionality, provide a guide to getting started quickly, and show illustrative examples for results obtained with DarkBit (both as a stand-alone tool and as a GAMBIT module). This includes a quantitative comparison between two of the main dark matter codes ( DarkSUSY and micrOMEGAs), and application of DarkBit 's advanced direct and indirect detection routines to a simple effective dark matter model.

High Bandwidth, Multi-Purpose Passive Radar Receiver Design For Aerospace and Geoscience Targets

NASA Astrophysics Data System (ADS)

Vertatschitsch, Laura

Passive radar permits inexpensive and stealthy detection and tracking of aerospace and geoscience targets. Transmitters of opportunity such as commercial FM broadcast, DTV broadcast, and cell phone towers are already illuminating many populated areas with continuous power. Passive radar receivers can be located at a distance from the transmitter, and can sense this direct transmission as well as any reflections from ground clutter, aircraft, ionospheric turbulence and meteor trails. The 100% duty cycle allows for long coherent integration, increasing the sensitivity of these instruments greatly. Traditional radar receivers employ analog front end downconverters to translate the radio frequency spectrum to an intermediate frequency (IF) for sampling and signal processing. Such downconverters limit the spectrum available for study, and can introduce nonlinearities which limit the detectability of weak signals in the presence of strong signals. With suitably fast digitizers one can bypass the downconversion stage completely. Very fast digitizers may have relatively few bits, but precision is recovered in subsequent signal processing. We present a new passive radar receiver designed to utilize a broad spectrum of commercial transmitters without the use of a front end analog downconverter. The receiver centers around a Reconfigurable Open Architecture Computing Hardware (ROACH) board developed by the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) group. Fast sampling rates (8-bit samples as fast as 3 GSps) combined with 640 multiply/addition operations on the Virtex-5 FPGA centered on the ROACH allows for coherent processing of broad spectrum and dynamic decision-making on one device all while sharing a single front end, putting this device on the cutting edge of wideband receiver technology. The radar is also designed to support mobile operation. It fits within a 19'' rack, it is equipped with solid state hard drives, and can run off an uninterruptible power supply (UPS) for up to 1 hour of continuous operation. In this document we provide technical details of the hardware, firmware, and software of the system and design strategies and decisions. We cover the topic of coherent processing for passive radar, specifically an overview of the cross-ambiguity function as a detection mechanism. While the applications of a system like this are incredibly broad, the initial validation and performance analysis was applied specifically to detection of aircraft using Digital Television (DTV) broadcast as an illuminator. We present results of both stationary and mobile operation. In stationary operation, the same helicopter has been detected using two different DTV transmissions. Early mobile operation results show the Doppler-spread ground clutter and possible detection of aircraft. In addition to the fully-functional aircraft detection signal chain, alternative FPGA designs are presented with modes for fast sampling on two antennas or four antennas, with access to an aggregate 240 MHz of spectrum, with 8-bit samples. At these extremely high data rates, moderate data loss occurs while saving this data to disk, but as detailed within this document, it can be accounted for and the effects minimalized, still allowing for detection of aircraft. With these modes, FM transmission and DTV transmission can be captured synchronously from a single antenna and digitizer feed, an exciting result that offers promise for both aerospace and geoscience applications.

Performance measurement results for a 220 Mbps QPPM optical communication receiver with an EG/G Slik APD

NASA Technical Reports Server (NTRS)

Davidson, Frederic M.; Sun, Xiaoli

1992-01-01

The performance of a 220 Mbps quaternary pulse position modulation (QPPM) optical communication receiver with a 'Slik' silicon avalanche photodiode (APD) and a wideband transimpedance preamplifier in a small hybrid circuit module was measured. The receiver performance had been poor due to the lack of a wideband and low noise transimpedance preamplifier. With the new APB preamplifier module, the receiver achieved a bit error rate (BER) of 10 exp -6 at an average received input optical signal power of 4.2 nW, which corresponds to an average of 80 received (incident) signal photons per information bit.

Design of an optical 4-bit binary to BCD converter using electro-optic effect of lithium niobate based Mach-Zehnder interferometers

NASA Astrophysics Data System (ADS)

Kumar, Santosh

2017-07-01

Binary to Binary coded decimal (BCD) converter is a basic building block for BCD processing. The last few decades have witnessed exponential rise in applications of binary coded data processing in the field of optical computing thus there is an eventual increase in demand of acceptable hardware platform for the same. Keeping this as an approach a novel design exploiting the preeminent feature of Mach-Zehnder Interferometer (MZI) is presented in this paper. Here, an optical 4-bit binary to binary coded decimal (BCD) converter utilizing the electro-optic effect of lithium niobate based MZI has been demonstrated. It exhibits the property of switching the optical signal from one port to the other, when a certain appropriate voltage is applied to its electrodes. The projected scheme is implemented using the combinations of cascaded electro-optic (EO) switches. Theoretical description along with mathematical formulation of the device is provided and the operation is analyzed through finite difference-Beam propagation method (FD-BPM). The fabrication techniques to develop the device are also discussed.

[Digital processing and evaluation of ultrasound images].

PubMed

Borchers, J; Klews, P M

1993-10-01

With the help of workstations and PCs, on-site image processing has become possible. If the images are not available in digital form the video signal has to be A/D converted. In the case of colour images the colour channels R (red), G (green) and B (blue) have to be digitized separately. "Truecolour" imaging calls for an 8 bit resolution per channel, leading to 24 bits per pixel. Out of a pool of 2(24) possible values only the relevant 128 gray values and 64 shades of red and blue respectively needed for a colour-coded ultrasound image have to be isolated. Digital images can be changed and evaluated with the help of readily available image evaluation programmes. It is mandatory that during image manipulation the gray scale and colour pixels and LUTs (Look-Up-Table) must be worked on separately. Using relatively simple LUT manipulations astonishing image improvements are possible. Application of simple mathematical operations can lead to completely new clinical results. For example, by subtracting two consecutive colour flow images in time and special LUT operations, local acceleration of blood flow can be visualized (Colour Acceleration Imaging).

Signal Detection and Frame Synchronization of Multiple Wireless Networking Waveforms

DTIC Science & Technology

2007-09-01

punctured to obtain coding rates of 2 3 and 3 4 . Convolutional forward error correction coding is used to detect and correct bit...likely to be isolated and be correctable by the convolutional decoder. 44 Data rate (Mbps) Modulation Coding Rate Coded bits per subcarrier...binary convolutional code . A shortened Reed-Solomon technique is employed first. The code is shortened depending upon the data

Combinatorial FSK modulation for power-efficient high-rate communications

NASA Technical Reports Server (NTRS)

Wagner, Paul K.; Budinger, James M.; Vanderaar, Mark J.

1991-01-01

Deep-space and satellite communications systems must be capable of conveying high-rate data accurately with low transmitter power, often through dispersive channels. A class of noncoherent Combinatorial Frequency Shift Keying (CFSK) modulation schemes is investigated which address these needs. The bit error rate performance of this class of modulation formats is analyzed and compared to the more traditional modulation types. Candidate modulator, demodulator, and digital signal processing (DSP) hardware structures are examined in detail. System-level issues are also discussed.

Proposal and performance analysis on the PDM microwave photonic link for the mm-wave signal with hybrid QAM-MPPM-RZ modulation

NASA Astrophysics Data System (ADS)

Tian, Bo; Zhang, Qi; Ma, Jianxin; Tao, Ying; Shen, Yufei; Wang, Yang; Zhang, Geng; Zhou, Wenmao; Zhao, Yi; Pan, Xiaolong

2018-07-01

A polarization division multiplexed (PDM) microwave photonic link for the millimeter (MM)-wave signal with hybrid modulation scheme is proposed in this paper, which is based on the combination of quadrature amplitude modulation, multi-pulse pulse-position modulation and return to zero modulation (QAM-MPPM-RZ). In this scheme, the two orthogonal polarization states enable simultaneous transmission of four data flows, which can provide different services for users according to the data rate requirement. To generate hybrid QAM-MPPM-RZ mm-wave signal, the QAM mm-wave signal is directly modulated by MPPM-RZ signal without using digital signal processing (DSP) devices, which reduces the overhead of the encoding process. Then, the generated QAM-MPPM-RZ mm-wave signal is transmitted in PDM microwave photonic link based on SSB modulation. The sparsity characteristic of QAM-MPPM-RZ not only improves the power efficiency, but also decreases the degradation caused by the fiber chromatic dispersion. The simulation results show that, under the constraint of the same transmitted data rate, the PDM microwave photonic link with 50 GHz QAM-MPPM-RZ mm-wave signal achieves much lower levels of bit-error rate than ordinary 32-QAM. In addition, the increase of laser linewidth brings no additional impact to the proposed scheme.

Cepstral domain modification of audio signals for data embedding: preliminary results

NASA Astrophysics Data System (ADS)

Gopalan, Kaliappan

2004-06-01

A method of embedding data in an audio signal using cepstral domain modification is described. Based on successful embedding in the spectral points of perceptually masked regions in each frame of speech, first the technique was extended to embedding in the log spectral domain. This extension resulted at approximately 62 bits /s of embedding with less than 2 percent of bit error rate (BER) for a clean cover speech (from the TIMIT database), and about 2.5 percent for a noisy speech (from an air traffic controller database), when all frames - including silence and transition between voiced and unvoiced segments - were used. Bit error rate increased significantly when the log spectrum in the vicinity of a formant was modified. In the next procedure, embedding by altering the mean cepstral values of two ranges of indices was studied. Tests on both a noisy utterance and a clean utterance indicated barely noticeable perceptual change in speech quality when lower range of cepstral indices - corresponding to vocal tract region - was modified in accordance with data. With an embedding capacity of approximately 62 bits/s - using one bit per each frame regardless of frame energy or type of speech - initial results showed a BER of less than 1.5 percent for a payload capacity of 208 embedded bits using the clean cover speech. BER of less than 1.3 percent resulted for the noisy host with a capacity was 316 bits. When the cepstrum was modified in the region of excitation, BER increased to over 10 percent. With quantization causing no significant problem, the technique warrants further studies with different cepstral ranges and sizes. Pitch-synchronous cepstrum modification, for example, may be more robust to attacks. In addition, cepstrum modification in regions of speech that are perceptually masked - analogous to embedding in frequency masked regions - may yield imperceptible stego audio with low BER.

The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

NASA Astrophysics Data System (ADS)

Qixing, Chen; Qiyu, Luo

2013-03-01

At present, the architecture of a digital-to-analog converter (DAC) in essence is based on the weight current, and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase, which is 2n-1 times of its least weight current. But for a dual weight resistance chain type DAC, by using the weight voltage manner to D/A conversion, the D/A signal current is fixed to chain current Icha; it is only 1/2n-1 order of magnitude of the average signal current value of the weight current type DAC. Its principle is: n pairs dual weight resistances form a resistance chain, which ensures the constancy of the chain current; if digital signals control the total weight resistance from the output point to the zero potential point, that could directly control the total weight voltage of the output point, so that the digital signals directly turn into a sum of the weight voltage signals; thus the following goals are realized: (1) the total current is less than 200 μA (2) the total power consumption is less than 2 mW; (3) an 18-bit conversion can be realized by adopting a multi-grade structure; (4) the chip area is one order of magnitude smaller than the subsection current-steering type DAC; (5) the error depends only on the error of the unit resistance, so it is smaller than the error of the subsection current-steering type DAC; (6) the conversion time is only one action time of switch on or off, so its speed is not lower than the present DAC.

Enhancing Performance and Bit Rates in a Brain-Computer Interface System With Phase-to-Amplitude Cross-Frequency Coupling: Evidences From Traditional c-VEP, Fast c-VEP, and SSVEP Designs.

PubMed

Dimitriadis, Stavros I; Marimpis, Avraam D

2018-01-01

A brain-computer interface (BCI) is a channel of communication that transforms brain activity into specific commands for manipulating a personal computer or other home or electrical devices. In other words, a BCI is an alternative way of interacting with the environment by using brain activity instead of muscles and nerves. For that reason, BCI systems are of high clinical value for targeted populations suffering from neurological disorders. In this paper, we present a new processing approach in three publicly available BCI data sets: (a) a well-known multi-class ( N = 6) coded-modulated Visual Evoked potential (c-VEP)-based BCI system for able-bodied and disabled subjects; (b) a multi-class ( N = 32) c-VEP with slow and fast stimulus representation; and (c) a steady-state Visual Evoked potential (SSVEP) multi-class ( N = 5) flickering BCI system. Estimating cross-frequency coupling (CFC) and namely δ-θ [δ: (0.5-4 Hz), θ: (4-8 Hz)] phase-to-amplitude coupling (PAC) within sensor and across experimental time, we succeeded in achieving high classification accuracy and Information Transfer Rates (ITR) in the three data sets. Our approach outperformed the originally presented ITR on the three data sets. The bit rates obtained for both the disabled and able-bodied subjects reached the fastest reported level of 324 bits/min with the PAC estimator. Additionally, our approach outperformed alternative signal features such as the relative power (29.73 bits/min) and raw time series analysis (24.93 bits/min) and also the original reported bit rates of 10-25 bits/min . In the second data set, we succeeded in achieving an average ITR of 124.40 ± 11.68 for the slow 60 Hz and an average ITR of 233.99 ± 15.75 for the fast 120 Hz. In the third data set, we succeeded in achieving an average ITR of 106.44 ± 8.94. Current methodology outperforms any previous methodologies applied to each of the three free available BCI datasets.

Design study report. Volume 2: Electronic unit

NASA Technical Reports Server (NTRS)

1973-01-01

The recording system discussed is required to record and reproduce wideband data from either of the two primary Earth Resources Technology Satellite sensors: Return Beam Vidicon (RBV) camera or Multi-Spectral Scanner (MSS). The camera input is an analog signal with a bandwidth from dc to 3.5 MHz; this signal is accommodated through FM recording techniques which provide a recorder signal-to-noise ratio in excess of 39 db, black-to-white signal/rms noise, over the specified bandwidth. The MSS provides, as initial output, 26 narrowband channels. These channels are multiplexed prior to transmission, or recording, into a single 15 Megabit/second digital data stream. Within the recorder, the 15 Megabit/second NRZL signal is processed through the same FM electronics as the RBV signal, but the basic FM standards are modified to provide an internal, 10.5 MHz baseland response with signal-to-noise ratio of about 25 db. Following FM demodulation, however, the MSS signal is digitally re-shaped and re-clocked so that good bit stability and signal-to-noise exist at the recorder output.

Research and design on orthogonal diffraction grating-based 3D nanometer displacement sensor

NASA Astrophysics Data System (ADS)

Liu, Baoshuai; Yuan, Yibao; Yin, Zhehao

2017-10-01

This study concerns an orthogonal diffraction grating-based nanometer displacement sensor. In this study, we performed calculation of displacements in the XYZ directions. In the optical measured path part, we used a two-dimensional orthogonal motion grating and a two-dimensional orthogonal reference grating with the pitch of 0.5um to measure the displacement of XYZ in three directions by detecting ±1st diffraction fringes. The self-collimated structure of the grating greatly extended the Z-axis range. We also simulated the optical path of the sensor with ZEMAX software and verified the feasibility of the scheme. For signal subdivision and processing, we combined large number counting (completed grating line) with small number counting (digital subdivision), realizing high multiples of subdivision of grating interference signals. We used PC to process the interference fringes and greatly improved the processing speed. In the scheme, the theoretical multiples of subdivision could reach 1024 with 10-bit AD conversion, but the actual multiples of subdivision was limited by the quality of the grating interference signals. So we introduced an orthogonal compensation circuit and a filter circuit to improve the signal quality.

Image display device in digital TV

DOEpatents

Choi, Seung Jong [Seoul, KR

2006-07-18

Disclosed is an image display device in a digital TV that is capable of carrying out the conversion into various kinds of resolution by using single bit map data in the digital TV. The image display device includes: a data processing part for executing bit map conversion, compression, restoration and format-conversion for text data; a memory for storing the bit map data obtained according to the bit map conversion and compression in the data processing part and image data inputted from an arbitrary receiving part, the receiving part receiving one of digital image data and analog image data; an image outputting part for reading the image data from the memory; and a display processing part for mixing the image data read from the image outputting part and the bit map data converted in format from the a data processing part. Therefore, the image display device according to the present invention can convert text data in such a manner as to correspond with various resolution, carry out the compression for bit map data, thereby reducing the memory space, and support text data of an HTML format, thereby providing the image with the text data of various shapes.

Switchable in-line monitor for multi-dimensional multiplexed photonic integrated circuit.

PubMed

Chen, Guanyu; Yu, Yu; Ye, Mengyuan; Zhang, Xinliang

2016-06-27

A flexible monitor suitable for the discrimination of on-chip transmitted mode division multiplexed (MDM) and wavelength division multiplexed (WDM) signals is proposed and fabricated. By selectively extracting part of the incoming signals through the tunable wavelength and mode dependent drop filter, the in-line and switchable monitor can discriminate the wavelength, mode and power information of the transmitted signals. Being different from a conventional mode and wavelength demultiplexer, the monitor is specifically designed to ensure a flexible in-line monitoring. For demonstration, three mode and three wavelength multiplexed signals are successfully processed. Assisted by the integrated photodetectors (PDs), both the measured photo currents and eye diagrams validate the performance of the proposed device. The bit error ratio (BER) measurement results show less than 0.4 dB power penalty between different modes and ~2 dB power penalty for single wavelength and WDM cases under 10^-9 BER level.

Fractional Gaussian noise-enhanced information capacity of a nonlinear neuron model with binary signal input

NASA Astrophysics Data System (ADS)

Gao, Feng-Yin; Kang, Yan-Mei; Chen, Xi; Chen, Guanrong

2018-05-01

This paper reveals the effect of fractional Gaussian noise with Hurst exponent H ∈(1 /2 ,1 ) on the information capacity of a general nonlinear neuron model with binary signal input. The fGn and its corresponding fractional Brownian motion exhibit long-range, strong-dependent increments. It extends standard Brownian motion to many types of fractional processes found in nature, such as the synaptic noise. In the paper, for the subthreshold binary signal, sufficient conditions are given based on the "forbidden interval" theorem to guarantee the occurrence of stochastic resonance, while for the suprathreshold binary signal, the simulated results show that additive fGn with Hurst exponent H ∈(1 /2 ,1 ) could increase the mutual information or bits count. The investigation indicated that the synaptic noise with the characters of long-range dependence and self-similarity might be the driving factor for the efficient encoding and decoding of the nervous system.

A full-duplex optical access system with hybrid 64/16/4QAM-OFDM downlink

NASA Astrophysics Data System (ADS)

He, Chao; Tan, Ze-fu; Shao, Yu-feng; Cai, Li; Pu, He-sheng; Zhu, Yun-le; Huang, Si-si; Liu, Yu

2016-09-01

A full-duplex optical passive access scheme is proposed and verified by simulation, in which hybrid 64/16/4-quadrature amplitude modulation (64/16/4QAM) orthogonal frequency division multiplexing (OFDM) optical signal is for downstream transmission and non-return-to-zero (NRZ) optical signal is for upstream transmission. In view of the transmitting and receiving process for downlink optical signal, in-phase/quadrature-phase (I/Q) modulation based on Mach-Zehnder modulator (MZM) and homodyne coherent detection technology are employed, respectively. The simulation results show that the bit error ratio ( BER) less than hardware decision forward error correction (HD-FEC) threshold is successfully obtained over transmission path with 20-km-long standard single mode fiber (SSMF) for hybrid downlink modulation OFDM optical signal. In addition, by dividing the system bandwidth into several subchannels consisting of some continuous subcarriers, it is convenient for users to select different channels depending on requirements of communication.

Synchronization trigger control system for flow visualization

NASA Technical Reports Server (NTRS)

Chun, K. S.

1987-01-01

The use of cinematography or holographic interferometry for dynamic flow visualization in an internal combustion engine requires a control device that globally synchronizes camera and light source timing at a predefined shaft encoder angle. The device is capable of 0.35 deg resolution for rotational speeds of up to 73 240 rpm. This was achieved by implementing the shaft encoder signal addressed look-up table (LUT) and appropriate latches. The developed digital signal processing technique achieves 25 nsec of high speed triggering angle detection by using direct parallel bit comparison of the shaft encoder digital code with a simulated angle reference code, instead of using angle value comparison which involves more complicated computation steps. In order to establish synchronization to an AC reference signal whose magnitude is variant with the rotating speed, a dynamic peak followup synchronization technique has been devised. This method scrutinizes the reference signal and provides the right timing within 40 nsec. Two application examples are described.

ImageJ: Image processing and analysis in Java

NASA Astrophysics Data System (ADS)

Rasband, W. S.

2012-06-01

ImageJ is a public domain Java image processing program inspired by NIH Image. It can display, edit, analyze, process, save and print 8-bit, 16-bit and 32-bit images. It can read many image formats including TIFF, GIF, JPEG, BMP, DICOM, FITS and "raw". It supports "stacks", a series of images that share a single window. It is multithreaded, so time-consuming operations such as image file reading can be performed in parallel with other operations.

Multigigahertz range-Doppler correlative processing in crystals

NASA Astrophysics Data System (ADS)

Harris, Todd L.; Babbitt, Wm. R.; Merkel, Kristian D.; Mohan, R. Krishna; Cole, Zachary; Olson, Andy

2004-06-01

Spectral-spatial holographic crystals have the unique ability to resolve fine spectral features (down to kilohertz) in an optical waveform over a broad bandwidth (over 10 gigahertz). This ability allows these crystals to record the spectral interference between spread spectrum waveforms that are temporally separated by up to several microseconds. Such crystals can be used for performing radar range-Doppler processing with fine temporal resolution. An added feature of these crystals is the long upper state lifetime of the absorbing rare earth ions, which allows the coherent integration of multiple recorded spectra, yielding integration gain and significant processing gain enhancement for selected code sets, as well as high resolution Doppler processing. Parallel processing of over 10,000 beams could be achieved with a crystal the size of a sugar cube. Spectral-spatial holographic processing and coherent integration of up to 2.5 Gigabit per second coded waveforms and of lengths up to 2047 bits has previously been reported. In this paper, we present the first demonstration of Doppler processing with these crystals. Doppler resolution down to a few hundred Hz for broadband radar signals can be achieved. The processing can be performed directly on signals modulated onto IF carriers (up to several gigahertz) without having to mix the signals down to baseband and without having to employ broadband analog to digital conversion.

True random bit generators based on current time series of contact glow discharge electrolysis

NASA Astrophysics Data System (ADS)

Rojas, Andrea Espinel; Allagui, Anis; Elwakil, Ahmed S.; Alawadhi, Hussain

2018-05-01

Random bit generators (RBGs) in today's digital information and communication systems employ a high rate physical entropy sources such as electronic, photonic, or thermal time series signals. However, the proper functioning of such physical systems is bound by specific constrains that make them in some cases weak and susceptible to external attacks. In this study, we show that the electrical current time series of contact glow discharge electrolysis, which is a dc voltage-powered micro-plasma in liquids, can be used for generating random bit sequences in a wide range of high dc voltages. The current signal is quantized into a binary stream by first using a simple moving average function which makes the distribution centered around zero, and then applying logical operations which enables the binarized data to pass all tests in industry-standard randomness test suite by the National Institute of Standard Technology. Furthermore, the robustness of this RBG against power supply attacks has been examined and verified.

Silicon microdisk-based full adders for optical computing.

PubMed

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z; Soref, Richard; Chen, Ray T

2018-03-01

Due to the projected saturation of Moore's law, as well as the drastically increasing trend of bandwidth with lower power consumption, silicon photonics has emerged as one of the most promising alternatives that has attracted a lasting interest due to the accessibility and maturity of ultra-compact passive and active integrated photonic components. In this Letter, we demonstrate a ripple-carry electro-optic 2-bit full adder using microdisks, which replaces the core part of an electrical full adder by optical counterparts and uses light to carry signals from one bit to the next with high bandwidth and low power consumption per bit. All control signals of the operands are applied simultaneously within each clock cycle. Thus, the severe latency issue that accumulates as the size of the full adder increases can be circumvented, allowing for an improvement in computing speed and a reduction in power consumption. This approach paves the way for future high-speed optical computing systems in the post-Moore's law era.

Fast interrupt platform for extended DOS

NASA Technical Reports Server (NTRS)

Duryea, T. W.

1995-01-01

Extended DOS offers the unique combination of a simple operating system which allows direct access to the interrupt tables, 32 bit protected mode access to 4096 MByte address space, and the use of industry standard C compilers. The drawback is that fast interrupt handling requires both 32 bit and 16 bit versions of each real-time process interrupt handler to avoid mode switches on the interrupts. A set of tools has been developed which automates the process of transforming the output of a standard 32 bit C compiler to 16 bit interrupt code which directly handles the real mode interrupts. The entire process compiles one set of source code via a make file, which boosts productivity by making the management of the compile-link cycle very simple. The software components are in the form of classes written mostly in C. A foreground process written as a conventional application which can use the standard C libraries can communicate with the background real-time classes via a message passing mechanism. The platform thus enables the integration of high performance real-time processing into a conventional application framework.

Practical remarks on the heart rate and saturation measurement methodology

NASA Astrophysics Data System (ADS)

Kowal, M.; Kubal, S.; Piotrowski, P.; Staniec, K.

2017-05-01

A surface reflection-based method for measuring heart rate and saturation has been introduced as one having a significant advantage over legacy methods in that it lends itself for use in special applications such as those where a person’s mobility is of prime importance (e.g. during a miner’s work) and excluding the use of traditional clips. Then, a complete ATmega1281-based microcontroller platform has been described for performing computational tasks of signal processing and wireless transmission. In the next section remarks have been provided regarding the basic signal processing rules beginning with raw voltage samples of converted optical signals, their acquisition, storage and smoothing. This chapter ends with practical remarks demonstrating an exponential dependence between the minimum measurable heart rate and the readout resolution at different sampling frequencies for different cases of averaging depth (in bits). The following section is devoted strictly to the heart rate and hemoglobin oxygenation (saturation) measurement with the use of the presented platform, referenced to measurements obtained with a stationary certified pulsoxymeter.

Time reversal focusing of high amplitude sound in a reverberation chamber.

PubMed

Willardson, Matthew L; Anderson, Brian E; Young, Sarah M; Denison, Michael H; Patchett, Brian D

2018-02-01

Time reversal (TR) is a signal processing technique that can be used for intentional sound focusing. While it has been studied in room acoustics, the application of TR to produce a high amplitude focus of sound in a room has not yet been explored. The purpose of this study is to create a virtual source of spherical waves with TR that are of sufficient intensity to study nonlinear acoustic propagation. A parameterization study of deconvolution, one-bit, clipping, and decay compensation TR methods is performed to optimize high amplitude focusing and temporal signal focus quality. Of all TR methods studied, clipping is shown to produce the highest amplitude focal signal. An experiment utilizing eight horn loudspeakers in a reverberation chamber is done with the clipping TR method. A peak focal amplitude of 9.05 kPa (173.1 dB peak re 20 μPa) is achieved. Results from this experiment indicate that this high amplitude focusing is a nonlinear process.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Ocean Basin Impact of Ambient Noise on Marine Mammal Detectability, Distribution, and Acoustic Communication - YIP

DTIC Science & Technology

2011-09-30

when applying the 4 passive sonar equation. The integration of acoustic time series from different ocean basins will provide a synoptic...Penn State ARL Hydrophone Analog signal (V) Preamplifiers & 24-bit AiD 1-100 HzBP filter Signal Flow for a Single Hydrophone Digital signal

Enzyme-like replication de novo in a microcontroller environment.

PubMed

Tangen, Uwe

2010-01-01

The desire to start evolution from scratch inside a computer memory is as old as computing. Here we demonstrate how viable computer programs can be established de novo in a Precambrian environment without supplying any specific instantiation, just starting with random bit sequences. These programs are not self-replicators, but act much more like catalysts. The microcontrollers used in the end are the result of a long series of simplifications. The objective of this simplification process was to produce universal machines with a human-readable interface, allowing software and/or hardware evolution to be studied. The power of the instruction set can be modified by introducing a secondary structure-folding mechanism, which is a state machine, allowing nontrivial replication to emerge with an instruction width of only a few bits. This state-machine approach not only attenuates the problems of brittleness and encoding functionality (too few bits available for coding, and too many instructions needed); it also enables the study of hardware evolution as such. Furthermore, the instruction set is sufficiently powerful to permit external signals to be processed. This information-theoretic approach forms one vertex of a triangle alongside artificial cell research and experimental research on the creation of life. Hopefully this work helps develop an understanding of how information—in a similar sense to the account of functional information described by Hazen et al.—is created by evolution and how this information interacts with or is embedded in its physico-chemical environment.

Measuring signal-to-noise ratio automatically

NASA Technical Reports Server (NTRS)

Bergman, L. A.; Johnston, A. R.

1980-01-01

Automated method of measuring signal-to-noise ratio in digital communication channels is more precise and 100 times faster than previous methods used. Method based on bit-error-rate (B&R) measurement can be used with cable, microwave radio, or optical links.

Modulation and synchronization technique for MF-TDMA system

NASA Technical Reports Server (NTRS)

Faris, Faris; Inukai, Thomas; Sayegh, Soheil

1994-01-01

This report addresses modulation and synchronization techniques for a multi-frequency time division multiple access (MF-TDMA) system with onboard baseband processing. The types of synchronization techniques analyzed are asynchronous (conventional) TDMA, preambleless asynchronous TDMA, bit synchronous timing with a preamble, and preambleless bit synchronous timing. Among these alternatives, preambleless bit synchronous timing simplifies onboard multicarrier demultiplexer/demodulator designs (about 2:1 reduction in mass and power), requires smaller onboard buffers (10:1 to approximately 3:1 reduction in size), and provides better frame efficiency as well as lower onboard processing delay. Analysis and computer simulation illustrate that this technique can support a bit rate of up to 10 Mbit/s (or higher) with proper selection of design parameters. High bit rate transmission may require Doppler compensation and multiple phase error measurements. The recommended modulation technique for bit synchronous timing is coherent QPSK with differential encoding for the uplink and coherent QPSK for the downlink.

Line-of-Sight Data Link Test Set

DTIC Science & Technology

1976-06-01

spheric layer model for layer refraction or a surface reflectivity model for ground reflection paths. Measurement of the channel impulse response...the model is exercised over a path consisting of only a constant direct component. The test would consist of measuring the modem demodulator bit...direct and a fading direct component. The test typically would consist of measuring the bit error-rate over a range of average signal-to-noise

Free-space coherent optical communication receivers implemented with photorefractive optical beam combiners

NASA Technical Reports Server (NTRS)

Davidson, Frederic M.

1992-01-01

Performance measurements are reported concerning a coherent optical communication receiver that contained an iron doped indium phosphide photorefractive beam combiner, rather than a conventional optical beam splitter. The system obtained a bit error probability of 10(exp -6) at received signal powers corresponding to less than 100 detected photons per bit. The system used phase modulated Nd:YAG laser light at a wavelength of 1.06 microns.

Pulse Shaped 8-PSK Bandwidth Efficiency and Spectral Spike Elimination

NASA Technical Reports Server (NTRS)

Tao, Jian-Ping

1998-01-01

The most bandwidth-efficient communication methods are imperative to cope with the congested frequency bands. Pulse shaping methods have excellent effects on narrowing bandwidth and increasing band utilization. The position of the baseband filters for the pulse shaping is crucial. Post-modulation pulse shaping (a low pass filter is located after the modulator) can change signals from constant envelope to non-constant envelope, and non-constant envelope signals through non-linear device (a SSPA or TWT) can further spread the power spectra. Pre-modulation pulse shaping (a filter is located before the modulator) will have constant envelope. These two pulse shaping methods have different effects on narrowing the bandwidth and producing bit errors. This report studied the effect of various pre-modulation pulse shaping filters with respect to bandwidth, spectral spikes and bit error rate. A pre-modulation pulse shaped 8-ary Phase Shift Keying (8PSK) modulation was used throughout the simulations. In addition to traditional pulse shaping filters, such as Bessel, Butterworth and Square Root Raised Cosine (SRRC), other kinds of filters or pulse waveforms were also studied in the pre-modulation pulse shaping method. Simulations were conducted by using the Signal Processing Worksystem (SPW) software package on HP workstations which simulated the power spectral density of pulse shaped 8-PSK signals, end to end system performance and bit error rates (BERS) as a function of Eb/No using pulse shaping in an AWGN channel. These results are compared with the post-modulation pulse shaped 8-PSK results. The simulations indicate traditional pulse shaping filters used in pre-modulation pulse shaping may produce narrower bandwidth, but with worse BER than those in post-modulation pulse shaping. Theory and simulations show pre- modulation pulse shaping could also produce discrete line power spectra (spikes) at regular frequency intervals. These spikes may cause interference with adjacent channel and reduce power efficiency. Some particular pulses (filters), such as trapezoid and pulses with different transits (such as weighted raised cosine transit) were found to reduce bandwidth and not generate spectral spikes. Although a solid state power amplifier (SSPA) was simulated in the non-linear (saturation) region, output power spectra did not spread due to the constant envelope 8-PSK signals.

A novel multireceiver communications system configuration based on optimal estimation theory

NASA Technical Reports Server (NTRS)

Kumar, R.

1990-01-01

A multireceiver configuration for the purpose of carrier arraying and/or signal arraying is presented. Such a problem arises for example, in the NASA Deep Space Network where the same data-modulated signal from a spacecraft is received by a number of geographically separated antennas and the data detection must be efficiently performed on the basis of the various received signals. The proposed configuration is arrived at by formulating the carrier and/or signal arraying problem as an optimal estimation problem. Two specific solutions are proposed. The first solution is to simultaneously and optimally estimate the various phase processes received at different receivers with coupled phase locked loops (PLLs) wherein the individual PLLs acquire and track their respective receivers' phase processes, but are aided by each other in an optimal manner. However, when the phase processes are relatively weakly correlated, and for the case of relatively high values of symbol energy-to-noise spectral density ratio, a novel configuration for combining the data modulated, loop-output signals is proposed. The scheme can be extended to the case of low symbol energy-to-noise case by performing the combining/detection process over a multisymbol period. Such a configuration results in the minimization of the effective radio loss at the combiner output, and thus a maximization of energy per bit to noise-power spectral density ration is achieved.

Processing and Analysis of Multichannel Extracellular Neuronal Signals: State-of-the-Art and Challenges

PubMed Central

Mahmud, Mufti; Vassanelli, Stefano

2016-01-01

In recent years multichannel neuronal signal acquisition systems have allowed scientists to focus on research questions which were otherwise impossible. They act as a powerful means to study brain (dys)functions in in-vivo and in in-vitro animal models. Typically, each session of electrophysiological experiments with multichannel data acquisition systems generate large amount of raw data. For example, a 128 channel signal acquisition system with 16 bits A/D conversion and 20 kHz sampling rate will generate approximately 17 GB data per hour (uncompressed). This poses an important and challenging problem of inferring conclusions from the large amounts of acquired data. Thus, automated signal processing and analysis tools are becoming a key component in neuroscience research, facilitating extraction of relevant information from neuronal recordings in a reasonable time. The purpose of this review is to introduce the reader to the current state-of-the-art of open-source packages for (semi)automated processing and analysis of multichannel extracellular neuronal signals (i.e., neuronal spikes, local field potentials, electroencephalogram, etc.), and the existing Neuroinformatics infrastructure for tool and data sharing. The review is concluded by pinpointing some major challenges that are being faced, which include the development of novel benchmarking techniques, cloud-based distributed processing and analysis tools, as well as defining novel means to share and standardize data. PMID:27313507

A wavelet-based ECG delineation algorithm for 32-bit integer online processing

PubMed Central

2011-01-01

Background Since the first well-known electrocardiogram (ECG) delineator based on Wavelet Transform (WT) presented by Li et al. in 1995, a significant research effort has been devoted to the exploitation of this promising method. Its ability to reliably delineate the major waveform components (mono- or bi-phasic P wave, QRS, and mono- or bi-phasic T wave) would make it a suitable candidate for efficient online processing of ambulatory ECG signals. Unfortunately, previous implementations of this method adopt non-linear operators such as root mean square (RMS) or floating point algebra, which are computationally demanding. Methods This paper presents a 32-bit integer, linear algebra advanced approach to online QRS detection and P-QRS-T waves delineation of a single lead ECG signal, based on WT. Results The QRS detector performance was validated on the MIT-BIH Arrhythmia Database (sensitivity Se = 99.77%, positive predictive value P+ = 99.86%, on 109010 annotated beats) and on the European ST-T Database (Se = 99.81%, P+ = 99.56%, on 788050 annotated beats). The ECG delineator was validated on the QT Database, showing a mean error between manual and automatic annotation below 1.5 samples for all fiducial points: P-onset, P-peak, P-offset, QRS-onset, QRS-offset, T-peak, T-offset, and a mean standard deviation comparable to other established methods. Conclusions The proposed algorithm exhibits reliable QRS detection as well as accurate ECG delineation, in spite of a simple structure built on integer linear algebra. PMID:21457580

A wavelet-based ECG delineation algorithm for 32-bit integer online processing.

PubMed

Di Marco, Luigi Y; Chiari, Lorenzo

2011-04-03

Since the first well-known electrocardiogram (ECG) delineator based on Wavelet Transform (WT) presented by Li et al. in 1995, a significant research effort has been devoted to the exploitation of this promising method. Its ability to reliably delineate the major waveform components (mono- or bi-phasic P wave, QRS, and mono- or bi-phasic T wave) would make it a suitable candidate for efficient online processing of ambulatory ECG signals. Unfortunately, previous implementations of this method adopt non-linear operators such as root mean square (RMS) or floating point algebra, which are computationally demanding. This paper presents a 32-bit integer, linear algebra advanced approach to online QRS detection and P-QRS-T waves delineation of a single lead ECG signal, based on WT. The QRS detector performance was validated on the MIT-BIH Arrhythmia Database (sensitivity Se = 99.77%, positive predictive value P+ = 99.86%, on 109010 annotated beats) and on the European ST-T Database (Se = 99.81%, P+ = 99.56%, on 788050 annotated beats). The ECG delineator was validated on the QT Database, showing a mean error between manual and automatic annotation below 1.5 samples for all fiducial points: P-onset, P-peak, P-offset, QRS-onset, QRS-offset, T-peak, T-offset, and a mean standard deviation comparable to other established methods. The proposed algorithm exhibits reliable QRS detection as well as accurate ECG delineation, in spite of a simple structure built on integer linear algebra.

Use of One Time Pad Algorithm for Bit Plane Security Improvement

NASA Astrophysics Data System (ADS)

Suhardi; Suwilo, Saib; Budhiarti Nababan, Erna

2017-12-01

BPCS (Bit-Plane Complexity Segmentation) which is one of the steganography techniques that utilizes the human vision characteristics that cannot see the change in binary patterns that occur in the image. This technique performs message insertion by making a switch to a high-complexity bit-plane or noise-like regions with bits of secret messages. Bit messages that were previously stored precisely result the message extraction process to be done easily by rearranging a set of previously stored characters in noise-like region in the image. Therefore the secret message becomes easily known by others. In this research, the process of replacing bit plane with message bits is modified by utilizing One Time Pad cryptography technique which aims to increase security in bit plane. In the tests performed, the combination of One Time Pad cryptographic algorithm to the steganography technique of BPCS works well in the insertion of messages into the vessel image, although in insertion into low-dimensional images is poor. The comparison of the original image with the stegoimage looks identical and produces a good quality image with a mean value of PSNR above 30db when using a largedimensional image as the cover messages.

Channel Modeling

NASA Astrophysics Data System (ADS)

Schmitz, Arne; Schinnenburg, Marc; Gross, James; Aguiar, Ana

For any communication system the Signal-to-Interference-plus-Noise-Ratio of the link is a fundamental metric. Recall (cf. Chapter 9) that the SINR is defined as the ratio between the received power of the signal of interest and the sum of all "disturbing" power sources (i.e. interference and noise). From information theory it is known that a higher SINR increases the maximum possible error-free transmission rate (referred to as Shannon capacity [417] of any communication system and vice versa). Conversely, the higher the SINR, the lower will be the bit error rate in practical systems. While one aspect of the SINR is the sum of all distracting power sources, another issue is the received power. This depends on the transmitted power, the used antennas, possibly on signal processing techniques and ultimately on the channel gain between transmitter and receiver.

A fully integrated mixed-signal neural processor for implantable multichannel cortical recording.

PubMed

Sodagar, Amir M; Wise, Kensall D; Najafi, Khalil

2007-06-01

A 64-channel neural processor has been developed for use in an implantable neural recording microsystem. In the Scan Mode, the processor is capable of detecting neural spikes by programmable positive, negative, or window thresholding. Spikes are tagged with their associated channel addresses and formed into 18-bit data words that are sent serially to the external host. In the Monitor Mode, two channels can be selected and viewed at high resolution for studies where the entire signal is of interest. The processor runs from a 3-V supply and a 2-MHz clock, with a channel scan rate of 64 kS/s and an output bit rate of 2 Mbps.

A Temperature-Hardened Sensor Interface with a 12-Bit Digital Output Using a Novel Pulse Width Modulation Technique

PubMed Central

Badets, Franck; Nouet, Pascal; Masmoudi, Mohamed

2018-01-01

A fully integrated sensor interface for a wide operational temperature range is presented. It translates the sensor signal into a pulse width modulated (PWM) signal that is then converted into a 12-bit digital output. The sensor interface is based on a pair of injection locked oscillators used to implement a differential time-domain architecture with low sensitivity to temperature variations. A prototype has been fabricated using a 180 nm partially depleted silicon-on-insulator (SOI) technology. Experimental results demonstrate a thermal stability as low as 65 ppm/°C over a large temperature range from −20 °C up to 220 °C. PMID:29621171

Challenge of Near-Field Recording beyond 50.4 Gbit/in2

NASA Astrophysics Data System (ADS)

Kishima, Koichiro; Ichimura, Isao; Saito, Kimihiro; Yamamoto, Kenji; Kuroda, Yuji; Iida, Atsushi; Masuhara, Shin; Osato, Kiyoshi

2002-03-01

The possibility of an areal density over 50 Gbit/in2 was examined in near-field phase-change recording. The disk structure was optimized to maximize readout signals under the land-and-groove recording condition at a tracking pitch of 160 nm. We also evaluated the signal crosstalk from adjacent tracks. Eye diagrams of 50.4 Gbit/in2 areal density were demonstrated using 1.5 \\mathit{NA} optics and a GaN laser diode. The track pitch and linear bit density are 160 nm and 80 nm/bit, respectively. The transmission electron microscope (TEM) micrograph of recorded amorphous marks at an areal density of 50.4 Gbit/in2 is also presented.

40-Gb/s PDM-QPSK signal transmission over 160-m wireless distance at W-band.

PubMed

Xiao, Jiangnan; Yu, Jianjun; Li, Xinying; Xu, Yuming; Zhang, Ziran; Chen, Long

2015-03-15

We experimentally demonstrate a W-band optical-wireless transmission system over 160-m wireless distance with a bit rate up to 40 Gb/s. The optical-wireless transmission system adopts optical polarization-division-multiplexing (PDM), multiple-input multiple-output (MIMO) reception and antenna polarization diversity. Using this system, we experimentally demonstrate the 2×2 MIMO wireless delivery of 20- and 40-Gb/s PDM quadrature-phase-shift-keying (PDM-QPSK) signals over 640- and 160-m wireless links, respectively. The bit-error ratios (BERs) of these transmission systems are both less than the forward-error-correction (FEC) threshold of 3.8×10^-3.

A Subsystem Test Bed for Chinese Spectral Radioheliograph

NASA Astrophysics Data System (ADS)

Zhao, An; Yan, Yihua; Wang, Wei

2014-11-01

The Chinese Spectral Radioheliograph is a solar dedicated radio interferometric array that will produce high spatial resolution, high temporal resolution, and high spectral resolution images of the Sun simultaneously in decimetre and centimetre wave range. Digital processing of intermediate frequency signal is an important part in a radio telescope. This paper describes a flexible and high-speed digital down conversion system for the CSRH by applying complex mixing, parallel filtering, and extracting algorithms to process IF signal at the time of being designed and incorporates canonic-signed digit coding and bit-plane method to improve program efficiency. The DDC system is intended to be a subsystem test bed for simulation and testing for CSRH. Software algorithms for simulation and hardware language algorithms based on FPGA are written which use less hardware resources and at the same time achieve high performances such as processing high-speed data flow (1 GHz) with 10 MHz spectral resolution. An experiment with the test bed is illustrated by using geostationary satellite data observed on March 20, 2014. Due to the easy alterability of the algorithms on FPGA, the data can be recomputed with different digital signal processing algorithms for selecting optimum algorithm.

Automated recognition of helium speech. Phase I: Investigation of microprocessor based analysis/synthesis system

NASA Astrophysics Data System (ADS)

Jelinek, H. J.

1986-01-01

This is the Final Report of Electronic Design Associates on its Phase I SBIR project. The purpose of this project is to develop a method for correcting helium speech, as experienced in diver-surface communication. The goal of the Phase I study was to design, prototype, and evaluate a real time helium speech corrector system based upon digital signal processing techniques. The general approach was to develop hardware (an IBM PC board) to digitize helium speech and software (a LAMBDA computer based simulation) to translate the speech. As planned in the study proposal, this initial prototype may now be used to assess expected performance from a self contained real time system which uses an identical algorithm. The Final Report details the work carried out to produce the prototype system. Four major project tasks were: a signal processing scheme for converting helium speech to normal sounding speech was generated. The signal processing scheme was simulated on a general purpose (LAMDA) computer. Actual helium speech was supplied to the simulation and the converted speech was generated. An IBM-PC based 14 bit data Input/Output board was designed and built. A bibliography of references on speech processing was generated.

No Quantum Realization of Extremal No-Signaling Boxes

NASA Astrophysics Data System (ADS)

Ramanathan, Ravishankar; Tuziemski, Jan; Horodecki, Michał; Horodecki, Paweł

2016-07-01

The study of quantum correlations is important for fundamental reasons as well as for quantum communication and information processing tasks. On the one hand, it is of tremendous interest to derive the correlations produced by measurements on separated composite quantum systems from within the set of all correlations obeying the no-signaling principle of relativity, by means of information-theoretic principles. On the other hand, an important ongoing research program concerns the formulation of device-independent cryptographic protocols based on quantum nonlocal correlations for the generation of secure keys, and the amplification and expansion of random bits against general no-signaling adversaries. In both these research programs, a fundamental question arises: Can any measurements on quantum states realize the correlations present in pure extremal no-signaling boxes? Here, we answer this question in full generality showing that no nontrivial (not local realistic) extremal boxes of general no-signaling theories can be realized in quantum theory. We then explore some important consequences of this fact.

A Study of a Standard BIT Circuit.

DTIC Science & Technology

1977-02-01

IENDED BIT APPROACHES FOR QED MODULES AND APPLICATION OF THE ANALYTIC MEASURES 36 4.1 Built-In-Test for Memory Class Modules 37 4.1.1 Random Access...Implementation 68 4.1.5.5 Criti cal Parameters 68 4.1.5.6 QED Module Test Equipment Requirements 68 4.1.6 Application of Analytic Measures to the...Microprocessor BIT Techniques.. 121 4.2.9 Application of Analytic Measures to the Recommended BIT App roaches 125 4.2.10 Process Class BIT by Partial

Linewidth-tolerant real-time 40-Gbit/s 16-QAM self-homodyne detection using a pilot carrier and ISI suppression based on electronic digital processing.

PubMed

Nakamura, Moriya; Kamio, Yukiyoshi; Miyazaki, Tetsuya

2010-01-01

We experimentally demonstrate linewidth-tolerant real-time 40-Gbit/s(10-Gsymbol/s) 16-quadrature amplitude modulation. We achieved bit-error rates of <10(-9) using an external-cavity laser diode with a linewidth of 200 kHz and <10(-7) using a distributed-feedback laser diode with a linewidth of 30 MHz, thanks to the phase-noise canceling capability provided by self-homodyne detection using a pilot carrier. Pre-equalization based on digital signal processing was employed to suppress intersymbol interference caused by the limited-frequency bandwidth of electrical components.

Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms.

PubMed

Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B; Liu, Shih-Chii

2015-01-01

Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms

PubMed Central

Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B.; Liu, Shih-Chii

2015-01-01

Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time. PMID:26217169

Transmission performance of a wavelength and NRZ-to-RZ format conversion with pulsewidth tunability by combination of SOA- and fiber-based switches.

PubMed

Tan, Hung Nguyen; Matsuura, Motoharu; Kishi, Naoto

2008-11-10

An all-optical signal processing scheme coupling wavelength conversion and NRZ-to-RZ data format conversion with pulsewidth tunability into one by combination of SOA- and fiber-based switches, is experimentally demonstrated, and its transmission performance is investigated. An 1558 nm NRZ data signal is converted to RZ data format at 1546 nm with widely tunable pulsewidth from 20 % to 80 % duty cycle at the bit-rate of 10 Gb/s. The investigation on transmission performance of the converted RZ signals at each different pulsewidth is carried out over various standard single-mode fiber (SSMF) links up to 65 km long without dispersion compensation. The results clarify a significant improvement on transmission performance of converted signal in comparison with the conventional NRZ signal through tunable pulsewidth management and show the existence of an optimal pulsewidth for the RZ data format at each transmission distance with particular cumulative dispersion. The optimal pulsewidths of the converted RZ signal and its corresponding power penalties against the NRZ signal are also investigated in different SSMF links.

Direct match data flow machine apparatus and process for data driven computing

DOEpatents

Davidson, G.S.; Grafe, V.G.

1997-08-12

A data flow computer and method of computing are disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ``fire`` signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.

Direct match data flow machine apparatus and process for data driven computing

DOEpatents

Davidson, George S.; Grafe, Victor Gerald

1997-01-01

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Dependence of the bit error rate on the signal power and length of a single-channel coherent single-span communication line (100 Gbit s{sup -1}) with polarisation division multiplexing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gurkin, N V; Konyshev, V A; Novikov, A G

2015-01-31

We have studied experimentally and using numerical simulations and a phenomenological analytical model the dependences of the bit error rate (BER) on the signal power and length of a coherent single-span communication line with transponders employing polarisation division multiplexing and four-level phase modulation (100 Gbit s{sup -1} DP-QPSK format). In comparing the data of the experiment, numerical simulations and theoretical analysis, we have found two optimal powers: the power at which the BER is minimal and the power at which the fade margin in the line is maximal. We have derived and analysed the dependences of the BER on themore » optical signal power at the fibre line input and the dependence of the admissible input signal power range for implementation of the communication lines with a length from 30 – 50 km up to a maximum length of 250 km. (optical transmission of information)« less

Method and apparatus for high speed data acquisition and processing

DOEpatents

Ferron, J.R.

1997-02-11

A method and apparatus are disclosed for high speed digital data acquisition. The apparatus includes one or more multiplexers for receiving multiple channels of digital data at a low data rate and asserting a multiplexed data stream at a high data rate, and one or more FIFO memories for receiving data from the multiplexers and asserting the data to a real time processor. Preferably, the invention includes two multiplexers, two FIFO memories, and a 64-bit bus connecting the FIFO memories with the processor. Each multiplexer receives four channels of 14-bit digital data at a rate of up to 5 MHz per channel, and outputs a data stream to one of the FIFO memories at a rate of 20 MHz. The FIFO memories assert output data in parallel to the 64-bit bus, thus transferring 14-bit data values to the processor at a combined rate of 40 MHz. The real time processor is preferably a floating-point processor which processes 32-bit floating-point words. A set of mask bits is prestored in each 32-bit storage location of the processor memory into which a 14-bit data value is to be written. After data transfer from the FIFO memories, mask bits are concatenated with each stored 14-bit data value to define a valid 32-bit floating-point word. Preferably, a user can select any of several modes for starting and stopping direct memory transfers of data from the FIFO memories to memory within the real time processor, by setting the content of a control and status register. 15 figs.

Method and apparatus for high speed data acquisition and processing

DOEpatents

Ferron, John R.

1997-01-01

A method and apparatus for high speed digital data acquisition. The apparatus includes one or more multiplexers for receiving multiple channels of digital data at a low data rate and asserting a multiplexed data stream at a high data rate, and one or more FIFO memories for receiving data from the multiplexers and asserting the data to a real time processor. Preferably, the invention includes two multiplexers, two FIFO memories, and a 64-bit bus connecting the FIFO memories with the processor. Each multiplexer receives four channels of 14-bit digital data at a rate of up to 5 MHz per channel, and outputs a data stream to one of the FIFO memories at a rate of 20 MHz. The FIFO memories assert output data in parallel to the 64-bit bus, thus transferring 14-bit data values to the processor at a combined rate of 40 MHz. The real time processor is preferably a floating-point processor which processes 32-bit floating-point words. A set of mask bits is prestored in each 32-bit storage location of the processor memory into which a 14-bit data value is to be written. After data transfer from the FIFO memories, mask bits are concatenated with each stored 14-bit data value to define a valid 32-bit floating-point word. Preferably, a user can select any of several modes for starting and stopping direct memory transfers of data from the FIFO memories to memory within the real time processor, by setting the content of a control and status register.

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

Fed-batch hydrolysate addition and cell separation by settling in high cell density lignocellulosic ethanol fermentations on AFEX™ corn stover in the Rapid Bioconversion with Integrated recycling Technology process.

PubMed

Sarks, Cory; Jin, Mingjie; Balan, Venkatesh; Dale, Bruce E

2017-09-01

The Rapid Bioconversion with Integrated recycling Technology (RaBIT) process uses enzyme and yeast recycling to improve cellulosic ethanol production economics. The previous versions of the RaBIT process exhibited decreased xylose consumption using cell recycle for a variety of different micro-organisms. Process changes were tested in an attempt to eliminate the xylose consumption decrease. Three different RaBIT process changes were evaluated in this work including (1) shortening the fermentation time, (2) fed-batch hydrolysate addition, and (3) selective cell recycling using a settling method. Shorting the RaBIT fermentation process to 11 h and introducing fed-batch hydrolysate addition eliminated any xylose consumption decrease over ten fermentation cycles; otherwise, decreased xylose consumption was apparent by the third cell recycle event. However, partial removal of yeast cells during recycle was not economical when compared to recycling all yeast cells.

Digital codec for real-time processing of broadcast quality video signals at 1.8 bits/pixel

NASA Technical Reports Server (NTRS)

Shalkhauser, Mary JO; Whyte, Wayne A., Jr.

1989-01-01

The authors present the hardware implementation of a digital television bandwidth compression algorithm which processes standard NTSC (National Television Systems Committee) composite color television signals and produces broadcast-quality video in real time at an average of 1.8 b/pixel. The sampling rate used with this algorithm results in 768 samples over the active portion of each video line by 512 active video lines per video frame. The algorithm is based on differential pulse code modulation (DPCM), but additionally utilizes a nonadaptive predictor, nonuniform quantizer, and multilevel Huffman coder to reduce the data rate substantially below that achievable with straight DPCM. The nonadaptive predictor and multilevel Huffman coder combine to set this technique apart from prior-art DPCM encoding algorithms. The authors describe the data compression algorithm and the hardware implementation of the codec and provide performance results.

Σ-Δ modulator for a programmable gain, low-power, high-linearity automotive sensor interface

NASA Astrophysics Data System (ADS)

de la Rosa, Jose M.; Medeiro, Fernando; Perez-Verdu, Belen; del Rio, Rocio; Rodriguez-Vazquez, Angel

2003-04-01

Smart sensors play a critical role in modern automotive electronic systems, covering a wide range of data capturing functions and operating under adverse environmental conditions - temperature range of [-40¦C,175¦C]. In such sensors, the signal provided by transducers is composed of an offset voltage, which depends on the manufacturing process, and a low-frequency signal carrying the information. In practice, the offset voltage is subject to temperature variations, thus causing a shifting of the signal range to be measured. Therefore, the measuring circuit driving the sensor, normally formed by a low-noise preamplifier and an Analog-to-Digital Converter (ADC), must accommodate the complete range of possible offsets and real signals. In this scenario, the use of ADCs based on Sigma-Delta Modulators (SDMs) is convenient for several reasons. On the one hand, the noise-shaping performed by SDMs allows to achieve high resolution (16-17bits), in the band of interest (10-20kHz), with less power consumption than full Nyquist ADCs. On the other hand, the action of feedback renders SDMs very linear, and high-linearity is a must for automotive applications. Last but not least, the robustness of SDMs with respect to circuit imperfections make them suitable to include programmable gain without significant performance degradation. This feature allows to accommodate the complete range of possible offsets and information signals in a sensor interface with relaxed specifications for the preamplifier circuitry. This paper describes the design and implementation of a third-order cascade (2-1) SDM with programmable gain in a 0.35mm CMOS technology - the type of technology commonly employed for automotive applications (deep submicron is mostly employed for telecom). It is capable of handling signals up to 20-kHz bandwidth with 17-bit resolution. The programmable gain is implemented by a capacitor array whose unitary capacitors are connected or disconnected depending on the value of the selected gain. In order to relax the amplifier dynamics requirements as the modulator gain varies, switchable capacitor arrays have been used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. As a result, a dynamic range equal to 105 dB is obtained for all cases of the modulator gain, which corresponds to 17 bit resolution.

A Bit Stream Scalable Speech/Audio Coder Combining Enhanced Regular Pulse Excitation and Parametric Coding

NASA Astrophysics Data System (ADS)

Riera-Palou, Felip; den Brinker, Albertus C.

2007-12-01

This paper introduces a new audio and speech broadband coding technique based on the combination of a pulse excitation coder and a standardized parametric coder, namely, MPEG-4 high-quality parametric coder. After presenting a series of enhancements to regular pulse excitation (RPE) to make it suitable for the modeling of broadband signals, it is shown how pulse and parametric codings complement each other and how they can be merged to yield a layered bit stream scalable coder able to operate at different points in the quality bit rate plane. The performance of the proposed coder is evaluated in a listening test. The major result is that the extra functionality of the bit stream scalability does not come at the price of a reduced performance since the coder is competitive with standardized coders (MP3, AAC, SSC).

A microcomputer-based data acquisition system for ECG, body and ambient temperatures measurement during bathing.

PubMed

Uokawa, Y; Yonezawa, Y; Caldwell, W M; Hahn, A W

2000-01-01

A data acquisition system employing a low power 8 bit microcomputer has been developed for heart rate variability monitoring before, during and after bathing. The system consists of three integral chest electrodes, two temperature sensors, an instrumentation amplifier, a low power 8-bit single chip microcomputer (SMC) and a 4 MB compact flash memory (CFM). The ECG from the electrodes is converted to an 8-bit digital format at a 1 ms rate by an A/D converter in the SMC. Both signals from the body and ambient temperature sensors are converted to an 8-bit digital format every 1 second. These data are stored by the CFM. The system is powered by a rechargeable 3.6 V lithium battery. The 4 x 11 x 1 cm system is encapsulated in epoxy and silicone, yielding a total volume of 44 cc. The weight is 100 g.

Alsep data processing: How we processed Apollo Lunar Seismic Data

NASA Technical Reports Server (NTRS)

Latham, G. V.; Nakamura, Y.; Dorman, H. J.

1979-01-01

The Apollo lunar seismic station network gathered data continuously at a rate of 3 x 10 to the 8th power bits per day for nearly eight years until the termination in September, 1977. The data were processed and analyzed using a PDP-15 minicomputer. On the average, 1500 long-period seismic events were detected yearly. Automatic event detection and identification schemes proved unsuccessful because of occasional high noise levels and, above all, the risk of overlooking unusual natural events. The processing procedures finally settled on consist of first plotting all the data on a compressed time scale, visually picking events from the plots, transferring event data to separate sets of tapes and performing detailed analyses using the latter. Many problems remain especially for automatically processing extraterrestrial seismic signals.

Bread: CDC 7600 program that processes Spent Fuel Test Climax data

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hage, G.L.

BREAD will process a family of files copied from a data tape made by Hewlett-Packard equipment employed for data acquisition on the Spent Fuel Test-Climax at NTS. Tapes are delivered to Livermore approximately monthly. The process at this stage consists of four steps: read the binary files and convert from H-P 16-bit words to CDC 7600 60-bit words; check identification and data ranges; write the data in 6-bit ASCII (BCD) format, one data point per line; then sort the file by identifier and time.

Invariance of the bit error rate in the ancilla-assisted homodyne detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yoshida, Yuhsuke; Takeoka, Masahiro; Sasaki, Masahide

2010-11-15

We investigate the minimum achievable bit error rate of the discrimination of binary coherent states with the help of arbitrary ancillary states. We adopt homodyne measurement with a common phase of the local oscillator and classical feedforward control. After one ancillary state is measured, its outcome is referred to the preparation of the next ancillary state and the tuning of the next mixing with the signal. It is shown that the minimum bit error rate of the system is invariant under the following operations: feedforward control, deformations, and introduction of any ancillary state. We also discuss the possible generalization ofmore » the homodyne detection scheme.« less

A Versatile Multichannel Digital Signal Processing Module for Microcalorimeter Arrays

NASA Astrophysics Data System (ADS)

Tan, H.; Collins, J. W.; Walby, M.; Hennig, W.; Warburton, W. K.; Grudberg, P.

2012-06-01

Different techniques have been developed for reading out microcalorimeter sensor arrays: individual outputs for small arrays, and time-division or frequency-division or code-division multiplexing for large arrays. Typically, raw waveform data are first read out from the arrays using one of these techniques and then stored on computer hard drives for offline optimum filtering, leading not only to requirements for large storage space but also limitations on achievable count rate. Thus, a read-out module that is capable of processing microcalorimeter signals in real time will be highly desirable. We have developed multichannel digital signal processing electronics that are capable of on-board, real time processing of microcalorimeter sensor signals from multiplexed or individual pixel arrays. It is a 3U PXI module consisting of a standardized core processor board and a set of daughter boards. Each daughter board is designed to interface a specific type of microcalorimeter array to the core processor. The combination of the standardized core plus this set of easily designed and modified daughter boards results in a versatile data acquisition module that not only can easily expand to future detector systems, but is also low cost. In this paper, we first present the core processor/daughter board architecture, and then report the performance of an 8-channel daughter board, which digitizes individual pixel outputs at 1 MSPS with 16-bit precision. We will also introduce a time-division multiplexing type daughter board, which takes in time-division multiplexing signals through fiber-optic cables and then processes the digital signals to generate energy spectra in real time.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Fault-tolerant corrector/detector chip for high-speed data processing

DOEpatents

Andaleon, David D.; Napolitano, Jr., Leonard M.; Redinbo, G. Robert; Shreeve, William O.

1994-01-01

An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented.

Fault-tolerant corrector/detector chip for high-speed data processing

DOEpatents

Andaleon, D.D.; Napolitano, L.M. Jr.; Redinbo, G.R.; Shreeve, W.O.

1994-03-01

An internally fault-tolerant data error detection and correction integrated circuit device and a method of operating same is described. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented. 8 figures.

Associative architecture for image processing

NASA Astrophysics Data System (ADS)

Adar, Rutie; Akerib, Avidan

1997-09-01

This article presents a new generation in parallel processing architecture for real-time image processing. The approach is implemented in a real time image processor chip, called the XiumTM-2, based on combining a fully associative array which provides the parallel engine with a serial RISC core on the same die. The architecture is fully programmable and can be programmed to implement a wide range of color image processing, computer vision and media processing functions in real time. The associative part of the chip is based on patented pending methodology of Associative Computing Ltd. (ACL), which condenses 2048 associative processors, each of 128 'intelligent' bits. Each bit can be a processing bit or a memory bit. At only 33 MHz and 0.6 micron manufacturing technology process, the chip has a computational power of 3 billion ALU operations per second and 66 billion string search operations per second. The fully programmable nature of the XiumTM-2 chip enables developers to use ACL tools to write their own proprietary algorithms combined with existing image processing and analysis functions from ACL's extended set of libraries.

Suppressing flashes of items surrounding targets during calibration of a P300-based brain-computer interface improves performance

NASA Astrophysics Data System (ADS)

Frye, G. E.; Hauser, C. K.; Townsend, G.; Sellers, E. W.

2011-04-01

Since the introduction of the P300 brain-computer interface (BCI) speller by Farwell and Donchin in 1988, the speed and accuracy of the system has been significantly improved. Larger electrode montages and various signal processing techniques are responsible for most of the improvement in performance. New presentation paradigms have also led to improvements in bit rate and accuracy (e.g. Townsend et al (2010 Clin. Neurophysiol. 121 1109-20)). In particular, the checkerboard paradigm for online P300 BCI-based spelling performs well, has started to document what makes for a successful paradigm, and is a good platform for further experimentation. The current paper further examines the checkerboard paradigm by suppressing items which surround the target from flashing during calibration (i.e. the suppression condition). In the online feedback mode the standard checkerboard paradigm is used with a stepwise linear discriminant classifier derived from the suppression condition and one classifier derived from the standard checkerboard condition, counter-balanced. The results of this research demonstrate that using suppression during calibration produces significantly more character selections/min ((6.46) time between selections included) than the standard checkerboard condition (5.55), and significantly fewer target flashes are needed per selection in the SUP condition (5.28) as compared to the RCP condition (6.17). Moreover, accuracy in the SUP and RCP conditions remained equivalent (~90%). Mean theoretical bit rate was 53.62 bits/min in the suppression condition and 46.36 bits/min in the standard checkerboard condition (ns). Waveform morphology also showed significant differences in amplitude and latency.

Smart measurement system for resistive (bridge) or capacitive sensors

NASA Astrophysics Data System (ADS)

Wang, Guijie; Meijer, Gerard C. M.

1998-07-01

A low-cost smart measurement system for resistive (bridge) and capacitive sensors is presented and demonstrated. The measurement system consists of three main parts: the sensor element, a universal transducer interface (UTI) and a microcontroller. The UTI is a sensor-signal-to-time converter, based on a period-modulated oscillator, which is equipped with front-ends for many types of resistive (bridge) and capacitive sensors, and which generates a microcontroller-compatible output signal. The microcontroller performs data acquisition of the output signals from the interface UTI, controls the working status of the UTI for a specified application and communicates with a personal computer. Continuous auto-calibration of the offset and the gain of the complete system is applied to eliminate many nonidealities. Experimental results show that the accuracy and resolution are 14 bits and 16 bits, respectively, for a measurement time of about 100 ms.

A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications

PubMed Central

Chang, Chia-Lin; Chang, Chih-Wei; Huang, Hong-Yi; Hsu, Chen-Ming; Huang, Chia-Hsuan; Chiou, Jin-Chern; Luo, Ching-Hsing

2010-01-01

This work describes a power-efficient bio-potential acquisition device for long-term healthcare applications that is implemented using novel microelectromechanical dry electrodes (MDE) and a low power bio-potential processing chip. Using micromachining technology, an attempt is also made to enhance the sensing reliability and stability by fabricating a diamond-shaped MDE (DS-MDE) that has a satisfactory self-stability capability and superior electric conductivity when attached onto skin without any extra skin tissue injury technology. To acquire differential bio-potentials such as ECG signals, the proposed processing chip fabricated in a standard CMOS process has a high common mode rejection ratio (C.M.R.R.) differential amplifier and a 12-bit analog-to-digital converter (ADC). Use of the proposed system and integrate simple peripheral commercial devices can obtain the ECG signal efficiently without additional skin tissue injury and ensure continuous monitoring more than 70 hours with a 400 mAh battery. PMID:22399907

A power-efficient bio-potential acquisition device with DS-MDE sensors for long-term healthcare monitoring applications.

PubMed

Chang, Chia-Lin; Chang, Chih-Wei; Huang, Hong-Yi; Hsu, Chen-Ming; Huang, Chia-Hsuan; Chiou, Jin-Chern; Luo, Ching-Hsing

2010-01-01

This work describes a power-efficient bio-potential acquisition device for long-term healthcare applications that is implemented using novel microelectromechanical dry electrodes (MDE) and a low power bio-potential processing chip. Using micromachining technology, an attempt is also made to enhance the sensing reliability and stability by fabricating a diamond-shaped MDE (DS-MDE) that has a satisfactory self-stability capability and superior electric conductivity when attached onto skin without any extra skin tissue injury technology. To acquire differential bio-potentials such as ECG signals, the proposed processing chip fabricated in a standard CMOS process has a high common mode rejection ratio (C.M.R.R.) differential amplifier and a 12-bit analog-to-digital converter (ADC). Use of the proposed system and integrate simple peripheral commercial devices can obtain the ECG signal efficiently without additional skin tissue injury and ensure continuous monitoring more than 70 hours with a 400 mAh battery.

Reduction of ETS-VI Laser Communication Equipment Optical-Downlink Telemetry Collected During GOLD

NASA Technical Reports Server (NTRS)

Toyoshima, M.; Araki, K.; Arimoto, Y.; Toyoda, M.; Jeganathan, M.; Wilson, K.; Lesh, J. R.

1997-01-01

Free-space laser communications experiments were conducted between the laser communication equipment (LCE) on board the Japanese Engineering Test Satellite VI (ETS-VI) and the ground station located at the Table Mountain Facility (TMF) during late 1995 and early 1996. This article describes the on-line data reduction process used to decode LCE telemetry (called E2) downlinked on the optical carrier during the Ground/Orbiter Lasercomm Demonstration (GOLD) experiments. The LCE has the capability of transmitting real-time sensor and status information at 128 kbps by modulating the onboard diode laser. The optical downlink was detected on the ground, bit synchronized, and the resulting data stream stored on a data recorder. The recorded data were subsequently decoded by on-line data processing that included cross-correlation of the known telemetry data format and the downlink data stream. Signals obtained from the processing can be useful not only in evaluating the characteristics of the LCE but also in understanding uplink and downlink signal quality.

Development of gallium arsenide high-speed, low-power serial parallel interface modules: Executive summary

NASA Technical Reports Server (NTRS)

1988-01-01

Final report to NASA LeRC on the development of gallium arsenide (GaAS) high-speed, low power serial/parallel interface modules. The report discusses the development and test of a family of 16, 32 and 64 bit parallel to serial and serial to parallel integrated circuits using a self aligned gate MESFET technology developed at the Honeywell Sensors and Signal Processing Laboratory. Lab testing demonstrated 1.3 GHz clock rates at a power of 300 mW. This work was accomplished under contract number NAS3-24676.

SIGPROC: Pulsar Signal Processing Programs

NASA Astrophysics Data System (ADS)

Lorimer, D. R.

2011-07-01

SIGPROC is a package designed to standardize the initial analysis of the many types of fast-sampled pulsar data. Currently recognized machines are the Wide Band Arecibo Pulsar Processor (WAPP), the Penn State Pulsar Machine (PSPM), the Arecibo Observatory Fourier Transform Machine (AOFTM), the Berkeley Pulsar Processors (BPP), the Parkes/Jodrell 1-bit filterbanks (SCAMP) and the filterbank at the Ooty radio telescope (OOTY). The SIGPROC tools should help users look at their data quickly, without the need to write (yet) another routine to read data or worry about big/little endian compatibility (byte swapping is handled automatically).

EFQPSK Versus CERN: A Comparative Study

NASA Technical Reports Server (NTRS)

Borah, Deva K.; Horan, Stephen

2001-01-01

This report presents a comparative study on Enhanced Feher's Quadrature Phase Shift Keying (EFQPSK) and Constrained Envelope Root Nyquist (CERN) techniques. These two techniques have been developed in recent times to provide high spectral and power efficiencies under nonlinear amplifier environment. The purpose of this study is to gain insights into these techniques and to help system planners and designers with an appropriate set of guidelines for using these techniques. The comparative study presented in this report relies on effective simulation models and procedures. Therefore, a significant part of this report is devoted to understanding the mathematical and simulation models of the techniques and their set-up procedures. In particular, mathematical models of EFQPSK and CERN, effects of the sampling rate in discrete time signal representation, and modeling of nonlinear amplifiers and predistorters have been considered in detail. The results of this study show that both EFQPSK and CERN signals provide spectrally efficient communications compared to filtered conventional linear modulation techniques when a nonlinear power amplifier is used. However, there are important differences. The spectral efficiency of CERN signals, with a small amount of input backoff, is significantly better than that of EFQPSK signals if the nonlinear amplifier is an ideal clipper. However, to achieve such spectral efficiencies with a practical nonlinear amplifier, CERN processing requires a predistorter which effectively translates the amplifier's characteristics close to those of an ideal clipper. Thus, the spectral performance of CERN signals strongly depends on the predistorter. EFQPSK signals, on the other hand, do not need such predistorters since their spectra are almost unaffected by the nonlinear amplifier, Ibis report discusses several receiver structures for EFQPSK signals. It is observed that optimal receiver structures can be realized for both coded and uncoded EFQPSK signals with not too much increase in computational complexity. When a nonlinear amplifier is used, the bit error rate (BER) performance of the CERN signals with a matched filter receiver is found to be more than one decibel (dB) worse compared to the bit error performance of EFQPSK signals. Although channel coding is found to provide BER performance improvement for both EFQPSK and CERN signals, the performance of EFQPSK signals remains better than that of CERN. Optimal receiver structures for CERN signals with nonlinear equalization is left as a possible future work. Based on the numerical results, it is concluded that, in nonlinear channels, CERN processing leads towards better bandwidth efficiency with a compromise in power efficiency. Hence for bandwidth efficient communications needs, CERN is a good solution provided effective adaptive predistorters can be realized. On the other hand, EFQPSK signals provide a good power efficient solution with a compromise in band width efficiency.

Development and testing of a Mudjet-augmented PDC bit.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Alan; Chahine, Georges; Raymond, David Wayne

2006-01-01

This report describes a project to develop technology to integrate passively pulsating, cavitating nozzles within Polycrystalline Diamond Compact (PDC) bits for use with conventional rig pressures to improve the rock-cutting process in geothermal formations. The hydraulic horsepower on a conventional drill rig is significantly greater than that delivered to the rock through bit rotation. This project seeks to leverage this hydraulic resource to extend PDC bits to geothermal drilling.

Reception of Multiple Telemetry Signals via One Dish Antenna

NASA Technical Reports Server (NTRS)

Mukai, Ryan; Vilnrotter, Victor

2010-01-01

A microwave aeronautical-telemetry receiver system includes an antenna comprising a seven-element planar array of receiving feed horns centered at the focal point of a paraboloidal dish reflector that is nominally aimed at a single aircraft or at multiple aircraft flying in formation. Through digital processing of the signals received by the seven feed horns, the system implements a method of enhanced cancellation of interference, such that it becomes possible to receive telemetry signals in the same frequency channel simultaneously from either or both of two aircraft at slightly different angular positions within the field of view of the antenna, even in the presence of multipath propagation. The present system is an advanced version of the system described in Spatio- Temporal Equalizer for a Receiving-Antenna Feed Array NPO-43077, NASA Tech Briefs, Vol. 34, No. 2 (February 2010), page 32. To recapitulate: The radio-frequency telemetry signals received by the seven elements of the array are digitized, converted to complex baseband form, and sent to a spatio-temporal equalizer that consists mostly of a bank of seven adaptive finite-impulse-response (FIR) filters (one for each element in the array) plus a unit that sums the outputs of the filters. The combination of the spatial diversity of the feedhorn array and the temporal diversity of the filter bank affords better multipath suppression performance than is achievable by means of temporal equalization alone. The FIR filter bank adapts itself in real time to enable reception of telemetry at a low bit error rate, even in the presence of frequency-selective multipath propagation like that commonly found at flight-test ranges. The combination of the array and the filter bank makes it possible to constructively add multipath incoming signals to the corresponding directly arriving signals, thereby enabling reductions in telemetry bit-error rates.

A digitally assisted, signal folding neural recording amplifier.

PubMed

Chen, Yi; Basu, Arindam; Liu, Lei; Zou, Xiaodan; Rajkumar, Ramamoorthy; Dawe, Gavin Stewart; Je, Minkyu

2014-08-01

A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.

Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

NASA Technical Reports Server (NTRS)

Gerber, Scott S.; Hammond, Ahmad; Elbuluk, Malik E.; Patterson, Richard L.; Overton, Eric; Ghaffarian, Reza; Ramesham, Rajeshuni; Agarwal, Shri G.

2001-01-01

Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

NASA Astrophysics Data System (ADS)

Yijun, Song; Wenyuan, Li

2014-06-01

A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 μm CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which canperform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within ±0.28 LSB and ±0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 mW.

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

NASA Technical Reports Server (NTRS)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Impact of ADC parameters on linear optical sampling systems

NASA Astrophysics Data System (ADS)

Nguyen, Trung-Hien; Gay, Mathilde; Gomez-Agis, Fausto; Lobo, Sébastien; Sentieys, Olivier; Simon, Jean-Claude; Peucheret, Christophe; Bramerie, Laurent

2017-11-01

Linear optical sampling (LOS), based on the coherent photodetection of an optical signal under test with a low repetition-rate signal originating from a pulsed local oscillator (LO), enables the characterization of the temporal electric field of optical sources. Thanks to this technique, low-speed photodetectors and analog-to-digital converters (ADCs) can be integrated in the LOS system providing a cost-effective tool for characterizing high-speed signals. However, the impact of photodetector and ADC parameters on such LOS systems has not been explored in detail so far. These parameters, including the integration time of the track-and-hold function, the effective number of bits (ENOB) of the ADC, as well as the combined limited bandwidth of the photodetector and ADC are experimentally and numerically investigated in a LOS system for the first time. More specifically, by reconstructing 10-Gbit/s non-return-to-zero on-off keying (NRZ-OOK) and 10-Gbaud NRZ-quadrature phase-shift-keying (QPSK) signals, it is shown that a short integration time provides a better recovered signal fidelity. Furthermore, an ENOB of 6 bits and an ADC bandwidth normalized to the sampling rate of 2.8 are found to be sufficient in order to reliably monitor the considered signals.

Experimental research of adaptive OFDM and OCT precoding with a high SE for VLLC system

NASA Astrophysics Data System (ADS)

Liu, Shuang-ao; He, Jing; Chen, Qinghui; Deng, Rui; Zhou, Zhihua; Chen, Shenghai; Chen, Lin

2017-09-01

In this paper, an adaptive orthogonal frequency division multiplexing (OFDM) modulation scheme with 128/64/32/16-quadrature amplitude modulation (QAM) and orthogonal circulant matrix transform (OCT) precoding is proposed and experimentally demonstrated for a visible laser light communication (VLLC) system with a cost-effective 450-nm blue-light laser diode (LD). The performance of OCT precoding is compared with conventional the adaptive Discrete Fourier Transform-spread (DFT-spread) OFDM scheme, 32 QAM OCT precoding OFDM scheme, 64 QAM OCT precoding OFDM scheme and adaptive OCT precoding OFDM scheme. The experimental results show that OCT precoding can achieve a relatively flat signal-to-noise ratio (SNR) curve, and it can provide performance improvement in bit error rate (BER). Furthermore, the BER of the proposed OFDM signal with a raw bit rate 5.04 Gb/s after 5-m free space transmission is less than 20% of soft-decision forward error correlation (SD-FEC) threshold of 2.4 × 10-2, and the spectral efficiency (SE) of 4.2 bit/s/Hz can be successfully achieved.

Word timing recovery in direct detection optical PPM communication systems with avalanche photodiodes using a phase lock loop

NASA Technical Reports Server (NTRS)

Sun, Xiaoli; Davidson, Frederic M.

1990-01-01

A technique for word timing recovery in a direct-detection optical PPM communication system is described. It tracks on back-to-back pulse pairs in the received random PPM data sequences with the use of a phase locked loop. The experimental system consisted of an 833-nm AlGaAs laser diode transmitter and a silicon avalanche photodiode photodetector, and it used Q = 4 PPM signaling at source data rate 25 Mb/s. The mathematical model developed to describe system performance is shown to be in good agreement with the experimental measurements. Use of this recovered PPM word clock with a slot clock recovery system caused no measurable penalty in receiver sensitivity. The completely self-synchronized receiver was capable of acquiring and maintaining both slot and word synchronizations for input optical signal levels as low as 20 average detected photons per information bit. The receiver achieved a bit error probability of 10 to the -6th at less than 60 average detected photons per information bit.

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

2015-06-01

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

The selection of Lorenz laser parameters for transmission in the SMF 3rd transmission window

NASA Astrophysics Data System (ADS)

Gajda, Jerzy K.; Niesterowicz, Andrzej; Zeglinski, Grzegorz

2003-10-01

The work presents simulation of transmission line results with the fiber standard ITU-T G.652. The parameters of Lorenz laser decide about electrical signal parameters like eye pattern, jitter, BER, S/N, Q-factor, scattering diagram. For a short line lasers with linewidth larger than 100MHz can be used. In the paper cases for 10 Gbit/s and 40 Gbit/s transmission and the fiber length 30km, 50km, and 70km are calculated. The average open eye patterns were 1*10-5-120*10-5. The Q factor was 10-23dB. In calcuations the bit error rate (BER) was 10-40-10-4. If the bandwidth of Lorenz laser increases from 10 MHz to 500MHz a distance of transmission decrease from 70km to 30km. Very important for transmission distance is a rate bit of transmitter. If a bit rate increase from 10Gbit/s to 40 Gbit/s, the transmission distance for the signal mode fiber G.652 will decrease from 70km to 5km.

Resolution-Adaptive Hybrid MIMO Architectures for Millimeter Wave Communications

NASA Astrophysics Data System (ADS)

Choi, Jinseok; Evans, Brian L.; Gatherer, Alan

2017-12-01

In this paper, we propose a hybrid analog-digital beamforming architecture with resolution-adaptive ADCs for millimeter wave (mmWave) receivers with large antenna arrays. We adopt array response vectors for the analog combiners and derive ADC bit-allocation (BA) solutions in closed form. The BA solutions reveal that the optimal number of ADC bits is logarithmically proportional to the RF chain's signal-to-noise ratio raised to the 1/3 power. Using the solutions, two proposed BA algorithms minimize the mean square quantization error of received analog signals under a total ADC power constraint. Contributions of this paper include 1) ADC bit-allocation algorithms to improve communication performance of a hybrid MIMO receiver, 2) approximation of the capacity with the BA algorithm as a function of channels, and 3) a worst-case analysis of the ergodic rate of the proposed MIMO receiver that quantifies system tradeoffs and serves as the lower bound. Simulation results demonstrate that the BA algorithms outperform a fixed-ADC approach in both spectral and energy efficiency, and validate the capacity and ergodic rate formula. For a power constraint equivalent to that of fixed 4-bit ADCs, the revised BA algorithm makes the quantization error negligible while achieving 22% better energy efficiency. Having negligible quantization error allows existing state-of-the-art digital beamformers to be readily applied to the proposed system.

Spaceborne synthetic aperture radar signal processing using FPGAs

NASA Astrophysics Data System (ADS)

Sugimoto, Yohei; Ozawa, Satoru; Inaba, Noriyasu

2017-10-01

Synthetic Aperture Radar (SAR) imagery requires image reproduction through successive signal processing of received data before browsing images and extracting information. The received signal data records of the ALOS-2/PALSAR-2 are stored in the onboard mission data storage and transmitted to the ground. In order to compensate the storage usage and the capacity of transmission data through the mission date communication networks, the operation duty of the PALSAR-2 is limited. This balance strongly relies on the network availability. The observation operations of the present spaceborne SAR systems are rigorously planned by simulating the mission data balance, given conflicting user demands. This problem should be solved such that we do not have to compromise the operations and the potential of the next-generation spaceborne SAR systems. One of the solutions is to compress the SAR data through onboard image reproduction and information extraction from the reproduced images. This is also beneficial for fast delivery of information products and event-driven observations by constellation. The Emergence Studio (Sōhatsu kōbō in Japanese) with Japan Aerospace Exploration Agency is developing evaluation models of FPGA-based signal processing system for onboard SAR image reproduction. The model, namely, "Fast L1 Processor (FLIP)" developed in 2016 can reproduce a 10m-resolution single look complex image (Level 1.1) from ALOS/PALSAR raw signal data (Level 1.0). The processing speed of the FLIP at 200 MHz results in twice faster than CPU-based computing at 3.7 GHz. The image processed by the FLIP is no way inferior to the image processed with 32-bit computing in MATLAB.

Massively parallel processor computer

NASA Technical Reports Server (NTRS)

Fung, L. W. (Inventor)

1983-01-01

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Quantization error of CCD cameras and their influence on phase calculation in fringe pattern analysis.

PubMed

Skydan, Oleksandr A; Lilley, Francis; Lalor, Michael J; Burton, David R

2003-09-10

We present an investigation into the phase errors that occur in fringe pattern analysis that are caused by quantization effects. When acquisition devices with a limited value of camera bit depth are used, there are a limited number of quantization levels available to record the signal. This may adversely affect the recorded signal and adds a potential source of instrumental error to the measurement system. Quantization effects also determine the accuracy that may be achieved by acquisition devices in a measurement system. We used the Fourier fringe analysis measurement technique. However, the principles can be applied equally well for other phase measuring techniques to yield a phase error distribution that is caused by the camera bit depth.

Design and implementation of a wireless (Bluetooth) four channel bio-instrumentation amplifier and digital data acquisition device with user-selectable gain, frequency, and driven reference.

PubMed

Cosmanescu, Alin; Miller, Benjamin; Magno, Terence; Ahmed, Assad; Kremenic, Ian

2006-01-01

A portable, multi-purpose Bio-instrumentation Amplifier and Data AcQuisition device (BADAQ) capable of measuring and transmitting EMG and EKG signals wirelessly via Bluetooth is designed and implemented. Common topologies for instrumentation amplifiers and filters are used and realized with commercially available, low-voltage, high precision operational amplifiers. An 8-bit PIC microcontroller performs 10-bit analog-to-digital conversion of the amplified and filtered signals and controls a Bluetooth transceiver capable of wirelessly transmitting the data to any Bluetooth enabled device. Electrical isolation between patient/subject, circuitry, and ancillary equipment is achieved by optocoupling components. The design focuses on simplicity, portability, and affordability.

Low-power silicon-organic hybrid (SOH) modulators for advanced modulation formats.

PubMed

Lauermann, M; Palmer, R; Koeber, S; Schindler, P C; Korn, D; Wahlbrink, T; Bolten, J; Waldow, M; Elder, D L; Dalton, L R; Leuthold, J; Freude, W; Koos, C

2014-12-01

We demonstrate silicon-organic hybrid (SOH) electro-optic modulators that enable quadrature phase-shift keying (QPSK) and 16-state quadrature amplitude modulation (16QAM) with high signal quality and record-low energy consumption. SOH integration combines highly efficient electro-optic organic materials with conventional silicon-on-insulator (SOI) slot waveguides, and allows to overcome the intrinsic limitations of silicon as an optical integration platform. We demonstrate QPSK and 16QAM signaling at symbol rates of 28 GBd with peak-to-peak drive voltages of 0.6 V(pp). For the 16QAM experiment at 112 Gbit/s, we measure a bit-error ratio of 5.1 × 10⁻⁵ and a record-low energy consumption of only 19 fJ/bit.

Deformation Recording Process In Polymer-Metal Bilayers And Its Use For Optical Storage

NASA Astrophysics Data System (ADS)

Cornet, Jean A.

1983-11-01

A non-antireflective polymer-metal bilayer structure, encapsulated inside a closed cons-truction/is used for digital data storage in the Thomson-CSF Gigadisc. In this paper, a simple model is presented for microdeformation recording in the medium. This model enables a good understanding of the readout signal as a function of the recording power and leads to some practical consequences. Useful polymers and metallic layers are identified and the disc performance is reported. It is shown that recording using laser diodes can be performed at bit rate up to 14 Mbits.s-1 with a laser power of 7 mW at the disc entry face, in case of a 1200 rpm disc speed. Moreover a working range of 4 mW, as defined by a 3 dB attenuation, is demonstrated. Discs from pilot production exhibit raw bit error rates at the level of 2.10-5. For usual environmental conditions, the disc behaviour is compatible with shelf-and archival life at scale of 10 years. Finally, the processes for both layers deposition and disc construction are easy and cost effective. It is concluded that Giaadisc can successfully enter today the market place.

On phaser-based processing of impulse radio UWB over fiber systems employing SOA

NASA Astrophysics Data System (ADS)

Taki, H.; Azou, S.; Hamie, A.; Al Housseini, A.; Alaeddine, A.; Sharaiha, A.

2017-07-01

In this study, we adopt a phaser-based processing to enhance the performance of impulse radio over fiber system utilizing SOA. The amplifier has been placed at a distance in the optical link, so as to extend the coverage area of proposed transceiver. Operating in the linear or saturation region for SOA, adds ASE noise or strong nonlinearities acting on the propagated pulses, respectively. Both lead to a degradation in the power efficiency and bit error rate performance. By applying up and down analog chirping technique, we have reduced the ASE power and nonlinearity simultaneously. Based on the 5th Gaussian pulse and Abraha's combination of doublets, a significant improvement has been achieved at extremely low and high input powers entering the amplifier (<-15 dBm and 0 dBm), recording a very good bit error rate performance and power efficiency. Better signal quality was observed after photo-detector, due to the fact that waveforms with lower frequency components are less affected by SOA nonlinearity. Our scheme has proved to be effective for 1 Gbps OOK and 0.5 Gbps PPM transmissions, while reaching a distance of 160 km in the optical fiber.

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

Quantization of Gaussian samples at very low SNR regime in continuous variable QKD applications

NASA Astrophysics Data System (ADS)

Daneshgaran, Fred; Mondin, Marina

2016-09-01

The main problem for information reconciliation in continuous variable Quantum Key Distribution (QKD) at low Signal to Noise Ratio (SNR) is quantization and assignment of labels to the samples of the Gaussian Random Variables (RVs) observed at Alice and Bob. Trouble is that most of the samples, assuming that the Gaussian variable is zero mean which is de-facto the case, tend to have small magnitudes and are easily disturbed by noise. Transmission over longer and longer distances increases the losses corresponding to a lower effective SNR exasperating the problem. This paper looks at the quantization problem of the Gaussian samples at very low SNR regime from an information theoretic point of view. We look at the problem of two bit per sample quantization of the Gaussian RVs at Alice and Bob and derive expressions for the mutual information between the bit strings as a result of this quantization. The quantization threshold for the Most Significant Bit (MSB) should be chosen based on the maximization of the mutual information between the quantized bit strings. Furthermore, while the LSB string at Alice and Bob are balanced in a sense that their entropy is close to maximum, this is not the case for the second most significant bit even under optimal threshold. We show that with two bit quantization at SNR of -3 dB we achieve 75.8% of maximal achievable mutual information between Alice and Bob, hence, as the number of quantization bits increases beyond 2-bits, the number of additional useful bits that can be extracted for secret key generation decreases rapidly. Furthermore, the error rates between the bit strings at Alice and Bob at the same significant bit level are rather high demanding very powerful error correcting codes. While our calculations and simulation shows that the mutual information between the LSB at Alice and Bob is 0.1044 bits, that at the MSB level is only 0.035 bits. Hence, it is only by looking at the bits jointly that we are able to achieve a mutual information of 0.2217 bits which is 75.8% of maximum achievable. The implication is that only by coding both MSB and LSB jointly can we hope to get close to this 75.8% limit. Hence, non-binary codes are essential to achieve acceptable performance.

Fast-Acquisition/Weak-Signal-Tracking GPS Receiver for HEO

NASA Technical Reports Server (NTRS)

Wintemitz, Luke; Boegner, Greg; Sirotzky, Steve

2004-01-01

A report discusses the technical background and design of the Navigator Global Positioning System (GPS) receiver -- . a radiation-hardened receiver intended for use aboard spacecraft. Navigator is capable of weak signal acquisition and tracking as well as much faster acquisition of strong or weak signals with no a priori knowledge or external aiding. Weak-signal acquisition and tracking enables GPS use in high Earth orbits (HEO), and fast acquisition allows for the receiver to remain without power until needed in any orbit. Signal acquisition and signal tracking are, respectively, the processes of finding and demodulating a signal. Acquisition is the more computationally difficult process. Previous GPS receivers employ the method of sequentially searching the two-dimensional signal parameter space (code phase and Doppler). Navigator exploits properties of the Fourier transform in a massively parallel search for the GPS signal. This method results in far faster acquisition times [in the lab, 12 GPS satellites have been acquired with no a priori knowledge in a Low-Earth-Orbit (LEO) scenario in less than one second]. Modeling has shown that Navigator will be capable of acquiring signals down to 25 dB-Hz, appropriate for HEO missions. Navigator is built using the radiation-hardened ColdFire microprocessor and housing the most computationally intense functions in dedicated field-programmable gate arrays. The high performance of the algorithm and of the receiver as a whole are made possible by optimizing computational efficiency and carefully weighing tradeoffs among the sampling rate, data format, and data-path bit width.

Eliminating ambiguity in digital signals

NASA Technical Reports Server (NTRS)

Weber, W. J., III

1979-01-01

Multiamplitude minimum shift keying (mamsk) transmission system, method of differential encoding overcomes problem of ambiguity associated with advanced digital-transmission techniques with little or no penalty in transmission rate, error rate, or system complexity. Principle of method states, if signal points are properly encoded and decoded, bits are detected correctly, regardless of phase ambiguities.

Direct digital conversion detector technology

NASA Astrophysics Data System (ADS)

Mandl, William J.; Fedors, Richard

1995-06-01

Future imaging sensors for the aerospace and commercial video markets will depend on low cost, high speed analog-to-digital (A/D) conversion to efficiently process optical detector signals. Current A/D methods place a heavy burden on system resources, increase noise, and limit the throughput. This paper describes a unique method for incorporating A/D conversion right on the focal plane array. This concept is based on Sigma-Delta sampling, and makes optimum use of the active detector real estate. Combined with modern digital signal processors, such devices will significantly increase data rates off the focal plane. Early conversion to digital format will also decrease the signal susceptibility to noise, lowering the communications bit error rate. Computer modeling of this concept is described, along with results from several simulation runs. A potential application for direct digital conversion is also reviewed. Future uses for this technology could range from scientific instruments to remote sensors, telecommunications gear, medical diagnostic tools, and consumer products.

Effect of second harmonic in pulse-width-modulation-based DAC for feedback of digital fluxgate magnetometer

NASA Astrophysics Data System (ADS)

Belyayev, Serhiy; Ivchenko, Nickolay

2018-04-01

Digital fluxgate magnetometers employ processing of the measured pickup signal to produce the value of the compensation current. Using pulse-width modulation with filtering for digital to analog conversion is a convenient approach, but it can introduce an intrinsic source of nonlinearity, which we discuss in this design note. A code shift of one least significant bit changes the second harmonic content of the pulse train, which feeds into the pick-up signal chain despite the heavy filtering. This effect produces a code-dependent nonlinearity. This nonlinearity can be overcome by the specific design of the timing of the pulse train signal. The second harmonic is suppressed if the first and third quarters of the excitation period pulse train are repeated in the second and fourth quarters. We demonstrate this principle on a digital magnetometer, achieving a magnetometer noise level corresponding to that of the sensor itself.

Integrated-Circuit Pseudorandom-Number Generator

NASA Technical Reports Server (NTRS)

Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

1992-01-01

Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

PDC bit hydraulics design, profile are key to reducing balling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hariharan, P.R.; Azar, J.J.

1996-12-09

Polycrystalline diamond compact (PDC) bits with a parabolic profile and bladed hydraulic design have a lesser tendency to ball during drilling of reactive shales. PDC bits with ribbed or open-face hydraulic designs and those with flat or rounded profiles tended to ball more often in the bit balling experiments conducted. Experimental work also indicates that PDC hydraulic design seems to have a greater influence on bit balling tendency compared to bit profile design. There are five main factors that affect bit balling: formation type, drilling fluid, drilling hydraulics, bit design, and confining pressures. An equation for specific energy showed thatmore » it could be used to describe the efficiency of the drilling process by examining the amount of energy spent in drilling a unit volume of rock. This concept of specific energy has been used herein to correlate with the parameter Rd, a parameter to quantify the degree of balling.« less

Completion processing for data communications instructions

DOEpatents

Blocksome, Michael A.; Kumar, Sameer; Jeffrey, Parker J.

2014-06-10

Completion processing of data communications instructions in a distributed computing environment with computers coupled for data communications through communications adapters and an active messaging interface (`AMI`), injecting for data communications instructions into slots in an injection FIFO buffer a transfer descriptor, at least some of the instructions specifying callback functions; injecting a completion descriptor for each instruction that specifies a callback function into an injection FIFO buffer slot having a corresponding slot in a pending callback list; listing in the pending callback list callback functions specified by data communications instructions; processing each descriptor in the injection FIFO buffer, setting a bit in a completion bit mask corresponding to the slot in the FIFO where the completion descriptor was injected; and calling by the AMI any callback functions in the pending callback list as indicated by set bits in the completion bit mask.

Reducing Bits in Electrodeposition Process of Commercial Vehicle - A Case Study

NASA Astrophysics Data System (ADS)

Rahim, Nabiilah Ab; Hamedon, Zamzuri; Mohd Turan, Faiz; Iskandar, Ismed

2016-02-01

Painting process is critical in commercial vehicle manufacturing process for protection and decorative. The good quality on painted body is important to reduce repair cost and achieve customer satisfaction. In order to achieve the good quality, it is important to reduce the defect at the first process in painting process which is electrodeposition process. The Pareto graph and cause and effect diagram in the seven QC tools is utilized to reduce the electrodeposition defects. The main defects in the electrodeposition process in this case study are the bits. The 55% of the bits are iron filings. The iron filings which come from the metal assembly process at the body shop are minimised by controlling the spot welding parameter, defect control and standard body cleaning process. However the iron filings are still remained on the body and carry over to the paint shop. The remained iron filings on the body are settled inside the dipping tank and removed by filtration system and magnetic separation. The implementation of filtration system and magnetic separation improved 27% of bits and reduced 42% of sanding man hour with a total saving of RM38.00 per unit.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Application of wavelet filtering and Barker-coded pulse compression hybrid method to air-coupled ultrasonic testing

NASA Astrophysics Data System (ADS)

Zhou, Zhenggan; Ma, Baoquan; Jiang, Jingtao; Yu, Guang; Liu, Kui; Zhang, Dongmei; Liu, Weiping

2014-10-01

Air-coupled ultrasonic testing (ACUT) technique has been viewed as a viable solution in defect detection of advanced composites used in aerospace and aviation industries. However, the giant mismatch of acoustic impedance in air-solid interface makes the transmission efficiency of ultrasound low, and leads to poor signal-to-noise (SNR) ratio of received signal. The utilisation of signal-processing techniques in non-destructive testing is highly appreciated. This paper presents a wavelet filtering and phase-coded pulse compression hybrid method to improve the SNR and output power of received signal. The wavelet transform is utilised to filter insignificant components from noisy ultrasonic signal, and pulse compression process is used to improve the power of correlated signal based on cross-correction algorithm. For the purpose of reasonable parameter selection, different families of wavelets (Daubechies, Symlet and Coiflet) and decomposition level in discrete wavelet transform are analysed, different Barker codes (5-13 bits) are also analysed to acquire higher main-to-side lobe ratio. The performance of the hybrid method was verified in a honeycomb composite sample. Experimental results demonstrated that the proposed method is very efficient in improving the SNR and signal strength. The applicability of the proposed method seems to be a very promising tool to evaluate the integrity of high ultrasound attenuation composite materials using the ACUT.

Quasi-elastic light scattering: Signal storage, correlation, and spectrum analysis under control of an 8-bit microprocessor

NASA Astrophysics Data System (ADS)

Glatter, Otto; Fuchs, Heribert; Jorde, Christian; Eigner, Wolf-Dieter

1987-03-01

The microprocessor of an 8-bit PC system is used as a central control unit for the acquisition and evaluation of data from quasi-elastic light scattering experiments. Data are sampled with a width of 8 bits under control of the CPU. This limits the minimum sample time to 20 μs. Shorter sample times would need a direct memory access channel. The 8-bit CPU can address a 64-kbyte RAM without additional paging. Up to 49 000 sample points can be measured without interruption. After storage, a correlation function or a power spectrum can be calculated from such a primary data set. Furthermore access is provided to the primary data for stability control, statistical tests, and for comparison of different evaluation methods for the same experiment. A detailed analysis of the signal (histogram) and of the effect of overflows is possible and shows that the number of pulses but not the number of overflows determines the error in the result. The correlation function can be computed with reasonable accuracy from data with a mean pulse rate greater than one, the power spectrum needs a three times higher pulse rate for convergence. The statistical accuracy of the results from 49 000 sample points is of the order of a few percent. Additional averages are necessary to improve their quality. The hardware extensions for the PC system are inexpensive. The main disadvantage of the present system is the high minimum sampling time of 20 μs and the fact that the correlogram or the power spectrum cannot be computed on-line as it can be done with hardware correlators or spectrum analyzers. These shortcomings and the storage size restrictions can be removed with a faster 16/32-bit CPU.

Tolerance of the frequency deviation of LO sources at a MIMO system

NASA Astrophysics Data System (ADS)

Xiao, Jiangnan; Li, Xingying; Zhang, Zirang; Xu, Yuming; Chen, Long; Yu, Jianjun

2015-11-01

We analyze and simulate the tolerance of frequency offset at a W-band optical-wireless transmission system. The transmission system adopts optical polarization division multiplexing (PDM), and multiple-input multiple-output (MIMO) reception. The transmission signal adopts optical quadrature phase shift keying (QPSK) modulation, and the generation of millimeter-wave is based on the optical heterodyning technique. After 20-km single-mode fiber-28 (SMF-28) transmission, tens of Gb/s millimeter-wave signal is delivered. At the receiver, two millimeter-wave signals are down-converted into electrical intermediate-frequency (IF) signals in the analog domain by mixing with two electrical local oscillators (LOs) with different frequencies. We investigate the different frequency LO effect on the 2×2 MIMO system performance for the first time, finding that the process during DSP of implementing frequency offset estimation (FOE) before cascaded multi-modulus-algorithm (CMMA) equalization can get rid of the inter-channel interference (ICI) and improve system bit-error-ratio (BER) performance in this type of transmission system.

Super-resolution technique for CW lidar using Fourier transform reordering and Richardson-Lucy deconvolution.

PubMed

Campbell, Joel F; Lin, Bing; Nehrir, Amin R; Harrison, F Wallace; Obland, Michael D

2014-12-15

An interpolation method is described for range measurements of high precision altimetry with repeating intensity modulated continuous wave (IM-CW) lidar waveforms using binary phase shift keying (BPSK), where the range profile is determined by means of a cross-correlation between the digital form of the transmitted signal and the digitized return signal collected by the lidar receiver. This method uses reordering of the array elements in the frequency domain to convert a repeating synthetic pulse signal to single highly interpolated pulse. This is then enhanced further using Richardson-Lucy deconvolution to greatly enhance the resolution of the pulse. We show the sampling resolution and pulse width can be enhanced by about two orders of magnitude using the signal processing algorithms presented, thus breaking the fundamental resolution limit for BPSK modulation of a particular bandwidth and bit rate. We demonstrate the usefulness of this technique for determining cloud and tree canopy thicknesses far beyond this fundamental limit in a lidar not designed for this purpose.

VLC-beacon detection with an under-sampled ambient light sensor

NASA Astrophysics Data System (ADS)

Green, Jacob; Pérez-Olivas, Huetzin; Martínez-Díaz, Saúl; García-Márquez, Jorge; Domínguez-González, Carlos; Santiago-Montero, Raúl; Guan, Hongyu; Rozenblat, Marc; Topsu, Suat

2017-08-01

LEDs will replace in a near future the current worldwide lighting mainly due to their low production-cost and energy-saving assets. Visible light communications (VLC) will turn gradually the existing lighting network into a communication network. Nowadays VLC transceivers can be found in some commercial centres in Europe; some of them broadcast continuously an identification tag that contains its coordinate position. In such a case, the transceiver acts as a geolocation beacon. Nevertheless, mobile transceivers represent a challenge in the VLC communication chain, as smartphones have not integrated yet a VLC customized detection stage. In order to make current smartphones capable to detect VLC broadcasted signals, their Ambient Light Sensor (ALS) is adapted as a VLC detector. For this to be achieved, lighting transceivers need to adapt their modulation scheme. For instance, frequencies representing start bit, 1, and 0 logic values can be set to avoid flicker from illumination and to permit detecting the under-sampled signal. Decoding the signal requires a multiple steps real-time signal processing as shown here.

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

The Half-Second Delay: What Follows?

ERIC Educational Resources Information Center

Wiliam, Dylan

2006-01-01

There is an increasing body of evidence that only a minuscule proportion of the sensory data processed by the unconscious mind (capable of processing approximately 11 million bits per second) is referred to the conscious mind (capable of processing approximately 50 bits per second). It is also clear that conscious awareness of stimuli from the…

Smart Vest: wearable multi-parameter remote physiological monitoring system.

PubMed

Pandian, P S; Mohanavelu, K; Safeer, K P; Kotresh, T M; Shakunthala, D T; Gopal, Parvati; Padaki, V C

2008-05-01

The wearable physiological monitoring system is a washable shirt, which uses an array of sensors connected to a central processing unit with firmware for continuously monitoring physiological signals. The data collected can be correlated to produce an overall picture of the wearer's health. In this paper, we discuss the wearable physiological monitoring system called 'Smart Vest'. The Smart Vest consists of a comfortable to wear vest with sensors integrated for monitoring physiological parameters, wearable data acquisition and processing hardware and remote monitoring station. The wearable data acquisition system is designed using microcontroller and interfaced with wireless communication and global positioning system (GPS) modules. The physiological signals monitored are electrocardiogram (ECG), photoplethysmogram (PPG), body temperature, blood pressure, galvanic skin response (GSR) and heart rate. The acquired physiological signals are sampled at 250samples/s, digitized at 12-bit resolution and transmitted wireless to a remote physiological monitoring station along with the geo-location of the wearer. The paper describes a prototype Smart Vest system used for remote monitoring of physiological parameters and the clinical validation of the data are also presented.

Uncovering a key to the process of metastasis in human cancers: a review of critical regulators of anoikis.

PubMed

Tan, Kevin; Goldstein, David; Crowe, Philip; Yang, Jia-Lin

2013-11-01

Anoikis ('homelessness' in Greek) is a form of apoptosis following the detachment of cells from the appropriate extracellular matrix (Chiarugi and Giannoni in Biochem Pharmacol 76:1352-1364, 2008). Resistance to anoikis is a critical mediator of metastasis in cancer by enabling cancer cells to survive during invasion and transport in the blood and lymph. Numerous regulators and mechanisms of anoikis in human cancer have been proposed to date. Consequently, the identification of key regulators of anoikis that can be targeted to at least partially restore anoikis sensitivity in cancer cells is important in the development of therapies to treat metastatic cancer. A literature search focusing on the regulators of anoikis in human cancer was performed on the Medline, Embase and Scopus databases. Mcl-1, Cav-1, Bcl-(xL), cFLIP, 14-3-3ζ and Bit1 appear to regulate anoikis in human cancer by participating in the intrinsic apoptotic pathway, extrinsic apoptotic pathway or caspase-independent pathways. Mcl-1, Cav-1, Bcl-(xL), cFLIP and 14-3-3ζ are suppressors of anoikis, and their upregulation confers anoikis resistance to cancer cells. Bit1 is a promoter of anoikis and is downregulated to confer anoikis resistance in metastatic cancer. Anoikis is a complex process involving the crosstalk between different signalling pathways. The dysregulated expression of key regulators of anoikis that participate in these signalling pathways promotes anoikis resistance in human cancer. These regulators of anoikis might therefore be the targets for developing therapies to overcome anoikis resistance in metastatic cancer.

GET: A generic electronics system for TPCs and nuclear physics instrumentation

NASA Astrophysics Data System (ADS)

Pollacco, E. C.; Grinyer, G. F.; Abu-Nimeh, F.; Ahn, T.; Anvar, S.; Arokiaraj, A.; Ayyad, Y.; Baba, H.; Babo, M.; Baron, P.; Bazin, D.; Beceiro-Novo, S.; Belkhiria, C.; Blaizot, M.; Blank, B.; Bradt, J.; Cardella, G.; Carpenter, L.; Ceruti, S.; De Filippo, E.; Delagnes, E.; De Luca, S.; De Witte, H.; Druillole, F.; Duclos, B.; Favela, F.; Fritsch, A.; Giovinazzo, J.; Gueye, C.; Isobe, T.; Hellmuth, P.; Huss, C.; Lachacinski, B.; Laffoley, A. T.; Lebertre, G.; Legeard, L.; Lynch, W. G.; Marchi, T.; Martina, L.; Maugeais, C.; Mittig, W.; Nalpas, L.; Pagano, E. V.; Pancin, J.; Poleshchuk, O.; Pedroza, J. L.; Pibernat, J.; Primault, S.; Raabe, R.; Raine, B.; Rebii, A.; Renaud, M.; Roger, T.; Roussel-Chomaz, P.; Russotto, P.; Saccà, G.; Saillant, F.; Sizun, P.; Suzuki, D.; Swartz, J. A.; Tizon, A.; Usher, N.; Wittwer, G.; Yang, J. C.

2018-04-01

General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wasner, Evan; Bearden, Sean; Žutić, Igor, E-mail: zigor@buffalo.edu

Digital operation of lasers with injected spin-polarized carriers provides an improved operation over their conventional counterparts with spin-unpolarized carriers. Such spin-lasers can attain much higher bit rates, crucial for optical communication systems. The overall quality of a digital signal in these two types of lasers is compared using eye diagrams and quantified by improved Q-factors and bit-error-rates in spin-lasers. Surprisingly, an optimal performance of spin-lasers requires finite, not infinite, spin-relaxation times, giving a guidance for the design of future spin-lasers.

Correlation Between Analog Noise Measurements and the Expected Bit Error Rate of a Digital Signal Propagating Through Passive Components

NASA Technical Reports Server (NTRS)

Warner, Joseph D.; Theofylaktos, Onoufrios

2012-01-01

A method of determining the bit error rate (BER) of a digital circuit from the measurement of the analog S-parameters of the circuit has been developed. The method is based on the measurement of the noise and the standard deviation of the noise in the S-parameters. Once the standard deviation and the mean of the S-parameters are known, the BER of the circuit can be calculated using the normal Gaussian function.

Fort Monmouth Technical Disclosure Bulletin. Volume 1, Number 1.

DTIC Science & Technology

1982-12-01

laser A may be placed between two plates in an evacuated area, and a space charge cloud caused by a multipactor i:.y be r.iade to niove between the...Radiation Detection Uodem Multipactor FuIP Ct] 1 AfTRACT (CAeM ree e, dl N nmeW -V md identl by block numbe) The Technical Disclosure Bulletin is...can be used with any digital signal containing regularly spaced synchronization bits or characters or else additional synchronization bits can be added

VINSON/AUTOVON Interface Applique for the Modem, Digital Data, AN/GSC-38

DTIC Science & Technology

1980-11-01

Measurement Indication Result Before Step 6 None Noise and beeping are heard in handset After Step 7 None Noise and beepi ng disappear Condition Measurement...linear range due to the compression used. Lowering the levels below the compression range may give increased linearity, but may cause signal-to- noise ...are encountered where the bit error rate at 16 KB/S results is objectionable audio noise or causes the KY-58 to squelch. On these channels the bit

Apparatus and Method for Communication over Power Lines

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor); Greer, III, Lawrence C. (Inventor); Nappier, Jennifer M. (Inventor)

2017-01-01

An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Apparatus and Method for Communication over Power Lines

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor); Greer, Lawrence C., III (Inventor); Nappier, Jennifer M. (Inventor)

2015-01-01

An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Quantifying pretreatment degradation compounds in solution and accumulated by cells during solids and yeast recycling in the Rapid Bioconversion with Integrated recycling Technology process using AFEX™ corn stover.

PubMed

Sarks, Cory; Higbee, Alan; Piotrowski, Jeff; Xue, Saisi; Coon, Joshua J; Sato, Trey K; Jin, Mingjie; Balan, Venkatesh; Dale, Bruce E

2016-04-01

Effects of degradation products (low molecular weight compounds produced during pretreatment) on the microbes used in the RaBIT (Rapid Bioconversion with Integrated recycling Technology) process that reduces enzyme usage up to 40% by efficient enzyme recycling were studied. Chemical genomic profiling was performed, showing no yeast response differences in hydrolysates produced during RaBIT enzymatic hydrolysis. Concentrations of degradation products in solution were quantified after different enzymatic hydrolysis cycles and fermentation cycles. Intracellular degradation product concentrations were also measured following fermentation. Degradation product concentrations in hydrolysate did not change between RaBIT enzymatic hydrolysis cycles; the cell population retained its ability to oxidize/reduce (detoxify) aldehydes over five RaBIT fermentation cycles; and degradation products accumulated within or on the cells as RaBIT fermentation cycles increased. Synthetic hydrolysate was used to confirm that pretreatment degradation products are the sole cause of decreased xylose consumption during RaBIT fermentations. Copyright © 2016 Elsevier Ltd. All rights reserved.

14 CFR 1215.102 - Definitions.

Code of Federal Regulations, 2011 CFR

2011-01-01

... NASA communication circuits to unify the above into a functioning system. It specifically excludes the user ground system/TDRSS interface. (c) Bit stream. The digital electronic signals acquired by TDRSS...

14 CFR 1215.102 - Definitions.

Code of Federal Regulations, 2012 CFR

2012-01-01

... NASA communication circuits to unify the above into a functioning system. It specifically excludes the user ground system/TDRSS interface. (c) Bit stream. The digital electronic signals acquired by TDRSS...

Results From YOUTHSAT - Indian experiment in earths thermosphere-ionosphere region.

NASA Astrophysics Data System (ADS)

Tarun Kumar, Pant

It is known that the characterization and modeling of the ionosphere/thermosphere necessitates a comprehensive understanding of the various processes prevailing therein. India’s first, indigenous and dedicated aeronomy satellite 'YOUTHSAT' carrying two Indian payloads - RaBIT (Radio Beacon for Ionospheric Tomography), and LiVHySI (Limb Viewing Hyper Spectral Imager) and one Russian payload SOLRAD, was conceived primarily to address to this aspect and launched on April 20, 2011 in an 818 Km polar orbit from SHAR on ISRO launch vehicle PSLV. The payloads RaBIT and LiVHySI were designed specifically to observe the ionised and neutral components of the upper atmosphere respectively. YOUTHSAT is a small satellite quiet advanced in its class having all the functionalities which are normally associated with a bigger satellite. The rising phase of the 23rd solar cycle was considered to be the best window for various observations from onboard YOUTHSAT. As an Indo Russian endeavour, it was launched with an objective of investigating the terrestrial upper atmosphere vis-a-vis the activity on the sun. RaBIT, an ISRO venture, is a radio beacon emitting coherent radio signal at 150 and 400 MHz frequencies. These are received using a chain of five receivers deployed along the ~76oE meridian at Trivandrum, Bangalore, Hyderabad, Bhopal and Delhi. The receivers estimate the Total Electron Content (TEC) of the ionosphere through the relative phase change of the received radio signals. The TECs thus estimated near simultaneously, are used to generate a tomogram, which gives an Altitude-Latitude distribution of the ionospheric electron density. For YOUTHSAT configuration, the tomogram covers the ionosphere from a few degrees (5-6o) south of Trivandrum to about 3-4o north of Delhi depending upon the satellite elevation. The RaBIT tomography network is by far the longest network existing anywhere in the world, and is unique therefore. Through RaBIT, a unique dataset leading to ionospheric tomograms representing altitude-latitude variation of electron density over the 77oE meridian over the Indian region has been generated around specific times (~10:30 AM/PM). These tomograms have provided, among others: (a) First ever images of the ionospheric nighttime ESF irregularities (b) Quantification of the topside F3 ionospheric layers using Tomography (c) Evidence of wavelike modulations in the overall low and equatorial ionospheric region using tomography (d) Day and night differences in the electron density distribution, (e) Evidence of the presence of the ionospheric top-side layer (f) Modulations in the ionosphere due to space weather activity and (g) Direct evidence of the presence of Travelling Atmospheric Disturbance (TAD). YOUTHSAT recently completed its mission life time of about two years, after having generated a comprehensive set of data on terrestrial upper atmosphere. The YOUTHSAT data are being analysed by various researchers and more results providing a new insight into the upper atmospheric processes are in offing. Some of the important outcomes mentioned above will be discussed in detail.

Event-driven processing for hardware-efficient neural spike sorting

NASA Astrophysics Data System (ADS)

Liu, Yan; Pereira, João L.; Constandinou, Timothy G.

2018-02-01

Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.

Wireless neural recording with single low-power integrated circuit.

PubMed

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

Completion processing for data communications instructions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blocksome, Michael A.; Kumar, Sameer; Parker, Jeffrey J.

Completion processing of data communications instructions in a distributed computing environment with computers coupled for data communications through communications adapters and an active messaging interface (`AMI`), injecting for data communications instructions into slots in an injection FIFO buffer a transfer descriptor, at least some of the instructions specifying callback functions; injecting a completion descriptor for each instruction that specifies a callback function into an injection FIFO buffer slot having a corresponding slot in a pending callback list; listing in the pending callback list callback functions specified by data communications instructions; processing each descriptor in the injection FIFO buffer, setting amore » bit in a completion bit mask corresponding to the slot in the FIFO where the completion descriptor was injected; and calling by the AMI any callback functions in the pending callback list as indicated by set bits in the completion bit mask.« less

A readout integrated circuit based on DBI-CTIA and cyclic ADC for MEMS-array-based focal plane

NASA Astrophysics Data System (ADS)

Miao, Liu; Dong, Wu; Zheyao, Wang

2016-11-01

A readout integrated circuit (ROIC) for a MEMS (microelectromechanical system)-array-based focal plane (MAFP) intended for imaging applications is presented. The ROIC incorporates current sources for diode detectors, scanners, timing sequence controllers, differential buffered injection-capacitive trans-impedance amplifier (DBI-CTIA) and 10-bit cyclic ADCs, and is integrated with MAFP using 3-D integration technology. A small-signal equivalent model is built to include thermal detectors into circuit simulations. The biasing current is optimized in terms of signal-to-noise ratio and power consumption. Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements, with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40 μm wide column. Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process, and verified in a code density test of which the results indicate a (0.29/-0.31) LSB differential nonlinearity (DNL) and a (0.61/-0.45) LSB integral nonlinearity (INL). Spectrum analysis shows that the effective number of bits (ENOB) is 9.09. The ROIC consumes 248 mW of power at most if not to cut off quiescent current paths when not needed. Project supported by by National Natural Science Foundation of China (No. 61271130), the Beijing Municipal Science and Tech Project (No. D13110100290000), the Tsinghua University Initiative Scientific Research Program (No. 20131089225), and the Shenzhen Science and Technology Development Fund (No. CXZZ20130322170740736).

Systems and methods for free space optical communication

DOEpatents

Harper, Warren W [Benton City, WA; Aker, Pamela M [Richland, WA; Pratt, Richard M [Richland, WA

2011-05-10

Free space optical communication methods and systems, according to various aspects are described. The methods and systems are characterized by transmission of data through free space with a digitized optical signal acquired using wavelength modulation, and by discrimination between bit states in the digitized optical signal using a spectroscopic absorption feature of a chemical substance.

Photonic-Assisted mm-Wave and THz Wireless Transmission towards 100 Gbit/s Data Rate

NASA Astrophysics Data System (ADS)

Freire Hermelo, Maria; Chuenchom, Rattana; Rymanov, Vitaly; Kaiser, Thomas; Sheikh, Fawad; Czylwik, Andreas; Stöhr, Andreas

2017-09-01

This paper presents photonic-assisted 60 GHz mm-wave and 325 GHz system approaches that enable the transmission of spectral-efficient and high data rate signals over fiber and over air. First, we focus on generic channel characteristics within the mm-wave 60 GHz band and at the terahertz (THz) band around 325 GHz. Next, for generating the high data rate baseband signals, we present a technical solution for constructing an extreme bandwidth arbitrary waveform generator (AWG). We then report the development of a novel coherent photonic mixer (CPX) module for direct optic-to-RF conversion of extreme wideband optical signals, with a>5 dB higher conversion gain compared to conventional photodiodes. Finally, we experimentally demonstrate record spectral efficient wireless transmission for both bands. The achieved spectral efficiencies reach 10 bit/s/Hz for the 60 GHz band and 6 bit/s/Hz for the 325 GHz band. The maximum data rate transmitted at THz frequencies in the 325 GHz band is 59 Gbit/s using a 64-QAM-OFDM modulation format and a 10 GHz wide data signal.

Demonstration of the CDMA-mode CAOS smart camera.

PubMed

Riza, Nabeel A; Mazhar, Mohsin A

2017-12-11

Demonstrated is the code division multiple access (CDMA)-mode coded access optical sensor (CAOS) smart camera suited for bright target scenarios. Deploying a silicon CMOS sensor and a silicon point detector within a digital micro-mirror device (DMD)-based spatially isolating hybrid camera design, this smart imager first engages the DMD starring mode with a controlled factor of 200 high optical attenuation of the scene irradiance to provide a classic unsaturated CMOS sensor-based image for target intelligence gathering. Next, this CMOS sensor provided image data is used to acquire a focused zone more robust un-attenuated true target image using the time-modulated CDMA-mode of the CAOS camera. Using four different bright light test target scenes, successfully demonstrated is a proof-of-concept visible band CAOS smart camera operating in the CDMA-mode using up-to 4096 bits length Walsh design CAOS pixel codes with a maximum 10 KHz code bit rate giving a 0.4096 seconds CAOS frame acquisition time. A 16-bit analog-to-digital converter (ADC) with time domain correlation digital signal processing (DSP) generates the CDMA-mode images with a 3600 CAOS pixel count and a best spatial resolution of one micro-mirror square pixel size of 13.68 μm side. The CDMA-mode of the CAOS smart camera is suited for applications where robust high dynamic range (DR) imaging is needed for un-attenuated un-spoiled bright light spectrally diverse targets.

Evaluate the Feasibility of Using Frontal SSVEP to Implement an SSVEP-Based BCI in Young, Elderly and ALS Groups.

PubMed

Hsu, Hao-Teng; Lee, I-Hui; Tsai, Han-Ting; Chang, Hsiang-Chih; Shyu, Kuo-Kai; Hsu, Chuan-Chih; Chang, Hsiao-Huang; Yeh, Ting-Kuang; Chang, Chun-Yen; Lee, Po-Lei

2016-05-01

This paper studies the amplitude-frequency characteristic of frontal steady-state visual evoked potential (SSVEP) and its feasibility as a control signal for brain computer interface (BCI). SSVEPs induced by different stimulation frequencies, from 13 ~ 31 Hz in 2 Hz steps, were measured in eight young subjects, eight elders and seven ALS patients. Each subject was requested to participate in a calibration study and an application study. The calibration study was designed to find the amplitude-frequency characteristics of SSVEPs recorded from Oz and Fpz positions, while the application study was designed to test the feasibility of using frontal SSVEP to control a two-command SSVEP-based BCI. The SSVEP amplitude was detected by an epoch-average process which enables artifact-contaminated epochs can be removed. The seven ALS patients were severely impaired, and four patients, who were incapable of completing our BCI task, were excluded from calculation of BCI performance. The averaged accuracies, command transfer intervals and information transfer rates in operating frontal SSVEP-based BCI were 96.1%, 3.43 s/command, and 14.42 bits/min in young subjects; 91.8%, 6.22 s/command, and 6.16 bits/min in elders; 81.2%, 12.14 s/command, and 1.51 bits/min in ALS patients, respectively. The frontal SSVEP could be an alternative choice to design SSVEP-based BCI.

14 CFR § 1215.102 - Definitions.

Code of Federal Regulations, 2014 CFR

2014-01-01

..., and the necessary TDRSS operational areas, interface devices, and NASA communication circuits that... interface. (c) Bit stream. The electronic signals acquired by TDRSS from the user craft or the user...

First Tests of a New Fast Waveform Digitizer for PMT Signal Read-out from Liquid Argon Dark Matter Detectors

NASA Astrophysics Data System (ADS)

Szelc, A. M.; Canci, N.; Cavanna, F.; Cortopassi, A.; D'Incecco, M.; Mini, G.; Pietropaolo, F.; Romboli, A.; Segreto, E.; Acciarri, R.

A new generation Waveform Digitizer board as been recently made available on the market by CAEN. The new board CAEN V1751 with 8 Channels per board, 10 bit, 1 GS/s Flash ADC Waveform Digitizer (or 4 channel, 10 bit, 2 GS/s Flash ADC Waveform Digitizer -Dual Edge Sampling mode) with threshold and Auto-Trigger capabilities provides an ideal (relatively low-cost) solution for reading signals from liquid Argon detectors for Dark Matter search equipped with an array of PMTs for the detection of scintillation light. The board was extensively used in real experimental conditions to test its usefulness for possible future uses and to compare it with a state of the art digital oscilloscope. As results, PMT Signal sampling at 1 or 2 GS/s is appropriate for the reconstruction of the fast component of the signal scintillation in Argon (characteristic time of about 4 ns) and the extended dynamic range, after a small customization, allows for the detection of signals in the range of energy needed. The bandwidth is found to be adequate and the intrinsic noise is very low.

Pulsed plasma solid propellant microthruster for the synchronous meteorological satellite. Task 4: Engineering model fabrication and test report

NASA Technical Reports Server (NTRS)

Guman, W. J. (Editor)

1972-01-01

Two flight prototype solid propellant pulsed plasma microthruster propulsion systems for the SMS satellite were fabricated, assembled and tested. The propulsion system is a completely self contained system requiring only three electrical inputs to operate: a 29.4 volt power source, a 28 volt enable signal and a 50 millsec long command fire signal that can be applied at any rate from 50 ppm to 110 ppm. The thrust level can be varied over a range 2.2 to 1 at constant impulse bit amplitude. By controlling the duration of the 28 volt enable either steady state thrust or a series of discrete impulse bits can be generated. A new technique of capacitor charging was implemented to reduce high voltage stress on energy storage capacitors.

Multichannel Brain-Signal-Amplifying and Digitizing System

NASA Technical Reports Server (NTRS)

Gevins, Alan

2005-01-01

An apparatus has been developed for use in acquiring multichannel electroencephalographic (EEG) data from a human subject. EEG apparatuses with many channels in use heretofore have been too heavy and bulky to be worn, and have been limited in dynamic range to no more than 18 bits. The present apparatus is small and light enough to be worn by the subject. It is capable of amplifying EEG signals and digitizing them to 22 bits in as many as 150 channels. The apparatus is controlled by software and is plugged into the USB port of a personal computer. This apparatus makes it possible, for the first time, to obtain high-resolution functional EEG images of a thinking brain in a real-life, ambulatory setting outside a research laboratory or hospital.

Optical signal suppression by a cascaded SOA/RSOA for wavelength reusing reflective PON upstream transmission.

PubMed

Jung, Sang Min; Mun, Kyoung Hak; Kang, Soo Min; Han, Sang Kook

2017-09-18

An optical signal suppression technique based on a cascaded SOA and RSOA is proposed for the reflective passive optical networks (PONs) with wavelength division multiplexing (WDM). By suppressing the downstream signal of the optical carrier, the proposed reflective PON effectively reuses the downstream optical carrier for upstream signal transmission. As an experimental demonstration, we show that the proposed optical signal suppression technique is effective in terms of the signal bandwidth and bit-error-rate (BER) performance of the remodulated upstream transmission.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

PubMed

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-12-26

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

Multi-wavelength access gate for WDM-formatted words in optical RAM row architectures

NASA Astrophysics Data System (ADS)

Fitsios, D.; Alexoudi, T.; Vagionas, C.; Miliou, A.; Kanellos, G. T.; Pleros, N.

2013-03-01

Optical RAM has emerged as a promising solution for overcoming the "Memory Wall" of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.

Hydrogen Peroxide Signaling in Plant Development and Abiotic Responses: Crosstalk with Nitric Oxide and Calcium

PubMed Central

Niu, Lijuan; Liao, Weibiao

2016-01-01

Hydrogen peroxide (H2O2), as a reactive oxygen species, is widely generated in many biological systems. It has been considered as an important signaling molecule that mediates various physiological and biochemical processes in plants. Normal metabolism in plant cells results in H2O2 generation, from a variety of sources. Also, it is now clear that nitric oxide (NO) and calcium (Ca2+) function as signaling molecules in plants. Both H2O2 and NO are involved in plant development and abiotic responses. A wide range of evidences suggest that NO could be generated under similar stress conditions and with similar kinetics as H2O2. The interplay between H2O2 and NO has important functional implications to modulate transduction processes in plants. Moreover, close interaction also exists between H2O2 and Ca2+ in response to development and abiotic stresses in plants. Cellular responses to H2O2 and Ca2+ signaling systems are complex. There is quite a bit of interaction between H2O2 and Ca2+ signaling in responses to several stimuli. This review aims to introduce these evidences in our understanding of the crosstalk among H2O2, NO, and Ca2+ signaling which regulates plant growth and development, and other cellular and physiological responses to abiotic stresses. PMID:26973673

Frame Decoder for Consultative Committee for Space Data Systems (CCSDS)

NASA Technical Reports Server (NTRS)

Reyes, Miguel A. De Jesus

2014-01-01

GNU Radio is a free and open source development toolkit that provides signal processing to implement software radios. It can be used with low-cost external RF hardware to create software defined radios, or without hardware in a simulation-like environment. GNU Radio applications are primarily written in Python and C++. The Universal Software Radio Peripheral (USRP) is a computer-hosted software radio designed by Ettus Research. The USRP connects to a host computer via high-speed Gigabit Ethernet. Using the open source Universal Hardware Driver (UHD), we can run GNU Radio applications using the USRP. An SDR is a "radio in which some or all physical layer functions are software defined"(IEEE Definition). A radio is any kind of device that wirelessly transmits or receives radio frequency (RF) signals in the radio frequency. An SDR is a radio communication system where components that have been typically implemented in hardware are implemented in software. GNU Radio has a generic packet decoder block that is not optimized for CCSDS frames. Using this generic packet decoder will add bytes to the CCSDS frames and will not permit for bit error correction using Reed-Solomon. The CCSDS frames consist of 256 bytes, including a 32-bit sync marker (0x1ACFFC1D). This frames are generated by the Space Data Processor and GNU Radio will perform the modulation and framing operations, including frame synchronization.

A Fully Integrated Sensor SoC with Digital Calibration Hardware and Wireless Transceiver at 2.4 GHz

PubMed Central

Kim, Dong-Sun; Jang, Sung-Joon; Hwang, Tae-Ho

2013-01-01

A single-chip sensor system-on-a-chip (SoC) that implements radio for 2.4 GHz, complete digital baseband physical layer (PHY), 10-bit sigma-delta analog-to-digital converter and dedicated sensor calibration hardware for industrial sensing systems has been proposed and integrated in a 0.18-μm CMOS technology. The transceiver's building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indicator, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, the digital building block consists of offset quadrature phase-shift keying (OQPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, digital MAC function, sensor calibration hardware and embedded 8-bit microcontroller. The digital MAC function supports cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. The embedded sensor signal processing block consists of calibration coefficient calculator, sensing data calibration mapper and sigma-delta analog-to-digital converter with digital decimation filter. The sensitivity of the overall receiver and the error vector magnitude (EVM) of the overall transmitter are −99 dBm and 18.14%, respectively. The proposed calibration scheme has a reduction of errors by about 45.4% compared with the improved progressive polynomial calibration (PPC) method and the maximum current consumption of the SoC is 16 mA. PMID:23698271

Data Capture Technique for High Speed Signaling

DOEpatents

Barrett, Wayne Melvin; Chen, Dong; Coteus, Paul William; Gara, Alan Gene; Jackson, Rory; Kopcsay, Gerard Vincent; Nathanson, Ben Jesse; Vranas, Paylos Michael; Takken, Todd E.

2008-08-26

A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

SAR processing on the MPP

NASA Technical Reports Server (NTRS)

Batcher, K. E.; Eddey, E. E.; Faiss, R. O.; Gilmore, P. A.

1981-01-01

The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.

The Quanta Image Sensor: Every Photon Counts

PubMed Central

Fossum, Eric R.; Ma, Jiaju; Masoodian, Saleh; Anzagira, Leo; Zizza, Rachel

2016-01-01

The Quanta Image Sensor (QIS) was conceived when contemplating shrinking pixel sizes and storage capacities, and the steady increase in digital processing power. In the single-bit QIS, the output of each field is a binary bit plane, where each bit represents the presence or absence of at least one photoelectron in a photodetector. A series of bit planes is generated through high-speed readout, and a kernel or “cubicle” of bits (x, y, t) is used to create a single output image pixel. The size of the cubicle can be adjusted post-acquisition to optimize image quality. The specialized sub-diffraction-limit photodetectors in the QIS are referred to as “jots” and a QIS may have a gigajot or more, read out at 1000 fps, for a data rate exceeding 1 Tb/s. Basically, we are trying to count photons as they arrive at the sensor. This paper reviews the QIS concept and its imaging characteristics. Recent progress towards realizing the QIS for commercial and scientific purposes is discussed. This includes implementation of a pump-gate jot device in a 65 nm CIS BSI process yielding read noise as low as 0.22 e− r.m.s. and conversion gain as high as 420 µV/e−, power efficient readout electronics, currently as low as 0.4 pJ/b in the same process, creating high dynamic range images from jot data, and understanding the imaging characteristics of single-bit and multi-bit QIS devices. The QIS represents a possible major paradigm shift in image capture. PMID:27517926

Mark 3 wideband digital recorder in perspective

NASA Technical Reports Server (NTRS)

Hinteregger, H. F.

1980-01-01

The tape recorder used for the Mark 3 data acquisition and processing system is compared with earlier very long baseline interferometry recorders. Wideband 33-1/3 kbpi digital channel characteristics of instrumentation recorders and of a modern video cassette recorder are illustrated. Factors which influenced selection of the three major commercial components (transport, heads, and tape) are discussed. A brief functional description and the reasons for development of efficient signal electronics and necessary auxiliary control electronics are given. The design and operation of a digital bit synchronizer is illustrated as an example of the high degree of simplicity achieved.

Encryption key distribution via chaos synchronization

NASA Astrophysics Data System (ADS)

Keuninckx, Lars; Soriano, Miguel C.; Fischer, Ingo; Mirasso, Claudio R.; Nguimdo, Romain M.; van der Sande, Guy

2017-02-01

We present a novel encryption scheme, wherein an encryption key is generated by two distant complex nonlinear units, forced into synchronization by a chaotic driver. The concept is sufficiently generic to be implemented on either photonic, optoelectronic or electronic platforms. The method for generating the key bitstream from the chaotic signals is reconfigurable. Although derived from a deterministic process, the obtained bit series fulfill the randomness conditions as defined by the National Institute of Standards test suite. We demonstrate the feasibility of our concept on an electronic delay oscillator circuit and test the robustness against attacks using a state-of-the-art system identification method.

Demonstration of intradyne BPSK optical free-space transmission in representative atmospheric turbulence conditions for geostationary uplink channel.

PubMed

Surof, Janis; Poliak, Juraj; Calvo, Ramon Mata

2017-06-01

Binary phase-shift keying optical transmission in the C-band with coherent intradyne reception is demonstrated over a long-range (10.45 km) link through the atmosphere. The link emulates representative channel conditions for geostationary optical feeder uplinks in satellite communications. The digital signal processing used in recovering the transmitted data and the performed measurements are described. Finally, the bit error rate results for 10 Gbit/s, 20 Gbit/s, and 30 Gbit/s of the outdoor experiments are presented and compared with back-to-back measurements and theory.

Noise reduction in plasmonic amplifiers

NASA Astrophysics Data System (ADS)

Vyshnevyy, Andrey A.; Fedyanin, Dmitry Yu.

2018-06-01

Surface plasmon polaritons amplification give the possibility to overcome strong absorption in metals and design truly nanoscale devices for on-chip photonic circuits. However, the process of stimulated emission in the gain medium is inevitably accompanied by spontaneous emission, which greatly increases the noise power. Herein we present an efficient strategy for noise reduction in plasmonic amplifiers,which is based on gain redistribution along the amplifier. We show that even a very small gain redistribution (∼3%) makes it possible to increase the signal-to-noise ratio by ∼100% and improve the bit error ratio by orders of magnitude.

High capacity reversible watermarking for audio by histogram shifting and predicted error expansion.

PubMed

Wang, Fei; Xie, Zhaoxin; Chen, Zuo

2014-01-01

Being reversible, the watermarking information embedded in audio signals can be extracted while the original audio data can achieve lossless recovery. Currently, the few reversible audio watermarking algorithms are confronted with following problems: relatively low SNR (signal-to-noise) of embedded audio; a large amount of auxiliary embedded location information; and the absence of accurate capacity control capability. In this paper, we present a novel reversible audio watermarking scheme based on improved prediction error expansion and histogram shifting. First, we use differential evolution algorithm to optimize prediction coefficients and then apply prediction error expansion to output stego data. Second, in order to reduce location map bits length, we introduced histogram shifting scheme. Meanwhile, the prediction error modification threshold according to a given embedding capacity can be computed by our proposed scheme. Experiments show that this algorithm improves the SNR of embedded audio signals and embedding capacity, drastically reduces location map bits length, and enhances capacity control capability.

Theoretical analysis of the performance of code division multiple access communications over multimode optical fiber channels. Part 1: Transmission and detection

NASA Astrophysics Data System (ADS)

Walker, Ernest L.

1994-05-01

This paper presents results of a theoretical investigation to evaluate the performance of code division multiple access communications over multimode optical fiber channels in an asynchronous, multiuser communication network environment. The system is evaluated using Gold sequences for spectral spreading of the baseband signal from each user employing direct-sequence biphase shift keying and intensity modulation techniques. The transmission channel model employed is a lossless linear system approximation of the field transfer function for the alpha -profile multimode optical fiber. Due to channel model complexity, a correlation receiver model employing a suboptimal receive filter was used in calculating the peak output signal at the ith receiver. In Part 1, the performance measures for the system, i.e., signal-to-noise ratio and bit error probability for the ith receiver, are derived as functions of channel characteristics, spectral spreading, number of active users, and the bit energy to noise (white) spectral density ratio. In Part 2, the overall system performance is evaluated.

A sub-microwatt asynchronous level-crossing ADC for biomedical applications.

PubMed

Li, Yongjia; Zhao, Duan; Serdijn, Wouter A

2013-04-01

A continuous-time level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. When compared to uniform-sampling (US) ADCs LC-ADCs generate fewer samples for various sparse biomedical signals. Lower power consumption and reduced design complexity with respect to conventional LC-ADCs are achieved due to: 1) replacing the n-bit digital-to-analog converter (DAC) with a 1-bit DAC; 2) splitting the level-crossing detections; and 3) fixing the comparison window. Designed and implemented in 0.18 μm CMOS technology, the proposed ADC uses a chip area of 220 × 203 μm(2). Operating from a supply voltage of 0.8 V, the ADC consumes 313-582 nW from 5 Hz to 5 kHz and achieves an ENOB up to 7.9 bits.

A microcontroller-based telemetry system for sympathetic nerve activity and ECG measurement.

PubMed

Harada, E; Yonezawa, Y; Caldwell, W M; Hahn, A W

1999-01-01

A telemetry system employing a low power 8-bit microcontroller has been developed for chronic unanesthetized small animal studies. The two-channel system is designed for use with animals in shielded cages. Analog signals from implantable ECG and nerve electrodes are converted to an 8-bit serial digital format. This is accomplished by individual 8 bit A/D converters included in the microcontroller, which also has serial I/O port. The converted serial binary code is applied directly to an antenna wire. Therefore, the system does not need to employ a separate transmitter, such as in FM or infrared optical telemeters. The system is used in a shielded animal cage to reduce interference from external radio signals and 60 Hz power line fields. The code is received by a high input impedance amplifier in the cage and is then demodulated. The telemeter is powered by a small 3 V lithium battery, which provides 100 hours of continuous operation. The circuit is constructed on two 25 x 25 mm. printed circuit boards and encapsulated in epoxy, yielding a total volume of 6.25 cc. The weight is 15 g.

A four-dimensional virtual hand brain-machine interface using active dimension selection.

PubMed

Rouse, Adam G

2016-06-01

Brain-machine interfaces (BMI) traditionally rely on a fixed, linear transformation from neural signals to an output state-space. In this study, the assumption that a BMI must control a fixed, orthogonal basis set was challenged and a novel active dimension selection (ADS) decoder was explored. ADS utilizes a two stage decoder by using neural signals to both (i) select an active dimension being controlled and (ii) control the velocity along the selected dimension. ADS decoding was tested in a monkey using 16 single units from premotor and primary motor cortex to successfully control a virtual hand avatar to move to eight different postures. Following training with the ADS decoder to control 2, 3, and then 4 dimensions, each emulating a grasp shape of the hand, performance reached 93% correct with a bit rate of 2.4 bits s(-1) for eight targets. Selection of eight targets using ADS control was more efficient, as measured by bit rate, than either full four-dimensional control or computer assisted one-dimensional control. ADS decoding allows a user to quickly and efficiently select different hand postures. This novel decoding scheme represents a potential method to reduce the complexity of high-dimension BMI control of the hand.

Spectrally efficient digitized radio-over-fiber system with k-means clustering-based multidimensional quantization.

PubMed

Zhang, Lu; Pang, Xiaodan; Ozolins, Oskars; Udalcovs, Aleksejs; Popov, Sergei; Xiao, Shilin; Hu, Weisheng; Chen, Jiajia

2018-04-01

We propose a spectrally efficient digitized radio-over-fiber (D-RoF) system by grouping highly correlated neighboring samples of the analog signals into multidimensional vectors, where the k-means clustering algorithm is adopted for adaptive quantization. A 30  Gbit/s D-RoF system is experimentally demonstrated to validate the proposed scheme, reporting a carrier aggregation of up to 40 100 MHz orthogonal frequency division multiplexing (OFDM) channels with quadrate amplitude modulation (QAM) order of 4 and an aggregation of 10 100 MHz OFDM channels with a QAM order of 16384. The equivalent common public radio interface rates from 37 to 150  Gbit/s are supported. Besides, the error vector magnitude (EVM) of 8% is achieved with the number of quantization bits of 4, and the EVM can be further reduced to 1% by increasing the number of quantization bits to 7. Compared with conventional pulse coding modulation-based D-RoF systems, the proposed D-RoF system improves the signal-to-noise-ratio up to ∼9  dB and greatly reduces the EVM, given the same number of quantization bits.

FPGA-based LDPC-coded APSK for optical communication systems.

PubMed

Zou, Ding; Lin, Changyu; Djordjevic, Ivan B

2017-02-20

In this paper, with the aid of mutual information and generalized mutual information (GMI) capacity analyses, it is shown that the geometrically shaped APSK that mimics an optimal Gaussian distribution with equiprobable signaling together with the corresponding gray-mapping rules can approach the Shannon limit closer than conventional quadrature amplitude modulation (QAM) at certain range of FEC overhead for both 16-APSK and 64-APSK. The field programmable gate array (FPGA) based LDPC-coded APSK emulation is conducted on block interleaver-based and bit interleaver-based systems; the results verify a significant improvement in hardware efficient bit interleaver-based systems. In bit interleaver-based emulation, the LDPC-coded 64-APSK outperforms 64-QAM, in terms of symbol signal-to-noise ratio (SNR), by 0.1 dB, 0.2 dB, and 0.3 dB at spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz, respectively. It is found by emulation that LDPC-coded 64-APSK for spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz is 1.6 dB, 1.7 dB, and 2.2 dB away from the GMI capacity.

Enhanced intercarrier interference mitigation based on encoded bit-sequence distribution inside optical superchannels

NASA Astrophysics Data System (ADS)

Torres, Jhon James Granada; Soto, Ana María Cárdenas; González, Neil Guerrero

2016-10-01

In the context of gridless optical multicarrier systems, we propose a method for intercarrier interference (ICI) mitigation which allows bit error correction in scenarios of nonspectral flatness between the subcarriers composing the multicarrier system and sub-Nyquist carrier spacing. We propose a hybrid ICI mitigation technique which exploits the advantages of signal equalization at both levels: the physical level for any digital and analog pulse shaping, and the bit-data level and its ability to incorporate advanced correcting codes. The concatenation of these two complementary techniques consists of a nondata-aided equalizer applied to each optical subcarrier, and a hard-decision forward error correction applied to the sequence of bits distributed along the optical subcarriers regardless of prior subchannel quality assessment as performed in orthogonal frequency-division multiplexing modulations for the implementation of the bit-loading technique. The impact of the ICI is systematically evaluated in terms of bit-error-rate as a function of the carrier frequency spacing and the roll-off factor of the digital pulse-shaping filter for a simulated 3×32-Gbaud single-polarization quadrature phase shift keying Nyquist-wavelength division multiplexing system. After the ICI mitigation, a back-to-back error-free decoding was obtained for sub-Nyquist carrier spacings of 28.5 and 30 GHz and roll-off values of 0.1 and 0.4, respectively.

Near-Field Chipless Radio-Frequency Identification (RFID) Sensing and Identification System with Switching Reading.

PubMed

Paredes, Ferran; Herrojo, Cristian; Mata-Contreras, Javier; Moras, Miquel; Núñez, Alba; Ramon, Eloi; Martín, Ferran

2018-04-09

A chipless radio-frequency identification (chipless-RFID) and sensing system, where tags are read by proximity (near-field) through a switch, is presented. The tags consist of a set of identical resonant elements (split-ring resonators or SRRs), printed or etched at predefined and equidistant positions, forming a linear chain, each SRR providing a bit of information. The logic state ('1' or '0') associated with each resonator depends on whether it is present or not in the predefined position. The reader is an array of power splitters used to feed a set of SRR-loaded transmission lines (in equal number to the number of resonant elements, or bits, of the tag). The feeding (interrogation) signal is a harmonic (single-tone) signal tuned to a frequency in the vicinity of the fundamental resonance of the SRRs. The set of SRR-loaded lines must be designed so that the corresponding SRRs are in perfect alignment with the SRRs of the tag, provided the tag is positioned on top of the reader. Thus, in a reading operation, as long as the tag is very close to the reader, the SRRs of the tag modify (decrease) the transmission coefficient of the corresponding reader line (through electromagnetic coupling between both SRRs), and the amplitude of the output signal is severely reduced. Therefore, the identification (ID) code of the tag is contained in the amplitudes of the output signals of the SRR-loaded lines, which can be inferred sequentially by means of a switching system. Unlike previous chipless-RFID systems based on near-field and sequential bit reading, the tags in the proposed system can be merely positioned on top of the reader, conveniently aligned, without the need to mechanically place them across the reader. Since tag reading is only possible if the tag is very close to the reader, this system can be also used as a proximity sensor with applications such as target identification. The proposed chipless-RFID and sensing approach is validated by reading a designed 4-bit tag. For identification purposes, this system is of special interest in applications where a low number of bits suffice, and tag reading by proximity is acceptable (or even convenient). Applications mostly related to secure paper, particularly involving a limited number of items (e.g., exams, ballots, etc.), in order to provide authenticity and avoid counterfeiting, are envisaged. As a proximity sensor, the system may be of use in detecting and distinguishing different targets in applications such as smart packaging.

Near-Field Chipless Radio-Frequency Identification (RFID) Sensing and Identification System with Switching Reading

PubMed Central

Mata-Contreras, Javier; Moras, Miquel; Ramon, Eloi; Martín, Ferran

2018-01-01

A chipless radio-frequency identification (chipless-RFID) and sensing system, where tags are read by proximity (near-field) through a switch, is presented. The tags consist of a set of identical resonant elements (split-ring resonators or SRRs), printed or etched at predefined and equidistant positions, forming a linear chain, each SRR providing a bit of information. The logic state (‘1’ or ‘0’) associated with each resonator depends on whether it is present or not in the predefined position. The reader is an array of power splitters used to feed a set of SRR-loaded transmission lines (in equal number to the number of resonant elements, or bits, of the tag). The feeding (interrogation) signal is a harmonic (single-tone) signal tuned to a frequency in the vicinity of the fundamental resonance of the SRRs. The set of SRR-loaded lines must be designed so that the corresponding SRRs are in perfect alignment with the SRRs of the tag, provided the tag is positioned on top of the reader. Thus, in a reading operation, as long as the tag is very close to the reader, the SRRs of the tag modify (decrease) the transmission coefficient of the corresponding reader line (through electromagnetic coupling between both SRRs), and the amplitude of the output signal is severely reduced. Therefore, the identification (ID) code of the tag is contained in the amplitudes of the output signals of the SRR-loaded lines, which can be inferred sequentially by means of a switching system. Unlike previous chipless-RFID systems based on near-field and sequential bit reading, the tags in the proposed system can be merely positioned on top of the reader, conveniently aligned, without the need to mechanically place them across the reader. Since tag reading is only possible if the tag is very close to the reader, this system can be also used as a proximity sensor with applications such as target identification. The proposed chipless-RFID and sensing approach is validated by reading a designed 4-bit tag. For identification purposes, this system is of special interest in applications where a low number of bits suffice, and tag reading by proximity is acceptable (or even convenient). Applications mostly related to secure paper, particularly involving a limited number of items (e.g., exams, ballots, etc.), in order to provide authenticity and avoid counterfeiting, are envisaged. As a proximity sensor, the system may be of use in detecting and distinguishing different targets in applications such as smart packaging. PMID:29642560

PAM-4 signal delivery in one radio-over-fiber system

NASA Astrophysics Data System (ADS)

Wang, Hada; Zhou, Wen; Yu, Jianjun

2017-10-01

We propose and experimentally demonstrate four-level pulse-amplitude-modulation (PAM-4) signal delivery in a radio-over-fiber system for the first time. Over 8-Gbit/s PAM-4 signals have been transmitted over 20-km single-mode fiber-28 and 1-m wireless distance. The signal after transmission is detected directly by an envelope detector at the receiver side. The maximal bit rate could be increased if the bandpass amplifier and envelope detector have more bandwidth.

Analytical estimation of laser phase noise induced BER floor in coherent receiver with digital signal processing.

PubMed

Vanin, Evgeny; Jacobsen, Gunnar

2010-03-01

The Bit-Error-Ratio (BER) floor caused by the laser phase noise in the optical fiber communication system with differential quadrature phase shift keying (DQPSK) and coherent detection followed by digital signal processing (DSP) is analytically evaluated. An in-phase and quadrature (I&Q) receiver with a carrier phase recovery using DSP is considered. The carrier phase recovery is based on a phase estimation of a finite sum (block) of the signal samples raised to the power of four and the phase unwrapping at transitions between blocks. It is demonstrated that errors generated at block transitions cause the dominating contribution to the system BER floor when the impact of the additive noise is negligibly small in comparison with the effect of the laser phase noise. Even the BER floor in the case when the phase unwrapping is omitted is analytically derived and applied to emphasize the crucial importance of this signal processing operation. The analytical results are verified by full Monte Carlo simulations. The BER for another type of DQPSK receiver operation, which is based on differential phase detection, is also obtained in the analytical form using the principle of conditional probability. The principle of conditional probability is justified in the case of differential phase detection due to statistical independency of the laser phase noise induced signal phase error and the additive noise contributions. Based on the achieved analytical results the laser linewidth tolerance is calculated for different system cases.

Enhancing Observability of Signal Composition and Error Signatures During Dynamic SEE Analog to Digital Device Testing

NASA Technical Reports Server (NTRS)

Berg, M.; Buchner, S.; Kim, H.; Friendlich, M.; Perez, C.; Phan, A.; Seidleck, C.; LaBel, K.; Kruckmeyer, K.

2010-01-01

A novel approach to dynamic SEE ADC testing is presented. The benefits of this test scheme versus prior implemented techniques include the ability to observe ADC SEE errors that are in the form of phase shifts, single bit upsets, bursts of disrupted signal composition, and device clock loss.

14 CFR 171.311 - Signal format requirements.

Code of Federal Regulations, 2013 CFR

2013-01-01

... zero state of the data filed represents the lower limit of the absolute range of the coded parameter... transmitted as a “zero” DPSK signal lasting for a six-bit period (see Tables 4a and 4b). Table 4a—Approach... microsecond. T0=Time separation in microseconds between TO and FRO beam centers corresponding to zero degrees...

14 CFR 171.311 - Signal format requirements.

Code of Federal Regulations, 2011 CFR

2011-01-01

... zero state of the data filed represents the lower limit of the absolute range of the coded parameter... transmitted as a “zero” DPSK signal lasting for a six-bit period (see Tables 4a and 4b). Table 4a—Approach... microsecond. T0=Time separation in microseconds between TO and FRO beam centers corresponding to zero degrees...

14 CFR 171.311 - Signal format requirements.

Code of Federal Regulations, 2012 CFR

2012-01-01

... zero state of the data filed represents the lower limit of the absolute range of the coded parameter... transmitted as a “zero” DPSK signal lasting for a six-bit period (see Tables 4a and 4b). Table 4a—Approach... microsecond. T0=Time separation in microseconds between TO and FRO beam centers corresponding to zero degrees...

14 CFR 171.311 - Signal format requirements.

Code of Federal Regulations, 2014 CFR

2014-01-01

... zero state of the data filed represents the lower limit of the absolute range of the coded parameter... transmitted as a “zero” DPSK signal lasting for a six-bit period (see Tables 4a and 4b). Table 4a—Approach... microsecond. T0=Time separation in microseconds between TO and FRO beam centers corresponding to zero degrees...

Frame synchronization performance and analysis

NASA Technical Reports Server (NTRS)

Aguilera, C. S. R.; Swanson, L.; Pitt, G. H., III

1988-01-01

The analysis used to generate the theoretical models showing the performance of the frame synchronizer is described for various frame lengths and marker lengths at various signal to noise ratios and bit error tolerances.

Digital seismo-acoustic signal processing aboard a wireless sensor platform

NASA Astrophysics Data System (ADS)

Marcillo, O.; Johnson, J. B.; Lorincz, K.; Werner-Allen, G.; Welsh, M.

2006-12-01

We are developing a low power, low-cost wireless sensor array to conduct real-time signal processing of earthquakes at active volcanoes. The sensor array, which integrates data from both seismic and acoustic sensors, is based on Moteiv TMote Sky wireless sensor nodes (www.moteiv.com). The nodes feature a Texas Instruments MSP430 microcontroller, 48 Kbytes of program memory, 10 Kbytes of static RAM, 1 Mbyte of external flash memory, and a 2.4-GHz Chipcon CC2420 IEEE 802.15.4 radio. The TMote Sky is programmed in TinyOS. Basic signal processing occurs on an array of three peripheral sensor nodes. These nodes are tied into a dedicated GPS receiver node, which is focused on time synchronization, and a central communications node, which handles data integration and additional processing. The sensor nodes incorporate dual 12-bit digitizers sampling a seismic sensor and a pressure transducer at 100 samples per second. The wireless capabilities of the system allow flexible array geometry, with a maximum aperture of 200m. We have already developed the digital signal processing routines on board the Moteiv Tmote sensor nodes. The developed routines accomplish Real-time Seismic-Amplitude Measurement (RSAM), Seismic Spectral- Amplitude Measurement (SSAM), and a user-configured Short Term Averaging / Long Term Averaging (STA LTA ratio), which is used to calculate first arrivals. The processed data from individual nodes are transmitted back to a central node, where additional processing may be performed. Such processing will include back azimuth determination and other wave field analyses. Future on-board signal processing will focus on event characterization utilizing pattern recognition and spectral characterization. The processed data is intended as low bandwidth information which can be transmitted periodically and at low cost through satellite telemetry to a web server. The processing is limited by the computational capabilities (RAM, ROM) of the nodes. Nevertheless, we envision this product to be a useful tool for assessing the state of unrest at remote volcanoes.

Method and apparatus for frequency spectrum analysis

NASA Technical Reports Server (NTRS)

Cole, Steven W. (Inventor)

1992-01-01

A method for frequency spectrum analysis of an unknown signal in real-time is discussed. The method is based upon integration of 1-bit samples of signal voltage amplitude corresponding to sine or cosine phases of a controlled center frequency clock which is changed after each integration interval to sweep the frequency range of interest in steps. Integration of samples during each interval is carried out over a number of cycles of the center frequency clock spanning a number of cycles of an input signal to be analyzed. The invention may be used to detect the frequency of at least two signals simultaneously. By using a reference signal of known frequency and voltage amplitude (added to the two signals for parallel processing in the same way, but in a different channel with a sampling at the known frequency and phases of the reference signal), the absolute voltage amplitude of the other two signals may be determined by squaring the sine and cosine integrals of each channel and summing the squares to obtain relative power measurements in all three channels and, from the known voltage amplitude of the reference signal, obtaining an absolute voltage measurement for the other two signals by multiplying the known voltage of the reference signal with the ratio of the relative power of each of the other two signals to the relative power of the reference signal.

Circuit for Communication over DC Power Line Using High Temperature Electronics

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)

2014-01-01

A high temperature communications circuit includes a power conductor for concurrently conducting electrical energy for powering circuit components and transmitting a modulated data signal, and a demodulator for demodulating the data signal and generating a serial bit stream based on the data signal. The demodulator includes an absolute value amplifier for conditionally inverting or conditionally passing a signal applied to the absolute value amplifier. The absolute value amplifier utilizes no diodes to control the conditional inversion or passing of the signal applied to the absolute value amplifier.

Low-voltage differentially-signaled modulators.

PubMed

Zortman, William A; Lentine, Anthony L; Trotter, Douglas C; Watts, Michael R

2011-12-19

For exascale computing applications, viable optical solutions will need to operate using low voltage signaling and with low power consumption. In this work, the first differentially signaled silicon resonator is demonstrated which can provide a 5dB extinction ratio using 3fJ/bit and 500mV signal amplitude at 10Gbps. Modulation with asymmetric voltage amplitudes as low as 150mV with 3dB extinction are demonstrated at 10Gbps as well. Differentially signaled resonators simplify and expand the design space for modulator implementation and require no special drivers.

Time-resolved x-ray scattering instrumentation

DOEpatents

Borso, C.S.

1985-11-21

An apparatus and method for increased speed and efficiency of data compilation and analysis in real time is presented in this disclosure. Data is sensed and grouped in combinations in accordance with predetermined logic. The combinations are grouped so that a simplified reduced signal results, such as pairwise summing of data values having offsetting algebraic signs, thereby reducing the magnitude of the net pair sum. Bit storage requirements are reduced and speed of data compilation and analysis is increased by manipulation of shorter bit length data values, making real time evaluation possible.

Rewriting magnetic phase change memory by laser heating

NASA Astrophysics Data System (ADS)

Timmerwilke, John; Liou, Sy-Hwang; Cheng, Shu Fan; Edelstein, Alan S.

2016-04-01

Magnetic phase change memory (MAG PCM) consists of bits with different magnetic permeability values. The bits are read by measuring their effect on a magnetic probe field. Previously low permeability crystalline bits had been written in high permeability amorphous films of Metglas via laser heating. Here data is presented showing that by applying short laser pulses with the appropriate power to previously crystallized regions they can first be vitrified and then again crystallized. Thus, MAG PCM is rewriteable. Technical issues in processing the bits are discussed and results on thermal modeling are presented.

Exploring the physical layer frontiers of cellular uplink: The Vienna LTE-A Uplink Simulator.

PubMed

Zöchmann, Erich; Schwarz, Stefan; Pratschner, Stefan; Nagel, Lukas; Lerch, Martin; Rupp, Markus

Communication systems in practice are subject to many technical/technological constraints and restrictions. Multiple input, multiple output (MIMO) processing in current wireless communications, as an example, mostly employs codebook-based pre-coding to save computational complexity at the transmitters and receivers. In such cases, closed form expressions for capacity or bit-error probability are often unattainable; effects of realistic signal processing algorithms on the performance of practical communication systems rather have to be studied in simulation environments. The Vienna LTE-A Uplink Simulator is a 3GPP LTE-A standard compliant MATLAB-based link level simulator that is publicly available under an academic use license, facilitating reproducible evaluations of signal processing algorithms and transceiver designs in wireless communications. This paper reviews research results that have been obtained by means of the Vienna LTE-A Uplink Simulator, highlights the effects of single-carrier frequency-division multiplexing (as the distinguishing feature to LTE-A downlink), extends known link adaptation concepts to uplink transmission, shows the implications of the uplink pilot pattern for gathering channel state information at the receiver and completes with possible future research directions.

Retained energy-based coding for EEG signals.

PubMed

Bazán-Prieto, Carlos; Blanco-Velasco, Manuel; Cárdenas-Barrera, Julián; Cruz-Roldán, Fernando

2012-09-01

The recent use of long-term records in electroencephalography is becoming more frequent due to its diagnostic potential and the growth of novel signal processing methods that deal with these types of recordings. In these cases, the considerable volume of data to be managed makes compression necessary to reduce the bit rate for transmission and storage applications. In this paper, a new compression algorithm specifically designed to encode electroencephalographic (EEG) signals is proposed. Cosine modulated filter banks are used to decompose the EEG signal into a set of subbands well adapted to the frequency bands characteristic of the EEG. Given that no regular pattern may be easily extracted from the signal in time domain, a thresholding-based method is applied for quantizing samples. The method of retained energy is designed for efficiently computing the threshold in the decomposition domain which, at the same time, allows the quality of the reconstructed EEG to be controlled. The experiments are conducted over a large set of signals taken from two public databases available at Physionet and the results show that the compression scheme yields better compression than other reported methods. Copyright © 2011 IPEM. Published by Elsevier Ltd. All rights reserved.

A parallel unbalanced digitization architecture to reduce the dynamic range of multiple signals

NASA Astrophysics Data System (ADS)

Vallérian, Mathieu; HuÅ£u, Florin; Villemaud, Guillaume; Miscopein, Benoît; Risset, Tanguy

2016-05-01

Technologies employed in urban sensor networks are permanently evolving, and thus the gateways employed to collect data in such kind of networks have to be very flexible in order to be compliant with the new communication standards. A convenient way to do that is to digitize all the received signals in one shot and then to digitally perform the signal processing, as it is done in software-defined radio (SDR). All signals can be emitted with very different features (bandwidth, modulation type, and power level) in order to respond to the various propagation conditions. Their difference in terms of power levels is a problem when digitizing them together, as no current commercial analog-to-digital converter (ADC) can provide a fine enough resolution to digitize this high dynamic range between the weakest possible signal in the presence of a stronger signal. This paper presents an RF front end receiver architecture capable of handling this problem by using two ADCs of lower resolutions. The architecture is validated through a set of simulations using Keysight's ADS software. The main validation criterion is the bit error rate comparison with a classical receiver.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

PubMed Central

Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

2015-01-01

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB. PMID:26712765

Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

NASA Astrophysics Data System (ADS)

Haron, Adib; Mahdzair, Fazren; Luqman, Anas; Osman, Nazmie; Junid, Syed Abdul Mutalib Al

2018-03-01

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.

Programmable Differential Delay Circuit With Fine Delay Adjustment

DOEpatents

DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

2002-07-09

Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Computer program CORDET. [computerized simulation of digital phase-lock loop for Omega navigation receiver

NASA Technical Reports Server (NTRS)

Palkovic, R. A.

1974-01-01

A FORTRAN 4 computer program provides convenient simulation of an all-digital phase-lock loop (DPLL). The DPLL forms the heart of the Omega navigation receiver prototype. Through the DPLL, the phase of the 10.2 KHz Omega signal is estimated when the true signal phase is contaminated with noise. This investigation has provided a convenient means of evaluating loop performance in a variety of noise environments, and has proved to be a useful tool for evaluating design changes. The goals of the simulation are to: (1) analyze the circuit on a bit-by-bit level in order to evaluate the overall design; (2) see easily the effects of proposed design changes prior to actual breadboarding; and (3) determine the optimum integration time for the DPLL in an environment typical of general aviation conditions.

Steganalysis of recorded speech

NASA Astrophysics Data System (ADS)

Johnson, Micah K.; Lyu, Siwei; Farid, Hany

2005-03-01

Digital audio provides a suitable cover for high-throughput steganography. At 16 bits per sample and sampled at a rate of 44,100 Hz, digital audio has the bit-rate to support large messages. In addition, audio is often transient and unpredictable, facilitating the hiding of messages. Using an approach similar to our universal image steganalysis, we show that hidden messages alter the underlying statistics of audio signals. Our statistical model begins by building a linear basis that captures certain statistical properties of audio signals. A low-dimensional statistical feature vector is extracted from this basis representation and used by a non-linear support vector machine for classification. We show the efficacy of this approach on LSB embedding and Hide4PGP. While no explicit assumptions about the content of the audio are made, our technique has been developed and tested on high-quality recorded speech.

8-channel prototype of SALT readout ASIC for Upstream Tracker in the upgraded LHCb experiment

NASA Astrophysics Data System (ADS)

Abellan Beteta, C.; Bugiel, S.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kane, C.; Moron, J.; Swientek, K.; Wang, J.

2017-02-01

SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Upstream Tracker of the LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of an analogue front-end and an ultra-low power (<0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. An 8-channel prototype (SALT8), comprising all important functionalities was designed, fabricated and tested. A full 128-channel version was also submitted. The design and test results of the SALT8 prototype are presented showing its full functionality.

Analysis of mobile fronthaul bandwidth and wireless transmission performance in split-PHY processing architecture.

PubMed

Miyamoto, Kenji; Kuwano, Shigeru; Terada, Jun; Otaka, Akihiro

2016-01-25

We analyze the mobile fronthaul (MFH) bandwidth and the wireless transmission performance in the split-PHY processing (SPP) architecture, which redefines the functional split of centralized/cloud RAN (C-RAN) while preserving high wireless coordinated multi-point (CoMP) transmission/reception performance. The SPP architecture splits the base stations (BS) functions between wireless channel coding/decoding and wireless modulation/demodulation, and employs its own CoMP joint transmission and reception schemes. Simulation results show that the SPP architecture reduces the MFH bandwidth by up to 97% from conventional C-RAN while matching the wireless bit error rate (BER) performance of conventional C-RAN in uplink joint reception with only 2-dB signal to noise ratio (SNR) penalty.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Data flow machine for data driven computing

DOEpatents

Davidson, G.S.; Grafe, V.G.

1988-07-22

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information from an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ''fire'' signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.

Direct match data flow memory for data driven computing

DOEpatents

Davidson, George S.; Grafe, Victor Gerald

1997-01-01

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Direct match data flow memory for data driven computing

DOEpatents

Davidson, G.S.; Grafe, V.G.

1997-10-07

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ``fire`` signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.

LSST camera readout chip ASPIC: test tools

NASA Astrophysics Data System (ADS)

Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

2012-02-01

The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

Dolphin Sounds-Inspired Covert Underwater Acoustic Communication and Micro-Modem

PubMed Central

Qiao, Gang; Liu, Songzuo; Bilal, Muhammad

2017-01-01

A novel portable underwater acoustic modem is proposed in this paper for covert communication between divers or underwater unmanned vehicles (UUVs) and divers at a short distance. For the first time, real dolphin calls are used in the modem to realize biologically inspired Covert Underwater Acoustic Communication (CUAC). A variety of dolphin whistles and clicks stored in an SD card inside the modem helps to realize different biomimetic CUAC algorithms based on the specified covert scenario. In this paper, the information is conveyed during the time interval between dolphin clicks. TMS320C6748 and TLV320AIC3106 are the core processors used in our unique modem for fast digital processing and interconnection with other terminals or sensors. Simulation results show that the bit error rate (BER) of the CUAC algorithm is less than 10−5 when the signal to noise ratio is over ‒5 dB. The modem was tested in an underwater pool, and a data rate of 27.1 bits per second at a distance of 10 m was achieved. PMID:29068363

Room temperature 1040fps, 1 megapixel photon-counting image sensor with 1.1um pixel pitch

NASA Astrophysics Data System (ADS)

Masoodian, S.; Ma, J.; Starkey, D.; Wang, T. J.; Yamashita, Y.; Fossum, E. R.

2017-05-01

A 1Mjot single-bit quanta image sensor (QIS) implemented in a stacked backside-illuminated (BSI) process is presented. This is the first work to report a megapixel photon-counting CMOS-type image sensor to the best of our knowledge. A QIS with 1.1μm pitch tapered-pump-gate jots is implemented with cluster-parallel readout, where each cluster of jots is associated with its own dedicated readout electronics stacked under the cluster. Power dissipation is reduced with this cluster readout because of the reduced column bus parasitic capacitance, which is important for the development of 1Gjot arrays. The QIS functions at 1040fps with binary readout and dissipates only 17.6mW, including I/O pads. The readout signal chain uses a fully differential charge-transfer amplifier (CTA) gain stage before a 1b-ADC to achieve an energy/bit FOM of 16.1pJ/b and 6.9pJ/b for the whole sensor and gain stage+ADC, respectively. Analog outputs with on-chip gain are implemented for pixel characterization purposes.

LSB-based Steganography Using Reflected Gray Code for Color Quantum Images

NASA Astrophysics Data System (ADS)

Li, Panchi; Lu, Aiping

2018-02-01

At present, the classical least-significant-bit (LSB) based image steganography has been extended to quantum image processing. For the existing LSB-based quantum image steganography schemes, the embedding capacity is no more than 3 bits per pixel. Therefore, it is meaningful to study how to improve the embedding capacity of quantum image steganography. This work presents a novel LSB-based steganography using reflected Gray code for colored quantum images, and the embedding capacity of this scheme is up to 4 bits per pixel. In proposed scheme, the secret qubit sequence is considered as a sequence of 4-bit segments. For the four bits in each segment, the first bit is embedded in the second LSB of B channel of the cover image, and and the remaining three bits are embedded in LSB of RGB channels of each color pixel simultaneously using reflected-Gray code to determine the embedded bit from secret information. Following the transforming rule, the LSB of stego-image are not always same as the secret bits and the differences are up to almost 50%. Experimental results confirm that the proposed scheme shows good performance and outperforms the previous ones currently found in the literature in terms of embedding capacity.

Hamming and Accumulator Codes Concatenated with MPSK or QAM

NASA Technical Reports Server (NTRS)

Divsalar, Dariush; Dolinar, Samuel

2009-01-01

In a proposed coding-and-modulation scheme, a high-rate binary data stream would be processed as follows: 1. The input bit stream would be demultiplexed into multiple bit streams. 2. The multiple bit streams would be processed simultaneously into a high-rate outer Hamming code that would comprise multiple short constituent Hamming codes a distinct constituent Hamming code for each stream. 3. The streams would be interleaved. The interleaver would have a block structure that would facilitate parallelization for high-speed decoding. 4. The interleaved streams would be further processed simultaneously into an inner two-state, rate-1 accumulator code that would comprise multiple constituent accumulator codes - a distinct accumulator code for each stream. 5. The resulting bit streams would be mapped into symbols to be transmitted by use of a higher-order modulation - for example, M-ary phase-shift keying (MPSK) or quadrature amplitude modulation (QAM). The novelty of the scheme lies in the concatenation of the multiple-constituent Hamming and accumulator codes and the corresponding parallel architectures of the encoder and decoder circuitry (see figure) needed to process the multiple bit streams simultaneously. As in the cases of other parallel-processing schemes, one advantage of this scheme is that the overall data rate could be much greater than the data rate of each encoder and decoder stream and, hence, the encoder and decoder could handle data at an overall rate beyond the capability of the individual encoder and decoder circuits.

Efficient bit sifting scheme of post-processing in quantum key distribution

NASA Astrophysics Data System (ADS)

Li, Qiong; Le, Dan; Wu, Xianyan; Niu, Xiamu; Guo, Hong

2015-10-01

Bit sifting is an important step in the post-processing of quantum key distribution (QKD). Its function is to sift out the undetected original keys. The communication traffic of bit sifting has essential impact on the net secure key rate of a practical QKD system. In this paper, an efficient bit sifting scheme is presented, of which the core is a lossless source coding algorithm. Both theoretical analysis and experimental results demonstrate that the performance of the scheme is approaching the Shannon limit. The proposed scheme can greatly decrease the communication traffic of the post-processing of a QKD system, which means the proposed scheme can decrease the secure key consumption for classical channel authentication and increase the net secure key rate of the QKD system, as demonstrated by analyzing the improvement on the net secure key rate. Meanwhile, some recommendations on the application of the proposed scheme to some representative practical QKD systems are also provided.

Beating Landauer's Bound: Tradeoff between Accuracy and Heat Dissipation

NASA Astrophysics Data System (ADS)

Talukdar, Saurav; Bhaban, Shreyas; Salapaka, Murti

The Landauer's Principle states that erasing of one bit of stored information is necessarily accompanied by heat dissipation of at least kb Tln 2 per bit. However, this is true only if the erasure process is always successful. We demonstrate that if the erasure process has a success probability p, the minimum heat dissipation per bit is given by kb T(plnp + (1 - p) ln (1 - p) + ln 2), referred to as the Generalized Landauer Bound, which is kb Tln 2 if the erasure process is always successful and decreases to zero as p reduces to 0.5. We present a model for a one-bit memory based on a Brownian particle in a double well potential motivated from optical tweezers and achieve erasure by manipulation of the optical fields. The method uniquely provides with a handle on the success proportion of the erasure. The thermodynamics framework for Langevin dynamics developed by Sekimoto is used for computation of heat dissipation in each realization of the erasure process. Using extensive Monte Carlo simulations, we demonstrate that the Landauer Bound of kb Tln 2 is violated by compromising on the success of the erasure process, while validating the existence of the Generalized Landauer Bound.

Wavelet-based image compression using shuffling and bit plane correlation

NASA Astrophysics Data System (ADS)

Kim, Seungjong; Jeong, Jechang

2000-12-01

In this paper, we propose a wavelet-based image compression method using shuffling and bit plane correlation. The proposed method improves coding performance in two steps: (1) removing the sign bit plane by shuffling process on quantized coefficients, (2) choosing the arithmetic coding context according to maximum correlation direction. The experimental results are comparable or superior for some images with low correlation, to existing coders.

Wireless Neural Recording With Single Low-Power Integrated Circuit

PubMed Central

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

High bit depth infrared image compression via low bit depth codecs

NASA Astrophysics Data System (ADS)

Belyaev, Evgeny; Mantel, Claire; Forchhammer, Søren

2017-08-01

Future infrared remote sensing systems, such as monitoring of the Earth's environment by satellites, infrastructure inspection by unmanned airborne vehicles etc., will require 16 bit depth infrared images to be compressed and stored or transmitted for further analysis. Such systems are equipped with low power embedded platforms where image or video data is compressed by a hardware block called the video processing unit (VPU). However, in many cases using two 8-bit VPUs can provide advantages compared with using higher bit depth image compression directly. We propose to compress 16 bit depth images via 8 bit depth codecs in the following way. First, an input 16 bit depth image is mapped into 8 bit depth images, e.g., the first image contains only the most significant bytes (MSB image) and the second one contains only the least significant bytes (LSB image). Then each image is compressed by an image or video codec with 8 bits per pixel input format. We analyze how the compression parameters for both MSB and LSB images should be chosen to provide the maximum objective quality for a given compression ratio. Finally, we apply the proposed infrared image compression method utilizing JPEG and H.264/AVC codecs, which are usually available in efficient implementations, and compare their rate-distortion performance with JPEG2000, JPEG-XT and H.265/HEVC codecs supporting direct compression of infrared images in 16 bit depth format. A preliminary result shows that two 8 bit H.264/AVC codecs can achieve similar result as 16 bit HEVC codec.

A biclustering algorithm for extracting bit-patterns from binary datasets.

PubMed

Rodriguez-Baena, Domingo S; Perez-Pulido, Antonio J; Aguilar-Ruiz, Jesus S

2011-10-01

Binary datasets represent a compact and simple way to store data about the relationships between a group of objects and their possible properties. In the last few years, different biclustering algorithms have been specially developed to be applied to binary datasets. Several approaches based on matrix factorization, suffix trees or divide-and-conquer techniques have been proposed to extract useful biclusters from binary data, and these approaches provide information about the distribution of patterns and intrinsic correlations. A novel approach to extracting biclusters from binary datasets, BiBit, is introduced here. The results obtained from different experiments with synthetic data reveal the excellent performance and the robustness of BiBit to density and size of input data. Also, BiBit is applied to a central nervous system embryonic tumor gene expression dataset to test the quality of the results. A novel gene expression preprocessing methodology, based on expression level layers, and the selective search performed by BiBit, based on a very fast bit-pattern processing technique, provide very satisfactory results in quality and computational cost. The power of biclustering in finding genes involved simultaneously in different cancer processes is also shown. Finally, a comparison with Bimax, one of the most cited binary biclustering algorithms, shows that BiBit is faster while providing essentially the same results. The source and binary codes, the datasets used in the experiments and the results can be found at: http://www.upo.es/eps/bigs/BiBit.html dsrodbae@upo.es Supplementary data are available at Bioinformatics online.

An 11-bit 200 MS/s subrange SAR ADC with low-cost integrated reference buffer

NASA Astrophysics Data System (ADS)

He, Xiuju; Gu, Xian; Li, Weitao; Jiang, Hanjun; Li, Fule; Wang, Zhihua

2017-10-01

This paper presents an 11-bit 200 MS/s subrange SAR ADC with an integrated reference buffer in 65 nm CMOS. The proposed ADC employs a 3.5-bit flash ADC for coarse conversion, and a compact timing scheme at the flash/SAR boundary to speed up the conversion. The flash decision is used to control charge compensating for the reference voltage to reduce its input-dependent fluctuation. Measurement results show that the fabricated ADC has achieved significant improvement by applying the reference charge compensation. In addition, the ADC achieves a maximum signal-to-noise-and-distortion ratio of 59.3 dB at 200 MS/s. It consumes 3.91 mW from a 1.2 V supply, including the reference buffer. Project supported by the Zhongxing Telecommunication Equipment Corporation and Beijing Microelectronics Technology Institute.

AESA diagnostics in operational environments

NASA Astrophysics Data System (ADS)

Hull, W. P.

The author discusses some possible solutions to ASEA (active electronically scanned array) diagnostics in the operational environment using built-in testing (BIT), which can play a key role in reducing life-cycle cost if accurately implemented. He notes that it is highly desirable to detect and correct in the operational environment all degradation that impairs mission performance. This degradation must be detected with low false alarm rate and the appropriate action initiated consistent with low life-cycle cost. Mutual coupling is considered as a BIT signal injection method and is shown to have potential. However, the limits of the diagnostic capability using this method clearly depend on its stability and on the level of multipath for a specific application. BIT using mutual coupling may need to be supplemented on the ground by an externally mounted passive antenna that interfaces with onboard avionics.