Multichannel Baseband Processor for Wideband CDMA

NASA Astrophysics Data System (ADS)

Jalloul, Louay M. A.; Lin, Jim

2005-12-01

The system architecture of the cellular base station modem engine (CBME) is described. The CBME is a single-chip multichannel transceiver capable of processing and demodulating signals from multiple users simultaneously. It is optimized to process different classes of code-division multiple-access (CDMA) signals. The paper will show that through key functional system partitioning, tightly coupled small digital signal processing cores, and time-sliced reuse architecture, CBME is able to achieve a high degree of algorithmic flexibility while maintaining efficiency. The paper will also highlight the implementation and verification aspects of the CBME chip design. In this paper, wideband CDMA is used as an example to demonstrate the architecture concept.

Control of coherent information via on-chip photonic-phononic emitter-receivers.

PubMed

Shin, Heedeuk; Cox, Jonathan A; Jarecki, Robert; Starbuck, Andrew; Wang, Zheng; Rakich, Peter T

2015-03-05

Rapid progress in integrated photonics has fostered numerous chip-scale sensing, computing and signal processing technologies. However, many crucial filtering and signal delay operations are difficult to perform with all-optical devices. Unlike photons propagating at luminal speeds, GHz-acoustic phonons moving at slower velocities allow information to be stored, filtered and delayed over comparatively smaller length-scales with remarkable fidelity. Hence, controllable and efficient coupling between coherent photons and phonons enables new signal processing technologies that greatly enhance the performance and potential impact of integrated photonics. Here we demonstrate a mechanism for coherent information processing based on travelling-wave photon-phonon transduction, which achieves a phonon emit-and-receive process between distinct nanophotonic waveguides. Using this device, physics--which supports GHz frequencies--we create wavelength-insensitive radiofrequency photonic filters with frequency selectivity, narrow-linewidth and high power-handling in silicon. More generally, this emit-receive concept is the impetus for enabling new signal processing schemes.

Design of video interface conversion system based on FPGA

NASA Astrophysics Data System (ADS)

Zhao, Heng; Wang, Xiang-jun

2014-11-01

This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor.The current experiment shows that it can achieve high-quality video conversion with minimum board size.

Defect Inspection of Flip Chip Solder Bumps Using an Ultrasonic Transducer

PubMed Central

Su, Lei; Shi, Tielin; Xu, Zhensong; Lu, Xiangning; Liao, Guanglan

2013-01-01

Surface mount technology has spurred a rapid decrease in the size of electronic packages, where solder bump inspection of surface mount packages is crucial in the electronics manufacturing industry. In this study we demonstrate the feasibility of using a 230 MHz ultrasonic transducer for nondestructive flip chip testing. The reflected time domain signal was captured when the transducer scanning the flip chip, and the image of the flip chip was generated by scanning acoustic microscopy. Normalized cross-correlation was used to locate the center of solder bumps for segmenting the flip chip image. Then five features were extracted from the signals and images. The support vector machine was adopted to process the five features for classification and recognition. The results show the feasibility of this approach with high recognition rate, proving that defect inspection of flip chip solder bumps using the ultrasonic transducer has high potential in microelectronics packaging.

A three channel telemetry system

NASA Technical Reports Server (NTRS)

Lesho, Jeffery C.; Eaton, Harry A. C.

1993-01-01

A three channel telemetry system intended for biomedical applications is described. The transmitter is implemented in a single chip using a 2 micron BiCMOS processes. The operation of the system and the test results from the latest chip are discussed. One channel is always dedicated to temperature measurement while the other two channels are generic. The generic channels carry information from transducers that are interfaced to the system through on-chip general purpose operational amplifiers. The generic channels have different bandwidths: one from dc to 250 Hz and the other from dc to 1300 Hz. Each generic channel modulates a current controlled oscillator to produce a frequency modulated signal. The two frequency modulated signals are summed and used to amplitude modulate the temperature signal which acts as a carrier. A near-field inductive link telemeters the combined signals over a short distance. The chip operates on a supply voltage anywhere from 2.5 to 3.6 Volts and draws less than 1 mA when transmitting a signal. The chip can be incorporated into ingestible, implantable and other configurations. The device can free the patient from tethered data collection systems and reduces the possibility of infection from subcutaneous leads. Data telemetry can increase patient comfort leading to a greater acceptance of monitoring.

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE PAGES

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan; ...

2018-01-01

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

A Data Acquisition System Using Single-Chip Microcomputer

NASA Astrophysics Data System (ADS)

Yonyjiang, Dai; Jingkuan, Gao; Lin, Wan; Mingjia, Pi; Jingda, Nan

1989-12-01

A data acquisition system by single-chip microcomputer was designed. It is suitable to the future devlopment of the miniature tidar signal processing epuipment . The characteristics of frequecy response, SNR, D* and NEP of FM-CW CO2 coherent tidar were discussed.

Control of coherent information via on-chip photonic–phononic emitter–receivers

DOE PAGES

Shin, Heedeuk; Cox, Jonathan A.; Jarecki, Robert; ...

2015-03-05

We report that rapid progress in integrated photonics has fostered numerous chip-scale sensing, computing and signal processing technologies. However, many crucial filtering and signal delay operations are difficult to perform with all-optical devices. Unlike photons propagating at luminal speeds, GHz-acoustic phonons moving at slower velocities allow information to be stored, filtered and delayed over comparatively smaller length-scales with remarkable fidelity. Hence, controllable and efficient coupling between coherent photons and phonons enables new signal processing technologies that greatly enhance the performance and potential impact of integrated photonics. Here we demonstrate a mechanism for coherent information processing based on travelling-wave photon–phonon transduction,more » which achieves a phonon emit-and-receive process between distinct nanophotonic waveguides. Using this device, physics—which supports GHz frequencies—we create wavelength-insensitive radiofrequency photonic filters with frequency selectivity, narrow-linewidth and high power-handling in silicon. More generally, this emit-receive concept is the impetus for enabling new signal processing schemes.« less

Control of coherent information via on-chip photonic–phononic emitter–receivers

PubMed Central

Shin, Heedeuk; Cox, Jonathan A.; Jarecki, Robert; Starbuck, Andrew; Wang, Zheng; Rakich, Peter T.

2015-01-01

Rapid progress in integrated photonics has fostered numerous chip-scale sensing, computing and signal processing technologies. However, many crucial filtering and signal delay operations are difficult to perform with all-optical devices. Unlike photons propagating at luminal speeds, GHz-acoustic phonons moving at slower velocities allow information to be stored, filtered and delayed over comparatively smaller length-scales with remarkable fidelity. Hence, controllable and efficient coupling between coherent photons and phonons enables new signal processing technologies that greatly enhance the performance and potential impact of integrated photonics. Here we demonstrate a mechanism for coherent information processing based on travelling-wave photon–phonon transduction, which achieves a phonon emit-and-receive process between distinct nanophotonic waveguides. Using this device, physics—which supports GHz frequencies—we create wavelength-insensitive radiofrequency photonic filters with frequency selectivity, narrow-linewidth and high power-handling in silicon. More generally, this emit-receive concept is the impetus for enabling new signal processing schemes. PMID:25740405

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

The MRI appearances of cancellous allograft bone chips after the excision of bone tumours.

PubMed

Kang, S; Han, I; Hong, S H; Cho, H S; Kim, W; Kim, H-S

2015-01-01

Cancellous allograft bone chips are commonly used in the reconstruction of defects in bone after removal of benign tumours. We investigated the MRI features of grafted bone chips and their change over time, and compared them with those with recurrent tumour. We retrospectively reviewed 66 post-operative MRIs from 34 patients who had undergone curettage and grafting with cancellous bone chips to fill the defect after excision of a tumour. All grafts showed consistent features at least six months after grafting: homogeneous intermediate or low signal intensities with or without scattered hyperintense foci (speckled hyperintensities) on T1 images; high signal intensities with scattered hypointense foci (speckled hypointensities) on T2 images, and peripheral rim enhancement with or without central heterogeneous enhancements on enhanced images. Incorporation of the graft occurred from the periphery to the centre, and was completed within three years. Recurrent lesions consistently showed the same signal intensities as those of pre-operative MRIs of the primary lesions. There were four misdiagnoses, three of which were chondroid tumours. We identified typical MRI features and clarified the incorporation process of grafted cancellous allograft bone chips. The most important characteristics of recurrent tumours were that they showed the same signal intensities as the primary tumours. It might sometimes be difficult to differentiate grafted cancellous allograft bone chips from a recurrent chondroid tumour. ©2015 The British Editorial Society of Bone & Joint Surgery.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Wireless neural recording with single low-power integrated circuit.

PubMed

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

NASA Technical Reports Server (NTRS)

Kaplan, Steven B.; Pylov, Sergey V.; Pambianchi, Michael

2003-01-01

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

The use of low resistivity substrates for optimal noise reduction, ground referencing, and current conduction in mixed signal ASICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zimmerman, T.

1997-12-01

This paper is distilled from a talk given at the 3rd International Meeting on Front End Electronics in Taos, N.M. on Nov. 7,1997. It is based on experience gained by designing and testing the SVX3 128 channel silicon strip detector readout chip. The SVX3 chip organization is shown in Fig. 1. The Front End section consists of an integrator and analog pipeline designed at Fermilab, and the Back End section is an ADC plus sparsification and readout logic designed at LBL. SVX3 is a deadtimeless readout chip, which means that the front end is acquiring low level analog signals whilemore » the back end is digitizing and reading out digital signals. It is thus a true mixed signal chip, and demands close attention to avoid disastrous coupling from the digital to the analog sections. SVX3 is designed in a bulk CMOS process (i.e., the circuits sit in a silicon substrate). In such a process, the substrate becomes a potential coupling path. This paper discusses the effect of the substrate resistivity on coupling, and also goes into a more general discussion of grounding and referencing in mixed signal designs and how low resistivity substrates can be used to advantage. Finally, an alternative power supply current conduction method for ASICs is presented as an additional advantage which can be obtained with low resistivity substrates. 1 ref., 13 figs., 1 tab.« less

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

PubMed Central

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-01-01

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

PubMed

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-04-13

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

An integrated microfluidic analysis microsystems with bacterial capture enrichment and in-situ impedance detection

NASA Astrophysics Data System (ADS)

Liu, Hai-Tao; Wen, Zhi-Yu; Xu, Yi; Shang, Zheng-Guo; Peng, Jin-Lan; Tian, Peng

2017-09-01

In this paper, an integrated microfluidic analysis microsystems with bacterial capture enrichment and in-situ impedance detection was purposed based on microfluidic chips dielectrophoresis technique and electrochemical impedance detection principle. The microsystems include microfluidic chip, main control module, and drive and control module, and signal detection and processing modulet and result display unit. The main control module produce the work sequence of impedance detection system parts and achieve data communication functions, the drive and control circuit generate AC signal which amplitude and frequency adjustable, and it was applied on the foodborne pathogens impedance analysis microsystems to realize the capture enrichment and impedance detection. The signal detection and processing circuit translate the current signal into impendence of bacteria, and transfer to computer, the last detection result is displayed on the computer. The experiment sample was prepared by adding Escherichia coli standard sample into chicken sample solution, and the samples were tested on the dielectrophoresis chip capture enrichment and in-situ impedance detection microsystems with micro-array electrode microfluidic chips. The experiments show that the Escherichia coli detection limit of microsystems is 5 × 104 CFU/mL and the detection time is within 6 min in the optimization of voltage detection 10 V and detection frequency 500 KHz operating conditions. The integrated microfluidic analysis microsystems laid the solid foundation for rapid real-time in-situ detection of bacteria.

USB video image controller used in CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhang, Wenxuan; Wang, Yuxia; Fan, Hong

2002-09-01

CMOS process is mainstream technique in VLSI, possesses high integration. SE402 is multifunction microcontroller, which integrates image data I/O ports, clock control, exposure control and digital signal processing into one chip. SE402 reduces the number of chips and PCB's room. The paper studies emphatically on USB video image controller used in CMOS image sensor and give the application on digital still camera.

Neuromorphic vision sensors and preprocessors in system applications

NASA Astrophysics Data System (ADS)

Kramer, Joerg; Indiveri, Giacomo

1998-09-01

A partial review of neuromorphic vision sensors that are suitable for use in autonomous systems is presented. Interfaces are being developed to multiplex the high- dimensional output signals of arrays of such sensors and to communicate them in standard formats to off-chip devices for higher-level processing, actuation, storage and display. Alternatively, on-chip processing stages may be implemented to extract sparse image parameters, thereby obviating the need for multiplexing. Autonomous robots are used to test neuromorphic vision chips in real-world environments and to explore the possibilities of data fusion from different sensing modalities. Examples of autonomous mobile systems that use neuromorphic vision chips for line tracking and optical flow matching are described.

Wireless Neural Recording With Single Low-Power Integrated Circuit

PubMed Central

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

PubMed

Chen, Guanyu; Yu, Yu; Zhang, Xinliang

2016-08-01

We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

SAW correlator spread spectrum receiver

DOEpatents

Brocato, Robert W

2014-04-01

A surface acoustic wave (SAW) correlator spread-spectrum (SS) receiver is disclosed which utilizes a first demodulation stage with a chip length n and a second demodulation stage with a chip length m to decode a transmitted SS signal having a code length l=n.times.m which can be very long (e.g. up to 2000 chips or more). The first demodulation stage utilizes a pair of SAW correlators which demodulate the SS signal to generate an appropriate code sequence at an intermediate frequency which can then be fed into the second demodulation stage which can be formed from another SAW correlator, or by a digital correlator. A compound SAW correlator comprising two input transducers and a single output transducer is also disclosed which can be used to form the SAW correlator SS receiver, or for use in processing long code length signals.

Design of a dual-mode electrochemical measurement and analysis system.

PubMed

Yang, Jr-Fu; Wei, Chia-Ling; Wu, Jian-Fu; Liu, Bin-Da

2013-01-01

A dual-mode electrochemical measurement and analysis system is proposed. This system includes a dual-mode chip, which was designed and fabricated by using TSMC 0.35 µm 3.3 V/5 V 2P4M mixed-signal CMOS process. Two electrochemical measurement and analysis methods, chronopotentiometry and voltammetry, can be performed by using the proposed chip and system. The proposed chip and system are verified successfully by performing voltammetry and chronopotentiometry on solutions.

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

NASA Astrophysics Data System (ADS)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed to DDC block, which down converts the data to base-band. The DDC block has NCO, mixer and two chains of Bessel filters (fifth order cascaded integration comb filter, two FIR filters, two half band filters and programmable FIR filters) for in-phase (I) and Quadrature phase (Q) channels. The NCO has 32 bits and is set to match the output frequency of ADC. Further, DDC down samples (decimation) the data and reduces the data rate to 16 MSPS. This data is further decimated and the data rate is reduced down to 4/2/1/0.5/0.25/0.125/0.0625 MSPS for baud lengths 0.25/0.5/1/2/4/8/16 μs respectively. The down sampled data is then fed to decoding block, which performs cross correlation to achieve pulse compression of the binary-phase coded data to obtain better range resolution with maximum possible height coverage. This step improves the signal power by a factor equal to the length of the code. Coherent integration block integrates the decoded data coherently for successive pulses, which improves the signal to noise ratio and reduces the data volume. DDC, decoding and coherent integration blocks are implemented in Xilinx vertex5 FPGA. Till this point, function of all six channels is same for DBS mode and multi-receiver modes. Data from vertex5 FPGA is transferred to PC via GbE-1 interface for multi-modes or to two Analog devices make ADSP-TS201 DSP chips (A and B), via link port for DBS mode. ADSP-TS201 chips perform the normalization, DC removal, windowing, FFT computation and spectral averaging on the data, which is transferred to storage/display PC via GbE-2 interface for real-time data display and data storing. Physical layer of GbE interface is implemented in an external chip (Marvel 88E1111) and MAC layer is implemented internal to vertex5 FPGA. The MCDRx has total 4 GB of DDR2 memory for data storage. Spartan6 FPGA is used for generating timing signals, required for basic operation of the radar and testing of the MCDRx.

Applied digital signal processing systems for vortex flowmeter with digital signal processing.

PubMed

Xu, Ke-Jun; Zhu, Zhi-Hai; Zhou, Yang; Wang, Xiao-Fen; Liu, San-Shan; Huang, Yun-Zhi; Chen, Zhi-Yuan

2009-02-01

The spectral analysis is combined with digital filter to process the vortex sensor signal for reducing the effect of disturbance at low frequency from pipe vibrations and increasing the turndown ratio. Using digital signal processing chip, two kinds of digital signal processing systems are developed to implement these algorithms. One is an integrative system, and the other is a separated system. A limiting amplifier is designed in the input analog condition circuit to adapt large amplitude variation of sensor signal. Some technique measures are taken to improve the accuracy of the output pulse, speed up the response time of the meter, and reduce the fluctuation of the output signal. The experimental results demonstrate the validity of the digital signal processing systems.

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Polymer waveguide grating sensor integrated with a thin-film photodetector

PubMed Central

Song, Fuchuan; Xiao, Jing; Xie, Antonio Jou; Seo, Sang-Woo

2014-01-01

This paper presents a planar waveguide grating sensor integrated with a photodetector (PD) for on-chip optical sensing systems which are suitable for diagnostics in the field and in-situ measurements. III–V semiconductor-based thin-film PD is integrated with a polymer based waveguide grating device on a silicon platform. The fabricated optical sensor successfully discriminates optical spectral characteristics of the polymer waveguide grating from the on-chip PD. In addition, its potential use as a refractive index sensor is demonstrated. Based on a planar waveguide structure, the demonstrated sensor chip may incorporate multiple grating waveguide sensing regions with their own optical detection PDs. In addition, the demonstrated processing is based on a post-integration process which is compatible with silicon complementary metal-oxide semiconductor (CMOS) electronics. Potentially, this leads a compact, chip-scale optical sensing system which can monitor multiple physical parameters simultaneously without need for external signal processing. PMID:24466407

Research and design of intelligent distributed traffic signal light control system based on CAN bus

NASA Astrophysics Data System (ADS)

Chen, Yu

2007-12-01

Intelligent distributed traffic signal light control system was designed based on technologies of infrared, CAN bus, single chip microprocessor (SCM), etc. The traffic flow signal is processed with the core of SCM AT89C51. At the same time, the SCM controls the CAN bus controller SJA1000/transceiver PCA82C250 to build a CAN bus communication system to transmit data. Moreover, up PC realizes to connect and communicate with SCM through USBCAN chip PDIUSBD12. The distributed traffic signal light control system with three control styles of Vehicle flux, remote and PC is designed. This paper introduces the system composition method and parts of hardware/software design in detail.

Research and development of biochip technologies in Taiwan

NASA Astrophysics Data System (ADS)

Ting, Solomon J.; Chiou, Arthur E. T.

2000-07-01

Recent advancements in several genome-sequencing projects have stimulated an enormous interest in microarray DNA chip technology, especially in the biomedical sciences and pharmaceutical industries. The DNA chips facilitated the miniaturization of conventional nucleic acid hybridizations, by either robotically spotting thousands of library cDNAs or in situ synthesis of high-density oligonucleotides onto solid supports. These innovations have found a wide range of applications in molecular biology, especially in studying gene expression and discovering new genes from the global view of genomic analysis. The research and development of this powerful tool has also received great attentions in Taiwan. In this paper, we report the current progresses of our DNA chip project, along with the current status of other biochip projects in Taiwan, such as protein chip, PCR chip, electrophoresis chip, olfactory chip, etc. The new development of biochip technologies integrates the biotechnology with the semiconductor processing, the micro- electro-mechanical, optoelectronic, and digital signal processing technologies. Most of these biochip technologies utilitze optical detection methods for data acquisition and analysis. The strengths and advantages of different approaches are compared and discussed in this report.

Thermal processing of bone: in vitro response of mesenchymal cells to bone-conditioned medium.

PubMed

Sawada, K; Caballé-Serrano, J; Schuldt Filho, G; Bosshardt, D D; Schaller, B; Buser, D; Gruber, R

2015-08-01

The autoclaving, pasteurization, and freezing of bone grafts to remove bacteria and viruses, and for preservation, respectively, is considered to alter biological properties during graft consolidation. Fresh bone grafts release paracrine-like signals that are considered to support tissue regeneration. However, the impact of the autoclaving, pasteurization, and freezing of bone grafts on paracrine signals remains unknown. Therefore, conditioned medium was prepared from porcine cortical bone chips that had undergone thermal processing. The biological properties of the bone-conditioned medium were assessed by examining the changes in expression of target genes in oral fibroblasts. The data showed that conditioned medium obtained from bone chips that had undergone pasteurization and freezing changed the expression of adrenomedullin, pentraxin 3, BTB/POZ domain-containing protein 11, interleukin 11, NADPH oxidase 4, and proteoglycan 4 by at least five-fold in oral fibroblasts. Bone-conditioned medium obtained from autoclaved bone chips, however, failed to change the expression of the respective genes. Also, when bone-conditioned medium was prepared from fresh bone chips, autoclaving blocked the capacity of bone-conditioned medium to modulate gene expression. These in vitro results suggest that pasteurization and freezing of bone grafts preserve the release of biologically active paracrine signals, but autoclaving does not. Copyright © 2015 International Association of Oral and Maxillofacial Surgeons. Published by Elsevier Ltd. All rights reserved.

Photonic band gap materials: towards an all-optical transistor

NASA Astrophysics Data System (ADS)

Florescu, Marian

2002-05-01

The transmission of information as optical signals encoded on light waves traveling through optical fibers and optical networks is increasingly moving to shorter and shorter distance scales. In the near future, optical networking is poised to supersede conventional transmission over electric wires and electronic networks for computer-to-computer communications, chip-to-chip communications, and even on-chip communications. The ever-increasing demand for faster and more reliable devices to process the optical signals offers new opportunities in developing all-optical signal processing systems (systems in which one optical signal controls another, thereby adding "intelligence" to the optical networks). All-optical switches, two-state and many-state all-optical memories, all-optical limiters, all-optical discriminators and all-optical transistors are only a few of the many devices proposed during the last two decades. The "all-optical" label is commonly used to distinguish the devices that do not involve dissipative electronic transport and require essentially no electrical communication of information. The all-optical transistor action was first observed in the context of optical bistability [1] and consists in a strong differential gain regime, in which, for small variations in the input intensity, the output intensity has a very strong variation. This analog operation is for all-optical input what transistor action is for electrical inputs.

Time of flight system on a chip

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas P. (Inventor)

2006-01-01

A CMOS time-of-flight TOF system-on-a-chip SoC for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators CFDs and a Time-to-Digital Converter TDC. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).

A digital pixel cell for address event representation image convolution processing

NASA Astrophysics Data System (ADS)

Camunas-Mesa, Luis; Acosta-Jimenez, Antonio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

On-chip integration of a superconducting microwave circulator and a Josephson parametric amplifier

NASA Astrophysics Data System (ADS)

Rosenthal, Eric I.; Chapman, Benjamin J.; Moores, Bradley A.; Kerckhoff, Joseph; Malnou, Maxime; Palken, D. A.; Mates, J. A. B.; Hilton, G. C.; Vale, L. R.; Ullom, J. N.; Lehnert, K. W.

Recent progress in microwave amplification based on parametric processes in superconducting circuits has revolutionized the measurement of feeble microwave signals. These devices, which operate near the quantum limit, are routinely used in ultralow temperature cryostats to: readout superconducting qubits, search for axionic dark matter, and characterize astrophysical sensors. However, these amplifiers often require ferrite circulators to separate incoming and outgoing traveling waves. For this reason, measurement efficiency and scalability are limited. In order to facilitate the routing of quantum signals we have created a superconducting, on-chip microwave circulator without permanent magnets. We integrate our circulator on-chip with a Josephson parametric amplifier for the purpose of near quantum-limited directional amplification. In this talk I will present a design overview and preliminary measurements.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly.

PubMed

Gall, Oren Z; Zhong, Xiahua; Schulman, Daniel S; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S

2017-06-30

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO 2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly

NASA Astrophysics Data System (ADS)

Gall, Oren Z.; Zhong, Xiahua; Schulman, Daniel S.; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S.

2017-06-01

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Implementation and Performance of GaAs Digital Signal Processing ASICs

NASA Technical Reports Server (NTRS)

Whitaker, William D.; Buchanan, Jeffrey R.; Burke, Gary R.; Chow, Terrance W.; Graham, J. Scott; Kowalski, James E.; Lam, Barbara; Siavoshi, Fardad; Thompson, Matthew S.; Johnson, Robert A.

1993-01-01

The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

NASA Astrophysics Data System (ADS)

Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

2017-10-01

In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

The design of high performance, low power triple-track magnetic sensor chip.

PubMed

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-07-09

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

PubMed Central

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-01-01

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target. PMID:23839231

A Low Cost Single Chip VDL Compatible Transceiver ASIC

NASA Technical Reports Server (NTRS)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

Chip-scale sensor system integration for portable health monitoring.

PubMed

Jokerst, Nan M; Brooke, Martin A; Cho, Sang-Yeon; Shang, Allan B

2007-12-01

The revolution in integrated circuits over the past 50 yr has produced inexpensive computing and communications systems that are powerful and portable. The technologies for these integrated chip-scale sensing systems, which will be miniature, lightweight, and portable, are emerging with the integration of sensors with electronics, optical systems, micromachines, microfluidics, and the integration of chemical and biological materials (soft/wet material integration with traditional dry/hard semiconductor materials). Hence, we stand at a threshold for health monitoring technology that promises to provide wearable biochemical sensing systems that are comfortable, inauspicious, wireless, and battery-operated, yet that continuously monitor health status, and can transmit compressed data signals at regular intervals, or alarm conditions immediately. In this paper, we explore recent results in chip-scale sensor integration technology for health monitoring. The development of inexpensive chip-scale biochemical optical sensors, such as microresonators, that are customizable for high sensitivity coupled with rapid prototyping will be discussed. Ground-breaking work in the integration of chip-scale optical systems to support these optical sensors will be highlighted, and the development of inexpensive Si complementary metal-oxide semiconductor circuitry (which makes up the vast majority of computational systems today) for signal processing and wireless communication with local receivers that lie directly on the chip-scale sensor head itself will be examined.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

K6 linked polyubiquitylation of FADD by CHIP prevents death inducing signaling complex formation suppressing cell death.

PubMed

Seo, Jinho; Lee, Eun-Woo; Shin, Jihye; Seong, Daehyeon; Nam, Young Woo; Jeong, Manhyung; Lee, Seon-Hyeong; Lee, Cheolju; Song, Jaewhan

2018-05-23

Fas-associated death domain (FADD) is an adaptor protein recruiting complexes of caspase 8 to death ligand receptors to induce extrinsic apoptotic cell death in response to a TNF superfamily member. Although, formation of the complex of FADD and caspase 8 upon death stimuli has been studied in detail, posttranslational modifications fine-tuning these processes have yet to be identified. Here we revealed that K6-linked polyubiquitylation of FADD on lysines 149 and 153 mediated by C terminus HSC70-interacting protein (CHIP) plays an important role in preventing formation of the death inducing signaling complex (DISC), thus leading to the suppression of cell death. Cells depleted of CHIP showed higher sensitivity toward death ligands such as FasL and TRAIL, leading to upregulation of DISC formation composed of a death receptor, FADD, and caspase 8. CHIP was able to bind to FADD, induce K6-linked polyubiquitylation of FADD, and suppress DISC formation. By mass spectrometry, lysines 149 and 153 of FADD were found to be responsible for CHIP-mediated FADD ubiquitylation. FADD mutated at these sites was capable of more potent cell death induction as compared with the wild type and was no longer suppressed by CHIP. On the other hand, CHIP deficient in E3 ligase activity was not capable of suppressing FADD function and of FADD ubiquitylation. CHIP depletion in ME-180 cells induced significant sensitization of these cells toward TRAIL in xenograft analyses. These results imply that K6-linked ubiquitylation of FADD by CHIP is a crucial checkpoint in cytokine-dependent extrinsic apoptosis.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

A single-chip 32-channel analog beamformer with 4-ns delay resolution and 768-ns maximum delay range for ultrasound medical imaging with a linear array transducer.

PubMed

Um, Ji-Yong; Kim, Yoon-Jee; Cho, Seong-Eun; Chae, Min-Kyun; Kim, Byungsub; Sim, Jae-Yoon; Park, Hong-June

2015-02-01

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- μ m CMOS process with an active area of 16 mm (2). The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Low-cost TDRSS communications for NASA's long duration balloon project

NASA Technical Reports Server (NTRS)

Israel, David J.

1993-01-01

A new transponder and RF ground support equipment for the NASA Tracking and Data Relay Satellite System (TDRSS) intended to support long duration scientific balloon flights in Antarctica are described. The new balloon class transponder features a highly integrated spread spectrum receiver design based on programmable charge coupled device (CCD) correlators and digital signal processing chips. The correlator chip is a Lincoln Labs 4ABC with four CCD channels. The balloon transponder is capable of reporting an estimate of its input bit error rate using digital signal processing. The TDRSS user RF test set is based on a set of RF ground support equipment capable of providing both the RF communications and direct control and monitoring necessary for transponder testing and a two-way RF link for preflight testing.

Fabrication and Characterization of Bi2Te3-Based Chip-Scale Thermoelectric Energy Harvesting Devices

NASA Astrophysics Data System (ADS)

Cornett, Jane; Chen, Baoxing; Haidar, Samer; Berney, Helen; McGuinness, Pat; Lane, Bill; Gao, Yuan; He, Yifan; Sun, Nian; Dunham, Marc; Asheghi, Mehdi; Goodson, Ken; Yuan, Yi; Najafi, Khalil

2017-05-01

Thermoelectric energy harvesters convert otherwise wasted heat into electrical energy. As a result, they have the potential to play a critical role in the autonomous wireless sensor network signal chain. In this paper, we present work carried out on the development of Bi2Te3-based thermoelectric chip-scale energy harvesting devices. Process flow, device demonstration and characterization are highlighted.

A dissipative self-sustained optomechanical resonator on a silicon chip

NASA Astrophysics Data System (ADS)

Huang, J. G.; Li, Y.; Chin, L. K.; Cai, H.; Gu, Y. D.; Karim, M. F.; Wu, J. H.; Chen, T. N.; Yang, Z. C.; Hao, Y. L.; Qiu, C. W.; Liu, A. Q.

2018-01-01

In this letter, we report the experimental demonstration of a dissipative self-sustained optomechanical resonator on a silicon chip by introducing dissipative optomechanical coupling between a vertically offset bus waveguide and a racetrack optical cavity. Different from conventional blue-detuning limited self-oscillation, the dissipative optomechanical resonator exhibits self-oscillation in the resonance and red detuning regime. The anti-damping effects of dissipative optomechanical coupling are validated by both numerical simulation and experimental results. The demonstration of the dissipative self-sustained optomechanical resonator with an extended working range has potential applications in optomechanical oscillation for on-chip signal modulation and processing.

On-Chip Power-Combining for High-Power Schottky Diode Based Frequency Multipliers

NASA Technical Reports Server (NTRS)

Siles Perez, Jose Vicente (Inventor); Chattopadhyay, Goutam (Inventor); Lee, Choonsup (Inventor); Schlecht, Erich T. (Inventor); Jung-Kubiak, Cecile D. (Inventor); Mehdi, Imran (Inventor)

2015-01-01

A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

Novel Ultrahigh Vacuum System for Chip-Scale Trapped Ion Quantum Computing

NASA Astrophysics Data System (ADS)

Chen, Shaw-Pin; Trapped Team

2011-05-01

This presentation reports the experimental results of an ultrahigh vacuum (UHV) system as a scheme to implement scalable trapped-ion quantum computers that use micro-fabricated ion traps as fundamental building blocks. The novelty of this system resides in our design, material selection, mechanical liability, low complexity of assembly, and reduced signal interference between DC and RF electrodes. Our system utilizes RF isolation and onsite-filtering topologies to attenuate AC signals generated from the resonator. We use a UHV compatible printed circuit board (PCB) material to perform DC routing, while the RF high and RF ground received separated routing via wire-wrapping. The standard PCB fabrication process enabled us to implement ceramic-based filter components adjacent to the chip trap. The DC electrodes are connected to air-side electrical feed through using four 25D adaptors made with polyether ether ketone (PEEK). The assembly process of this system is straight forward and in-chamber structure is self-supporting. We report on initial testing of this concept with a linear chip trap fabricated by the Sandia National Labs.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

The Level 0 Pixel Trigger system for the ALICE experiment

NASA Astrophysics Data System (ADS)

Aglieri Rinella, G.; Kluge, A.; Krivda, M.; ALICE Silicon Pixel Detector project

2007-01-01

The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper.

Optical and electrical interfacing technologies for living cell bio-chips.

PubMed

Shacham-Diamand, Y; Belkin, S; Rishpon, J; Elad, T; Melamed, S; Biran, A; Yagur-Kroll, S; Almog, R; Daniel, R; Ben-Yoav, H; Rabner, A; Vernick, S; Elman, N; Popovtzer, R

2010-06-01

Whole-cell bio-chips for functional sensing integrate living cells on miniaturized platforms made by micro-system-technologies (MST). The cells are integrated, deposited or immersed in a media which is in contact with the chip. The cells behavior is monitored via electrical, electrochemical or optical methods. In this paper we describe such whole-cell biochips where the signal is generated due to the genetic response of the cells. The solid-state platform hosts the biological component, i.e. the living cells, and integrates all the required micro-system technologies, i.e. the micro-electronics, micro-electro optics, micro-electro or magneto mechanics and micro-fluidics. The genetic response of the cells expresses proteins that generate: a. light by photo-luminescence or bioluminescence, b. electrochemical signal by interaction with a substrate, or c. change in the cell impedance. The cell response is detected by a front end unit that converts it to current or voltage amplifies and filters it. The resultant signal is analyzed and stored for further processing. In this paper we describe three examples of whole-cell bio chips, photo-luminescent, bioluminescent and electrochemical, which are based on the genetic response of genetically modified E. coli microbes integrated on a micro-fluidics MEMS platform. We describe the chip outline as well as the basic modeling scheme of such sensors. We discuss the highlights and problems of such system, from the point of view of micro-system-technology.

A MEMS-based, wireless, biometric-like security system

NASA Astrophysics Data System (ADS)

Cross, Joshua D.; Schneiter, John L.; Leiby, Grant A.; McCarter, Steven; Smith, Jeremiah; Budka, Thomas P.

2010-04-01

We present a system for secure identification applications that is based upon biometric-like MEMS chips. The MEMS chips have unique frequency signatures resulting from fabrication process variations. The MEMS chips possess something analogous to a "voiceprint". The chips are vacuum encapsulated, rugged, and suitable for low-cost, highvolume mass production. Furthermore, the fabrication process is fully integrated with standard CMOS fabrication methods. One is able to operate the MEMS-based identification system similarly to a conventional RFID system: the reader (essentially a custom network analyzer) detects the power reflected across a frequency spectrum from a MEMS chip in its vicinity. We demonstrate prototype "tags" - MEMS chips placed on a credit card-like substrate - to show how the system could be used in standard identification or authentication applications. We have integrated power scavenging to provide DC bias for the MEMS chips through the use of a 915 MHz source in the reader and a RF-DC conversion circuit on the tag. The system enables a high level of protection against typical RFID hacking attacks. There is no need for signal encryption, so back-end infrastructure is minimal. We believe this system would make a viable low-cost, high-security system for a variety of identification and authentication applications.

Lab-on-chip systems for integrated bioanalyses

PubMed Central

Madaboosi, Narayanan; Soares, Ruben R.G.; Fernandes, João Tiago S.; Novo, Pedro; Moulas, Geraud; Chu, Virginia

2016-01-01

Biomolecular detection systems based on microfluidics are often called lab-on-chip systems. To fully benefit from the miniaturization resulting from microfluidics, one aims to develop ‘from sample-to-answer’ analytical systems, in which the input is a raw or minimally processed biological, food/feed or environmental sample and the output is a quantitative or qualitative assessment of one or more analytes of interest. In general, such systems will require the integration of several steps or operations to perform their function. This review will discuss these stages of operation, including fluidic handling, which assures that the desired fluid arrives at a specific location at the right time and under the appropriate flow conditions; molecular recognition, which allows the capture of specific analytes at precise locations on the chip; transduction of the molecular recognition event into a measurable signal; sample preparation upstream from analyte capture; and signal amplification procedures to increase sensitivity. Seamless integration of the different stages is required to achieve a point-of-care/point-of-use lab-on-chip device that allows analyte detection at the relevant sensitivity ranges, with a competitive analysis time and cost. PMID:27365042

Research on control law accelerator of digital signal process chip TMS320F28035 for real-time data acquisition and processing

NASA Astrophysics Data System (ADS)

Zhao, Shuangle; Zhang, Xueyi; Sun, Shengli; Wang, Xudong

2017-08-01

TI C2000 series digital signal process (DSP) chip has been widely used in electrical engineering, measurement and control, communications and other professional fields, DSP TMS320F28035 is one of the most representative of a kind. When using the DSP program, need data acquisition and data processing, and if the use of common mode C or assembly language programming, the program sequence, analogue-to-digital (AD) converter cannot be real-time acquisition, often missing a lot of data. The control low accelerator (CLA) processor can run in parallel with the main central processing unit (CPU), and the frequency is consistent with the main CPU, and has the function of floating point operations. Therefore, the CLA coprocessor is used in the program, and the CLA kernel is responsible for data processing. The main CPU is responsible for the AD conversion. The advantage of this method is to reduce the time of data processing and realize the real-time performance of data acquisition.

Single-chip microcomputer for image processing in the photonic measuring system

NASA Astrophysics Data System (ADS)

Smoleva, Olga S.; Ljul, Natalia Y.

2002-04-01

The non-contact measuring system has been designed for rail- track parameters control on the Moscow Metro. It detects some significant parameters: rail-track width, rail-track height, gage, rail-slums, crosslevel, pickets, and car speed. The system consists of three subsystems: non-contact system of rail-track width, height, and gage inspection, non-contact system of rail-slums inspection and subsystem for crosslevel, speed, and pickets detection. Data from subsystems is transferred to pre-processing unit. In order to process data received from subsystems, the single-chip signal processor ADSP-2185 must be used due to providing required processing speed. After data will be processed, it is send to PC, which processes it and outputs it in the readable form.

The design of an adaptive predictive coder using a single-chip digital signal processor

NASA Astrophysics Data System (ADS)

Randolph, M. A.

1985-01-01

A speech coding processor architecture design study has been performed in which Texas Instruments TMS32010 has been selected from among three commercially available digital signal processing integrated circuits and evaluated in an implementation study of real-time Adaptive Predictive Coding (APC). The TMS32010 has been compared with AR&T Bell Laboratories DSP I and Nippon Electric Co. PD7720 and was found to be most suitable for a single chip implementation of APC. A preliminary design system based on TMS32010 has been performed, and several of the hardware and software design issues are discussed. Particular attention was paid to the design of an external memory controller which permits rapid sequential access of external RAM. As a result, it has been determined that a compact hardware implementation of the APC algorithm is feasible based of the TSM32010. Originator-supplied keywords include: vocoders, speech compression, adaptive predictive coding, digital signal processing microcomputers, speech processor architectures, and special purpose processor.

Socket with built-in valves for the interconnection of microfluidic chips to macro constituents.

PubMed

Yang, Zhen; Maeda, Ryutaro

2003-09-26

This paper reports a prototype for a standard connector between a microfluidic chip and the macro world. This prototype demonstrate a fully functioning socket for a microchip to access the outside world by means of fluids, data signals and energy supply. It supports up to 10 channels for the input and output of liquids or gases, as well as compressed air or vacuum lines for pneumatic power lines. The socket has built-in valves for each flow channel. It also contains 28 pins for the connection of electrical signals and power. Built-in valves make it possible to control the flow in each channel independently. A chip ( 11.0 x 11.0 x 0.9 mm) can be mounted into or dismounted from the socket with one touch. The fluidic connectors of the socket are designed to contact vertically on the top of chip. And the electrical connectors (the spring array) of that physically support the chip and contact lead pads at the bottom of chip. No adhesives or solders are used at any contact points. The pressure limit for the connection of working fluids was 0.2 MPa and the current limit for the electrical connections was 1 A. This socket supports both serial and parallel processing applications. It exhibits great potential for developing microfluidic systems efficiently.

MEMS ultrasonic transducer for monitoring of steel structures

NASA Astrophysics Data System (ADS)

Jain, Akash; Greve, David W.; Oppenheim, Irving J.

2002-06-01

Ultrasonic methods can be used to monitor crack propagation, weld failure, or section loss at critical locations in steel structures. However, ultrasonic inspection requires a skilled technician, and most commonly the signal obtained at any inspection is not preserved for later use. A preferred technology would use a MEMS device permanently installed at a critical location, polled remotely, and capable of on-chip signal processing using a signal history. We review questions related to wave geometry, signal levels, flaw localization, and electromechanical design issues for microscale transducers, and then describe the design, characterization, and initial testing of a MEMS transducer to function as a detector array. The device is approximately 1-cm square and was fabricated by the MUMPS process. The chip has 23 sensor elements to function in a phased array geometry, each element containing 180 hexagonal polysilicon diaphragms with a typical leg length of 49 microns and an unloaded natural frequency near 3.5 MHz. We first report characterization studies including capacitance-voltage measurements and admittance measurements, and then report initial experiments using a conventional piezoelectric transducer for excitation, with successful detection of signals in an on-axis transmission experiment and successful source localization from phased array performance in an off-axis transmission experiment.

Surface acoustic wave coding for orthogonal frequency coded devices

NASA Technical Reports Server (NTRS)

Malocha, Donald (Inventor); Kozlovski, Nikolai (Inventor)

2011-01-01

Methods and systems for coding SAW OFC devices to mitigate code collisions in a wireless multi-tag system. Each device producing plural stepped frequencies as an OFC signal with a chip offset delay to increase code diversity. A method for assigning a different OCF to each device includes using a matrix based on the number of OFCs needed and the number chips per code, populating each matrix cell with OFC chip, and assigning the codes from the matrix to the devices. The asynchronous passive multi-tag system includes plural surface acoustic wave devices each producing a different OFC signal having the same number of chips and including a chip offset time delay, an algorithm for assigning OFCs to each device, and a transceiver to transmit an interrogation signal and receive OFC signals in response with minimal code collisions during transmission.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology.« less

Molecular mechanism of the negative regulation of Smad1/5 protein by carboxyl terminus of Hsc70-interacting protein (CHIP).

PubMed

Wang, Le; Liu, Yi-Tong; Hao, Rui; Chen, Lei; Chang, Zhijie; Wang, Hong-Rui; Wang, Zhi-Xin; Wu, Jia-Wei

2011-05-06

The transforming growth factor-β (TGF-β) superfamily of ligands signals along two intracellular pathways, Smad2/3-mediated TGF-β/activin pathway and Smad1/5/8-mediated bone morphogenetic protein pathway. The C terminus of Hsc70-interacting protein (CHIP) serves as an E3 ubiquitin ligase to mediate the degradation of Smad proteins and many other signaling proteins. However, the molecular mechanism for CHIP-mediated down-regulation of TGF-β signaling remains unclear. Here we show that the extreme C-terminal sequence of Smad1 plays an indispensable role in its direct association with the tetratricopeptide repeat (TPR) domain of CHIP. Interestingly, Smad1 undergoes CHIP-mediated polyubiquitination in the absence of molecular chaperones, and phosphorylation of the C-terminal SXS motif of Smad1 enhances the interaction and ubiquitination. We also found that CHIP preferentially binds to Smad1/5 and specifically disrupts the core signaling complex of Smad1/5 and Smad4. We determined the crystal structures of CHIP-TPR in complex with the phosphorylated/pseudophosphorylated Smad1 peptides and with an Hsp70/Hsc70 C-terminal peptide. Structural analyses and subsequent biochemical studies revealed that the distinct CHIP binding affinities of Smad1/5 or Smad2/3 result from the nonconservative hydrophobic residues at R-Smad C termini. Unexpectedly, the C-terminal peptides from Smad1 and Hsp70/Hsc70 bind in the same groove of CHIP-TPR, and heat shock proteins compete with Smad1/5 for CHIP interaction and concomitantly suppress, rather than facilitate, CHIP-mediated Smad ubiquitination. Thus, we conclude that CHIP inhibits the signaling activities of Smad1/5 by recruiting Smad1/5 from the functional R-/Co-Smad complex and further promoting the ubiquitination/degradation of Smad1/5 in a chaperone-independent manner.

A UWB Radar Signal Processing Platform for Real-Time Human Respiratory Feature Extraction Based on Four-Segment Linear Waveform Model.

PubMed

Hsieh, Chi-Hsuan; Chiu, Yu-Fang; Shen, Yi-Hsiang; Chu, Ta-Shun; Huang, Yuan-Hao

2016-02-01

This paper presents an ultra-wideband (UWB) impulse-radio radar signal processing platform used to analyze human respiratory features. Conventional radar systems used in human detection only analyze human respiration rates or the response of a target. However, additional respiratory signal information is available that has not been explored using radar detection. The authors previously proposed a modified raised cosine waveform (MRCW) respiration model and an iterative correlation search algorithm that could acquire additional respiratory features such as the inspiration and expiration speeds, respiration intensity, and respiration holding ratio. To realize real-time respiratory feature extraction by using the proposed UWB signal processing platform, this paper proposes a new four-segment linear waveform (FSLW) respiration model. This model offers a superior fit to the measured respiration signal compared with the MRCW model and decreases the computational complexity of feature extraction. In addition, an early-terminated iterative correlation search algorithm is presented, substantially decreasing the computational complexity and yielding negligible performance degradation. These extracted features can be considered the compressed signals used to decrease the amount of data storage required for use in long-term medical monitoring systems and can also be used in clinical diagnosis. The proposed respiratory feature extraction algorithm was designed and implemented using the proposed UWB radar signal processing platform including a radar front-end chip and an FPGA chip. The proposed radar system can detect human respiration rates at 0.1 to 1 Hz and facilitates the real-time analysis of the respiratory features of each respiration period.

Design of remote car anti-theft system based on ZigBee

NASA Astrophysics Data System (ADS)

Fang, Hong; Yan, GangFeng; Li, Hong Lian

2015-12-01

A set of remote car anti-theft system based on ZigBee and GPRS with ARM11 built-in chip S3C6410 as the controller is designed. This system can detect the alarm information of the car with vibration sensor, pyroelectric sensor and infrared sensor. When the sensor detects any alarm signal, the ZigBee node in sleep will be awakened and then directly send the alarm signal to the microcontroller chip S3C6410 in the control room of the parking lot through ZigBee wireless transceiver module. After S3C6410 processes and analyzes the alarm signal, when any two sensors of the three collect the alarm signal, the LCD will display and generate an alarm and meanwhile it will send the alarm signal to the phone of the user in a wireless manner through the form of short message through GPRS module. Thus, the wireless remote monitoring of the system is realized.

[Fluorescent signal detection of chromatographic chip by algorithms of pyramid connection and Gaussian mixture model].

PubMed

Hu, Beibei; Zhang, Xueqing; Chen, Haopeng; Cui, Daxiang

2011-03-01

We proposed a new algorithm for automatic identification of fluorescent signal. Based on the features of chromatographic chips, mathematic morphology in RGB color space was used to filter and enhance the images, pyramid connection was used to segment the areas of fluorescent signal, and then the method of Gaussian Mixture Model was used to detect the fluorescent signal. Finally we calculated the average fluorescent intensity in obtained fluorescent areas. Our results show that the algorithm has a good efficacy to segment the fluorescent areas, can detect the fluorescent signal quickly and accurately, and finally realize the quantitative detection of fluorescent signal in chromatographic chip.

Single event effects on the APV25 front-end chip

NASA Astrophysics Data System (ADS)

Friedl, M.; Bauer, T.; Pernicka, M.

2003-03-01

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider at CERN will include a Silicon Strip Tracker covering a sensitive area of 206 m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25 μm deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets are inevitable. Moreover, localized ionization can also produce fake signals in the analog circuitry. Eight APV25 chips were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

Millimeter-wave signal generation for a wireless transmission system based on on-chip photonic integrated circuit structures.

PubMed

Guzmán, R; Carpintero, G; Gordon, C; Orbe, L

2016-10-15

We demonstrate and compare two different photonic-based signal sources for generating the carrier wave in a wireless communication link operating in the millimeter-wave range. The first signal source uses the optical heterodyne technique to generate a 113 GHz carrier wave frequency, while the second employs a different technique based on a pulsed mode-locked source with 100 GHz repetition rate frequency. The two optical sources were fabricated in a multi-project wafer run from an active/passive generic integration platform process using standardized building blocks, including multimode interference reflectors which allow us to define the structures on chip, without the need for cleaved facet mirrors. We highlight the superior performance of the mode-locked sources over an optical heterodyne technique. Error-free transmission was achieved in this experiment.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

A neuromorphic VLSI device for implementing 2-D selective attention systems.

PubMed

Indiveri, G

2001-01-01

Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

Enhancement of local surface plasmon resonance (LSPR) effect by biocompatible metal clustering based on ZnO nanorods in Raman measurements.

PubMed

Lee, Sanghwa; Lee, Seung Ho; Paulson, Bjorn; Lee, Jae-Chul; Kim, Jun Ki

2018-06-20

The development of size-selective and non-destructive detection techniques for nanosized biomarkers has many reasons, including the study of living cells and diagnostic applications. We present an approach for Raman signal enhancement on biocompatible sensing chips based on surface enhancement Raman spectroscopy (SERS). A sensing chip was fabricated by forming a ZnO-based nanorod structure so that the Raman enhancement occurred at a gap of several tens to several hundred nanometers. The effect of coffee-ring formation was eliminated by introducing the porous ZnO nanorods for the bio-liquid sample. A peculiarity of this approach is that the gold sputtered on the ZnO nanorods initially grows at their heads forming clusters, as confirmed by secondary electron microscopy. This clustering was verified by finite element analysis to be the main factor for enhancement of local surface plasmon resonance (LSPR). This clustering property and the ability to adjust the size of the nanorods enabled the signal acquisition points to be refined using confocal based Raman spectroscopy, which could be applied directly to the sensor chip based on the optimization process in this experiment. It was demonstrated by using common cancer cell lines that cell growth was high on these gold-clad ZnO nanorod-based surface-enhanced Raman substrates. The porosity of the sensing chip, the improved structure for signal enhancement, and the cell assay make these gold-coated ZnO nanorods substrates promising biosensing chips with excellent potential for detecting nanometric biomarkers secreted by cells. Copyright © 2018 Elsevier B.V. All rights reserved.

Integrated Electrode Arrays for Neuro-Prosthetic Implants

NASA Technical Reports Server (NTRS)

Brandon, Erik; Mojarradi, Mohammede

2003-01-01

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

NASA Astrophysics Data System (ADS)

Bugiel, Sz.; Dasgupta, R.; Firlej, M.; Fiutowski, T.; Idzik, M.; Kuczynska, M.; Moron, J.; Swientek, K.; Szumlak, T.

2016-02-01

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications

PubMed Central

Chang, Chia-Lin; Chang, Chih-Wei; Huang, Hong-Yi; Hsu, Chen-Ming; Huang, Chia-Hsuan; Chiou, Jin-Chern; Luo, Ching-Hsing

2010-01-01

This work describes a power-efficient bio-potential acquisition device for long-term healthcare applications that is implemented using novel microelectromechanical dry electrodes (MDE) and a low power bio-potential processing chip. Using micromachining technology, an attempt is also made to enhance the sensing reliability and stability by fabricating a diamond-shaped MDE (DS-MDE) that has a satisfactory self-stability capability and superior electric conductivity when attached onto skin without any extra skin tissue injury technology. To acquire differential bio-potentials such as ECG signals, the proposed processing chip fabricated in a standard CMOS process has a high common mode rejection ratio (C.M.R.R.) differential amplifier and a 12-bit analog-to-digital converter (ADC). Use of the proposed system and integrate simple peripheral commercial devices can obtain the ECG signal efficiently without additional skin tissue injury and ensure continuous monitoring more than 70 hours with a 400 mAh battery. PMID:22399907

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

A power-efficient bio-potential acquisition device with DS-MDE sensors for long-term healthcare monitoring applications.

PubMed

Chang, Chia-Lin; Chang, Chih-Wei; Huang, Hong-Yi; Hsu, Chen-Ming; Huang, Chia-Hsuan; Chiou, Jin-Chern; Luo, Ching-Hsing

2010-01-01

This work describes a power-efficient bio-potential acquisition device for long-term healthcare applications that is implemented using novel microelectromechanical dry electrodes (MDE) and a low power bio-potential processing chip. Using micromachining technology, an attempt is also made to enhance the sensing reliability and stability by fabricating a diamond-shaped MDE (DS-MDE) that has a satisfactory self-stability capability and superior electric conductivity when attached onto skin without any extra skin tissue injury technology. To acquire differential bio-potentials such as ECG signals, the proposed processing chip fabricated in a standard CMOS process has a high common mode rejection ratio (C.M.R.R.) differential amplifier and a 12-bit analog-to-digital converter (ADC). Use of the proposed system and integrate simple peripheral commercial devices can obtain the ECG signal efficiently without additional skin tissue injury and ensure continuous monitoring more than 70 hours with a 400 mAh battery.

Analysis of acoustic emission signals and monitoring of machining processes

PubMed

Govekar; Gradisek; Grabec

2000-03-01

Monitoring of a machining process on the basis of sensor signals requires a selection of informative inputs in order to reliably characterize and model the process. In this article, a system for selection of informative characteristics from signals of multiple sensors is presented. For signal analysis, methods of spectral analysis and methods of nonlinear time series analysis are used. With the aim of modeling relationships between signal characteristics and the corresponding process state, an adaptive empirical modeler is applied. The application of the system is demonstrated by characterization of different parameters defining the states of a turning machining process, such as: chip form, tool wear, and onset of chatter vibration. The results show that, in spite of the complexity of the turning process, the state of the process can be well characterized by just a few proper characteristics extracted from a representative sensor signal. The process characterization can be further improved by joining characteristics from multiple sensors and by application of chaotic characteristics.

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

Ubiquitin ligase CHIP functions as an oncogene and activates the AKT signaling pathway in prostate cancer.

PubMed

Cheng, Li; Zang, Jin; Dai, Han-Jue; Li, Feng; Guo, Feng

2018-07-01

Carboxyl terminus of Hsc-70-interacting protein (CHIP) is an E3 ubiquitin ligase that induces the ubiquitination and degradation of numerous tumor-associated proteins and serves as a suppressor or promoter in tumor progression. To date, the molecular mechanism of CHIP in prostate cancer remains unknown. Therefore, the present study investigated the biological function of CHIP in prostate cancer cells and obtained evidence that CHIP expression is upregulated in prostate cancer tissues. The CHIP vector was introduced into DU145 cancer cells and the cell biological behaviour was examined through a series of experiments, including cell growth, cell apoptosis and migration and invasion assays. The results indicated that the overexpression of CHIP in DU145 prostatic cancer cells promoted cell proliferation through activation of the protein kinase B (AKT) signaling pathway, which subsequently increased cyclin D1 protein levels and decreased p21 and p27 protein levels. The overexpression of CHIP significantly increased the migration and invasion of the DU145 cells, which is possible due to activation of the AKT signaling pathway and upregulation of vimentin. The expression level of CHIP was observed to be increased in human prostate cancer tissues compared with the adjacent normal tissue. Furthermore, the CHIP expression level exhibited a positively association with the Gleason score of the patents. These findings indicate that CHIP functions as an oncogene in prostate cancer.

A long distance voice transmission system based on the white light LED

NASA Astrophysics Data System (ADS)

Tian, Chunyu; Wei, Chang; Wang, Yulian; Wang, Dachi; Yu, Benli; Xu, Feng

2017-10-01

A long distance voice transmission system based on a visible light communication technology (VLCT) is proposed in the paper. Our proposed system includes transmitter, receiver and the voice signal processing of single chip microcomputer. In the compact-sized LED transmitter, we use on-off-keying and not-return-to-zero (OOK-NRZ) to easily realize high speed modulation, and then systematic complexity is reduced. A voice transmission system, which possesses the properties of the low-noise and wide modulation band, is achieved by the design of high efficiency receiving optical path and using filters to reduce noise from the surrounding light. To improve the speed of the signal processing, we use single chip microcomputer to code and decode voice signal. Furthermore, serial peripheral interface (SPI) is adopted to accurately transmit voice signal data. The test results of our proposed system show that the transmission distance of this system is more than100 meters with the maximum data rate of 1.5 Mbit/s and a SNR of 30dB. This system has many advantages, such as simple construction, low cost and strong practicality. Therefore, it has extensive application prospect in the fields of the emergency communication and indoor wireless communication, etc.

Adaptive WTA with an analog VLSI neuromorphic learning chip.

PubMed

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

Engineering of Neuron Growth and Enhancing Cell-Chip Communication via Mixed SAMs.

PubMed

Markov, Aleksandr; Maybeck, Vanessa; Wolf, Nikolaus; Mayer, Dirk; Offenhäusser, Andreas; Wördenweber, Roger

2018-06-06

The interface between cells and inorganic surfaces represents one of the key elements for bioelectronics experiments and applications ranging from cell cultures and bioelectronics devices to medical implants. In the present paper, we describe a way to tailor the biocompatibility of substrates in terms of cell growth and to significantly improve cell-chip communication, and we also demonstrate the reusability of the substrates for cell experiments. All these improvements are achieved by coating the substrates or chips with a self-assembled monolayer (SAM) consisting of a mixture of organic molecules, (3-aminopropyl)-triethoxysilane and (3-glycidyloxypropyl)-trimethoxysilane. By varying the ratio of these molecules, we are able to tune the cell density and live/dead ratios of rat cortical neurons cultured directly on the mixed SAM as well as neurons cultured on protein-coated SAMs. Furthermore, the use of the SAM leads to a significant improvement in cell-chip communications. Action potential signals of up to 9.4 ± 0.6 mV (signal-to-noise ratio up to 47) are obtained for HL-1 cells on microelectrode arrays. Finally, we demonstrate that the SAMs facilitate a reusability of the samples for all cell experiments with little re-processing.

(abstract) A High Throughput 3-D Inner Product Processor

NASA Technical Reports Server (NTRS)

Daud, Tuan

1996-01-01

A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated.

Bio-Inspired Microsystem for Robust Genetic Assay Recognition

PubMed Central

Lue, Jaw-Chyng; Fang, Wai-Chi

2008-01-01

A compact integrated system-on-chip (SoC) architecture solution for robust, real-time, and on-site genetic analysis has been proposed. This microsystem solution is noise-tolerable and suitable for analyzing the weak fluorescence patterns from a PCR prepared dual-labeled DNA microchip assay. In the architecture, a preceding VLSI differential logarithm microchip is designed for effectively computing the logarithm of the normalized input fluorescence signals. A posterior VLSI artificial neural network (ANN) processor chip is used for analyzing the processed signals from the differential logarithm stage. A single-channel logarithmic circuit was fabricated and characterized. A prototype ANN chip with unsupervised winner-take-all (WTA) function was designed, fabricated, and tested. An ANN learning algorithm using a novel sigmoid-logarithmic transfer function based on the supervised backpropagation (BP) algorithm is proposed for robustly recognizing low-intensity patterns. Our results show that the trained new ANN can recognize low-fluorescence patterns better than an ANN using the conventional sigmoid function. PMID:18566679

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

PubMed Central

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

PubMed

López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Electronic pictures from charged-coupled devices

NASA Technical Reports Server (NTRS)

Mccann, D. H.; Turly, A. P.; White, M.

1979-01-01

Imaging system uses charge-coupled devices (CCD's) to generate TV-like pictures with high resolution, sensitivity, and signal-to-noise ratio. It combines detectors for five spectral bands as well as processing and control circuitry all on single silicon chip.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

A CMOS ASIC Design for SiPM Arrays

PubMed Central

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2012-01-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

Detection of the ODMR signal of a nitrogen vacancy centre in nanodiamond in propagating surface plasmons

NASA Astrophysics Data System (ADS)

Al-Baiaty, Zahraa; Cumming, Benjamin P.; Gan, Xiaosong; Gu, Min

2018-02-01

We demonstrate that the optically detected magnetic resonance (ODMR) signal of a nitrogen vacancy (NV) centre can be coupled to propagating surface plasmons for the detection of the NV centre spin states, and of external magnetic fields. By coupling the spin dependent luminescence signal of a NV centre in a nanodiamond (ND) to a chemically synthesized silver nanowire, we demonstrate the readout of the ODMR signal as a reduction in the surface plasmon polariton intensity, with improved contrast in comparison to the emission from the NV centre. Furthermore, on the application of a permanent magnetic field from zero to 13 G, we demonstrate that the Zeeman splitting of the magnetic spin states of the nitrogen vacancy centre ground states can also be detected in the coupled surface plasmons. This is an important step in the development of a compact on-chip information processing system utilizing the nitrogen vacancy in nanodiamond as an on-chip source with efficient magnetometry sensing properties.

Techniques of EMG signal analysis: detection, processing, classification and applications

PubMed Central

Hussain, M.S.; Mohd-Yasin, F.

2006-01-01

Electromyography (EMG) signals can be used for clinical/biomedical applications, Evolvable Hardware Chip (EHW) development, and modern human computer interaction. EMG signals acquired from muscles require advanced methods for detection, decomposition, processing, and classification. The purpose of this paper is to illustrate the various methodologies and algorithms for EMG signal analysis to provide efficient and effective ways of understanding the signal and its nature. We further point up some of the hardware implementations using EMG focusing on applications related to prosthetic hand control, grasp recognition, and human computer interaction. A comparison study is also given to show performance of various EMG signal analysis methods. This paper provides researchers a good understanding of EMG signal and its analysis procedures. This knowledge will help them develop more powerful, flexible, and efficient applications. PMID:16799694

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

VHDL Implementation of Sigma-Delta Analog To Digital Converter

NASA Astrophysics Data System (ADS)

Chavan, R. N.; Chougule, D. G.

2010-11-01

Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

A multi-channel low-power system-on-chip for single-unit recording and narrowband wireless transmission of neural signal.

PubMed

Bonfanti, A; Ceravolo, M; Zambra, G; Gusmeroli, R; Spinelli, A S; Lacaita, A L; Angotzi, G N; Baranauskas, G; Fadiga, L

2010-01-01

This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole system is designed to work with 64 channels demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. A digital data compression, based on the detection of action potentials and storage of correspondent waveforms, allows the use of a 1.25-Mbit/s binary FSK wireless transmission. This moderate bit-rate and a low frequency deviation, Manchester-coded modulation are crucial for exploiting a narrowband wireless link and an efficient embeddable antenna. The chip is realized in a 0.35- εm CMOS process with a power consumption of 105 εW per channel (269 εW per channel with an extended transmission range of 4 m) and an area of 3.1 × 2.7 mm(2). The transmitted signal is captured by a digital TV tuner and demodulated by a wideband phase-locked loop (PLL), and then sent to a PC via an FPGA module. The system has been tested for electrical specifications and its functionality verified in in-vivo neural recording experiments.

A design of Si-based nanoplasmonic structure as an antenna and reception amplifier for visible light communication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, J. H.; Lin, Z. Y.; Liu, P.

2014-10-21

Visible light communication has been widely investigated due to its larger bandwidth and higher bit rate, and it can combine with the indoor illumination system that makes it more convenient to carry out. Receiving and processing the visible light signal on chip request for nanophotonics devices performing well. However, conventional optical device cannot be used for light-on-chip integration at subwavelength dimensions due to the diffraction limit. Herein, we propose a design of Si-based nanoplasmonic structure as an antenna and reception amplifier for visible light communication based on the interaction between Si nanoparticle and Au nanorod. This device integrates the uniquemore » scattering property of high-refractive index dielectric Si nanoparticles, whose scattering spectrum is dependent on the particle size, with the localized surface plasmon resonance of Au nanorod. We calculated the spectra collected by plane detector and near field distribution of nanostructure, and theoretically demonstrate that the proposed device can act as good receiver, amplifier and superlens during the visible light signal receiving and processing. Besides, unlike some other designs of nanoantenna devices focused less on how to detect the signals, our hybrid nanoantenna can realize the transfer between the scattering source and the detector effectively by Au nanorod waveguides. These findings suggest that the designed nanoplasmonic structure is expected to be used in on-chip nanophotonics as antenna, spectral splitter and demultiplexer for visible light communication.« less

Multichannel detection of ionic currents through two nanopores fabricated on integrated Si3N4 membranes.

PubMed

Yanagi, Itaru; Akahori, Rena; Aoki, Mayu; Harada, Kunio; Takeda, Ken-Ichi

2016-08-16

Integration of solid-state nanopores and multichannel detection of signals from each nanopore are effective measures for realizing high-throughput nanopore sensors. In the present study, we demonstrated fabrication of Si3N4 membrane arrays and the simultaneous measurement of ionic currents through two nanopores formed in two adjacent membranes. Membranes with thicknesses as low as 6.4 nm and small nanopores with diameters of less than 2 nm could be fabricated using the poly-Si sacrificial-layer process and multilevel pulse-voltage injection. Using the fabricated nanopore membranes, we successfully achieved simultaneous detection of clear ionic-current blockades when single-stranded short homopolymers (poly(dA)60) passed through two nanopores. In addition, we investigated the signal crosstalk and leakage current among separated chambers. When two nanopores were isolated on the front surface of the membrane, there was no signal crosstalk or leakage current between the chambers. However, when two nanopores were isolated on the backside of the Si substrate, signal crosstalk and leakage current were observed owing to high-capacitance coupling between the chambers and electrolysis of water on the surface of the Si substrate. The signal crosstalk and leakage current could be suppressed by oxidizing the exposed Si surface in the membrane chip. Finally, the observed ionic-current blockade when poly(dA)60 passed through the nanopore in the oxidized chip was approximately half of that observed in the non-oxidized chip.

LSST camera readout chip ASPIC: test tools

NASA Astrophysics Data System (ADS)

Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

2012-02-01

The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

Fully chip-embedded automation of a multi-step lab-on-a-chip process using a modularized timer circuit.

PubMed

Kang, Junsu; Lee, Donghyeon; Heo, Young Jin; Chung, Wan Kyun

2017-11-07

For highly-integrated microfluidic systems, an actuation system is necessary to control the flow; however, the bulk of actuation devices including pumps or valves has impeded the broad application of integrated microfluidic systems. Here, we suggest a microfluidic process control method based on built-in microfluidic circuits. The circuit is composed of a fluidic timer circuit and a pneumatic logic circuit. The fluidic timer circuit is a serial connection of modularized timer units, which sequentially pass high pressure to the pneumatic logic circuit. The pneumatic logic circuit is a NOR gate array designed to control the liquid-controlling process. By using the timer circuit as a built-in signal generator, multi-step processes could be done totally inside the microchip without any external controller. The timer circuit uses only two valves per unit, and the number of process steps can be extended without limitation by adding timer units. As a demonstration, an automation chip has been designed for a six-step droplet treatment, which entails 1) loading, 2) separation, 3) reagent injection, 4) incubation, 5) clearing and 6) unloading. Each process was successfully performed for a pre-defined step-time without any external control device.

An Energy-Efficient Algorithm for Wearable Electrocardiogram Signal Processing in Ubiquitous Healthcare Applications

PubMed Central

Sodhro, Ali Hassan; Sodhro, Gul Hassan; Lohano, Sonia; Pirbhulal, Sandeep

2018-01-01

Rapid progress and emerging trends in miniaturized medical devices have enabled the un-obtrusive monitoring of physiological signals and daily activities of everyone’s life in a prominent and pervasive manner. Due to the power-constrained nature of conventional wearable sensor devices during ubiquitous sensing (US), energy-efficiency has become one of the highly demanding and debatable issues in healthcare. This paper develops a single chip-based wearable wireless electrocardiogram (ECG) monitoring system by adopting analog front end (AFE) chip model ADS1292R from Texas Instruments. The developed chip collects real-time ECG data with two adopted channels for continuous monitoring of human heart activity. Then, these two channels and the AFE are built into a right leg drive right leg drive (RLD) driver circuit with lead-off detection and medical graded test signal. Human ECG data was collected at 60 beats per minute (BPM) to 120 BPM with 60 Hz noise and considered throughout the experimental set-up. Moreover, notch filter (cutoff frequency 60 Hz), high-pass filter (cutoff frequency 0.67 Hz), and low-pass filter (cutoff frequency 100 Hz) with cut-off frequencies of 60 Hz, 0.67 Hz, and 100 Hz, respectively, were designed with bilinear transformation for rectifying the power-line noise and artifacts while extracting real-time ECG signals. Finally, a transmission power control-based energy-efficient (ETPC) algorithm is proposed, implemented on the hardware and then compared with the several conventional TPC methods. Experimental results reveal that our developed chip collects real-time ECG data efficiently, and the proposed ETPC algorithm achieves higher energy savings of 35.5% with a slightly larger packet loss ratio (PLR) as compared to conventional TPC (e.g., constant TPC, Gao’s, and Xiao’s methods). PMID:29558433

An Energy-Efficient Algorithm for Wearable Electrocardiogram Signal Processing in Ubiquitous Healthcare Applications.

PubMed

Sodhro, Ali Hassan; Sangaiah, Arun Kumar; Sodhro, Gul Hassan; Lohano, Sonia; Pirbhulal, Sandeep

2018-03-20

Rapid progress and emerging trends in miniaturized medical devices have enabled the un-obtrusive monitoring of physiological signals and daily activities of everyone's life in a prominent and pervasive manner. Due to the power-constrained nature of conventional wearable sensor devices during ubiquitous sensing (US), energy-efficiency has become one of the highly demanding and debatable issues in healthcare. This paper develops a single chip-based wearable wireless electrocardiogram (ECG) monitoring system by adopting analog front end (AFE) chip model ADS1292R from Texas Instruments. The developed chip collects real-time ECG data with two adopted channels for continuous monitoring of human heart activity. Then, these two channels and the AFE are built into a right leg drive right leg drive (RLD) driver circuit with lead-off detection and medical graded test signal. Human ECG data was collected at 60 beats per minute (BPM) to 120 BPM with 60 Hz noise and considered throughout the experimental set-up. Moreover, notch filter (cutoff frequency 60 Hz), high-pass filter (cutoff frequency 0.67 Hz), and low-pass filter (cutoff frequency 100 Hz) with cut-off frequencies of 60 Hz, 0.67 Hz, and 100 Hz, respectively, were designed with bilinear transformation for rectifying the power-line noise and artifacts while extracting real-time ECG signals. Finally, a transmission power control-based energy-efficient (ETPC) algorithm is proposed, implemented on the hardware and then compared with the several conventional TPC methods. Experimental results reveal that our developed chip collects real-time ECG data efficiently, and the proposed ETPC algorithm achieves higher energy savings of 35.5% with a slightly larger packet loss ratio (PLR) as compared to conventional TPC (e.g., constant TPC, Gao's, and Xiao's methods).

Integrated three-dimensional optical MEMS for chip-based fluorescence detection

NASA Astrophysics Data System (ADS)

Hung, Kuo-Yung; Tseng, Fan-Gang; Khoo, Hwa-Seng

2009-04-01

This paper presents a novel fluorescence sensing chip for parallel protein microarray detection in the context of a 3-in-1 protein chip system. This portable microchip consists of a monolithic integration of CMOS-based avalanche photo diodes (APDs) combined with a polymer micro-lens, a set of three-dimensional (3D) inclined mirrors for separating adjacent light signals and a low-noise transformer-free dc-dc boost mini-circuit to power the APDs (ripple below 1.28 mV, 0-5 V input, 142 V and 12 mA output). We fabricated our APDs using the planar CMOS process so as to facilitate the post-CMOS integration of optical MEMS components such as the lenses. The APD arrays were arranged in unique circular patterns appropriate for detecting the specific fluorescently labelled protein spots in our study. The array-type APDs were designed so as to compensate for any alignment error as detected by a positional error signal algorithm. The condenser lens was used as a structure for light collection to enhance the fluorescent signals by about 25%. This element also helped to reduce the light loss due to surface absorption. We fabricated an inclined mirror to separate two adjacent fluorescent signals from different specimens. Excitation using evanescent waves helped reduce the interference of the excitation light source. This approach also reduced the number of required optical lenses and minimized the complexity of the structural design. We achieved detection floors for anti-rabbit IgG and Cy5 fluorescent dye as low as 0.5 ng/µl (~3.268 nM). We argue that the intrinsic nature of point-to-point and batch-detection methods as showcased in our chip offers advantages over the serial-scanning approach used in traditional scanner systems. In addition, our system is low cost and lightweight.

Crossbar Nanocomputer Development

DTIC Science & Technology

2012-04-01

their utilization. Areas such as neuromorphic computing, signal processing, arithmetic processing, and crossbar computing are only some of the...due to its intrinsic, network-on- chip flexibility to re-route around defects. Preliminary efforts in crossbar computing have been demonstrated by...they approach their scaling limits [2]. Other applications that memristive devices are suited for include FPGA [3], encryption [4], and neuromorphic

A three-channel LED driver with single line transportation technique

NASA Astrophysics Data System (ADS)

Yu, Caideng; Du, Yiying; Jiang, Qiao; Zhou, Yun; Lv, Jian

2012-10-01

Designed a three-channel LED driver, realized the single-wire transmission of cascade signal between the drive IC of LED. Including the MCU digital interface, date register, clock synchronization, PWM grayscale adjustment circuit, as well as high voltage driver circuit for LED, etc… The driver control LED displaying 256 gray. Chip will generate synchronous sampling clock signals according to the received serial signals, when 24 bits dates have been received, the output pin begins to transport the dates followed-up which are automotive shaped to the input of the next chip. When the date receiving becomes low level that represent RESET, the red, green and blue channels will export different signals based on different input dates. Through the external MCU, it is realized the Separate luminance, and by connecting chips in series it achieved the control of outdoor big screen' colorful display. The automatic shaping forward technique makes the number of chips cascading immune to the limitations of signal transmission, but only limited by the refresh speed.

Single chip camera active pixel sensor

NASA Technical Reports Server (NTRS)

Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

2003-01-01

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Towards a Chemiresistive Sensor-Integrated Electronic Nose: A Review

PubMed Central

Chiu, Shih-Wen; Tang, Kea-Tiong

2013-01-01

Electronic noses have potential applications in daily life, but are restricted by their bulky size and high price. This review focuses on the use of chemiresistive gas sensors, metal-oxide semiconductor gas sensors and conductive polymer gas sensors in an electronic nose for system integration to reduce size and cost. The review covers the system design considerations and the complementary metal-oxide-semiconductor integrated technology for a chemiresistive gas sensor electronic nose, including the integrated sensor array, its readout interface, and pattern recognition hardware. In addition, the state-of-the-art technology integrated in the electronic nose is also presented, such as the sensing front-end chip, electronic nose signal processing chip, and the electronic nose system-on-chip. PMID:24152879

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

Transmission of wireless neural signals through a 0.18 µm CMOS low-power amplifier.

PubMed

Gazziro, M; Braga, C F R; Moreira, D A; Carvalho, A C P L F; Rodrigues, J F; Navarro, J S; Ardila, J C M; Mioni, D P; Pessatti, M; Fabbro, P; Freewin, C; Saddow, S E

2015-01-01

In the field of Brain Machine Interfaces (BMI) researchers still are not able to produce clinically viable solutions that meet the requirements of long-term operation without the use of wires or batteries. Another problem is neural compatibility with the electrode probes. One of the possible ways of approaching these problems is the use of semiconductor biocompatible materials (silicon carbide) combined with an integrated circuit designed to operate with low power consumption. This paper describes a low-power neural signal amplifier chip, named Cortex, fabricated using 0.18 μm CMOS process technology with all electronics integrated in an area of 0.40 mm(2). The chip has 4 channels, total power consumption of only 144 μW, and is impedance matched to silicon carbide biocompatible electrodes.

An evaluation of the directed flow graph methodology

NASA Technical Reports Server (NTRS)

Snyder, W. E.; Rajala, S. A.

1984-01-01

The applicability of the Directed Graph Methodology (DGM) to the design and analysis of special purpose image and signal processing hardware was evaluated. A special purpose image processing system was designed and described using DGM. The design, suitable for very large scale integration (VLSI) implements a region labeling technique. Two computer chips were designed, both using metal-nitride-oxide-silicon (MNOS) technology, as well as a functional system utilizing those chips to perform real time region labeling. The system is described in terms of DGM primitives. As it is currently implemented, DGM is inappropriate for describing synchronous, tightly coupled, special purpose systems. The nature of the DGM formalism lends itself more readily to modeling networks of general purpose processors.

Integrated Flexible Electronic Devices Based on Passive Alignment for Physiological Measurement

PubMed Central

Ryu, Jin Hwa; Byun, Sangwon; Baek, In-Bok; Lee, Bong Kuk; Jang, Won Ick; Jang, Eun-Hye; Kim, Ah-Yung; Yu, Han Yung

2017-01-01

This study proposes a simple method of fabricating flexible electronic devices using a metal template for passive alignment between chip components and an interconnect layer, which enabled efficient alignment with high accuracy. An electrocardiogram (ECG) sensor was fabricated using 20 µm thick polyimide (PI) film as a flexible substrate to demonstrate the feasibility of the proposed method. The interconnect layer was fabricated by a two-step photolithography process and evaporation. After applying solder paste, the metal template was placed on top of the interconnect layer. The metal template had rectangular holes at the same position as the chip components on the interconnect layer. Rectangular hole sizes were designed to account for alignment tolerance of the chips. Passive alignment was performed by simply inserting the components in the holes of the template, which resulted in accurate alignment with positional tolerance of less than 10 µm based on the structural design, suggesting that our method can efficiently perform chip mounting with precision. Furthermore, a fabricated flexible ECG sensor was easily attachable to the curved skin surface and able to measure ECG signals from a human subject. These results suggest that the proposed method can be used to fabricate epidermal sensors, which are mounted on the skin to measure various physiological signals. PMID:28420219

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

All-optical control of light on a graphene-on-silicon nitride chip using thermo-optic effect.

PubMed

Qiu, Ciyuan; Yang, Yuxing; Li, Chao; Wang, Yifang; Wu, Kan; Chen, Jianping

2017-12-06

All-optical signal processing avoids the conversion between optical signals and electronic signals and thus has the potential to achieve a power efficient photonic system. Micro-scale all-optical devices for light manipulation are the key components in the all-optical signal processing and have been built on the semiconductor platforms (e.g., silicon and III-V semiconductors). However, the two-photon absorption (TPA) effect and the free-carrier absorption (FCA) effect in these platforms deteriorate the power handling and limit the capability to realize complex functions. Instead, silicon nitride (Si 3 N 4 ) provides a possibility to realize all-optical large-scale integrated circuits due to its insulator nature without TPA and FCA. In this work, we investigate the physical dynamics of all-optical control on a graphene-on-Si 3 N 4 chip based on thermo-optic effect. In the experimental demonstration, a switching response time constant of 253.0 ns at a switching energy of ~50 nJ is obtained with a device dimension of 60 μm × 60 μm, corresponding to a figure of merit (FOM) of 3.0 nJ mm. Detailed coupled-mode theory based analysis on the thermo-optic effect of the device has been performed.

Rapid prototyping of update algorithm of discrete Fourier transform for real-time signal processing

NASA Astrophysics Data System (ADS)

Kakad, Yogendra P.; Sherlock, Barry G.; Chatapuram, Krishnan V.; Bishop, Stephen

2001-10-01

An algorithm is developed in the companion paper, to update the existing DFT to represent the new data series that results when a new signal point is received. Updating the DFT in this way uses less computation than directly evaluating the DFT using the FFT algorithm, This reduces the computational order by a factor of log2 N. The algorithm is able to work in the presence of data window function, for use with rectangular window, the split triangular, Hanning, Hamming, and Blackman windows. In this paper, a hardware implementation of this algorithm, using FPGA technology, is outlined. Unlike traditional fully customized VLSI circuits, FPGAs represent a technical break through in the corresponding industry. The FPGA implements thousands of gates of logic in a single IC chip and it can be programmed by users at their site in a few seconds or less depending on the type of device used. The risk is low and the development time is short. The advantages have made FPGAs very popular for rapid prototyping of algorithms in the area of digital communication, digital signal processing, and image processing. Our paper addresses the related issues of implementation using hardware descriptive language in the development of the design and the subsequent downloading on the programmable hardware chip.

Real-time encoding and compression of neuronal spikes by metal-oxide memristors

NASA Astrophysics Data System (ADS)

Gupta, Isha; Serb, Alexantrou; Khiat, Ali; Zeitler, Ralf; Vassanelli, Stefano; Prodromakis, Themistoklis

2016-09-01

Advanced brain-chip interfaces with numerous recording sites bear great potential for investigation of neuroprosthetic applications. The bottleneck towards achieving an efficient bio-electronic link is the real-time processing of neuronal signals, which imposes excessive requirements on bandwidth, energy and computation capacity. Here we present a unique concept where the intrinsic properties of memristive devices are exploited to compress information on neural spikes in real-time. We demonstrate that the inherent voltage thresholds of metal-oxide memristors can be used for discriminating recorded spiking events from background activity and without resorting to computationally heavy off-line processing. We prove that information on spike amplitude and frequency can be transduced and stored in single devices as non-volatile resistive state transitions. Finally, we show that a memristive device array allows for efficient data compression of signals recorded by a multi-electrode array, demonstrating the technology's potential for building scalable, yet energy-efficient on-node processors for brain-chip interfaces.

Real-time encoding and compression of neuronal spikes by metal-oxide memristors

PubMed Central

Gupta, Isha; Serb, Alexantrou; Khiat, Ali; Zeitler, Ralf; Vassanelli, Stefano; Prodromakis, Themistoklis

2016-01-01

Advanced brain-chip interfaces with numerous recording sites bear great potential for investigation of neuroprosthetic applications. The bottleneck towards achieving an efficient bio-electronic link is the real-time processing of neuronal signals, which imposes excessive requirements on bandwidth, energy and computation capacity. Here we present a unique concept where the intrinsic properties of memristive devices are exploited to compress information on neural spikes in real-time. We demonstrate that the inherent voltage thresholds of metal-oxide memristors can be used for discriminating recorded spiking events from background activity and without resorting to computationally heavy off-line processing. We prove that information on spike amplitude and frequency can be transduced and stored in single devices as non-volatile resistive state transitions. Finally, we show that a memristive device array allows for efficient data compression of signals recorded by a multi-electrode array, demonstrating the technology's potential for building scalable, yet energy-efficient on-node processors for brain-chip interfaces. PMID:27666698

Extreme temperature robust optical sensor designs and fault-tolerant signal processing

DOEpatents

Riza, Nabeel Agha [Oviedo, FL; Perez, Frank [Tujunga, CA

2012-01-17

Silicon Carbide (SiC) probe designs for extreme temperature and pressure sensing uses a single crystal SiC optical chip encased in a sintered SiC material probe. The SiC chip may be protected for high temperature only use or exposed for both temperature and pressure sensing. Hybrid signal processing techniques allow fault-tolerant extreme temperature sensing. Wavelength peak-to-peak (or null-to-null) collective spectrum spread measurement to detect wavelength peak/null shift measurement forms a coarse-fine temperature measurement using broadband spectrum monitoring. The SiC probe frontend acts as a stable emissivity Black-body radiator and monitoring the shift in radiation spectrum enables a pyrometer. This application combines all-SiC pyrometry with thick SiC etalon laser interferometry within a free-spectral range to form a coarse-fine temperature measurement sensor. RF notch filtering techniques improve the sensitivity of the temperature measurement where fine spectral shift or spectrum measurements are needed to deduce temperature.

Design of a Multi-Channel Front-End Readout ASIC With Low Noise and Large Dynamic Input Range for APD-Based PET Imaging

NASA Astrophysics Data System (ADS)

Fang, X. C.; Hu-Guo, Ch.; Ollivier-Henry, N.; Brasse, D.; Hu, Y.

2010-06-01

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e -+ 10 e-/pF. In this paper the prototype is presented for both its theoretical analysis and its test results.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Organic printed photonics: From microring lasers to integrated circuits

PubMed Central

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-01-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

Organic printed photonics: From microring lasers to integrated circuits.

PubMed

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-09-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

A high-speed on-chip pseudo-random binary sequence generator for multi-tone phase calibration

NASA Astrophysics Data System (ADS)

Gommé, Liesbeth; Vandersteen, Gerd; Rolain, Yves

2011-07-01

An on-chip reference generator is conceived by adopting the technique of decimating a pseudo-random binary sequence (PRBS) signal in parallel sequences. This is of great benefit when high-speed generation of PRBS and PRBS-derived signals is the objective. The design implemented standard CMOS logic is available in commercial libraries to provide the logic functions for the generator. The design allows the user to select the periodicity of the PRBS and the PRBS-derived signals. The characterization of the on-chip generator marks its performance and reveals promising specifications.

Optical time division multiplexer on silicon chip.

PubMed

Aboketaf, Abdelsalam A; Elshaari, Ali W; Preble, Stefan F

2010-06-21

In this work, we experimentally demonstrate a novel broadband optical time division multiplexer (OTDM) on a silicon chip. The fabricated devices generate 20 Gb/s and 40 Gb/s signals starting from a 5 Gb/s input signal. The proposed design has a small footprint of 1mm x 1mm. The system is inherently broadband with a bandwidth of over 100nm making it suitable for high-speed optical networks on chip.

A research of a high precision multichannel data acquisition system

NASA Astrophysics Data System (ADS)

Zhong, Ling-na; Tang, Xiao-ping; Yan, Wei

2013-08-01

The output signals of the focusing system in lithography are analog. To convert the analog signals into digital ones which are more flexible and stable to process, a desirable data acquisition system is required. The resolution of data acquisition, to some extent, affects the accuracy of focusing. In this article, we first compared performance between the various kinds of analog-to-digital converters (ADC) available on the market at the moment. Combined with the specific requirements (sampling frequency, converting accuracy, numbers of channels etc) and the characteristics (polarization, amplitude range etc) of the analog signals, the model of the ADC to be used as the core chip in our hardware design was determined. On this basis, we chose other chips needed in the hardware circuit that would well match with ADC, then the overall hardware design was obtained. Validation of our data acquisition system was verified through experiments and it can be demonstrated that the system can effectively realize the high resolution conversion of the multi-channel analog signals and give the accurate focusing information in lithography.

Minimum Requirements for Accurate and Efficient Real-Time On-Chip Spike Sorting

PubMed Central

Navajas, Joaquin; Barsakcioglu, Deren Y.; Eftekhar, Amir; Jackson, Andrew; Constandinou, Timothy G.; Quiroga, Rodrigo Quian

2014-01-01

Background Extracellular recordings are performed by inserting electrodes in the brain, relaying the signals to external power-demanding devices, where spikes are detected and sorted in order to identify the firing activity of different putative neurons. A main caveat of these recordings is the necessity of wires passing through the scalp and skin in order to connect intracortical electrodes to external amplifiers. The aim of this paper is to evaluate the feasibility of an implantable platform (i.e. a chip) with the capability to wirelessly transmit the neural signals and perform real-time on-site spike sorting. New Method We computationally modelled a two-stage implementation for online, robust, and efficient spike sorting. In the first stage, spikes are detected on-chip and streamed to an external computer where mean templates are created and sent back to the chip. In the second stage, spikes are sorted in real-time through template matching. Results We evaluated this procedure using realistic simulations of extracellular recordings and describe a set of specifications that optimise performance while keeping to a minimum the signal requirements and the complexity of the calculations. Comparison with Existing Methods A key bottleneck for the development of long-term BMIs is to find an inexpensive method for real-time spike sorting. Here, we simulated a solution to this problem that uses both offline and online processing of the data. Conclusions Hardware implementations of this method therefore enable low-power long-term wireless transmission of multiple site extracellular recordings, with application to wireless BMIs or closed-loop stimulation designs. PMID:24769170

High-throughput particle manipulation by hydrodynamic, electrokinetic, and dielectrophoretic effects in an integrated microfluidic chip

PubMed Central

Li, Shunbo; Li, Ming; Bougot-Robin, Kristelle; Cao, Wenbin; Yeung Yeung Chau, Irene; Li, Weihua; Wen, Weijia

2013-01-01

Integrating different steps on a chip for cell manipulations and sample preparation is of foremost importance to fully take advantage of microfluidic possibilities, and therefore make tests faster, cheaper and more accurate. We demonstrated particle manipulation in an integrated microfluidic device by applying hydrodynamic, electroosmotic (EO), electrophoretic (EP), and dielectrophoretic (DEP) forces. The process involves generation of fluid flow by pressure difference, particle trapping by DEP force, and particle redirect by EO and EP forces. Both DC and AC signals were applied, taking advantages of DC EP, EO and AC DEP for on-chip particle manipulation. Since different types of particles respond differently to these signals, variations of DC and AC signals are capable to handle complex and highly variable colloidal and biological samples. The proposed technique can operate in a high-throughput manner with thirteen independent channels in radial directions for enrichment and separation in microfluidic chip. We evaluated our approach by collecting Polystyrene particles, yeast cells, and E. coli bacteria, which respond differently to electric field gradient. Live and dead yeast cells were separated successfully, validating the capability of our device to separate highly similar cells. Our results showed that this technique could achieve fast pre-concentration of colloidal particles and cells and separation of cells depending on their vitality. Hydrodynamic, DC electrophoretic and DC electroosmotic forces were used together instead of syringe pump to achieve sufficient fluid flow and particle mobility for particle trapping and sorting. By eliminating bulky mechanical pumps, this new technique has wide applications for in situ detection and analysis. PMID:24404011

High-throughput particle manipulation by hydrodynamic, electrokinetic, and dielectrophoretic effects in an integrated microfluidic chip.

PubMed

Li, Shunbo; Li, Ming; Bougot-Robin, Kristelle; Cao, Wenbin; Yeung Yeung Chau, Irene; Li, Weihua; Wen, Weijia

2013-01-01

Integrating different steps on a chip for cell manipulations and sample preparation is of foremost importance to fully take advantage of microfluidic possibilities, and therefore make tests faster, cheaper and more accurate. We demonstrated particle manipulation in an integrated microfluidic device by applying hydrodynamic, electroosmotic (EO), electrophoretic (EP), and dielectrophoretic (DEP) forces. The process involves generation of fluid flow by pressure difference, particle trapping by DEP force, and particle redirect by EO and EP forces. Both DC and AC signals were applied, taking advantages of DC EP, EO and AC DEP for on-chip particle manipulation. Since different types of particles respond differently to these signals, variations of DC and AC signals are capable to handle complex and highly variable colloidal and biological samples. The proposed technique can operate in a high-throughput manner with thirteen independent channels in radial directions for enrichment and separation in microfluidic chip. We evaluated our approach by collecting Polystyrene particles, yeast cells, and E. coli bacteria, which respond differently to electric field gradient. Live and dead yeast cells were separated successfully, validating the capability of our device to separate highly similar cells. Our results showed that this technique could achieve fast pre-concentration of colloidal particles and cells and separation of cells depending on their vitality. Hydrodynamic, DC electrophoretic and DC electroosmotic forces were used together instead of syringe pump to achieve sufficient fluid flow and particle mobility for particle trapping and sorting. By eliminating bulky mechanical pumps, this new technique has wide applications for in situ detection and analysis.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to begin laying the foundations for both the SiC front-end optical chip fabrication techniques for high pressure gas species sensing as well as the design, assembly, and test of a portable high pressure high temperature calibration test cell chamber for introducing gas species. This calibration cell will be used in the remaining months for proposed first stage high pressure high temperature gas species sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for themore » mechanical elements as well as the optical systems are provided. Photographs of the fabricated calibration test chamber cell, the optical sensor setup with the calibration cell, the SiC sample chip holder, and relevant signal processing mathematics are provided. Initial experimental data from both the optical sensor and fabricated test gas species SiC chips is provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature high pressure gas species detection optical sensor technology.« less

A fully integrated distance readout ELISA-Chip for point-of-care testing with sample-in-answer-out capability.

PubMed

Liu, Dan; Li, Xingrui; Zhou, Junkai; Liu, Shibo; Tian, Tian; Song, Yanling; Zhu, Zhi; Zhou, Leiji; Ji, Tianhai; Yang, Chaoyong

2017-10-15

Enzyme-linked immunosorbent assay (ELISA) is a popular laboratory technique for detection of disease-specific protein biomarkers with high specificity and sensitivity. However, ELISA requires labor-intensive and time-consuming procedures with skilled operators and spectroscopic instrumentation. Simplification of the procedures and miniaturization of the devices are crucial for ELISA-based point-of-care (POC) testing in resource-limited settings. Here, we present a fully integrated, instrument-free, low-cost and portable POC platform which integrates the process of ELISA and the distance readout into a single microfluidic chip. Based on manipulation using a permanent magnet, the process is initiated by moving magnetic beads with capture antibody through different aqueous phases containing ELISA reagents to form bead/antibody/antigen/antibody sandwich structure, and finally converts the molecular recognition signal into a highly sensitive distance readout for visual quantitative bioanalysis. Without additional equipment and complicated operations, our integrated ELISA-Chip with distance readout allows ultrasensitive quantitation of disease biomarkers within 2h. The ELISA-Chip method also showed high specificity, good precision and great accuracy. Furthermore, the ELISA-Chip system is highly applicable as a sandwich-based platform for the detection of a variety of protein biomarkers. With the advantages of visual analysis, easy operation, high sensitivity, and low cost, the integrated sample-in-answer-out ELISA-Chip with distance readout shows great potential for quantitative POCT in resource-limited settings. Copyright © 2017. Published by Elsevier B.V.

L-connect routing of die surface pads to the die edge for stacking in a 3D array

DOEpatents

Petersen, Robert W.

2000-01-01

Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

A single active nanoelectromechanical tuning fork front-end radio-frequency receiver

NASA Astrophysics Data System (ADS)

Bartsch, Sebastian T.; Rusu, A.; Ionescu, Adrian M.

2012-06-01

Nanoelectromechanical systems (NEMS) offer the potential to revolutionize fundamental methods employed for signal processing in today’s telecommunication systems, owing to their spectral purity and the prospect of integration with existing technology. In this work we present a novel, front-end receiver topology based on a single device silicon nanoelectromechanical mixer-filter. The operation is demonstrated by using the signal amplification in a field effect transistor (FET) merged into a tuning fork resonator. The combination of both a transistor and a mechanical element into a hybrid unit enables on-chip functionality and performance previously unachievable in silicon. Signal mixing, filtering and demodulation are experimentally demonstrated at very high frequencies ( > 100 MHz), maintaining a high quality factor of Q = 800 and stable operation at near ambient pressure (0.1 atm) and room temperature (T = 300 K). The results show that, ultimately miniaturized, silicon NEMS can be utilized to realize multi-band, single-chip receiver systems based on NEMS mixer-filter arrays with reduced system complexity and power consumption.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

DOEpatents

Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

2012-03-20

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

A configurable and low-power mixed signal SoC for portable ECG monitoring applications.

PubMed

Kim, Hyejung; Kim, Sunyoung; Van Helleputte, Nick; Artes, Antonio; Konijnenburg, Mario; Huisken, Jos; Van Hoof, Chris; Yazicioglu, Refet Firat

2014-04-01

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

NASA Astrophysics Data System (ADS)

Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

2013-08-01

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

Nonreciprocal frequency conversion in a multimode microwave optomechanical circuit

NASA Astrophysics Data System (ADS)

Feofanov, A. K.; Bernier, N. R.; Toth, L. D.; Koottandavida, A.; Kippenberg, T. J.

Nonreciprocal devices such as isolators, circulators, and directional amplifiers are pivotal to quantum signal processing with superconducting circuits. In the microwave domain, commercially available nonreciprocal devices are based on ferrite materials. They are barely compatible with superconducting quantum circuits, lossy, and cannot be integrated on chip. Significant potential exists for implementing non-magnetic chip-scale nonreciprocal devices using microwave optomechanical circuits. Here we demonstrate a possibility of nonreciprocal frequency conversion in a multimode microwave optomechanical circuit using solely optomechanical interaction between modes. The conversion scheme and the results reflecting the actual progress on the experimental implementation of the scheme will be presented.

A fast one-chip event-preprocessor and sequencer for the Simbol-X Low Energy Detector

NASA Astrophysics Data System (ADS)

Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

2010-12-01

We present an FPGA-based digital camera electronics consisting of an Event-Preprocessor (EPP) for on-board data preprocessing and a related Sequencer (SEQ) to generate the necessary signals to control the readout of the detector. The device has been originally designed for the Simbol-X low energy detector (LED). The EPP operates on 64×64 pixel images and has a real-time processing capability of more than 8000 frames per second. The already working releases of the EPP and the SEQ are now combined into one Digital-Camera-Controller-Chip (D3C).

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units.

PubMed

Rath, N; Kato, S; Levesque, J P; Mauel, M E; Navratil, G A; Peng, Q

2014-04-01

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

Signal Amplification in Field Effect-Based Sandwich Enzyme-Linked Immunosensing by Tuned Buffer Concentration with Ionic Strength Adjuster.

PubMed

Kumar, Satyendra; Kumar, Narendra; Panda, Siddhartha

2016-04-01

Miniaturization of the sandwich enzyme-based immunosensor has several advantages but could result in lower signal strength due to lower enzyme loading. Hence, technologies for amplification of the signal are needed. Signal amplification in a field effect-based electrochemical immunosensor utilizing chip-based ELISA is presented in this work. First, the molarities of phosphate buffer saline (PBS) and concentrations of KCl as ionic strength adjuster were optimized to maximize the GOx glucose-based enzymatic reactions in a beaker for signal amplification measured by change in the voltage shift with an EIS device (using 20 μl of solution) and validated with a commercial pH meter (using 3 ml of solution). The PBS molarity of 100 μM with 25 mM KCl provided the maximum voltage shift. These optimized buffer conditions were further verified for GOx immobilized on silicon chips, and similar trends with decreased PBS molarity were obtained; however, the voltage shift values obtained on chip reaction were lower as compared to the reactions occurring in the beaker. The decreased voltage shift with immobilized enzyme on chip could be attributed to the increased Km (Michaelis-Menten constant) values in the immobilized GOx. Finally, a more than sixfold signal enhancement (from 8 to 47 mV) for the chip-based sandwich immunoassay was obtained by altering the PBS molarity from 10 to 100 μM with 25 mM KCl.

Real time SAR processing

NASA Technical Reports Server (NTRS)

Premkumar, A. B.; Purviance, J. E.

1990-01-01

A simplified model for the SAR imaging problem is presented. The model is based on the geometry of the SAR system. Using this model an expression for the entire phase history of the received SAR signal is formulated. From the phase history, it is shown that the range and the azimuth coordinates for a point target image can be obtained by processing the phase information during the intrapulse and interpulse periods respectively. An architecture for a VLSI implementation for the SAR signal processor is presented which generates images in real time. The architecture uses a small number of chips, a new correlation processor, and an efficient azimuth correlation process.

CHIP Regulates Osteoclast Formation through Promoting TRAF6 Protein Degradation

PubMed Central

Li, Shan; Shu, Bing; Zhang, Yanquan; Li, Jia; Guo, Junwei; Wang, Yinyin; Ren, Fangli; Xiao, Guozhi; Chang, Zhijie; Chen, Di

2014-01-01

Objective Carboxyl terminus of Hsp70-interacting protein (CHIP or STUB1) is an E3 ligase and regulates the stability of several proteins which are involved in tumor growth and metastasis. However, the role of CHIP in bone growth and bone remodeling in vivo has not been reported. The objective of this study is to investigate the role and mechanism of CHIP in regulation of bone mass and bone remodeling. Methods The bone phenotype of Chip−/− mice was examined by histology, histomorphometry and micro-CT analyses. The regulatory mechanism of CHIP on the degradation of TRAF6 and the inhibition of NF-κB signaling was examined by immunoprecipitation (IP), western blotting and luciferase reporter assays. Results In this study, we found that deletion of the Chip gene leads to osteopenic phenotype and increased osteoclast formation. We further found that TRAF6, as a novel substrate of CHIP, is up-regulated in Chip−/− osteoclasts. TRAF6 is critical for RANKL-induced osteoclastogenesis. TRAF6 is an adaptor protein which functions as an E3 ligase to regulate the activation of TAK1 and the I-κB kinase (IKK) and is a key regulator of NF-κB signaling. CHIP interacts with TRAF6 to promote TRAF6 ubiquitination and proteasome degradation. CHIP inhibits p65 nuclear translocation, leading to the repression of the TRAF6-mediated NF-κB transcription. Conclusion CHIP inhibits NF-κB signaling via promoting TRAF6 degradation and plays an important role in osteoclastogenesis and bone remodeling, suggesting that it may be a novel therapeutic target for the treatment of bone loss associated diseases. PMID:24578159

Design and DSP implementation of star image acquisition and star point fast acquiring and tracking

NASA Astrophysics Data System (ADS)

Zhou, Guohui; Wang, Xiaodong; Hao, Zhihang

2006-02-01

Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper, the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing, a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design, the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory, DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme, DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us, the data in five expanded windows including stars are moved into the internal memory of DSP, and in 1.6ms, five star coordinates are achieved in the star tracking stage.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nabeel A. Riza

The goals of the first six months of this project were to lay the foundations for both the SiC front-end optical chip fabrication as well as the free-space laser beam interferometer designs and preliminary tests. In addition, a Phase I goal was to design and experimentally build the high temperature and pressure infrastructure and test systems that will be used in the next 6 months for proposed sensor experimentation and data processing. All these goals have been achieved and are described in detail in the report. Both design process and diagrams for the mechanical elements as well as the opticalmore » systems are provided. In addition, photographs of the fabricated SiC optical chips, the high temperature & pressure test chamber instrument, the optical interferometer, the SiC sample chip holder, and signal processing data are provided. The design and experimentation results are summarized to give positive conclusions on the proposed novel high temperature optical sensor technology. The goals of the second six months of this project were to conduct high temperature sensing tests using the test chamber and optical sensing instrument designs developed in the first part of the project. In addition, a Phase I goal was to develop the basic processing theory and physics for the proposed first sensor experimentation and data processing. All these goals have been achieved and are described in detail. Both optical experimental design process and sensed temperature are provided. In addition, photographs of the fabricated SiC optical chips after deployment in the high temperature test chamber are shown from a material study point-of-view.« less

Nanohole Array-directed Trapping of Mammalian Mitochondria Enabling Single Organelle Analysis

PubMed Central

Kumar, Shailabh; Wolken, Gregory G.; Wittenberg, Nathan J.; Arriaga, Edgar A.; Oh, Sang-Hyun

2016-01-01

We present periodic nanohole arrays fabricated in free-standing metal-coated nitride films as a platform for trapping and analyzing single organelles. When a microliter-scale droplet containing mitochondria is dispensed above the nanohole array, the combination of evaporation and capillary flow directs individual mitochondria to the nanoholes. Mammalian mitochondria arrays were rapidly formed on chip using this technique without any surface modification steps, microfluidic interconnects or external power sources. The trapped mitochondria were depolarized on chip using an ionophore with results showing that the organelle viability and behavior were preserved during the on-chip assembly process. Fluorescence signal related to mitochondrial membrane potential was obtained from single mitochondria trapped in individual nanoholes revealing statistical differences between the behavior of polarized vs. depolarized mammalian mitochondria. This technique provides a fast and stable route for droplet-based directed localization of organelles-on-a-chip with minimal limitations and complexity, as well as promotes integration with other optical or electrochemical detection techniques. PMID:26593329

A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

PubMed

Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

2016-06-18

This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

PubMed Central

Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

2016-01-01

This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments. PMID:27322288

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

NASA Astrophysics Data System (ADS)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

Low-cost mm-wave Doppler/FMCW transceivers for ground surveillance applications

NASA Astrophysics Data System (ADS)

Hansen, H. J.; Lindop, R. W.; Majstorovic, D.

2005-12-01

A 35 GHz Doppler CW/FMCW transceiver (Equivalent Radiated Power ERP=30dBm) has been assembled and its operation described. Both instantaneous beat signals (relating to range in FMCW mode) and Doppler signals (relating to targets moving at ~1.5 ms -1) exhibit audio frequencies. Consequently, the radar processing is provided by laptop PC using its inbuilt video-audio media system with appropriate MathWorks software. The implications of radar-on-chip developments are addressed.

Plasmonically amplified fluorescence bioassay with microarray format

NASA Astrophysics Data System (ADS)

Gogalic, S.; Hageneder, S.; Ctortecka, C.; Bauch, M.; Khan, I.; Preininger, Claudia; Sauer, U.; Dostalek, J.

2015-05-01

Plasmonic amplification of fluorescence signal in bioassays with microarray detection format is reported. A crossed relief diffraction grating was designed to couple an excitation laser beam to surface plasmons at the wavelength overlapping with the absorption and emission bands of fluorophore Dy647 that was used as a label. The surface of periodically corrugated sensor chip was coated with surface plasmon-supporting gold layer and a thin SU8 polymer film carrying epoxy groups. These groups were employed for the covalent immobilization of capture antibodies at arrays of spots. The plasmonic amplification of fluorescence signal on the developed microarray chip was tested by using interleukin 8 sandwich immunoassay. The readout was performed ex situ after drying the chip by using a commercial scanner with high numerical aperture collecting lens. Obtained results reveal the enhancement of fluorescence signal by a factor of 5 when compared to a regular glass chip.

Advanced Analog Signal Processing for Fuzing Final Report CRADA No. TC-1306-96

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fu, C. Y.; Spencer, D.

The purpose of this CRADA between LLNL and Kaman Aerospace/Raymond Engineering Operations (Raymond) was to demonstrate the feasibility of using Analog/Digital Neural Network (ANN) Technology for advanced signal processing, fuzing, and other applications. This cooperation sought to Ieverage the expertise and capabilities of both parties--Raymond to develop the signature recognition hardware system, using Raymond’s extensive experience in the area of system development plus Raymond’s knowledge of military applications, and LLNL to apply ANN and related technologies to an area of significant interest to the United States government. This CRADA effort was anticipated to be a three-year project consisting of threemore » phases: Phase I, Proof-of-Principle Demonstration; Phase II, Proof-of-Design, involving the development of a form-factored integrated sensor and ANN technology processo~ and Phase III, Final Design and Release of the integrated sensor and ANN fabrication process: Under Phase I, to be conducted during calendar year 1996, Raymond was to deliver to LLNL an architecture (design) for an ANN chip. LLNL was to translate the design into a stepper mask and to produce and test a prototype chip from the Raymond design.« less

On-chip WDM mode-division multiplexing interconnection with optional demodulation function.

PubMed

Ye, Mengyuan; Yu, Yu; Chen, Guanyu; Luo, Yuchan; Zhang, Xinliang

2015-12-14

We propose and fabricate a wavelength-division-multiplexing (WDM) compatible and multi-functional mode-division-multiplexing (MDM) integrated circuit, which can perform the mode conversion and multiplexing for the incoming multipath WDM signals, avoiding the wavelength conflict. An phase-to-intensity demodulation function can be optionally applied within the circuit while performing the mode multiplexing. For demonstration, 4 × 10 Gb/s non-return-to-zero differential phase shift keying (NRZ-DPSK) signals are successfully processed, with open and clear eye diagrams. Measured bit error ratio (BER) results show less than 1 dB receive sensitivity variation for three modes and four wavelengths with demodulation. In the case without demodulation, the average power penalties at 4 wavelengths are -1.5, -3 and -3.5 dB for TE₀-TE₀, TE₀-TE₁ and TE₀-TE₂ mode conversions, respectively. The proposed flexible scheme can be used at the interface of long-haul and on-chip communication systems.

Integrated test system of infrared and laser data based on USB 3.0

NASA Astrophysics Data System (ADS)

Fu, Hui Quan; Tang, Lin Bo; Zhang, Chao; Zhao, Bao Jun; Li, Mao Wen

2017-07-01

Based on USB3.0, this paper presents the design method of an integrated test system for both infrared image data and laser signal data processing module. The core of the design is FPGA logic control, the design uses dual-chip DDR3 SDRAM to achieve high-speed laser data cache, and receive parallel LVDS image data through serial-to-parallel conversion chip, and it achieves high-speed data communication between the system and host computer through the USB3.0 bus. The experimental results show that the developed PC software realizes the real-time display of 14-bit LVDS original image after 14-to-8 bit conversion and JPEG2000 compressed image after decompression in software, and can realize the real-time display of the acquired laser signal data. The correctness of the test system design is verified, indicating that the interface link is normal.

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

PubMed

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Stanford Hardware Development Program

NASA Technical Reports Server (NTRS)

Peterson, A.; Linscott, I.; Burr, J.

1986-01-01

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

Development Of A Three-Dimensional Circuit Integration Technology And Computer Architecture

NASA Astrophysics Data System (ADS)

Etchells, R. D.; Grinberg, J.; Nudd, G. R.

1981-12-01

This paper is the first of a series 1,2,3 describing a range of efforts at Hughes Research Laboratories, which are collectively referred to as "Three-Dimensional Microelectronics." The technology being developed is a combination of a unique circuit fabrication/packaging technology and a novel processing architecture. The packaging technology greatly reduces the parasitic impedances associated with signal-routing in complex VLSI structures, while simultaneously allowing circuit densities orders of magnitude higher than the current state-of-the-art. When combined with the 3-D processor architecture, the resulting machine exhibits a one- to two-order of magnitude simultaneous improvement over current state-of-the-art machines in the three areas of processing speed, power consumption, and physical volume. The 3-D architecture is essentially that commonly referred to as a "cellular array", with the ultimate implementation having as many as 512 x 512 processors working in parallel. The three-dimensional nature of the assembled machine arises from the fact that the chips containing the active circuitry of the processor are stacked on top of each other. In this structure, electrical signals are passed vertically through the chips via thermomigrated aluminum feedthroughs. Signals are passed between adjacent chips by micro-interconnects. This discussion presents a broad view of the total effort, as well as a more detailed treatment of the fabrication and packaging technologies themselves. The results of performance simulations of the completed 3-D processor executing a variety of algorithms are also presented. Of particular pertinence to the interests of the focal-plane array community is the simulation of the UNICORNS nonuniformity correction algorithms as executed by the 3-D architecture.

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

PubMed

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Smart single-chip gas sensor microsystem

NASA Astrophysics Data System (ADS)

Hagleitner, C.; Hierlemann, A.; Lange, D.; Kummer, A.; Kerness, N.; Brand, O.; Baltes, H.

2001-11-01

Research activity in chemical gas sensing is currently directed towards the search for highly selective (bio)chemical layer materials, and to the design of arrays consisting of different partially selective sensors that permit subsequent pattern recognition and multi-component analysis. Simultaneous use of various transduction platforms has been demonstrated, and the rapid development of integrated-circuit technology has facilitated the fabrication of planar chemical sensors and sensors based on three-dimensional microelectromechanical systems. Complementary metal-oxide silicon processes have previously been used to develop gas sensors based on metal oxides and acoustic-wave-based sensor devices. Here we combine several of these developments to fabricate a smart single-chip chemical microsensor system that incorporates three different transducers (mass-sensitive, capacitive and calorimetric), all of which rely on sensitive polymeric layers to detect airborne volatile organic compounds. Full integration of the microelectronic and micromechanical components on one chip permits control and monitoring of the sensor functions, and enables on-chip signal amplification and conditioning that notably improves the overall sensor performance. The circuitry also includes analog-to-digital converters, and an on-chip interface to transmit the data to off-chip recording units. We expect that our approach will provide a basis for the further development and optimization of gas microsystems.

Solid-State Photomultiplier with Integrated Front End Electronics

NASA Astrophysics Data System (ADS)

Christian, James; Stapels, Christopher; Johnson, Erik; Mukhopadhyay, Sharmistha; Jie Chen, Xiao; Miskimen, Rory

2009-10-01

The instrumentation cost of physics experiments has been reduced per channel, by the use of solid-state detectors, but these cost-effective techniques have not been translated to scintillation-based detectors. When considering photodetectors, the cost per channel is determined by the use of high-voltage, analog-to-digital converters, BNC cables, and any other ancillary devices. The overhead associated with device operation limits the number of channels for the detector system, while potentially limiting the scope of physics that can be explored. The PRIMEX experiment at JLab, which is being designed to measure the radiative widths of the η and η' pseudo-scalar mesons for a more comprehensive understanding of QCD at low energies, is an example where CMOS solid-state photomultipliers (SSPMs) can be implemented. The ubiquitous nature of CMOS allows for on-chip signal processing to provide front-end electronics within the detector package. We present the results of the device development for the PRIMEX calorimeter, discussing the characteristics of SSPMs, the potential cost savings, and experimental results of on-chip signal processing.

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

NASA Astrophysics Data System (ADS)

Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

1995-02-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

1997-01-01

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

An accuracy aware low power wireless EEG unit with information content based adaptive data compression.

PubMed

Tolbert, Jeremy R; Kabali, Pratik; Brar, Simeranjit; Mukhopadhyay, Saibal

2009-01-01

We present a digital system for adaptive data compression for low power wireless transmission of Electroencephalography (EEG) data. The proposed system acts as a base-band processor between the EEG analog-to-digital front-end and RF transceiver. It performs a real-time accuracy energy trade-off for multi-channel EEG signal transmission by controlling the volume of transmitted data. We propose a multi-core digital signal processor for on-chip processing of EEG signals, to detect signal information of each channel and perform real-time adaptive compression. Our analysis shows that the proposed approach can provide significant savings in transmitter power with minimal impact on the overall signal accuracy.

A low-power, high-throughput maximum-likelihood convolutional decoder chip for NASA's 30/20 GHz program

NASA Technical Reports Server (NTRS)

Mccallister, R. D.; Crawford, J. J.

1981-01-01

It is pointed out that the NASA 30/20 GHz program will place in geosynchronous orbit a technically advanced communication satellite which can process time-division multiple access (TDMA) information bursts with a data throughput in excess of 4 GBPS. To guarantee acceptable data quality during periods of signal attenuation it will be necessary to provide a significant forward error correction (FEC) capability. Convolutional decoding (utilizing the maximum-likelihood techniques) was identified as the most attractive FEC strategy. Design trade-offs regarding a maximum-likelihood convolutional decoder (MCD) in a single-chip CMOS implementation are discussed.

Silicon waveguide with four zero-dispersion wavelengths and its application in on-chip octave-spanning supercontinuum generation.

PubMed

Zhang, Lin; Lin, Qiang; Yue, Yang; Yan, Yan; Beausoleil, Raymond G; Willner, Alan E

2012-01-16

We propose a novel silicon waveguide that exhibits four zero-dispersion wavelengths for the first time, to the best of our knowledge, with a flattened dispersion over a 670-nm bandwidth. This holds a great potential for exploration of new nonlinear effects and achievement of ultra-broadband signal processing on a silicon chip. As an example, we show that an octave-spanning supercontinuum assisted by dispersive wave generation can be obtained in silicon, over a wavelength range from 1217 to 2451 nm, almost from bandgap wavelength to half-bandgap wavelength. Input pulse is greatly compressed to 10 fs.

Binary/Analog CCD Correlator Development.

DTIC Science & Technology

1981-07-01

architecture , design and performance of a general purpose, 1,024-stage, programmable transversal filter implemented in CCD/NMOS technology is described. The device features programmability of the reference signal, the filter length and weighting coefficient resolution. Off-ship circuitry is minimized by incorporating both analog and digital support circuitry, on-chip. This results in a monolithic analog signal processing system that has the flexibility to be operated in nine programmable configurations, from 1,024-stages by 1-bit, to 128-stages by 8-bits. The versatility

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2010-10-26

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2015-07-07

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald; Yuan, Thomas

2012-07-10

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

NASA Astrophysics Data System (ADS)

Seiler, David G.

1997-10-01

A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

NASA Astrophysics Data System (ADS)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

On-chip passive three-port circuit of all-optical ordered-route transmission.

PubMed

Liu, Li; Dong, Jianji; Gao, Dingshan; Zheng, Aoling; Zhang, Xinliang

2015-05-13

On-chip photonic circuits of different specific functions are highly desirable and becoming significant demands in all-optical communication network. Especially, the function to control the transmission directions of the optical signals in integrated circuits is a fundamental research. Previous schemes, such as on-chip optical circulators, are mostly realized by Faraday effect which suffers from material incompatibilities between semiconductors and magneto-optical materials. Achieving highly functional circuits in which light circulates in a particular direction with satisfied performances are still difficult in pure silicon photonics platform. Here, we propose and experimentally demonstrate a three-port passive device supporting optical ordered-route transmission based on silicon thermo-optic effect for the first time. By injecting strong power from only one port, the light could transmit through the three ports in a strict order (1→2, 2→3, 3→1) while be blocked in the opposite order (1→3, 3→2, 2→1). The blocking extinction ratios and operation bandwidths have been investigated in this paper. Moreover, with compact size, economic fabrication process and great extensibility, this proposed photonic integrated circuit is competitive to be applied in on-chip all-optical information processing systems, such as path priority selector.

On-chip passive three-port circuit of all-optical ordered-route transmission

PubMed Central

Liu, Li; Dong, Jianji; Gao, Dingshan; Zheng, Aoling; Zhang, Xinliang

2015-01-01

On-chip photonic circuits of different specific functions are highly desirable and becoming significant demands in all-optical communication network. Especially, the function to control the transmission directions of the optical signals in integrated circuits is a fundamental research. Previous schemes, such as on-chip optical circulators, are mostly realized by Faraday effect which suffers from material incompatibilities between semiconductors and magneto-optical materials. Achieving highly functional circuits in which light circulates in a particular direction with satisfied performances are still difficult in pure silicon photonics platform. Here, we propose and experimentally demonstrate a three-port passive device supporting optical ordered-route transmission based on silicon thermo-optic effect for the first time. By injecting strong power from only one port, the light could transmit through the three ports in a strict order (1→2, 2→3, 3→1) while be blocked in the opposite order (1→3, 3→2, 2→1). The blocking extinction ratios and operation bandwidths have been investigated in this paper. Moreover, with compact size, economic fabrication process and great extensibility, this proposed photonic integrated circuit is competitive to be applied in on-chip all-optical information processing systems, such as path priority selector. PMID:25970855

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate ( C'' or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability bymore » using DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate (``C`` or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability by usingmore » DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

1997-08-05

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

A perforated CMOS microchip for immobilization and activity monitoring of electrogenic cells

NASA Astrophysics Data System (ADS)

Greve, F.; Lichtenberg, J.; Kirstein, K.-U.; Frey, U.; Perriard, J.-C.; Hierlemann, A.

2007-03-01

CMOS-based microelectrode systems offer decisive advantages over conventional micro-electrode arrays, which include the possibility to perform on-chip signal conditioning or to efficiently use larger numbers of electrodes to obtain statistically relevant data, e.g., in pharmacological drug screening. A larger number of electrodes can only be realized with the help of on-chip multiplexing and readout schemes, which require integrated electronics. Another fundamental issue in performing high-fidelity recordings from electrogenic cells is a good electrical coupling between the cells and the microelectrodes, in particular, since the recorded extracellular signals are in the range of only 10-1000 µV. In this paper we present the first CMOS microelectrode system with integrated micromechanical cell-placement features fabricated in a commercial CMOS process with subsequent post-CMOS bulk micromachining. This new microdevice aims at enabling the precise placement of single cells in the center of the electrodes to ensure an efficient use of the available electrodes, even for low-density cell cultures. Small through-chip holes have been generated at the metal-electrode sites by using a combination of bulk micromachining and reactive-ion etching. These holes act as orifices so that cell immobilization can be achieved by means of pneumatic anchoring. The chip additionally hosts integrated circuitry, i.e., multiplexers to select the respective readout electrodes, an amplifier with selectable gain (2×, 10×, 100×), and a high-pass filter (100 Hz cut-off). In this paper we show that electrical signals from most of the electrodes can be recorded, even in low-density cultures of neonatal rat cardiomyocytes, by using perforated metal electrodes and by applying a small underpressure from the backside of the chip. The measurements evidenced that, in most cases, about 90% of the electrodes were covered with single cells, approximately 4% were covered with more than one cell due to clustering and approximately 6% were not covered with any cell, mostly as a consequence of orifice clogging. After 4 days of culturing, the cells were still in place on the electrodes so that the cell electrical activity could be measured using the on-chip circuitry. Measured signal amplitudes were in the range of 500-700 µV, while the input-referred noise of the readout was below 15 µVrms (100 Hz-4 kHz bandwidth). We report on the development and fabrication of this new cell-biological tool and present first results collected during the characterization and evaluation of the chip. The recordings of electrical potentials of neonatal rat cardiomyocytes after several days in vitro, which, on the one hand, were conventionally cultured (no pneumatic anchoring) and, on the other hand, were anchored and immobilized, will be detailed.

An Attachable Electromagnetic Energy Harvester Driven Wireless Sensing System Demonstrating Milling-Processes and Cutter-Wear/Breakage-Condition Monitoring.

PubMed

Chung, Tien-Kan; Yeh, Po-Chen; Lee, Hao; Lin, Cheng-Mao; Tseng, Chia-Yung; Lo, Wen-Tuan; Wang, Chieh-Min; Wang, Wen-Chin; Tu, Chi-Jen; Tasi, Pei-Yuan; Chang, Jui-Wen

2016-02-23

An attachable electromagnetic-energy-harvester driven wireless vibration-sensing system for monitoring milling-processes and cutter-wear/breakage-conditions is demonstrated. The system includes an electromagnetic energy harvester, three single-axis Micro Electro-Mechanical Systems (MEMS) accelerometers, a wireless chip module, and corresponding circuits. The harvester consisting of magnets with a coil uses electromagnetic induction to harness mechanical energy produced by the rotating spindle in milling processes and consequently convert the harnessed energy to electrical output. The electrical output is rectified by the rectification circuit to power the accelerometers and wireless chip module. The harvester, circuits, accelerometer, and wireless chip are integrated as an energy-harvester driven wireless vibration-sensing system. Therefore, this completes a self-powered wireless vibration sensing system. For system testing, a numerical-controlled machining tool with various milling processes is used. According to the test results, the system is fully self-powered and able to successfully sense vibration in the milling processes. Furthermore, by analyzing the vibration signals (i.e., through analyzing the electrical outputs of the accelerometers), criteria are successfully established for the system for real-time accurate simulations of the milling-processes and cutter-conditions (such as cutter-wear conditions and cutter-breaking occurrence). Due to these results, our approach can be applied to most milling and other machining machines in factories to realize more smart machining technologies.

An Attachable Electromagnetic Energy Harvester Driven Wireless Sensing System Demonstrating Milling-Processes and Cutter-Wear/Breakage-Condition Monitoring

PubMed Central

Chung, Tien-Kan; Yeh, Po-Chen; Lee, Hao; Lin, Cheng-Mao; Tseng, Chia-Yung; Lo, Wen-Tuan; Wang, Chieh-Min; Wang, Wen-Chin; Tu, Chi-Jen; Tasi, Pei-Yuan; Chang, Jui-Wen

2016-01-01

An attachable electromagnetic-energy-harvester driven wireless vibration-sensing system for monitoring milling-processes and cutter-wear/breakage-conditions is demonstrated. The system includes an electromagnetic energy harvester, three single-axis Micro Electro-Mechanical Systems (MEMS) accelerometers, a wireless chip module, and corresponding circuits. The harvester consisting of magnets with a coil uses electromagnetic induction to harness mechanical energy produced by the rotating spindle in milling processes and consequently convert the harnessed energy to electrical output. The electrical output is rectified by the rectification circuit to power the accelerometers and wireless chip module. The harvester, circuits, accelerometer, and wireless chip are integrated as an energy-harvester driven wireless vibration-sensing system. Therefore, this completes a self-powered wireless vibration sensing system. For system testing, a numerical-controlled machining tool with various milling processes is used. According to the test results, the system is fully self-powered and able to successfully sense vibration in the milling processes. Furthermore, by analyzing the vibration signals (i.e., through analyzing the electrical outputs of the accelerometers), criteria are successfully established for the system for real-time accurate simulations of the milling-processes and cutter-conditions (such as cutter-wear conditions and cutter-breaking occurrence). Due to these results, our approach can be applied to most milling and other machining machines in factories to realize more smart machining technologies. PMID:26907297

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

NASA Astrophysics Data System (ADS)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

A Library of Rad Hard Mixed-Voltage/Mixed-Signal Building Blocks for Integration of Avionics Systems for Deep Space

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Blaes, B.; Kolawa, E. A.; Blalock, B. J.; Li, H. W.; Buck, K.; Houge, D.

2001-01-01

To build the sensor intensive system-on-a-chip for the next generation spacecrafts for deep space, Center for Integration of Space Microsystems at JPL (CISM) takes advantage of the lower power rating and inherent radiation resistance of Silicon on Insulator technology (SOI). We are developing a suite of mixed-voltage and mixed-signal building blocks in Honeywell's SOI process that can enable the rapid integration of the next generation avionics systems with lower power rating, higher reliability, longer life, and enhanced radiation tolerance for spacecrafts such as the Europa Orbiter and Europa Lander. The mixed-voltage building blocks are predominantly for design of adaptive power management systems. Their design centers around an LDMOS structure that is being developed by Honeywell, Boeing Corp, and the University of Idaho. The mixed-signal building blocks are designed to meet the low power, extreme radiation requirement of deep space applications. These building blocks are predominantly used to interface analog sensors to the digital CPU of the next generation avionics system on a chip. Additional information is contained in the original extended abstract.

Hardware and circuit design of a vibrational cleaner

NASA Astrophysics Data System (ADS)

Fhong Soon, Chin; Thong, Kok Tung; Sek Tee, Kian; Nayan, Nafarizal; Khairul Ahmad, Mohd; Nurashikin Nordin, Anis

2016-11-01

Microtissue can be grown on soft substrates of hydrogel or liquid crystal gel. These gels are adherent to the microtissues and they may interfere fluorescence imaging as background noise due to their absorbance property. A microfluidic vibrational cleaner with polydimethylsiloxane (PDMS) microfluidic chip platform was proposed and developed to remove the residual gel of liquid crystal adhered to the microtissues. The microtissues were placed in a microfluidic chip attaching to a microfluidic vibrational platform. In the system design, two motorised vibrators vibrating attached to a microfluidic platform and generating vibration signals at 148 Hz and 0.89 Grms to clean the microtissues. The acceleration of the vibration increased gradually from 0 to 0.96 Grms when the duty cycle of PWM pulses increased from 50 - 90%. It dropped slightly to 0.89 Grms at 100% duty cycle. Irrigation water valve was designed to control the fluid flow from water pump during cleaning process. Water pumps were included to flush the channels of the microfluidic device. The signals in controlling the pump, motor and valve were linearly proportional to the duty cycles of the pulse width modulation signals generated from a microcontroller.

SAR processing using SHARC signal processing systems

NASA Astrophysics Data System (ADS)

Huxtable, Barton D.; Jackson, Christopher R.; Skaron, Steve A.

1998-09-01

Synthetic aperture radar (SAR) is uniquely suited to help solve the Search and Rescue problem since it can be utilized either day or night and through both dense fog or thick cloud cover. Other papers in this session, and in this session in 1997, describe the various SAR image processing algorithms that are being developed and evaluated within the Search and Rescue Program. All of these approaches to using SAR data require substantial amounts of digital signal processing: for the SAR image formation, and possibly for the subsequent image processing. In recognition of the demanding processing that will be required for an operational Search and Rescue Data Processing System (SARDPS), NASA/Goddard Space Flight Center and NASA/Stennis Space Center are conducting a technology demonstration utilizing SHARC multi-chip modules from Boeing to perform SAR image formation processing.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Maximizing Computational Capability with Minimal Power

DTIC Science & Technology

2009-03-01

Chip -Scale Energy and Power... and Heat Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting burden for the collection of...OpticalBench Mounting Posts Imager Chip LCDinterfaced withthecomputer P o l a r i z e r P o l a r i z e r XYZ Translator Optical Slide VMM Computational Pixel...Signal routing power / memory: ? Power does not include comm off chip (i.e. accessing memory) Power = ½ C Vdd2 f for CMOS Chip to Chip (10pF load min

Effects of channel tap spacing on delay-lock tracking

NASA Astrophysics Data System (ADS)

Dana, Roger A.; Milner, Brian R.; Bogusch, Robert L.

1995-12-01

High fidelity simulations of communication links operating through frequency selective fading channels require both accurate channel models and faithful reproduction of the received signal. In modern radio receivers, processing beyond the analog-to-digital converter (A/D) is done digitally, so a high fidelity simulation is actually an emulation of this digital signal processing. The 'simulation' occurs in constructing the output of the A/D. One approach to constructing the A/D output is to convolve the channel impulse response function with the combined impulse response of the transmitted modulation and the A/D. For both link simulations and hardware channel simulators, the channel impulse response function is then generated with a finite number of samples per chip, and the convolution is implemented in a tapped delay line. In this paper we discuss the effects of the channel model tap spacing on the performance of delay locked loops (DLLs) in both direct sequence and frequency hopped spread spectrum systems. A frequency selective fading channel is considered, and the channel impulse response function is constructed with an integer number of taps per modulation symbol or chip. The tracking loop time delay is computed theoretically for this tapped delay line channel model and is compared to the results of high fidelity simulations of actual DLLs. A surprising result is obtained. The performance of the DLL depends strongly on the number of taps per chip. As this number increases the DLL delay approaches the theoretical limit.

Highly localized distributed Brillouin scattering response in a photonic integrated circuit

NASA Astrophysics Data System (ADS)

Zarifi, Atiyeh; Stiller, Birgit; Merklein, Moritz; Li, Neuton; Vu, Khu; Choi, Duk-Yong; Ma, Pan; Madden, Stephen J.; Eggleton, Benjamin J.

2018-03-01

The interaction of optical and acoustic waves via stimulated Brillouin scattering (SBS) has recently reached on-chip platforms, which has opened new fields of applications ranging from integrated microwave photonics and on-chip narrow-linewidth lasers, to phonon-based optical delay and signal processing schemes. Since SBS is an effect that scales exponentially with interaction length, on-chip implementation on a short length scale is challenging, requiring carefully designed waveguides with optimized opto-acoustic overlap. In this work, we use the principle of Brillouin optical correlation domain analysis to locally measure the SBS spectrum with high spatial resolution of 800 μm and perform a distributed measurement of the Brillouin spectrum along a spiral waveguide in a photonic integrated circuit. This approach gives access to local opto-acoustic properties of the waveguides, including the Brillouin frequency shift and linewidth, essential information for the further development of high quality photonic-phononic waveguides for SBS applications.

The realization of an SVGA OLED-on-silicon microdisplay driving circuit

NASA Astrophysics Data System (ADS)

Bohua, Zhao; Ran, Huang; Fei, Ma; Guohua, Xie; Zhensong, Zhang; Huan, Du; Jiajun, Luo; Yi, Zhao

2012-03-01

An 800 × 600 pixel organic light-emitting diode-on-silicon (OLEDoS) driving circuit is proposed. The pixel cell circuit utilizes a subthreshold-voltage-scaling structure which can modulate the pixel current between 170 pA and 11.4 nA. In order to keep the voltage of the column bus at a relatively high level, the sample-and-hold circuits adopt a ping-pong operation. The driving circuit is fabricated in a commercially available 0.35 μm two-poly four-metal 3.3 V mixed-signal CMOS process. The pixel cell area is 15 × 15 μm2 and the total chip occupies 15.5 × 12.3 mm2. Experimental results show that the chip can work properly at a frame frequency of 60 Hz and has a 64 grayscale (monochrome) display. The total power consumption of the chip is about 85 mW with a 3.3V supply voltage.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Comparison of contamination of femoral heads and pre-processed bone chips during hip revision arthroplasty.

PubMed

Mathijssen, N M C; Sturm, P D; Pilot, P; Bloem, R M; Buma, P; Petit, P L; Schreurs, B W

2013-12-01

With bone impaction grafting, cancellous bone chips made from allograft femoral heads are impacted in a bone defect, which introduces an additional source of infection. The potential benefit of the use of pre-processed bone chips was investigated by comparing the bacterial contamination of bone chips prepared intraoperatively with the bacterial contamination of pre-processed bone chips at different stages in the surgical procedure. To investigate baseline contamination of the bone grafts, specimens were collected during 88 procedures before actual use or preparation of the bone chips: in 44 procedures intraoperatively prepared chips were used (Group A) and in the other 44 procedures pre-processed bone chips were used (Group B). In 64 of these procedures (32 using locally prepared bone chips and 32 using pre-processed bone chips) specimens were also collected later in the procedure to investigate contamination after use and preparation of the bone chips. In total, 8 procedures had one or more positive specimen(s) (12.5 %). Contamination rates were not significantly different between bone chips prepared at the operating theatre and pre-processed bone chips. In conclusion, there was no difference in bacterial contamination between bone chips prepared from whole femoral heads in the operating room and pre-processed bone chips, and therefore, both types of bone allografts are comparable with respect to risk of infection.

Lossless microwave photonic delay line using a ring resonator with an integrated semiconductor optical amplifier

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Zhuang, Leimeng; Boller, Klaus-Jochen; Lowery, Arthur James

2017-06-01

Optical delay lines implemented in photonic integrated circuits (PICs) are essential for creating robust and low-cost optical signal processors on miniaturized chips. In particular, tunable delay lines enable a key feature of programmability for the on-chip processing functions. However, the previously investigated tunable delay lines are plagued by a severe drawback of delay-dependent loss due to the propagation loss in the constituent waveguides. In principle, a serial-connected amplifier can be used to compensate such losses or perform additional amplitude manipulation. However, this solution is generally unpractical as it introduces additional burden on chip area and power consumption, particularly for large-scale integrated PICs. Here, we report an integrated tunable delay line that overcomes the delay-dependent loss, and simultaneously allows for independent manipulation of group delay and amplitude responses. It uses a ring resonator with a tunable coupler and a semiconductor optical amplifier in the feedback path. A proof-of-concept device with a free spectral range of 11.5 GHz and a delay bandwidth in the order of 200 MHz is discussed in the context of microwave photonics and is experimentally demonstrated to be able to provide a lossless delay up to 1.1 to a 5 ns Gaussian pulse. The proposed device can be designed for different frequency scales with potential for applications across many other areas such as telecommunications, LIDAR, and spectroscopy, serving as a novel building block for creating chip-scale programmable optical signal processors.

A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

PubMed

Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

2009-01-01

For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

The Department of Defense Very High Speed Integrated Circuit (VHSIC) Technology Availability Program Plan for the Committees on Armed Services United States Congress.

DTIC Science & Technology

1986-06-30

features of computer aided design systems and statistical quality control procedures that are generic to chip sets and processes. RADIATION HARDNESS -The...System PSP Programmable Signal Processor SSI Small Scale Integration ." TOW Tube Launched, Optically Tracked, Wire Guided TTL Transistor Transitor Logic

Laser pulse coded signal frequency measuring device based on DSP and CPLD

NASA Astrophysics Data System (ADS)

Zhang, Hai-bo; Cao, Li-hua; Geng, Ai-hui; Li, Yan; Guo, Ru-hai; Wang, Ting-feng

2011-06-01

Laser pulse code is an anti-jamming measures used in semi-active laser guided weapons. On account of the laser-guided signals adopting pulse coding mode and the weak signal processing, it need complex calculations in the frequency measurement process according to the laser pulse code signal time correlation to meet the request in optoelectronic countermeasures in semi-active laser guided weapons. To ensure accurately completing frequency measurement in a short time, it needed to carry out self-related process with the pulse arrival time series composed of pulse arrival time, calculate the signal repetition period, and then identify the letter type to achieve signal decoding from determining the time value, number and rank number in a signal cycle by Using CPLD and DSP for signal processing chip, designing a laser-guided signal frequency measurement in the pulse frequency measurement device, improving the signal processing capability through the appropriate software algorithms. In this article, we introduced the principle of frequency measurement of the device, described the hardware components of the device, the system works and software, analyzed the impact of some system factors on the accuracy of the measurement. The experimental results indicated that this system improve the accuracy of the measurement under the premise of volume, real-time, anti-interference, low power of the laser pulse frequency measuring device. The practicality of the design, reliability has been demonstrated from the experimental point of view.

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

PubMed

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Capillary-driven surface-enhanced Raman scattering (SERS)-based microfluidic chip for abrin detection

NASA Astrophysics Data System (ADS)

Yang, Hao; Deng, Min; Ga, Shan; Chen, Shouhui; Kang, Lin; Wang, Junhong; Xin, Wenwen; Zhang, Tao; You, Zherong; An, Yuan; Wang, Jinglin; Cui, Daxiang

2014-03-01

Herein, we firstly demonstrate the design and the proof-of-concept use of a capillary-driven surface-enhanced Raman scattering (SERS)-based microfluidic chip for abrin detection. The micropillar array substrate was etched and coated with a gold film by microelectromechanical systems (MEMS) process to integrate into a lateral flow test strip. The detection of abrin solutions of various concentrations was performed by the as-prepared microfluidic chip. It was shown that the correlation between the abrin concentration and SERS signal was found to be linear within the range of 0.1 ng/mL to 1 μg/mL with a limit of detection of 0.1 ng/mL. Our microfluidic chip design enhanced the operability of SERS-based immunodiagnostic techniques, significantly reducing the complication and cost of preparation as compared to previous SERS-based works. Meanwhile, this design proved the superiority to conventional lateral flow test strips in respect of both sensitivity and quantitation and showed great potential in the diagnosis and treatment for abrin poisoning as well as on-site screening of abrin-spiked materials.

A piezo-ring-on-chip microfluidic device for simple and low-cost mass spectrometry interfacing.

PubMed

Tsao, Chia-Wen; Lei, I-Chao; Chen, Pi-Yu; Yang, Yu-Liang

2018-02-12

Mass spectrometry (MS) interfacing technology provides the means for incorporating microfluidic processing with post MS analysis. In this study, we propose a simple piezo-ring-on-chip microfluidic device for the controlled spraying of MALDI-MS targets. This device uses a low-cost, commercially-available ring-shaped piezoelectric acoustic atomizer (piezo-ring) directly integrated into a polydimethylsiloxane microfluidic device to spray the sample onto the MS target substrate. The piezo-ring-on-chip microfluidic device's design, fabrication, and actuation, and its pulsatile pumping effects were evaluated. The spraying performance was examined by depositing organic matrix samples onto the MS target substrate by using both an automatic linear motion motor, and manual deposition. Matrix-assisted laser desorption/ionization mass spectrometry (MALDI-MS) was performed to analyze the peptide samples on the MALDI target substrates. Using our technique, model peptides with 10 -6 M concentration can be successfully detected. The results also indicate that the piezo-ring-on-chip approach forms finer matrix crystals and presents better MS signal uniformity with little sample consumption compared to the conventional pipetting method.

Identifying the substrate proteins of U-box E3s E4B and CHIP by orthogonal ubiquitin transfer.

PubMed

Bhuripanyo, Karan; Wang, Yiyang; Liu, Xianpeng; Zhou, Li; Liu, Ruochuan; Duong, Duc; Zhao, Bo; Bi, Yingtao; Zhou, Han; Chen, Geng; Seyfried, Nicholas T; Chazin, Walter J; Kiyokawa, Hiroaki; Yin, Jun

2018-01-01

E3 ubiquitin (UB) ligases E4B and carboxyl terminus of Hsc70-interacting protein (CHIP) use a common U-box motif to transfer UB from E1 and E2 enzymes to their substrate proteins and regulate diverse cellular processes. To profile their ubiquitination targets in the cell, we used phage display to engineer E2-E4B and E2-CHIP pairs that were free of cross-reactivity with the native UB transfer cascades. We then used the engineered E2-E3 pairs to construct "orthogonal UB transfer (OUT)" cascades so that a mutant UB (xUB) could be exclusively used by the engineered E4B or CHIP to label their substrate proteins. Purification of xUB-conjugated proteins followed by proteomics analysis enabled the identification of hundreds of potential substrates of E4B and CHIP in human embryonic kidney 293 cells. Kinase MAPK3 (mitogen-activated protein kinase 3), methyltransferase PRMT1 (protein arginine N -methyltransferase 1), and phosphatase PPP3CA (protein phosphatase 3 catalytic subunit alpha) were identified as the shared substrates of the two E3s. Phosphatase PGAM5 (phosphoglycerate mutase 5) and deubiquitinase OTUB1 (ovarian tumor domain containing ubiquitin aldehyde binding protein 1) were confirmed as E4B substrates, and β-catenin and CDK4 (cyclin-dependent kinase 4) were confirmed as CHIP substrates. On the basis of the CHIP-CDK4 circuit identified by OUT, we revealed that CHIP signals CDK4 degradation in response to endoplasmic reticulum stress.

Identifying the substrate proteins of U-box E3s E4B and CHIP by orthogonal ubiquitin transfer

PubMed Central

Bhuripanyo, Karan; Wang, Yiyang; Liu, Xianpeng; Zhou, Li; Liu, Ruochuan; Duong, Duc; Zhao, Bo; Bi, Yingtao; Zhou, Han; Chen, Geng; Seyfried, Nicholas T.; Chazin, Walter J.; Kiyokawa, Hiroaki; Yin, Jun

2018-01-01

E3 ubiquitin (UB) ligases E4B and carboxyl terminus of Hsc70-interacting protein (CHIP) use a common U-box motif to transfer UB from E1 and E2 enzymes to their substrate proteins and regulate diverse cellular processes. To profile their ubiquitination targets in the cell, we used phage display to engineer E2-E4B and E2-CHIP pairs that were free of cross-reactivity with the native UB transfer cascades. We then used the engineered E2-E3 pairs to construct “orthogonal UB transfer (OUT)” cascades so that a mutant UB (xUB) could be exclusively used by the engineered E4B or CHIP to label their substrate proteins. Purification of xUB-conjugated proteins followed by proteomics analysis enabled the identification of hundreds of potential substrates of E4B and CHIP in human embryonic kidney 293 cells. Kinase MAPK3 (mitogen-activated protein kinase 3), methyltransferase PRMT1 (protein arginine N-methyltransferase 1), and phosphatase PPP3CA (protein phosphatase 3 catalytic subunit alpha) were identified as the shared substrates of the two E3s. Phosphatase PGAM5 (phosphoglycerate mutase 5) and deubiquitinase OTUB1 (ovarian tumor domain containing ubiquitin aldehyde binding protein 1) were confirmed as E4B substrates, and β-catenin and CDK4 (cyclin-dependent kinase 4) were confirmed as CHIP substrates. On the basis of the CHIP-CDK4 circuit identified by OUT, we revealed that CHIP signals CDK4 degradation in response to endoplasmic reticulum stress. PMID:29326975

275 C Downhole Microcomputer System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chris Hutchens; Hooi Miin Soo

2008-08-31

An HC11 controller IC and along with serial SRAM and ROM support ICs chip set were developed to support a data acquisition and control for extreme temperature/harsh environment conditions greater than 275 C. The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and signal processing applications and was the logical choice for a downhole controller. This extreme temperature version of the 68HC11 enables new high temperature designs and additionally allows 68HC11-based well logging tools and MWD tools to be upgraded for high temperature operation in deep gas reservoirs, The microcomputer chip consists of the microprocessormore » ALU, a small boot ROM, 4 kbyte data RAM, counter/timer unit, serial peripheral interface (SPI), asynchronous serial interface (SCI), and the A, B, C, and D parallel ports. The chip is code compatible with the single chip mode commercial 68HC11 except for the absence of the analog to digital converter system. To avoid mask programmed internal ROM, a boot program is used to load the microcomputer program from an external mask SPI ROM. A SPI RAM IC completes the chip set and allows data RAM to be added in 4 kbyte increments. The HC11 controller IC chip set is implemented in the Peregrine Semiconductor 0.5 micron Silicon-on-Sapphire (SOS) process using a custom high temperature cell library developed at Oklahoma State University. Yield data is presented for all, the HC11, SPI-RAM and ROM. The lessons learned in this project were extended to the successful development of two high temperature versions of the LEON3 and a companion 8 Kbyte SRAM, a 200 C version for the Navy and a 275 C version for the gas industry.« less

System on a chip with MPEG-4 capability

NASA Astrophysics Data System (ADS)

Yassa, Fathy; Schonfeld, Dan

2002-12-01

Current products supporting video communication applications rely on existing computer architectures. RISC processors have been used successfully in numerous applications over several decades. DSP processors have become ubiquitous in signal processing and communication applications. Real-time applications such as speech processing in cellular telephony rely extensively on the computational power of these processors. Video processors designed to implement the computationally intensive codec operations have also been used to address the high demands of video communication applications (e.g., cable set-top boxes and DVDs). This paper presents an overview of a system-on-chip (SOC) architecture used for real-time video in wireless communication applications. The SOC specifications answer to the system requirements imposed by the application environment. A CAM-based video processor is used to accelerate data intensive video compression tasks such as motion estimations and filtering. Other components are dedicated to system level data processing and audio processing. A rich set of I/Os allows the SOC to communicate with other system components such as baseband and memory subsystems.

A label-free, fluorescence based assay for microarray

NASA Astrophysics Data System (ADS)

Niu, Sanjun

DNA chip technology has drawn tremendous attention since it emerged in the mid 90's as a method that expedites gene sequencing by over 100-fold. DNA chip, also called DNA microarray, is a combinatorial technology in which different single-stranded DNA (ssDNA) molecules of known sequences are immobilized at specific spots. The immobilized ssDNA strands are called probes. In application, the chip is exposed to a solution containing ssDNA of unknown sequence, called targets, which are labeled with fluorescent dyes. Due to specific molecular recognition among the base pairs in the DNA, the binding or hybridization occurs only when the probe and target sequences are complementary. The nucleotide sequence of the target is determined by imaging the fluorescence from the spots. The uncertainty of background in signal detection and statistical error in data analysis, primarily due to the error in the DNA amplification process and statistical distribution of the tags in the target DNA, have become the fundamental barriers in bringing the technology into application for clinical diagnostics. Furthermore, the dye and tagging process are expensive, making the cost of DNA chips inhibitive for clinical testing. These limitations and challenges make it difficult to implement DNA chip methods as a diagnostic tool in a pathology laboratory. The objective of this dissertation research is to provide an alternative approach that will address the above challenges. In this research, a label-free assay is designed and studied. Polystyrene (PS), a commonly used polymeric material, serves as the fluorescence agent. Probe ssDNA is covalently immobilized on polystyrene thin film that is supported by a reflecting substrate. When this chip is exposed to excitation light, fluorescence light intensity from PS is detected as the signal. Since the optical constants and conformations of ssDNA and dsDNA (double stranded DNA) are different, the measured fluorescence from PS changes for the same intensity of excitation light. The fluorescence contrast is used to quantify the amount of probe-target hybridization. A mathematical model that considers multiple reflections and scattering is developed to explain the mechanism of the fluorescence contrast which depends on the thickness of the PS film. Scattering is the dominant factor that contributes to the contrast. The potential of this assay to detect single nucleotide polymorphism is also tested.

A Fiber Bragg Grating Sensor Interrogation System Based on a Linearly Wavelength-Swept Thermo-Optic Laser Chip

PubMed Central

Lee, Hyung-Seok; Lee, Hwi Don; Kim, Hyo Jin; Cho, Jae Du; Jeong, Myung Yung; Kim, Chang-Seok

2014-01-01

A linearized wavelength-swept thermo-optic laser chip was applied to demonstrate a fiber Bragg grating (FBG) sensor interrogation system. A broad tuning range of 11.8 nm was periodically obtained from the laser chip for a sweep rate of 16 Hz. To measure the linear time response of the reflection signal from the FBG sensor, a programmed driving signal was directly applied to the wavelength-swept laser chip. The linear wavelength response of the applied strain was clearly extracted with an R-squared value of 0.99994. To test the feasibility of the system for dynamic measurements, the dynamic strain was successfully interrogated with a repetition rate of 0.2 Hz by using this FBG sensor interrogation system. PMID:25177803

Preface to the special issue on "Integrated Microwave Photonic Signal Processing"

NASA Astrophysics Data System (ADS)

Azaña, José; Yao, Jianping

2016-08-01

As Guest Editors, we are pleased to introduce this special issue on ;Integrated Microwave Photonic Signal Processing; published by the Elsevier journal Optics Communications. Microwave photonics is a field of growing importance from both scientific and practical application perspectives. The field of microwave photonics is devoted to the study, development and application of optics-based techniques and technologies aimed to the generation, processing, control, characterization and/or distribution of microwave signals, including signals well into the millimeter-wave frequency range. The use of photonic technologies for these microwave applications translates into a number of key advantages, such as the possibility of dealing with high-frequency, wide bandwidth signals with minimal losses and reduced electromagnetic interferences, and the potential for enhanced reconfigurability. The central purpose of this special issue is to provide an overview of the state of the art of generation, processing and characterization technologies for high-frequency microwave signals. It is now widely accepted that the practical success of microwave photonics at a large scale will essentially depend on the realization of high-performance microwave-photonic signal-processing engines in compact and integrated formats, preferably on a chip. Thus, the focus of the issue is on techniques implemented using integrated photonic technologies, with the goal of providing an update of the most recent advances toward realization of this vision.

Process for 3D chip stacking

DOEpatents

Malba, V.

1998-11-10

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

Process for 3D chip stacking

DOEpatents

Malba, Vincent

1998-01-01

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

Development of low fat potato chips through microwave processing.

PubMed

Joshi, A; Rudra, S G; Sagar, V R; Raigond, P; Dutt, S; Singh, B; Singh, B P

2016-08-01

Since snacks high in fats are known to be a significant source of fat and energy intake, these have been put in high dietary restraint category. Therefore, an attempt was made to process potato chips through microwave processing without incorporation of any oil in potato chips. Microwave processing of potato chips was done using microwave power varying from 180 to 600 W using constant sample size. Among eleven different drying models, Parabolic model was found to be the best fit through non-linear regression analysis to illustrate drying kinetics of potato chips. The structural, textural and colour attributes of microwaved potato chips were similar to commercial fried potato chips. It was found that at 600 W after 2.5-3.0 min of processing, potato chips gained the fracturability and crispiness index as that of commercial fried chips. Microwave processing was found suitable for processing of potato chips with low fat content (~3.09 vs 35.5 % in commercial preparation) and with acceptable sensory scores (≥7.6 on 9.0 point on hedonic scale vs 8.0 of control preparation).

System-on-fluidics immunoassay device integrating wireless radio-frequency-identification sensor chips.

PubMed

Yazawa, Yoshiaki; Oonishi, Tadashi; Watanabe, Kazuki; Shiratori, Akiko; Funaoka, Sohei; Fukushima, Masao

2014-09-01

A simple and sensitive point-of-care-test (POCT) device for chemiluminescence (CL) immunoassay was devised and tested. The device consists of a plastic flow-channel reactor and two wireless-communication sensor chips, namely, a photo-sensor chip and a temperature-sensor chip. In the flow-channel reactor, a target antigen is captured by an antibody immobilized on the inner wall of the flow-channel and detected with enzyme labeled antibody by using CL substrate. The CL signal corresponding to the amount of antigen is measured by a newly developed radio-frequency-identification (RFID) sensor, which enables batteryless operation and wireless data communication with an external reader. As for the POCT device, its usage environment, especially temperature, varies for each measurement. Hence, temperature compensation is a key issue in regard to eliminating dark-signal fluctuation, which is a major factor in deterioration of the precision of the POCT device. A two-stage temperature-compensation scheme was adopted. As for the first stage, the signals of two photodiodes, one with an open window and one with a sealed window, integrated on the photo-sensor chip are differentiated to delete the dark signal. As for the second stage, the differentiated signal fluctuation caused by a temperature variation is compensated by using the other sensor chip (equipped with a temperature sensor). The dark-level fluctuation caused by temperature was reduced from 0.24 to 0.02 pA/°C. The POCT device was evaluated as a CL immunoassay of thyroid-stimulating hormone (TSH). The flow rate of the CL reagent in the flow channel was optimized. As a result, the detection limit of the POCT device was 0.08 ng/ml (i.e., 0.4 μIU/ml). Copyright © 2014 The Society for Biotechnology, Japan. Published by Elsevier B.V. All rights reserved.

Functional differentiation of human pluripotent stem cells on a chip.

PubMed

Giobbe, Giovanni G; Michielin, Federica; Luni, Camilla; Giulitti, Stefano; Martewicz, Sebastian; Dupont, Sirio; Floreani, Annarosa; Elvassore, Nicola

2015-07-01

Microengineering human "organs-on-chips" remains an open challenge. Here, we describe a robust microfluidics-based approach for the differentiation of human pluripotent stem cells directly on a chip. Extrinsic signal modulation, achieved through optimal frequency of medium delivery, can be used as a parameter for improved germ layer specification and cell differentiation. Human cardiomyocytes and hepatocytes derived on chips showed functional phenotypes and responses to temporally defined drug treatments.

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

Resonant-type MEMS transducers excited by two acoustic emission simulation techniques

NASA Astrophysics Data System (ADS)

Ozevin, Didem; Greve, David W.; Oppenheim, Irving J.; Pessiki, Stephen

2004-07-01

Acoustic emission testing is a passive nondestructive testing technique used to identify the onset and characteristics of damage through the detection and analysis of transient stress waves. Successful detection and implementation of acoustic emission requires good coupling, high transducer sensitivity and ability to discriminate noise from real signals. We report here detection of simulated acoustic emission signals using a MEMS chip fabricated in the multi-user polysilicon surface micromachining (MUMPs) process. The chip includes 18 different transducers with 10 different resonant frequencies in the range of 100 kHz to 1 MHz. It was excited by two different source simulation techniques; pencil lead break and impact loading. The former simulation was accomplished by breaking 0.5 mm lead on the ceramic package. Four transducer outputs were collected simultaneously using a multi-channel oscilloscope. The impact loading was repeated for five different diameter ball bearings. Traditional acoustic emission waveform analysis methods were applied to both data sets to illustrate the identification of different source mechanisms. In addition, a sliding window Fourier transform was performed to differentiate frequencies in time-frequency-amplitude domain. The arrival and energy contents of each resonant frequency were investigated in time-magnitude plots. The advantages of the simultaneous excitation of resonant transducers on one chip are discussed and compared with broadband acoustic emission transducers.

NbN A/D Conversion of IR Focal Plane Sensor Signal at 10 K

NASA Technical Reports Server (NTRS)

Eaton, L.; Durand, D.; Sandell, R.; Spargo, J.; Krabach, T.

1994-01-01

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.

A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

NASA Astrophysics Data System (ADS)

Cho, M.; Lim, K.-t.; Kim, H.; Yeom, J.-y.; Kim, J.; Lee, C.; Choi, H.; Cho, G.

2017-01-01

In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

A multi-channel instrumentation system for biosignal recording.

PubMed

Yu, Hong; Li, Pengfei; Xiao, Zhiming; Peng, Chung-Ching; Bashirullah, Rizwan

2008-01-01

This paper reports a highly integrated battery operated multi-channel instrumentation system intended for physiological signal recording. The mixed signal IC has been fabricated in standard 0.5microm 5V 3M-2P CMOS process and features 32 instrumentation amplifiers, four 8b SAR ADCs, a wireless power interface with Li-ion battery charger, low power bidirectional telemetry and FSM controller with power gating control for improved energy efficiency. The chip measures 3.2mm by 4.8mm and dissipates approximately 2.1mW when fully operational.

[A modified speech enhancement algorithm for electronic cochlear implant and its digital signal processing realization].

PubMed

Wang, Yulin; Tian, Xuelong

2014-08-01

In order to improve the speech quality and auditory perceptiveness of electronic cochlear implant under strong noise background, a speech enhancement system used for electronic cochlear implant front-end was constructed. Taking digital signal processing (DSP) as the core, the system combines its multi-channel buffered serial port (McBSP) data transmission channel with extended audio interface chip TLV320AIC10, so speech signal acquisition and output with high speed are realized. Meanwhile, due to the traditional speech enhancement method which has the problems as bad adaptability, slow convergence speed and big steady-state error, versiera function and de-correlation principle were used to improve the existing adaptive filtering algorithm, which effectively enhanced the quality of voice communications. Test results verified the stability of the system and the de-noising performance of the algorithm, and it also proved that they could provide clearer speech signals for the deaf or tinnitus patients.

[Design of blood-pressure parameter auto-acquisition circuit].

PubMed

Chen, Y P; Zhang, D L; Bai, H W; Zhang, D A

2000-02-01

This paper presents the realization and design of a kind of blood-pressure parameter auto-acquisition circuit. The auto-acquisition of blood-pressure parameter controlled by 89C2051 single chip microcomputer is accomplished by collecting and processing the driving signal of LCD. The circuit that is successfully applied in the home unit of telemedicine system has the simple and reliable properties.

Design and Training of Limited-Interconnect Architectures

DTIC Science & Technology

1991-07-16

and signal processing. Neuromorphic (brain like) models, allow an alternative for achieving real-time operation tor such tasks, while having a...compact and robust architecture. Neuromorphic models consist of interconnections of simple computational nodes. In this approach, each node computes a...operational performance. I1. Research Objectives The research objectives were: 1. Development of on- chip local training rules specifically designed for

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

PubMed Central

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-01

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

PubMed

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-27

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

A highly attenuating and frequency tailorable annular hole phononic crystal for surface acoustic waves.

PubMed

Ash, B J; Worsfold, S R; Vukusic, P; Nash, G R

2017-08-02

Surface acoustic wave (SAW) devices are widely used for signal processing, sensing and increasingly for lab-on-a-chip applications. Phononic crystals can control the propagation of SAW, analogous to photonic crystals, enabling components such as waveguides and cavities. Here we present an approach for the realisation of robust, tailorable SAW phononic crystals, based on annular holes patterned in a SAW substrate. Using simulations and experiments, we show that this geometry supports local resonances which create highly attenuating phononic bandgaps at frequencies with negligible coupling of SAWs into other modes, even for relatively shallow features. The enormous bandgap attenuation is up to an order-of-magnitude larger than that achieved with a pillar phononic crystal of the same size, enabling effective phononic crystals to be made up of smaller numbers of elements. This work transforms the ability to exploit phononic crystals for developing novel SAW device concepts, mirroring contemporary progress in photonic crystals.The control and manipulation of propagating sound waves on a surface has applications in on-chip signal processing and sensing. Here, Ash et al. deviate from standard designs and fabricate frequency tailorable phononic crystals with an order-of-magnitude increase in attenuation.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Thermal ink-jet device using single-chip silicon microchannels

NASA Astrophysics Data System (ADS)

Wuu, DongSing; Cheng, Chen-Yue; Horng, RayHua; Chan, G. C.; Chiu, Sao-Ling; Wu, Yi-Yung

1998-06-01

We present a new method to fabricate silicon microfluidic channels by through-hole etching with subsequent planarization. The method is based on etching out the deep grooves through a perforated silicon carbide membrane, followed by sealing the membrane with plasma-enhanced chemical vapor deposition (PECVD). Low-pressure-chemical-vapor- deposited (LPCVD) polysilicon was used as a sacrificial layer to define the channel structure and only one etching step is required. This permits the realization of planarization after a very deep etching step in silicon and offers the possibility for film deposition, resist spinning and film patterning across deep grooves. The process technology was demonstrated on the fabrication of a monolithic silicon microchannel structure for thermal inkjet printing. The Ta-Al heater arrays are integrated on the top of each microchannel, which connect to a common on-chip front-end ink reservoir. The fabrication of this device requires six masks and no active nozzle-to-chip alignment. Moreover, the present micromachining process is compatible with the addition of on-chip circuitry for multiplexing the heater control signals. Heat transfer efficiency to the ink is enhanced by the high thermal conductivity of the silicon carbide in the channel ceiling, while the bulk silicon maintains high interchannel isolation. The fabricated inkjet devices show the droplet sizes of 20 - 50 micrometer in diameter with various channel dimensions and stable ejection of ink droplets more than 1 million.

Pseudo Asynchronous Level Crossing adc for ecg Signal Acquisition.

PubMed

Marisa, T; Niederhauser, T; Haeberlin, A; Wildhaber, R A; Vogel, R; Goette, J; Jacomet, M

2017-02-07

A new pseudo asynchronous level crossing analogue-to-digital converter (adc) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing adc designs, the proposed design has no digital-to-analogue converter (dac) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed adc was implemented in [Formula: see text] complementary metal-oxide-semiconductor (cmos) technology, the hardware occupies a chip area of 0.0372 mm 2 and operates from a supply voltage of [Formula: see text] to [Formula: see text]. The adc's power consumption is as low as 0.6 μW with signal bandwidth from [Formula: see text] to [Formula: see text] and achieves an equivalent number of bits (enob) of up to 8 bits.

On-chip integratable all-optical quantizer using strong cross-phase modulation in a silicon-organic hybrid slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Sang, Xinzhu; Wang, Kuiru; Wu, Qiang; Yan, Binbin; Li, Feng; Zhou, Xian; Zhong, Kangping; Zhou, Guiyao; Yu, Chongxiu; Farrell, Gerald; Lu, Chao; Yaw Tam, Hwa; Wai, P. K. A.

2016-01-01

High performance all-optical quantizer based on silicon waveguide is believed to have significant applications in photonic integratable optical communication links, optical interconnection networks, and real-time signal processing systems. In this paper, we propose an integratable all-optical quantizer for on-chip and low power consumption all-optical analog-to-digital converters. The quantization is realized by the strong cross-phase modulation and interference in a silicon-organic hybrid (SOH) slot waveguide based Mach-Zehnder interferometer. By carefully designing the dimension of the SOH waveguide, large nonlinear coefficients up to 16,000 and 18,069 W−1/m for the pump and probe signals can be obtained respectively, along with a low pulse walk-off parameter of 66.7 fs/mm, and all-normal dispersion in the wavelength regime considered. Simulation results show that the phase shift of the probe signal can reach 8π at a low pump pulse peak power of 206 mW and propagation length of 5 mm such that a 4-bit all-optical quantizer can be realized. The corresponding signal-to-noise ratio is 23.42 dB and effective number of bit is 3.89-bit. PMID:26777054

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Osteoclast TGF-β Receptor Signaling Induces Wnt1 Secretion and Couples Bone Resorption to Bone Formation

PubMed Central

Weivoda, Megan M; Ruan, Ming; Pederson, Larry; Hachfeld, Christine; Davey, Rachel A; Zajac, Jeffrey D; Westendorf, Jennifer J; Khosla, Sundeep; Oursler, Merry Jo

2016-01-01

Osteoblast-mediated bone formation is coupled to osteoclast-mediated bone resorption. These processes become uncoupled with age, leading to increased risk for debilitating fractures. Therefore, understanding how osteoblasts are recruited to sites of resorption is vital to treating age-related bone loss. Osteoclasts release and activate TGF-β from the bone matrix. Here we show that osteoclastspecific inhibition of TGF-β receptor signaling in mice results in osteopenia due to reduced osteoblast numbers with no significant impact on osteoclast numbers or activity. TGF-β induced osteoclast expression of Wnt1, a protein crucial to normal bone formation, and this response was blocked by impaired TGF-β receptor signaling. Osteoclasts in aged murine bones had lower TGF-β signaling and Wnt1 expression in vivo. Ex vivo stimulation of osteoclasts derived from young or old mouse bone marrow macrophages showed no difference in TGF-β–induced Wnt1 expression. However, young osteoclasts expressed reduced Wnt1 when cultured on aged mouse bone chips compared to young mouse bone chips, consistent with decreased skeletal TGF-β availability with age. Therefore, osteoclast responses to TGF-β are essential for coupling bone resorption to bone formation, and modulating this pathway may provide opportunities to treat age-related bone loss. PMID:26108893

Development of an LSI for Tactile Sensor Systems on the Whole-Body of Robots

NASA Astrophysics Data System (ADS)

Muroyama, Masanori; Makihata, Mitsutoshi; Nakano, Yoshihiro; Matsuzaki, Sakae; Yamada, Hitoshi; Yamaguchi, Ui; Nakayama, Takahiro; Nonomura, Yutaka; Fujiyoshi, Motohiro; Tanaka, Shuji; Esashi, Masayoshi

We have developed a network type tactile sensor system, which realizes high-density tactile sensors on the whole-body of nursing and communication robots. The system consists of three kinds of nodes: host, relay and sensor nodes. Roles of the sensor node are to sense forces and, to encode the sensing data and to transmit the encoded data on serial channels by interruption handling. Relay nodes and host deal with a number of the encoded sensing data from the sensor nodes. A sensor node consists of a capacitive MEMS force sensor and a signal processing/transmission LSI. In this paper, details of an LSI for the sensor node are described. We designed experimental sensor node LSI chips by a commercial 0.18µm standard CMOS process. The 0.18µm LSIs were supplied in wafer level for MEMS post-process. The LSI chip area is 2.4mm × 2.4mm, which includes logic, CF converter and memory circuits. The maximum clock frequency of the chip with a large capacitive load is 10MHz. Measured power consumption at 10MHz clock is 2.23mW. Experimental results indicate that size, response time, sensor sensitivity and power consumption are all enough for practical tactile sensor systems.

Plastic straw: future of high-speed signaling

NASA Astrophysics Data System (ADS)

Song, Ha Il; Jin, Huxian; Bae, Hyeon-Min

2015-11-01

The ever-increasing demand for bandwidth triggered by mobile and video Internet traffic requires advanced interconnect solutions satisfying functional and economic constraints. A new interconnect called E-TUBE is proposed as a cost-and-power-effective all-electrical-domain wideband waveguide solution for high-speed high-volume short-reach communication links. The E-TUBE achieves an unprecedented level of performance in terms of bandwidth-per-carrier frequency, power, and density without requiring a precision manufacturing process unlike conventional optical/waveguide solutions. The E-TUBE exhibits a frequency-independent loss-profile of 4 dB/m and has nearly 20-GHz bandwidth over the V band. A single-sideband signal transmission enabled by the inherent frequency response of the E-TUBE renders two-times data throughput without any physical overhead compared to conventional radio frequency communication technologies. This new interconnect scheme would be attractive to parties interested in high throughput links, including but not limited to, 100/400 Gbps chip-to-chip communications.

Nanomechanical silicon resonators with intrinsic tunable gain and sub-nW power consumption.

PubMed

Bartsch, Sebastian T; Lovera, Andrea; Grogg, Daniel; Ionescu, Adrian M

2012-01-24

Nanoelectromechanical systems (NEMS) as integrated components for ultrasensitive sensing, time keeping, or radio frequency applications have driven the search for scalable nanomechanical transduction on-chip. Here, we present a hybrid silicon-on-insulator platform for building NEM oscillators in which fin field effect transistors (FinFETs) are integrated into nanomechanical silicon resonators. We demonstrate transistor amplification and signal mixing, coupled with mechanical motion at very high frequencies (25-80 MHz). By operating the transistor in the subthreshold region, the power consumption of resonators can be reduced to record-low nW levels, opening the way for the parallel operation of hundreds of thousands of NEM oscillators. The electromechanical charge modulation due to the field effect in a resonant transistor body constitutes a scalable nanomechanical motion detection all-on-chip and at room temperature. The new class of tunable NEMS represents a major step toward their integration in resonator arrays for applications in sensing and signal processing. © 2011 American Chemical Society

Wireless biopotential acquisition system for portable healthcare monitoring.

PubMed

Wang, W-S; Huang, H-Y; Wu, Z-C; Chen, S-C; Wang, W-F; Wu, C-F; Luo, C-H

2011-07-01

A complete biopotential acquisition system with an analogue front-end (AFE) chip is proposed for portable healthcare monitoring. A graphical user interface (GUI) is also implemented to display the extracted biopotential signals in real-time on a computer for patients or in a hospital via the internet for doctors. The AFE circuit defines the quality of the acquired biosignals. Thus, an AFE chip with low power consumption and a high common-mode rejection ratio (CMRR) was implemented in the TSMC 0.18-μm CMOS process. The measurement results show that the proposed AFE, with a core area of 0.1 mm(2), has a CMRR of 90 dB, and power consumption of 21.6 μW. Biopotential signals of electroencephalogram (EEG), electrocardiogram (ECG) and electromyogram (EMG) were measured to verify the proposed system. The board size of the proposed system is 6 cm × 2.5 cm and the weight is 30 g. The total power consumption of the proposed system is 66 mW. Copyright © 2011 Informa UK, Ltd.

A Compact Polarization Imager

NASA Technical Reports Server (NTRS)

Thompson, Karl E.; Rust, David M.; Chen, Hua

1995-01-01

A new type of image detector has been designed to analyze the polarization of light simultaneously at all picture elements (pixels) in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a custom-designed charge-coupled device with signal-analysis circuitry, all integrated on a silicon chip. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Other applications include environmental monitoring and robot vision. Innovations in the IDID include two interleaved 512 x 1024 pixel imaging arrays (one for each polarization plane), large dynamic range (well depth of 10(exp 6) electrons per pixel), simultaneous readout and display of both images at 10(exp 6) pixels per second, and on-chip analog signal processing to produce polarization maps in real time. When used with a lithium niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can reveal tiny differences between simultaneous images at two wavelengths.

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

SVGA and XGA active matrix microdisplays for head-mounted applications

NASA Astrophysics Data System (ADS)

Alvelda, Phillip; Bolotski, Michael; Brown, Imani L.

2000-03-01

The MicroDisplay Corporation's liquid crystal on silicon (LCOS) display devices are based on the union of several technologies with the extreme integration capability of conventionally fabricated CMOS substrates. The fast liquid crystal operation modes and new scalable high-performance pixel addressing architectures presented in this paper enable substantially improved color, contrast, and brightness while still satisfying the optical, packaging, and power requirements of portable applications. The entire suite of MicroDisplay's technologies was devised to create a line of mixed-signal application-specific integrated circuits (ASICs) in single-chip display systems. Mixed-signal circuits can integrate computing, memory, and communication circuitry on the same substrate as the display drivers and pixel array for a multifunctional complete system-on-a-chip. System-on-a-chip benefits also include reduced head supported weight requirements through the elimination of off-chip drive electronics.

Identification of conformational epitopes for human IgG on Chemotaxis inhibitory protein of Staphylococcus aureus

PubMed Central

Gustafsson, Erika; Haas, Pieter-Jan; Walse, Björn; Hijnen, Marcel; Furebring, Christina; Ohlin, Mats; van Strijp, Jos AG; van Kessel, Kok PM

2009-01-01

Background The Chemotaxis inhibitory protein of Staphylococcus aureus (CHIPS) blocks the Complement fragment C5a receptor (C5aR) and formylated peptide receptor (FPR) and is thereby a potent inhibitor of neutrophil chemotaxis and activation of inflammatory responses. The majority of the healthy human population has antibodies against CHIPS that have been shown to interfere with its function in vitro. The aim of this study was to define potential epitopes for human antibodies on the CHIPS surface. We also initiate the process to identify a mutated CHIPS molecule that is not efficiently recognized by preformed anti-CHIPS antibodies and retains anti-inflammatory activity. Results In this paper, we panned peptide displaying phage libraries against a pool of CHIPS specific affinity-purified polyclonal human IgG. The selected peptides could be divided into two groups of sequences. The first group was the most dominant with 36 of the 48 sequenced clones represented. Binding to human affinity-purified IgG was verified by ELISA for a selection of peptide sequences in phage format. For further analysis, one peptide was chemically synthesized and antibodies affinity-purified on this peptide were found to bind the CHIPS molecule as studied by ELISA and Surface Plasmon Resonance. Furthermore, seven potential conformational epitopes responsible for antibody recognition were identified by mapping phage selected peptide sequences on the CHIPS surface as defined in the NMR structure of the recombinant CHIPS31–121 protein. Mapped epitopes were verified by in vitro mutational analysis of the CHIPS molecule. Single mutations introduced in the proposed antibody epitopes were shown to decrease antibody binding to CHIPS. The biological function in terms of C5aR signaling was studied by flow cytometry. A few mutations were shown to affect this biological function as well as the antibody binding. Conclusion Conformational epitopes recognized by human antibodies have been mapped on the CHIPS surface and amino acid residues involved in both antibody and C5aR interaction could be defined. This information has implications for the development of an effective anti-inflammatory agent based on a functional CHIPS molecule with low interaction with human IgG. PMID:19284584

Towards High Throughput Cell Growth Screening: A New CMOS 8 × 8 Biosensor Array for Life Science Applications.

PubMed

Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Letourneau, Antoine; Sawan, Mohamad

2017-04-01

In this paper we present a CMOS capacitive sensor array as a compact and low-cost platform for high-throughput cell growth monitoring. The proposed biosensor, consists of an array of 8 × 8 CMOS fully differential charge-based capacitive measurement sensors. A DC-input Σ∆ modulator is used to convert the sensors' signals to digital values for reading out the biological/chemical data and further signal processing. To compensate the mismatch variations between the current mirror transistors, a calibration circuitry is proposed which removes the output voltage offset with less than 8.2% error. We validate the chip functionality using various organic solvents with different dielectric constants. Moreover, we show the response of the chip to different concentrations of Polystyrene beads that have the same electrical properties as the living cells. The experimental results show that the chip allows the detection of a wide range of Polystyrene beads concentrations from as low as 10 beads/ml to 100 k beads/ml. In addition, we present the experimental results from H1299 (human lung carcinoma) cell line where we show that the chip successfully allows the detection of cell attachment and growth over capacitive electrodes in a 30 h measurement time and the results are in consistency with the standard cell-based assays. The capability of proposed device for label-free and real-time detection of cell growth with very high sensitivity opens up the important opportunity for utilizing the device in rapid screening of living cells.

A Decade of Boon or Burden: What Has the CHIP Ever Done for Cellular Protein Quality Control Mechanism Implicated in Neurodegeneration and Aging?

PubMed Central

Joshi, Vibhuti; Amanullah, Ayeman; Upadhyay, Arun; Mishra, Ribhav; Kumar, Amit; Mishra, Amit

2016-01-01

Cells regularly synthesize new proteins to replace old and abnormal proteins for normal cellular functions. Two significant protein quality control pathways inside the cellular milieu are ubiquitin proteasome system (UPS) and autophagy. Autophagy is known for bulk clearance of cytoplasmic aggregated proteins, whereas the specificity of protein degradation by UPS comes from E3 ubiquitin ligases. Few E3 ubiquitin ligases, like C-terminus of Hsc70-interacting protein (CHIP) not only take part in protein quality control pathways, but also plays a key regulatory role in other cellular processes like signaling, development, DNA damage repair, immunity and aging. CHIP targets misfolded proteins for their degradation through proteasome, as well as autophagy; simultaneously, with the help of chaperones, it also regulates folding attempts for misfolded proteins. The broad range of CHIP substrates and their associations with multiple pathologies make it a key molecule to work upon and focus for future therapeutic interventions. E3 ubiquitin ligase CHIP interacts and degrades many protein inclusions formed in neurodegenerative diseases. The presence of CHIP at various nodes of cellular protein-protein interaction network presents this molecule as a potential candidate for further research. In this review, we have explored a wide range of functionality of CHIP inside cells by a detailed presentation of its co-chaperone, E3 and E4 enzyme like functions, with central focus on its protein quality control roles in neurodegenerative diseases. We have also raised many unexplored but expected fundamental questions regarding CHIP functions, which generate hopes for its future applications in research, as well as drug discovery. PMID:27757073

Chip-based ingroove microplasma with orthogonal signal collection: new approach for carbon-containing species detection through open air reaction for performance enhancement

PubMed Central

Meng, Fanying; Li, Xuemei; Duan, Yixiang

2014-01-01

A novel microplasma generator based on ceramic chips has been developed and coupled with optical emission spectrometry through orthogonal detection. Stable microplasma was generated between two electrodes in the ingroove discharge chamber and the optical fiber was set in perpendicular to the gas outlet to collect emitted light. The emission signal of CN is surprisingly enhanced by reacting carbon-containing species with back-diffusion nitrogen from open air, and the enhanced CN signal is successfully applied to sensitively detect organic compounds for the first time. This article focuses to study the structural characteristic and the signal enhancement mechanism through back-diffusion reaction. Several organic compounds were detected directly with the limits of detection down to ppb level. Besides, the advantages of low energy consumption and the chip-based discharge chamber show great potential to be applied in portable devices. This development may lead to a new way for the sensitive detection of organic compounds. PMID:24763181

A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.

PubMed

Wang, Yi-Xiao; Chen, Wei-Ming; Wu, Chung-Yu

2014-01-01

This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 μW in the first PLL and 195 μW in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Low cost MATLAB-based pulse oximeter for deployment in research and development applications.

PubMed

Shokouhian, M; Morling, R C S; Kale, I

2013-01-01

Problems such as motion artifact and effects of ambient lights have forced developers to design different signal processing techniques and algorithms to increase the reliability and accuracy of the conventional pulse oximeter device. To evaluate the robustness of these techniques, they are applied either to recorded data or are implemented on chip to be applied to real-time data. Recorded data is the most common method of evaluating however it is not as reliable as real-time measurements. On the other hand, hardware implementation can be both expensive and time consuming. This paper presents a low cost MATLAB-based pulse oximeter that can be used for rapid evaluation of newly developed signal processing techniques and algorithms. Flexibility to apply different signal processing techniques, providing both processed and unprocessed data along with low implementation cost are the important features of this design which makes it ideal for research and development purposes, as well as commercial, hospital and healthcare application.

Ultra-low-power and robust digital-signal-processing hardware for implantable neural interface microsystems.

PubMed

Narasimhan, S; Chiel, H J; Bhunia, S

2011-04-01

Implantable microsystems for monitoring or manipulating brain activity typically require on-chip real-time processing of multichannel neural data using ultra low-power, miniaturized electronics. In this paper, we propose an integrated-circuit/architecture-level hardware design framework for neural signal processing that exploits the nature of the signal-processing algorithm. First, we consider different power reduction techniques and compare the energy efficiency between the ultra-low frequency subthreshold and conventional superthreshold design. We show that the superthreshold design operating at a much higher frequency can achieve comparable energy dissipation by taking advantage of extensive power gating. It also provides significantly higher robustness of operation and yield under large process variations. Next, we propose an architecture level preferential design approach for further energy reduction by isolating the critical computation blocks (with respect to the quality of the output signal) and assigning them higher delay margins compared to the noncritical ones. Possible delay failures under parameter variations are confined to the noncritical components, allowing graceful degradation in quality under voltage scaling. Simulation results using prerecorded neural data from the sea-slug (Aplysia californica) show that the application of the proposed design approach can lead to significant improvement in total energy, without compromising the output signal quality under process variations, compared to conventional design approaches.

Design of a lock-amplifier circuit

NASA Astrophysics Data System (ADS)

Liu, H.; Huang, W. J.; Song, X.; Zhang, W. Y.; Sa, L. B.

2017-01-01

The lock-in amplifier is recovered by phase sensitive detection technique for the weak signal submerged in the noise background. This design is based on the TI ultra low power LM358, INA129, OPA227, OP07 and other chips as the core design and production of the lock-in amplifier. Signal generator by 10m ohms /1K ohm resistance points pressure network 10 mu V 1mV adjustable sine wave signal s (T). The concomitant interference signal together through the AC amplifier and band-pass filter signal x (T), on the other hand reference signal R (T) driven by square wave phase shift etc. steps to get the signal R (T), two signals and by phase sensitive detector are a DC full wave, again through its low pass filter and a DC amplifier to be measured signal more accurate detection, the final circuit through the AD conversion and the use of single-chip will display the output.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Tarsa, Eric; Ibbetson, James; Morgan, Frederick; Dowling, Kevin; Lys, Ihor

2017-10-17

An LED component according to the present invention comprising an array of LED chips mounted on a submount with the LED chips capable of emitting light in response to an electrical signal. The array can comprise LED chips emitting at two colors of light wherein the LED component emits light comprising the combination of the two colors of light. A single lens is included over the array of LED chips. The LED chip array can emit light of greater than 800 lumens with a drive current of less than 150 milli-Amps. The LED chip component can also operate at temperatures less than 3000 degrees K. In one embodiment, the LED array is in a substantially circular pattern on the submount.

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

NASA Astrophysics Data System (ADS)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

AQP2 Abundance is Regulated by the E3-Ligase CHIP Via HSP70.

PubMed

Centrone, Mariangela; Ranieri, Marianna; Di Mise, Annarita; Berlingerio, Sante Princiero; Russo, Annamaria; Deen, Peter M T; Staub, Olivier; Valenti, Giovanna; Tamma, Grazia

2017-01-01

AQP2 expression is mainly controlled by vasopressin-dependent changes in protein abundance which is in turn regulated by AQP2 ubiquitylation and degradation, however the proteins involved in these processes are largely unknown. Here, we investigated the potential role of the CHIP E3 ligase in AQP2 regulation. MCD4 cells and kidney slices were used to study the involvement of the E3 ligase CHIP on AQP2 protein abundance by cell homogenization and immunoprecipitation followed by immunoblotting. We found that AQP2 complexes with CHIP in renal tissue. Expression of CHIP increased proteasomal degradation of AQP2 and HSP70 abundance, a molecular signature of HSP90 inhibition. Increased HSP70 level, secondary to CHIP expression, promoted ERK signaling resulting in increased AQP2 phosphorylation at S261. Phosphorylation of AQP2 at S256 and T269 were instead downregulated. Next, we investigated HSP70 interaction with AQP2, which is important for endocytosis. Compared with AQP2-wt, HSP70 binding decreased in AQP2-S256D and AQP2-S256D-S261D, while increased in AQP2-S256D-S261A. Surprisingly, expression of CHIP-delUbox, displaying a loss of E3 ligase activity, still induced AQP2 degradation, indicating that CHIP does not ubiquitylate and degrade AQP2 itself. Conversely, the AQP2 half-life was increased upon the expression of CHIP-delTPR a domain which binds Hsc70/HSP70 and HSP90. HSP70 has been reported to bind other E3 ligases such as MDM2. Notably, we found that co-expression of CHIP and MDM2 increased AQP2 degradation, whereas co-expression of CHIP with MDM2-delRING, an inactive form of MDM2, impaired AQP2 degradation. Our findings indicate CHIP as a master regulator of AQP2 degradation via HSP70 that has dual functions: (1) as chaperone for AQP2 and (2) as an anchoring protein for MDM2 E3 ligase, which is likely to be involved in AQP2 degradation. © 2017 The Author(s). Published by S. Karger AG, Basel.

Design of an intelligent instrument for large direct-current measurement

NASA Astrophysics Data System (ADS)

Zhang, Rong; Zhang, Gang; Zhang, Zhipeng

2000-05-01

The principle and structure of an intelligent large direct current measurement is presented in this paper. It is of reflective type and detects signal by employing the high direct current sensor. The single-chip microcomputer of this system provides a powerful function of control and processing and greatly improves the extent of intelligence. The value can be displayed and printed automatically or manually.

Ultralow-power all-optical processing of high-speed data signals in deposited silicon waveguides.

PubMed

Wang, Ke-Yao; Petrillo, Keith G; Foster, Mark A; Foster, Amy C

2012-10-22

Utilizing a 6-mm-long hydrogenated amorphous silicon nanowaveguide, we demonstrate error-free (BER < 10(-9)) 160-to-10 Gb/s OTDM demultiplexing using ultralow switching peak powers of 50 mW. This material is deposited at low temperatures enabling a path toward multilayer integration and therefore massive scaling of the number of devices in a single photonic chip.

Highly efficient on-chip direct electronic-plasmonic transducers

NASA Astrophysics Data System (ADS)

Du, Wei; Wang, Tao; Chu, Hong-Son; Nijhuis, Christian A.

2017-10-01

Photonic elements can carry information with a capacity exceeding 1,000 times that of electronic components, but, due to the optical diffraction limit, these elements are large and difficult to integrate with modern-day nanoelectronics or upcoming packages, such as three-dimensional integrated circuits or stacked high-bandwidth memories1-3. Surface plasmon polaritons can be confined to subwavelength dimensions and can carry information at high speeds (>100 THz)4-6. To combine the small dimensions of nanoelectronics with the fast operating speed of optics via plasmonics, on-chip electronic-plasmonic transducers that directly convert electrical signals into plasmonic signals (and vice versa) are required. Here, we report electronic-plasmonic transducers based on metal-insulator-metal tunnel junctions coupled to plasmonic waveguides with high-efficiency on-chip generation, manipulation and readout of plasmons. These junctions can be readily integrated into existing technologies, and we thus believe that they are promising for applications in on-chip integrated plasmonic circuits.

Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

NASA Astrophysics Data System (ADS)

Blin, S.; Callier, S.; Conforti Di Lorenzo, S.; Dulucq, F.; De La Taille, C.; Martin-Chassard, G.; Seguin-Moreau, N.

2017-03-01

CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE PAGES

Kanisauskas, K.; Affolder, A.; Arndt, K.; ...

2017-02-15

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanisauskas, K.; Affolder, A.; Arndt, K.

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

CMOS compatible on-chip telecom-band to mid-infrared supercontinuum generation in dispersion-engineered reverse strip/slot hybrid Si3N4 waveguide

NASA Astrophysics Data System (ADS)

Hui, Zhanqiang; Zhang, Lingxuan; Zhang, Wenfu

2018-01-01

A silicon nitride (Si3N4)-based reverse strip/slot hybrid waveguide with single vertical silica slot is proposed to acquire extremely low and flat chromatic dispersion profile. This is achieved by design and optimization of the geometrical structural parameters of the reverse hybrid waveguide. The flat dispersion varying between ±10 ps/(nm.km) is obtained over 610 nm bandwidth. Both the effective area and nonlinear coefficient of the waveguide across the entire spectral range of interest are investigated. This led to design of an on-chip supercontinuum (SC) source with -30 dB bandwidth of 2996 nm covering from 1.209 to 4.205 μm. Furthermore, we discuss the output signal spectral and temporal characteristic as a function of the pump power. Our waveguide design offers a CMOS compatible, low-cost/high yield (no photolithography or lift-off processes are necessary) on-chip SC source for near- and mid-infrared nonlinear applications.

On-Chip Fluorescence Switching System for Constructing a Rewritable Random Access Data Storage Device.

PubMed

Nguyen, Hoang Hiep; Park, Jeho; Hwang, Seungwoo; Kwon, Oh Seok; Lee, Chang-Soo; Shin, Yong-Beom; Ha, Tai Hwan; Kim, Moonil

2018-01-10

We report the development of on-chip fluorescence switching system based on DNA strand displacement and DNA hybridization for the construction of a rewritable and randomly accessible data storage device. In this study, the feasibility and potential effectiveness of our proposed system was evaluated with a series of wet experiments involving 40 bits (5 bytes) of data encoding a 5-charactered text (KRIBB). Also, a flexible data rewriting function was achieved by converting fluorescence signals between "ON" and "OFF" through DNA strand displacement and hybridization events. In addition, the proposed system was successfully validated on a microfluidic chip which could further facilitate the encoding and decoding process of data. To the best of our knowledge, this is the first report on the use of DNA hybridization and DNA strand displacement in the field of data storage devices. Taken together, our results demonstrated that DNA-based fluorescence switching could be applicable to construct a rewritable and randomly accessible data storage device through controllable DNA manipulations.

Fully Integrated Optical Spectrometer in Visible and Near-IR in CMOS.

PubMed

Hong, Lingyu; Sengupta, Kaushik

2017-12-01

Optical spectrometry in the visible and near-infrared range has a wide range of applications in healthcare, sensing, imaging, and diagnostics. This paper presents the first fully integrated optical spectrometer in standard bulk CMOS process without custom fabrication, postprocessing, or any external optical passive structure such as lenses, gratings, collimators, or mirrors. The architecture exploits metal interconnect layers available in CMOS processes with subwavelength feature sizes to guide, manipulate, control, diffract light, integrated photodetector, and read-out circuitry to detect dispersed light, and then back-end signal processing for robust spectral estimation. The chip, realized in bulk 65-nm low power-CMOS process, measures 0.64 mm 0.56 mm in active area, and achieves 1.4 nm in peak detection accuracy for continuous wave excitations between 500 and 830 nm. This paper demonstrates the ability to use these metal-optic nanostructures to miniaturize complex optical instrumentation into a new class of optics-free CMOS-based systems-on-chip in the visible and near-IR for various sensing and imaging applications.

Differential ubiquitination of Smad1 mediated by CHIP: implications in the regulation of the bone morphogenetic protein signaling pathway.

PubMed

Li, Ren-Feng; Shang, Yu; Liu, Di; Ren, Ze-Song; Chang, Zhijie; Sui, Sen-Fang

2007-11-30

Smad1, a downstream regulator of the bone morphogenetic protein (BMP) receptors, is tightly regulated by the ubiquitin-proteasomal degradation system. To dissect the mechanisms that underlie the regulation of Smad1, it is important to investigate the specific ubiquitination site(s) in Smad1. Here we report that the alpha-NH(2) group of the N terminus and the epsilon-NH(2) groups of internal lysine residues 116, 118 and 269 (K116, K118 and K269) of Smad1 are ubiquitin acceptor sites mediated by the carboxyl terminus of Hsc70-interacting protein (CHIP). The in vitro degradation assay indicates that ubiquitination at the N terminus partially contributes to the degradation of Smad1. Furthermore, we demonstrate that the ubiquitination level of pseudo-phosphorylated Smad1 by CHIP is stronger than that of wild-type Smad1 and can be strongly inhibited by a phosphorylated tail of Smad1, PIS(pS)V(pS). Third, our results indicate that Hsp70 facilitates CHIP-mediated poly-ubiquitination of Smad1 whereas it attenuates CHIP-meditated mono-ubiquitination of Smad1. Finally, consistent with the in vitro observation, we show that CHIP preferentially mediates the degradation of phospho-Smad1/5 in vivo. Taken together, these results provide us a hint that CHIP might preferentially regulate phosphorylated Smad1 and thus the BMP signaling.

Intelligent lightening system of urban and rural road traffic based on pyroelectric infrared detector

NASA Astrophysics Data System (ADS)

Miao, Man-Xiang

2007-12-01

By using the photo-voltage characteristics of pyroelectric infrared detector to fulfill signal acquisition, the detecting signal is processed with the core of a single chip microprocessor AT89C51. AT89C51 controls the CAN bus controller SJA1000/transceiver 82C250 to structure CAN bus communication system to transmit data through serial interface MAX232 connected with PC. The intelligent lightening system of urban and rural road traffic was carried out. In this paper, its construction and part's methods of hardware and software design were introduced in detail.

An 81.6 μW FastICA processor for epileptic seizure detection.

PubMed

Yang, Chia-Hsiang; Shih, Yi-Hsin; Chiueh, Herming

2015-02-01

To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 mm(2). The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 μW at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 × computation speedup are achieved. The performance of the chip was verified by human dataset.

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

NASA Astrophysics Data System (ADS)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

An Integrated Imaging Detector of Polarization and Spectral Content

NASA Technical Reports Server (NTRS)

Rust, D. M.; Thompson, K. E.

1993-01-01

A new type of image detector has been designed to simultaneously analyze the polarization of light at all picture elements in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. It should be capable of 1:10(exp 4) polarization discrimination. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Innovations in the IDID include (1) two interleaved 512 x 1024-pixel imaging arrays (one for each polarization plane); (2) large dynamic range (well depth of 10(exp 6) electrons per pixel); (3) simultaneous readout of both images at 10 million pixels per second each; (4) on-chip analog signal processing to produce polarization maps in real time; (5) on-chip 10-bit A/D conversion. When used with a lithium-niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can collect and analyze simultaneous images at two wavelengths. Precise photometric analysis of molecular or atomic concentrations in the atmosphere is one suggested application. When used in a solar telescope, the IDID will charge the polarization, which can then be converted to maps of the vector magnetic fields on the solar surface.

Smart image sensors: an emerging key technology for advanced optical measurement and microsystems

NASA Astrophysics Data System (ADS)

Seitz, Peter

1996-08-01

Optical microsystems typically include photosensitive devices, analog preprocessing circuitry and digital signal processing electronics. The advances in semiconductor technology have made it possible today to integrate all photosensitive and electronical devices on one 'smart image sensor' or photo-ASIC (application-specific integrated circuits containing photosensitive elements). It is even possible to provide each 'smart pixel' with additional photoelectronic functionality, without compromising the fill factor substantially. This technological capability is the basis for advanced cameras and optical microsystems showing novel on-chip functionality: Single-chip cameras with on- chip analog-to-digital converters for less than $10 are advertised; image sensors have been developed including novel functionality such as real-time selectable pixel size and shape, the capability of performing arbitrary convolutions simultaneously with the exposure, as well as variable, programmable offset and sensitivity of the pixels leading to image sensors with a dynamic range exceeding 150 dB. Smart image sensors have been demonstrated offering synchronous detection and demodulation capabilities in each pixel (lock-in CCD), and conventional image sensors are combined with an on-chip digital processor for complete, single-chip image acquisition and processing systems. Technological problems of the monolithic integration of smart image sensors include offset non-uniformities, temperature variations of electronic properties, imperfect matching of circuit parameters, etc. These problems can often be overcome either by designing additional compensation circuitry or by providing digital correction routines. Where necessary for technological or economic reasons, smart image sensors can also be combined with or realized as hybrids, making use of commercially available electronic components. It is concluded that the possibilities offered by custom smart image sensors will influence the design and the performance of future electronic imaging systems in many disciplines, reaching from optical metrology to machine vision on the factory floor and in robotics applications.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

PubMed Central

Ballini, Marco; Müller, Jan; Livi, Paolo; Chen, Yihui; Frey, Urs; Stettler, Alexander; Shadmani, Amir; Viswam, Vijay; Jones, Ian Lloyd; Jäckel, David; Radivojevic, Milos; Lewandowska, Marta K.; Gong, Wei; Fiscella, Michele; Bakkum, Douglas J.; Heer, Flavio; Hierlemann, Andreas

2017-01-01

To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm2) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μVrms in the action-potential band (300 Hz–10 kHz) and 5.4 μVrms in the local-field-potential band (1 Hz–300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures. PMID:28502989

Fast and Precise Emulation of Stochastic Biochemical Reaction Networks With Amplified Thermal Noise in Silicon Chips.

PubMed

Kim, Jaewook; Woo, Sung Sik; Sarpeshkar, Rahul

2018-04-01

The analysis and simulation of complex interacting biochemical reaction pathways in cells is important in all of systems biology and medicine. Yet, the dynamics of even a modest number of noisy or stochastic coupled biochemical reactions is extremely time consuming to simulate. In large part, this is because of the expensive cost of random number and Poisson process generation and the presence of stiff, coupled, nonlinear differential equations. Here, we demonstrate that we can amplify inherent thermal noise in chips to emulate randomness physically, thus alleviating these costs significantly. Concurrently, molecular flux in thermodynamic biochemical reactions maps to thermodynamic electronic current in a transistor such that stiff nonlinear biochemical differential equations are emulated exactly in compact, digitally programmable, highly parallel analog "cytomorphic" transistor circuits. For even small-scale systems involving just 80 stochastic reactions, our 0.35-μm BiCMOS chips yield a 311× speedup in the simulation time of Gillespie's stochastic algorithm over COPASI, a fast biochemical-reaction software simulator that is widely used in computational biology; they yield a 15 500× speedup over equivalent MATLAB stochastic simulations. The chip emulation results are consistent with these software simulations over a large range of signal-to-noise ratios. Most importantly, our physical emulation of Poisson chemical dynamics does not involve any inherently sequential processes and updates such that, unlike prior exact simulation approaches, they are parallelizable, asynchronous, and enable even more speedup for larger-size networks.

Low-complexity camera digital signal imaging for video document projection system

NASA Astrophysics Data System (ADS)

Hsia, Shih-Chang; Tsai, Po-Shien

2011-04-01

We present high-performance and low-complexity algorithms for real-time camera imaging applications. The main functions of the proposed camera digital signal processing (DSP) involve color interpolation, white balance, adaptive binary processing, auto gain control, and edge and color enhancement for video projection systems. A series of simulations demonstrate that the proposed method can achieve good image quality while keeping computation cost and memory requirements low. On the basis of the proposed algorithms, the cost-effective hardware core is developed using Verilog HDL. The prototype chip has been verified with one low-cost programmable device. The real-time camera system can achieve 1270 × 792 resolution with the combination of extra components and can demonstrate each DSP function.

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

NASA Technical Reports Server (NTRS)

Aanstoos, J. V.; Snyder, W. E.

1981-01-01

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Novel microwave photonic fractional Hilbert transformer using a ring resonator-based optical all-pass filter.

PubMed

Zhuang, Leimeng; Khan, Muhammad Rezaul; Beeker, Willem; Leinse, Arne; Heideman, René; Roeloffzen, Chris

2012-11-19

We propose and demonstrate a novel wideband microwave photonic fractional Hilbert transformer implemented using a ring resonator-based optical all-pass filter. The full programmability of the ring resonator allows variable and arbitrary fractional order of the Hilbert transformer. The performance analysis in both frequency and time domain validates that the proposed implementation provides a good approximation to an ideal fractional Hilbert transformer. This is also experimentally verified by an electrical S₂₁ response characterization performed on a waveguide realization of a ring resonator. The waveguide-based structure allows the proposed Hilbert transformer to be integrated together with other building blocks on a photonic integrated circuit to create various system-level functionalities for on-chip microwave photonic signal processors. As an example, a circuit consisting of a splitter and a ring resonator has been realized which can perform on-chip phase control of microwave signals generated by means of optical heterodyning, and simultaneous generation of in-phase and quadrature microwave signals for a wide frequency range. For these functionalities, this simple and on-chip solution is considered to be practical, particularly when operating together with a dual-frequency laser. To our best knowledge, this is the first-time on-chip demonstration where ring resonators are employed to perform phase control functionalities for optical generation of microwave signals by means of optical heterodyning.

Leverage principle of retardation signal in titration of double protein via chip moving reaction boundary electrophoresis.

PubMed

Zhang, Liu-Xia; Cao, Yi-Ren; Xiao, Hua; Liu, Xiao-Ping; Liu, Shao-Rong; Meng, Qing-Hua; Fan, Liu-Yin; Cao, Cheng-Xi

2016-03-15

In the present work we address a simple, rapid and quantitative analytical method for detection of different proteins present in biological samples. For this, we proposed the model of titration of double protein (TDP) and its relevant leverage theory relied on the retardation signal of chip moving reaction boundary electrophoresis (MRBE). The leverage principle showed that the product of the first protein content and its absolute retardation signal is equal to that of the second protein content and its absolute one. To manifest the model, we achieved theoretical self-evidence for the demonstration of the leverage principle at first. Then relevant experiments were conducted on the TDP-MRBE chip. The results revealed that (i) there was a leverage principle of retardation signal within the TDP of two pure proteins, and (ii) a lever also existed within these two complex protein samples, evidently demonstrating the validity of TDP model and leverage theory in MRBE chip. It was also showed that the proposed technique could provide a rapid and simple quantitative analysis of two protein samples in a mixture. Finally, we successfully applied the developed technique for the quantification of soymilk in adulterated infant formula. The TDP-MRBE opens up a new window for the detection of adulteration ratio of the poor food (milk) in blended high quality one. Copyright © 2015 Elsevier B.V. All rights reserved.

Matching Condition of Direct THz-Signal Detection from On-Chip Resonating Antennas with CMOS Transistors in Non-resonant Plasma Wave Mode

NASA Astrophysics Data System (ADS)

Chai, S.; Lim, S.; Kim, C.-Y.; Hong, S.

2018-06-01

This paper presents matching condition for detector at THz frequencies, which directly read signals from an integrated antenna. We use direct THz-signal detections with CMOS transistors in non-resonant plasma wave mode, which are embedded in on-chip resonating antennas. The detector detects THz envelope signals directly from the side edges of the on-chip patch antennas. The signal detection mechanism is studied in the view of the impedance conditions of the antenna and the detector. The detectors are implemented with stacked transistors structures to achieve high responsivity. The measured responsivities of the detectors with antenna impedances that were simulated to be 599.7, 912.3, 1565, and 3190.6 Ω agree well with the calculated values. Moreover, the responsivity dependence on the detector impedance is shown with two different input impedances of the detectors. Since CMOS circuit models from foundry are not accurate at frequencies higher than f t , the matching guideline between the antenna and the detector is very useful in designing high responsivity detectors. This study found that a detector has to have a large input impedance conjugately matched to the antenna's impedance to have high responsivity.

Matching Condition of Direct THz-Signal Detection from On-Chip Resonating Antennas with CMOS Transistors in Non-resonant Plasma Wave Mode

NASA Astrophysics Data System (ADS)

Chai, S.; Lim, S.; Kim, C.-Y.; Hong, S.

2018-04-01

This paper presents matching condition for detector at THz frequencies, which directly read signals from an integrated antenna. We use direct THz-signal detections with CMOS transistors in non-resonant plasma wave mode, which are embedded in on-chip resonating antennas. The detector detects THz envelope signals directly from the side edges of the on-chip patch antennas. The signal detection mechanism is studied in the view of the impedance conditions of the antenna and the detector. The detectors are implemented with stacked transistors structures to achieve high responsivity. The measured responsivities of the detectors with antenna impedances that were simulated to be 599.7, 912.3, 1565, and 3190.6 Ω agree well with the calculated values. Moreover, the responsivity dependence on the detector impedance is shown with two different input impedances of the detectors. Since CMOS circuit models from foundry are not accurate at frequencies higher than f t , the matching guideline between the antenna and the detector is very useful in designing high responsivity detectors. This study found that a detector has to have a large input impedance conjugately matched to the antenna's impedance to have high responsivity.

A binary search approach to whole-genome data analysis.

PubMed

Brodsky, Leonid; Kogan, Simon; Benjacob, Eshel; Nevo, Eviatar

2010-09-28

A sequence analysis-oriented binary search-like algorithm was transformed to a sensitive and accurate analysis tool for processing whole-genome data. The advantage of the algorithm over previous methods is its ability to detect the margins of both short and long genome fragments, enriched by up-regulated signals, at equal accuracy. The score of an enriched genome fragment reflects the difference between the actual concentration of up-regulated signals in the fragment and the chromosome signal baseline. The "divide-and-conquer"-type algorithm detects a series of nonintersecting fragments of various lengths with locally optimal scores. The procedure is applied to detected fragments in a nested manner by recalculating the lower-than-baseline signals in the chromosome. The algorithm was applied to simulated whole-genome data, and its sensitivity/specificity were compared with those of several alternative algorithms. The algorithm was also tested with four biological tiling array datasets comprising Arabidopsis (i) expression and (ii) histone 3 lysine 27 trimethylation CHIP-on-chip datasets; Saccharomyces cerevisiae (iii) spliced intron data and (iv) chromatin remodeling factor binding sites. The analyses' results demonstrate the power of the algorithm in identifying both the short up-regulated fragments (such as exons and transcription factor binding sites) and the long--even moderately up-regulated zones--at their precise genome margins. The algorithm generates an accurate whole-genome landscape that could be used for cross-comparison of signals across the same genome in evolutionary and general genomic studies.

Multi-dimensional spatial light communication made with on-chip InGaN photonic integration

NASA Astrophysics Data System (ADS)

Yang, Yongchao; Zhu, Bingcheng; Shi, Zheng; Wang, Jinyuan; Li, Xin; Gao, Xumin; Yuan, Jialei; Li, Yuanhang; Jiang, Yan; Wang, Yongjin

2017-04-01

Here, we propose, fabricate and characterize suspended photonic integration of InGaN multiple-quantum-well light-emitting diode (MQW-LED), waveguide and InGaN MQW-photodetector on a single chip. The unique light emission property of InGaN MQW-LED makes it feasible to establish multi-dimensional spatial data transmission using visible light. The in-plane light communication system is comprised of InGaN MQW-LED, waveguide and InGaN MQW-photodetector, and the out-of-plane data transmission is realized by detecting the free-space light emission via a commercial photodiode module. Moreover, a full-duplex light communication is experimentally demonstrated at a data transmission rate of 50 Mbps when both InGaN MQW-diodes operate under simultaneous light emission and detection mode. The in-plane superimposed signals are able to be extracted through the self-interference cancellation method, and the out-of-plane superimposed signals are in good agreement with the calculated signals according to the extracted transmitted signals. These results are promising for the development of on-chip InGaN photonic integration for diverse applications.

Modeling, Simulation and Design of Plasmonic Interconnects for On-Chip Signal Processing

DTIC Science & Technology

2011-02-14

integration and computation can be achieved by using the photonic detection devices such as the ultrafast photodectors and nanowire field transistors... infrared to optical frequencies, and their FDTD simulation results are shown in the middle diagram. In the right most diagram, the HSPICE simulation...FDTD simulation. The results tally very well to affirm that plasmonic nanowires can be simulated using circuit simulators like HSPICE to combine the

Research on intelligent monitoring technology of machining process

NASA Astrophysics Data System (ADS)

Wang, Taiyong; Meng, Changhong; Zhao, Guoli

1995-08-01

Based upon research on sound and vibration characteristics of tool condition, we explore the multigrade monitoring system which takes single-chip microcomputers as the core hardware. By using the specially designed pickup true signal devices, we can more effectively do the intelligent multigrade monitoring and forecasting, and furthermore, we can build the tool condition models adaptively. This is the key problem in FMS, CIMS, and even the IMS.

Quantized correlation coefficient for measuring reproducibility of ChIP-chip data.

PubMed

Peng, Shouyong; Kuroda, Mitzi I; Park, Peter J

2010-07-27

Chromatin immunoprecipitation followed by microarray hybridization (ChIP-chip) is used to study protein-DNA interactions and histone modifications on a genome-scale. To ensure data quality, these experiments are usually performed in replicates, and a correlation coefficient between replicates is used often to assess reproducibility. However, the correlation coefficient can be misleading because it is affected not only by the reproducibility of the signal but also by the amount of binding signal present in the data. We develop the Quantized correlation coefficient (QCC) that is much less dependent on the amount of signal. This involves discretization of data into set of quantiles (quantization), a merging procedure to group the background probes, and recalculation of the Pearson correlation coefficient. This procedure reduces the influence of the background noise on the statistic, which then properly focuses more on the reproducibility of the signal. The performance of this procedure is tested in both simulated and real ChIP-chip data. For replicates with different levels of enrichment over background and coverage, we find that QCC reflects reproducibility more accurately and is more robust than the standard Pearson or Spearman correlation coefficients. The quantization and the merging procedure can also suggest a proper quantile threshold for separating signal from background for further analysis. To measure reproducibility of ChIP-chip data correctly, a correlation coefficient that is robust to the amount of signal present should be used. QCC is one such measure. The QCC statistic can also be applied in a variety of other contexts for measuring reproducibility, including analysis of array CGH data for DNA copy number and gene expression data.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

A neural network device for on-line particle identification in cosmic ray experiments

NASA Astrophysics Data System (ADS)

Scrimaglio, R.; Finetti, N.; D'Altorio, L.; Rantucci, E.; Raso, M.; Segreto, E.; Tassoni, A.; Cardarilli, G. C.

2004-05-01

On-line particle identification is one of the main goals of many experiments in space both for rare event studies and for optimizing measurements along the orbital trajectory. Neural networks can be a useful tool for signal processing and real time data analysis in such experiments. In this document we report on the performances of a programmable neural device which was developed in VLSI analog/digital technology. Neurons and synapses were accomplished by making use of Operational Transconductance Amplifier (OTA) structures. In this paper we report on the results of measurements performed in order to verify the agreement of the characteristic curves of each elementary cell with simulations and on the device performances obtained by implementing simple neural structures on the VLSI chip. A feed-forward neural network (Multi-Layer Perceptron, MLP) was implemented on the VLSI chip and trained to identify particles by processing the signals of two-dimensional position-sensitive Si detectors. The radiation monitoring device consisted of three double-sided silicon strip detectors. From the analysis of a set of simulated data it was found that the MLP implemented on the neural device gave results comparable with those obtained with the standard method of analysis confirming that the implemented neural network could be employed for real time particle identification.

The research of data acquisition system for Raman spectrometer

NASA Astrophysics Data System (ADS)

Cui, Xiao; Guo, Pan; Zhang, Yinchao; Chen, Siying; Chen, He; Chen, Wenbo

2011-11-01

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*105(S-1PW-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

A systems approach for data compression and latency reduction in cortically controlled brain machine interfaces.

PubMed

Oweiss, Karim G

2006-07-01

This paper suggests a new approach for data compression during extracutaneous transmission of neural signals recorded by high-density microelectrode array in the cortex. The approach is based on exploiting the temporal and spatial characteristics of the neural recordings in order to strip the redundancy and infer the useful information early in the data stream. The proposed signal processing algorithms augment current filtering and amplification capability and may be a viable replacement to on chip spike detection and sorting currently employed to remedy the bandwidth limitations. Temporal processing is devised by exploiting the sparseness capabilities of the discrete wavelet transform, while spatial processing exploits the reduction in the number of physical channels through quasi-periodic eigendecomposition of the data covariance matrix. Our results demonstrate that substantial improvements are obtained in terms of lower transmission bandwidth, reduced latency and optimized processor utilization. We also demonstrate the improvements qualitatively in terms of superior denoising capabilities and higher fidelity of the obtained signals.

The integrated design and archive of space-borne signal processing and compression coding

NASA Astrophysics Data System (ADS)

He, Qiang-min; Su, Hao-hang; Wu, Wen-bo

2017-10-01

With the increasing demand of users for the extraction of remote sensing image information, it is very urgent to significantly enhance the whole system's imaging quality and imaging ability by using the integrated design to achieve its compact structure, light quality and higher attitude maneuver ability. At this present stage, the remote sensing camera's video signal processing unit and image compression and coding unit are distributed in different devices. The volume, weight and consumption of these two units is relatively large, which unable to meet the requirements of the high mobility remote sensing camera. This paper according to the high mobility remote sensing camera's technical requirements, designs a kind of space-borne integrated signal processing and compression circuit by researching a variety of technologies, such as the high speed and high density analog-digital mixed PCB design, the embedded DSP technology and the image compression technology based on the special-purpose chips. This circuit lays a solid foundation for the research of the high mobility remote sensing camera.

QI2S - Quick Image Interpretation System

NASA Astrophysics Data System (ADS)

Naghmouchi, Jamin; Aviely, Peleg; Ginosar, Ran; Ober, Giovanna; Bischoff, Ole; Nadler, Ron; Guiser, David; Citroen, Meira; Freddi, Riccardo; Berekovic, Mladen

2015-09-01

The evolution of the Earth Observation mission will be driven by many factors, and the deveploment of new processing paradigms to facilitate data downlink, handling and storage will be a key factor. Next generation EO satellites will generate a great amount of data at a very high data rate, both radar and optical. Real-time onboard processing can be the solution to reduce data downlink and management on ground. Radiometric, geometric, and atmospheric corrections of EO data as well as material/object detection in addition to the well-known needs for image compression and signal processing can be performed directly on board and the aim of QI2S project is to demonstrate this. QI2S, a concept prototype system for novel onboard image processing and image interpretation which has been designed, developed and validated in the framework of an EU FP7 project, targets these needs and makes a significant step towards exceeding current roadmaps of leading space agencies for future payload processors. The QI2S system features multiple chip components of the RC64, a novel rad-hard 64-core signal processing chip, which targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. It integrates advanced DSP cores with a multibank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high-speed serial links using SpaceFibre and other protocols. The processor is being developed within the European FP7 Framework Program and will be qualified to the highest space standards.

Comparison of laser Doppler and laser speckle contrast imaging using a concurrent processing system

NASA Astrophysics Data System (ADS)

Sun, Shen; Hayes-Gill, Barrie R.; He, Diwei; Zhu, Yiqun; Huynh, Nam T.; Morgan, Stephen P.

2016-08-01

Full field laser Doppler imaging (LDI) and single exposure laser speckle contrast imaging (LSCI) are directly compared using a novel instrument which can concurrently image blood flow using both LDI and LSCI signal processing. Incorporating a commercial CMOS camera chip and a field programmable gate array (FPGA) the flow images of LDI and the contrast maps of LSCI are simultaneously processed by utilizing the same detected optical signals. The comparison was carried out by imaging a rotating diffuser. LDI has a linear response to the velocity. In contrast, LSCI is exposure time dependent and does not provide a linear response in the presence of static speckle. It is also demonstrated that the relationship between LDI and LSCI can be related through a power law which depends on the exposure time of LSCI.

Controlling the type and the form of chip when machining steel

NASA Astrophysics Data System (ADS)

Gruby, S. V.; Lasukov, A. A.; Nekrasov, R. Yu; Politsinsky, E. V.; Arkhipova, D. A.

2016-08-01

The type of the chip produced in the process of machining influences many factors of production process. Controlling the type of chip when cutting metals is important for producing swarf chips and for easing its utilization as well as for protecting the machined surface, cutting tool and the worker. In the given work we provide the experimental data on machining structural steel with implanted tool. The authors show that it is possible to control the chip formation process to produce the required type of chip by selecting the material for machining the tool surface.

On-chip switch for reconfigurable mode-multiplexing optical network.

PubMed

Sun, Chunlei; Yu, Yu; Chen, Guanyu; Zhang, Xinliang

2016-09-19

The switching and routing is essential for an advanced and reconfigurable optical network, and great efforts have been done for traditional single-mode system. We propose and demonstrate an on-chip switch compatible with mode-division multiplexing system. By controlling the induced phase difference, the functionalities of dynamically routing data channels can be achieved. The proposed switch is experimentally demonstrated with low insertion loss of ~1 dB and high extinction ratio of ~20 dB over the C-band for OFF-ON switchover. For further demonstration, the non-return-to-zero on-off keying signals at 10 Gb/s carried on the two spatial modes are successfully processed. Open and clear eye diagrams can be observed and the bit error rate measurements indicate a good data routing performance.

Detection system of capillary array electrophoresis microchip based on optical fiber

NASA Astrophysics Data System (ADS)

Yang, Xiaobo; Bai, Haiming; Yan, Weiping

2009-11-01

To meet the demands of the post-genomic era study and the large parallel detections of epidemic diseases and drug screening, the high throughput micro-fluidic detection system is needed urgently. A scanning laser induced fluorescence detection system based on optical fiber has been established by using a green laser diode double-pumped solid-state laser as excitation source. It includes laser induced fluorescence detection subsystem, capillary array electrophoresis micro-chip, channel identification unit and fluorescent signal processing subsystem. V-shaped detecting probe composed with two optical fibers for transmitting the excitation light and detecting induced fluorescence were constructed. Parallel four-channel signal analysis of capillary electrophoresis was performed on this system by using Rhodamine B as the sample. The distinction of different samples and separation of samples were achieved with the constructed detection system. The lowest detected concentration is 1×10-5 mol/L for Rhodamine B. The results show that the detection system possesses some advantages, such as compact structure, better stability and higher sensitivity, which are beneficial to the development of microminiaturization and integration of capillary array electrophoresis chip.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

A 12b 200kS/s 0.52mA 0.47mm2 Algorithmic A/D Converter for MEMS Applications

NASA Astrophysics Data System (ADS)

Kim, Young-Ju; Choi, Hee-Cheol; Lee, Seung-Hoon; Cho, Dongil “Dan”

This work describes a 12b 200kS/s 0.52mA 0.47mm2 ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200kS/s and 10kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18μm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200kS/s, respectively. The ADC occupies an active die area of 0.47mm2 and consumes 0.94mW at 200kS/s and 0.63mW at 10kS/s with a 1.8V supply.

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

NASA Technical Reports Server (NTRS)

Ruiz, B. Ian; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

Applications of SPICE for modeling miniaturized biomedical sensor systems

NASA Technical Reports Server (NTRS)

Mundt, C. W.; Nagle, H. T.

2000-01-01

This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.

DINS Final Report.

DTIC Science & Technology

1979-10-19

A optical input from a laser ggw system . The photodetector assembly shall consist of two chips: (1) photodiode chip and (2) preamplifier chip. The...181 4.1 Transienit Gamm ------ - 182 4.2 Therm~al Noise ------------------- 186 2 1 System F’unatioma Diagram -B 2 Bonding...5 2u.0 ed IG o Hl MM The desJign reurnents of the DIM~ Pbto detector System are - The system sball 1eev a 300 nhnowatt, (Min.) 63282 signal from a

High-definition video display based on the FPGA and THS8200

NASA Astrophysics Data System (ADS)

Qian, Jia; Sui, Xiubao

2014-11-01

This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

Femtosecond laser fabrication of fiber based optofluidic platform for flow cytometry applications

NASA Astrophysics Data System (ADS)

Serhatlioglu, Murat; Elbuken, Caglar; Ortac, Bulend; Solmaz, Mehmet E.

2017-02-01

Miniaturized optofluidic platforms play an important role in bio-analysis, detection and diagnostic applications. The advantages of such miniaturized devices are extremely low sample requirement, low cost development and rapid analysis capabilities. Fused silica is advantageous for optofluidic systems due to properties such as being chemically inert, mechanically stable, and optically transparent to a wide spectrum of light. As a three dimensional manufacturing method, femtosecond laser scanning followed by chemical etching shows great potential to fabricate glass based optofluidic chips. In this study, we demonstrate fabrication of all-fiber based, optofluidic flow cytometer in fused silica glass by femtosecond laser machining. 3D particle focusing was achieved through a straightforward planar chip design with two separately fabricated fused silica glass slides thermally bonded together. Bioparticles in a fluid stream encounter with optical interrogation region specifically designed to allocate 405nm single mode fiber laser source and two multi-mode collection fibers for forward scattering (FSC) and side scattering (SSC) signals detection. Detected signal data collected with oscilloscope and post processed with MATLAB script file. We were able to count number of events over 4000events/sec, and achieve size distribution for 5.95μm monodisperse polystyrene beads using FSC and SSC signals. Our platform shows promise for optical and fluidic miniaturization of flow cytometry systems.

Polarization division multiplexing for optical data communications

NASA Astrophysics Data System (ADS)

Ivanovich, Darko; Powell, Samuel B.; Gruev, Viktor; Chamberlain, Roger D.

2018-02-01

Multiple parallel channels are ubiquitous in optical communications, with spatial division multiplexing (separate physical paths) and wavelength division multiplexing (separate optical wavelengths) being the most common forms. Here, we investigate the viability of polarization division multiplexing, the separation of distinct parallel optical communication channels through the polarization properties of light. Two or more linearly polarized optical signals (at different polarization angles) are transmitted through a common medium, filtered using aluminum nanowire optical filters fabricated on-chip, and received using individual silicon photodetectors (one per channel). The entire receiver (including optics) is compatible with standard CMOS fabrication processes. The filter model is based upon an input optical signal formed as the sum of the Stokes vectors for each individual channel, transformed by the Mueller matrix that models the filter proper, resulting in an output optical signal that impinges on each photodiode. The results show that two- and three-channel systems can operate with a fixed-threshold comparator in the receiver circuit, but four-channel systems (and larger) will require channel coding of some form. For example, in the four-channel system, 10 of 16 distinct bit patterns are separable by the receiver. The model supports investigation of the range of variability tolerable in the fabrication of the on-chip polarization filters.

Coplanar electrode microfluidic chip enabling accurate sheathless impedance cytometry.

PubMed

De Ninno, Adele; Errico, Vito; Bertani, Francesca Romana; Businaro, Luca; Bisegna, Paolo; Caselli, Federica

2017-03-14

Microfluidic impedance cytometry offers a simple non-invasive method for single-cell analysis. Coplanar electrode chips are especially attractive due to ease of fabrication, yielding miniaturized, reproducible, and ultimately low-cost devices. However, their accuracy is challenged by the dependence of the measured signal on particle trajectory within the interrogation volume, that manifests itself as an error in the estimated particle size, unless any kind of focusing system is used. In this paper, we present an original five-electrode coplanar chip enabling accurate particle sizing without the need for focusing. The chip layout is designed to provide a peculiar signal shape from which a new metric correlating with particle trajectory can be extracted. This metric is exploited to correct the estimated size of polystyrene beads of 5.2, 6 and 7 μm nominal diameter, reaching coefficient of variations lower than the manufacturers' quoted values. The potential impact of the proposed device in the field of life sciences is demonstrated with an application to Saccharomyces cerevisiae yeast.

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

Thermoacoustic chips with carbon nanotube thin yarn arrays.

PubMed

Wei, Yang; Lin, Xiaoyang; Jiang, Kaili; Liu, Peng; Li, Qunqing; Fan, Shoushan

2013-10-09

Aligned carbon nanotube (CNT) films drawn from CNT arrays have shown the potential as thermoacoustic loudspeakers. CNT thermoacoustic chips with robust structures are proposed to promote the applications. The silicon-based chips can play sound and fascinating rhythms by feeding alternating currents and audio signal to the suspending CNT thin yarn arrays across grooves in them. In additional to the thin yarns, experiments further revealed more essential elements of the chips, the groove depth and the interdigital electrodes. The sound pressure depends on the depth of the grooves, and the thermal wavelength can be introduced to define the influence-free depth. The interdigital fingers can effectively reduce the driving voltage, making the chips safe and easy to use. The chips were successfully assembled into earphones and have been working stably for about one year. The thermoacoustic chips can find many applications in consumer electronics and possibly improve the audiovisual experience.

Fiber-optic voltage measuring system

NASA Astrophysics Data System (ADS)

Ye, Miaoyuan; Nie, De-Xin; Li, Yan; Peng, Yu; Lin, Qi-Qing; Wang, Jing-Gang

1993-09-01

A new fibre optic voltage measuring system has been developed based on the electrooptic effect of bismuth germanium oxide (Bi4Ge3O12)crystal. It uses the LED as the light source. The light beam emitted from the light source is transmitted to the sensor through the optic fibre and the intensity of the output beam is changed by the applied voltage. This optic signal is transmitted to the PIN detector and converted to an electric signal which is processed by the electronic circuit and 8098 single chip microcomputer the output voltage signal obtained is directly proportional to the applied voltage. This paper describes the principle the configuration and the performance parameters of the system. Test results are evaluated and discussed.

Modeling of heat transfer in compacted machining chips during friction consolidation process

NASA Astrophysics Data System (ADS)

Abbas, Naseer; Deng, Xiaomin; Li, Xiao; Reynolds, Anthony

2018-04-01

The current study aims to provide an understanding of the heat transfer process in compacted aluminum alloy AA6061 machining chips during the friction consolidation process (FCP) through experimental investigations and mathematical modelling and numerical simulation. Compaction and friction consolidation of machining chips is the first stage of the Friction Extrusion Process (FEP), which is a novel method for recycling machining chips to produce useful products such as wires. In this study, compacted machining chips are modelled as a continuum whose material properties vary with density during friction consolidation. Based on density and temperature dependent thermal properties, the temperature field in the chip material and process chamber caused by frictional heating during the friction consolidation process is predicted. The predicted temperature field is found to compare well with temperature measurements at select points where such measurements can be made using thermocouples.

High-performance, scalable optical network-on-chip architectures

NASA Astrophysics Data System (ADS)

Tan, Xianfang

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption.

Analog signal processing for optical coherence imaging systems

NASA Astrophysics Data System (ADS)

Xu, Wei

Optical coherence tomography (OCT) and optical coherence microscopy (OCM) are non-invasive optical coherence imaging techniques, which enable micron-scale resolution, depth resolved imaging capability. Both OCT and OCM are based on Michelson interferometer theory. They are widely used in ophthalmology, gastroenterology and dermatology, because of their high resolution, safety and low cost. OCT creates cross sectional images whereas OCM obtains en face images. In this dissertation, the design and development of three increasingly complicated analog signal processing (ASP) solutions for optical coherence imaging are presented. The first ASP solution was implemented for a time domain OCT system with a Rapid Scanning Optical Delay line (RSOD)-based optical signal modulation and logarithmic amplifier (Log amp) based demodulation. This OCT system can acquire up to 1600 A-scans per second. The measured dynamic range is 106dB at 200A-scan per second. This OCT signal processing electronics includes an off-the-shelf filter box with a Log amp circuit implemented on a PCB board. The second ASP solution was developed for an OCM system with synchronized modulation and demodulation and compensation for interferometer phase drift. This OCM acquired micron-scale resolution, high dynamic range images at acquisition speeds up to 45,000 pixels/second. This OCM ASP solution is fully custom designed on a perforated circuit board. The third ASP solution was implemented on a single 2.2 mm x 2.2 mm complementary metal oxide semiconductor (CMOS) chip. This design is expandable to a multiple channel OCT system. A single on-chip CMOS photodetector and ASP channel was used for coherent demodulation in a time domain OCT system. Cross-sectional images were acquired with a dynamic range of 76dB (limited by photodetector responsivity). When incorporated with a bump-bonded InGaAs photodiode with higher responsivity, the expected dynamic range is close to 100dB.

Image processing using Gallium Arsenide (GaAs) technology

NASA Technical Reports Server (NTRS)

Miller, Warner H.

1989-01-01

The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.

Accuracy-energy configurable sensor processor and IoT device for long-term activity monitoring in rare-event sensing applications.

PubMed

Park, Daejin; Cho, Jeonghun

2014-01-01

A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error.

Hybrid indium phosphide-on-silicon nanolaser diode

NASA Astrophysics Data System (ADS)

Crosnier, Guillaume; Sanchez, Dorian; Bouchoule, Sophie; Monnier, Paul; Beaudoin, Gregoire; Sagnes, Isabelle; Raj, Rama; Raineri, Fabrice

2017-04-01

The most-awaited convergence of microelectronics and photonics promises to bring about a revolution for on-chip data communications and processing. Among all the optoelectronic devices to be developed, power-efficient nanolaser diodes able to be integrated densely with silicon photonics and electronics are essential to convert electrical data into the optical domain. Here, we report a demonstration of ultracompact laser diodes based on one-dimensional (1D) photonic crystal (PhC) nanocavities made in InP nanoribs heterogeneously integrated on a silicon-waveguide circuitry. The specific nanorib design enables an efficient electrical injection of carriers in the nanocavity without spoiling its optical properties. Room-temperature continuous-wave (CW) single-mode operation is obtained with a low current threshold of 100 µA. Laser emission at 1.56 µm in the silicon waveguides is obtained with wall-plug efficiencies greater than 10%. This result opens up exciting avenues for constructing optical networks at the submillimetre scale for on-chip interconnects and signal processing.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

PubMed

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-03-28

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study

PubMed Central

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-01-01

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation. PMID:28350358

Optical sectioning in wide-field microscopy obtained by dynamic structured light illumination and detection based on a smart pixel detector array.

PubMed

Mitić, Jelena; Anhut, Tiemo; Meier, Matthias; Ducros, Mathieu; Serov, Alexander; Lasser, Theo

2003-05-01

Optical sectioning in wide-field microscopy is achieved by illumination of the object with a continuously moving single-spatial-frequency pattern and detecting the image with a smart pixel detector array. This detector performs an on-chip electronic signal processing that extracts the optically sectioned image. The optically sectioned image is directly observed in real time without any additional postprocessing.

Another expert system rule inference based on DNA molecule logic gates

NASA Astrophysics Data System (ADS)

WÄ siewicz, Piotr

2013-10-01

With the help of silicon industry microfluidic processors were invented utilizing nano membrane valves, pumps and microreactors. These so called lab-on-a-chips combined together with molecular computing create molecular-systems-ona- chips. This work presents a new approach to implementation of molecular inference systems. It requires the unique representation of signals by DNA molecules. The main part of this work includes the concept of logic gates based on typical genetic engineering reactions. The presented method allows for constructing logic gates with many inputs and for executing them at the same quantity of elementary operations, regardless of a number of input signals. Every microreactor of the lab-on-a-chip performs one unique operation on input molecules and can be connected by dataflow output-input connections to other ones.

Compression Debarking of Stored Wood Chips

Treesearch

James A. Mattson

1974-01-01

Two 750 ft. piles of unbarked chips were stored for 1 year to evaluate the effect of chip storage on the effectiveness of bark-chip separations-segregation methods under study. in processing stored chips suffered more wood loss than fresh chips.

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

White balance tester with color sensor for industrial applications

NASA Astrophysics Data System (ADS)

Chen, Jiasheng; Zhu, XiaoSong

1996-12-01

The white balance tester is an instrument that adjusts the white balance for color TVs, monitors, and PC displays. We have designed a new white balance tester for use directly at the production line. It picks up the R (Red), G (Green), and B (Blue) signals for the screen using color sensors, compares the signals with the data previously stored in the internal memory, displays their differences with LED bars in the compare mode or displays x y Y, u v Y, JND (just noticeable difference) as well as correlated color temperature in the numerical mode. A built-in TV signal generator sets the luminance of the adjusting screen to the brightness of the reference white screen automatically. A 16-bit single chip microcomputer processes the measured values and controls the output levels of the TV signal generator.

Fluorimetric urease inhibition assay on a multilayer microfluidic chip with immunoaffinity immobilized enzyme reactors.

PubMed

Zhang, Qin; Tang, Xiuwen; Hou, Fenghua; Yang, Jianping; Xie, Zhiyong; Cheng, Zhiyi

2013-10-01

We fabricated a three-layer polydimethylsiloxane (PDMS)-based microfluidic chip for realizing urease inhibition assay with sensitive fluorescence detection. Procedures such as sample prehandling, enzyme reaction, reagent mixing, fluorescence derivatization, and detection can be readily carried out. Urease reactors were prepared by adsorption of rabbit immunoglobulin G (IgG) and immunoreaction with urease-conjugated goat anti-rabbit IgG. Acetohydroxamic acid (AHA) as a competitive inhibitor of urease was tested on the chip. Microfluidically generated gradient concentrations of AHA with substrate (urea) were loaded into urease reactors. After incubation, the produced ammonia was transported out of reactors and then reacted with o-phthalaldehyde (OPA) to generate fluorescent products. Urease inhibition was indicated by a decrease in fluorescence signal detected by microplate reader. The IC50 value of AHA was determined and showed good agreement with that obtained in microplate. The presented device combines several steps of the analytical process with advantages of low reagent consumption, reduced analysis time, and ease of manipulation. This microfluidic approach can be extended to the screening of inhibitory compounds in drug discovery. Copyright © 2013 Elsevier Inc. All rights reserved.

Disposable MoS2-Arrayed MALDI MS Chip for High-Throughput and Rapid Quantification of Sulfonamides in Multiple Real Samples.

PubMed

Zhao, Yaju; Tang, Minmin; Liao, Qiaobo; Li, Zhoumin; Li, Hui; Xi, Kai; Tan, Li; Zhang, Mei; Xu, Danke; Chen, Hong-Yuan

2018-04-27

In this work, we demonstrate, for the first time, the development of a disposable MoS 2 -arrayed matrix-assisted laser desorption/ionization mass spectrometry (MALDI MS) chip combined with an immunoaffinity enrichment method for high-throughput, rapid, and simultaneous quantitation of multiple sulfonamides (SAs). The disposable MALDI MS chip was designed and fabricated by MoS 2 array formation on a commercial indium tin oxide (ITO) glass slide. A series of SAs were analyzed, and clear deprotonated signals were obtained in negative-ion mode. Compared with MoS 2 -arrayed commercial steel plate, the prepared MALDI MS chip exhibited comparable LDI efficiency, providing a good alternative and disposable substrate for MALDI MS analysis. Furthermore, internal standard (IS) was previously deposited onto the MoS 2 array to simplify the experimental process for MALDI MS quantitation. 96 sample spots could be analyzed within 10 min in one single chip to perform quantitative analysis, recovery studies, and real foodstuff detection. Upon targeted extraction and enrichment by antibody conjugated magnetic beads, five SAs were quantitatively determined by the IS-first method with the linear range of 0.5-10 ng/mL ( R 2 > 0.990). Good recoveries and repeatability were obtained for spiked pork, egg, and milk samples. SAs in several real foodstuffs were successfully identified and quantified. The developed method may provide a promising tool for the routine analysis of antibiotic residues in real samples.

On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

PubMed Central

Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

2016-01-01

An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

Sequencing of real-world samples using a microfabricated hybrid device having unconstrained straight separation channels.

PubMed

Liu, Shaorong; Elkin, Christopher; Kapur, Hitesh

2003-11-01

We describe a microfabricated hybrid device that consists of a microfabricated chip containing multiple twin-T injectors attached to an array of capillaries that serve as the separation channels. A new fabrication process was employed to create two differently sized round channels in a chip. Twin-T injectors were formed by the smaller round channels that match the bore of the separation capillaries and separation capillaries were incorporated to the injectors through the larger round channels that match the outer diameter of the capillaries. This allows for a minimum dead volume and provides a robust chip/capillary interface. This hybrid design takes full advantage, such as sample stacking and purification and uniform signal intensity profile, of the unique chip injection scheme for DNA sequencing while employing long straight capillaries for the separations. In essence, the separation channel length is optimized for both speed and resolution since it is unconstrained by chip size. To demonstrate the reliability and practicality of this hybrid device, we sequenced over 1000 real-world samples from Human Chromosome 5 and Ciona intestinalis, prepared at Joint Genome Institute. We achieved average Phred20 read of 675 bases in about 70 min with a success rate of 91%. For the similar type of samples on MegaBACE 1000, the average Phred20 read is about 550-600 bases in 120 min separation time with a success rate of about 80-90%.

Utilisation of chip thickness models in grinding

NASA Astrophysics Data System (ADS)

Singleton, Roger

Grinding is now a well established process utilised for both stock removal and finish applications. Although significant research is performed in this field, grinding still experiences problems with burn and high forces which can lead to poor quality components and damage to equipment. This generally occurs in grinding when the process deviates from its safe working conditions. In milling, chip thickness parameters are utilised to predict and maintain process outputs leading to improved control of the process. This thesis looks to further the knowledge of the relationship between chip thickness and the grinding process outputs to provide an increased predictive and maintenance modelling capability. Machining trials were undertaken using different chip thickness parameters to understand how these affect the process outputs. The chip thickness parameters were maintained at different grinding wheel diameters for a constant productivity process to determine the impact of chip thickness at a constant material removal rate.. Additional testing using a modified pin on disc test rig was performed to provide further information on process variables. The different chip thickness parameters provide control of different process outputs in the grinding process. These relationships can be described using contact layer theory and heat flux partitioning. The contact layer is defined as the immediate layer beneath the contact arc at the wheel workpiece interface. The size of the layer governs the force experienced during the process. The rate of contact layer removal directly impacts the net power required from the system. It was also found that the specific grinding energy of a process is more dependent on the productivity of a grinding process rather than the value of chip thickness. Changes in chip thickness at constant material removal rate result in microscale changes in the rate of contact layer removal when compared to changes in process productivity. This is a significant piece of information in relation to specific grinding energy where conventional theory states it is primarily dependent on chip thickness..

Ultrathin Polymer Membranes with Patterned, Micrometric Pores for Organs-on-Chips.

PubMed

Pensabene, Virginia; Costa, Lino; Terekhov, Alexander Y; Gnecco, Juan S; Wikswo, John P; Hofmeister, William H

2016-08-31

The basal lamina or basement membrane (BM) is a key physiological system that participates in physicochemical signaling between tissue types. Its formation and function are essential in tissue maintenance, growth, angiogenesis, disease progression, and immunology. In vitro models of the BM (e.g., Boyden and transwell chambers) are common in cell biology and lab-on-a-chip devices where cells require apical and basolateral polarization. Extravasation, intravasation, membrane transport of chemokines, cytokines, chemotaxis of cells, and other key functions are routinely studied in these models. The goal of the present study was to integrate a semipermeable ultrathin polymer membrane with precisely positioned pores of 2 μm diameter in a microfluidic device with apical and basolateral chambers. We selected poly(l-lactic acid) (PLLA), a transparent biocompatible polymer, to prepare the semipermeable ultrathin membranes. The pores were generated by pattern transfer using a three-step method coupling femtosecond laser machining, polymer replication, and spin coating. Each step of the fabrication process was characterized by scanning electron microscopy to investigate reliability of the process and fidelity of pattern transfer. In order to evaluate the compatibility of the fabrication method with organs-on-a-chip technology, porous PLLA membranes were embedded in polydimethylsiloxane (PDMS) microfluidic devices and used to grow human umbilical vein endothelial cells (HUVECS) on top of the membrane with perfusion through the basolateral chamber. Viability of cells, optical transparency of membranes and strong adhesion of PLLA to PDMS were observed, thus confirming the suitability of the prepared membranes for use in organs-on-a-chip devices.

Design and validation of a real-time spiking-neural-network decoder for brain-machine interfaces.

PubMed

Dethier, Julie; Nuyujukian, Paul; Ryu, Stephen I; Shenoy, Krishna V; Boahen, Kwabena

2013-06-01

Cortically-controlled motor prostheses aim to restore functions lost to neurological disease and injury. Several proof of concept demonstrations have shown encouraging results, but barriers to clinical translation still remain. In particular, intracortical prostheses must satisfy stringent power dissipation constraints so as not to damage cortex. One possible solution is to use ultra-low power neuromorphic chips to decode neural signals for these intracortical implants. The first step is to explore in simulation the feasibility of translating decoding algorithms for brain-machine interface (BMI) applications into spiking neural networks (SNNs). Here we demonstrate the validity of the approach by implementing an existing Kalman-filter-based decoder in a simulated SNN using the Neural Engineering Framework (NEF), a general method for mapping control algorithms onto SNNs. To measure this system's robustness and generalization, we tested it online in closed-loop BMI experiments with two rhesus monkeys. Across both monkeys, a Kalman filter implemented using a 2000-neuron SNN has comparable performance to that of a Kalman filter implemented using standard floating point techniques. These results demonstrate the tractability of SNN implementations of statistical signal processing algorithms on different monkeys and for several tasks, suggesting that a SNN decoder, implemented on a neuromorphic chip, may be a feasible computational platform for low-power fully-implanted prostheses. The validation of this closed-loop decoder system and the demonstration of its robustness and generalization hold promise for SNN implementations on an ultra-low power neuromorphic chip using the NEF.

MEMS-based thermally-actuated image stabilizer for cellular phone camera

NASA Astrophysics Data System (ADS)

Lin, Chun-Ying; Chiou, Jin-Chern

2012-11-01

This work develops an image stabilizer (IS) that is fabricated using micro-electro-mechanical system (MEMS) technology and is designed to counteract the vibrations when human using cellular phone cameras. The proposed IS has dimensions of 8.8 × 8.8 × 0.3 mm3 and is strong enough to suspend an image sensor. The processes that is utilized to fabricate the IS includes inductive coupled plasma (ICP) processes, reactive ion etching (RIE) processes and the flip-chip bonding method. The IS is designed to enable the electrical signals from the suspended image sensor to be successfully emitted out using signal output beams, and the maximum actuating distance of the stage exceeds 24.835 µm when the driving current is 155 mA. Depending on integration of MEMS device and designed controller, the proposed IS can decrease the hand tremor by 72.5%.

Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khare, Surhud; Somasekhar, Dinesh; More, Ankit

Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

Measured thermal images of a gallium arsenide power MMIC with and without RF applied to the input

NASA Astrophysics Data System (ADS)

Oxley, C. H.; Coaker, B. M.; Priestley, N. E.

2003-04-01

A gallium arsenide microwave monolithic integrated circuit (MMIC) power amplifier (M/ACom type MAAM71100) has been measured using infra-red microscope technology, with and without the application of a RF input signal. A reduction of approximately 10 °C in chip temperature was observed with the application of a RF input signal, which will influence the MTTF of the chip. Further, the measurement technique may be used to monitor the thermal impedance and dynamic cooling of RF power devices under operational conditions in complex circuits.

Chemiluminescence generation and detection in a capillary-driven microfluidic chip

NASA Astrophysics Data System (ADS)

Ramon, Charlotte; Temiz, Yuksel; Delamarche, Emmanuel

2017-02-01

The use of microfluidic technology represents a strong opportunity for providing sensitive, low-cost and rapid diagnosis at the point-of-care and such a technology might therefore support better, faster and more efficient diagnosis and treatment of patients at home and in healthcare settings both in developed and developing countries. In this work, we consider luminescence-based assays as an alternative to well-established fluorescence-based systems because luminescence does not require a light source or expensive optical components and is therefore a promising detection method for point-of-care applications. Here, we show a proof-of-concept of chemiluminescence (CL) generation and detection in a capillary-driven microfluidic chip for potential immunoassay applications. We employed a commercial acridan-based reaction, which is catalyzed by horseradish peroxidase (HRP). We investigated CL generation under flow conditions using a simplified immunoassay model where HRP is used instead of the complete sandwich immunocomplex. First, CL signals were generated in a capillary microfluidic chip by immobilizing HRP on a polydimethylsiloxane (PDMS) sealing layer using stencil deposition and flowing CL substrate through the hydrophilic channels. CL signals were detected using a compact (only 5×5×2.5 cm3) and custom-designed scanner, which was assembled for less than $30 and comprised a 128×1 photodiode array, a mini stepper motor, an Arduino microcontroller, and a 3D-printed housing. In addition, microfluidic chips having specific 30-μm-deep structures were fabricated and used to immobilize ensembles of 4.50 μm beads functionalized with HRP so as to generate high CL signals from capillary-driven chips.

Radiation hard programmable delay line for LHCb calorimeter upgrade

NASA Astrophysics Data System (ADS)

Mauricio, J.; Gascón, D.; Vilasís, X.; Picatoste, E.; Machefert, F.; Lefrancois, J.; Duarte, O.; Beigbeder, C.

2014-01-01

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.

Wireless Sensor Node for Autonomous Monitoring and Alerts in Remote Environments

NASA Technical Reports Server (NTRS)

Panangadan, Anand V. (Inventor); Monacos, Steve P. (Inventor)

2015-01-01

A method, apparatus, system, and computer program products provides personal alert and tracking capabilities using one or more nodes. Each node includes radio transceiver chips operating at different frequency ranges, a power amplifier, sensors, a display, and embedded software. The chips enable the node to operate as either a mobile sensor node or a relay base station node while providing a long distance relay link between nodes. The power amplifier enables a line-of-sight communication between the one or more nodes. The sensors provide a GPS signal, temperature, and accelerometer information (used to trigger an alert condition). The embedded software captures and processes the sensor information, provides a multi-hop packet routing protocol to relay the sensor information to and receive alert information from a command center, and to display the alert information on the display.

Electromechanical Displacement Detection With an On-Chip High Electron Mobility Transistor Amplifier

NASA Astrophysics Data System (ADS)

Oda, Yasuhiko; Onomitsu, Koji; Kometani, Reo; Warisawa, Shin-ichi; Ishihara, Sunao; Yamaguchi, Hiroshi

2011-06-01

We developed a highly sensitive displacement detection scheme for a GaAs-based electromechanical resonator using an integrated high electron mobility transistor (HEMT). Piezoelectric voltage generated by the vibration of the resonator is applied to the gate of the HEMT, resulting in the on-chip amplification of the signal voltage. This detection scheme achieves a displacement sensitivity of ˜9 pm·Hz-1/2, which is one of the highest among on-chip purely electrical displacement detection schemes at room temperature.

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

Antiseptic solutions modulate the paracrine-like activity of bone chips: differential impact of chlorhexidine and sodium hypochlorite.

PubMed

Sawada, Kosaku; Caballé-Serrano, Jordi; Bosshardt, Dieter D; Schaller, Benoit; Miron, Richard J; Buser, Daniel; Gruber, Reinhard

2015-09-01

Chemical decontamination increases the availability of bone grafts; however, it remains unclear whether antiseptic processing changes the biological activity of bone. Bone chips were incubated with four different antiseptic solutions including (1) povidone-iodine (0.5%), (2) chlorhexidine diguluconate (0.2%), (3) hydrogen peroxide (1%) and (4) sodium hypochlorite (0.25%). After 10 min. of incubation, changes in the capacity of the bone-conditioned medium (BCM) to modulate gene expression of gingival fibroblasts was investigated. Conditioned medium obtained from freshly prepared bone chips increased the expression of TGF-β target genes interleukin 11 (IL11), proteoglycan4 (PRG4), NADPH oxidase 4 (NOX4), and decreased the expression of adrenomedullin (ADM), and pentraxin 3 (PTX3) in gingival fibroblasts. Incubation of bone chips with 0.2% chlorhexidine, followed by vigorously washing resulted in a BCM with even higher expression of IL11, PRG4 and NOX4. These findings were also detected with a decrease in cell viability and an activation of apoptosis signalling. Chlorhexidine alone, at low concentrations, increased IL11, PRG4 and NOX4 expression, independent of the TGF-β receptor I kinase activity. In contrast, 0.25% sodium hypochlorite almost entirely abolished the activity of BCM, whereas the other two antiseptic solutions, 1% hydrogen peroxide and 0.5% povidone-iodine, had relatively no impact respectively. These in vitro findings demonstrate that incubation of bone chips with chlorhexidine differentially affects the activity of the respective BCM compared to the other antiseptic solutions. The data further suggest that the main effects are caused by chlorhexidine remaining in the BCM after repeated washing of the bone chips. © 2015 John Wiley & Sons A/S. Published by John Wiley & Sons Ltd.

Development of a cleaning process for uranium chips machined with a glycol-water-borax coolant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taylor, P.A.

1984-12-01

A chip-cleaning process has been developed to remove the new glycol-water-borax coolant from oralloy chips. The process involves storing the freshly cut chips in Freon-TDF until they are cleaned, washing with water, and displacing the water with Freon-TDF. The wash water can be reused many times and still yield clean chips and then be added to the coolant to make up for evaporative losses. The Freon-TDF will be cycled by evaporation. The cleaning facility is currently being designed and should be operational by April 1985.

Inhibition of the Hedgehog Signaling Pathway Depresses the Cigarette Smoke-Induced Malignant Transformation of 16HBE Cells on a Microfluidic Chip.

PubMed

Qin, Yong-Xin; Yang, Zhi-Hui; Du, Xiao-Hui; Zhao, Hui; Liu, Yuan-Bin; Guo, Zhe; Wang, Qi

2018-05-20

The hedgehog signaling system (HHS) plays an important role in the regulation of cell proliferation and differentiation during the embryonic phases. However, little is known about the involvement of HHS in the malignant transformation of cells. This study aimed to detect the role of HHS in the malignant transformation of human bronchial epithelial (16HBE) cells. In this study, two microfluidic chips were designed to investigate cigarette smoke extract (CSE)-induced malignant transformation of cells. Chip A contained a concentration gradient generator, while chip B had four cell chambers with a central channel. The 16HBE cells cultured in chip A were used to determine the optimal concentration of CSE for inducing malignant transformation. The 16HBE cells in chip B were cultured with 12.25% CSE (Group A), 12.25% CSE + 5 μmol/L cyclopamine (Group B), or normal complete medium as control for 8 months (Group C), to establish the in vitro lung inflammatory-cancer transformation model. The transformed cells were inoculated into 20 nude mice as cells alone (Group 1) or cells with cyclopamine (Group 2) for tumorigenesis testing. Expression of HHS proteins was detected by Western blot. Data were expressed as mean ± standard deviation. The t-test was used for paired samples, and the difference among groups was analyzed using a one-way analysis of variance. The optimal concentration of CSE was 12.25%. Expression of HHS proteins increased during the process of malignant transformation (Group B vs. Group A, F = 7.65, P < 0.05). After CSE exposure for 8 months, there were significant changes in cellular morphology, which allowed the transformed cells to grow into tumors in 40 days after being inoculated into nude mice. Cyclopamine could effectively depress the expression of HHS proteins (Group C vs. Group B, F = 6.47, P < 0.05) and prevent tumor growth in nude mice (Group 2 vs. Group 1, t = 31.59, P < 0.01). The activity of HHS is upregulated during the CSE-induced malignant transformation of 16HBE cells. Cyclopamine can effectively depress expression of HHS proteins in vitro and prevent tumor growth of the transformed cells in vivo.

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

NASA Astrophysics Data System (ADS)

Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

2018-04-01

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

On-Chip Microwave Quantum Hall Circulator

NASA Astrophysics Data System (ADS)

Mahoney, A. C.; Colless, J. I.; Pauka, S. J.; Hornibrook, J. M.; Watson, J. D.; Gardner, G. C.; Manfra, M. J.; Doherty, A. C.; Reilly, D. J.

2017-01-01

Circulators are nonreciprocal circuit elements that are integral to technologies including radar systems, microwave communication transceivers, and the readout of quantum information devices. Their nonreciprocity arises from the interference of microwaves over the centimeter scale of the signal wavelength, in the presence of bulky magnetic media that breaks time-reversal symmetry. Here, we realize a completely passive on-chip microwave circulator with size 1 /1000 th the wavelength by exploiting the chiral, "slow-light" response of a two-dimensional electron gas in the quantum Hall regime. For an integrated GaAs device with 330 μ m diameter and about 1-GHz center frequency, a nonreciprocity of 25 dB is observed over a 50-MHz bandwidth. Furthermore, the nonreciprocity can be dynamically tuned by varying the voltage at the port, an aspect that may enable reconfigurable passive routing of microwave signals on chip.

Complex Microfluidic Systems Architectures and Applications to Micropower Generation

DTIC Science & Technology

2010-07-07

signal. Images are recorded via an Hamamatsu Orca camera and processed with Matlab. The observed results show the ability of the micromixer to distribute...Generator was produced. References [1] F. Bottausci, C. Cardonne, C. Meinhart, and I. Mezić. An ultrashort mixing length micromixer : The shear superposition... micromixer . Lab on a Chip, 7(3):396–398, 2007. [2] F. Bottausci, I. Mezić, C.D. Meinhart, and C. Cardonne. Mixing in the shear superposition

Evaluation of the Sensitivity and Signal Response of the DT-702 LiF:Mg,Cu,P TLD

DTIC Science & Technology

2007-06-27

energy stored from the radiation interactions that occurs prior to the TLD being read. Electrons can absorb additional energy from sources other...thermoluminescent dosimetry , annealing is the 24 process used to clear any radiation exposure information from a TLD , preparing it for reuse...702 four-chip TLDs were obtained from the Naval Dosimetry Center (NDC), Bethesda, MD. Each card was tested by Thermo prior to delivery to NDC to

[The design and applications of a non-invasive intelligent detector for cardiovascular functions].

PubMed

Li, Feng; Xing, Wu; Chen, Ming-zhi; Shang, Huai

2006-05-01

An apparatus based on a high sensitive sensor which detects cardiovascular functions is introduced in this paper. Some intelligent detecting technologies, such as syntactic pattern recognition and a medical expert system are used in this detector. Its embedded single-chip microcomputer processes and analyzes pulse signals for gaining automatically the parameters about heart, blood vessel and blood etc., so as to get the health evaluation, correct medical diagnosis and prediction of cardiovascular diseases.

CHIP regulates bone mass by targeting multiple TRAF family members in bone marrow stromal cells.

PubMed

Wang, Tingyu; Li, Shan; Yi, Dan; Zhou, Guang-Qian; Chang, Zhijie; Ma, Peter X; Xiao, Guozhi; Chen, Di

2018-01-01

Carboxyl terminus of Hsp70-interacting protein (CHIP or STUB1) is an E3 ligase and regulates the stability of several proteins which are involved in different cellular functions. Our previous studies demonstrated that Chip deficient mice display bone loss phenotype due to increased osteoclast formation through enhancing TRAF6 activity in osteoclasts. In this study we provide novel evidence about the function of CHIP. We found that osteoblast differentiation and bone formation were also decreased in Chip KO mice. In bone marrow stromal (BMS) cells derived from Chip -/- mice, expression of a panel of osteoblast marker genes was significantly decreased. ALP activity and mineralized bone matrix formation were also reduced in Chip- deficient BMS cells. We also found that in addition to the regulation of TRAF6, CHIP also inhibits TNFα-induced NF-κB signaling through promoting TRAF2 and TRAF5 degradation. Specific deletion of Chip in BMS cells downregulated expression of osteoblast marker genes which could be reversed by the addition of NF-κB inhibitor. These results demonstrate that the osteopenic phenotype observed in Chip -/- mice was due to the combination of increased osteoclast formation and decreased osteoblast differentiation. Taken together, our findings indicate a significant role of CHIP in bone remodeling.

Adjustment of multi-CCD-chip-color-camera heads

NASA Astrophysics Data System (ADS)

Guyenot, Volker; Tittelbach, Guenther; Palme, Martin

1999-09-01

The principle of beam-splitter-multi-chip cameras consists in splitting an image into differential multiple images of different spectral ranges and in distributing these onto separate black and white CCD-sensors. The resulting electrical signals from the chips are recombined to produce a high quality color picture on the monitor. Because this principle guarantees higher resolution and sensitivity in comparison to conventional single-chip camera heads, the greater effort is acceptable. Furthermore, multi-chip cameras obtain the compete spectral information for each individual object point while single-chip system must rely on interpolation. In a joint project, Fraunhofer IOF and STRACON GmbH and in future COBRA electronic GmbH develop methods for designing the optics and dichroitic mirror system of such prism color beam splitter devices. Additionally, techniques and equipment for the alignment and assembly of color beam splitter-multi-CCD-devices on the basis of gluing with UV-curable adhesives have been developed, too.

Three levels of neuroelectronic interfacing: silicon chips with ion channels, nerve cells, and brain tissue.

PubMed

Fromherz, Peter

2006-12-01

We consider the direct electrical interfacing of semiconductor chips with individual nerve cells and brain tissue. At first, the structure of the cell-chip contact is studied. Then we characterize the electrical coupling of ion channels--the electrical elements of nerve cells--with transistors and capacitors in silicon chips. On that basis it is possible to implement signal transmission between microelectronics and the microionics of nerve cells in both directions. Simple hybrid neuroelectronic systems are assembled with neuron pairs and with small neuronal networks. Finally, the interfacing with capacitors and transistors is extended to brain tissue cultured on silicon chips. The application of highly integrated silicon chips allows an imaging of neuronal activity with high spatiotemporal resolution. The goal of the work is an integration of neuronal network dynamics with digital electronics on a microscopic level with respect to experiments in brain research, medical prosthetics, and information technology.

Performance of 20:1 multiplexer for large area charge readouts in directional dark matter TPC detectors

NASA Astrophysics Data System (ADS)

Ezeribe, A. C.; Robinson, M.; Robinson, N.; Scarff, A.; Spooner, N. J. C.; Yuriev, L.

2018-02-01

More target mass is required in current TPC based directional dark matter detectors for improved detector sensitivity. This can be achieved by scaling up the detector volumes, but this results in the need for more analogue signal channels. A possible solution to reducing the overall cost of the charge readout electronics is to multiplex the signal readout channels. Here, we present a multiplexer system in expanded mode based on LMH6574 chips produced by Texas Instruments, originally designed for video processing. The setup has a capability of reducing the number of readouts in such TPC detectors by a factor of 20. Results indicate that the important charge distribution asymmetry along an ionization track is retained after multiplexed signals are demultiplexed.

Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor.

PubMed

Chang, Nai-Fu; Chiang, Cheng-Yi; Chen, Tung-Chien; Chen, Liang-Gee

2011-01-01

On-chip implementation of Hilbert-Huang transform (HHT) has great impact to analyze the non-linear and non-stationary biomedical signals on wearable or implantable sensors for the real-time applications. Cubic spline interpolation (CSI) consumes the most computation in HHT, and is the key component for the HHT processor. In tradition, CSI in HHT is usually performed after the collection of a large window of signals, and the long latency violates the realtime requirement of the applications. In this work, we propose to keep processing the incoming signals on-line with small and overlapped data windows without sacrificing the interpolation accuracy. 58% multiplication and 73% division of CSI are saved after the data reuse between the data windows.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

PubMed

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

PubMed Central

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A.; Wu, Wen-Jung; Lin, Chih-Ting

2014-01-01

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems. PMID:24859027

Optic nerve signals in a neuromorphic chip II: Testing and results.

PubMed

Zaghloul, Kareem A; Boahen, Kwabena

2004-04-01

Seeking to match the brain's computational efficiency, we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 microm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip's subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip's circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

A fast and reliable readout method for quantitative analysis of surface-enhanced Raman scattering nanoprobes on chip surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, Hyejin; Jeong, Sinyoung; Ko, Eunbyeol

2015-05-15

Surface-enhanced Raman scattering techniques have been widely used for bioanalysis due to its high sensitivity and multiplex capacity. However, the point-scanning method using a micro-Raman system, which is the most common method in the literature, has a disadvantage of extremely long measurement time for on-chip immunoassay adopting a large chip area of approximately 1-mm scale and confocal beam point of ca. 1-μm size. Alternative methods such as sampled spot scan with high confocality and large-area scan method with enlarged field of view and low confocality have been utilized in order to minimize the measurement time practically. In this study, wemore » analyzed the two methods in respect of signal-to-noise ratio and sampling-led signal fluctuations to obtain insights into a fast and reliable readout strategy. On this basis, we proposed a methodology for fast and reliable quantitative measurement of the whole chip area. The proposed method adopted a raster scan covering a full area of 100 μm × 100 μm region as a proof-of-concept experiment while accumulating signals in the CCD detector for single spectrum per frame. One single scan with 10 s over 100 μm × 100 μm area yielded much higher sensitivity compared to sampled spot scanning measurements and no signal fluctuations attributed to sampled spot scan. This readout method is able to serve as one of key technologies that will bring quantitative multiplexed detection and analysis into practice.« less

Team of rivals: alliance formation in territorial songbirds is predicted by vocal signal structure

PubMed Central

Goodwin, Sarah E.; Podos, Jeffrey

2014-01-01

Cooperation and conflict are regarded as diametric extremes of animal social behaviour, yet the two may intersect under rare circumstances. We here report that territorial competitors in a common North American songbird species, the chipping sparrow (Spizella passerina), sometimes form temporary coalitions in the presence of simulated territorial intruders. Moreover, analysis of birds’ vocal mating signals (songs) reveals that coalitions occur nearly exclusively under specific triadic relationships, in which vocal performances of allies and simulated intruders exceed those of residents. Our results provide the first evidence that animals like chipping sparrows rely on precise assessments of mating signal features, as well as relative comparisons of signal properties among multiple animals in communication networks, when deciding when and with whom to form temporary alliances against a backdrop of competition and rivalry. PMID:24573153

Team of rivals: alliance formation in territorial songbirds is predicted by vocal signal structure.

PubMed

Goodwin, Sarah E; Podos, Jeffrey

2014-02-01

Cooperation and conflict are regarded as diametric extremes of animal social behaviour, yet the two may intersect under rare circumstances. We here report that territorial competitors in a common North American songbird species, the chipping sparrow (Spizella passerina), sometimes form temporary coalitions in the presence of simulated territorial intruders. Moreover, analysis of birds' vocal mating signals (songs) reveals that coalitions occur nearly exclusively under specific triadic relationships, in which vocal performances of allies and simulated intruders exceed those of residents. Our results provide the first evidence that animals like chipping sparrows rely on precise assessments of mating signal features, as well as relative comparisons of signal properties among multiple animals in communication networks, when deciding when and with whom to form temporary alliances against a backdrop of competition and rivalry.

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.

1992-01-01

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.

Directly amplified redox sensor for on-chip chemical analysis

NASA Astrophysics Data System (ADS)

Takahashi, Sou; Futagawa, Masato; Ishida, Makoto; Sawada, Kazuaki

2014-03-01

In recent years, many groups have studied redox sensors for chemical analysis. A redox sensor has certain powerful advantages, such as its ability to detect multiple ions inside the sensing area, and its ability to measure concentrations of materials by using voltage and current signals. However, the output current signal of a redox sensor decreases when either concentration or sensing area decreases. Therefore, we propose the use of an amplified redox sensor (ARS) for measuring small current signals. The proposed sensor consists of a working electrode combined with a bipolar transistor. In this study, we fabricated an ARS sensor and performed low-concentration measurements using current signal amplification with an integrated bipolar transistor. The sensor chip successfully detected a potassium ferricyanide (K3[Fe(CN)6]) concentration of as low as 10 µM using cyclic voltammetry.

ITO/gold nanoparticle/RGD peptide composites to enhance electrochemical signals and proliferation of human neural stem cells.

PubMed

Kim, Tae-Hyung; El-Said, Waleed Ahmed; An, Jeung Hee; Choi, Jeong-Woo

2013-04-01

A cell chip composed of ITO, gold nanoparticles (GNP) and RGD-MAP-C peptide composites was fabricated to enhance the electrochemical signals and proliferation of undifferentiated human neural stem cells (HB1.F3). The structural characteristics of the fabricated surfaces were confirmed by both scanning electron microscopy and surface-enhanced Raman spectroscopy. HB1.F3 cells were allowed to attach to various composites electrodes in the cell chip and the material-dependent effects on electrochemical signals and cell proliferation were analyzed. The ITO/60 nm GNP/RGD-MAP-C composite electrode was found to be the best material in regards to enhancing the voltammetric signals of HB1.F3 cells when exposed to cyclic voltammetry, as well as for increasing cell proliferation. Differential pulse voltammetry was performed to evaluate the adverse effects of doxorubicin on HB1.F3 cells. In these experiments, negative correlations between cell viability and chemical concentrations were obseved, which were more sensitive than MTT viability assay especially at low concentrations (<0.1 μg/mL). In this basic science study, a cell chip composed of ITO, gold nanoparticles and RGD-MAP-C peptide composites was fabricated to enhance electrochemical signals and proliferation of undifferentiated human neural stem cells (HB1.F3). The ITO/60 nm GNP/RGD-MAP-C composite electrode was found to best enhance the voltammetric signals of the studied cells. Copyright © 2013 Elsevier Inc. All rights reserved.

CMOS Image Sensor with a Built-in Lane Detector.

PubMed

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

Aryl diazonium for biomolecules immobilization onto SPRi chips.

PubMed

Mandon, Céline A; Blum, Loïc J; Marquette, Christophe A

2009-12-21

A method for the immobilization of proteins at the surface of surface plasmon resonance imaging (SPRi) chips is presented. The technology, based on the electro-deposition of a 4-carboxymethyl aryl diazonium (CMA) monolayer is compared to a classical thioctic acid self-assembled monolayer. SPRi live recording experiments followed by the quantification of the diazonium surface coverage demonstrate the presence of a monolayer of electro-deposited molecules (11*10(12) molecules mm(-2)). This monolayer, when activated through a classical carbodiimide route, generates a surface suitable for the protein immobilization. In the present study, protein A and BSA are immobilized as specific and control spots (150 microm id), respectively. The AFM characterization of the spots deposited onto CMA or thioctic acid modified chips prove the presence of 4.7 nm protein monolayers. Finally, the SPRi detection capabilities of the two surface chemistries are compared according to specific signal, non-specific interaction and regeneration possibilities. Advantages are given to the CMA surface modification since no measurable non-specific signal is obtained while reaching a higher specific signal.

Genome-wide Target Enrichment-aided Chip Design: a 66 K SNP Chip for Cashmere Goat.

PubMed

Qiao, Xian; Su, Rui; Wang, Yang; Wang, Ruijun; Yang, Ting; Li, Xiaokai; Chen, Wei; He, Shiyang; Jiang, Yu; Xu, Qiwu; Wan, Wenting; Zhang, Yaolei; Zhang, Wenguang; Chen, Jiang; Liu, Bin; Liu, Xin; Fan, Yixing; Chen, Duoyuan; Jiang, Huaizhi; Fang, Dongming; Liu, Zhihong; Wang, Xiaowen; Zhang, Yanjun; Mao, Danqing; Wang, Zhiying; Di, Ran; Zhao, Qianjun; Zhong, Tao; Yang, Huanming; Wang, Jian; Wang, Wen; Dong, Yang; Chen, Xiaoli; Xu, Xun; Li, Jinquan

2017-08-17

Compared with the commercially available single nucleotide polymorphism (SNP) chip based on the Bead Chip technology, the solution hybrid selection (SHS)-based target enrichment SNP chip is not only design-flexible, but also cost-effective for genotype sequencing. In this study, we propose to design an animal SNP chip using the SHS-based target enrichment strategy for the first time. As an update to the international collaboration on goat research, a 66 K SNP chip for cashmere goat was created from the whole-genome sequencing data of 73 individuals. Verification of this 66 K SNP chip with the whole-genome sequencing data of 436 cashmere goats showed that the SNP call rates was between 95.3% and 99.8%. The average sequencing depth for target SNPs were 40X. The capture regions were shown to be 200 bp that flank target SNPs. This chip was further tested in a genome-wide association analysis of cashmere fineness (fiber diameter). Several top hit loci were found marginally associated with signaling pathways involved in hair growth. These results demonstrate that the 66 K SNP chip is a useful tool in the genomic analyses of cashmere goats. The successful chip design shows that the SHS-based target enrichment strategy could be applied to SNP chip design in other species.

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

NASA Astrophysics Data System (ADS)

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

Chip bonding of low-melting eutectic alloys by transmitted laser radiation

NASA Astrophysics Data System (ADS)

Hoff, Christian; Venkatesh, Arjun; Schneider, Friedrich; Hermsdorf, Jörg; Bengsch, Sebastian; Wurz, Marc C.; Kaierle, Stefan; Overmeyer, Ludger

2017-06-01

Present-day thermode bond systems for the assembly of radio-frequency identification (RFID) chips are mechanically inflexible, difficult to control, and will not meet future manufacturing challenges sufficiently. Chip bonding, one of the key processes in the production of integrated circuits (ICs), has a high potential for optimization with respect to process duration and process flexibility. For this purpose, the technologies used, so far, are supposed to be replaced by a transmission laser-bonding process using low-melting eutectic alloys. In this study, successful bonding investigations of mock silicon chips and of RFID chips on flexible polymer substrates are presented using the low-melting eutectic alloy, 52In48Sn, and a laser with a wavelength of 2 μm.

Switchable in-line monitor for multi-dimensional multiplexed photonic integrated circuit.

PubMed

Chen, Guanyu; Yu, Yu; Ye, Mengyuan; Zhang, Xinliang

2016-06-27

A flexible monitor suitable for the discrimination of on-chip transmitted mode division multiplexed (MDM) and wavelength division multiplexed (WDM) signals is proposed and fabricated. By selectively extracting part of the incoming signals through the tunable wavelength and mode dependent drop filter, the in-line and switchable monitor can discriminate the wavelength, mode and power information of the transmitted signals. Being different from a conventional mode and wavelength demultiplexer, the monitor is specifically designed to ensure a flexible in-line monitoring. For demonstration, three mode and three wavelength multiplexed signals are successfully processed. Assisted by the integrated photodetectors (PDs), both the measured photo currents and eye diagrams validate the performance of the proposed device. The bit error ratio (BER) measurement results show less than 0.4 dB power penalty between different modes and ~2 dB power penalty for single wavelength and WDM cases under 10^-9 BER level.

Detection of underground pipeline based on Golay waveform design

NASA Astrophysics Data System (ADS)

Dai, Jingjing; Xu, Dazhuan

2017-08-01

The detection of underground pipeline is an important problem in the development of the city, but the research about it is not mature at present. In this paper, based on the principle of waveform design in wireless communication, we design an acoustic signal detection system to detect the location of underground pipelines. According to the principle of acoustic localization, we chose DSP-F28335 as the development board, and use DA and AD module as the master control chip. The DA module uses complementary Golay sequence as emission signal. The AD module acquisiting data synchronously, so that the echo signals which containing position information of the target is recovered through the signal processing. The test result shows that the method in this paper can not only calculate the sound velocity of the soil, but also can locate the location of underground pipelines accurately.

Multiple functions of the E3 ubiquitin ligase CHIP in immunity.

PubMed

Zhan, Shaohua; Wang, Tianxiao; Ge, Wei

2017-09-03

The carboxyl terminal of Hsp70-interacting protein (CHIP) is an E3 ubiquitin ligase that plays a pivotal role in the protein quality control system by shifting the balance of the folding-refolding machinery toward the degradative pathway. However, the precise mechanisms by which nonnative proteins are selected for degradation by CHIP either directly or indirectly via chaperone Hsp70 or Hsp90 are still not clear. In this review, we aim to provide a comprehensive model of the mechanism by which CHIP degrades its substrate in a chaperone-dependent or direct manner. In addition, through tight regulation of the protein level of its substrates, CHIP plays important roles in many physiological and pathological conditions, including cancers, neurological disorders, cardiac diseases, bone metabolism, immunity, and so on. Nonetheless, the precise mechanisms underlying the regulation of the immune system by CHIP are still poorly understood despite accumulating developments in our understanding of the regulatory roles of CHIP in both innate and adaptive immune responses. In this review, we also aim to provide a view of CHIP-mediated regulation of immune responses and the signaling pathways involved in the model described. Finally, we discuss the roles of CHIP in immune-related diseases.

Easy detection of multiple Alexandrium species using DNA chromatography chip.

PubMed

Nagai, Satoshi; Miyamoto, Shigehiko; Ino, Keita; Tajimi, Seisuke; Nishi, Hiromi; Tomono, Jun

2016-01-01

In this study, the Kaneka DNA chromatography chip (KDCC) for the Alexandrium species was successfully developed for simultaneous detection of five Alexandrium species. This method utilizes a DNA-DNA hybridization technology. In the PCR process, specifically designed tagged-primers are used, i.e. a forward primer consisting of a tag domain, which can conjugate with gold nanocolloids on the chip, and a primer domain, which can anneal/amplify the target sequence. However, the reverse primer consists of a tag domain, which can hybridize to the solid-phased capture probe on the chip, and a primer domain, which can anneal/amplify the target sequence. As a result, a red line that originates from gold nanocolloids appears as a positive signal on the chip, and the amplicon is detected visually by the naked eye. This technique is simple, because it is possible to visually detect the target species soon after (<5min) the application of 2μL of PCR amplicon and 65μL of development buffer to the sample pad of the chip. Further, this technique is relatively inexpensive and does not require expensive laboratory equipment, such as real-time Q-PCR machines or DNA microarray detectors, but a thermal cycler. Regarding the detection limit of KDCC for the five Alexandrium species, it varied among species and it was <0.1-10pg and equivalent to 5-500 copies of rRNA genes, indicating that the technique is sensitive enough for practical use to detect several cells of the target species from 1L of seawater. The detection sensitivity of KDCC was also evaluated with two different techniques, i.e. a multiplex-PCR and a digital DNA hybridization by digital DNA chip analyzer (DDCA), using natural plankton assemblages. There was no significant difference in the detection sensitivity among the three techniques, suggesting KDCC can be readily used to monitor the HAB species. Copyright © 2015 Elsevier B.V. All rights reserved.

Lab-on-a-chip enabled HLA diagnostic: combined sample preparation and real time PCR for HLA-B57 diagnosis

NASA Astrophysics Data System (ADS)

Gärtner, Claudia; Becker, Holger; Hlawatsch, Nadine; Klemm, Richard; Moche, Christian; Schattschneider, Sebastian; Frank, Rainer; Willems, Andreas

2015-05-01

The diverse human HLA (human leukocyte antigen) system is responsible for antigen presentation and recognition. It is essential for the immune system to maintain a stable defense line, but also is also involved in autoimmunity as well as metabolic disease. HLA-haplotype (HLA-B27), for instance, is associated with inflammatory diseases such as Bechterew's disease. The administration of the HIV drug Abacavir in combination with another HLA-haplotype (HLAB57) is associated with severe hypersensitivity reactions. Accordingly, the HLA status has to be monitored for diagnosis or prior to start of therapy. Along this line, a miniaturized microfluidic platform has been developed allowing performing the complete analytical process from "sample-in" to "answer-out" in a point-of-care environment. The main steps of the analytical cascade inside the integrated system are blood cell lysis and DNA isolation, DNA purification, real-time PCR and quantitative monitoring of the rise of a fluorescent signal appearing during the PCR based sequence amplification. All bio-analytical steps were intended to be performed inside one chip and will be actuated, controlled and monitored by a matching device. This report will show that all required processes are established and tested and all device components work well and interact with the functional modules on the chips in a harmonized fashion.

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Producing Silicon Carbide for Semiconductor Devices

NASA Technical Reports Server (NTRS)

Hsu, G. C.; Rohatgi, N. K.

1986-01-01

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

State of the art in perceptual design of hearing aids

NASA Astrophysics Data System (ADS)

Edwards, Brent W.; van Tasell, Dianne J.

2002-05-01

Hearing aid capabilities have increased dramatically over the past six years, in large part due to the development of small, low-power digital signal processing chips suitable for hearing aid applications. As hearing aid signal processing capabilities increase, there will be new opportunities to apply perceptually based knowledge to technological development. Most hearing loss compensation techniques in today's hearing aids are based on simple estimates of audibility and loudness. As our understanding of the psychoacoustical and physiological characteristics of sensorineural hearing loss improves, the result should be improved design of hearing aids and fitting methods. The state of the art in hearing aids will be reviewed, including form factors, user requirements, and technology that improves speech intelligibility, sound quality, and functionality. General areas of auditory perception that remain unaddressed by current hearing aid technology will be discussed.

Therapeutic hypertension system based on a microbreathing pressure sensor system.

PubMed

Diao, Ziji; Liu, Hongying; Zhu, Lan; Gao, Xiaoqiang; Zhao, Suwen; Pi, Xitian; Zheng, Xiaolin

2011-01-01

A novel therapeutic system for the treatment of hypertension was developed on the basis of a slow-breath training mechanism, using a microbreathing pressure sensor device for the detection of human respiratory signals attached to the abdomen. The system utilizes a single-chip AT89C51 microcomputer as a core processor, programmed by Microsoft Visual C++6.0 to communicate with a PC via a full-speed PDIUSBD12 interface chip. The programming is based on a slow-breath guided algorithm in which the respiratory signal serves as a physiological feedback parameter. Inhalation and exhalation by the subject is guided by music signals. Our study indicates that this microbreathing sensor system may assist in slow-breath training and may help to decrease blood pressure.

Microfluidic CODES: a scalable multiplexed electronic sensor for orthogonal detection of particles in microfluidic channels.

PubMed

Liu, Ruxiu; Wang, Ningquan; Kamili, Farhan; Sarioglu, A Fatih

2016-04-21

Numerous biophysical and biochemical assays rely on spatial manipulation of particles/cells as they are processed on lab-on-a-chip devices. Analysis of spatially distributed particles on these devices typically requires microscopy negating the cost and size advantages of microfluidic assays. In this paper, we introduce a scalable electronic sensor technology, called microfluidic CODES, that utilizes resistive pulse sensing to orthogonally detect particles in multiple microfluidic channels from a single electrical output. Combining the techniques from telecommunications and microfluidics, we route three coplanar electrodes on a glass substrate to create multiple Coulter counters producing distinct orthogonal digital codes when they detect particles. We specifically design a digital code set using the mathematical principles of Code Division Multiple Access (CDMA) telecommunication networks and can decode signals from different microfluidic channels with >90% accuracy through computation even if these signals overlap. As a proof of principle, we use this technology to detect human ovarian cancer cells in four different microfluidic channels fabricated using soft lithography. Microfluidic CODES offers a simple, all-electronic interface that is well suited to create integrated, low-cost lab-on-a-chip devices for cell- or particle-based assays in resource-limited settings.

Accuracy-Energy Configurable Sensor Processor and IoT Device for Long-Term Activity Monitoring in Rare-Event Sensing Applications

PubMed Central

2014-01-01

A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error. PMID:25580458

High-speed highly temperature stable 980 nm VCSELs operating at 25 Gb/s at up to 85 °C for short reach optical interconnects

NASA Astrophysics Data System (ADS)

Mutig, Alex; Lott, James A.; Blokhin, Sergey A.; Moser, Philip; Wolf, Philip; Hofmann, Werner; Nadtochiy, Alexey M.; Bimberg, Dieter

2011-03-01

The progressive penetration of optical communication links into traditional copper interconnect markets greatly expands the applications of vertical cavity surface emitting lasers (VCSELs) for the next-generation of board-to-board, moduleto- module, chip-to-chip, and on-chip optical interconnects. Stability of the VCSEL parameters at high temperatures is indispensable for such applications, since these lasers typically reside directly on or near integrated circuit chips. Here we present 980 nm oxide-confined VCSELs operating error-free at bit rates up to 25 Gbit/s at temperatures as high as 85 °C without adjustment of the drive current and peak-to-peak modulation voltage. The driver design is therefore simplified and the power consumption of the driver electronics is lowered, reducing the production and operational costs. Small and large signal modulation experiments at various temperatures from 20 up to 85 °C for lasers with different oxide aperture diameters are presented in order to analyze the physical processes controlling the performance of the VCSELs. Temperature insensitive maximum -3 dB bandwidths of around 13-15 GHz for VCSELs with aperture diameters of 10 μm and corresponding parasitic cut-off frequencies exceeding 22 GHz are observed. Presented results demonstrate the suitability of our VCSELs for practical high speed and high temperature stable short-reach optical links.

Nanoelectromechanical Chip (NELMEC) Combination of Nanoelectronics and Microfluidics to Diagnose Epithelial and Mesenchymal Circulating Tumor Cells from Leukocytes.

PubMed

Hosseini, Seied Ali; Abdolahad, Mohammad; Zanganeh, Somayeh; Dahmardeh, Mahyar; Gharooni, Milad; Abiri, Hamed; Alikhani, Alireza; Mohajerzadeh, Shams; Mashinchian, Omid

2016-02-17

An integrated nano-electromechanical chip (NELMEC) has been developed for the label-free distinguishing of both epithelial and mesenchymal circulating tumor cells (ECTCs and MCTCs, respectively) from white blood cells (WBCs). This nanoelectronic microfluidic chip fabricated by silicon micromachining can trap large single cells (>12 µm) at the opening of the analysis microchannel arrays. The nature of the captured cells is detected using silicon nanograss (SiNG) electrodes patterned at the entrance of the channels. There is an observable difference between the membrane capacitance of the ECTCs and MCTCs and that of WBCs (measured using SiNG electrodes), which is the key indication for our diagnosis. The NELMEC chip not only solves the problem of the size overlap between CTCs and WBCs but also detects MCTCs without the need for any markers or tagging processes, which has been an important problem in previously reported CTC detection systems. The great conductivity of the gold-coated SiNG nanocontacts as well as their safe penetration into the membrane of captured cells, facilitate a precise and direct signal extraction to distinguish the type of captured cell. The results achieved from epithelial (MCF-7) and mesenchymal (MDA-MB231) breast cancer cells circulated in unprocessed blood suggest the significant applications for these diagnostic abilities of NELMEC. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A pixelated x-ray detector for diffraction imaging at next-generation high-rate FEL sources

NASA Astrophysics Data System (ADS)

Lodola, L.; Ratti, L.; Comotti, D.; Fabris, L.; Grassi, M.; Malcovati, P.; Manghisoni, M.; Re, V.; Traversi, G.; Vacchi, C.; Batignani, G.; Bettarini, S.; Forti, F.; Casarosa, G.; Morsani, F.; Paladino, A.; Paoloni, E.; Rizzo, G.; Benkechkache, M. A.; Dalla Betta, G.-F.; Mendicino, R.; Pancheri, L.; Verzellesi, G.; Xu, H.

2017-08-01

The PixFEL collaboration has developed the building blocks for an X-ray imager to be used in applications at FELs. In particular, slim edge pixel detectors with high detection efficiency over a broad energy range, from 1 to 12 keV, have been developed. Moreover, a multichannel readout chip, called PFM2 (PixFEL front-end Matrix 2) and consisting of 32 × 32 cells, has been designed and fabricated in a 65 nm CMOS technology. The pixel pitch is 110 μm, the overall area is around 16 mm2. In the chip, different solutions have been implemented for the readout channel, which includes a charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper and an A-to-D converter with a 10 bit resolution. The CSA can be configured in four different gain modes, so as to comply with photon energies in the 1 to 10 keV range. The paper will describe in detail the channel architecture and present the results from the characterization of PFM2. It will discuss the design of a new version of the chip, called PFM3, suitable for post-processing with peripheral, under-pad through silicon vias (TSVs), which are needed to develop four-side buttable chips and cover large surfaces with minimum inactive area.

Simplifying the circuit of Josephson parametric converters

NASA Astrophysics Data System (ADS)

Abdo, Baleegh; Brink, Markus; Chavez-Garcia, Jose; Keefe, George

Josephson parametric converters (JPCs) are quantum-limited three-wave mixing devices that can play various important roles in quantum information processing in the microwave domain, including amplification of quantum signals, transduction of quantum information, remote entanglement of qubits, nonreciprocal amplification, and circulation of signals. However, the input-output and biasing circuit of a state-of-the-art JPC consists of bulky components, i.e. two commercial off-chip broadband 180-degree hybrids, four phase-matched short coax cables, and one superconducting magnetic coil. Such bulky hardware significantly hinders the integration of JPCs in scalable quantum computing architectures. In my talk, I will present ideas on how to simplify the JPC circuit and show preliminary experimental results

A wideband software reconfigurable modem

NASA Astrophysics Data System (ADS)

Turner, J. H., Jr.; Vickers, H.

A wideband modem is described which provides signal processing capability for four Lx-band signals employing QPSK, MSK and PPM waveforms and employs a software reconfigurable architecture for maximum system flexibility and graceful degradation. The current processor uses a 2901 and two 8086 microprocessors per channel and performs acquisition, tracking, and data demodulation for JITDS, GPS, IFF and TACAN systems. The next generation processor will be implemented using a VHSIC chip set employing a programmable complex array vector processor module, a GP computer module, customized gate array modules, and a digital array correlator. This integrated processor has application to a wide number of diverse system waveforms, and will bring the benefits of VHSIC technology insertion into avionic antijam communications systems.

Detection of solder bump defects on a flip chip using vibration analysis

NASA Astrophysics Data System (ADS)

Liu, Junchao; Shi, Tielin; Xia, Qi; Liao, Guanglan

2012-03-01

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

Chip-LC-MS for label-free profiling of human serum.

PubMed

Horvatovich, Peter; Govorukhina, Natalia I; Reijmers, Theo H; van der Zee, Ate G J; Suits, Frank; Bischoff, Rainer

2007-12-01

The discovery of biomarkers in easily accessible body fluids such as serum is one of the most challenging topics in proteomics requiring highly efficient separation and detection methodologies. Here, we present the application of a microfluidics-based LC-MS system (chip-LC-MS) to the label-free profiling of immunodepleted, trypsin-digested serum in comparison to conventional capillary LC-MS (cap-LC-MS). Both systems proved to have a repeatability of approximately 20% RSD for peak area, all sample preparation steps included, while repeatability of the LC-MS part by itself was less than 10% RSD for the chip-LC-MS system. Importantly, the chip-LC-MS system had a two times higher resolution in the LC dimension and resulted in a lower average charge state of the tryptic peptide ions generated in the ESI interface when compared to cap-LC-MS while requiring approximately 30 times less (~5 pmol) sample. In order to characterize both systems for their capability to find discriminating peptides in trypsin-digested serum samples, five out of ten individually prepared, identical sera were spiked with horse heart cytochrome c. A comprehensive data processing methodology was applied including 2-D smoothing, resolution reduction, peak picking, time alignment, and matching of the individual peak lists to create an aligned peak matrix amenable for statistical analysis. Statistical analysis by supervised classification and variable selection showed that both LC-MS systems could discriminate the two sample groups. However, the chip-LC-MS system allowed to assign 55% of the overall signal to selected peaks against 32% for the cap-LC-MS system.

System for particle concentration and detection

DOEpatents

Morales, Alfredo M.; Whaley, Josh A.; Zimmerman, Mark D.; Renzi, Ronald F.; Tran, Huu M.; Maurer, Scott M.; Munslow, William D.

2013-03-19

A new microfluidic system comprising an automated prototype insulator-based dielectrophoresis (iDEP) triggering microfluidic device for pathogen monitoring that can eventually be run outside the laboratory in a real world environment has been used to demonstrate the feasibility of automated trapping and detection of particles. The system broadly comprised an aerosol collector for collecting air-borne particles, an iDEP chip within which to temporarily trap the collected particles and a laser and fluorescence detector with which to induce a fluorescence signal and detect a change in that signal as particles are trapped within the iDEP chip.

Monolithic integration of a silica AWG and Ge photodiodes on Si photonic platform for one-chip WDM receiver.

PubMed

Nishi, Hidetaka; Tsuchizawa, Tai; Kou, Rai; Shinojima, Hiroyuki; Yamada, Takashi; Kimura, Hideaki; Ishikawa, Yasuhiko; Wada, Kazumi; Yamada, Koji

2012-04-09

On the silicon (Si) photonic platform, we monolithically integrated a silica-based arrayed-waveguide grating (AWG) and germanium (Ge) photodiodes (PDs) using low-temperature fabrication technology. We confirmed demultiplexing by the AWG, optical-electrical signal conversion by Ge PDs, and high-speed signal detection at all channels. In addition, we mounted a multichannel transimpedance amplifier/limiting amplifier (TIA/LA) circuit on the fabricated AWG-PD device using flip-chip bonding technology. The results show the promising potential of our Si photonic platform as a photonics-electronics convergence.

Experimental single-chip color HDTV image acquisition system with 8M-pixel CMOS image sensor

NASA Astrophysics Data System (ADS)

Shimamoto, Hiroshi; Yamashita, Takayuki; Funatsu, Ryohei; Mitani, Kohji; Nojiri, Yuji

2006-02-01

We have developed an experimental single-chip color HDTV image acquisition system using 8M-pixel CMOS image sensor. The sensor has 3840 × 2160 effective pixels and is progressively scanned at 60 frames per second. We describe the color filter array and interpolation method to improve image quality with a high-pixel-count single-chip sensor. We also describe an experimental image acquisition system we used to measured spatial frequency characteristics in the horizontal direction. The results indicate good prospects for achieving a high quality single chip HDTV camera that reduces pseudo signals and maintains high spatial frequency characteristics within the frequency band for HDTV.

A Spiking Strategy for ChIP-chip Data Normalization in S. cerevisiae.

PubMed

Jeronimo, Célia; Robert, François

2017-01-01

Chromatin immunoprecipitation coupled to DNA microarrays (ChIP-chip) is widely used in the chromatin field, notably to map the position of histone variants or histone modifications along the genome. Often, the position and the occupancy of these epigenetic marks are to be compared between different experiments. It is now increasingly recognized that such cross-sample comparison is better done using externally added exogenous controls for normalization but no such method has been described for ChIP-chip. Here we describe a spiking normalization strategy that makes use of phiX174 phage DNA as a spiked control for normalization of ChIP-chip signals across different experiments.

Quad-Chip Double-Balanced Frequency Tripler

NASA Technical Reports Server (NTRS)

Lin, Robert H.; Ward, John S.; Bruneau, Peter J.; Mehdi, Imran; Thomas, Bertrand C.; Maestrini, Alain

2010-01-01

Solid-state frequency multipliers are used to produce tunable broadband sources at millimeter and submillimeter wavelengths. The maximum power produced by a single chip is limited by the electrical breakdown of the semiconductor and by the thermal management properties of the chip. The solution is to split the drive power to a frequency tripler using waveguides to divide the power among four chips, then recombine the output power from the four chips back into a single waveguide. To achieve this, a waveguide branchline quadrature hybrid coupler splits a 100-GHz input signal into two paths with a 90 relative phase shift. These two paths are split again by a pair of waveguide Y-junctions. The signals from the four outputs of the Y-junctions are tripled in frequency using balanced Schottky diode frequency triplers before being recombined with another pair of Y-junctions. A final waveguide branchline quadrature hybrid coupler completes the combination. Using four chips instead of one enables using four-times higher power input, and produces a nearly four-fold power output as compared to using a single chip. The phase shifts introduced by the quadrature hybrid couplers provide isolation for the input and output waveguides, effectively eliminating standing waves between it and surrounding components. This is accomplished without introducing the high losses and expense of ferrite isolators. A practical use of this technology is to drive local oscillators as was demonstrated around 300 GHz for a heterodyne spectrometer operating in the 2-3-THz band. Heterodyne spectroscopy in this frequency band is especially valuable for astrophysics due to the presence of a very large number of molecular spectral lines. Besides high-resolution radar and spectrographic screening applications, this technology could also be useful for laboratory spectroscopy.

MOBE-ChIP: Probing Cell Type-Specific Binding Through Large-Scale Chromatin Immunoprecipitation.

PubMed

Wang, Shenqi; Lau, On Sun

2018-01-01

In multicellular organisms, the initiation and maintenance of specific cell types often require the activity of cell type-specific transcriptional regulators. Understanding their roles in gene regulation is crucial but probing their DNA targets in vivo, especially in a genome-wide manner, remains a technical challenge with their limited expression. To improve the sensitivity of chromatin immunoprecipitation (ChIP) for detecting the cell type-specific signals, we have developed the Maximized Objects for Better Enrichment (MOBE)-ChIP, where ChIP is performed at a substantially larger experimental scale and under low background conditions. Here, we describe the procedure in the study of transcription factors in the model plant Arabidopsis. However, with some modifications, the technique should also be implemented in other systems. Besides cell type-specific studies, MOBE-ChIP can also be used as a general strategy to improve ChIP signals.

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

Commercial Product Activation Using RFID

NASA Technical Reports Server (NTRS)

Jedrey, Thomas

2008-01-01

Radio-frequency identification (RFID) would be used for commercial product activation, according to a proposal. What is new here is the concept of combining RFID with activation - more specifically, using RFID for activating commercial products (principally, electronic ones) and for performing such ancillary functions as tracking individual product units on production lines, tracking shipments, and updating inventories. According to the proposal, an RFID chip would be embedded in each product. The information encoded in the chip would include a unique number for identifying the product. An RFID reader at the point of sale would record the number of the product and would write digital information to the RFID chip for either immediate activation of the product or for later interrogation and processing. To be practical, an RFID product-activation system should satisfy a number of key requirements: the system should be designed to be integrable into the inventory-tracking and the data-processing and -communication infrastructures of businesses along the entire supply chain from manufacture to retail; the system should be resistant to sophisticated hacking; activation codes should be made sufficiently complexity to minimize the probability of activating stolen products; RFID activation equipment at points of sale must be capable to two-way RF communication for the purposes of reading information from, and writing information to, embedded RFID chips; the equipment at points of sale should be easily operable by sales clerks with little or no training; the point-of-sale equipment should verify activation and provide visible and/or audible signals indicating verification or lack thereof; and, the system should be able to handle millions of products per year with minimal human intervention, among other requirements.

Development and Testing of an Ultra Low Power System-On-Chip (SOC) Platform for Marine Mammal Tags and Passive Acoustic Signal Processing

DTIC Science & Technology

2014-09-30

current (3-5mA). The system can harvest 16 power from a DC input source like a thermoelectric generator (TEG) or photovoltaic cell (PV). The boost...results from components to report. Designed for thermoelectric energy harvesting in 130nm CMOS, the boost converter reduces the achievable input...harvesting. The boost converter further incorporates maximum power point tracking for harvesting from both thermoelectric generators (TEGs) and solar

High-accurate optical fiber liquid level sensor

NASA Astrophysics Data System (ADS)

Sun, Dexing; Chen, Shouliu; Pan, Chao; Jin, Henghuan

1991-08-01

A highly accurate optical fiber liquid level sensor is presented. The single-chip microcomputer is used to process and control the signal. This kind of sensor is characterized by self-security and is explosion-proof, so it can be applied in any liquid level detecting areas, especially in the oil and chemical industries. The theories and experiments about how to improve the measurement accuracy are described. The relative error for detecting the measurement range 10 m is up to 0.01%.

[Development of automatic urine monitoring system].

PubMed

Wei, Liang; Li, Yongqin; Chen, Bihua

2014-03-01

An automatic urine monitoring system is presented to replace manual operation. The system is composed of the flow sensor, MSP430f149 single chip microcomputer, human-computer interaction module, LCD module, clock module and memory module. The signal of urine volume is captured when the urine flows through the flow sensor and then displayed on the LCD after data processing. The experiment results suggest that the design of the monitor provides a high stability, accurate measurement and good real-time, and meets the demand of the clinical application.

Real Time Detecting and Processing Signals by an Integrated Sensor Chip Based on Meta-materials and Photonic Crystals

DTIC Science & Technology

2012-05-29

the ring. At first, the resonating behavior of a typical SRR is noted by the red curve in Figure 13. Following that, with the omission of the inner...resonant frequency. Finally, in the third case, the resonance was eliminated altogether as shown in Figure 13 with the green curve . The ’short’ of the... Micromirror Devices (DMD) and phased array antenna design by controlling each element of the array or pixel electronically. 4.2.1 Numerical

Smart Phase Tuning in Microwave Photonic Integrated Circuits Toward Automated Frequency Multiplication by Design

NASA Astrophysics Data System (ADS)

Nabavi, N.

2018-07-01

The author investigates the monitoring methods for fine adjustment of the previously proposed on-chip architecture for frequency multiplication and translation of harmonics by design. Digital signal processing (DSP) algorithms are utilized to create an optimized microwave photonic integrated circuit functionality toward automated frequency multiplication. The implemented DSP algorithms are formed on discrete Fourier transform and optimization-based algorithms (Greedy and gradient-based algorithms), which are analytically derived and numerically compared based on the accuracy and speed of convergence criteria.

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Design and validation of a real-time spiking-neural-network decoder for brain-machine interfaces

NASA Astrophysics Data System (ADS)

Dethier, Julie; Nuyujukian, Paul; Ryu, Stephen I.; Shenoy, Krishna V.; Boahen, Kwabena

2013-06-01

Objective. Cortically-controlled motor prostheses aim to restore functions lost to neurological disease and injury. Several proof of concept demonstrations have shown encouraging results, but barriers to clinical translation still remain. In particular, intracortical prostheses must satisfy stringent power dissipation constraints so as not to damage cortex. Approach. One possible solution is to use ultra-low power neuromorphic chips to decode neural signals for these intracortical implants. The first step is to explore in simulation the feasibility of translating decoding algorithms for brain-machine interface (BMI) applications into spiking neural networks (SNNs). Main results. Here we demonstrate the validity of the approach by implementing an existing Kalman-filter-based decoder in a simulated SNN using the Neural Engineering Framework (NEF), a general method for mapping control algorithms onto SNNs. To measure this system’s robustness and generalization, we tested it online in closed-loop BMI experiments with two rhesus monkeys. Across both monkeys, a Kalman filter implemented using a 2000-neuron SNN has comparable performance to that of a Kalman filter implemented using standard floating point techniques. Significance. These results demonstrate the tractability of SNN implementations of statistical signal processing algorithms on different monkeys and for several tasks, suggesting that a SNN decoder, implemented on a neuromorphic chip, may be a feasible computational platform for low-power fully-implanted prostheses. The validation of this closed-loop decoder system and the demonstration of its robustness and generalization hold promise for SNN implementations on an ultra-low power neuromorphic chip using the NEF.

Novel electrochemical nickel metallization in silicon impedance engineering for mixed-signal system-on-chip crosstalk isolation

NASA Astrophysics Data System (ADS)

Zhang, Xi

One of the major challenges for single chip radio frequency integrated circuits (RFIC's) built on Si is the RE crosstalk through the Si substrate. Noise from switching transient in digital circuits can be transmitted through Si substrate and degrades the performance of analog circuit elements. A highly conductive moat or Faraday cage type structure of through-the-wafer thickness in the Si substrate was demonstrated to be effective in shielding electromagnetic interference thereby reducing RE cross-talk in high performance mixed signal integrated circuits. Such a structure incorporated into the p- Si substrate was realized by electroless Ni metallization over selected regions with ultra-high-aspect-ratio macropores that was etched electrochemically in p- Si substrates. The metallization process was conducted by immersing the macroporous Si sample in an alkaline aqueous solution containing Ni2+ without a reducing agent. It was found that working at slightly elevated temperature, Ni 2+ was rapidly reduced and deposited in the macropores. During the wet chemical process, conformal metallization on the pore wall was achieved. The entire porous Si skeleton was gradually replaced by Ni along the extended duration of immersion. In a p-/p+ epi Si substrate used for high performance digital CMOS, the suppression of crosstalk by the arrayed metallic Ni via structure fabricated from the front p side was significant that the crosstalk went down to the noise floor of the conventional measurement instruments. The process and mechanism of forming such a Ni structure over the original Si were studied. Theoretical computation relevant to the process was carried out to show a good consistency with the experiments.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

Multiple plasmonically induced transparency for chip-scale bandpass filters in metallic nanowaveguides

NASA Astrophysics Data System (ADS)

Lu, Hua; Yue, Zengqi; Zhao, Jianlin

2018-05-01

We propose and investigate a new kind of bandpass filters based on the plasmonically induced transparency (PIT) effect in a special metal-insulator-metal (MIM) waveguide system. The finite element method (FEM) simulations illustrate that the obvious PIT response can be generated in the metallic nanostructure with the stub and coupled cavities. The lineshape and position of the PIT peak are particularly dependent on the lengths of the stub and coupled cavities, the waveguide width, as well as the coupling distance between the stub and coupled cavities. The numerical simulations are in accordance with the results obtained by the temporal coupled-mode theory. The multi-peak PIT effect can be achieved by integrating multiple coupled cavities into the plasmonic waveguide. This PIT response contributes to the flexible realization of chip-scale multi-channel bandpass filters, which could find crucial applications in highly integrated optical circuits for signal processing.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring

NASA Astrophysics Data System (ADS)

Iwato, Hirofumi; Sakanushi, Keishi; Takeuchi, Yoshinori; Imai, Masaharu

To measure the detrusor pressure for diagnosing lower urinary tract symptoms, we designed a small-area and low-power System on a Chip (SoC). The SoC should be small and low power because it is encapsulated in tiny air-tight capsules which are simultaneously inserted in the urinary bladder and rectum for several days. Since the SoC is also required to be programmable, we designed an Application Specific Instruction set Processor (ASIP) for pressure measurement and wireless communication, and implemented almost required functions on the ASIP. The SoC was fabricated using a 0.18µm CMOS mixed-signal process and the chip size is 2.5×2.5mm2. Evaluation results show that the power consumption of the SoC is 93.5µW, and that it can operate the capsule for seven days with a tiny battery.

Air Force highly integrated photonics program: development and demonstration of an optically transparent fiber optic network for avionics applications

NASA Astrophysics Data System (ADS)

Whaley, Gregory J.; Karnopp, Roger J.

2010-04-01

The goal of the Air Force Highly Integrated Photonics (HIP) program is to develop and demonstrate single photonic chip components which support a single mode fiber network architecture for use on mobile military platforms. We propose an optically transparent, broadcast and select fiber optic network as the next generation interconnect on avionics platforms. In support of this network, we have developed three principal, single-chip photonic components: a tunable laser transmitter, a 32x32 port star coupler, and a 32 port multi-channel receiver which are all compatible with demanding avionics environmental and size requirements. The performance of the developed components will be presented as well as the results of a demonstration system which integrates the components into a functional network representative of the form factor used in advanced avionics computing and signal processing applications.

Subwavelength grating enabled on-chip ultra-compact optical true time delay line

PubMed Central

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R.

2016-01-01

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth. PMID:27457024

Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

NASA Astrophysics Data System (ADS)

Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

2017-07-01

Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

MEAs and 3D nanoelectrodes: electrodeposition as tool for a precisely controlled nanofabrication.

PubMed

Weidlich, Sabrina; Krause, Kay J; Schnitker, Jan; Wolfrum, Bernhard; Offenhäusser, Andreas

2017-01-31

Microelectrode arrays (MEAs) are gaining increasing importance for the investigation of signaling processes between electrogenic cells. However, efficient cell-chip coupling for robust and long-term electrophysiological recording and stimulation still remains a challenge. A possible approach for the improvement of the cell-electrode contact is the utilization of three-dimensional structures. In recent years, various 3D electrode geometries have been developed, but we are still lacking a fabrication approach that enables the formation of different 3D structures on a single chip in a controlled manner. This, however, is needed to enable a direct and reliable comparison of the recording capabilities of the different structures. Here, we present a method for a precisely controlled deposition of nanoelectrodes, enabling the fabrication of multiple, well-defined types of structures on our 64 electrode MEAs towards a rapid-prototyping approach to 3D electrodes.

Subwavelength grating enabled on-chip ultra-compact optical true time delay line.

PubMed

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R

2016-07-26

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth.

[Lab-on-a-chip systems in the point-of-care diagnostics].

PubMed

Szabó, Barnabás; Borbíró, András; Fürjes, Péter

2015-12-27

The need in modern medicine for near-patient diagnostics being able to accelerate therapeutic decisions and possibly replacing laboratory measurements is significantly growing. Reliable and cost-effective bioanalytical measurement systems are required which - acting as a micro-laboratory - contain integrated biomolecular recognition, sensing, signal processing and complex microfluidic sample preparation modules. These micro- and nanofabricated Lab-on-a-chip systems open new perspectives in the diagnostic supply chain, since they are able even for quantitative, high-precision and immediate analysis of special disease specific molecular markers or their combinations from a single drop of sample. Accordingly, crucial requirements regarding the instruments and the analytical methods are the high selectivity, extremely low detection limit, short response time and integrability into the healthcare information networks. All these features can make the hierarchical examination chain shorten, and revolutionize laboratory diagnostics, evolving a brand new situation in therapeutic intervention.

SFERA: An Integrated Circuit for the Readout of X and gamma -Ray Detectors

NASA Astrophysics Data System (ADS)

Schembari, Filippo; Quaglia, Riccardo; Bellotti, Giovanni; Fiorini, Carlo

2016-06-01

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both Xand y-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely 2800 e-, 4400 e-, 10000 e-, 14000 e- and 20000 e-, considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times (tP) are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X, intended for high-rate X-ray applications, the polling y, for scintillation light detection and the sparse, for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-Ku line of an 55Fe X-ray source using a 10 mm2 SDD cooled at -35 °C at 4 μs filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS 0.35 μm CMOS and the chip area occupancy is 5 × 5 mm2.

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

Simultaneous wavelength conversion of ASK and DPSK signals based on four-wave-mixing in dispersion engineered silicon waveguides.

PubMed

Xu, Lin; Ophir, Noam; Menard, Michael; Lau, Ryan Kin Wah; Turner-Foster, Amy C; Foster, Mark A; Lipson, Michal; Gaeta, Alexander L; Bergman, Keren

2011-06-20

We experimentally demonstrate four-wave-mixing (FWM)-based continuous wavelength conversion of optical differential-phase-shift-keyed (DPSK) signals with large wavelength conversion ranges as well as simultaneous wavelength conversion of dual-wavelength channels with mixed modulation formats in 1.1-cm-long dispersion-engineered silicon waveguides. We first validate up to 100-nm wavelength conversion range for 10-Gb/s DPSK signals, showcasing the capability to perform phase-preserving operations at high bit rates in chip-scale devices over wide conversion ranges. We further validate the wavelength conversion of dual-wavelength channels modulated with 10-Gb/s packetized phase-shift-keyed (PSK) and amplitude-shift-keyed (ASK) signals; demonstrate simultaneous operation on multiple channels with mixed formats in chip-scale devices. For both configurations, we measure the spectral and temporal responses and evaluate the performances using bit-error-rate (BER) measurements.

Superconducting Switch for Fast On-Chip Routing of Quantum Microwave Fields

NASA Astrophysics Data System (ADS)

Pechal, M.; Besse, J.-C.; Mondal, M.; Oppliger, M.; Gasparinetti, S.; Wallraff, A.

2016-08-01

A switch capable of routing microwave signals at cryogenic temperatures is a desirable component for state-of-the-art experiments in many fields of applied physics, including but not limited to quantum-information processing, communication, and basic research in engineered quantum systems. Conventional mechanical switches provide low insertion loss but disturb operation of dilution cryostats and the associated experiments by heat dissipation. Switches based on semiconductors or microelectromechanical systems have a lower thermal budget but are not readily integrated with current superconducting circuits. Here we design and test an on-chip switch built by combining tunable transmission-line resonators with microwave beam splitters. The device is superconducting and as such dissipates a negligible amount of heat. It is compatible with current superconducting circuit fabrication techniques, operates with a bandwidth exceeding 100 MHz, is capable of handling photon fluxes on the order of 1 05 μ s-1 , equivalent to powers exceeding -90 dBm , and can be switched within approximately 6-8 ns. We successfully demonstrate operation of the device in the quantum regime by integrating it on a chip with a single-photon source and using it to route nonclassical itinerant microwave fields at the single-photon level.

Fermented non-digestible fraction from combined nixtamalized corn (Zea mays L.)/cooked common bean (Phaseolus vulgaris L.) chips modulate anti-inflammatory markers on RAW 264.7 macrophages.

PubMed

Luzardo-Ocampo, I; Campos-Vega, R; Cuellar-Nuñez, M L; Vázquez-Landaverde, P A; Mojica, L; Acosta-Gallegos, J A; Loarca-Piña, G

2018-09-01

Chronic non-communicable diseases (NCDs) are low-level inflammation processes affected by several factors including diet. It has been reported that mixed whole grain and legume consumption, e.g. corn and common bean, might be a beneficial combination due to its content of bioactive compounds. A considerable amount would be retained in the non-digestible fraction (NDF), reaching the colon, where microbiota produce short-chain fatty acids (SCFAs) and phenolic compounds (PC) with known anti-inflammatory effect. The aim of this study was to estimate the anti-inflammatory potential of fermented-NDF of corn-bean chips (FNDFC) in RAW 264.7 macrophages. After 24 h, FNDFC produced SCFAs (0.156-0.222 mmol/l), inhibited nitric oxide production > 80% and H 2 O 2  > 30%, up-regulated anti-inflammatory cytokines (I-TAC, TIMP-1) > 2-fold, and produced angiostatic and protective factors against vascular/tissue damage, and amelioration of tumor necrosis factor signalling and inflammatory bowel disease. These results confirm the anti-inflammatory potential derived from healthy corn-bean chips. Copyright © 2018. Published by Elsevier Ltd.

A world-to-chip socket for microfluidic prototype development.

PubMed

Yang, Zhen; Maeda, Ryutaro

2002-10-01

We report a prototype for a standard connector between a microfluidic chip and the macroworld. This prototype is the first to demonstrate a fully functioning socket for a microchip to access the outside world by means of fluids, data, and energy supply, as well as providing process visibility. It has 20 channels for the input and output of liquids or gases, as well as compressed air or vacuum lines for pneumatic power lines. It also contains 42 pins for electrical signals and power. All these connections were designed in a planar configuration with linear orthogonal arrays. The vertical space was opened for optical measurement and evaluation. The die (29.1 mm x 27.5 mm x 0.9 mm) can be easily mounted and dismounted from the socket. No adhesives or solders are used at any contact points. The pressure limit for the connection of working fluids was 0.2 MPa and the current limit for the electrical connections was 1 A. This socket supports both serial and parallel processing applications. It exhibits great potential for developing microfluidic systems efficiently.

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

PubMed

Cho, Hwasuk; Son, Hyunwoo; Seong, Kihwan; Kim, Byungsub; Park, Hong-June; Sim, Jae-Yoon

2018-02-01

This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine. The IC is fabricated using 28-nm CMOS process and is verified in a three-layer network of encoder-decoder pair for training and recovery of images with two-dimensional pixels. With a dataset of 50 digits, the IC shows a normalized root mean square error of 0.078. Measured energy efficiencies are 4.46 pJ per synaptic operation for inference and 19.26 pJ per synaptic weight update for learning, respectively. The learning performance is also estimated by simulations if the proposed hardware architecture is extended to apply to a batch training of 60 000 MNIST datasets.

Systems-on-chip approach for real-time simulation of wheel-rail contact laws

NASA Astrophysics Data System (ADS)

Mei, T. X.; Zhou, Y. J.

2013-04-01

This paper presents the development of a systems-on-chip approach to speed up the simulation of wheel-rail contact laws, which can be used to reduce the requirement for high-performance computers and enable simulation in real time for the use of hardware-in-loop for experimental studies of the latest vehicle dynamic and control technologies. The wheel-rail contact laws are implemented using a field programmable gate array (FPGA) device with a design that substantially outperforms modern general-purpose PC platforms or fixed architecture digital signal processor devices in terms of processing time, configuration flexibility and cost. In order to utilise the FPGA's parallel-processing capability, the operations in the contact laws algorithms are arranged in a parallel manner and multi-contact patches are tackled simultaneously in the design. The interface between the FPGA device and the host PC is achieved by using a high-throughput and low-latency Ethernet link. The development is based on FASTSIM algorithms, although the design can be adapted and expanded for even more computationally demanding tasks.

A System-on-Chip Solution for Point-of-Care Ultrasound Imaging Systems: Architecture and ASIC Implementation.

PubMed

Kang, Jeeun; Yoon, Changhan; Lee, Jaejin; Kye, Sang-Bum; Lee, Yongbae; Chang, Jin Ho; Kim, Gi-Duck; Yoo, Yangmo; Song, Tai-kyong

2016-04-01

In this paper, we present a novel system-on-chip (SOC) solution for a portable ultrasound imaging system (PUS) for point-of-care applications. The PUS-SOC includes all of the signal processing modules (i.e., the transmit and dynamic receive beamformer modules, mid- and back-end processors, and color Doppler processors) as well as an efficient architecture for hardware-based imaging methods (e.g., dynamic delay calculation, multi-beamforming, and coded excitation and compression). The PUS-SOC was fabricated using a UMC 130-nm NAND process and has 16.8 GFLOPS of computing power with a total equivalent gate count of 12.1 million, which is comparable to a Pentium-4 CPU. The size and power consumption of the PUS-SOC are 27×27 mm(2) and 1.2 W, respectively. Based on the PUS-SOC, a prototype hand-held US imaging system was implemented. Phantom experiments demonstrated that the PUS-SOC can provide appropriate image quality for point-of-care applications with a compact PDA size ( 200×120×45 mm(3)) and 3 hours of battery life.

Universal method for crosstalk noise and transmission loss analysis for N-port nonblocking optical router for photonic networks-on-chip

NASA Astrophysics Data System (ADS)

Xie, Yiyuan; Zhang, Zhendong; Song, Tingting; He, Chao; Li, Jiachao; Wang, Guijin

2016-05-01

Crosstalk noise and transmission loss are two key elements in determining the performance of optical routers. We propose a universal method for crosstalk noise and transmission loss analysis for the N-port nonblocking optical router used in photonic networks-on-chip. Utilizing this method, we study the crosstalk noise and transmission loss for the five-, six-, seven-, and eight-port optical routers. We ascertain that the crosstalk noise and transmission loss are different for different input-output pairs. For the five-port optical router, the maximum crosstalk noise ranges from 0 to -7.07 dBm, and the transmission loss ranges from -9.05 to -0.51 dB. Furthermore, based on the crosstalk noise and transmission loss, we analyze optical signal-to-noise ratio (OSNR) and bit error ratio (BER) for the five-, six-, seven-, and eight-port nonblocking optical routers. As the number of ports increases, the minimum average OSNR decreases and the average BER increases. In addition, in order to present the performance of the routers more visually, a fiber-optic communications system is designed to simulate the transmission processes of the signals of the different paths of the routers in Optisystem. The results show that the power amplitude of the input signal is obviously higher than the corresponding output signal. With this method, we can easily evaluate the transmission loss, crosstalk noise, OSNR, and BER of high-radix nonblocking optical routers and conveniently study the performance of the N-port optical router.

P-code enhanced method for processing encrypted GPS signals without knowledge of the encryption code

NASA Technical Reports Server (NTRS)

Young, Lawrence E. (Inventor); Meehan, Thomas K. (Inventor); Thomas, Jr., Jess Brooks (Inventor)

2000-01-01

In the preferred embodiment, an encrypted GPS signal is down-converted from RF to baseband to generate two quadrature components for each RF signal (L1 and L2). Separately and independently for each RF signal and each quadrature component, the four down-converted signals are counter-rotated with a respective model phase, correlated with a respective model P code, and then successively summed and dumped over presum intervals substantially coincident with chips of the respective encryption code. Without knowledge of the encryption-code signs, the effect of encryption-code sign flips is then substantially reduced by selected combinations of the resulting presums between associated quadrature components for each RF signal, separately and independently for the L1 and L2 signals. The resulting combined presums are then summed and dumped over longer intervals and further processed to extract amplitude, phase and delay for each RF signal. Precision of the resulting phase and delay values is approximately four times better than that obtained from straight cross-correlation of L1 and L2. This improved method provides the following options: separate and independent tracking of the L1-Y and L2-Y channels; separate and independent measurement of amplitude, phase and delay L1-Y channel; and removal of the half-cycle ambiguity in L1-Y and L2-Y carrier phase.

Protein–Protein Interactions Modulate the Docking-Dependent E3-Ubiquitin Ligase Activity of Carboxy-Terminus of Hsc70-Interacting Protein (CHIP)*

PubMed Central

Narayan, Vikram; Landré, Vivien; Ning, Jia; Hernychova, Lenka; Muller, Petr; Verma, Chandra; Walkinshaw, Malcolm D.; Blackburn, Elizabeth A.; Ball, Kathryn L.

2015-01-01

CHIP is a tetratricopeptide repeat (TPR) domain protein that functions as an E3-ubiquitin ligase. As well as linking the molecular chaperones to the ubiquitin proteasome system, CHIP also has a docking-dependent mode where it ubiquitinates native substrates, thereby regulating their steady state levels and/or function. Here we explore the effect of Hsp70 on the docking-dependent E3-ligase activity of CHIP. The TPR-domain is revealed as a binding site for allosteric modulators involved in determining CHIP's dynamic conformation and activity. Biochemical, biophysical and modeling evidence demonstrate that Hsp70-binding to the TPR, or Hsp70-mimetic mutations, regulate CHIP-mediated ubiquitination of p53 and IRF-1 through effects on U-box activity and substrate binding. HDX-MS was used to establish that conformational-inhibition-signals extended from the TPR-domain to the U-box. This underscores inter-domain allosteric regulation of CHIP by the core molecular chaperones. Defining the chaperone-associated TPR-domain of CHIP as a manager of inter-domain communication highlights the potential for scaffolding modules to regulate, as well as assemble, complexes that are fundamental to protein homeostatic control. PMID:26330542

Experiences in flip chip production of radiation detectors

NASA Astrophysics Data System (ADS)

Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

2006-09-01

Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang Meizhen; Shi Longzhao; Wang Yuxing

2006-08-15

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13x13 mm{sup 2}, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range ofmore » a 13x13 mm{sup 2} active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was {+-}20 {mu}m. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.« less

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

NASA Astrophysics Data System (ADS)

Huang, Mei-Zhen; Shi, Long-Zhao; Wang, Yu-Xing; Ni, Yi; Li, Zhen-Qing; Ding, Hai-Feng

2006-08-01

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13×13mm2, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range of a 13×13mm2 active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was ±20μm. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.

Dual signal amplification of surface plasmon resonance imaging for sensitive immunoassay of tumor marker.

PubMed

Hu, Weihua; Chen, Hongming; Shi, Zhuanzhuan; Yu, Ling

2014-05-15

Surface plasmon resonance imaging (SPRi) is an intriguing technique for immunoassay with the inherent advantages of being high throughput, real time, and label free, but its sensitivity needs essential improvement for practical applications. Here, we report a dual signal amplification strategy using functional gold nanoparticles (AuNPs) followed by on-chip atom transfer radical polymerization (ATRP) for sensitive SPRi immunoassay of tumor biomarker in human serum. The AuNPs are grafted with an initiator of ATRP as well as a recognition antibody, where the antibody directs the specific binding of functional AuNPs onto the SPRi sensing surface to form immunocomplexes for first signal amplification and the initiator allows for on-chip ATRP of 2-hydroxyethyl methacrylate (HEMA) from the AuNPs to further enhance the SPRi signal. High sensitivity and broad dynamic range are achieved with this dual signal amplification strategy for detection of a model tumor marker, α-fetoprotein (AFP), in 10% human serum. Copyright © 2014 Elsevier Inc. All rights reserved.

Bi-level multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A bi-level, multilayered package with an integral window for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that the light-sensitive side is optically accessible through the window. A second chip can be bonded to the backside of the first chip, with the second chip being wirebonded to the second level of the bi-level package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed.

Low-power, transparent optical network interface for high bandwidth off-chip interconnects.

PubMed

Liboiron-Ladouceur, Odile; Wang, Howard; Garg, Ajay S; Bergman, Keren

2009-04-13

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

Engineered peptide-based nanobiomaterials for electrochemical cell chip.

PubMed

Kafi, Md Abdul; Cho, Hyeon-Yeol; Choi, Jeong-Woo

2016-01-01

Biomaterials having cell adhesion ability are considered to be integral part of a cell chip. A number of researches have been carried out to search for a suitable material for effective immobilization of cell on substrate. Engineered ECM materials or their components like collagen, Poly-l-Lysine (PLL), Arg-Gly-Asp (RGD) peptide have been extensively used for mammalian cell adhesion and proliferation with the aim of tissue regeneration or cell based sensing application. This review focuses on the various approaches for two- and three-dimensionally patterned nanostructures of a short peptide i.e. RGD peptide on chip surfaces together with their effects on cell behaviors and electrochemical measurements. Most of the study concluded with positive remarks on the well-oriented engineered RGD peptide over their homogenous thin film. The engineered RGD peptide not only influences cell adhesion, spreading and proliferation but also their periodic nano-arrays directly influence electrochemical measurements of the chips. The electrochemical signals found to be enhanced when RGD peptides were used in well-defined two-dimensional nano-arrays. The topographic alteration of three-dimensional structure of engineered RGD peptide was reported to be suitably contacted with the integrin receptors of cellular membrane which results indicated the enhanced cell-electrode adhesion and efficient electron exchange phenomenon. This enhanced electrochemical signal increases the sensitivity of the chip against the target analytes. Therefore, development of engineered cellular recognizable peptides and its 3D topological design for fabrication of cell chip will provide the synergetic effect on bio-affinity, sensitivity and accuracy for the in situ real-time monitoring of analytes.

Low-Power SOI CMOS Transceiver

NASA Technical Reports Server (NTRS)

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

The Antitumor Effect of C-terminus of Hsp70-Interacting Protein via Degradation of c-Met in Small Cell Lung Cancer.

PubMed

Cho, Sung Ho; Kim, Jong In; Kim, Hyun Su; Park, Sung Dal; Jang, Kang Won

2017-06-01

The mesenchymal-epithelial transition factor (MET) receptor can be overexpressed in solid tumors, including small cell lung cancer (SCLC). However, the molecular mechanism regulating MET stability and turnover in SCLC remains undefined. One potential mechanism of MET regulation involves the C-terminus of Hsp70-interacting protein (CHIP), which targets heat shock protein 90-interacting proteins for ubiquitination and proteasomal degradation. In the present study, we investigated the functional effects of CHIP expression on MET regulation and the control of SCLC cell apoptosis and invasion. To evaluate the expression of CHIP and c-Met, which is a protein that in humans is encoded by the MET gene (the MET proto-oncogene), we examined the expression pattern of c-Met and CHIP in SCLC cell lines by western blotting. To investigate whether CHIP overexpression reduced cell proliferation and invasive activity in SCLC cell lines, we transfected cells with CHIP and performed a cell viability assay and cellular apoptosis assays. We found an inverse relationship between the expression of CHIP and MET in SCLC cell lines (n=5). CHIP destabilized the endogenous MET receptor in SCLC cell lines, indicating an essential role for CHIP in the regulation of MET degradation. In addition, CHIP inhibited MET-dependent pathways, and invasion, cell growth, and apoptosis were reduced by CHIP overexpression in SCLC cell lines. CHIP is capable of regulating SCLC cell apoptosis and invasion by inhibiting MET-mediated cytoskeletal and cell survival pathways in NCI-H69 cells. CHIP suppresses MET-dependent signaling, and regulates MET-mediated SCLC motility.

Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging

NASA Astrophysics Data System (ADS)

Shih, T. I.; Duh, J. G.

2008-06-01

The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points.

A Study of Chip Formation Feedrates of Various Steels in Low-Speed Milling Process

NASA Astrophysics Data System (ADS)

Prasetyo, L.; Tauviqirrahman, M.; Rusnaldy

2017-05-01

Milling is a process of metal removal by feeding the workpiece a rotating multitoothed cutter. The objective of the study was to investigate the chip characteristics (chip length, width, and thickness) during the milling process by varying the feedrates and the types of materials used based on an experimental approach. The chosen materials were AISI 1020, AISI 1045, AISI 1090, AISI D2, and AISI 4340 with a high-speed steel (HSS) as a cutter. In this work, the feedrates were varied of 5, 10, and 15 mm/minutes with the depth of cut of 0.5 mm and a low spindle speed of 70 rpm. The results show that, in general, increasing the feedrate will lead to the growth of chip length, width, and thickness for all types of materials used. Also, related to the chip shape, AISI 1020 produces the discontinuous chip which can be related to its hardness value.

Development of the output monitor with single-chip microcomputer in a time-keeping system.

NASA Astrophysics Data System (ADS)

Zhou, Jiguang; Gong, Yuanfang

An output monitor has been designed with Intel 8031 single-chip microcomputer for a time working station. The functions of the instrument include the comparable measurement of the clocks, the buffer output of time and frequency signals, the monitoring and alarming of working state etc. The principle and application of the instrument are described.

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Signal amplification by magnetic force on polydiacetylene supramolecules for detection of prostate cancer.

PubMed

Kwon, Il Kyoung; Song, Min Sun; Won, Sang Ho; Choi, Seung Phill; Kim, Moonil; Sim, Sang Jun

2012-01-23

A method in which a permanent magnet is introduced onto polydiacetylene (PDA) vesicle chips is introduced for enhancement of the fluorescence of PDA vesicles. This strategy can be applied to general antibody-based PDA vesicle chips to detect clinically important biomarkers for disease diagnosis. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Vertically aligned carbon nanofiber as nano-neuron interface for monitoring neural function.

PubMed

Yu, Zhe; McKnight, Timothy E; Ericson, M Nance; Melechko, Anatoli V; Simpson, Michael L; Morrison, Barclay

2012-05-01

Neural chips, which are capable of simultaneous multisite neural recording and stimulation, have been used to detect and modulate neural activity for almost thirty years. As neural interfaces, neural chips provide dynamic functional information for neural decoding and neural control. By improving sensitivity and spatial resolution, nano-scale electrodes may revolutionize neural detection and modulation at cellular and molecular levels as nano-neuron interfaces. We developed a carbon-nanofiber neural chip with lithographically defined arrays of vertically aligned carbon nanofiber electrodes and demonstrated its capability of both stimulating and monitoring electrophysiological signals from brain tissues in vitro and monitoring dynamic information of neuroplasticity. This novel nano-neuron interface may potentially serve as a precise, informative, biocompatible, and dual-mode neural interface for monitoring of both neuroelectrical and neurochemical activity at the single-cell level and even inside the cell. The authors demonstrate the utility of a neural chip with lithographically defined arrays of vertically aligned carbon nanofiber electrodes. The new device can be used to stimulate and/or monitor signals from brain tissue in vitro and for monitoring dynamic information of neuroplasticity both intracellularly and at the single cell level including neuroelectrical and neurochemical activities. Copyright © 2012 Elsevier Inc. All rights reserved.

On-chip spin-controlled orbital angular momentum directional coupling

NASA Astrophysics Data System (ADS)

Xie, Zhenwei; Lei, Ting; Si, Guangyuan; Du, Luping; Lin, Jiao; Min, Changjun; Yuan, Xiaocong

2018-01-01

Optical vortex beams have many potential applications in the particle trapping, quantum encoding, optical orbital angular momentum (OAM) communications and interconnects. However, the on-chip compact OAM detection is still a big challenge. Based on a holographic configuration and a spin-dependent structure design, we propose and demonstrate an on-chip spin-controlled OAM-mode directional coupler, which can couple the OAM signal to different directions due to its topological charge. While the directional coupling function can be switched on/off by altering the spin of incident beam. Both simulation and experimental measurements verify the validity of the proposed approach. This work would benefit the on-chip OAM devices for optical communications and high dimensional quantum coding/decoding in the future.

Reliability study of high-brightness multiple single emitter diode lasers

NASA Astrophysics Data System (ADS)

Zhu, Jing; Yang, Thomas; Zhang, Cuipeng; Lang, Chao; Jiang, Xiaochen; Liu, Rui; Gao, Yanyan; Guo, Weirong; Jiang, Yuhua; Liu, Yang; Zhang, Luyan; Chen, Louisa

2015-03-01

In this study the chip bonding processes for various chips from various chip suppliers around the world have been optimized to achieve reliable chip on sub-mount for high performance. These chip on sub-mounts, for examples, includes three types of bonding, 8xx nm-1.2W/10.0W Indium bonded lasers, 9xx nm 10W-20W AuSn bonded lasers and 1470 nm 6W Indium bonded lasers will be reported below. The MTTF@25 of 9xx nm chip on sub-mount (COS) is calculated to be more than 203,896 hours. These chips from various chip suppliers are packaged into many multiple single emitter laser modules, using similar packaging techniques from 2 emitters per module to up to 7 emitters per module. A reliability study including aging test is performed on those multiple single emitter laser modules. With research team's 12 years' experienced packaging design and techniques, precise optical and fiber alignment processes and superior chip bonding capability, we have achieved a total MTTF exceeding 177,710 hours of life time with 60% confidence level for those multiple single emitter laser modules. Furthermore, a separated reliability study on wavelength stabilized laser modules have shown this wavelength stabilized module packaging process is reliable as well.

Teaching Quality Control with Chocolate Chip Cookies

ERIC Educational Resources Information Center

Baker, Ardith

2014-01-01

Chocolate chip cookies are used to illustrate the importance and effectiveness of control charts in Statistical Process Control. By counting the number of chocolate chips, creating the spreadsheet, calculating the control limits and graphing the control charts, the student becomes actively engaged in the learning process. In addition, examining…

Sensitive Spin Detection Using An On-Chip Squid-Waveguide Resonator

NASA Astrophysics Data System (ADS)

Yue, Guang

Quantum computing gives novel way of computing using quantum mechanics, which furthers human knowledge and has exciting applications. Quantum systems with diluted spins such as rare earth ions hosted in single crystal, molecule-based magnets etc. are promising qubits candidates to form the basis of a quantum computer. High sensitivity measurement and coherent control of these spin systems are crucial for their practical usage as qubits. The micro-SQUID (direct-current micrometer-sized Superconducting QUantum Interference Device) is capable to measure magnetization of spin system with high sensitivity. For example, the micro-SQUID technique can measure magnetic moments as small as several thousand muB as shown by the study of [W. Wernsdorfer, Supercond. Sci. Technol. 22, 064013 (2009)]. Here we develop a novel on-chip setup that combines the micro-SQUID sensitivity with microwave excitation. Such setup can be used for electron spin resonance measurements or coherent control of spins utilizing the high sensitivity of micro-SQUID for signal detection. To build the setup, we studied the fabrication process of the micro-SQUID, which is made of weak-linked Josephson junctions. The SQUID as a detector is integrated on the same chip with a shorted coplanar waveguide, so that the microwave pulses can be applied through the waveguide to excite the sample for resonance measurements. The whole device is plasma etched from a thin (˜ 20nm) niobium film, so that the SQUID can work at in large in-plane magnetic fields of several tesla. In addition, computer simulations are done to find the best design of the waveguide such that the microwave excitation field is sufficiently strong and uniformly applied to the sample. The magnetization curve of Mn12 molecule-based magnet sample is measured to prove the proper working of the micro-SQUID. Electron spin resonance measurement is done on the setup for gadolinium ions diluted in a CaWO4 single crystal. The measurement shows clear evidence of the resonance signal from the 1st transition of the gadolinium ions' energy levels, which shows the setup is successfully built. Due to the high sensitivity of micro-SQUID and the ability to concentrate microwave energy in small areas of the chip, this setup can detect signals from a small number of spins (107) in a small volume (several mum 3).

Tailorable stimulated Brillouin scattering in nanoscale silicon waveguides.

PubMed

Shin, Heedeuk; Qiu, Wenjun; Jarecki, Robert; Cox, Jonathan A; Olsson, Roy H; Starbuck, Andrew; Wang, Zheng; Rakich, Peter T

2013-01-01

Nanoscale modal confinement is known to radically enhance the effect of intrinsic Kerr and Raman nonlinearities within nanophotonic silicon waveguides. By contrast, stimulated Brillouin-scattering nonlinearities, which involve coherent coupling between guided photon and phonon modes, are stifled in conventional nanophotonics, preventing the realization of a host of Brillouin-based signal-processing technologies in silicon. Here we demonstrate stimulated Brillouin scattering in silicon waveguides, for the first time, through a new class of hybrid photonic-phononic waveguides. Tailorable travelling-wave forward-stimulated Brillouin scattering is realized-with over 1,000 times larger nonlinearity than reported in previous systems-yielding strong Brillouin coupling to phonons from 1 to 18 GHz. Experiments show that radiation pressures, produced by subwavelength modal confinement, yield enhancement of Brillouin nonlinearity beyond those of material nonlinearity alone. In addition, such enhanced and wideband coherent phonon emission paves the way towards the hybridization of silicon photonics, microelectromechanical systems and CMOS signal-processing technologies on chip.

Optical wireless link between a nanoscale antenna and a transducing rectenna.

PubMed

Dasgupta, Arindam; Mennemanteuil, Marie-Maxime; Buret, Mickaël; Cazier, Nicolas; Colas-des-Francs, Gérard; Bouhelier, Alexandre

2018-05-18

Initiated as a cable-replacement solution, short-range wireless power transfer has rapidly become ubiquitous in the development of modern high-data throughput networking in centimeter to meter accessibility range. Wireless technology is now penetrating a higher level of system integration for chip-to-chip and on-chip radiofrequency interconnects. However, standard CMOS integrated millimeter-wave antennas have typical size commensurable with the operating wavelength, and are thus an unrealistic solution for downsizing transmitters and receivers to the micrometer and nanometer scale. Herein, we demonstrate a light-in and electrical signal-out, on-chip wireless near-infrared link between a 220 nm optical antenna and a sub-nanometer rectifying antenna converting the transmitted optical energy into direct electrical current. The co-integration of subwavelength optical functional devices with electronic transduction offers a disruptive solution to interface photons and electrons at the nanoscale for on-chip wireless optical interconnects.

Multi-channel imaging cytometry with a single detector

NASA Astrophysics Data System (ADS)

Locknar, Sarah; Barton, John; Entwistle, Mark; Carver, Gary; Johnson, Robert

2018-02-01

Multi-channel microscopy and multi-channel flow cytometry generate high bit data streams. Multiple channels (both spectral and spatial) are important in diagnosing diseased tissue and identifying individual cells. Omega Optical has developed techniques for mapping multiple channels into the time domain for detection by a single high gain, high bandwidth detector. This approach is based on pulsed laser excitation and a serial array of optical fibers coated with spectral reflectors such that up to 15 wavelength bins are sequentially detected by a single-element detector within 2.5 μs. Our multichannel microscopy system uses firmware running on dedicated DSP and FPGA chips to synchronize the laser, scanning mirrors, and sampling clock. The signals are digitized by an NI board into 14 bits at 60MHz - allowing for 232 by 174 pixel fields in up to 15 channels with 10x over sampling. Our multi-channel imaging cytometry design adds channels for forward scattering and back scattering to the fluorescence spectral channels. All channels are detected within the 2.5 μs - which is compatible with fast cytometry. Going forward, we plan to digitize at 16 bits with an A-toD chip attached to a custom board. Processing these digital signals in custom firmware would allow an on-board graphics processing unit to display imaging flow cytometry data over configurable scanning line lengths. The scatter channels can be used to trigger data buffering when a cell is present in the beam. This approach enables a low cost mechanically robust imaging cytometer.

A VLSI implementation for synthetic aperture radar image processing

NASA Technical Reports Server (NTRS)

Premkumar, A.; Purviance, J.

1990-01-01

A simple physical model for the Synthetic Aperture Radar (SAR) is presented. This model explains the one dimensional and two dimensional nature of the received SAR signal in the range and azimuth directions. A time domain correlator, its algorithm, and features are explained. The correlator is ideally suited for VLSI implementation. A real time SAR architecture using these correlators is proposed. In the proposed architecture, the received SAR data is processed using one dimensional correlators for determining the range while two dimensional correlators are used to determine the azimuth of a target. The architecture uses only three different types of custom VLSI chips and a small amount of memory.

CAVIAR: a 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing- learning-actuating system for high-speed visual object recognition and tracking.

PubMed

Serrano-Gotarredona, Rafael; Oster, Matthias; Lichtsteiner, Patrick; Linares-Barranco, Alejandro; Paz-Vicente, Rafael; Gomez-Rodriguez, Francisco; Camunas-Mesa, Luis; Berner, Raphael; Rivas-Perez, Manuel; Delbruck, Tobi; Liu, Shih-Chii; Douglas, Rodney; Hafliger, Philipp; Jimenez-Moreno, Gabriel; Civit Ballcels, Anton; Serrano-Gotarredona, Teresa; Acosta-Jimenez, Antonio J; Linares-Barranco, Bernabé

2009-09-01

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.

Research on Control System of Three - phase Brushless DC Motor for Electric Vehicle

NASA Astrophysics Data System (ADS)

Wang, Zhiwei; Jin, Hai; Guo, Jie; Su, Jie; Wang, Miao

2017-12-01

In order to study the three-phase brushless motor control system of electric vehicle, Freescale9S12XS128 chip is used as the control core, and the power MOSFET is used as the inverter device. The software is compiled by Codewarrior software. The speed control link adopts open-loop control, and the control chip collects the external sensor signal voltage Change control PWM signal output control three-phase brushless DC motor speed. The whole system consists of Hall position detection module, current detection module, power drive module and voltage detection module. The basic functions of three-phase brushless DC motor drive control are realized.

On-chip, self-detected terahertz dual-comb source

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rösch, Markus, E-mail: mroesch@phys.ethz.ch; Scalari, Giacomo, E-mail: scalari@phys.ethz.ch; Villares, Gustavo

2016-04-25

We present a directly generated on-chip dual-comb source at terahertz (THz) frequencies. The multi-heterodyne beating signal of two free-running THz quantum cascade laser frequency combs is measured electrically using one of the combs as a detector, fully exploiting the unique characteristics of quantum cascade active regions. Up to 30 modes can be detected corresponding to a spectral bandwidth of 630 GHz, being the available bandwidth of the dual comb configuration. The multi-heterodyne signal is used to investigate the equidistance of the comb modes showing an accuracy of 10{sup −12} at the carrier frequency of 2.5 THz.

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

PubMed

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

Optimization of wireless Bluetooth sensor systems.

PubMed

Lonnblad, J; Castano, J; Ekstrom, M; Linden, M; Backlund, Y

2004-01-01

Within this study, three different Bluetooth sensor systems, replacing cables for transmission of biomedical sensor data, have been designed and evaluated. The three sensor architectures are built on 1-, 2- and 3-chip solutions and depending on the monitoring situation and signal character, different solutions are optimal. Essential parameters for all systems have been low physical weight and small size, resistance to interference and interoperability with other technologies as global- or local networks, PC's and mobile phones. Two different biomedical input signals, ECG and PPG (photoplethysmography), have been used to evaluate the three solutions. The study shows that it is possibly to continuously transmit an analogue signal. At low sampling rates and slowly varying parameters, as monitoring the heart rate with PPG, the 1-chip solution is the most suitable, offering low power consumption and thus a longer battery lifetime or a smaller battery, minimizing the weight of the sensor system. On the other hand, when a higher sampling rate is required, as an ECG, the 3-chip architecture, with a FPGA or micro-controller, offers the best solution and performance. Our conclusion is that Bluetooth might be useful in replacing cables of medical monitoring systems.

Chemiresistive and Gravimetric Dual-Mode Gas Sensor toward Target Recognition and Differentiation.

PubMed

Chen, Yan; Zhang, Hao; Feng, Zhihong; Zhang, Hongxiang; Zhang, Rui; Yu, Yuanyuan; Tao, Jin; Zhao, Hongyuan; Guo, Wenlan; Pang, Wei; Duan, Xuexin; Liu, Jing; Zhang, Daihua

2016-08-24

We demonstrate a dual-mode gas sensor for simultaneous and independent acquisition of electrical and mechanical signals from the same gas adsorption event. The device integrates a graphene field-effect transistor (FET) with a piezoelectric resonator in a seamless manner by leveraging multiple structural and functional synergies. Dual signals resulting from independent physical processes, i.e., mass attachment and charge transfer can reflect intrinsic properties of gas molecules and potentially enable target recognition and quantification at the same time. Fabrication of the device is based on standard Integrated Circuit (IC) foundry processes and fully compatible with system-on-a-chip (SoC) integration to achieve extremely small form factors. In addition, the ability of simultaneous measurements of mass adsorption and charge transfer guides us to a more precise understanding of the interactions between graphene and various gas molecules. Besides its practical functions, the device serves as an effective tool to quantitatively investigate the physical processes and sensing mechanisms for a large library of sensing materials and target analytes.

Signal-chip microcomputer control system for a diffraction grating ruling engine

NASA Astrophysics Data System (ADS)

Wang, Xiaolin; Zhang, Yuhua; Yang, Houmin; Guo, Du

1998-08-01

A control system with a chip of 8031 single-chip microcomputer as its nucleus for a diffraction grating ruling engine has been developed, its hardware and software are presented in this paper. A series of techniques such as program-controlled amplifier and interference fringes subdivision as well as motor velocity step governing are adopted to improve the control accuracy. With this control system, 8 kinds of gratings of different spacings can be ruled, the positioning precision of the diffraction grating ruling engine (sigma) equals 3.6 nm, and the maximum positioning error is less than 14.6 nm.

Integrated Optics for Planar imaging and Optical Signal Processing

NASA Astrophysics Data System (ADS)

Song, Qi

Silicon photonics is a subject of growing interest with the potential of delivering planar electro-optical devices with chip scale integration. Silicon-on-insulator (SOI) technology has provided a marvelous platform for photonics industry because of its advantages in integration capability in CMOS circuit and countless nonlinearity applications in optical signal processing. This thesis is focused on the investigation of planar imaging techniques on SOI platform and potential applications in ultra-fast optical signal processing. In the first part, a general review and background introduction about integrated photonics circuit and planar imaging technique are provided. In chapter 2, planar imaging platform is realized by a silicon photodiode on SOI chip. Silicon photodiode on waveguide provides a high numerical aperture for an imaging transceiver pixel. An erbium doped Y2O3 particle is excited by 1550nm Laser and the fluorescent image is obtained with assistance of the scanning system. Fluorescence image is reconstructed by using image de-convolution technique. Under photovoltaic mode, we use an on-chip photodiode and an external PIN photodiode to realize similar resolution as 5μm. In chapter 3, a time stretching technique is developed to a spatial domain to realize a 2D imaging system as an ultrafast imaging tool. The system is evaluated based on theoretical calculation. The experimental results are shown for a verification of system capability to imaging a micron size particle or a finger print. Meanwhile, dynamic information for a moving object is also achieved by correlation algorithm. In chapter 4, the optical leaky wave antenna based on SOI waveguide has been utilized for imaging applications and extensive numerical studied has been conducted. and the theoretical explanation is supported by leaky wave theory. The highly directive radiation has been obtained from the broadside with 15.7 dB directivity and a 3dB beam width of ΔØ 3dB ≈ 1.65° in free space environment when β -1 = 2.409 × 105/m, α=4.576 ×103/m. At the end, electronics beam-steering principle has been studied and the comprehensive model has been built to explain carrier transformation behavior in a PIN junction as individual silicon perturbation. Results show that 1019/cm3 is possible obtained with electron injection mechanism. Although the radiation modulation based on carrier injection of 1019/cm3 gives 0.5dB variation, resonant structure, such as Fabry Perrot Cavity, can be integrated with LOWAs to enhance modulation effect.

Apparatus to collect, classify, concentrate, and characterize gas-borne particles

DOEpatents

Rader, Daniel J.; Torczynski, John R.; Wally, Karl; Brockmann, John E.

2003-12-16

An aerosol lab-on-a-chip (ALOC) integrates one or more of a variety of particle collection, classification, concentration (enrichment), an characterization processes onto a single substrate or layered stack of such substrates. By mounting a UV laser diode laser light source on the substrate, or substrates tack, so that it is located down-stream of the sample inlet port and at right angle the sample particle stream, the UV light source can illuminate individual particles in the stream to induce a fluorescence response in those particles having a fluorescent signature such as biological particles, some of said particles. An illuminated particle having a fluorescent signal above a threshold signal would trigger a sorter module that would separate that particle from the particle stream.

Spiral Chip Implantable Radiator and Printed Loop External Receptor for RF Telemetry in Bio-Sensor Systems

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Hall, David G.; Miranda, Felix A.

2004-01-01

The paper describes the operation of a patented wireless RF telemetry system, consisting of a bio-MEMS implantable sensor and an external hand held unit, operating over the frequency range of few hundreds of MHz. A MEMS capacitive pressure sensor integrated with a miniature inductor/antenna together constitute the implantable sensor. Signal processing circuits collocated with a printed loop antenna together form the hand held unit, capable of inductively powering and also receiving the telemetry signals from the sensor. The paper in addition, demonstrates a technique to enhance the quality factor and inductance of the inductor in the presence of a lower ground plane and also presents the radiation characteristics of the loop antenna.

Property-driven functional verification technique for high-speed vision system-on-chip processor

NASA Astrophysics Data System (ADS)

Nshunguyimfura, Victor; Yang, Jie; Liu, Liyuan; Wu, Nanjian

2017-04-01

The implementation of functional verification in a fast, reliable, and effective manner is a challenging task in a vision chip verification process. The main reason for this challenge is the stepwise nature of existing functional verification techniques. This vision chip verification complexity is also related to the fact that in most vision chip design cycles, extensive efforts are focused on how to optimize chip metrics such as performance, power, and area. Design functional verification is not explicitly considered at an earlier stage at which the most sound decisions are made. In this paper, we propose a semi-automatic property-driven verification technique. The implementation of all verification components is based on design properties. We introduce a low-dimension property space between the specification space and the implementation space. The aim of this technique is to speed up the verification process for high-performance parallel processing vision chips. Our experimentation results show that the proposed technique can effectively improve the verification effort up to 20% for the complex vision chip design while reducing the simulation and debugging overheads.

From Understanding Cellular Function to Novel Drug Discovery: The Role of Planar Patch-Clamp Array Chip Technology

PubMed Central

Py, Christophe; Martina, Marzia; Diaz-Quijada, Gerardo A.; Luk, Collin C.; Martinez, Dolores; Denhoff, Mike W.; Charrier, Anne; Comas, Tanya; Monette, Robert; Krantis, Anthony; Syed, Naweed I.; Mealing, Geoffrey A. R.

2011-01-01

All excitable cell functions rely upon ion channels that are embedded in their plasma membrane. Perturbations of ion channel structure or function result in pathologies ranging from cardiac dysfunction to neurodegenerative disorders. Consequently, to understand the functions of excitable cells and to remedy their pathophysiology, it is important to understand the ion channel functions under various experimental conditions – including exposure to novel drug targets. Glass pipette patch-clamp is the state of the art technique to monitor the intrinsic and synaptic properties of neurons. However, this technique is labor intensive and has low data throughput. Planar patch-clamp chips, integrated into automated systems, offer high throughputs but are limited to isolated cells from suspensions, thus limiting their use in modeling physiological function. These chips are therefore not most suitable for studies involving neuronal communication. Multielectrode arrays (MEAs), in contrast, have the ability to monitor network activity by measuring local field potentials from multiple extracellular sites, but specific ion channel activity is challenging to extract from these multiplexed signals. Here we describe a novel planar patch-clamp chip technology that enables the simultaneous high-resolution electrophysiological interrogation of individual neurons at multiple sites in synaptically connected neuronal networks, thereby combining the advantages of MEA and patch-clamp techniques. Each neuron can be probed through an aperture that connects to a dedicated subterranean microfluidic channel. Neurons growing in networks are aligned to the apertures by physisorbed or chemisorbed chemical cues. In this review, we describe the design and fabrication process of these chips, approaches to chemical patterning for cell placement, and present physiological data from cultured neuronal cells. PMID:22007170

From understanding cellular function to novel drug discovery: the role of planar patch-clamp array chip technology.

PubMed

Py, Christophe; Martina, Marzia; Diaz-Quijada, Gerardo A; Luk, Collin C; Martinez, Dolores; Denhoff, Mike W; Charrier, Anne; Comas, Tanya; Monette, Robert; Krantis, Anthony; Syed, Naweed I; Mealing, Geoffrey A R

2011-01-01

All excitable cell functions rely upon ion channels that are embedded in their plasma membrane. Perturbations of ion channel structure or function result in pathologies ranging from cardiac dysfunction to neurodegenerative disorders. Consequently, to understand the functions of excitable cells and to remedy their pathophysiology, it is important to understand the ion channel functions under various experimental conditions - including exposure to novel drug targets. Glass pipette patch-clamp is the state of the art technique to monitor the intrinsic and synaptic properties of neurons. However, this technique is labor intensive and has low data throughput. Planar patch-clamp chips, integrated into automated systems, offer high throughputs but are limited to isolated cells from suspensions, thus limiting their use in modeling physiological function. These chips are therefore not most suitable for studies involving neuronal communication. Multielectrode arrays (MEAs), in contrast, have the ability to monitor network activity by measuring local field potentials from multiple extracellular sites, but specific ion channel activity is challenging to extract from these multiplexed signals. Here we describe a novel planar patch-clamp chip technology that enables the simultaneous high-resolution electrophysiological interrogation of individual neurons at multiple sites in synaptically connected neuronal networks, thereby combining the advantages of MEA and patch-clamp techniques. Each neuron can be probed through an aperture that connects to a dedicated subterranean microfluidic channel. Neurons growing in networks are aligned to the apertures by physisorbed or chemisorbed chemical cues. In this review, we describe the design and fabrication process of these chips, approaches to chemical patterning for cell placement, and present physiological data from cultured neuronal cells.

Detection of tobacco rattle virus RNA in processed potato chips displaying symptoms of corky ringspot disease

USDA-ARS?s Scientific Manuscript database

A portion of genomic RNA 1 of tobacco rattle tobravirus (TRV) was amplified by reverse transcription polymerase chain reaction from each of eight processed potato chips from three different bags purchased at three locations. The positive chips all had symptoms typical of corky ringspot disease, cau...

Study of process parameter on mist lubrication of Titanium (Grade 5) alloy

NASA Astrophysics Data System (ADS)

Maity, Kalipada; Pradhan, Swastik

2017-02-01

This paper deals with the machinability of Ti-6Al-4V alloy with mist cooling lubrication using carbide inserts. The influence of process parameter on the cutting forces, evolution of tool wear, surface finish of the workpiece, material removal rate and chip reduction coefficient have been investigated. Weighted principal component analysis coupled with grey relational analysis optimization is applied to identify the optimum setting of the process parameter. Optimal condition of the process parameter was cutting speed at 160 m/min, feed at 0.16 mm/rev and depth of cut at 1.6 mm. Effects of cutting speed and depth of cut on the type of chips formation were observed. Most of the chips forms were long tubular and long helical type. Image analyses of the segmented chip were examined to study the shape and size of the saw tooth profile of serrated chips. It was found that by increasing cutting speed from 95 m/min to 160 m/min, the free surface lamella of the chips increased and the visibility of the saw tooth segment became clearer.

Integrated circuit for SAW and MEMS sensors

NASA Astrophysics Data System (ADS)

Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

2001-11-01

The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

Advanced Initiation Systems Manufacturing Level 2 Milestone Completion Summary

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chow, R; Schmidt, M

2009-10-01

Milestone Description - Advanced Initiation Systems Detonator Design and Prototype. Milestone Grading Criteria - Design new generation chip slapper detonator and manufacture a prototype using advanced manufacturing processes, such as all-dry chip metallization and solvent-less flyer coatings. The advanced processes have been developed for manufacturing detonators with high material compatibility and reliability to support future LEPs, e.g. the B61, and new weapons systems. Perform velocimetry measurements to determine slapper velocity as a function of flight distance. A prototype detonator assembly and stripline was designed for low-energy chip slappers. Pictures of the prototype detonator and stripline are shown. All-dry manufacturing processesmore » were used to address compatibility issues. KCP metallized the chips in a physical vapor deposition system through precision-aligned shadow masks. LLNL deposited a solvent-less polyimide flyer with a processes called SLIP, which stands for solvent-less vapor deposition followed by in-situ polymerization. LANL manufactured the high-surface-area (HSA) high explosive (HE) pellets. Test fires of two chip slapper designs, radius and bowtie, were performed at LLNL in the High Explosives Application Facility (HEAF). Test fires with HE were conducted to establish the threshold firing voltages. pictures of the chip slappers before and after test fires are shown. Velocimetry tests were then performed to obtain slapper velocities at or above the threshold firing voltages. Figure 5 shows the slapper velocity as a function of distance and time at the threshold voltage, for both radius and bowtie bridge designs. Both designs were successful at initiating the HE at low energy levels. Summary of Accomplishments are: (1) All-dry process for chip manufacture developed; (2) Solventless process for slapper materials developed; (3) High-surface area explosive pellets developed; (4) High performance chip slappers developed; (5) Low-energy chip slapper detonator designs; and (6) Low-voltage threshold chip slapper detonator demonstrated.« less

Optical Characterization of Tissue Phantoms Using a Silicon Integrated fdNIRS System on Chip.

PubMed

Sthalekar, Chirag C; Miao, Yun; Koomson, Valencia Joyner

2017-04-01

An interface circuit with signal processing and digitizing circuits for a high frequency, large area avalanche photodiode (APD) has been integrated in a 130 nm BiCMOS chip. The system enables the absolute oximetry of tissue using frequency domain Near Infrared Spectroscopy (fdNIRS). The system measures the light absorbed and scattered by the tissue by measuring the reduction in the amplitude of signal and phase shift introduced between the light source and detector which are placed a finite distance away from each other. The received 80 MHz RF signal is downconverted to a low frequency and amplified using a heterodyning scheme. The front-end transimpedance amplifier has a 3-level programmable gain that increases the dynamic range to 60 dB. The phase difference between an identical reference channel and the optical channel is measured with a 0.5° accuracy. The detectable current range is [Formula: see text] and with a 40 A/W reponsivity using the APD, power levels as low as 500 pW can be detected. Measurements of the absorption and reduced scattering coefficients of solid tissue phantoms using this system are compared with those using a commercial instrument with differences within 30%. Measurement of a milk based liquid tissue phantom show an increase in absorption coefficient with addition of black ink. The miniaturized circuit serves as an efficiently scalable system for multi-site detection for applications in neonatal cerebral oximetry and optical mammography.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Rapid detection of aflatoxigenic Aspergillus sp. in herbal specimens by a simple, bendable, paper-based lab-on-a-chip.

PubMed

Chaumpluk, Piyasak; Plubcharoensook, Pattra; Prasongsuk, Sehanat

2016-06-01

Postharvest herbal product contamination with mycotoxins and mycotoxin-producing fungi represents a potentially carcinogenic hazard. Aspergillus flavus is a major cause of this issue. Available mold detection methods are PCR-based and rely heavily on laboratories; thus, they are unsuitable for on-site monitoring. In this study, a bendable, paper-based lab-on-a-chip platform was developed to rapidly detect toxigenic Aspergillus spp. DNA. The 3.0-4.0 cm(2) chip is fabricated using Whatman™ filter paper, fishing line and a simple plastic lamination process and has nucleic acid amplification and signal detection components. The Aspergillus assay specifically amplifies the aflatoxin biosynthesis gene, aflR, using loop-mediated isothermal amplification (LAMP); hybridization between target DNA and probes on blue silvernanoplates (AgNPls) yields colorimetric results. Positive results are indicated by the detection pad appearing blue due to dispersed blue AgNPls; negative results are indicated by the detection pad appearing colorless or pale yellow due to probe/target DNA hybridization and AgNPls aggregation. Assay completion requires less than 40 min, has a limit of detection (LOD) of 100 aflR copies, and has high specificity (94.47%)and sensitivity (100%). Contamination was identified in 14 of 32 herbal samples tested (43.75%). This work demonstrates the fabrication of a simple, low-cost, paper-based lab-on-a-chip platform suitable for rapid-detection applications. Copyright © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Continual exposure to cigarette smoke extracts induces tumor-like transformation of human nontumor bronchial epithelial cells in a microfluidic chip.

PubMed

Li, Encheng; Xu, Zhiyun; Liu, Fen; Wang, Huiling; Wen, Jiabin; Shao, Shujuan; Zhang, Lichuan; Wang, Lei; Liu, Chong; Lu, Jianxin; Wang, Wenxin; Gao, Zhancheng; Wang, Qi

2014-08-01

Heavy cigarette smoking-related chronic obstructive pulmonary disease is an independent risk factor for lung squamous carcinoma. However, the mechanisms underlying the malignant transformation of bronchial epithelial cells are unclear. In our study, human tumor-adjacent bronchial epithelial cells were obtained from 10 cases with smoking-related chronic obstructive pulmonary disease and lung squamous carcinoma and cultured in an established microfluidic chip for continual exposure to cigarette smoke extracts (CSE) to investigate the potential tumor-like transformation and mechanisms. The integrated microfluidic chip included upstream concentration gradient generator and downstream cell culture chambers supplied by flowing medium containing different concentrations of CSE. Our results showed that continual exposure to low doses of CSE promoted cell proliferation whereas to high doses of CSE triggered cell apoptosis. Continual exposure to CSE promoted reactive oxygen species production in human epithelial cells in a dose-dependent manner. More importantly, continual exposure to low dose of CSE promoted the epithelial-to-mesenchymal transition process and anchorage-independent growth, and increased chromosome instability in bronchial epithelial cells, accompanied by activating the GRP78, NF-κB, and PI3K pathways. The established microfluidic chip is suitable for primary culture of human tumor-adjacent bronchial epithelial cells to investigate the malignant transformation. Continual exposure to low doses of CSE promoted tumor-like transformation of human nontumor bronchial epithelial cells by inducing reactive oxygen species production and activating the relevant signaling.

Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus

The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various attributes that would make them superior for use in X-ray astronomy. In particular, PMOS has: "no" photo-charge recombination; "no" Random Telegraph Signal noise (RTS); and lower read noise. The existing SRI/Sarnoff PMOS devices are small and have been developed for non-intensified night vision applications, however, no x-ray evaluation of a monolithic PMOS device has ever been made. In addition to these PMOS devices, SAO will also evaluate existing NMOS scale-able format devices that can be fabricated in any rectangular size/shape using stitchable reticles. These "Mk by Nk" devices would be ideal for large X-ray focal planes or long grating readouts. The Sarnoff/SRI Mk by Nk format devices have been designed, with foresight, so that they can be fabricated in either PMOS or NMOS by changing a single fabrication reticle and by changing the type of Si substrate. If X-ray performance results are expected, this proposal will lead the way to future fabrication of Mk by Nk PMOS devices that would be ideal for X-ray astronomy missions such as "X-ray Surveyor". SAO will also investigate the interaction of directly deposited Optical Blocking Filters (OBFs) on various back side passivated devices, and their resultant effects on very "soft" x-ray response. The latest CMOS processes and very fast on-chip, and off-chip digital readout signal chains and camera systems will be demonstrated.

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Around Marshall

NASA Image and Video Library

2003-12-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Lab-on a-Chip

NASA Technical Reports Server (NTRS)

2003-01-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Implementation Strategies for a Universal Acquisition and Tracking Channel Applied to Real GNSS Signals.

PubMed

Fortin, Marc-Antoine; Landry, René

2016-05-02

This paper presents a universal GNSS receiver channel capable of tracking any civil GNSS signal. This fundamentally differs from dedicated channels, each customized for a given signal. A mobile device could integrate fewer universal channels to harvest all available signals. This would allow securing signal availability, while minimizing power consumption and chip size, thus maximizing battery lifetime. In fact, the universal channel allows sequential acquisition and tracking of any chipping rate, carrier frequency, FDMA channel, modulation, or constellation, and is totally configurable (any integration time, any discriminator, etc.). It can switch from one signal to another in 1.07 ms, making it possible for the receiver to rapidly adapt to its sensed environment. All this would consume 3.5 mW/channel in an ASIC implementation, i.e., with a slight overhead compared to the original GPS L1 C/A dedicated channel from which it was derived. After extensive surveys on GNSS signals and tracking channels, this paper details the implementation strategies that led to the proposed universal channel architecture. Validation is achieved using GNSS signals issued from different constellations, frequency bands, modulations and spreading code schemes. A discussion on acquisition approaches and conclusive remarks follow, which open up a new signal selection challenge, rather than satellite selection.

Implementation Strategies for a Universal Acquisition and Tracking Channel Applied to Real GNSS Signals

PubMed Central

Fortin, Marc-Antoine; Landry, René

2016-01-01

This paper presents a universal GNSS receiver channel capable of tracking any civil GNSS signal. This fundamentally differs from dedicated channels, each customized for a given signal. A mobile device could integrate fewer universal channels to harvest all available signals. This would allow securing signal availability, while minimizing power consumption and chip size, thus maximizing battery lifetime. In fact, the universal channel allows sequential acquisition and tracking of any chipping rate, carrier frequency, FDMA channel, modulation, or constellation, and is totally configurable (any integration time, any discriminator, etc.). It can switch from one signal to another in 1.07 ms, making it possible for the receiver to rapidly adapt to its sensed environment. All this would consume 3.5 mW/channel in an ASIC implementation, i.e., with a slight overhead compared to the original GPS L1 C/A dedicated channel from which it was derived. After extensive surveys on GNSS signals and tracking channels, this paper details the implementation strategies that led to the proposed universal channel architecture. Validation is achieved using GNSS signals issued from different constellations, frequency bands, modulations and spreading code schemes. A discussion on acquisition approaches and conclusive remarks follow, which open up a new signal selection challenge, rather than satellite selection. PMID:27144569

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Computation of dark frames in digital imagers

NASA Astrophysics Data System (ADS)

Widenhorn, Ralf; Rest, Armin; Blouke, Morley M.; Berry, Richard L.; Bodegom, Erik

2007-02-01

Dark current is caused by electrons that are thermally exited into the conduction band. These electrons are collected by the well of the CCD and add a false signal to the chip. We will present an algorithm that automatically corrects for dark current. It uses a calibration protocol to characterize the image sensor for different temperatures. For a given exposure time, the dark current of every pixel is characteristic of a specific temperature. The dark current of every pixel can therefore be used as an indicator of the temperature. Hot pixels have the highest signal-to-noise ratio and are the best temperature sensors. We use the dark current of a several hundred hot pixels to sense the chip temperature and predict the dark current of all pixels on the chip. Dark current computation is not a new concept, but our approach is unique. Some advantages of our method include applicability for poorly temperature-controlled camera systems and the possibility of ex post facto dark current correction.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

PubMed

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Construction of large scale switch matrix by interconnecting integrated optical switch chips with EDFAs

NASA Astrophysics Data System (ADS)

Liao, Mingle; Wu, Baojian; Hou, Jianhong; Qiu, Kun

2018-03-01

Large scale optical switches are essential components in optical communication network. We aim to build up a large scale optical switch matrix by the interconnection of silicon-based optical switch chips using 3-stage CLOS structure, where EDFAs are needed to compensate for the insertion loss of the chips. The optical signal-to-noise ratio (OSNR) performance of the resulting large scale optical switch matrix is investigated for TE-mode light and the experimental results are in agreement with the theoretical analysis. We build up a 64 ×64 switch matrix by use of 16 ×16 optical switch chips and the OSNR and receiver sensibility can respectively be improved by 0.6 dB and 0.2 dB by optimizing the gain configuration of the EDFAs.

In vitro RNA release from a human rhinovirus monitored by means of a molecular beacon and chip electrophoresis.

PubMed

Weiss, Victor U; Bliem, Christina; Gösler, Irene; Fedosyuk, Sofiya; Kratzmeier, Martin; Blaas, Dieter; Allmaier, Günter

2016-06-01

Liquid-phase electrophoresis either in the classical capillary format or miniaturized (chip CE) is a valuable tool for quality control of virus preparations and for targeting questions related to conformational changes of viruses during infection. We present an in vitro assay to follow the release of the RNA genome from a human rhinovirus (common cold virus) by using a molecular beacon (MB) and chip CE. The MB, a probe that becomes fluorescent upon hybridization to a complementary sequence, was designed to bind close to the 3' end of the viral genome. Addition of Trolox (6-hydroxy-2,5,7,8-tetramethylchroman-2-carboxylic acid), a well-known additive for reduction of bleaching and blinking of fluorophores in fluorescence microscopy, to the background electrolyte increased the sensitivity of our chip CE set-up. Hence, a fast, sensitive and straightforward method for the detection of viral RNA is introduced. Additionally, challenges of our assay will be discussed. In particular, we found that (i) desalting of virus preparations prior to analysis increased the recorded signal and (ii) the MB-RNA complex signal decreased with the time of virus storage at -70 °C. This suggests that 3'-proximal sequences of the viral RNA, if not the whole genome, underwent degradation during storage and/or freezing and thawing. In summary, we demonstrate, for two independent virus batches, that chip electrophoresis can be used to monitor MB hybridization to RNA released upon incubation of the native virus at 56 °C. Graphical Abstract Schematic of the study strategy: RNA released from HRV-A2 is detected by chip electrophoresis through the increase in fluorescence after genom complexation to a cognate molecular beacon.

A Novel and Simple Spike Sorting Implementation.

PubMed

Petrantonakis, Panagiotis C; Poirazi, Panayiota

2017-04-01

Monitoring the activity of multiple, individual neurons that fire spikes in the vicinity of an electrode, namely perform a Spike Sorting (SS) procedure, comprises one of the most important tools for contemporary neuroscience in order to reverse-engineer the brain. As recording electrodes' technology rabidly evolves by integrating thousands of electrodes in a confined spatial setting, the algorithms that are used to monitor individual neurons from recorded signals have to become even more reliable and computationally efficient. In this work, we propose a novel framework of the SS approach in which a single-step processing of the raw (unfiltered) extracellular signal is sufficient for both the detection and sorting of the activity of individual neurons. Despite its simplicity, the proposed approach exhibits comparable performance with state-of-the-art approaches, especially for spike detection in noisy signals, and paves the way for a new family of SS algorithms with the potential for multi-recording, fast, on-chip implementations.