Energy consumption estimation of an OMAP-based Android operating system

NASA Astrophysics Data System (ADS)

González, Gabriel; Juárez, Eduardo; Castro, Juan José; Sanz, César

2011-05-01

System-level energy optimization of battery-powered multimedia embedded systems has recently become a design goal. The poor operational time of multimedia terminals makes computationally demanding applications impractical in real scenarios. For instance, the so-called smart-phones are currently unable to remain in operation longer than several hours. The OMAP3530 processor basically consists of two processing cores, a General Purpose Processor (GPP) and a Digital Signal Processor (DSP). The former, an ARM Cortex-A8 processor, is aimed to run a generic Operating System (OS) while the latter, a DSP core based on the C64x+, has architecture optimized for video processing. The BeagleBoard, a commercial prototyping board based on the OMAP processor, has been used to test the Android Operating System and measure its performance. The board has 128 MB of SDRAM external memory, 256 MB of Flash external memory and several interfaces. Note that the clock frequency of the ARM and DSP OMAP cores is 600 MHz and 430 MHz, respectively. This paper describes the energy consumption estimation of the processes and multimedia applications of an Android v1.6 (Donut) OS on the OMAP3530-Based BeagleBoard. In addition, tools to communicate the two processing cores have been employed. A test-bench to profile the OS resource usage has been developed. As far as the energy estimates concern, the OMAP processor energy consumption model provided by the manufacturer has been used. The model is basically divided in two energy components. The former, the baseline core energy, describes the energy consumption that is independent of any chip activity. The latter, the module active energy, describes the energy consumed by the active modules depending on resource usage.

Low-Power Embedded DSP Core for Communication Systems

NASA Astrophysics Data System (ADS)

Tsao, Ya-Lan; Chen, Wei-Hao; Tan, Ming Hsuan; Lin, Maw-Ching; Jou, Shyh-Jye

2003-12-01

This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35[InlineEquation not available: see fulltext.]m SPQM and 0.25[InlineEquation not available: see fulltext.]m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a[InlineEquation not available: see fulltext.] version is 100 MHz (0.35[InlineEquation not available: see fulltext.]m) and 140 MHz (0.25[InlineEquation not available: see fulltext.]m).

A DSP equipped digitizer for online analysis of nuclear detector signals

NASA Astrophysics Data System (ADS)

Pasquali, G.; Ciaranfi, R.; Bardelli, L.; Bini, M.; Boiano, A.; Giannelli, F.; Ordine, A.; Poggi, G.

2007-01-01

In the framework of the NUCL-EX collaboration, a DSP equipped fast digitizer has been implemented and it has now reached the production stage. Each sampling channel is implemented on a separate daughter-board to be plugged on a VME mother-board. Each channel features a 12-bit, 125 MSamples/s ADC and a Digital Signal Processor (DSP) for online analysis of detector signals. A few algorithms have been written and successfully tested on detectors of different types (scintillators, solid-state, gas-filled), implementing pulse shape discrimination, constant fraction timing, semi-Gaussian shaping, gated integration.

A Real-Time System for Lane Detection Based on FPGA and DSP

NASA Astrophysics Data System (ADS)

Xiao, Jing; Li, Shutao; Sun, Bin

2016-12-01

This paper presents a real-time lane detection system including edge detection and improved Hough Transform based lane detection algorithm and its hardware implementation with field programmable gate array (FPGA) and digital signal processor (DSP). Firstly, gradient amplitude and direction information are combined to extract lane edge information. Then, the information is used to determine the region of interest. Finally, the lanes are extracted by using improved Hough Transform. The image processing module of the system consists of FPGA and DSP. Particularly, the algorithms implemented in FPGA are working in pipeline and processing in parallel so that the system can run in real-time. In addition, DSP realizes lane line extraction and display function with an improved Hough Transform. The experimental results show that the proposed system is able to detect lanes under different road situations efficiently and effectively.

Low-power wireless ECG acquisition and classification system for body sensor networks.

PubMed

Lee, Shuenn-Yuh; Hong, Jia-Hua; Hsieh, Cheng-Han; Liang, Ming-Chun; Chang Chien, Shih-Yu; Lin, Kuang-Hao

2015-01-01

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

Texas Instruments-Digital Signal Processor(TI-DSP)SMJ320F20 SEL Testing

NASA Technical Reports Server (NTRS)

Sanders, Anthony B.; Poivey, C.; Kim, H. S.; Gee, George B.

2006-01-01

This viewgraph presentation reviews the testing of the Texas Instrument Digital Signal Processor(TI-DSP)SMJ320F20. Tests were performed to screen for susceptibility to Single Event Latchup (SEL) and measure sensitivity as a function of Linear Energy Transfer (LET) for an application specific test setup. The Heavy Ion Testing of two TI-DSP SMJ320F240 devices experienced Single Event Latchup (SEL) conditions at an LET of 1.8 MeV/(mg/square cm) The devices were exposed from a fluence of 1.76 x l0(exp 3) to 5.00 x 10(exp 6) particles/square cm of the Neon, Argon and Krypton ion beams. For DI(sub DD) an average latchup current occurred at about 700mA, which is a magnitude of 10 over the nominal current of 700mA.

Dataflow Integration and Simulation Techniques for DSP System Design Tools

DTIC Science & Technology

2007-01-01

Lebak, M. Richards , and D. Campbell, “VSIPL: An object-based open standard API for vector, signal, and image processing,” in Proceedings of the...Inc., document Version 0.98a. [56] P. Marwedel and G. Goossens , Eds., Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995. [57

Automated speech understanding: the next generation

NASA Astrophysics Data System (ADS)

Picone, J.; Ebel, W. J.; Deshmukh, N.

1995-04-01

Modern speech understanding systems merge interdisciplinary technologies from Signal Processing, Pattern Recognition, Natural Language, and Linguistics into a unified statistical framework. These systems, which have applications in a wide range of signal processing problems, represent a revolution in Digital Signal Processing (DSP). Once a field dominated by vector-oriented processors and linear algebra-based mathematics, the current generation of DSP-based systems rely on sophisticated statistical models implemented using a complex software paradigm. Such systems are now capable of understanding continuous speech input for vocabularies of several thousand words in operational environments. The current generation of deployed systems, based on small vocabularies of isolated words, will soon be replaced by a new technology offering natural language access to vast information resources such as the Internet, and provide completely automated voice interfaces for mundane tasks such as travel planning and directory assistance.

Portable laser speckle perfusion imaging system based on digital signal processor.

PubMed

Tang, Xuejun; Feng, Nengyun; Sun, Xiaoli; Li, Pengcheng; Luo, Qingming

2010-12-01

The ability to monitor blood flow in vivo is of major importance in clinical diagnosis and in basic researches of life science. As a noninvasive full-field technique without the need of scanning, laser speckle contrast imaging (LSCI) is widely used to study blood flow with high spatial and temporal resolution. Current LSCI systems are based on personal computers for image processing with large size, which potentially limit the widespread clinical utility. The need for portable laser speckle contrast imaging system that does not compromise processing efficiency is crucial in clinical diagnosis. However, the processing of laser speckle contrast images is time-consuming due to the heavy calculation for enormous high-resolution image data. To address this problem, a portable laser speckle perfusion imaging system based on digital signal processor (DSP) and the algorithm which is suitable for DSP is described. With highly integrated DSP and the algorithm, we have markedly reduced the size and weight of the system as well as its energy consumption while preserving the high processing speed. In vivo experiments demonstrate that our portable laser speckle perfusion imaging system can obtain blood flow images at 25 frames per second with the resolution of 640 × 480 pixels. The portable and lightweight features make it capable of being adapted to a wide variety of application areas such as research laboratory, operating room, ambulance, and even disaster site.

High performance 3D adaptive filtering for DSP based portable medical imaging systems

NASA Astrophysics Data System (ADS)

Bockenbach, Olivier; Ali, Murtaza; Wainwright, Ian; Nadeski, Mark

2015-03-01

Portable medical imaging devices have proven valuable for emergency medical services both in the field and hospital environments and are becoming more prevalent in clinical settings where the use of larger imaging machines is impractical. Despite their constraints on power, size and cost, portable imaging devices must still deliver high quality images. 3D adaptive filtering is one of the most advanced techniques aimed at noise reduction and feature enhancement, but is computationally very demanding and hence often cannot be run with sufficient performance on a portable platform. In recent years, advanced multicore digital signal processors (DSP) have been developed that attain high processing performance while maintaining low levels of power dissipation. These processors enable the implementation of complex algorithms on a portable platform. In this study, the performance of a 3D adaptive filtering algorithm on a DSP is investigated. The performance is assessed by filtering a volume of size 512x256x128 voxels sampled at a pace of 10 MVoxels/sec with an Ultrasound 3D probe. Relative performance and power is addressed between a reference PC (Quad Core CPU) and a TMS320C6678 DSP from Texas Instruments.

The design of an adaptive predictive coder using a single-chip digital signal processor

NASA Astrophysics Data System (ADS)

Randolph, M. A.

1985-01-01

A speech coding processor architecture design study has been performed in which Texas Instruments TMS32010 has been selected from among three commercially available digital signal processing integrated circuits and evaluated in an implementation study of real-time Adaptive Predictive Coding (APC). The TMS32010 has been compared with AR&T Bell Laboratories DSP I and Nippon Electric Co. PD7720 and was found to be most suitable for a single chip implementation of APC. A preliminary design system based on TMS32010 has been performed, and several of the hardware and software design issues are discussed. Particular attention was paid to the design of an external memory controller which permits rapid sequential access of external RAM. As a result, it has been determined that a compact hardware implementation of the APC algorithm is feasible based of the TSM32010. Originator-supplied keywords include: vocoders, speech compression, adaptive predictive coding, digital signal processing microcomputers, speech processor architectures, and special purpose processor.

[Image processing system of visual prostheses based on digital signal processor DM642].

PubMed

Xie, Chengcheng; Lu, Yanyu; Gu, Yun; Wang, Jing; Chai, Xinyu

2011-09-01

This paper employed a DSP platform to create the real-time and portable image processing system, and introduced a series of commonly used algorithms for visual prostheses. The results of performance evaluation revealed that this platform could afford image processing algorithms to be executed in real time.

Hardware design and implementation of fast DOA estimation method based on multicore DSP

NASA Astrophysics Data System (ADS)

Guo, Rui; Zhao, Yingxiao; Zhang, Yue; Lin, Qianqiang; Chen, Zengping

2016-10-01

In this paper, we present a high-speed real-time signal processing hardware platform based on multicore digital signal processor (DSP). The real-time signal processing platform shows several excellent characteristics including high performance computing, low power consumption, large-capacity data storage and high speed data transmission, which make it able to meet the constraint of real-time direction of arrival (DOA) estimation. To reduce the high computational complexity of DOA estimation algorithm, a novel real-valued MUSIC estimator is used. The algorithm is decomposed into several independent steps and the time consumption of each step is counted. Based on the statistics of the time consumption, we present a new parallel processing strategy to distribute the task of DOA estimation to different cores of the real-time signal processing hardware platform. Experimental results demonstrate that the high processing capability of the signal processing platform meets the constraint of real-time direction of arrival (DOA) estimation.

Single-Scale Retinex Using Digital Signal Processors

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2005-01-01

The Retinex is an image enhancement algorithm that improves the brightness, contrast and sharpness of an image. It performs a non-linear spatial/spectral transform that provides simultaneous dynamic range compression and color constancy. It has been used for a wide variety of applications ranging from aviation safety to general purpose photography. Many potential applications require the use of Retinex processing at video frame rates. This is difficult to achieve with general purpose processors because the algorithm contains a large number of complex computations and data transfers. In addition, many of these applications also constrain the potential architectures to embedded processors to save power, weight and cost. Thus we have focused on digital signal processors (DSPs) and field programmable gate arrays (FPGAs) as potential solutions for real-time Retinex processing. In previous efforts we attained a 21 (full) frame per second (fps) processing rate for the single-scale monochromatic Retinex with a TMS320C6711 DSP operating at 150 MHz. This was achieved after several significant code improvements and optimizations. Since then we have migrated our design to the slightly more powerful TMS320C6713 DSP and the fixed point TMS320DM642 DSP. In this paper we briefly discuss the Retinex algorithm, the performance of the algorithm executing on the TMS320C6713 and the TMS320DM642, and compare the results with the TMS320C6711.

Real-Time Visualization of Tissue Ischemia

NASA Technical Reports Server (NTRS)

Bearman, Gregory H. (Inventor); Chrien, Thomas D. (Inventor); Eastwood, Michael L. (Inventor)

2000-01-01

A real-time display of tissue ischemia which comprises three CCD video cameras, each with a narrow bandwidth filter at the correct wavelength is discussed. The cameras simultaneously view an area of tissue suspected of having ischemic areas through beamsplitters. The output from each camera is adjusted to give the correct signal intensity for combining with, the others into an image for display. If necessary a digital signal processor (DSP) can implement algorithms for image enhancement prior to display. Current DSP engines are fast enough to give real-time display. Measurement at three, wavelengths, combined into a real-time Red-Green-Blue (RGB) video display with a digital signal processing (DSP) board to implement image algorithms, provides direct visualization of ischemic areas.

Noise generator for tinnitus treatment based on look-up tables

NASA Astrophysics Data System (ADS)

Uriz, Alejandro J.; Agüero, Pablo; Tulli, Juan C.; Castiñeira Moreira, Jorge; González, Esteban; Hidalgo, Roberto; Casadei, Manuel

2016-04-01

Treatment of tinnitus by means of masking sounds allows to obtain a significant improve of the quality of life of the individual that suffer that condition. In view of that, it is possible to develop noise synthesizers based on random number generators in digital signal processors (DSP), which are used in almost any digital hearing aid devices. DSP architecture have limitations to implement a pseudo random number generator, due to it, the noise statistics can be not as good as expectations. In this paper, a technique to generate additive white gaussian noise (AWGN) or other types of filtered noise using coefficients stored in program memory of the DSP is proposed. Also, an implementation of the technique is carried out on a dsPIC from Microchip®. Objective experiments and experimental measurements are performed to analyze the proposed technique.

Integrated optical 3D digital imaging based on DSP scheme

NASA Astrophysics Data System (ADS)

Wang, Xiaodong; Peng, Xiang; Gao, Bruce Z.

2008-03-01

We present a scheme of integrated optical 3-D digital imaging (IO3DI) based on digital signal processor (DSP), which can acquire range images independently without PC support. This scheme is based on a parallel hardware structure with aid of DSP and field programmable gate array (FPGA) to realize 3-D imaging. In this integrated scheme of 3-D imaging, the phase measurement profilometry is adopted. To realize the pipeline processing of the fringe projection, image acquisition and fringe pattern analysis, we present a multi-threads application program that is developed under the environment of DSP/BIOS RTOS (real-time operating system). Since RTOS provides a preemptive kernel and powerful configuration tool, with which we are able to achieve a real-time scheduling and synchronization. To accelerate automatic fringe analysis and phase unwrapping, we make use of the technique of software optimization. The proposed scheme can reach a performance of 39.5 f/s (frames per second), so it may well fit into real-time fringe-pattern analysis and can implement fast 3-D imaging. Experiment results are also presented to show the validity of proposed scheme.

Preliminary Study of Image Reconstruction Algorithm on a Digital Signal Processor

DTIC Science & Technology

2014-03-01

5.2 Comparison of CPU-GPU, CPU-FPGA, and CPU-DSP Designs The work for implementing VHDL description of the back-projection algorithm on a physical...FPGA was not complete. Hence, the DSP implementation results are compared with the simulated results for the VHDL design. Simulating VHDL provides an...rather than at the software level. Depending on an application’s characteristics, FPGA implementations can provide a significant performance

Fault-Tolerant, Radiation-Hard DSP

NASA Technical Reports Server (NTRS)

Czajkowski, David

2011-01-01

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

DSP Implementation of the Retinex Image Enhancement Algorithm

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2004-01-01

The Retinex is a general-purpose image enhancement algorithm that is used to produce good visual representations of scenes. It performs a non-linear spatial/spectral transform that synthesizes strong local contrast enhancement and color constancy. A real-time, video frame rate implementation of the Retinex is required to meet the needs of various potential users. Retinex processing contains a relatively large number of complex computations, thus to achieve real-time performance using current technologies requires specialized hardware and software. In this paper we discuss the design and development of a digital signal processor (DSP) implementation of the Retinex. The target processor is a Texas Instruments TMS320C6711 floating point DSP. NTSC video is captured using a dedicated frame-grabber card, Retinex processed, and displayed on a standard monitor. We discuss the optimizations used to achieve real-time performance of the Retinex and also describe our future plans on using alternative architectures.

An Intrinsically Digital Amplification Scheme for Hearing Aids

NASA Astrophysics Data System (ADS)

Blamey, Peter J.; Macfarlane, David S.; Steele, Brenton R.

2005-12-01

Results for linear and wide-dynamic range compression were compared with a new 64-channel digital amplification strategy in three separate studies. The new strategy addresses the requirements of the hearing aid user with efficient computations on an open-platform digital signal processor (DSP). The new amplification strategy is not modeled on prior analog strategies like compression and linear amplification, but uses statistical analysis of the signal to optimize the output dynamic range in each frequency band independently. Using the open-platform DSP processor also provided the opportunity for blind trial comparisons of the different processing schemes in BTE and ITE devices of a high commercial standard. The speech perception scores and questionnaire results show that it is possible to provide improved audibility for sound in many narrow frequency bands while simultaneously improving comfort, speech intelligibility in noise, and sound quality.

Signal Processing and Calibration of Continuous-Wave Focused CO2 Doppler Lidars for Atmospheric Backscatter Measurement

NASA Technical Reports Server (NTRS)

Rothermel, Jeffry; Chambers, Diana M.; Jarzembski, Maurice A.; Srivastava, Vandana; Bowdle, David A.; Jones, William D.

1996-01-01

Two continuous-wave(CW)focused C02 Doppler lidars (9.1 and 10.6 micrometers) were developed for airborne in situ aerosol backscatter measurements. The complex path of reliably calibrating these systems, with different signal processors, for accurate derivation of atmospheric backscatter coefficients is documented. Lidar calibration for absolute backscatter measurement for both lidars is based on range response over the lidar sample volume, not solely at focus. Both lidars were calibrated with a new technique using well-characterized aerosols as radiometric standard targets and related to conventional hard-target calibration. A digital signal processor (DSP), a surface acoustic and spectrum analyzer and manually tuned spectrum analyzer signal analyzers were used. The DSP signals were analyzed with an innovative method of correcting for systematic noise fluctuation; the noise statistics exhibit the chi-square distribution predicted by theory. System parametric studies and detailed calibration improved the accuracy of conversion from the measured signal-to-noise ratio to absolute backscatter. The minimum backscatter sensitivity is approximately 3 x 10(exp -12)/m/sr at 9.1 micrometers and approximately 9 x 10(exp -12)/m/sr at 10.6 micrometers. Sample measurements are shown for a flight over the remote Pacific Ocean in 1990 as part of the NASA Global Backscatter Experiment (GLOBE) survey missions, the first time to our knowledge that 9.1-10.6 micrometer lidar intercomparisons were made. Measurements at 9.1 micrometers, a potential wavelength for space-based lidar remote-sensing applications, are to our knowledge the first based on the rare isotope C-12 O(2)-18 gas.

Feasibility of an ultra-low power digital signal processor platform as a basis for a fully implantable brain-computer interface system.

PubMed

Wang, Po T; Gandasetiawan, Keulanna; McCrimmon, Colin M; Karimi-Bidhendi, Alireza; Liu, Charles Y; Heydari, Payam; Nenadic, Zoran; Do, An H

2016-08-01

A fully implantable brain-computer interface (BCI) can be a practical tool to restore independence to those affected by spinal cord injury. We envision that such a BCI system will invasively acquire brain signals (e.g. electrocorticogram) and translate them into control commands for external prostheses. The feasibility of such a system was tested by implementing its benchtop analogue, centered around a commercial, ultra-low power (ULP) digital signal processor (DSP, TMS320C5517, Texas Instruments). A suite of signal processing and BCI algorithms, including (de)multiplexing, Fast Fourier Transform, power spectral density, principal component analysis, linear discriminant analysis, Bayes rule, and finite state machine was implemented and tested in the DSP. The system's signal acquisition fidelity was tested and characterized by acquiring harmonic signals from a function generator. In addition, the BCI decoding performance was tested, first with signals from a function generator, and subsequently using human electroencephalogram (EEG) during eyes opening and closing task. On average, the system spent 322 ms to process and analyze 2 s of data. Crosstalk (<;-65 dB) and harmonic distortion (~1%) were minimal. Timing jitter averaged 49 μs per 1000 ms. The online BCI decoding accuracies were 100% for both function generator and EEG data. These results show that a complex BCI algorithm can be executed on an ULP DSP without compromising performance. This suggests that the proposed hardware platform may be used as a basis for future, fully implantable BCI systems.

A customizable system for real-time image processing using the Blackfin DSProcessor and the MicroC/OS-II real-time kernel

NASA Astrophysics Data System (ADS)

Coffey, Stephen; Connell, Joseph

2005-06-01

This paper presents a development platform for real-time image processing based on the ADSP-BF533 Blackfin processor and the MicroC/OS-II real-time operating system (RTOS). MicroC/OS-II is a completely portable, ROMable, pre-emptive, real-time kernel. The Blackfin Digital Signal Processors (DSPs), incorporating the Analog Devices/Intel Micro Signal Architecture (MSA), are a broad family of 16-bit fixed-point products with a dual Multiply Accumulate (MAC) core. In addition, they have a rich instruction set with variable instruction length and both DSP and MCU functionality thus making them ideal for media based applications. Using the MicroC/OS-II for task scheduling and management, the proposed system can capture and process raw RGB data from any standard 8-bit greyscale image sensor in soft real-time and then display the processed result using a simple PC graphical user interface (GUI). Additionally, the GUI allows configuration of the image capture rate and the system and core DSP clock rates thereby allowing connectivity to a selection of image sensors and memory devices. The GUI also allows selection from a set of image processing algorithms based in the embedded operating system.

Servo Platform Circuit Design of Pendulous Gyroscope Based on DSP

NASA Astrophysics Data System (ADS)

Tan, Lilong; Wang, Pengcheng; Zhong, Qiyuan; Zhang, Cui; Liu, Yunfei

2018-03-01

In order to solve the problem when a certain type of pendulous gyroscope in the initial installation deviation more than 40 degrees, that the servo platform can not be up to the speed of the gyroscope in the rough north seeking phase. This paper takes the digital signal processor TMS320F28027 as the core, uses incremental digital PID algorithm, carries out the circuit design of the servo platform. Firstly, the hardware circuit is divided into three parts: DSP minimum system, motor driving circuit and signal processing circuit, then the mathematical model of incremental digital PID algorithm is established, based on the model, writes the PID control program in CCS3.3, finally, the servo motor tracking control experiment is carried out, it shows that the design can significantly improve the tracking ability of the servo platform, and the design has good engineering practice.

Automatic efficiency optimization of an axial compressor with adjustable inlet guide vanes

NASA Astrophysics Data System (ADS)

Li, Jichao; Lin, Feng; Nie, Chaoqun; Chen, Jingyi

2012-04-01

The inlet attack angle of rotor blade reasonably can be adjusted with the change of the stagger angle of inlet guide vane (IGV); so the efficiency of each condition will be affected. For the purpose to improve the efficiency, the DSP (Digital Signal Processor) controller is designed to adjust the stagger angle of IGV automatically in order to optimize the efficiency at any operating condition. The A/D signal collection includes inlet static pressure, outlet static pressure, outlet total pressure, rotor speed and torque signal, the efficiency can be calculated in the DSP, and the angle signal for the stepping motor which control the IGV will be sent out from the D/A. Experimental investigations are performed in a three-stage, low-speed axial compressor with variable inlet guide vanes. It is demonstrated that the DSP designed can well adjust the stagger angle of IGV online, the efficiency under different conditions can be optimized. This establishment of DSP online adjustment scheme may provide a practical solution for improving performance of multi-stage axial flow compressor when its operating condition is varied.

Universal sensor interface module (USIM)

NASA Astrophysics Data System (ADS)

King, Don; Torres, A.; Wynn, John

1999-01-01

A universal sensor interface model (USIM) is being developed by the Raytheon-TI Systems Company for use with fields of unattended distributed sensors. In its production configuration, the USIM will be a multichip module consisting of a set of common modules. The common module USIM set consists of (1) a sensor adapter interface (SAI) module, (2) digital signal processor (DSP) and associated memory module, and (3) a RF transceiver model. The multispectral sensor interface is designed around a low-power A/D converted, whose input/output interface consists of: -8 buffered, sampled inputs from various devices including environmental, acoustic seismic and magnetic sensors. The eight sensor inputs are each high-impedance, low- capacitance, differential amplifiers. The inputs are ideally suited for interface with discrete or MEMS sensors, since the differential input will allow direct connection with high-impedance bridge sensors and capacitance voltage sources. Each amplifier is connected to a 22-bit (Delta) (Sigma) A/D converter to enable simultaneous samples. The low power (Delta) (Sigma) converter provides 22-bit resolution at sample frequencies up to 142 hertz (used for magnetic sensors) and 16-bit resolution at frequencies up to 1168 hertz (used for acoustic and seismic sensors). The video interface module is based around the TMS320C5410 DSP. It can provide sensor array addressing, video data input, data calibration and correction. The processor module is based upon a MPC555. It will be used for mode control, synchronization of complex sensors, sensor signal processing, array processing, target classification and tracking. Many functions of the A/D, DSP and transceiver can be powered down by using variable clock speeds under software command or chip power switches. They can be returned to intermediate or full operation by DSP command. Power management may be based on the USIM's internal timer, command from the USIM transceiver, or by sleep mode processing management. The low power detection mode is implemented by monitoring any of the sensor analog outputs at lower sample rates for detection over a software controllable threshold.

Hardware description ADSP-21020 40-bit floating point DSP as designed in a remotely controlled digital CW Doppler radar

NASA Astrophysics Data System (ADS)

Morrison, R. E.; Robinson, S. H.

A continuous wave Doppler radar system has been designed which is portable, easily deployed, and remotely controlled. The heart of this system is a DSP/control board using Analog Devices ADSP-21020 40-bit floating point digital signal processor (DSP) microprocessor. Two 18-bit audio A/D converters provide digital input to the DSP/controller board for near real time target detection. Program memory for the DSP is dual ported with an Intel 87C51 microcontroller allowing DSP code to be up-loaded or down-loaded from a central controlling computer. The 87C51 provides overall system control for the remote radar and includes a time-of-day/day-of-year real time clock, system identification (ID) switches, and input/output (I/O) expansion by an Intel 82C55 I/O expander.

Design and evaluation of an architecture for a digital signal processor for instrumentation applications

NASA Astrophysics Data System (ADS)

Fellman, Ronald D.; Kaneshiro, Ronald T.; Konstantinides, Konstantinos

1990-03-01

The authors present the design and evaluation of an architecture for a monolithic, programmable, floating-point digital signal processor (DSP) for instrumentation applications. An investigation of the most commonly used algorithms in instrumentation led to a design that satisfies the requirements for high computational and I/O (input/output) throughput. In the arithmetic unit, a 16- x 16-bit multiplier and a 32-bit accumulator provide the capability for single-cycle multiply/accumulate operations, and three format adjusters automatically adjust the data format for increased accuracy and dynamic range. An on-chip I/O unit is capable of handling data block transfers through a direct memory access port and real-time data streams through a pair of parallel I/O ports. I/O operations and program execution are performed in parallel. In addition, the processor includes two data memories with independent addressing units, a microsequencer with instruction RAM, and multiplexers for internal data redirection. The authors also present the structure and implementation of a design environment suitable for the algorithmic, behavioral, and timing simulation of a complete DSP system. Various benchmarking results are reported.

PCI-based WILDFIRE reconfigurable computing engines

NASA Astrophysics Data System (ADS)

Fross, Bradley K.; Donaldson, Robert L.; Palmer, Douglas J.

1996-10-01

WILDFORCE is the first PCI-based custom reconfigurable computer that is based on the Splash 2 technology transferred from the National Security Agency and the Institute for Defense Analyses, Supercomputing Research Center (SRC). The WILDFORCE architecture has many of the features of the WILDFIRE computer, such as field- programmable gate array (FPGA) based processing elements, linear array and crossbar interconnection, and high- performance memory and I/O subsystems. New features introduced in the PCI-based WILDFIRE systems include memory/processor options that can be added to any processing element. These options include static and dynamic memory, digital signal processors (DSPs), FPGAs, and microprocessors. In addition to memory/processor options, many different application specific connectors can be used to extend the I/O capabilities of the system, including systolic I/O, camera input and video display output. This paper also discusses how this new PCI-based reconfigurable computing engine is used for rapid-prototyping, real-time video processing and other DSP applications.

Optimization of image processing algorithms on mobile platforms

NASA Astrophysics Data System (ADS)

Poudel, Pramod; Shirvaikar, Mukul

2011-03-01

This work presents a technique to optimize popular image processing algorithms on mobile platforms such as cell phones, net-books and personal digital assistants (PDAs). The increasing demand for video applications like context-aware computing on mobile embedded systems requires the use of computationally intensive image processing algorithms. The system engineer has a mandate to optimize them so as to meet real-time deadlines. A methodology to take advantage of the asymmetric dual-core processor, which includes an ARM and a DSP core supported by shared memory, is presented with implementation details. The target platform chosen is the popular OMAP 3530 processor for embedded media systems. It has an asymmetric dual-core architecture with an ARM Cortex-A8 and a TMS320C64x Digital Signal Processor (DSP). The development platform was the BeagleBoard with 256 MB of NAND RAM and 256 MB SDRAM memory. The basic image correlation algorithm is chosen for benchmarking as it finds widespread application for various template matching tasks such as face-recognition. The basic algorithm prototypes conform to OpenCV, a popular computer vision library. OpenCV algorithms can be easily ported to the ARM core which runs a popular operating system such as Linux or Windows CE. However, the DSP is architecturally more efficient at handling DFT algorithms. The algorithms are tested on a variety of images and performance results are presented measuring the speedup obtained due to dual-core implementation. A major advantage of this approach is that it allows the ARM processor to perform important real-time tasks, while the DSP addresses performance-hungry algorithms.

CORDIC-based digital signal processing (DSP) element for adaptive signal processing

NASA Astrophysics Data System (ADS)

Bolstad, Gregory D.; Neeld, Kenneth B.

1995-04-01

The High Performance Adaptive Weight Computation (HAWC) processing element is a CORDIC based application specific DSP element that, when connected in a linear array, can perform extremely high throughput (100s of GFLOPS) matrix arithmetic operations on linear systems of equations in real time. In particular, it very efficiently performs the numerically intense computation of optimal least squares solutions for large, over-determined linear systems. Most techniques for computing solutions to these types of problems have used either a hard-wired, non-programmable systolic array approach, or more commonly, programmable DSP or microprocessor approaches. The custom logic methods can be efficient, but are generally inflexible. Approaches using multiple programmable generic DSP devices are very flexible, but suffer from poor efficiency and high computation latencies, primarily due to the large number of DSP devices that must be utilized to achieve the necessary arithmetic throughput. The HAWC processor is implemented as a highly optimized systolic array, yet retains some of the flexibility of a programmable data-flow system, allowing efficient implementation of algorithm variations. This provides flexible matrix processing capabilities that are one to three orders of magnitude less expensive and more dense than the current state of the art, and more importantly, allows a realizable solution to matrix processing problems that were previously considered impractical to physically implement. HAWC has direct applications in RADAR, SONAR, communications, and image processing, as well as in many other types of systems.

Adaptive Signal Processing Testbed: VME-based DSP board market survey

NASA Astrophysics Data System (ADS)

Ingram, Rick E.

1992-04-01

The Adaptive Signal Processing Testbed (ASPT) is a real-time multiprocessor system utilizing digital signal processor technology on VMEbus based printed circuit boards installed on a Sun workstation. The ASPT has specific requirements, particularly as regards to the signal excision application, with respect to interfacing with current and planned data generation equipment, processing of the data, storage to disk of final and intermediate results, and the development tools for applications development and integration into the overall EW/COM computing environment. A prototype ASPT was implemented using three VME-C-30 boards from Applied Silicon. Experience gained during the prototype development led to the conclusions that interprocessor communications capability is the most significant contributor to overall ASPT performance. In addition, the host involvement should be minimized. Boards using different processors were evaluated with respect to the ASPT system requirements, pricing, and availability. Specific recommendations based on various priorities are made as well as recommendations concerning the integration and interaction of various tools developed during the prototype implementation.

Achieving supercomputer performance for neural net simulation with an array of digital signal processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muller, U.A.; Baumle, B.; Kohler, P.

1992-10-01

Music, a DSP-based system with a parallel distributed-memory architecture, provides enormous computing power yet retains the flexibility of a general-purpose computer. Reaching a peak performance of 2.7 Gflops at a significantly lower cost, power consumption, and space requirement than conventional supercomputers, Music is well suited to computationally intensive applications such as neural network simulation. 12 refs., 9 figs., 2 tabs.

The research and application of multi-biometric acquisition embedded system

NASA Astrophysics Data System (ADS)

Deng, Shichao; Liu, Tiegen; Guo, Jingjing; Li, Xiuyan

2009-11-01

The identification technology based on multi-biometric can greatly improve the applicability, reliability and antifalsification. This paper presents a multi-biometric system bases on embedded system, which includes: three capture daughter boards are applied to obtain different biometric: one each for fingerprint, iris and vein of the back of hand; FPGA (Field Programmable Gate Array) is designed as coprocessor, which uses to configure three daughter boards on request and provides data path between DSP (digital signal processor) and daughter boards; DSP is the master processor and its functions include: control the biometric information acquisition, extracts feature as required and responsible for compare the results with the local database or data server through network communication. The advantages of this system were it can acquire three different biometric in real time, extracts complexity feature flexibly in different biometrics' raw data according to different purposes and arithmetic and network interface on the core-board will be the solution of big data scale. Because this embedded system has high stability, reliability, flexibility and fit for different data scale, it can satisfy the demand of multi-biometric recognition.

Automatic calibration system for analog instruments based on DSP and CCD sensor

NASA Astrophysics Data System (ADS)

Lan, Jinhui; Wei, Xiangqin; Bai, Zhenlong

2008-12-01

Currently, the calibration work of analog measurement instruments is mainly completed by manual and there are many problems waiting for being solved. In this paper, an automatic calibration system (ACS) based on Digital Signal Processor (DSP) and Charge Coupled Device (CCD) sensor is developed and a real-time calibration algorithm is presented. In the ACS, TI DM643 DSP processes the data received by CCD sensor and the outcome is displayed on Liquid Crystal Display (LCD) screen. For the algorithm, pointer region is firstly extracted for improving calibration speed. And then a math model of the pointer is built to thin the pointer and determine the instrument's reading. Through numbers of experiments, the time of once reading is no more than 20 milliseconds while it needs several seconds if it is done manually. At the same time, the error of the instrument's reading satisfies the request of the instruments. It is proven that the automatic calibration system can effectively accomplish the calibration work of the analog measurement instruments.

Spacewire on Earth orbiting scatterometers

NASA Technical Reports Server (NTRS)

Bachmann, Alex; Lang, Minh; Lux, James; Steffke, Richard

2002-01-01

The need for a high speed, reliable and easy to implement communication link has led to the development of a space flight oriented version of IEEE 1355 called SpaceWire. SpaceWire is based on high-speed (200 Mbps) serial point-to-point links using Low Voltage Differential Signaling (LVDS). SpaceWIre has provisions for routing messages between a large network of processors, using wormhole routing for low overhead and latency. {additionally, there are available space qualified hybrids, which provide the Link layer to the user's bus}. A test bed of multiple digital signal processor breadboards, demonstrating the ability to meet signal processing requirements for an orbiting scatterometer has been implemented using three Astrium MCM-DSPs, each breadboard consists of a Multi Chip Module (MCM) that combines a space qualified Digital Signal Processor and peripherals, including IEEE-1355 links. With the addition of appropriate physical layer interfaces and software on the DSP, the SpaceWire link is used to communicate between processors on the test bed, e.g. sending timing references, commands, status, and science data among the processors. Results are presented on development issues surrounding the use of SpaceWire in this environment, from physical layer implementation (cables, connectors, LVDS drivers) to diagnostic tools, driver firmware, and development methodology. The tools, methods, and hardware, software challenges and preliminary performance are investigated and discussed.

A real-time tracking system of infrared dim and small target based on FPGA and DSP

NASA Astrophysics Data System (ADS)

Rong, Sheng-hui; Zhou, Hui-xin; Qin, Han-lin; Wang, Bing-jian; Qian, Kun

2014-11-01

A core technology in the infrared warning system is the detection tracking of dim and small targets with complicated background. Consequently, running the detection algorithm on the hardware platform has highly practical value in the military field. In this paper, a real-time detection tracking system of infrared dim and small target which is used FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) as the core was designed and the corresponding detection tracking algorithm and the signal flow is elaborated. At the first stage, the FPGA obtain the infrared image sequence from the sensor, then it suppresses background clutter by mathematical morphology method and enhances the target intensity by Laplacian of Gaussian operator. At the second stage, the DSP obtain both the original image and the filtered image form the FPGA via the video port. Then it segments the target from the filtered image by an adaptive threshold segmentation method and gets rid of false target by pipeline filter. Experimental results show that our system can achieve higher detection rate and lower false alarm rate.

Realization of a single image haze removal system based on DaVinci DM6467T processor

NASA Astrophysics Data System (ADS)

Liu, Zhuang

2014-10-01

Video monitoring system (VMS) has been extensively applied in domains of target recognition, traffic management, remote sensing, auto navigation and national defence. However the VMS has a strong dependence on the weather, for instance, in foggy weather, the quality of images received by the VMS are distinct degraded and the effective range of VMS is also decreased. All in all, the VMS performs terribly in bad weather. Thus the research of fog degraded images enhancement has very high theoretical and practical application value. A design scheme of a fog degraded images enhancement system based on the TI DaVinci processor is presented in this paper. The main function of the referred system is to extract and digital cameras capture images and execute image enhancement processing to obtain a clear image. The processor used in this system is the dual core TI DaVinci DM6467T - ARM@500MHz+DSP@1GH. A MontaVista Linux operating system is running on the ARM subsystem which handles I/O and application processing. The DSP handles signal processing and the results are available to the ARM subsystem in shared memory.The system benefits from the DaVinci processor so that, with lower power cost and smaller volume, it provides the equivalent image processing capability of a X86 computer. The outcome shows that the system in this paper can process images at 25 frames per second on D1 resolution.

The research of laser marking control technology

NASA Astrophysics Data System (ADS)

Zhang, Qiue; Zhang, Rong

2009-08-01

In the area of Laser marking, the general control method is insert control card to computer's mother board, it can not support hot swap, it is difficult to assemble or it. Moreover, the one marking system must to equip one computer. In the system marking, the computer can not to do the other things except to transmit marking digital information. Otherwise it can affect marking precision. Based on traditional control methods existed some problems, introduced marking graphic editing and digital processing by the computer finish, high-speed digital signal processor (DSP) control marking the whole process. The laser marking controller is mainly contain DSP2812, digital memorizer, DAC (digital analog converting) transform unit circuit, USB interface control circuit, man-machine interface circuit, and other logic control circuit. Download the marking information which is processed by computer to U disk, DSP read the information by USB interface on time, then processing it, adopt the DSP inter timer control the marking time sequence, output the scanner control signal by D/A parts. Apply the technology can realize marking offline, thereby reduce the product cost, increase the product efficiency. The system have good effect in actual unit markings, the marking speed is more quickly than PCI control card to 20 percent. It has application value in practicality.

Compact lidar system using laser diode, binary continuous wave power modulation, and an avalanche photodiode-based receiver controlled by a digital signal processor

NASA Astrophysics Data System (ADS)

Ardanuy, Antoni; Comerón, Adolfo

2018-04-01

We analyze the practical limits of a lidar system based on the use of a laser diode, random binary continuous wave power modulation, and an avalanche photodiode (APD)-based photereceiver, combined with the control and computing power of the digital signal processors (DSP) currently available. The target is to design a compact portable lidar system made all in semiconductor technology, with a low-power demand and an easy configuration of the system, allowing change in some of its features through software. Unlike many prior works, we emphasize the use of APDs instead of photomultiplier tubes to detect the return signal and the application of the system to measure not only hard targets, but also medium-range aerosols and clouds. We have developed an experimental prototype to evaluate the behavior of the system under different environmental conditions. Experimental results provided by the prototype are presented and discussed.

Very low cost real time histogram-based contrast enhancer utilizing fixed-point DSP processing

NASA Astrophysics Data System (ADS)

McCaffrey, Nathaniel J.; Pantuso, Francis P.

1998-03-01

A real time contrast enhancement system utilizing histogram- based algorithms has been developed to operate on standard composite video signals. This low-cost DSP based system is designed with fixed-point algorithms and an off-chip look up table (LUT) to reduce the cost considerably over other contemporary approaches. This paper describes several real- time contrast enhancing systems advanced at the Sarnoff Corporation for high-speed visible and infrared cameras. The fixed-point enhancer was derived from these high performance cameras. The enhancer digitizes analog video and spatially subsamples the stream to qualify the scene's luminance. Simultaneously, the video is streamed through a LUT that has been programmed with the previous calculation. Reducing division operations by subsampling reduces calculation- cycles and also allows the processor to be used with cameras of nominal resolutions. All values are written to the LUT during blanking so no frames are lost. The enhancer measures 13 cm X 6.4 cm X 3.2 cm, operates off 9 VAC and consumes 12 W. This processor is small and inexpensive enough to be mounted with field deployed security cameras and can be used for surveillance, video forensics and real- time medical imaging.

MoNET: media over net gateway processor for next-generation network

NASA Astrophysics Data System (ADS)

Elabd, Hammam; Sundar, Rangarajan; Dedes, John

2001-12-01

MoNETTM (Media over Net) SX000 product family is designed using a scalable voice, video and packet-processing platform to address applications with channel densities from few voice channels to four OC3 per card. This platform is developed for bridging public circuit-switched network to the next generation packet telephony and data network. The platform consists of a DSP farm, RISC processors and interface modules. DSP farm is required to execute voice compression, image compression and line echo cancellation algorithms for large number of voice, video, fax, and modem or data channels. RISC CPUs are used for performing various packetizations based on RTP, UDP/IP and ATM encapsulations. In addition, RISC CPUs also participate in the DSP farm load management and communication with the host and other MoP devices. The MoNETTM S1000 communications device is designed for voice processing and for bridging TDM to ATM and IP packet networks. The S1000 consists of the DSP farm based on Carmel DSP core and 32-bit RISC CPU, along with Ethernet, Utopia, PCI, and TDM interfaces. In this paper, we will describe the VoIP infrastructure, building blocks of the S500, S1000 and S3000 devices, algorithms executed on these device and associated channel densities, detailed DSP architecture, memory architecture, data flow and scheduling.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Interband cascade laser-based ppbv-level mid-infrared methane detection using two digital lock-in amplifier schemes

NASA Astrophysics Data System (ADS)

Song, Fang; Zheng, Chuantao; Yu, Di; Zhou, Yanwen; Yan, Wanhong; Ye, Weilin; Zhang, Yu; Wang, Yiding; Tittel, Frank K.

2018-03-01

A parts-per-billion in volume (ppbv) level mid-infrared methane (CH4) sensor system was demonstrated using second-harmonic wavelength modulation spectroscopy (2 f-WMS). A 3291 nm interband cascade laser (ICL) and a multi-pass gas cell (MPGC) with a 16 m optical path length were adopted in the reported sensor system. Two digital lock-in amplifier (DLIA) schemes, a digital signal processor (DSP)-based DLIA and a LabVIEW-based DLIA, were used for harmonic signal extraction. A limit of detection (LoD) of 13.07 ppbv with an averaging time of 2 s was achieved using the DSP-based DLIA and a LoD of 5.84 ppbv was obtained using the LabVIEW-based DLIA with the same averaging time. A rise time of 0→2 parts-per-million in volume (ppmv) and fall time of 2→0 ppmv were observed. Outdoor atmospheric CH4 concentration measurements were carried out to evaluate the sensor performance using the two DLIA schemes.

A portable detection instrument based on DSP for beef marbling

NASA Astrophysics Data System (ADS)

Zhou, Tong; Peng, Yankun

2014-05-01

Beef marbling is one of the most important indices to assess beef quality. Beef marbling is graded by the measurement of the fat distribution density in the rib-eye region. However quality grades of beef in most of the beef slaughtering houses and businesses depend on trainees using their visual senses or comparing the beef slice to the Chinese standard sample cards. Manual grading demands not only great labor but it also lacks objectivity and accuracy. Aiming at the necessity of beef slaughtering houses and businesses, a beef marbling detection instrument was designed. The instrument employs Charge-coupled Device (CCD) imaging techniques, digital image processing, Digital Signal Processor (DSP) control and processing techniques and Liquid Crystal Display (LCD) screen display techniques. The TMS320DM642 digital signal processor of Texas Instruments (TI) is the core that combines high-speed data processing capabilities and real-time processing features. All processes such as image acquisition, data transmission, image processing algorithms and display were implemented on this instrument for a quick, efficient, and non-invasive detection of beef marbling. Structure of the system, working principle, hardware and software are introduced in detail. The device is compact and easy to transport. The instrument can determine the grade of beef marbling reliably and correctly.

High-Speed Current dq PI Controller for Vector Controlled PMSM Drive

PubMed Central

Reaz, Mamun Bin Ibne; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era. PMID:24574913

System on a chip with MPEG-4 capability

NASA Astrophysics Data System (ADS)

Yassa, Fathy; Schonfeld, Dan

2002-12-01

Current products supporting video communication applications rely on existing computer architectures. RISC processors have been used successfully in numerous applications over several decades. DSP processors have become ubiquitous in signal processing and communication applications. Real-time applications such as speech processing in cellular telephony rely extensively on the computational power of these processors. Video processors designed to implement the computationally intensive codec operations have also been used to address the high demands of video communication applications (e.g., cable set-top boxes and DVDs). This paper presents an overview of a system-on-chip (SOC) architecture used for real-time video in wireless communication applications. The SOC specifications answer to the system requirements imposed by the application environment. A CAM-based video processor is used to accelerate data intensive video compression tasks such as motion estimations and filtering. Other components are dedicated to system level data processing and audio processing. A rich set of I/Os allows the SOC to communicate with other system components such as baseband and memory subsystems.

Encoder fault analysis system based on Moire fringe error signal

NASA Astrophysics Data System (ADS)

Gao, Xu; Chen, Wei; Wan, Qiu-hua; Lu, Xin-ran; Xie, Chun-yu

2018-02-01

Aiming at the problem of any fault and wrong code in the practical application of photoelectric shaft encoder, a fast and accurate encoder fault analysis system is researched from the aspect of Moire fringe photoelectric signal processing. DSP28335 is selected as the core processor and high speed serial A/D converter acquisition card is used. And temperature measuring circuit using AD7420 is designed. Discrete data of Moire fringe error signal is collected at different temperatures and it is sent to the host computer through wireless transmission. The error signal quality index and fault type is displayed on the host computer based on the error signal identification method. The error signal quality can be used to diagnosis the state of error code through the human-machine interface.

Long-Wavelength Beam Steerer Based on a Micro-Electromechanical Mirror

PubMed Central

Kos, Anthony B; Gerecht, Eyal

2013-01-01

Commercially available mirrors for scanning long-wavelength beams are too large for high-speed imaging. There is a need for a smaller, more agile pointing apparatus to provide images in seconds, not minutes or hours. A fast long-wavelength beam steerer uses a commercial micro-electro-mechanical system (MEMS) mirror controlled by a high-performance digital signal processor (DSP). The DSP allows high-speed raster scanning of the incident radiation, which is focused to a small waist onto the 9mm2, gold-coated, MEMS mirror surface, while simultaneously acquiring an undistorted, high spatial-resolution image of an object. The beam steerer hardware, software and performance are described. The system can also serve as a miniaturized, high-performance long-wavelength beam chopper for lock-in detection. PMID:26401426

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

Low-cost, digital lock-in module with external reference for coating glass transmission/reflection spectrophotometer

NASA Astrophysics Data System (ADS)

Alonso, R.; Villuendas, F.; Borja, J.; Barragán, L. A.; Salinas, I.

2003-05-01

A versatile, low-cost, digital signal processor (DSP) based lock-in module with external reference is described. This module is used to implement an industrial spectrophotometer for measuring spectral transmission and reflection of automotive and architectonic coating glasses over the ultraviolet, visible and near-infrared wavelength range. The light beams are modulated with an optical chopper. A digital phase-locked loop (DPLL) is used to lock the lock-in to the chop frequency. The lock-in rejects the ambient radiation and permits the spectrophotometer to work in the presence of ambient light. The algorithm that implements the dual lock-in and the DPLL in the DSP56002 evaluation module from Motorola is described. The use of a DSP allows implementation of the lock-in and DPLL by software, which gives flexibility and programmability to the system. Lock-in module cost, under 300 euro, is an important parameter taking into account that two modules are used in the system. Besides, the algorithms implemented in this DSP can be directly implemented in the latest DSP generations. The DPLL performance and the spectrophotometer are characterized. Capture and lock DPLL ranges have been measured and checked to be greater than the chop frequency drifts. The lock-in measured frequency response shows that the lock-in performs as theoretically predicted.

Segmentation of financial seals and its implementation on a DSP-based system

NASA Astrophysics Data System (ADS)

He, Jin; Liu, Tiegen; Guo, Jingjing; Zhang, Hao

2009-11-01

Automatic seal imprint identification is an important part of modern financial security. Accurate segmentation is the basis of correct identification. In this paper, a DSP (digital signal processor) based identification system was designed, and an adaptive algorithm was proposed to extract binary seal images from financial instruments. As the kernel of the identification system, a DSP chip of TMS320DM642 was used to implement image processing, controlling and coordinating works of each system module. The proposed algorithm consisted of three stages, including extraction of grayscale seal image, denoising and binarization. A grayscale seal image was extracted by color transform from a financial instrument image. Adaptive morphological operations were used to highlight details of the extracted grayscale seal image and smooth the background. After median filter for noise elimination, the filtered seal image was binarized by Otsu's method. The algorithm was developed based on the DSP development environment CCS and real-time operation system DSP/BIOS. To simplify the implementation of the proposed algorithm, the calibration of white balance and the coarse positioning of the seal imprint were implemented by TMS320DM642 controlling image acquisition. IMGLIB of TMS320DM642 was used for the efficiency improvement. The experiment result showed that financial seal imprints, even with intricate and dense strokes can be correctly segmented by the proposed algorithm. Adhesion and incompleteness distortions in the segmentation results were reduced, even when the original seal imprint had a poor quality.

Design of an anti-Rician-fading modem for mobile satellite communication systems

NASA Technical Reports Server (NTRS)

Kojima, Toshiharu; Ishizu, Fumio; Miyake, Makoto; Murakami, Keishi; Fujino, Tadashi

1995-01-01

To design a demodulator applicable to mobile satellite communication systems using differential phase shift keying modulation, we have developed key technologies including an anti-Rician-fading demodulation scheme, an initial acquisition scheme, automatic gain control (AGC), automatic frequency control (AFC), and bit timing recovery (BTR). Using these technologies, we have developed one-chip digital signal processor (DSP) modem for mobile terminal, which is compact, of light weight, and of low power consumption. Results of performance test show that the developed DSP modem achieves good performance in terms of bit error ratio in mobile satellite communication environment, i.e., Rician fading channel. It is also shown that the initial acquisition scheme acquires received signal rapidly even if the carrier-to-noise power ratio (CNR) of the received signal is considerably low.

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate ( C'' or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability bymore » using DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate (``C`` or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability by usingmore » DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Feasibility Study on a Portable Field Pest Classification System Design Based on DSP and 3G Wireless Communication Technology

PubMed Central

Han, Ruizhen; He, Yong; Liu, Fei

2012-01-01

This paper presents a feasibility study on a real-time in field pest classification system design based on Blackfin DSP and 3G wireless communication technology. This prototype system is composed of remote on-line classification platform (ROCP), which uses a digital signal processor (DSP) as a core CPU, and a host control platform (HCP). The ROCP is in charge of acquiring the pest image, extracting image features and detecting the class of pest using an Artificial Neural Network (ANN) classifier. It sends the image data, which is encoded using JPEG 2000 in DSP, to the HCP through the 3G network at the same time for further identification. The image transmission and communication are accomplished using 3G technology. Our system transmits the data via a commercial base station. The system can work properly based on the effective coverage of base stations, no matter the distance from the ROCP to the HCP. In the HCP, the image data is decoded and the pest image displayed in real-time for further identification. Authentication and performance tests of the prototype system were conducted. The authentication test showed that the image data were transmitted correctly. Based on the performance test results on six classes of pests, the average accuracy is 82%. Considering the different live pests’ pose and different field lighting conditions, the result is satisfactory. The proposed technique is well suited for implementation in field pest classification on-line for precision agriculture. PMID:22736996

Feasibility study on a portable field pest classification system design based on DSP and 3G wireless communication technology.

PubMed

Han, Ruizhen; He, Yong; Liu, Fei

2012-01-01

This paper presents a feasibility study on a real-time in field pest classification system design based on Blackfin DSP and 3G wireless communication technology. This prototype system is composed of remote on-line classification platform (ROCP), which uses a digital signal processor (DSP) as a core CPU, and a host control platform (HCP). The ROCP is in charge of acquiring the pest image, extracting image features and detecting the class of pest using an Artificial Neural Network (ANN) classifier. It sends the image data, which is encoded using JPEG 2000 in DSP, to the HCP through the 3G network at the same time for further identification. The image transmission and communication are accomplished using 3G technology. Our system transmits the data via a commercial base station. The system can work properly based on the effective coverage of base stations, no matter the distance from the ROCP to the HCP. In the HCP, the image data is decoded and the pest image displayed in real-time for further identification. Authentication and performance tests of the prototype system were conducted. The authentication test showed that the image data were transmitted correctly. Based on the performance test results on six classes of pests, the average accuracy is 82%. Considering the different live pests' pose and different field lighting conditions, the result is satisfactory. The proposed technique is well suited for implementation in field pest classification on-line for precision agriculture.

High Speed A/D DSP Interface for Carrier Doppler Tracking

NASA Technical Reports Server (NTRS)

Baggett, Timothy

1998-01-01

As on-board satellite systems continue to increase in ability to perform self diagnostic checks, it will become more important for satellites to initiate ground communications contact. Currently, the NASA Space Network requires users to pre-arranged times for satellite communications links through the Tracking and Data Relay Satellite (TDRS). One of the challenges in implementing an on-demand access protocol into the Space Network, is the fact that a low Earth orbiting (LEO) satellite's communications will be subject to a doppler shift which is outside the capability of the NASA ground station to lock onto. In a prearranged system, the satellite's doppler is known a priori, and the ground station is able to lock onto the satellite's signal. This paper describes the development of a high speed analog to digital interface into a Digital Signal Processor (DSP). This system will be used for identifying the doppler shift of a LEO satellite through the Space Network, and aiding the ground station equipment in locking onto the signal. Although this interface is specific to one application, it can be used as a basis for interfacing other devices with a DSP.

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery

PubMed Central

Qi, Baogui; Zhuang, Yin; Chen, He; Chen, Liang

2018-01-01

With the development of remote-sensing technology, optical remote-sensing imagery processing has played an important role in many application fields, such as geological exploration and natural disaster prevention. However, relative radiation correction and geometric correction are key steps in preprocessing because raw image data without preprocessing will cause poor performance during application. Traditionally, remote-sensing data are downlinked to the ground station, preprocessed, and distributed to users. This process generates long delays, which is a major bottleneck in real-time applications for remote-sensing data. Therefore, on-board, real-time image preprocessing is greatly desired. In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed. First, a hierarchical optimization and mapping method is proposed to realize the preprocessing algorithm in a hardware structure, which can effectively reduce the computation burden of on-board processing. Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing. The experimental results demonstrate the potential application of our system to an on-board processor, for which resources and power consumption are limited. PMID:29693585

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery.

PubMed

Qi, Baogui; Shi, Hao; Zhuang, Yin; Chen, He; Chen, Liang

2018-04-25

With the development of remote-sensing technology, optical remote-sensing imagery processing has played an important role in many application fields, such as geological exploration and natural disaster prevention. However, relative radiation correction and geometric correction are key steps in preprocessing because raw image data without preprocessing will cause poor performance during application. Traditionally, remote-sensing data are downlinked to the ground station, preprocessed, and distributed to users. This process generates long delays, which is a major bottleneck in real-time applications for remote-sensing data. Therefore, on-board, real-time image preprocessing is greatly desired. In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed. First, a hierarchical optimization and mapping method is proposed to realize the preprocessing algorithm in a hardware structure, which can effectively reduce the computation burden of on-board processing. Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing. The experimental results demonstrate the potential application of our system to an on-board processor, for which resources and power consumption are limited.

A DSP-based neural network non-uniformity correction algorithm for IRFPA

NASA Astrophysics Data System (ADS)

Liu, Chong-liang; Jin, Wei-qi; Cao, Yang; Liu, Xiu

2009-07-01

An effective neural network non-uniformity correction (NUC) algorithm based on DSP is proposed in this paper. The non-uniform response in infrared focal plane array (IRFPA) detectors produces corrupted images with a fixed-pattern noise(FPN).We introduced and analyzed the artificial neural network scene-based non-uniformity correction (SBNUC) algorithm. A design of DSP-based NUC development platform for IRFPA is described. The DSP hardware platform designed is of low power consumption, with 32-bit fixed point DSP TMS320DM643 as the kernel processor. The dependability and expansibility of the software have been improved by DSP/BIOS real-time operating system and Reference Framework 5. In order to realize real-time performance, the calibration parameters update is set at a lower task priority then video input and output in DSP/BIOS. In this way, calibration parameters updating will not affect video streams. The work flow of the system and the strategy of real-time realization are introduced. Experiments on real infrared imaging sequences demonstrate that this algorithm requires only a few frames to obtain high quality corrections. It is computationally efficient and suitable for all kinds of non-uniformity.

Real-time video compressing under DSP/BIOS

NASA Astrophysics Data System (ADS)

Chen, Qiu-ping; Li, Gui-ju

2009-10-01

This paper presents real-time MPEG-4 Simple Profile video compressing based on the DSP processor. The programming framework of video compressing is constructed using TMS320C6416 Microprocessor, TDS510 simulator and PC. It uses embedded real-time operating system DSP/BIOS and the API functions to build periodic function, tasks and interruptions etcs. Realize real-time video compressing. To the questions of data transferring among the system. Based on the architecture of the C64x DSP, utilized double buffer switched and EDMA data transfer controller to transit data from external memory to internal, and realize data transition and processing at the same time; the architecture level optimizations are used to improve software pipeline. The system used DSP/BIOS to realize multi-thread scheduling. The whole system realizes high speed transition of a great deal of data. Experimental results show the encoder can realize real-time encoding of 768*576, 25 frame/s video images.

Ship detection in panchromatic images: a new method and its DSP implementation

NASA Astrophysics Data System (ADS)

Yao, Yuan; Jiang, Zhiguo; Zhang, Haopeng; Wang, Mengfei; Meng, Gang

2016-03-01

In this paper, a new ship detection method is proposed after analyzing the characteristics of panchromatic remote sensing images and ship targets. Firstly, AdaBoost(Adaptive Boosting) classifiers trained by Haar features are utilized to make coarse detection of ship targets. Then LSD (Line Segment Detector) is adopted to extract the line features in target slices to make fine detection. Experimental results on a dataset of panchromatic remote sensing images with a spatial resolution of 2m show that the proposed algorithm can achieve high detection rate and low false alarm rate. Meanwhile, the algorithm can meet the needs of practical applications on DSP (Digital Signal Processor).

Multiformat decoder for a DSP-based IP set-top box

NASA Astrophysics Data System (ADS)

Pescador, F.; Garrido, M. J.; Sanz, C.; Juárez, E.; Samper, D.; Antoniello, R.

2007-05-01

Internet Protocol Set-Top Boxes (IP STBs) based on single-processor architectures have been recently introduced in the market. In this paper, the implementation of an MPEG-4 SP/ASP video decoder for a multi-format IP STB based on a TMS320DM641 DSP is presented. An initial decoder for PC platform was fully tested and ported to the DSP. Using this code an optimization process was started achieving a 90% speedup. This process allows real-time MPEG-4 SP/ASP decoding. The MPEG-4 decoder has been integrated in an IP STB and tested in a real environment using DVD movies and TV channels with excellent results.

Embedded Palmprint Recognition System Using OMAP 3530

PubMed Central

Shen, Linlin; Wu, Shipei; Zheng, Songhao; Ji, Zhen

2012-01-01

We have proposed in this paper an embedded palmprint recognition system using the dual-core OMAP 3530 platform. An improved algorithm based on palm code was proposed first. In this method, a Gabor wavelet is first convolved with the palmprint image to produce a response image, where local binary patterns are then applied to code the relation among the magnitude of wavelet response at the ccentral pixel with that of its neighbors. The method is fully tested using the public PolyU palmprint database. While palm code achieves only about 89% accuracy, over 96% accuracy is achieved by the proposed G-LBP approach. The proposed algorithm was then deployed to the DSP processor of OMAP 3530 and work together with the ARM processor for feature extraction. When complicated algorithms run on the DSP processor, the ARM processor can focus on image capture, user interface and peripheral control. Integrated with an image sensing module and central processing board, the designed device can achieve accurate and real time performance. PMID:22438721

Embedded palmprint recognition system using OMAP 3530.

PubMed

Shen, Linlin; Wu, Shipei; Zheng, Songhao; Ji, Zhen

2012-01-01

We have proposed in this paper an embedded palmprint recognition system using the dual-core OMAP 3530 platform. An improved algorithm based on palm code was proposed first. In this method, a Gabor wavelet is first convolved with the palmprint image to produce a response image, where local binary patterns are then applied to code the relation among the magnitude of wavelet response at the central pixel with that of its neighbors. The method is fully tested using the public PolyU palmprint database. While palm code achieves only about 89% accuracy, over 96% accuracy is achieved by the proposed G-LBP approach. The proposed algorithm was then deployed to the DSP processor of OMAP 3530 and work together with the ARM processor for feature extraction. When complicated algorithms run on the DSP processor, the ARM processor can focus on image capture, user interface and peripheral control. Integrated with an image sensing module and central processing board, the designed device can achieve accurate and real time performance.

Indirect rotor position sensing in real time for brushless permanent magnet motor drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ertugrul, N.; Acarnley, P.P.

1998-07-01

This paper describes a modern solution to real-time rotor position estimation of brushless permanent magnet (PM) motor drives. The position estimation scheme, based on flux linkage and line-current estimation, is implemented in real time by using the abc reference frame, and it is tested dynamically. The position estimation model of the test motor, development of hardware, and basic operation of the digital signal processor (DSP) are discussed. The overall position estimation strategy is accomplished with a fast DSP (TMS320C30). The method is a shaft position sensorless method that is applicable to a wide range of excitation types in brushless PMmore » motors without any restriction on the motor model and the current excitation. Both rectangular and sinewave-excited brushless PM motor drives are examined, and the results are given to demonstrate the effectiveness of the method with dynamic loads in closed estimated position loop.« less

FPGA-Based Reconfigurable Processor for Ultrafast Interlaced Ultrasound and Photoacoustic Imaging

PubMed Central

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2016-01-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

PubMed

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2012-07-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Scalable Multiprocessor for High-Speed Computing in Space

NASA Technical Reports Server (NTRS)

Lux, James; Lang, Minh; Nishimoto, Kouji; Clark, Douglas; Stosic, Dorothy; Bachmann, Alex; Wilkinson, William; Steffke, Richard

2004-01-01

A report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.

JPRS Report Science & Technology Europe.

DTIC Science & Technology

1992-09-17

9 Jul 92] 48 HERA Project Gets Green Light for Quark Structure Analysis [DuesseldorfVDI NACHRICHTEN, 12 Jul 92] .... 48 TELECOMMUNICATIONS...communicating with the control station. The demonstrator is the product of research performed at the Robot and Artificial Intel - ligence Unit of...from the microphones, speedometers, or tachometers. Each board is linked to a Motorola DSP [digital signal processor ]. Although the system has been

Fast and robust control of nanopositioning systems: Performance limits enabled by field programmable analog arrays.

PubMed

Baranwal, Mayank; Gorugantu, Ram S; Salapaka, Srinivasa M

2015-08-01

This paper aims at control design and its implementation for robust high-bandwidth precision (nanoscale) positioning systems. Even though modern model-based control theoretic designs for robust broadband high-resolution positioning have enabled orders of magnitude improvement in performance over existing model independent designs, their scope is severely limited by the inefficacies of digital implementation of the control designs. High-order control laws that result from model-based designs typically have to be approximated with reduced-order systems to facilitate digital implementation. Digital systems, even those that have very high sampling frequencies, provide low effective control bandwidth when implementing high-order systems. In this context, field programmable analog arrays (FPAAs) provide a good alternative to the use of digital-logic based processors since they enable very high implementation speeds, moreover with cheaper resources. The superior flexibility of digital systems in terms of the implementable mathematical and logical functions does not give significant edge over FPAAs when implementing linear dynamic control laws. In this paper, we pose the control design objectives for positioning systems in different configurations as optimal control problems and demonstrate significant improvements in performance when the resulting control laws are applied using FPAAs as opposed to their digital counterparts. An improvement of over 200% in positioning bandwidth is achieved over an earlier digital signal processor (DSP) based implementation for the same system and same control design, even when for the DSP-based system, the sampling frequency is about 100 times the desired positioning bandwidth.

A single-board NMR spectrometer based on a software defined radio architecture

NASA Astrophysics Data System (ADS)

Tang, Weinan; Wang, Weimin

2011-01-01

A single-board software defined radio (SDR) spectrometer for nuclear magnetic resonance (NMR) is presented. The SDR-based architecture, realized by combining a single field programmable gate array (FPGA) and a digital signal processor (DSP) with peripheral radio frequency (RF) front-end circuits, makes the spectrometer compact and reconfigurable. The DSP, working as a pulse programmer, communicates with a personal computer via a USB interface and controls the FPGA through a parallel port. The FPGA accomplishes digital processing tasks such as a numerically controlled oscillator (NCO), digital down converter (DDC) and gradient waveform generator. The NCO, with agile control of phase, frequency and amplitude, is part of a direct digital synthesizer that is used to generate an RF pulse. The DDC performs quadrature demodulation, multistage low-pass filtering and gain adjustment to produce a bandpass signal (receiver bandwidth from 3.9 kHz to 10 MHz). The gradient waveform generator is capable of outputting shaped gradient pulse waveforms and supports eddy-current compensation. The spectrometer directly acquires an NMR signal up to 30 MHz in the case of baseband sampling and is suitable for low-field (<0.7 T) application. Due to the featured SDR architecture, this prototype has flexible add-on ability and is expected to be suitable for portable NMR systems.

Digital Audio Signal Processing and Nde: AN Unlikely but Valuable Partnership

NASA Astrophysics Data System (ADS)

Gaydecki, Patrick

2008-02-01

In the Digital Signal Processing (DSP) group, within the School of Electrical and Electronic Engineering at The University of Manchester, research is conducted into two seemingly distinct and disparate subjects: instrumentation for nondestructive evaluation, and DSP systems & algorithms for digital audio. We have often found that many of the hardware systems and algorithms employed to recover, extract or enhance audio signals may also be applied to signals provided by ultrasonic or magnetic NDE instruments. Furthermore, modern DSP hardware is so fast (typically performing hundreds of millions of operations per second), that much of the processing and signal reconstruction may be performed in real time. Here, we describe some of the hardware systems we have developed, together with algorithms that can be implemented both in real time and offline. A next generation system has now been designed, which incorporates a processor operating at 0.55 Giga MMACS, six input and eight output analogue channels, digital input/output in the form of S/PDIF, a JTAG and a USB interface. The software allows the user, with no knowledge of filter theory or programming, to design and run standard or arbitrary FIR, IIR and adaptive filters. Using audio as a vehicle, we can demonstrate the remarkable properties of modern reconstruction algorithms when used in conjunction with such hardware; applications in NDE include signal enhancement and recovery in acoustic, ultrasonic, magnetic and eddy current modalities.

Research on control law accelerator of digital signal process chip TMS320F28035 for real-time data acquisition and processing

NASA Astrophysics Data System (ADS)

Zhao, Shuangle; Zhang, Xueyi; Sun, Shengli; Wang, Xudong

2017-08-01

TI C2000 series digital signal process (DSP) chip has been widely used in electrical engineering, measurement and control, communications and other professional fields, DSP TMS320F28035 is one of the most representative of a kind. When using the DSP program, need data acquisition and data processing, and if the use of common mode C or assembly language programming, the program sequence, analogue-to-digital (AD) converter cannot be real-time acquisition, often missing a lot of data. The control low accelerator (CLA) processor can run in parallel with the main central processing unit (CPU), and the frequency is consistent with the main CPU, and has the function of floating point operations. Therefore, the CLA coprocessor is used in the program, and the CLA kernel is responsible for data processing. The main CPU is responsible for the AD conversion. The advantage of this method is to reduce the time of data processing and realize the real-time performance of data acquisition.

Modulated Fourier Transform Raman Fiber-Optic Spectroscopy

NASA Technical Reports Server (NTRS)

Jensen, Brian J. (Inventor); Cooper, John B. (Inventor); Wise, Kent L. (Inventor)

2000-01-01

A modification to a commercial Fourier Transform (FT) Raman spectrometer is presented for the elimination of thermal backgrounds in the FT Raman spectra. The modification involves the use of a mechanical optical chopper to modulate the continuous wave laser, remote collection of the signal via fiber optics, and connection of a dual-phase digital-signal-processor (DSP) lock-in amplifier between the detector and the spectrometer's collection electronics to demodulate and filter the optical signals. The resulting Modulated Fourier Transform Raman Fiber-Optic Spectrometer is capable of completely eliminating thermal backgrounds at temperatures exceeding 300 C.

Computer Algorithms and Architectures for Three-Dimensional Eddy-Current Nondestructive Evaluation. Volume 3. Chapters 6-11

DTIC Science & Technology

1989-01-20

addressable memory can be loaded or off- loaded as the number crunching continues. Modem VLSI processors can often process data faster than today’s...Available DSP Chips Texas Instruments was one of the first serious manufacturers of DSP chips. With the Texas Instruments TMS310 DSP chip, modem , voice...Can handle double presicion data types. Texas Instruments TMS32010 T’s first-generation DSP design: a fixed-point DSP that has found its way into modem

Real-time separation of multineuron recordings with a DSP32C signal processor.

PubMed

Gädicke, R; Albus, K

1995-04-01

We have developed a hardware and software package for real-time discrimination of multiple-unit activities recorded simultaneously from multiple microelectrodes using a VME-Bus system. Compared with other systems cited in literature or commercially available, our system has the following advantages. (1) Each electrode is served by its own preprocessor (DSP32C); (2) On-line spike discrimination is performed independently for each electrode. (3) The VME-bus allows processing of data received from 16 electrodes. The digitized (62.5 kHz) spike form is itself used as the model spike; the algorithm allows for comparing and sorting complete wave forms in real time into 8 different models per electrode.

Advanced Power Electronic Interfaces for Distributed Energy Systems, Part 2: Modeling, Development, and Experimental Evaluation of Advanced Control Functions for Single-Phase Utility-Connected Inverter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chakraborty, S.; Kroposki, B.; Kramer, W.

Integrating renewable energy and distributed generations into the Smart Grid architecture requires power electronic (PE) for energy conversion. The key to reaching successful Smart Grid implementation is to develop interoperable, intelligent, and advanced PE technology that improves and accelerates the use of distributed energy resource systems. This report describes the simulation, design, and testing of a single-phase DC-to-AC inverter developed to operate in both islanded and utility-connected mode. It provides results on both the simulations and the experiments conducted, demonstrating the ability of the inverter to provide advanced control functions such as power flow and VAR/voltage regulation. This report alsomore » analyzes two different techniques used for digital signal processor (DSP) code generation. Initially, the DSP code was written in C programming language using Texas Instrument's Code Composer Studio. In a later stage of the research, the Simulink DSP toolbox was used to self-generate code for the DSP. The successful tests using Simulink self-generated DSP codes show promise for fast prototyping of PE controls.« less

a Continuous Health Monitoring Guided Wave Fmd System for Retrofit to Existing Offshore Oilrigs

NASA Astrophysics Data System (ADS)

Mijarez, R.; Solis, L.; Martinez, F.

2010-02-01

An automatic health monitoring guided wave flood member detection (FMD) system, for retrofit to existing offshore oilrigs is presented. The system employs a microcontroller piezoelectric (PZT) based transmitter and a receiver instrumentation package composed of a PZT 40 kHz ultrasound transducer and a digital signal processor (DSP) module connected to a PC via USB for monitoring purposes. The transmitter and receiver were attached, non-intrusively, to the external wall of a steel tube; 1 m×27 cm×2 mm. Experiments performed in the laboratory have successfully identified automatically flooded tubes.

Research on grid connection control technology of double fed wind generator

NASA Astrophysics Data System (ADS)

Ling, Li

2017-01-01

The composition and working principle of variable speed constant frequency doubly fed wind power generation system is discussed in this thesis. On the basis of theoretical analysis and control on the modeling, the doubly fed wind power generation simulation control system is designed based on a TMS320F2407 digital signal processor (DSP), and has done a large amount of experimental research, which mainly include, variable speed constant frequency, constant pressure, Grid connected control experiment. The running results show that the design of simulation control system is reasonable and can meet the need of experimental research.

Implantable control, telemetry, and solar energy system in the moving actuator type total artificial heart.

PubMed

Ahn, J M; Lee, J H; Choi, S W; Kim, W E; Omn, K S; Park, S K; Kim, W G; Roh, J R; Min, B G

1998-03-01

The moving actuator type total artificial heart (TAH) developed in the Seoul National University has numerous design improvements based upon the digital signal processor (DSP). These improvements include the implantability of all electronics, an automatic control algorithm, and extension of the battery run-time in connection with an amorphous silicon solar system (SS). The implantable electronics consist of the motor drive, main processor, intelligent Li ion battery management (LIBM) based upon the DSP, telemetry system, and transcutaneous energy transmission (TET) system. Major changes in the implantable electronics include decreasing the temperature rise by over 21 degrees C on the motor drive, volume reduction (40 x 55 x 33 mm, 7 cell assembly) of the battery pack using a Li ion (3.6 V/cell, 900 mA.h), and improvement of the battery run-time (over 40 min) while providing the cardiac output (CO) of 5 L/min at 100 mm Hg afterload when the external battery for testing is connected with the SS (2.5 W, 192.192, 1 kg) for the external battery recharge or the partial TAH drive. The phase locked loop (PLL) based telemetry system was implemented to improve stability and the error correction DSP algorithm programmed to achieve high accuracy. A field focused light emitting diode (LED) was used to obtain low light scattering along the propagation path, similar to the optical property of the laser and miniature sized, mounted on the pancake type TET coils. The TET operating resonance frequency was self tuned in a range of 360 to 410 kHz to provide enough power even at high afterloads. An automatic cardiac output regulation algorithm was developed based on interventricular pressure analysis and carried out in several animal experiments successfully. All electronics have been evaluated in vitro and in vivo and prepared for implantation of the TAH. Substantial progress has been made in designing a completely implantable TAH at the preclinical stage.

Low-power wearable respiratory sound sensing.

PubMed

Oletic, Dinko; Arsenali, Bruno; Bilas, Vedran

2014-04-09

Building upon the findings from the field of automated recognition of respiratory sound patterns, we propose a wearable wireless sensor implementing on-board respiratory sound acquisition and classification, to enable continuous monitoring of symptoms, such as asthmatic wheezing. Low-power consumption of such a sensor is required in order to achieve long autonomy. Considering that the power consumption of its radio is kept minimal if transmitting only upon (rare) occurrences of wheezing, we focus on optimizing the power consumption of the digital signal processor (DSP). Based on a comprehensive review of asthmatic wheeze detection algorithms, we analyze the computational complexity of common features drawn from short-time Fourier transform (STFT) and decision tree classification. Four algorithms were implemented on a low-power TMS320C5505 DSP. Their classification accuracies were evaluated on a dataset of prerecorded respiratory sounds in two operating scenarios of different detection fidelities. The execution times of all algorithms were measured. The best classification accuracy of over 92%, while occupying only 2.6% of the DSP's processing time, is obtained for the algorithm featuring the time-frequency tracking of shapes of crests originating from wheezing, with spectral features modeled using energy.

PPM-based System for Guided Waves Communication Through Corrosion Resistant Multi-wire Cables

NASA Astrophysics Data System (ADS)

Trane, G.; Mijarez, R.; Guevara, R.; Pascacio, D.

Novel wireless communication channels are a necessity in applications surrounded by harsh environments, for instance down-hole oil reservoirs. Traditional radio frequency (RF) communication schemes are not capable of transmitting signals through metal enclosures surrounded by corrosive gases and liquids. As an alternative to RF, a pulse position modulation (PPM) guided waves communication system has been developed and evaluated using a corrosion resistant 4H18 multi-wire cable, commonly used to descend electronic gauges in down-hole oil applications, as the communication medium. The system consists of a transmitter and a receiver that utilizes a PZT crystal, for electrical/mechanical coupling, attached to each extreme of the multi-wire cable. The modulator is based on a microcontroller, which transmits60 kHz guided wave pulses, and the demodulator is based on a commercial digital signal processor (DSP) module that performs real time DSP algorithms. Experimental results are presented, which were obtained using a 1m corrosion resistant 4H18multi-wire cable, commonly used with downhole electronic gauges in the oil sector. Although there was significant dispersion and multiple mode excitations of the transmitted guided wave energy pulses, the results show that data rates on the order of 500 bits per second are readily available employing PPM and simple communications techniques.

Spacecube: A Family of Reconfigurable Hybrid On-Board Science Data Processors

NASA Technical Reports Server (NTRS)

Flatley, Thomas P.

2015-01-01

SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science data processing systems developed at the NASA Goddard Space Flight Center (GSFC). The goal of the SpaceCube program is to provide 10x to 100x improvements in on-board computing power while lowering relative power consumption and cost. SpaceCube is based on the Xilinx Virtex family of FPGAs, which include processor, FPGA logic and digital signal processing (DSP) resources. These processing elements are leveraged to produce a hybrid science data processing platform that accelerates the execution of algorithms by distributing computational functions to the most suitable elements. This approach enables the implementation of complex on-board functions that were previously limited to ground based systems, such as on-board product generation, data reduction, calibration, classification, eventfeature detection, data mining and real-time autonomous operations. The system is fully reconfigurable in flight, including data parameters, software and FPGA logic, through either ground commanding or autonomously in response to detected eventsfeatures in the instrument data stream.

Monitoring of electric-cardio signals based on DSP

NASA Astrophysics Data System (ADS)

Yan, Yi-xin; Sun, Hui-nan; Lv, Shuang

2008-10-01

Monitoring of electric-cardio signals is the most direct method of discovering heart diseases. This article presents an electric-cardio signal acquisition and processing system based on DSP. According to the features of electric-cardio signals, the proposed system uses the AgCl electrode as electric-cardio signals sensor, and acquires analog signals with AD620 as the prepositional amplifier, and the digital system equipped is with TMS320LF2407A DSP. The design of digital filter and the analysis of heart rate variation are realized by programming in the DSP. Finally the ECG is obtained with P and T waves along with obvious QRS multi-wave characteristics. The system has low power dissipation, low cost and high precision, which meets the requirements for medical instruments.

Speech coding at 4800 bps for mobile satellite communications

NASA Technical Reports Server (NTRS)

Gersho, Allen; Chan, Wai-Yip; Davidson, Grant; Chen, Juin-Hwey; Yong, Mei

1988-01-01

A speech compression project has recently been completed to develop a speech coding algorithm suitable for operation in a mobile satellite environment aimed at providing telephone quality natural speech at 4.8 kbps. The work has resulted in two alternative techniques which achieve reasonably good communications quality at 4.8 kbps while tolerating vehicle noise and rather severe channel impairments. The algorithms are embodied in a compact self-contained prototype consisting of two AT and T 32-bit floating-point DSP32 digital signal processors (DSP). A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. On a wirewrapped card, the prototype's circuit footprint amounts to only 200 sq cm, and consumes about 9 watts of power.

A digitally implemented preambleless demodulator for maritime and mobile data communications

NASA Astrophysics Data System (ADS)

Chalmers, Harvey; Shenoy, Ajit; Verahrami, Farhad B.

The hardware design and software algorithms for a low-bit-rate, low-cost, all-digital preambleless demodulator are described. The demodulator operates under severe high-noise conditions, fast Doppler frequency shifts, large frequency offsets, and multipath fading. Sophisticated algorithms, including a fast Fourier transform (FFT)-based burst acquisition algorithm, a cycle-slip resistant carrier phase tracker, an innovative Doppler tracker, and a fast acquisition symbol synchronizer, were developed and extensively simulated for reliable burst reception. The compact digital signal processor (DSP)-based demodulator hardware uses a unique personal computer test interface for downloading test data files. The demodulator test results demonstrate a near-ideal performance within 0.2 dB of theory.

Multichannel Phase and Power Detector

NASA Technical Reports Server (NTRS)

Li, Samuel; Lux, James; McMaster, Robert; Boas, Amy

2006-01-01

An electronic signal-processing system determines the phases of input signals arriving in multiple channels, relative to the phase of a reference signal with which the input signals are known to be coherent in both phase and frequency. The system also gives an estimate of the power levels of the input signals. A prototype of the system has four input channels that handle signals at a frequency of 9.5 MHz, but the basic principles of design and operation are extensible to other signal frequencies and greater numbers of channels. The prototype system consists mostly of three parts: An analog-to-digital-converter (ADC) board, which coherently digitizes the input signals in synchronism with the reference signal and performs some simple processing; A digital signal processor (DSP) in the form of a field-programmable gate array (FPGA) board, which performs most of the phase- and power-measurement computations on the digital samples generated by the ADC board; and A carrier board, which allows a personal computer to retrieve the phase and power data. The DSP contains four independent phase-only tracking loops, each of which tracks the phase of one of the preprocessed input signals relative to that of the reference signal (see figure). The phase values computed by these loops are averaged over intervals, the length of which is chosen to obtain output from the DSP at a desired rate. In addition, a simple sum of squares is computed for each channel as an estimate of the power of the signal in that channel. The relative phases and the power level estimates computed by the DSP could be used for diverse purposes in different settings. For example, if the input signals come from different elements of a phased-array antenna, the phases could be used as indications of the direction of arrival of a received signal and/or as feedback for electronic or mechanical beam steering. The power levels could be used as feedback for automatic gain control in preprocessing of incoming signals. For another example, the system could be used to measure the phases and power levels of outputs of multiple power amplifiers to enable adjustment of the amplifiers for optimal power combining.

Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification.

PubMed

Yang, Fan; Paindavoine, M

2003-01-01

This paper describes a real time vision system that allows us to localize faces in video sequences and verify their identity. These processes are image processing techniques based on the radial basis function (RBF) neural network approach. The robustness of this system has been evaluated quantitatively on eight video sequences. We have adapted our model for an application of face recognition using the Olivetti Research Laboratory (ORL), Cambridge, UK, database so as to compare the performance against other systems. We also describe three hardware implementations of our model on embedded systems based on the field programmable gate array (FPGA), zero instruction set computer (ZISC) chips, and digital signal processor (DSP) TMS320C62, respectively. We analyze the algorithm complexity and present results of hardware implementations in terms of the resources used and processing speed. The success rates of face tracking and identity verification are 92% (FPGA), 85% (ZISC), and 98.2% (DSP), respectively. For the three embedded systems, the processing speeds for images size of 288 /spl times/ 352 are 14 images/s, 25 images/s, and 4.8 images/s, respectively.

A Next Generation Digital Counting System For Low-Level Tritium Studies (Project Report)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bowman, P.

2016-10-03

Since the early seventies, SRNL has pioneered low-level tritium analysis using various nuclear counting technologies and techniques. Since 1999, SRNL has successfully performed routine low-level tritium analyses with counting systems based on digital signal processor (DSP) modules developed in the late 1990s. Each of these counting systems are complex, unique to SRNL, and fully dedicated to performing routine tritium analyses of low-level environmental samples. It is time to modernize these systems due to a variety of issues including (1) age, (2) lack of direct replacement electronics modules and (3) advances in digital signal processing and computer technology. There has beenmore » considerable development in many areas associated with the enterprise of performing low-level tritium analyses. The objective of this LDRD project was to design, build, and demonstrate a Next Generation Tritium Counting System (NGTCS), while not disrupting the routine low-level tritium analyses underway in the facility on the legacy counting systems. The work involved (1) developing a test bed for building and testing new counting system hardware that does not interfere with our routine analyses, (2) testing a new counting system based on a modern state of the art DSP module, and (3) evolving the low-level tritium counter design to reflect the state of the science.« less

Development, implementation, and characterization of a standalone embedded viscosity measurement system based on the impedance spectroscopy of a vibrating wire sensor

NASA Astrophysics Data System (ADS)

Santos, José; Janeiro, Fernando M.; Ramos, Pedro M.

2015-10-01

This paper presents an embedded liquid viscosity measurement system based on a vibrating wire sensor. Although multiple viscometers based on different working principles are commercially available, there is still a market demand for a dedicated measurement system capable of performing accurate, fast measurements and requiring little or no operator training for simple systems and solution monitoring. The developed embedded system is based on a vibrating wire sensor that works by measuring the impedance response of the sensor, which depends on the viscosity and density of the liquid in which the sensor is immersed. The core of the embedded system is a digital signal processor (DSP) which controls the waveform generation and acquisitions for the measurement of the impedance frequency response. The DSP also processes the acquired waveforms and estimates the liquid viscosity. The user can interact with the measurement system through a keypad and an LCD or through a computer with a USB connection for data logging and processing. The presented system is tested on a set of viscosity standards and the estimated values are compared with the standard manufacturer specified viscosity values. A stability study of the measurement system is also performed.

Code Compression for DSP

DTIC Science & Technology

1998-12-01

PAGES 6 19a. NAME OF RESPONSIBLE PERSON a. REPORT unclassified b . ABSTRACT unclassified c. THIS PAGE unclassified Standard Form 298 (Rev. 8...Automation Conference, June 1998. [Liao95] S. Liao, S. Devadas , K. Keutzer, “Code Density Optimization for Embedded DSP Processors Using Data Compression

Secure communication based on spatiotemporal chaos

NASA Astrophysics Data System (ADS)

Ren, Hai-Peng; Bai, Chao

2015-08-01

In this paper, we propose a novel approach to secure communication based on spatiotemporal chaos. At the transmitter end, the state variables of the coupled map lattice system are divided into two groups: one is used as the key to encrypt the plaintext in the N-shift encryption function, and the other is used to mix with the output of the N-shift function to further confuse the information to transmit. At the receiver end, the receiver lattices are driven by the received signal to synchronize with the transmitter lattices and an inverse procedure of the encoding is conducted to decode the information. Numerical simulation and experiment based on the TI TMS320C6713 Digital Signal Processor (DSP) show the feasibility and the validity of the proposed scheme. Project supported by the National Natural Science Foundation of China (Grant No. 61172070) and the Funds from the Science and Technology Innovation Team of Shaanxi Province, China (Grant No. 2013CKT-04).

[Digital signal processing of a novel neuron discharge model stimulation strategy for cochlear implants].

PubMed

Yang, Yiwei; Xu, Yuejin; Miu, Jichang; Zhou, Linghong; Xiao, Zhongju

2012-10-01

To apply the classic leakage integrate-and-fire models, based on the mechanism of the generation of physiological auditory stimulation, in the information processing coding of cochlear implants to improve the auditory result. The results of algorithm simulation in digital signal processor (DSP) were imported into Matlab for a comparative analysis. Compared with CIS coding, the algorithm of membrane potential integrate-and-fire (MPIF) allowed more natural pulse discharge in a pseudo-random manner to better fit the physiological structures. The MPIF algorithm can effectively solve the problem of the dynamic structure of the delivered auditory information sequence issued in the auditory center and allowed integration of the stimulating pulses and time coding to ensure the coherence and relevance of the stimulating pulse time.

A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Dutton, Kenneth

2005-01-01

The design of an Evolvable Machine VHDL Core is presented, representing a discrete-time processing structure capable of supporting control system applications. This VHDL Core is implemented in an FPGA and is interfaced with an evolutionary algorithm implemented in firmware on a Digital Signal Processor (DSP) to create an evolvable system platform. The salient features of this architecture are presented. The capability to implement IIR filter structures is presented along with the results of the intrinsic evolution of a filter. The robustness of the evolved filter design is tested and its unique characteristics are described.

Research on phase locked loop in optical memory servo system

NASA Astrophysics Data System (ADS)

Qin, Liqin; Ma, Jianshe; Zhang, Jianyong; Pan, Longfa; Deng, Ming

2005-09-01

Phase locked loop (PLL) is a closed loop automatic control system, which can track the phase of input signal. It widely applies in each area of electronic technology. This paper research the phase locked loop in optical memory servo area. This paper introduces the configuration of digital phase locked loop (PLL) and phase locked servo system, the control theory, and analyses system's stability. It constructs the phase locked loop experiment system of optical disk spindle servo, which based on special chip. DC motor is main object, this system adopted phase locked servo technique and digital signal processor (DSP) to achieve constant linear velocity (CLV) in controlling optical spindle motor. This paper analyses the factors that affect the stability of phase locked loop in spindle servo system, and discusses the affection to the optical disk readout signal and jitter due to the stability of phase locked loop.

Interior Noise Reduction by Adaptive Feedback Vibration Control

NASA Technical Reports Server (NTRS)

Lim, Tae W.

1998-01-01

The objective of this project is to investigate the possible use of adaptive digital filtering techniques in simultaneous, multiple-mode identification of the modal parameters of a vibrating structure in real-time. It is intended that the results obtained from this project will be used for state estimation needed in adaptive structural acoustics control. The work done in this project is basically an extension of the work on real-time single mode identification, which was performed successfully using a digital signal processor (DSP) at NASA, Langley. Initially, in this investigation the single mode identification work was duplicated on a different processor, namely the Texas Instruments TMS32OC40 DSP. The system identification results for the single mode case were very good. Then an algorithm for simultaneous two mode identification was developed and tested using analytical simulation. When it successfully performed the expected tasks, it was implemented in real-time on the DSP system to identify the first two modes of vibration of a cantilever aluminum beam. The results of the simultaneous two mode case were good but some problems were identified related to frequency warping and spurious mode identification. The frequency warping problem was found to be due to the bilinear transformation used in the algorithm to convert the system transfer function from the continuous-time domain to the discrete-time domain. An alternative approach was developed to rectify the problem. The spurious mode identification problem was found to be associated with high sampling rates. Noise in the signal is suspected to be the cause of this problem but further investigation will be needed to clarify the cause. For simultaneous identification of more than two modes, it was found that theoretically an adaptive digital filter can be designed to identify the required number of modes, but the algebra became very complex which made it impossible to implement in the DSP system used in this study. The on-line identification algorithm developed in this research will be useful in constructing a state estimator for feedback vibration control.

Secretion and translocation signals and DspB/F-binding domains in the type III effector DspA/E of Erwinia amylovora.

PubMed

Oh, Chang-Sik; Carpenter, Sara C D; Hayes, Marshall L; Beer, Steven V

2010-04-01

DspA/E is a type III effector of Erwinia amylovora, the bacterial pathogen that causes fire blight disease in roseaceous plants. This effector is indispensable for disease development, and it is translocated into plant cells. A DspA/E-specific chaperone, DspB/F, is necessary for DspA/E secretion and possibly for its translocation. In this work, DspB/F-binding sites and secretion and translocation signals in the DspA/E protein were determined. Based on yeast two-hybrid assays, DspB/F was found to bind DspA/E within the first 210 amino acids of the protein. Surprisingly, both DspB/F and OrfA, the putative chaperone of Eop1, also interacted with the C-terminal 1059 amino acids of DspA/E; this suggests another chaperone-binding site. Secretion and translocation assays using serial N-terminal lengths of DspA/E fused with the active form of AvrRpt2 revealed that at least the first 109 amino acids, including the first N-terminal chaperone-binding motif and DspB/F, were required for efficient translocation of DspA/E, although the first 35 amino acids were sufficient for its secretion and the presence of DspB/F was not required. These results indicate that secretion and translocation signals are present in the N terminus of DspA/E, and that at least one DspB/F-binding motif is required for efficient translocation into plant cells.

Parallel processing approach to transform-based image coding

NASA Astrophysics Data System (ADS)

Normile, James O.; Wright, Dan; Chu, Ken; Yeh, Chia L.

1991-06-01

This paper describes a flexible parallel processing architecture designed for use in real time video processing. The system consists of floating point DSP processors connected to each other via fast serial links, each processor has access to a globally shared memory. A multiple bus architecture in combination with a dual ported memory allows communication with a host control processor. The system has been applied to prototyping of video compression and decompression algorithms. The decomposition of transform based algorithms for decompression into a form suitable for parallel processing is described. A technique for automatic load balancing among the processors is developed and discussed, results ar presented with image statistics and data rates. Finally techniques for accelerating the system throughput are analyzed and results from the application of one such modification described.

Stereo and IMU-Assisted Visual Odometry for Small Robots

NASA Technical Reports Server (NTRS)

2012-01-01

This software performs two functions: (1) taking stereo image pairs as input, it computes stereo disparity maps from them by cross-correlation to achieve 3D (three-dimensional) perception; (2) taking a sequence of stereo image pairs as input, it tracks features in the image sequence to estimate the motion of the cameras between successive image pairs. A real-time stereo vision system with IMU (inertial measurement unit)-assisted visual odometry was implemented on a single 750 MHz/520 MHz OMAP3530 SoC (system on chip) from TI (Texas Instruments). Frame rates of 46 fps (frames per second) were achieved at QVGA (Quarter Video Graphics Array i.e. 320 240), or 8 fps at VGA (Video Graphics Array 640 480) resolutions, while simultaneously tracking up to 200 features, taking full advantage of the OMAP3530's integer DSP (digital signal processor) and floating point ARM processors. This is a substantial advancement over previous work as the stereo implementation produces 146 Mde/s (millions of disparities evaluated per second) in 2.5W, yielding a stereo energy efficiency of 58.8 Mde/J, which is 3.75 better than prior DSP stereo while providing more functionality.

DSPACE hardware architecture for on-board real-time image/video processing in European space missions

NASA Astrophysics Data System (ADS)

Saponara, Sergio; Donati, Massimiliano; Fanucci, Luca; Odendahl, Maximilian; Leupers, Reiner; Errico, Walter

2013-02-01

The on-board data processing is a vital task for any satellite and spacecraft due to the importance of elaborate the sensing data before sending them to the Earth, in order to exploit effectively the bandwidth to the ground station. In the last years the amount of sensing data collected by scientific and commercial space missions has increased significantly, while the available downlink bandwidth is comparatively stable. The increasing demand of on-board real-time processing capabilities represents one of the critical issues in forthcoming European missions. Faster and faster signal and image processing algorithms are required to accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunications. The only available space-qualified Digital Signal Processor (DSP) free of International Traffic in Arms Regulations (ITAR) restrictions faces inadequate performance, thus the development of a next generation European DSP is well known to the space community. The DSPACE space-qualified DSP architecture fills the gap between the computational requirements and the available devices. It leverages a pipelined and massively parallel core based on the Very Long Instruction Word (VLIW) paradigm, with 64 registers and 8 operational units, along with cache memories, memory controllers and SpaceWire interfaces. Both the synthesizable VHDL and the software development tools are generated from the LISA high-level model. A Xilinx-XC7K325T FPGA is chosen to realize a compact PCI demonstrator board. Finally first synthesis results on CMOS standard cell technology (ASIC 180 nm) show an area of around 380 kgates and a peak performance of 1000 MIPS and 750 MFLOPS at 125MHz.

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

An Architecture for Measuring Joint Angles Using a Long Period Fiber Grating-Based Sensor

PubMed Central

Perez-Ramirez, Carlos A.; Almanza-Ojeda, Dora L.; Guerrero-Tavares, Jesus N.; Mendoza-Galindo, Francisco J.; Estudillo-Ayala, Julian M.; Ibarra-Manzano, Mario A.

2014-01-01

The implementation of signal filters in a real-time form requires a tradeoff between computation resources and the system performance. Therefore, taking advantage of low lag response and the reduced consumption of resources, in this article, the Recursive Least Square (RLS) algorithm is used to filter a signal acquired from a fiber-optics-based sensor. In particular, a Long-Period Fiber Grating (LPFG) sensor is used to measure the bending movement of a finger. After that, the Gaussian Mixture Model (GMM) technique allows us to classify the corresponding finger position along the motion range. For these measures to help in the development of an autonomous robotic hand, the proposed technique can be straightforwardly implemented on real time platforms such as Field Programmable Gate Array (FPGA) or Digital Signal Processors (DSP). Different angle measurements of the finger's motion are carried out by the prototype and a detailed analysis of the system performance is presented. PMID:25536002

Modular uncooled video engines based on a DSP processor

NASA Astrophysics Data System (ADS)

Schapiro, F.; Milstain, Y.; Aharon, A.; Neboshchik, A.; Ben-Simon, Y.; Kogan, I.; Lerman, I.; Mizrahi, U.; Maayani, S.; Amsterdam, A.; Vaserman, I.; Duman, O.; Gazit, R.

2011-06-01

The market demand for low SWaP (Size, Weight and Power) uncooled engines keeps growing. Low SWaP is especially critical in battery-operated applications such as goggles and Thermal Weapon Sights. A new approach for the design of the engines was implemented by SCD to optimize size and power consumption at system level. The new approach described in the paper, consists of: 1. A modular hardware design that allows the user to define the exact level of integration needed for his system 2. An "open architecture" based on the OMAPTM530 DSP that allows the integrator to take advantage of unused hardware (FPGA) and software (DSP) resources, for implementation of additional algorithms or functionality. The approach was successfully implemented on the first generation of 25μm pitch BIRD detectors, and more recently on the new, 640 x480, 17 μm pitch detector.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Known-plaintext attack on the double phase encoding and its implementation with parallel hardware

NASA Astrophysics Data System (ADS)

Wei, Hengzheng; Peng, Xiang; Liu, Haitao; Feng, Songlin; Gao, Bruce Z.

2008-03-01

A known-plaintext attack on the double phase encryption scheme implemented with parallel hardware is presented. The double random phase encoding (DRPE) is one of the most representative optical cryptosystems developed in mid of 90's and derives quite a few variants since then. Although the DRPE encryption system has a strong power resisting to a brute-force attack, the inherent architecture of DRPE leaves a hidden trouble due to its linearity nature. Recently the real security strength of this opto-cryptosystem has been doubted and analyzed from the cryptanalysis point of view. In this presentation, we demonstrate that the optical cryptosystems based on DRPE architecture are vulnerable to known-plain text attack. With this attack the two encryption keys in the DRPE can be accessed with the help of the phase retrieval technique. In our approach, we adopt hybrid input-output algorithm (HIO) to recover the random phase key in the object domain and then infer the key in frequency domain. Only a plaintext-ciphertext pair is sufficient to create vulnerability. Moreover this attack does not need to select particular plaintext. The phase retrieval technique based on HIO is an iterative process performing Fourier transforms, so it fits very much into the hardware implementation of the digital signal processor (DSP). We make use of the high performance DSP to accomplish the known-plaintext attack. Compared with the software implementation, the speed of the hardware implementation is much fast. The performance of this DSP-based cryptanalysis system is also evaluated.

A digital-signal-processor-based optical tomographic system for dynamic imaging of joint diseases

NASA Astrophysics Data System (ADS)

Lasker, Joseph M.

Over the last decade, optical tomography (OT) has emerged as viable biomedical imaging modality. Various imaging systems have been developed that are employed in preclinical as well as clinical studies, mostly targeting breast imaging, brain imaging, and cancer related studies. Of particular interest are so-called dynamic imaging studies where one attempts to image changes in optical properties and/or physiological parameters as they occur during a system perturbation. To successfully perform dynamic imaging studies, great effort is put towards system development that offers increasingly enhanced signal-to-noise performance at ever shorter data acquisition times, thus capturing high fidelity tomographic data within narrower time periods. Towards this goal, I have developed in this thesis a dynamic optical tomography system that is, unlike currently available analog instrumentation, based on digital data acquisition and filtering techniques. At the core of this instrument is a digital signal processor (DSP) that collects, collates, and processes the digitized data set. Complementary protocols between the DSP and a complex programmable logic device synchronizes the sampling process and organizes data flow. Instrument control is implemented through a comprehensive graphical user interface which integrates automated calibration, data acquisition, and signal post-processing. Real-time data is generated at frame rates as high as 140 Hz. An extensive dynamic range (˜190 dB) accommodates a wide scope of measurement geometries and tissue types. Performance analysis demonstrates very low system noise (˜1 pW rms noise equivalent power), excellent signal precision (˜0.04%--0.2%) and long term system stability (˜1% over 40 min). Experiments on tissue phantoms validate spatial and temporal accuracy of the system. As a potential new application of dynamic optical imaging I present the first application of this method to use vascular hemodynamics as a means of characterizing joint diseases, especially effects of rheumatoid arthritis (RA) in the proximal interphalangeal finger joints. Using a dual-wavelength tomographic imaging system and previously implemented reconstruction scheme, I have performed initial dynamic imaging case studies on healthy volunteers and patients diagnosed with RA. These studies support our hypothesis that differences in the vascular and metabolic reactivity exist between affected and unaffected joints and can be used for diagnostic purposes.

Locomotive track detection for underground

NASA Astrophysics Data System (ADS)

Ma, Zhonglei; Lang, Wenhui; Li, Xiaoming; Wei, Xing

2017-08-01

In order to improve the PC-based track detection system, this paper proposes a method to detect linear track for underground locomotive based on DSP + FPGA. Firstly, the analog signal outputted from the camera is sampled by A / D chip. Then the collected digital signal is preprocessed by FPGA. Secondly, the output signal of FPGA is transmitted to DSP via EMIF port. Subsequently, the adaptive threshold edge detection, polar angle and radius constrain based Hough transform are implemented by DSP. Lastly, the detected track information is transmitted to host computer through Ethernet interface. The experimental results show that the system can not only meet the requirements of real-time detection, but also has good robustness.

JSATS Detector Field Manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choi, Eric Y.; Flory, Adam E.; Lamarche, Brian L.

2014-06-01

The Juvenile Salmon Acoustic Telemetry System (JSATS) Detector is a software and hardware system that captures JSATS Acoustic Micro Transmitter (AMT) signals. The system uses hydrophones to capture acoustic signals in the water. This analog signal is then amplified and processed by the Analog to Digital Converter (ADC) and Digital Signal Processor (DSP) board in the computer. This board digitizes and processes the acoustic signal to determine if a possible JSATS tag is present. With this detection, the data will be saved to the computer for further analysis. This document details the features and functionality of the JSATS Detector software.more » The document covers how to install the software, setup and run the detector software. The document will also go over the raw binary waveform file format and CSV files containing RMS values« less

A Nonlinear Digital Control Solution for a DC/DC Power Converter

NASA Technical Reports Server (NTRS)

Zhu, Minshao

2002-01-01

A digital Nonlinear Proportional-Integral-Derivative (NPID) control algorithm was proposed to control a 1-kW, PWM, DC/DC, switching power converter. The NPID methodology is introduced and a practical hardware control solution is obtained. The design of the controller was completed using Matlab (trademark) Simulink, while the hardware-in-the-loop testing was performed using both the dSPACE (trademark) rapid prototyping system, and a stand-alone Texas Instruments (trademark) Digital Signal Processor (DSP)-based system. The final Nonlinear digital control algorithm was implemented and tested using the ED408043-1 Westinghouse DC-DC switching power converter. The NPID test results are discussed and compared to the results of a standard Proportional-Integral (PI) controller.

A distributed control system for the lower-hybrid current drive system on the Tokamak de Varennes

NASA Astrophysics Data System (ADS)

Bagdoo, J.; Guay, J. M.; Chaudron, G.-A.; Decoste, R.; Demers, Y.; Hubbard, A.

1990-08-01

An rf current drive system with an output power of 1 MW at 3.7 GHz is under development for the Tokamak de Varennes. The control system is based on an Ethernet local-area network of programmable logic controllers as front end, personal computers as consoles, and CAMAC-based DSP processors. The DSP processors ensure the PID control of the phase and rf power of each klystron, and the fast protection of high-power rf hardware, all within a 40 μs loop. Slower control and protection, event sequencing and the run-time database are provided by the programmable logic controllers, which communicate, via the LAN, with the consoles. The latter run a commercial process-control console software. The LAN protocol respects the first four layers of the ISO/OSI 802.3 standard. Synchronization with the tokamak control system is provided by commercially available CAMAC timing modules which trigger shot-related events and reference waveform generators. A detailed description of each subsystem and a performance evaluation of the system will be presented.

Digital signal processing at Bell Labs-Foundations for speech and acoustics research

NASA Astrophysics Data System (ADS)

Rabiner, Lawrence R.

2004-05-01

Digital signal processing (DSP) is a fundamental tool for much of the research that has been carried out of Bell Labs in the areas of speech and acoustics research. The fundamental bases for DSP include the sampling theorem of Nyquist, the method for digitization of analog signals by Shannon et al., methods of spectral analysis by Tukey, the cepstrum by Bogert et al., and the FFT by Tukey (and Cooley of IBM). Essentially all of these early foundations of DSP came out of the Bell Labs Research Lab in the 1930s, 1940s, 1950s, and 1960s. This fundamental research was motivated by fundamental applications (mainly in the areas of speech, sonar, and acoustics) that led to novel design methods for digital filters (Kaiser, Golden, Rabiner, Schafer), spectrum analysis methods (Rabiner, Schafer, Allen, Crochiere), fast convolution methods based on the FFT (Helms, Bergland), and advanced digital systems used to implement telephony channel banks (Jackson, McDonald, Freeny, Tewksbury). This talk summarizes the key contributions to DSP made at Bell Labs, and illustrates how DSP was utilized in the areas of speech and acoustics research. It also shows the vast, worldwide impact of this DSP research on modern consumer electronics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Poivey, C.; Notebaert, O.; Garnier, P.

The ARIANE5 On Board Computer (OBC) and Inertial Reference System (SRI) are based on Motorola MC68020 processor and MC68882 coprocessor. The SRI data acquisition board also uses the DSP TMS320C25 from Texas Instruments. These devices were characterized to proton induced SEUs. But representativeness of SEU test results on processors was questioned during ARIANE5 studies. Protons test of these devices were also performed in the actual equipments with flight (or representative of) softwares. The results show that the On Board Computer and the Inertial Reference System can satisfy the requirements of the ARIANE5 missions.

BPSK Demodulation Using Digital Signal Processing

NASA Technical Reports Server (NTRS)

Garcia, Thomas R.

1996-01-01

A digital communications signal is a sinusoidal waveform that is modified by a binary (digital) information signal. The sinusoidal waveform is called the carrier. The carrier may be modified in amplitude, frequency, phase, or a combination of these. In this project a binary phase shift keyed (BPSK) signal is the communication signal. In a BPSK signal the phase of the carrier is set to one of two states, 180 degrees apart, by a binary (i.e., 1 or 0) information signal. A digital signal is a sampled version of a "real world" time continuous signal. The digital signal is generated by sampling the continuous signal at discrete points in time. The rate at which the signal is sampled is called the sampling rate (f(s)). The device that performs this operation is called an analog-to-digital (A/D) converter or a digitizer. The digital signal is composed of the sequence of individual values of the sampled BPSK signal. Digital signal processing (DSP) is the modification of the digital signal by mathematical operations. A device that performs this processing is called a digital signal processor. After processing, the digital signal may then be converted back to an analog signal using a digital-to-analog (D/A) converter. The goal of this project is to develop a system that will recover the digital information from a BPSK signal using DSP techniques. The project is broken down into the following steps: (1) Development of the algorithms required to demodulate the BPSK signal; (2) Simulation of the system; and (3) Implementation a BPSK receiver using digital signal processing hardware.

Execution of parallel algorithms on a heterogeneous multicomputer

NASA Astrophysics Data System (ADS)

Isenstein, Barry S.; Greene, Jonathon

1995-04-01

Many aerospace/defense sensing and dual-use applications require high-performance computing, extensive high-bandwidth interconnect and realtime deterministic operation. This paper will describe the architecture of a scalable multicomputer that includes DSP and RISC processors. A single chassis implementation is capable of delivering in excess of 10 GFLOPS of DSP processing power with 2 Gbytes/s of realtime sensor I/O. A software approach to implementing parallel algorithms called the Parallel Application System (PAS) is also presented. An example of applying PAS to a DSP application is shown.

Fast Fourier Transform Co-Processor (FFTC)- Towards Embedded GFLOPs

NASA Astrophysics Data System (ADS)

Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Wite, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland

2012-08-01

Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co- Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment.In frame of the ESA activity “Fast Fourier Transform DSP Co-processor (FFTC)” (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following:Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP.The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance.The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT- based processing tasks.A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses.The presentation will give and overview on the project, including the results of the validation of the FFTC ASIC prototypes.

Fast Fourier Transform Co-processor (FFTC), towards embedded GFLOPs

NASA Astrophysics Data System (ADS)

Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Witte, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland; Kopp, Nicholas

2012-10-01

Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co-Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment. In frame of the ESA activity "Fast Fourier Transform DSP Co-processor (FFTC)" (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following: • Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP. • The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance. The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT-based processing tasks. A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses. The paper will give an overview on the project, including the results of the validation of the FFTC ASIC prototypes.

On-board multicarrier demodulator for mobile applications using DSP implementation

NASA Astrophysics Data System (ADS)

Yim, W. H.; Kwan, C. C. D.; Coakley, F. P.; Evans, B. G.

1990-11-01

This paper describes the design and implementation of an on-board multicarrier demodulator using commercial digital signal processors. This is for use in a mobile satellite communication system employing an up-link SCPC/FDMA scheme. Channels are separated by a flexible multistage digital filter bank followed by a channel multiplexed digital demodulator array. The cross/dot product design approach of error detector leads to a new QPSK frequency control algorithm that allows fast acquisition without special preamble pattern. Timing correction is performed digitally using an extended stack of polyphase sub-filters.

CATAVIÑA: new infrared camera for OAN-SPM

NASA Astrophysics Data System (ADS)

Iriarte, Arturo; Cruz-González, Irene; Martínez, Luis A.; Tinoco, Silvio; Lara, Gerardo; Ruiz, Elfego; Sohn, Erika; Bernal, Abel; Angeles, Fernando; Moreno, Arturo; Murillo, Francisco; Langarica, Rosalía; Luna, Esteban; Salas, Luis; Cajero, Vicente

2006-06-01

CATAVIÑA is a near-infrared camera system to be operated in conjunction with the existing multi-purpose nearinfrared optical bench "CAMALEON" in OAN-SPM. Observing modes include direct imaging, spectroscopy, Fabry- Perot interferometry and polarimetry. This contribution focuses on the optomechanics and detector controller description of CATAVIÑA, which is planned to start operating later in 2006. The camera consists of an 8 inch LN2 dewar containing a 10 filter carousel, a radiation baffle and the detector circuit board mount. The system is based on a Rockwell 1024x1024 HgCdTe (HAWAII-I) FPA, operating in the 1 to 2.5 micron window. The detector controller/readout system was designed and developed at UNAM Instituto de Astronomia. It is based on five Texas Instruments DSK digital signal processor (DSP) modules. One module generates the detector and ADC-system control, while the remaining four are in charge of the acquisition of each of the detector's quadrants. Each DSP has a built-in expanded memory module in order to store more than one image. The detector read-out and signal driver subsystems are mounted onto the dewar in a "back-pack" fashion, each containing four independent pre-amplifiers, converters and signal drivers, that communicate through fiber optics with their respective DSPs. This system has the possibility of programming the offset input voltage and converter gain. The controller software architecture is based on a client/server model. The client sends commands through the TCP/IP protocol and acquires the image. The server consists of a microcomputer with an embedded Linux operating system, which runs the main program that receives the user commands and interacts with the timing and acquisition DSPs. The observer's interface allows for several readout and image processing modes.

Developing infrared array controller with software real time operating system

NASA Astrophysics Data System (ADS)

Sako, Shigeyuki; Miyata, Takashi; Nakamura, Tomohiko; Motohara, Kentaro; Uchimoto, Yuka Katsuno; Onaka, Takashi; Kataza, Hirokazu

2008-07-01

Real-time capabilities are required for a controller of a large format array to reduce a dead-time attributed by readout and data transfer. The real-time processing has been achieved by dedicated processors including DSP, CPLD, and FPGA devices. However, the dedicated processors have problems with memory resources, inflexibility, and high cost. Meanwhile, a recent PC has sufficient resources of CPUs and memories to control the infrared array and to process a large amount of frame data in real-time. In this study, we have developed an infrared array controller with a software real-time operating system (RTOS) instead of the dedicated processors. A Linux PC equipped with a RTAI extension and a dual-core CPU is used as a main computer, and one of the CPU cores is allocated to the real-time processing. A digital I/O board with DMA functions is used for an I/O interface. The signal-processing cores are integrated in the OS kernel as a real-time driver module, which is composed of two virtual devices of the clock processor and the frame processor tasks. The array controller with the RTOS realizes complicated operations easily, flexibly, and at a low cost.

An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

ERIC Educational Resources Information Center

Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

2010-01-01

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

The design and implementation of signal decomposition system of CL multi-wavelet transform based on DSP builder

NASA Astrophysics Data System (ADS)

Huang, Yan; Wang, Zhihui

2015-12-01

With the development of FPGA, DSP Builder is widely applied to design system-level algorithms. The algorithm of CL multi-wavelet is more advanced and effective than scalar wavelets in processing signal decomposition. Thus, a system of CL multi-wavelet based on DSP Builder is designed for the first time in this paper. The system mainly contains three parts: a pre-filtering subsystem, a one-level decomposition subsystem and a two-level decomposition subsystem. It can be converted into hardware language VHDL by the Signal Complier block that can be used in Quartus II. After analyzing the energy indicator, it shows that this system outperforms Daubenchies wavelet in signal decomposition. Furthermore, it has proved to be suitable for the implementation of signal fusion based on SoPC hardware, and it will become a solid foundation in this new field.

A Wireless Electronic Nose System Using a Fe2O3 Gas Sensing Array and Least Squares Support Vector Regression

PubMed Central

Song, Kai; Wang, Qi; Liu, Qi; Zhang, Hongquan; Cheng, Yingguo

2011-01-01

This paper describes the design and implementation of a wireless electronic nose (WEN) system which can online detect the combustible gases methane and hydrogen (CH4/H2) and estimate their concentrations, either singly or in mixtures. The system is composed of two wireless sensor nodes—a slave node and a master node. The former comprises a Fe2O3 gas sensing array for the combustible gas detection, a digital signal processor (DSP) system for real-time sampling and processing the sensor array data and a wireless transceiver unit (WTU) by which the detection results can be transmitted to the master node connected with a computer. A type of Fe2O3 gas sensor insensitive to humidity is developed for resistance to environmental influences. A threshold-based least square support vector regression (LS-SVR)estimator is implemented on a DSP for classification and concentration measurements. Experimental results confirm that LS-SVR produces higher accuracy compared with artificial neural networks (ANNs) and a faster convergence rate than the standard support vector regression (SVR). The designed WEN system effectively achieves gas mixture analysis in a real-time process. PMID:22346587

QI2S - Quick Image Interpretation System

NASA Astrophysics Data System (ADS)

Naghmouchi, Jamin; Aviely, Peleg; Ginosar, Ran; Ober, Giovanna; Bischoff, Ole; Nadler, Ron; Guiser, David; Citroen, Meira; Freddi, Riccardo; Berekovic, Mladen

2015-09-01

The evolution of the Earth Observation mission will be driven by many factors, and the deveploment of new processing paradigms to facilitate data downlink, handling and storage will be a key factor. Next generation EO satellites will generate a great amount of data at a very high data rate, both radar and optical. Real-time onboard processing can be the solution to reduce data downlink and management on ground. Radiometric, geometric, and atmospheric corrections of EO data as well as material/object detection in addition to the well-known needs for image compression and signal processing can be performed directly on board and the aim of QI2S project is to demonstrate this. QI2S, a concept prototype system for novel onboard image processing and image interpretation which has been designed, developed and validated in the framework of an EU FP7 project, targets these needs and makes a significant step towards exceeding current roadmaps of leading space agencies for future payload processors. The QI2S system features multiple chip components of the RC64, a novel rad-hard 64-core signal processing chip, which targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. It integrates advanced DSP cores with a multibank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high-speed serial links using SpaceFibre and other protocols. The processor is being developed within the European FP7 Framework Program and will be qualified to the highest space standards.

Design, characterization and control of the Unique Mobility Corporation robot

NASA Technical Reports Server (NTRS)

Velasco, Virgilio B., Jr.; Newman, Wyatt S.; Steinetz, Bruce; Kopf, Carlo; Malik, John

1994-01-01

Space and mass are at a premium on any space mission, and thus any machinery designed for space use should be lightweight and compact, without sacrificing strength. It is for this reason that NASA/LeRC contracted Unique Mobility Corporation to exploit their novel actuator designs to build a robot that would advance the present state of technology with respect to these requirements. Custom-designed motors are the key feature of this robot. They are compact, high-performance dc brushless servo motors with a high pole count and low inductance, thus permitting high torque generation and rapid phase commutation. Using a custom-designed digital signal processor-based controller board, the pulse width modulation power amplifiers regulate the fast dynamics of the motor currents. In addition, the programmable digital signal processor (DSP) controller permits implementation of nonlinear compensation algorithms to account for motoring vs. regeneration, torque ripple, and back-EMF. As a result, the motors produce a high torque relative to their size and weight, and can do so with good torque regulation and acceptably high velocity saturation limits. This paper presents the Unique Mobility Corporation robot prototype: its actuators, its kinematic design, its control system, and its experimental characterization. Performance results, including saturation torques, saturation velocities and tracking accuracy tests are included.

LIBS data analysis using a predictor-corrector based digital signal processor algorithm

NASA Astrophysics Data System (ADS)

Sanders, Alex; Griffin, Steven T.; Robinson, Aaron

2012-06-01

There are many accepted sensor technologies for generating spectra for material classification. Once the spectra are generated, communication bandwidth limitations favor local material classification with its attendant reduction in data transfer rates and power consumption. Transferring sensor technologies such as Cavity Ring-Down Spectroscopy (CRDS) and Laser Induced Breakdown Spectroscopy (LIBS) require effective material classifiers. A result of recent efforts has been emphasis on Partial Least Squares - Discriminant Analysis (PLS-DA) and Principle Component Analysis (PCA). Implementation of these via general purpose computers is difficult in small portable sensor configurations. This paper addresses the creation of a low mass, low power, robust hardware spectra classifier for a limited set of predetermined materials in an atmospheric matrix. Crucial to this is the incorporation of PCA or PLS-DA classifiers into a predictor-corrector style implementation. The system configuration guarantees rapid convergence. Software running on multi-core Digital Signal Processor (DSPs) simulates a stream-lined plasma physics model estimator, reducing Analog-to-Digital (ADC) power requirements. This paper presents the results of a predictorcorrector model implemented on a low power multi-core DSP to perform substance classification. This configuration emphasizes the hardware system and software design via a predictor corrector model that simultaneously decreases the sample rate while performing the classification.

High-resolution streaming video integrated with UGS systems

NASA Astrophysics Data System (ADS)

Rohrer, Matthew

2010-04-01

Imagery has proven to be a valuable complement to Unattended Ground Sensor (UGS) systems. It provides ultimate verification of the nature of detected targets. However, due to the power, bandwidth, and technological limitations inherent to UGS, sacrifices have been made to the imagery portion of such systems. The result is that these systems produce lower resolution images in small quantities. Currently, a high resolution, wireless imaging system is being developed to bring megapixel, streaming video to remote locations to operate in concert with UGS. This paper will provide an overview of how using Wifi radios, new image based Digital Signal Processors (DSP) running advanced target detection algorithms, and high resolution cameras gives the user an opportunity to take high-powered video imagers to areas where power conservation is a necessity.

Development of Coriolis mass flowmeter with digital drive and signal processing technology.

PubMed

Hou, Qi-Li; Xu, Ke-Jun; Fang, Min; Liu, Cui; Xiong, Wen-Jun

2013-09-01

Coriolis mass flowmeter (CMF) often suffers from two-phase flowrate which may cause flowtube stalling. To solve this problem, a digital drive method and a digital signal processing method of CMF is studied and implemented in this paper. A positive-negative step signal is used to initiate the flowtube oscillation without knowing the natural frequency of the flowtube. A digital zero-crossing detection method based on Lagrange interpolation is adopted to calculate the frequency and phase difference of the sensor output signals in order to synthesize the digital drive signal. The digital drive approach is implemented by a multiplying digital to analog converter (MDAC) and a direct digital synthesizer (DDS). A digital Coriolis mass flow transmitter is developed with a digital signal processor (DSP) to control the digital drive, and realize the signal processing. Water flow calibrations and gas-liquid two-phase flowrate experiments are conducted to examine the performance of the transmitter. The experimental results show that the transmitter shortens the start-up time and can maintain the oscillation of flowtube in two-phase flowrate condition. Copyright © 2013 ISA. Published by Elsevier Ltd. All rights reserved.

Research on numerical control system based on S3C2410 and MCX314AL

NASA Astrophysics Data System (ADS)

Ren, Qiang; Jiang, Tingbiao

2008-10-01

With the rapid development of micro-computer technology, embedded system, CNC technology and integrated circuits, numerical control system with powerful functions can be realized by several high-speed CPU chips and RISC (Reduced Instruction Set Computing) chips which have small size and strong stability. In addition, the real-time operating system also makes the attainment of embedded system possible. Developing the NC system based on embedded technology can overcome some shortcomings of common PC-based CNC system, such as the waste of resources, low control precision, low frequency and low integration. This paper discusses a hardware platform of ENC (Embedded Numerical Control) system based on embedded processor chip ARM (Advanced RISC Machines)-S3C2410 and DSP (Digital Signal Processor)-MCX314AL and introduces the process of developing ENC system software. Finally write the MCX314AL's driver under the embedded Linux operating system. The embedded Linux operating system can deal with multitask well moreover satisfy the real-time and reliability of movement control. NC system has the advantages of best using resources and compact system with embedded technology. It provides a wealth of functions and superior performance with a lower cost. It can be sure that ENC is the direction of the future development.

High Resolution Imaging Testbed Utilizing Sodium Laser Guide Star Adaptive Optics: The Real Time Wavefront Reconstructor Computer

DTIC Science & Technology

2008-07-31

Unlike the Lyrtech, each DSP on a Bittware board offers 3 MB of on-chip memory and 3 GFLOPs of 32-bit peak processing power. Based on the performance...Each NVIDIA 8800 Ultra features 576 GFLOPS on 128 612-MHz single-precision floating-point SIMD processors, arranged in 16 clusters of eight. Each

Method and apparatus for optical encoding with compressible imaging

NASA Technical Reports Server (NTRS)

Leviton, Douglas B. (Inventor)

2006-01-01

The present invention presents an optical encoder with increased conversion rates. Improvement in the conversion rate is a result of combining changes in the pattern recognition encoder's scale pattern with an image sensor readout technique which takes full advantage of those changes, and lends itself to operation by modern, high-speed, ultra-compact microprocessors and digital signal processors (DSP) or field programmable gate array (FPGA) logic elements which can process encoder scale images at the highest speeds. Through these improvements, all three components of conversion time (reciprocal conversion rate)--namely exposure time, image readout time, and image processing time--are minimized.

Control of automated behavior: insights from the discrete sequence production task

PubMed Central

Abrahamse, Elger L.; Ruitenberg, Marit F. L.; de Kleine, Elian; Verwey, Willem B.

2013-01-01

Work with the discrete sequence production (DSP) task has provided a substantial literature on discrete sequencing skill over the last decades. The purpose of the current article is to provide a comprehensive overview of this literature and of the theoretical progress that it has prompted. We start with a description of the DSP task and the phenomena that are typically observed with it. Then we propose a cognitive model, the dual processor model (DPM), which explains performance of (skilled) discrete key-press sequences. Key features of this model are the distinction between a cognitive processor and a motor system (i.e., motor buffer and motor processor), the interplay between these two processing systems, and the possibility to execute familiar sequences in two different execution modes. We further discuss how this model relates to several related sequence skill research paradigms and models, and we outline outstanding questions for future research throughout the paper. We conclude by sketching a tentative neural implementation of the DPM. PMID:23515430

Field oriented control of induction motors

NASA Technical Reports Server (NTRS)

Burrows, Linda M.; Zinger, Don S.; Roth, Mary Ellen

1990-01-01

Induction motors have always been known for their simple rugged construction, but until lately were not suitable for variable speed or servo drives due to the inherent complexity of the controls. With the advent of field oriented control (FOC), however, the induction motor has become an attractive option for these types of drive systems. An FOC system which utilizes the pulse population modulation method to synthesize the motor drive frequencies is examined. This system allows for a variable voltage to frequency ratio and enables the user to have independent control of both the speed and torque of an induction motor. A second generation of the control boards were developed and tested with the next point of focus being the minimization of the size and complexity of these controls. Many options were considered with the best approach being the use of a digital signal processor (DSP) due to its inherent ability to quickly evaluate control algorithms. The present test results of the system and the status of the optimization process using a DSP are discussed.

Compilation time analysis to minimize run-time overhead in preemptive scheduling on multiprocessors

NASA Astrophysics Data System (ADS)

Wauters, Piet; Lauwereins, Rudy; Peperstraete, J.

1994-10-01

This paper describes a scheduling method for hard real-time Digital Signal Processing (DSP) applications, implemented on a multi-processor. Due to the very high operating frequencies of DSP applications (typically hundreds of kHz) runtime overhead should be kept as small as possible. Because static scheduling introduces very little run-time overhead it is used as much as possible. Dynamic pre-emption of tasks is allowed if and only if it leads to better performance in spite of the extra run-time overhead. We essentially combine static scheduling with dynamic pre-emption using static priorities. Since we are dealing with hard real-time applications we must be able to guarantee at compile-time that all timing requirements will be satisfied at run-time. We will show that our method performs at least as good as any static scheduling method. It also reduces the total amount of dynamic pre-emptions compared with run time methods like deadline monotonic scheduling.

The impact of Moore's Law and loss of Dennard scaling: Are DSP SoCs an energy efficient alternative to x86 SoCs?

NASA Astrophysics Data System (ADS)

Johnsson, L.; Netzer, G.

2016-10-01

Moore's law, the doubling of transistors per unit area for each CMOS technology generation, is expected to continue throughout the decade, while Dennard voltage scaling resulting in constant power per unit area stopped about a decade ago. The semiconductor industry's response to the loss of Dennard scaling and the consequent challenges in managing power distribution and dissipation has been leveled off clock rates, a die performance gain reduced from about a factor of 2.8 to 1.4 per technology generation, and multi-core processor dies with increased cache sizes. Increased caches sizes offers performance benefits for many applications as well as energy savings. Accessing data in cache is considerably more energy efficient than main memory accesses. Further, caches consume less power than a corresponding amount of functional logic. As feature sizes continue to be scaled down an increasing fraction of the die must be “underutilized” or “dark” due to power constraints. With power being a prime design constraint there is a concerted effort to find significantly more energy efficient chip architectures than dominant in servers today, with chips potentially incorporating several types of cores to cover a range of applications, or different functions in an application, as is already common for the mobile processor market. Digital Signal Processors (DSPs), largely targeting the embedded and mobile processor markets, typically have been designed for a power consumption of 10% or less of a typical x86 CPU, yet with much more than 10% of the floating-point capability of the same technology generation x86 CPUs. Thus, DSPs could potentially offer an energy efficient alternative to x86 CPUs. Here we report an assessment of the Texas Instruments TMS320C6678 DSP in regards to its energy efficiency for two common HPC benchmarks: STREAM (memory system benchmark) and HPL (CPU benchmark)

Implementation theory of distortion-invariant pattern recognition for optical and digital signal processing systems

NASA Astrophysics Data System (ADS)

Lhamon, Michael Earl

A pattern recognition system which uses complex correlation filter banks requires proportionally more computational effort than single-real valued filters. This introduces increased computation burden but also introduces a higher level of parallelism, that common computing platforms fail to identify. As a result, we consider algorithm mapping to both optical and digital processors. For digital implementation, we develop computationally efficient pattern recognition algorithms, referred to as, vector inner product operators that require less computational effort than traditional fast Fourier methods. These algorithms do not need correlation and they map readily onto parallel digital architectures, which imply new architectures for optical processors. These filters exploit circulant-symmetric matrix structures of the training set data representing a variety of distortions. By using the same mathematical basis as with the vector inner product operations, we are able to extend the capabilities of more traditional correlation filtering to what we refer to as "Super Images". These "Super Images" are used to morphologically transform a complicated input scene into a predetermined dot pattern. The orientation of the dot pattern is related to the rotational distortion of the object of interest. The optical implementation of "Super Images" yields feature reduction necessary for using other techniques, such as artificial neural networks. We propose a parallel digital signal processor architecture based on specific pattern recognition algorithms but general enough to be applicable to other similar problems. Such an architecture is classified as a data flow architecture. Instead of mapping an algorithm to an architecture, we propose mapping the DSP architecture to a class of pattern recognition algorithms. Today's optical processing systems have difficulties implementing full complex filter structures. Typically, optical systems (like the 4f correlators) are limited to phase-only implementation with lower detection performance than full complex electronic systems. Our study includes pseudo-random pixel encoding techniques for approximating full complex filtering. Optical filter bank implementation is possible and they have the advantage of time averaging the entire filter bank at real time rates. Time-averaged optical filtering is computational comparable to billions of digital operations-per-second. For this reason, we believe future trends in high speed pattern recognition will involve hybrid architectures of both optical and DSP elements.

Design of Small MEMS Microphone Array Systems for Direction Finding of Outdoors Moving Vehicles

PubMed Central

Zhang, Xin; Huang, Jingchang; Song, Enliang; Liu, Huawei; Li, Baoqing; Yuan, Xiaobing

2014-01-01

In this paper, a MEMS microphone array system scheme is proposed which implements real-time direction of arrival (DOA) estimation for moving vehicles. Wind noise is the primary source of unwanted noise on microphones outdoors. A multiple signal classification (MUSIC) algorithm is used in this paper for direction finding associated with spatial coherence to discriminate between the wind noise and the acoustic signals of a vehicle. The method is implemented in a SHARC DSP processor and the real-time estimated DOA is uploaded through Bluetooth or a UART module. Experimental results in different places show the validity of the system and the deviation is no bigger than 6° in the presence of wind noise. PMID:24603636

Design of small MEMS microphone array systems for direction finding of outdoors moving vehicles.

PubMed

Zhang, Xin; Huang, Jingchang; Song, Enliang; Liu, Huawei; Li, Baoqing; Yuan, Xiaobing

2014-03-05

In this paper, a MEMS microphone array system scheme is proposed which implements real-time direction of arrival (DOA) estimation for moving vehicles. Wind noise is the primary source of unwanted noise on microphones outdoors. A multiple signal classification (MUSIC) algorithm is used in this paper for direction finding associated with spatial coherence to discriminate between the wind noise and the acoustic signals of a vehicle. The method is implemented in a SHARC DSP processor and the real-time estimated DOA is uploaded through Bluetooth or a UART module. Experimental results in different places show the validity of the system and the deviation is no bigger than 6° in the presence of wind noise.

Effects of recombinant dentin sialoprotein in dental pulp cells.

PubMed

Lee, S-Y; Kim, S-Y; Park, S-H; Kim, J-J; Jang, J-H; Kim, E-C

2012-04-01

Dentin sialophosphoprotein (DSPP) is critical for dentin mineralization. However, the function of dentin sialoprotein (DSP), the cleaved product of DSPP, remains unclear. This study aimed to investigate the signal transduction pathways and effects of recombinant human DSP (rh-DSP) on proliferation, migration, and odontoblastic differentiation in human dental pulp cells (HDPCs). The exogenous addition of rh-DSP enhanced the proliferation and migration of HDPCs in dose- and time-dependent manners. rh-DSP markedly increased ALP activity, calcium nodule formation, and levels of odontoblastic marker mRNA. rh-DSP increased BMP-2 expression and Smad1/5/8 phosphorylation, which was blocked by the BMP antagonist, noggin. Furthermore, rh-DSP phosphorylated extracellular signal-regulated kinase (ERK), c-Jun N-terminal kinase (JNK), Akt, and IκB-α, and induced the nuclear translocation of the NF-κB p65 subunit. Analysis of these data demonstrates a novel signaling function of rh-DSP for the promotion of growth, migration, and differentiation in HDPCS via the BMP/Smad, JNK, ERK, MAPK, and NF-κB signaling pathways, suggesting that rh-DSP may have therapeutic utility in dentin regeneration or dental pulp tissue engineering.

A low-cost FMCW radar for footprint detection from a mobile platform

NASA Astrophysics Data System (ADS)

Boutte, David; Taylor, Paul; Hunt, Allan

2015-05-01

Footprint and human trail detection in rugged all-weather environments is an important and challenging problem for perimeter security, passive surveillance and reconnaissance. To address this challenge a low-cost, wideband, frequency-modulated continuous wave (FMCW) radar operating at 33.4GHz - 35.5GHz is being developed through a Department of Homeland Security Science and Technology Directorate Phase I SBIR and has been experimentally demonstrated to be capable of detecting footprints and footprint trails on unimproved roads in an experimental setting. It uses a low-cost digital signal processor (DSP) that makes important operating parameters reconfigurable and allows for frequency sweep linearization, a key technique developed to increase footprint signal-to-noise ratio (SNR). This paper discusses the design, DSP implementation and experimental results of a low-cost FMCW radar for mobile footprint detection. A technique for wideband sweep linearization is detailed along with system performance metrics and experimental results showing receive-SNR from footprint trails in sand and on unimproved dirt roads. Results from a second stepped frequency CW (SFCW) Ka-band system are also shown, verifying the ability of both systems to detect footprints and footprint trails in an experimental setting. The results show that there is sufficient receive-SNR to detect even shallow footprints (~1cm) using a radar based detection system in Ka-band. Field experimental results focus on system proof of concept from a static position with mobile results also presented highlighting necessary improvements to both systems.

Digital Intermediate Frequency Receiver Module For Use In Airborne Sar Applications

DOEpatents

Tise, Bertice L.; Dubbert, Dale F.

2005-03-08

A digital IF receiver (DRX) module directly compatible with advanced radar systems such as synthetic aperture radar (SAR) systems. The DRX can combine a 1 G-Sample/sec 8-bit ADC with high-speed digital signal processor, such as high gate-count FPGA technology or ASICs to realize a wideband IF receiver. DSP operations implemented in the DRX can include quadrature demodulation and multi-rate, variable-bandwidth IF filtering. Pulse-to-pulse (Doppler domain) filtering can also be implemented in the form of a presummer (accumulator) and an azimuth prefilter. An out of band noise source can be employed to provide a dither signal to the ADC, and later be removed by digital signal processing. Both the range and Doppler domain filtering operations can be implemented using a unique pane architecture which allows on-the-fly selection of the filter decimation factor, and hence, the filter bandwidth. The DRX module can include a standard VME-64 interface for control, status, and programming. An interface can provide phase history data to the real-time image formation processors. A third front-panel data port (FPDP) interface can send wide bandwidth, raw phase histories to a real-time phase history recorder for ground processing.

ELITE-3 active vibration isolation workstation

NASA Astrophysics Data System (ADS)

Anderson, Eric H.; Houghton, Bowie

2001-06-01

This paper describes the development and capabilities of ELITE-3, a product that incorporates piezoelectric actuators to provide ultrastable work surfaces for very high resolution wafer production, metrology, microscopy, and other applications. The electromechanical, electronic, and software/firmware parts of the ELITE-3 active workstation are described, with an emphasis on considerations relating to the piezoelectric transducers. Performance of the system and its relation to the smart materials is discussed. As the floor beneath a vibration-sensitive instrument supported by ELITE-3 moves, piezoelectrics are controlled to minimize the motion of the instrument. A digital signal processor (DSP) determines the appropriate signals to apply to the actuators. A PC-based interface allows reprogramming of control algorithms and resetting of other parameters within the firmware. The modular product allows incorporation of vibration isolator, actuator and sensor modules into original equipment manufacturer (OEM) products. Alternatively, a workstation can be integrated as an integrated standalone system. The paper describes the system architecture, overall approach to vibration isolation, and various system components, and summarizes motivations for key design approaches.

Pre-Hardware Optimization of Spacecraft Image Processing Algorithms and Hardware Implementation

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Petrick, David J.; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Day, John H. (Technical Monitor)

2002-01-01

Spacecraft telemetry rates and telemetry product complexity have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image data processing and color picture generation application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The proposed solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms, and reconfigurable computing hardware (RC) technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processors (DSP). It has been shown that this approach can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft.

Digital Low Level RF Systems for Fermilab Main Ring and Tevatron

NASA Astrophysics Data System (ADS)

Chase, B.; Barnes, B.; Meisner, K.

1997-05-01

At Fermilab, a new Low Level RF system is successfully installed and operating in the Main Ring. Installation is proceeding for a Tevatron system. This upgrade replaces aging CAMAC/NIM components for an increase in accuracy, reliability, and flexibility. These VXI systems are based on a custom three channel direct digital synthesizer(DDS) module. Each synthesizer channel is capable of independent or ganged operation for both frequency and phase modulation. New frequency and phase values are computed at a 100kHz rate on the module's Analog Devices ADSP21062 (SHARC) digital signal processor. The DSP concurrently handles feedforward, feedback, and beam manipulations. Higher level state machines and the control system interface are handled at the crate level using the VxWorks operating system. This paper discusses the hardware, software and operational aspects of these LLRF systems.

DDGIPS: a general image processing system in robot vision

NASA Astrophysics Data System (ADS)

Tian, Yuan; Ying, Jun; Ye, Xiuqing; Gu, Weikang

2000-10-01

Real-Time Image Processing is the key work in robot vision. With the limitation of the hardware technique, many algorithm-oriented firmware systems were designed in the past. But their architectures were not flexible enough to achieve a multi-algorithm development system. Because of the rapid development of microelectronics technique, many high performance DSP chips and high density FPGA chips have come to life, and this makes it possible to construct a more flexible architecture in real-time image processing system. In this paper, a Double DSP General Image Processing System (DDGIPS) is concerned. We try to construct a two-DSP-based FPGA-computational system with two TMS320C6201s. The TMS320C6x devices are fixed-point processors based on the advanced VLIW CPU, which has eight functional units, including two multipliers and six arithmetic logic units. These features make C6x a good candidate for a general purpose system. In our system, the two TMS320C6201s each has a local memory space, and they also have a shared system memory space which enables them to intercommunicate and exchange data efficiently. At the same time, they can be directly inter-connected in star-shaped architecture. All of these are under the control of a FPGA group. As the core of the system, FPGA plays a very important role: it takes charge of DPS control, DSP communication, memory space access arbitration and the communication between the system and the host machine. And taking advantage of reconfiguring FPGA, all of the interconnection between the two DSP or between DSP and FPGA can be changed. In this way, users can easily rebuild the real-time image processing system according to the data stream and the task of the application and gain great flexibility.

DDGIPS: a general image processing system in robot vision

NASA Astrophysics Data System (ADS)

Tian, Yuan; Ying, Jun; Ye, Xiuqing; Gu, Weikang

2000-10-01

Real-Time Image Processing is the key work in robot vision. With the limitation of the hardware technique, many algorithm-oriented firmware systems were designed in the past. But their architectures were not flexible enough to achieve a multi- algorithm development system. Because of the rapid development of microelectronics technique, many high performance DSP chips and high density FPGA chips have come to life, and this makes it possible to construct a more flexible architecture in real-time image processing system. In this paper, a Double DSP General Image Processing System (DDGIPS) is concerned. We try to construct a two-DSP-based FPGA-computational system with two TMS320C6201s. The TMS320C6x devices are fixed-point processors based on the advanced VLIW CPU, which has eight functional units, including two multipliers and six arithmetic logic units. These features make C6x a good candidate for a general purpose system. In our system, the two TMS320C6210s each has a local memory space, and they also have a shared system memory space which enable them to intercommunicate and exchange data efficiently. At the same time, they can be directly interconnected in star- shaped architecture. All of these are under the control of FPGA group. As the core of the system, FPGA plays a very important role: it takes charge of DPS control, DSP communication, memory space access arbitration and the communication between the system and the host machine. And taking advantage of reconfiguring FPGA, all of the interconnection between the two DSP or between DSP and FPGA can be changed. In this way, users can easily rebuild the real-time image processing system according to the data stream and the task of the application and gain great flexibility.

CMOS Image Sensor with a Built-in Lane Detector.

PubMed

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Advanced one-dimensional optical strain measurement system, phase 4

NASA Technical Reports Server (NTRS)

Lant, Christian T.

1992-01-01

An improved version of the speckle-shift strain measurement system was developed. The system uses a two-dimensional sensor array to maintain speckle correlation in the presence of large off-axis rigid body motions. A digital signal processor (DSP) is used to calculate strains at a rate near the RS-170 camera frame rate. Strain measurements were demonstrated on small diameter wires and fibers used in composite materials research. Accurate values of Young's modulus were measured on tungsten wires, and silicon carbide and sapphire fibers. This optical technique has measured surface strains at specimen temperatures above 750 C and has shown the potential for measurements at much higher temperatures.

What does voice-processing technology support today?

PubMed Central

Nakatsu, R; Suzuki, Y

1995-01-01

This paper describes the state of the art in applications of voice-processing technologies. In the first part, technologies concerning the implementation of speech recognition and synthesis algorithms are described. Hardware technologies such as microprocessors and DSPs (digital signal processors) are discussed. Software development environment, which is a key technology in developing applications software, ranging from DSP software to support software also is described. In the second part, the state of the art of algorithms from the standpoint of applications is discussed. Several issues concerning evaluation of speech recognition/synthesis algorithms are covered, as well as issues concerning the robustness of algorithms in adverse conditions. Images Fig. 3 PMID:7479720

Distributed Two-Dimensional Fourier Transforms on DSPs with an Application for Phase Retrieval

NASA Technical Reports Server (NTRS)

Smith, Jeffrey Scott

2006-01-01

Many applications of two-dimensional Fourier Transforms require fixed timing as defined by system specifications. One example is image-based wavefront sensing. The image-based approach has many benefits, yet it is a computational intensive solution for adaptive optic correction, where optical adjustments are made in real-time to correct for external (atmospheric turbulence) and internal (stability) aberrations, which cause image degradation. For phase retrieval, a type of image-based wavefront sensing, numerous two-dimensional Fast Fourier Transforms (FFTs) are used. To meet the required real-time specifications, a distributed system is needed, and thus, the 2-D FFT necessitates an all-to-all communication among the computational nodes. The 1-D floating point FFT is very efficient on a digital signal processor (DSP). For this study, several architectures and analysis of such are presented which address the all-to-all communication with DSPs. Emphasis of this research is on a 64-node cluster of Analog Devices TigerSharc TS-101 DSPs.

Ambulatory REACT: real-time seizure detection with a DSP microprocessor.

PubMed

McEvoy, Robert P; Faul, Stephen; Marnane, William P

2010-01-01

REACT (Real-Time EEG Analysis for event deteCTion) is a Support Vector Machine based technology which, in recent years, has been successfully applied to the problem of automated seizure detection in both adults and neonates. This paper describes the implementation of REACT on a commercial DSP microprocessor; the Analog Devices Blackfin®. The primary aim of this work is to develop a prototype system for use in ambulatory or in-ward automated EEG analysis. Furthermore, the complexity of the various stages of the REACT algorithm on the Blackfin processor is analysed; in particular the EEG feature extraction stages. This hardware profile is used to select a reduced, platform-aware feature set, in order to evaluate the seizure classification accuracy of a lower-complexity, lower-power REACT system.

The design of multi-core DSP parallel model based on message passing and multi-level pipeline

NASA Astrophysics Data System (ADS)

Niu, Jingyu; Hu, Jian; He, Wenjing; Meng, Fanrong; Li, Chuanrong

2017-10-01

Currently, the design of embedded signal processing system is often based on a specific application, but this idea is not conducive to the rapid development of signal processing technology. In this paper, a parallel processing model architecture based on multi-core DSP platform is designed, and it is mainly suitable for the complex algorithms which are composed of different modules. This model combines the ideas of multi-level pipeline parallelism and message passing, and summarizes the advantages of the mainstream model of multi-core DSP (the Master-Slave model and the Data Flow model), so that it has better performance. This paper uses three-dimensional image generation algorithm to validate the efficiency of the proposed model by comparing with the effectiveness of the Master-Slave and the Data Flow model.

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Design of overload vehicle monitoring and response system based on DSP

NASA Astrophysics Data System (ADS)

Yu, Yan; Liu, Yiheng; Zhao, Xuefeng

2014-03-01

The overload vehicles are making much more damage to the road surface than the regular ones. Many roads and bridges are equipped with structural health monitoring system (SHM) to provide early-warning to these damage and evaluate the safety of road and bridge. However, because of the complex nature of SHM system, it's expensive to manufacture, difficult to install and not well-suited for the regular bridges and roads. Based on this application background, this paper designs a compact structural health monitoring system based on DSP, which is highly integrated, low-power, easy to install and inexpensive to manufacture. The designed system is made up of sensor arrays, the charge amplifier module, the DSP processing unit, the alarm system for overload, and the estimate for damage of the road and bridge structure. The signals coming from sensor arrays go through the charge amplifier. DSP processing unit will receive the amplified signals, estimate whether it is an overload signal or not, and convert analog variables into digital ones so that they are compatible with the back-end digital circuit for further processing. The system will also restrict certain vehicles that are overweight, by taking image of the car brand, sending the alarm, and transferring the collected pressure data to remote data center for further monitoring analysis by rain-flow counting method.

Laser Speckle Imaging of Cerebral Blood Flow

NASA Astrophysics Data System (ADS)

Luo, Qingming; Jiang, Chao; Li, Pengcheng; Cheng, Haiying; Wang, Zhen; Wang, Zheng; Tuchin, Valery V.

Monitoring the spatio-temporal characteristics of cerebral blood flow (CBF) is crucial for studying the normal and pathophysiologic conditions of brain metabolism. By illuminating the cortex with laser light and imaging the resulting speckle pattern, relative CBF images with tens of microns spatial and millisecond temporal resolution can be obtained. In this chapter, a laser speckle imaging (LSI) method for monitoring dynamic, high-resolution CBF is introduced. To improve the spatial resolution of current LSI, a modified LSI method is proposed. To accelerate the speed of data processing, three LSI data processing frameworks based on graphics processing unit (GPU), digital signal processor (DSP), and field-programmable gate array (FPGA) are also presented. Applications for detecting the changes in local CBF induced by sensory stimulation and thermal stimulation, the influence of a chemical agent on CBF, and the influence of acute hyperglycemia following cortical spreading depression on CBF are given.

A method of incident angle estimation for high resolution spectral recovery in filter-array-based spectrometers

NASA Astrophysics Data System (ADS)

Kim, Cheolsun; Lee, Woong-Bi; Ju, Gun Wu; Cho, Jeonghoon; Kim, Seongmin; Oh, Jinkyung; Lim, Dongsung; Lee, Yong Tak; Lee, Heung-No

2017-02-01

In recent years, there has been an increasing interest in miniature spectrometers for research and development. Especially, filter-array-based spectrometers have advantages of low cost and portability, and can be applied in various fields such as biology, chemistry and food industry. Miniaturization in optical filters causes degradation of spectral resolution due to limitations on spectral responses and the number of filters. Nowadays, many studies have been reported that the filter-array-based spectrometers have achieved resolution improvements by using digital signal processing (DSP) techniques. The performance of the DSP-based spectral recovery highly depends on the prior information of transmission functions (TFs) of the filters. The TFs vary with respect to an incident angle of light onto the filter-array. Conventionally, it is assumed that the incident angle of light on the filters is fixed and the TFs are known to the DSP. However, the incident angle is inconstant according to various environments and applications, and thus TFs also vary, which leads to performance degradation of spectral recovery. In this paper, we propose a method of incident angle estimation (IAE) for high resolution spectral recovery in the filter-array-based spectrometers. By exploiting sparse signal reconstruction of the L1- norm minimization, IAE estimates an incident angle among all possible incident angles which minimizes the error of the reconstructed signal. Based on IAE, DSP effectively provides a high resolution spectral recovery in the filter-array-based spectrometers.

Advanced digital signal processing for short-haul and access network

NASA Astrophysics Data System (ADS)

Zhang, Junwen; Yu, Jianjun; Chi, Nan

2016-02-01

Digital signal processing (DSP) has been proved to be a successful technology recently in high speed and high spectrum-efficiency optical short-haul and access network, which enables high performances based on digital equalizations and compensations. In this paper, we investigate advanced DSP at the transmitter and receiver side for signal pre-equalization and post-equalization in an optical access network. A novel DSP-based digital and optical pre-equalization scheme has been proposed for bandwidth-limited high speed short-distance communication system, which is based on the feedback of receiver-side adaptive equalizers, such as least-mean-squares (LMS) algorithm and constant or multi-modulus algorithms (CMA, MMA). Based on this scheme, we experimentally demonstrate 400GE on a single optical carrier based on the highest ETDM 120-GBaud PDM-PAM-4 signal, using one external modulator and coherent detection. A line rate of 480-Gb/s is achieved, which enables 20% forward-error correction (FEC) overhead to keep the 400-Gb/s net information rate. The performance after fiber transmission shows large margin for both short range and metro/regional networks. We also extend the advanced DSP for short haul optical access networks by using high order QAMs. We propose and demonstrate a high speed multi-band CAP-WDM-PON system on intensity modulation, direct detection and digital equalizations. A hybrid modified cascaded MMA post-equalization schemes are used to equalize the multi-band CAP-mQAM signals. Using this scheme, we successfully demonstrates 550Gb/s high capacity WDMPON system with 11 WDM channels, 55 sub-bands, and 10-Gb/s per user in the downstream over 40-km SMF.

Communication-Driven Codesign for Multiprocessor Systems

DTIC Science & Technology

2004-01-01

processors, FPGA or ASIC subsystems, mi- croprocessors, and microcontrollers. When a processor is embedded within a SLOT architecture, one or more...Broderson, Low-power CMOS digital design, IEEE Journal of Solid-State Circuits 27 (1992), no. 4, 473–484. [25] L. Chao and E. Sha , Scheduling data-flow...1997), 239– 256 . [82] P. K. Murthy, E. G. Cohen, and S. Rowland, System Canvas: A new design en- vironment for embedded DSP and telecommunications

[Research on automatic external defibrillator based on DSP].

PubMed

Jing, Jun; Ding, Jingyan; Zhang, Wei; Hong, Wenxue

2012-10-01

Electrical defibrillation is the most effective way to treat the ventricular tachycardia (VT) and ventricular fibrillation (VF). An automatic external defibrillator based on DSP is introduced in this paper. The whole design consists of the signal collection module, the microprocessor controlingl module, the display module, the defibrillation module and the automatic recognition algorithm for VF and non VF, etc. This automatic external defibrillator has achieved goals such as ECG signal real-time acquisition, ECG wave synchronous display, data delivering to U disk and automatic defibrillate when shockable rhythm appears, etc.

The Dentin Sialoprotein (DSP) Domain Regulates Dental Mesenchymal Cell Differentiation through a Novel Surface Receptor

PubMed Central

Wan, Chunyan; Yuan, Guohua; Luo, Daoshu; Zhang, Lu; Lin, Heng; Liu, Huan; Chen, Lei; Yang, Guobin; Chen, Shuo; Chen, Zhi

2016-01-01

Dentin sialophosphoprotein (DSPP) is a dentin extracellular matrix protein that is processed into dentin sialoprotein (DSP), dentin glycoprotein (DGP) and dentin phosphoprotein (DPP). DSP is mainly expressed in odontoblasts. We hypothesized that DSP interacts with cell surface receptors and subsequently activates intracellular signaling. Using DSP as bait for screening a protein library, we demonstrate that DSP acts as a ligand and binds to integrin β6. The 36 amino acid residues of DSP are sufficient to bind to integrin β6. This peptide promoted cell attachment, migration, differentiation and mineralization of dental mesenchymal cells. In addition, DSP aa183-219 stimulated phosphorylation of ERK1/2 and P38 kinases. This activation was inhibited by an anti-integrin β6 antibody and siRNA. Furthermore, we demonstrate that this DSP fragment induces SMAD1/5/8 phosphorylation and nuclear translocation via ERK1/2 and P38 signaling. SMAD1/5/8 binds to SMAD binding elements (SBEs) in the DSPP gene promoter. SBE mutations result in a decrease in DSPP transcriptional activity. Endogenous DSPP expression was up-regulated by DSP aa183-219 in dental mesenchymal cells. The data in the current study demonstrate for the first time that this DSP domain acts as a ligand in a RGD-independent manner and is involved in intracellular signaling via interacting with integrin β6. The DSP domain regulates DSPP expression and odontoblast homeostasis via a positive feedback loop. PMID:27430624

The Dentin Sialoprotein (DSP) Domain Regulates Dental Mesenchymal Cell Differentiation through a Novel Surface Receptor.

PubMed

Wan, Chunyan; Yuan, Guohua; Luo, Daoshu; Zhang, Lu; Lin, Heng; Liu, Huan; Chen, Lei; Yang, Guobin; Chen, Shuo; Chen, Zhi

2016-07-19

Dentin sialophosphoprotein (DSPP) is a dentin extracellular matrix protein that is processed into dentin sialoprotein (DSP), dentin glycoprotein (DGP) and dentin phosphoprotein (DPP). DSP is mainly expressed in odontoblasts. We hypothesized that DSP interacts with cell surface receptors and subsequently activates intracellular signaling. Using DSP as bait for screening a protein library, we demonstrate that DSP acts as a ligand and binds to integrin β6. The 36 amino acid residues of DSP are sufficient to bind to integrin β6. This peptide promoted cell attachment, migration, differentiation and mineralization of dental mesenchymal cells. In addition, DSP (aa183-219) stimulated phosphorylation of ERK1/2 and P38 kinases. This activation was inhibited by an anti-integrin β6 antibody and siRNA. Furthermore, we demonstrate that this DSP fragment induces SMAD1/5/8 phosphorylation and nuclear translocation via ERK1/2 and P38 signaling. SMAD1/5/8 binds to SMAD binding elements (SBEs) in the DSPP gene promoter. SBE mutations result in a decrease in DSPP transcriptional activity. Endogenous DSPP expression was up-regulated by DSP (aa183-219) in dental mesenchymal cells. The data in the current study demonstrate for the first time that this DSP domain acts as a ligand in a RGD-independent manner and is involved in intracellular signaling via interacting with integrin β6. The DSP domain regulates DSPP expression and odontoblast homeostasis via a positive feedback loop.

FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods.

PubMed

Zierke, Stephanie; Bakos, Jason D

2010-04-12

Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA)-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10x speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs).

High precision locating control system based on VCM for Talbot lithography

NASA Astrophysics Data System (ADS)

Yao, Jingwei; Zhao, Lixin; Deng, Qian; Hu, Song

2016-10-01

Aiming at the high precision and efficiency requirements of Z-direction locating in Talbot lithography, a control system based on Voice Coil Motor (VCM) was designed. In this paper, we built a math model of VCM and its moving characteristic was analyzed. A double-closed loop control strategy including position loop and current loop were accomplished. The current loop was implemented by driver, in order to achieve the rapid follow of the system current. The position loop was completed by the digital signal processor (DSP) and the position feedback was achieved by high precision linear scales. Feed forward control and position feedback Proportion Integration Differentiation (PID) control were applied in order to compensate for dynamic lag and improve the response speed of the system. And the high precision and efficiency of the system were verified by simulation and experiments. The results demonstrated that the performance of Z-direction gantry was obviously improved, having high precision, quick responses, strong real-time and easily to expend for higher precision.

Design and implementation of a hybrid sub-band acoustic echo canceller (AEC)

NASA Astrophysics Data System (ADS)

Bai, Mingsian R.; Yang, Cheng-Ken; Hur, Ker-Nan

2009-04-01

An efficient method is presented for implementing an acoustic echo canceller (AEC) that makes use of hybrid sub-band approach. The hybrid system is comprised of a fixed processor and an adaptive filter in each sub-band. The AEC aims at reducing the echo resulting from the acoustic feedback in loudspeaker-enclosure-microphone (LEM) systems such as teleconferencing and hands-free systems. In order to cancel the acoustical echo efficiently, various processing architectures including fixed filters, hybrid processors, and sub-band structure are investigated. A double-talk detector is incorporated into the proposed AEC to prevent the adaptive filter from diverging in double-talk situations. A de-correlation filter is also used alongside sub-band processing in order to enhance the performance and efficiency of AEC. All algorithms are implemented and verified on the platform of a fixed-point digital signal processor (DSP). The AECs are evaluated in terms of cancellation performance and computation complexity. In addition, listening tests are conducted to assess the subjective performance of the AECs. From the results, the proposed hybrid sub-band AEC was found to be the most effective among all methods in terms of echo reduction and timbral quality.

Implementation of MPEG-2 encoder to multiprocessor system using multiple MVPs (TMS320C80)

NASA Astrophysics Data System (ADS)

Kim, HyungSun; Boo, Kenny; Chung, SeokWoo; Choi, Geon Y.; Lee, YongJin; Jeon, JaeHo; Park, Hyun Wook

1997-05-01

This paper presents the efficient algorithm mapping for the real-time MPEG-2 encoding on the KAIST image computing system (KICS), which has a parallel architecture using five multimedia video processors (MVPs). The MVP is a general purpose digital signal processor (DSP) of Texas Instrument. It combines one floating-point processor and four fixed- point DSPs on a single chip. The KICS uses the MVP as a primary processing element (PE). Two PEs form a cluster, and there are two processing clusters in the KICS. Real-time MPEG-2 encoder is implemented through the spatial and the functional partitioning strategies. Encoding process of spatially partitioned half of the video input frame is assigned to ne processing cluster. Two PEs perform the functionally partitioned MPEG-2 encoding tasks in the pipelined operation mode. One PE of a cluster carries out the transform coding part and the other performs the predictive coding part of the MPEG-2 encoding algorithm. One MVP among five MVPs is used for system control and interface with host computer. This paper introduces an implementation of the MPEG-2 algorithm with a parallel processing architecture.

Real-Time Data Processing in the muon system of the D0 detector.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Neeti Parashar et al.

2001-07-03

This paper presents a real-time application of the 16-bit fixed point Digital Signal Processors (DSPs), in the Muon System of the D0 detector located at the Fermilab Tevatron, presently the world's highest-energy hadron collider. As part of the Upgrade for a run beginning in the year 2000, the system is required to process data at an input event rate of 10 KHz without incurring significant deadtime in readout. The ADSP21csp01 processor has high I/O bandwidth, single cycle instruction execution and fast task switching support to provide efficient multisignal processing. The processor's internal memory consists of 4K words of Program Memorymore » and 4K words of Data Memory. In addition there is an external memory of 32K words for general event buffering and 16K words of Dual port Memory for input data queuing. This DSP fulfills the requirement of the Muon subdetector systems for data readout. All error handling, buffering, formatting and transferring of the data to the various trigger levels of the data acquisition system is done in software. The algorithms developed for the system complete these tasks in about 20 {micro}s per event.« less

Infrared hyperspectral imaging sensor for gas detection

NASA Astrophysics Data System (ADS)

Hinnrichs, Michele

2000-11-01

A small light weight man portable imaging spectrometer has many applications; gas leak detection, flare analysis, threat warning, chemical agent detection, just to name a few. With support from the US Air Force and Navy, Pacific Advanced Technology has developed a small man portable hyperspectral imaging sensor with an embedded DSP processor for real time processing that is capable of remotely imaging various targets such as gas plums, flames and camouflaged targets. Based upon their spectral signature the species and concentration of gases can be determined. This system has been field tested at numerous places including White Mountain, CA, Edwards AFB, and Vandenberg AFB. Recently evaluation of the system for gas detection has been performed. This paper presents these results. The system uses a conventional infrared camera fitted with a diffractive optic that images as well as disperses the incident radiation to form spectral images that are collected in band sequential mode. Because the diffractive optic performs both imaging and spectral filtering, the lens system consists of only a single element that is small, light weight and robust, thus allowing man portability. The number of spectral bands are programmable such that only those bands of interest need to be collected. The system is entirely passive, therefore, easily used in a covert operation. Currently Pacific Advanced Technology is working on the next generation of this camera system that will have both an embedded processor as well as an embedded digital signal processor in a small hand held camera configuration. This will allow the implementation of signal and image processing algorithms for gas detection and identification in real time. This paper presents field test data on gas detection and identification as well as discuss the signal and image processing used to enhance the gas visibility. Flow rates as low as 0.01 cubic feet per minute have been imaged with this system.

High Speed and High Functional Inverter Power Supplies for Plasma Generation and Control, and their Performance

NASA Astrophysics Data System (ADS)

Uesugi, Yoshihiko; Razzak, Mohammad A.; Kondo, Kenji; Kikuchi, Yusuke; Takamura, Shuichi; Imai, Takahiro; Toyoda, Mitsuhiro

The Rapid development of high power and high speed semiconductor switching devices has led to their various applications in related plasma fields. Especially, a high speed inverter power supply can be used as an RF power source instead of conventional linear amplifiers and a power supply to control the magnetic field in a fusion plasma device. In this paper, RF thermal plasma production and plasma heating experiments are described emphasis placed on using a static induction transistor inverter at a frequency range between 200 kHz and 2.5 MHz as an RF power supply. Efficient thermal plasma production is achieved experimentally by using a flexible and easily operated high power semiconductor inverter power supply. Insulated gate bipolar transistor (IGBT) inverter power supplies driven by a high speed digital signal processor are applied as tokamak joule coil and vertical coil power supplies to control plasma current waveform and plasma equilibrium. Output characteristics, such as the arbitrary bipolar waveform generation of a pulse width modulation (PWM) inverter using digital signal processor (DSP) can be successfully applied to tokamak power supplies for flexible plasma current operation and fast position control of a small tokamak.

Real-time 3D adaptive filtering for portable imaging systems

NASA Astrophysics Data System (ADS)

Bockenbach, Olivier; Ali, Murtaza; Wainwright, Ian; Nadeski, Mark

2015-03-01

Portable imaging devices have proven valuable for emergency medical services both in the field and hospital environments and are becoming more prevalent in clinical settings where the use of larger imaging machines is impractical. 3D adaptive filtering is one of the most advanced techniques aimed at noise reduction and feature enhancement, but is computationally very demanding and hence often not able to run with sufficient performance on a portable platform. In recent years, advanced multicore DSPs have been introduced that attain high processing performance while maintaining low levels of power dissipation. These processors enable the implementation of complex algorithms like 3D adaptive filtering, improving the image quality of portable medical imaging devices. In this study, the performance of a 3D adaptive filtering algorithm on a digital signal processor (DSP) is investigated. The performance is assessed by filtering a volume of size 512x256x128 voxels sampled at a pace of 10 MVoxels/sec.

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barhen, Jacob; Kerekes, Ryan A; ST Charles, Jesse Lee

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlationmore » processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core performs the matrix-vector multiplications, where the nominal matrix size is 256x256. The system clock is 125MHz. At each clock cycle, 128K multiply-and-add operations per second (OPS) are carried out, which yields a peak performance of 16 TeraOPS. IBM Cell Broadband Engine. The Cell processor is the extraordinary resulting product of 5 years of sustained, intensive R&D collaboration (involving over $400M investment) between IBM, Sony, and Toshiba. Its architecture comprises one multithreaded 64-bit PowerPC processor element (PPE) with VMX capabilities and two levels of globally coherent cache, and 8 synergistic processor elements (SPEs). Each SPE consists of a processor (SPU) designed for streaming workloads, local memory, and a globally coherent direct memory access (DMA) engine. Computations are performed in 128-bit wide single instruction multiple data streams (SIMD). An integrated high-bandwidth element interconnect bus (EIB) connects the nine processors and their ports to external memory and to system I/O. The Applied Software Engineering Research (ASER) Group at the ORNL is applying the Cell to a variety of text and image analysis applications. Research on Cell-equipped PlayStation3 (PS3) consoles has led to the development of a correlation-based image recognition engine that enables a single PS3 to process images at more than 10X the speed of state-of-the-art single-core processors. NVIDIA Graphics Processing Units. The ASER group is also employing the latest NVIDIA graphical processing units (GPUs) to accelerate clustering of thousands of text documents using recently developed clustering algorithms such as document flocking and affinity propagation.« less

Perception SoC Based on an Ultrasonic Array of Sensors: Efficient DSP Core Implementation and Subsequent Experimental Results

NASA Astrophysics Data System (ADS)

Kassem, A.; Sawan, M.; Boukadoum, M.; Haidar, A.

2005-12-01

We are concerned with the design, implementation, and validation of a perception SoC based on an ultrasonic array of sensors. The proposed SoC is dedicated to ultrasonic echography applications. A rapid prototyping platform is used to implement and validate the new architecture of the digital signal processing (DSP) core. The proposed DSP core efficiently integrates all of the necessary ultrasonic B-mode processing modules. It includes digital beamforming, quadrature demodulation of RF signals, digital filtering, and envelope detection of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a[InlineEquation not available: see fulltext.] angle of view span. The design uses a minimum size lookup memory to store the initial scan information. Rapid prototyping using an ARM/FPGA combination is used to validate the operation of the described system. This system offers significant advantages of portability and a rapid time to market.

Floating-to-Fixed-Point Conversion for Digital Signal Processors

NASA Astrophysics Data System (ADS)

Menard, Daniel; Chillet, Daniel; Sentieys, Olivier

2006-12-01

Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus, methodologies which establish automatically the fixed-point specification are required to reduce the application time-to-market. In this paper, a new methodology for the floating-to-fixed point conversion is proposed for software implementations. The aim of our approach is to determine the fixed-point specification which minimises the code execution time for a given accuracy constraint. Compared to previous methodologies, our approach takes into account the DSP architecture to optimise the fixed-point formats and the floating-to-fixed-point conversion process is coupled with the code generation process. The fixed-point data types and the position of the scaling operations are optimised to reduce the code execution time. To evaluate the fixed-point computation accuracy, an analytical approach is used to reduce the optimisation time compared to the existing methods based on simulation. The methodology stages are described and several experiment results are presented to underline the efficiency of this approach.

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

Digital Analysis and Sorting of Fluorescence Lifetime by Flow Cytometry

PubMed Central

Houston, Jessica P.; Naivar, Mark A.; Freyer, James P.

2010-01-01

Frequency-domain flow cytometry techniques are combined with modifications to the digital signal processing capabilities of the Open Reconfigurable Cytometric Acquisition System (ORCAS) to analyze fluorescence decay lifetimes and control sorting. Real-time fluorescence lifetime analysis is accomplished by rapidly digitizing correlated, radiofrequency modulated detector signals, implementing Fourier analysis programming with ORCAS’ digital signal processor (DSP) and converting the processed data into standard cytometric list mode data. To systematically test the capabilities of the ORCAS 50 MS/sec analog-to-digital converter (ADC) and our DSP programming, an error analysis was performed using simulated light scatter and fluorescence waveforms (0.5–25 ns simulated lifetime), pulse widths ranging from 2 to 15 µs, and modulation frequencies from 2.5 to 16.667 MHz. The standard deviations of digitally acquired lifetime values ranged from 0.112 to >2 ns, corresponding to errors in actual phase shifts from 0.0142° to 1.6°. The lowest coefficients of variation (<1%) were found for 10-MHz modulated waveforms having pulse widths of 6 µs and simulated lifetimes of 4 ns. Direct comparison of the digital analysis system to a previous analog phase-sensitive flow cytometer demonstrated similar precision and accuracy on measurements of a range of fluorescent microspheres, unstained cells and cells stained with three common fluorophores. Sorting based on fluorescence lifetime was accomplished by adding analog outputs to ORCAS and interfacing with a commercial cell sorter with a radiofrequency modulated solid-state laser. Two populations of fluorescent microspheres with overlapping fluorescence intensities but different lifetimes (2 and 7 ns) were separated to ~98% purity. Overall, the digital signal acquisition and processing methods we introduce present a simple yet robust approach to phase-sensitive measurements in flow cytometry. The ability to simply and inexpensively implement this system on a commercial flow sorter will both allow better dissemination of this technology and better exploit the traditionally underutilized parameter of fluorescence lifetime. PMID:20662090

VPI - VIBRATION PATTERN IMAGER: A CONTROL AND DATA ACQUISITION SYSTEM FOR SCANNING LASER VIBROMETERS

NASA Technical Reports Server (NTRS)

Rizzi, S. A.

1994-01-01

The Vibration Pattern Imager (VPI) system was designed to control and acquire data from laser vibrometer sensors. The PC computer based system uses a digital signal processing (DSP) board and an analog I/O board to control the sensor and to process the data. The VPI system was originally developed for use with the Ometron VPI Sensor (Ometron Limited, Kelvin House, Worsley Bridge Road, London, SE26 5BX, England), but can be readily adapted to any commercially available sensor which provides an analog output signal and requires analog inputs for control of mirror positioning. VPI's graphical user interface allows the operation of the program to be controlled interactively through keyboard and mouse-selected menu options. The main menu controls all functions for setup, data acquisition, display, file operations, and exiting the program. Two types of data may be acquired with the VPI system: single point or "full field". In the single point mode, time series data is sampled by the A/D converter on the I/O board at a user-defined rate for the selected number of samples. The position of the measuring point, adjusted by mirrors in the sensor, is controlled via a mouse input. In the "full field" mode, the measurement point is moved over a user-selected rectangular area with up to 256 positions in both x and y directions. The time series data is sampled by the A/D converter on the I/O board and converted to a root-mean-square (rms) value by the DSP board. The rms "full field" velocity distribution is then uploaded for display and storage. VPI is written in C language and Texas Instruments' TMS320C30 assembly language for IBM PC series and compatible computers running MS-DOS. The program requires 640K of RAM for execution, and a hard disk with 10Mb or more of disk space is recommended. The program also requires a mouse, a VGA graphics display, a Four Channel analog I/O board (Spectrum Signal Processing, Inc.; Westborough, MA), a break-out box and a Spirit-30 board (Sonitech International, Inc.; Wellesley, MA) which includes a TMS320C30 DSP processor, 256Kb zero wait state SRAM, and a daughter board with 8Mb one wait state DRAM. Please contact COSMIC for additional information on required hardware and software. In order to compile the provided VPI source code, a Microsoft C version 6.0 compiler, a Texas Instruments' TMS320C30 assembly language compiler, and the Spirit 30 run time libraries are required. A math co-processor is highly recommended. A sample MS-DOS executable is provided on the distribution medium. The standard distribution medium for this program is one 5.25 inch 360K MS-DOS format diskette. The contents of the diskettes are compressed using the PKWARE archiving tools. The utility to unarchive the files, PKUNZIP.EXE, is included. VPI was developed in 1991-1992.

Autonomous vision networking: miniature wireless sensor networks with imaging technology

NASA Astrophysics Data System (ADS)

Messinger, Gioia; Goldberg, Giora

2006-09-01

The recent emergence of integrated PicoRadio technology, the rise of low power, low cost, System-On-Chip (SOC) CMOS imagers, coupled with the fast evolution of networking protocols and digital signal processing (DSP), created a unique opportunity to achieve the goal of deploying large-scale, low cost, intelligent, ultra-low power distributed wireless sensor networks for the visualization of the environment. Of all sensors, vision is the most desired, but its applications in distributed sensor networks have been elusive so far. Not any more. The practicality and viability of ultra-low power vision networking has been proven and its applications are countless, from security, and chemical analysis to industrial monitoring, asset tracking and visual recognition, vision networking represents a truly disruptive technology applicable to many industries. The presentation discusses some of the critical components and technologies necessary to make these networks and products affordable and ubiquitous - specifically PicoRadios, CMOS imagers, imaging DSP, networking and overall wireless sensor network (WSN) system concepts. The paradigm shift, from large, centralized and expensive sensor platforms, to small, low cost, distributed, sensor networks, is possible due to the emergence and convergence of a few innovative technologies. Avaak has developed a vision network that is aided by other sensors such as motion, acoustic and magnetic, and plans to deploy it for use in military and commercial applications. In comparison to other sensors, imagers produce large data files that require pre-processing and a certain level of compression before these are transmitted to a network server, in order to minimize the load on the network. Some of the most innovative chemical detectors currently in development are based on sensors that change color or pattern in the presence of the desired analytes. These changes are easily recorded and analyzed by a CMOS imager and an on-board DSP processor. Image processing at the sensor node level may also be required for applications in security, asset management and process control. Due to the data bandwidth requirements posed on the network by video sensors, new networking protocols or video extensions to existing standards (e.g. Zigbee) are required. To this end, Avaak has designed and implemented an ultra-low power networking protocol designed to carry large volumes of data through the network. The low power wireless sensor nodes that will be discussed include a chemical sensor integrated with a CMOS digital camera, a controller, a DSP processor and a radio communication transceiver, which enables relaying of an alarm or image message, to a central station. In addition to the communications, identification is very desirable; hence location awareness will be later incorporated to the system in the form of Time-Of-Arrival triangulation, via wide band signaling. While the wireless imaging kernel already exists specific applications for surveillance and chemical detection are under development by Avaak, as part of a co-founded program from ONR and DARPA. Avaak is also designing vision networks for commercial applications - some of which are undergoing initial field tests.

REVIEW ARTICLE: Spectrophotometric applications of digital signal processing

NASA Astrophysics Data System (ADS)

Morawski, Roman Z.

2006-09-01

Spectrophotometry is more and more often the method of choice not only in analysis of (bio)chemical substances, but also in the identification of physical properties of various objects and their classification. The applications of spectrophotometry include such diversified tasks as monitoring of optical telecommunications links, assessment of eating quality of food, forensic classification of papers, biometric identification of individuals, detection of insect infestation of seeds and classification of textiles. In all those applications, large numbers of data, generated by spectrophotometers, are processed by various digital means in order to extract measurement information. The main objective of this paper is to review the state-of-the-art methodology for digital signal processing (DSP) when applied to data provided by spectrophotometric transducers and spectrophotometers. First, a general methodology of DSP applications in spectrophotometry, based on DSP-oriented models of spectrophotometric data, is outlined. Then, the most important classes of DSP methods for processing spectrophotometric data—the methods for DSP-aided calibration of spectrophotometric instrumentation, the methods for the estimation of spectra on the basis of spectrophotometric data, the methods for the estimation of spectrum-related measurands on the basis of spectrophotometric data—are presented. Finally, the methods for preprocessing and postprocessing of spectrophotometric data are overviewed. Throughout the review, the applications of DSP are illustrated with numerous examples related to broadly understood spectrophotometry.

Design and Implementation of Sound Searching Robots in Wireless Sensor Networks

PubMed Central

Han, Lianfu; Shen, Zhengguang; Fu, Changfeng; Liu, Chao

2016-01-01

A sound target-searching robot system which includes a 4-channel microphone array for sound collection, magneto-resistive sensor for declination measurement, and a wireless sensor networks (WSN) for exchanging information is described. It has an embedded sound signal enhancement, recognition and location method, and a sound searching strategy based on a digital signal processor (DSP). As the wireless network nodes, three robots comprise the WSN a personal computer (PC) in order to search the three different sound targets in task-oriented collaboration. The improved spectral subtraction method is used for noise reduction. As the feature of audio signal, Mel-frequency cepstral coefficient (MFCC) is extracted. Based on the K-nearest neighbor classification method, we match the trained feature template to recognize sound signal type. This paper utilizes the improved generalized cross correlation method to estimate time delay of arrival (TDOA), and then employs spherical-interpolation for sound location according to the TDOA and the geometrical position of the microphone array. A new mapping has been proposed to direct the motor to search sound targets flexibly. As the sink node, the PC receives and displays the result processed in the WSN, and it also has the ultimate power to make decision on the received results in order to improve their accuracy. The experiment results show that the designed three-robot system implements sound target searching function without collisions and performs well. PMID:27657088

An ultra-low power (ULP) bandage-type ECG sensor for efficient cardiac disease management.

PubMed

Shin, Kunsoo; Park, G G; Kim, J P; Lee, T H; Ko, B H; Kim, Y H

2013-01-01

This paper proposed an ultra-low power bandage-type ECG sensor (the size: 76 × 34 × 3 (mm(3)) and the power consumption: 1 mW) which allows for a continuous and real-time monitoring of a user's ECG signals over 24h during daily activities. For its compact size and lower power consumption, we designed the analog front-end, the SRP (Samsung Reconfigurable Processor) based DSP of 30 uW/MHz, and the ULP wireless RF of 1 nJ/bit. Also, to tackle motion artifacts(MA), a MA monitoring technique based on the HCP (Half-cell Potential) is proposed which resulted in the high correlation between the MA and the HCP, the correlation coefficient of 0.75 ± 0.18. To assess its feasibility and validity as a wearable health monitor, we performed the comparison of two ECG signals recorded form it and a conventional Holter device. As a result, the performance of the former is a little lower as compared with the latter, although showing no statistical significant difference (the quality of the signal: 94.3% vs 99.4%; the accuracy of arrhythmia detection: 93.7% vs 98.7%). With those results, it has been confirmed that it can be used as a wearable health monitor due to its comfortability, its long operation lifetime and the good quality of the measured ECG signal.

Design and Implementation of Sound Searching Robots in Wireless Sensor Networks.

PubMed

Han, Lianfu; Shen, Zhengguang; Fu, Changfeng; Liu, Chao

2016-09-21

A sound target-searching robot system which includes a 4-channel microphone array for sound collection, magneto-resistive sensor for declination measurement, and a wireless sensor networks (WSN) for exchanging information is described. It has an embedded sound signal enhancement, recognition and location method, and a sound searching strategy based on a digital signal processor (DSP). As the wireless network nodes, three robots comprise the WSN a personal computer (PC) in order to search the three different sound targets in task-oriented collaboration. The improved spectral subtraction method is used for noise reduction. As the feature of audio signal, Mel-frequency cepstral coefficient (MFCC) is extracted. Based on the K-nearest neighbor classification method, we match the trained feature template to recognize sound signal type. This paper utilizes the improved generalized cross correlation method to estimate time delay of arrival (TDOA), and then employs spherical-interpolation for sound location according to the TDOA and the geometrical position of the microphone array. A new mapping has been proposed to direct the motor to search sound targets flexibly. As the sink node, the PC receives and displays the result processed in the WSN, and it also has the ultimate power to make decision on the received results in order to improve their accuracy. The experiment results show that the designed three-robot system implements sound target searching function without collisions and performs well.

DHS Internship Paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dreyer, J

2007-09-18

During my internship at Lawrence Livermore National Laboratory I worked with microcalorimeter gamma-ray and fast-neutron detectors based on superconducting Transition Edge Sensors (TESs). These instruments are being developed for fundamental science and nuclear non-proliferation applications because of their extremely high energy resolution; however, this comes at the expense of a small pixel size and slow decay times. The small pixel sizes are being addressed by developing detector arrays while the low count rate is being addressed by developing Digital Signal Processors (DSPs) that allow higher throughput than traditional pulse processing algorithms. Traditionally, low-temperature microcalorimeter pulses have been processed off-line withmore » optimum filtering routines based on the measured spectral characteristics of the signal and the noise. These optimum filters rely on the spectral content of the signal being identical for all events, and therefore require capturing the entire pulse signal without pile-up. In contrast, the DSP algorithm being developed is based on differences in signal levels before and after a trigger event, and therefore does not require the waveform to fully decay, or even the signal level to be close to the base line. The readout system allows for real time data acquisition and analysis at count rates exceeding 100 Hz for pulses with several {approx}ms decay times with minimal loss of energy resolution. Originally developed for gamma-ray analysis with HPGe detectors we have modified the hardware and firmware of the system to accommodate the slower TES signals and optimized the parameters of the filtering algorithm to maximize either resolution or throughput. The following presents an overview of the digital signal processing hardware and discusses the results of characterization measurements made to determine the systems performance.« less

Architectures for single-chip image computing

NASA Astrophysics Data System (ADS)

Gove, Robert J.

1992-04-01

This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

NASA Astrophysics Data System (ADS)

Zou, Liang; Fu, Zhuang; Zhao, YanZheng; Yang, JunYan

2010-07-01

This paper proposes a kind of pipelined electric circuit architecture implemented in FPGA, a very large scale integrated circuit (VLSI), which efficiently deals with the real time non-uniformity correction (NUC) algorithm for infrared focal plane arrays (IRFPA). Dual Nios II soft-core processors and a DSP with a 64+ core together constitute this image system. Each processor undertakes own systematic task, coordinating its work with each other's. The system on programmable chip (SOPC) in FPGA works steadily under the global clock frequency of 96Mhz. Adequate time allowance makes FPGA perform NUC image pre-processing algorithm with ease, which has offered favorable guarantee for the work of post image processing in DSP. And at the meantime, this paper presents a hardware (HW) and software (SW) co-design in FPGA. Thus, this systematic architecture yields an image processing system with multiprocessor, and a smart solution to the satisfaction with the performance of the system.

Design of thin-film filters for resolution improvements in filter-array based spectrometers using DSP

NASA Astrophysics Data System (ADS)

Lee, Woong-Bi; Kim, Cheolsun; Ju, Gun Wu; Lee, Yong Tak; Lee, Heung-No

2016-05-01

Miniature spectrometers have been widely developed in various academic and industrial applications such as bio-medical, chemical and environmental engineering. As a family of spectrometers, optical filter-array based spectrometers fabricated using CMOS or Nano technology provide miniaturization, superior portability and cost effectiveness. In filterarray based spectrometers, the resolution which represents the ability how closely resolve two neighboring spectra, depends on the number of filters and the characteristics of the transmission functions (TFs) of the filters. In practice, due to the small-size and low-cost fabrication, the number of filters is limited and the shape of the TF of each filter is nonideal. As a development of modern digital signal processing (DSP), the spectrometers are equipped with DSP algorithms not only to alleviate distortions due to unexpected noise or interferences among filters but also reconstruct the original signal spectrum. For a high-resolution spectrum reconstruction by the DSP, the TFs of the filters need to be sufficiently uncorrelated with each other. In this paper, we present a design of optical thin-film filters which have the uncorrelated TFs. Each filter consists of multiple layers of high- and low-refractive index materials deposited on a substrate. The proposed design helps the DSP algorithm to improve resolution with a small number of filters. We demonstrate that a resolution of 5 nm within a range from 500 nm to 1100 nm can be achieved with only 64 filters.

Sensored Field Oriented Control of a Robust Induction Motor Drive Using a Novel Boundary Layer Fuzzy Controller

PubMed Central

Saghafinia, Ali; Ping, Hew Wooi; Uddin, Mohammad Nasir

2013-01-01

Physical sensors have a key role in implementation of real-time vector control for an induction motor (IM) drive. This paper presents a novel boundary layer fuzzy controller (NBLFC) based on the boundary layer approach for speed control of an indirect field-oriented control (IFOC) of an induction motor (IM) drive using physical sensors. The boundary layer approach leads to a trade-off between control performances and chattering elimination. For the NBLFC, a fuzzy system is used to adjust the boundary layer thickness to improve the tracking performance and eliminate the chattering problem under small uncertainties. Also, to eliminate the chattering under the possibility of large uncertainties, the integral filter is proposed inside the variable boundary layer. In addition, the stability of the system is analyzed through the Lyapunov stability theorem. The proposed NBLFC based IM drive is implemented in real-time using digital signal processor (DSP) board TI TMS320F28335. The experimental and simulation results show the effectiveness of the proposed NBLFC based IM drive at different operating conditions.

Global rotational motion and displacement estimation of digital image stabilization based on the oblique vectors matching algorithm

NASA Astrophysics Data System (ADS)

Yu, Fei; Hui, Mei; Zhao, Yue-jin

2009-08-01

The image block matching algorithm based on motion vectors of correlative pixels in oblique direction is presented for digital image stabilization. The digital image stabilization is a new generation of image stabilization technique which can obtains the information of relative motion among frames of dynamic image sequences by the method of digital image processing. In this method the matching parameters are calculated from the vectors projected in the oblique direction. The matching parameters based on the vectors contain the information of vectors in transverse and vertical direction in the image blocks at the same time. So the better matching information can be obtained after making correlative operation in the oblique direction. And an iterative weighted least square method is used to eliminate the error of block matching. The weights are related with the pixels' rotational angle. The center of rotation and the global emotion estimation of the shaking image can be obtained by the weighted least square from the estimation of each block chosen evenly from the image. Then, the shaking image can be stabilized with the center of rotation and the global emotion estimation. Also, the algorithm can run at real time by the method of simulated annealing in searching method of block matching. An image processing system based on DSP was used to exam this algorithm. The core processor in the DSP system is TMS320C6416 of TI, and the CCD camera with definition of 720×576 pixels was chosen as the input video signal. Experimental results show that the algorithm can be performed at the real time processing system and have an accurate matching precision.

DSP-Based dual-polarity mass spectrum pattern recognition for bio-detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

Riot, V; Coffee, K; Gard, E

2006-04-21

The Bio-Aerosol Mass Spectrometry (BAMS) instrument analyzes single aerosol particles using a dual-polarity time-of-flight mass spectrometer recording simultaneously spectra of thirty to a hundred thousand points on each polarity. We describe here a real-time pattern recognition algorithm developed at Lawrence Livermore National Laboratory that has been implemented on a nine Digital Signal Processor (DSP) system from Signatec Incorporated. The algorithm first preprocesses independently the raw time-of-flight data through an adaptive baseline removal routine. The next step consists of a polarity dependent calibration to a mass-to-charge representation, reducing the data to about five hundred to a thousand channels per polarity. Themore » last step is the identification step using a pattern recognition algorithm based on a library of known particle signatures including threat agents and background particles. The identification step includes integrating the two polarities for a final identification determination using a score-based rule tree. This algorithm, operating on multiple channels per-polarity and multiple polarities, is well suited for parallel real-time processing. It has been implemented on the PMP8A from Signatec Incorporated, which is a computer based board that can interface directly to the two one-Giga-Sample digitizers (PDA1000 from Signatec Incorporated) used to record the two polarities of time-of-flight data. By using optimized data separation, pipelining, and parallel processing across the nine DSPs it is possible to achieve a processing speed of up to a thousand particles per seconds, while maintaining the recognition rate observed on a non-real time implementation. This embedded system has allowed the BAMS technology to improve its throughput and therefore its sensitivity while maintaining a large dynamic range (number of channels and two polarities) thus maintaining the systems specificity for bio-detection.« less

Implementation of a High-Speed FPGA and DSP Based FFT Processor for Improving Strain Demodulation Performance in a Fiber-Optic-Based Sensing System

NASA Technical Reports Server (NTRS)

Farley, Douglas L.

2005-01-01

NASA's Aviation Safety and Security Program is pursuing research in on-board Structural Health Management (SHM) technologies for purposes of reducing or eliminating aircraft accidents due to system and component failures. Under this program, NASA Langley Research Center (LaRC) is developing a strain-based structural health-monitoring concept that incorporates a fiber optic-based measuring system for acquiring strain values. This fiber optic-based measuring system provides for the distribution of thousands of strain sensors embedded in a network of fiber optic cables. The resolution of strain value at each discrete sensor point requires a computationally demanding data reduction software process that, when hosted on a conventional processor, is not suitable for near real-time measurement. This report describes the development and integration of an alternative computing environment using dedicated computing hardware for performing the data reduction. Performance comparison between the existing and the hardware-based system is presented.

Real-time digital signal processing in multiphoton and time-resolved microscopy

NASA Astrophysics Data System (ADS)

Wilson, Jesse W.; Warren, Warren S.; Fischer, Martin C.

2016-03-01

The use of multiphoton interactions in biological tissue for imaging contrast requires highly sensitive optical measurements. These often involve signal processing and filtering steps between the photodetector and the data acquisition device, such as photon counting and lock-in amplification. These steps can be implemented as real-time digital signal processing (DSP) elements on field-programmable gate array (FPGA) devices, an approach that affords much greater flexibility than commercial photon counting or lock-in devices. We will present progress toward developing two new FPGA-based DSP devices for multiphoton and time-resolved microscopy applications. The first is a high-speed multiharmonic lock-in amplifier for transient absorption microscopy, which is being developed for real-time analysis of the intensity-dependence of melanin, with applications in vivo and ex vivo (noninvasive histopathology of melanoma and pigmented lesions). The second device is a kHz lock-in amplifier running on a low cost (50-200) development platform. It is our hope that these FPGA-based DSP devices will enable new, high-speed, low-cost applications in multiphoton and time-resolved microscopy.

Single channel 112Gbit/sec PAM4 at 56Gbaud with digital signal processing for data centers applications.

PubMed

Sadot, Dan; Dorman, G; Gorshtein, Albert; Sonkin, Eduard; Vidal, Or

2015-01-26

112Gbit/sec DSP-based single channel transmission of PAM4 at 56Gbaud over 15GHz of effective analog bandwidth is experimentally demonstrated. The DSP enables use of mature 25G optoelectronics for 2-10km datacenter intra-connections, and 8Tbit/sec over 80km interconnections between data centers.

Design and implementation of a hybrid digital phase-locked loop with a TMS320C25: An application to a transponder receiver breadboard

NASA Technical Reports Server (NTRS)

Yeh, H.-G.; Nguyen, T. M.

1994-01-01

Design, modeling, analysis, and simulation of a phase-locked loop (PLL) with a digital loop filter are presented in this article. A TMS320C25 digital signal processor (DSP) is used to implement this digital loop filter. In order to keep the compatibility, the main design goal was to replace the analog PLL (APLL) of the Deep-Space Transponder (DST) receiver breadboard's loop filter with a digital loop filter without changing anything else. This replacement results in a hybrid digital PLL (HDPLL). Both the original APLL and the designed HDPLL are Type I second-order systems. The real-time performance of the HDPLL and the receiver is provided and evaluated.

Determination of torque speed current characteristics of a brushless DC motor by utilizing back-EMF of non-energized phase

NASA Astrophysics Data System (ADS)

Jang, G. H.; Yeom, J. H.; Kim, M. G.

2007-03-01

This paper presents a method to determine the torque constant and the torque-speed-current characteristics of a brushless DC (BLDC) motor by utilizing back-EMF variation of nonenergized phase. It also develops a BLDC motor controller with a digital signal processor (DSP) to monitor its current, voltage and speed in real time. Torque-speed-current characteristics of a BLDC motor are determined by using the proposed method and the developed controller. They are compared with the torque-speed-current characteristics measured by dynamometer experimentally. This research shows that the proposed method is an effective method to determine the torque constant and the torque-speed-current characteristics of the BLDC motor without using dynamometer.

A Succinct Naming Convention for Lengthy Hexadecimal Numbers

NASA Technical Reports Server (NTRS)

Grant, Michael S.

1997-01-01

Engineers, computer scientists, mathematicians and others must often deal with lengthy hexadecimal numbers. As memory requirements for software increase, the associated memory address space for systems necessitates the use of longer and longer strings of hexadecimal characters to describe a given number. For example, the address space of some digital signal processors (DSP's) now ranges in the billions of words, requiring eight hexadecimal characters for many of the addresses. This technical memorandum proposes a simple grouping scheme for more clearly representing lengthy hexadecimal numbers in written material, as well as a "code" for naming and more quickly verbalizing such numbers. This should facilitate communications among colleagues in engineering and related fields, and aid in comprehension and temporary memorization of important hexadecimal numbers during design work.

Multiple-function multi-input/multi-output digital control and on-line analysis

NASA Technical Reports Server (NTRS)

Hoadley, Sherwood T.; Wieseman, Carol D.; Mcgraw, Sandra M.

1992-01-01

The design and capabilities of two digital controller systems for aeroelastic wind-tunnel models are described. The first allowed control of flutter while performing roll maneuvers with wing load control as well as coordinating the acquisition, storage, and transfer of data for on-line analysis. This system, which employs several digital signal multi-processor (DSP) boards programmed in high-level software languages, is housed in a SUN Workstation environment. A second DCS provides a measure of wind-tunnel safety by functioning as a trip system during testing in the case of high model dynamic response or in case the first DCS fails. The second DCS uses National Instruments LabVIEW Software and Hardware within a Macintosh environment.

UWB radar technique for arc detection in coaxial cables

NASA Astrophysics Data System (ADS)

Salvador, Sara; Maggiora, Riccardo

2010-11-01

UWB signals constituted by a sequence of chips (properly chosen to reduce side lobes and to improve detection accuracy) are transmitted along the transmission lines at a specified Pulse Repetition Frequency (PRF) and their echoes are received by means of directional couplers. The core of the receiver is an ultra high-speed correlator implemented in a Digital Signal Processor (DSP). When a target (arc) is detected, its position and its ``radar cross section'' are calculated to be able to provide the arc position along the transmission line and to be able to classify the type of detected arc. The ``background scattering'' is routinely extracted from the received signal at any pulse. This permits to be resilient to the background structure of transmission lines (bends, junctions, windows, etc.). Thanks to the localization feature, segmentation is also possible for creating sensed and non- sensed zones (for example, to be insensitive to antenna load variations). A complete test bed has been installed using standard coaxial cables (RG58) to demonstrate the system capabilities.

Smart Phase Tuning in Microwave Photonic Integrated Circuits Toward Automated Frequency Multiplication by Design

NASA Astrophysics Data System (ADS)

Nabavi, N.

2018-07-01

The author investigates the monitoring methods for fine adjustment of the previously proposed on-chip architecture for frequency multiplication and translation of harmonics by design. Digital signal processing (DSP) algorithms are utilized to create an optimized microwave photonic integrated circuit functionality toward automated frequency multiplication. The implemented DSP algorithms are formed on discrete Fourier transform and optimization-based algorithms (Greedy and gradient-based algorithms), which are analytically derived and numerically compared based on the accuracy and speed of convergence criteria.

Genomic signal processing methods for computation of alignment-free distances from DNA sequences.

PubMed

Borrayo, Ernesto; Mendizabal-Ruiz, E Gerardo; Vélez-Pérez, Hugo; Romo-Vázquez, Rebeca; Mendizabal, Adriana P; Morales, J Alejandro

2014-01-01

Genomic signal processing (GSP) refers to the use of digital signal processing (DSP) tools for analyzing genomic data such as DNA sequences. A possible application of GSP that has not been fully explored is the computation of the distance between a pair of sequences. In this work we present GAFD, a novel GSP alignment-free distance computation method. We introduce a DNA sequence-to-signal mapping function based on the employment of doublet values, which increases the number of possible amplitude values for the generated signal. Additionally, we explore the use of three DSP distance metrics as descriptors for categorizing DNA signal fragments. Our results indicate the feasibility of employing GAFD for computing sequence distances and the use of descriptors for characterizing DNA fragments.

Genomic Signal Processing Methods for Computation of Alignment-Free Distances from DNA Sequences

PubMed Central

Borrayo, Ernesto; Mendizabal-Ruiz, E. Gerardo; Vélez-Pérez, Hugo; Romo-Vázquez, Rebeca; Mendizabal, Adriana P.; Morales, J. Alejandro

2014-01-01

Genomic signal processing (GSP) refers to the use of digital signal processing (DSP) tools for analyzing genomic data such as DNA sequences. A possible application of GSP that has not been fully explored is the computation of the distance between a pair of sequences. In this work we present GAFD, a novel GSP alignment-free distance computation method. We introduce a DNA sequence-to-signal mapping function based on the employment of doublet values, which increases the number of possible amplitude values for the generated signal. Additionally, we explore the use of three DSP distance metrics as descriptors for categorizing DNA signal fragments. Our results indicate the feasibility of employing GAFD for computing sequence distances and the use of descriptors for characterizing DNA fragments. PMID:25393409

Noise-Canceling Helmet Audio System

NASA Technical Reports Server (NTRS)

Seibert, Marc A.; Culotta, Anthony J.

2007-01-01

A prototype helmet audio system has been developed to improve voice communication for the wearer in a noisy environment. The system was originally intended to be used in a space suit, wherein noise generated by airflow of the spacesuit life-support system can make it difficult for remote listeners to understand the astronaut s speech and can interfere with the astronaut s attempt to issue vocal commands to a voice-controlled robot. The system could be adapted to terrestrial use in helmets of protective suits that are typically worn in noisy settings: examples include biohazard, fire, rescue, and diving suits. The system (see figure) includes an array of microphones and small loudspeakers mounted at fixed positions in a helmet, amplifiers and signal-routing circuitry, and a commercial digital signal processor (DSP). Notwithstanding the fixed positions of the microphones and loudspeakers, the system can accommodate itself to any normal motion of the wearer s head within the helmet. The system operates in conjunction with a radio transceiver. An audio signal arriving via the transceiver intended to be heard by the wearer is adjusted in volume and otherwise conditioned and sent to the loudspeakers. The wearer s speech is collected by the microphones, the outputs of which are logically combined (phased) so as to form a microphone- array directional sensitivity pattern that discriminates in favor of sounds coming from vicinity of the wearer s mouth and against sounds coming from elsewhere. In the DSP, digitized samples of the microphone outputs are processed to filter out airflow noise and to eliminate feedback from the loudspeakers to the microphones. The resulting conditioned version of the wearer s speech signal is sent to the transceiver.

Trade Study of Implementation of Software Defined Radio (SDR): Fundamental Limitations and Future Prospects

DTIC Science & Technology

2008-12-09

as an antenna followed by an analog signal processing chain ( filters , RF amplifiers) followed by an analog-to- digital converter (ADC) followed by a...Figure 2.3 Block diagram of a DSP- based superheterodyne receiver. ADC RF Filter LNA IF Filter IF Amplifier Tunable Local Oscillator ADC...some band limiting filtering and amplification. In a more realistic architecture (Figure 2.3) that we call the DSP- based superheterodyne receiver, a

Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

NASA Astrophysics Data System (ADS)

Price, D. C.; Kocz, J.; Bailes, M.; Greenhill, L. J.

2016-03-01

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

Database for LDV Signal Processor Performance Analysis

NASA Technical Reports Server (NTRS)

Baker, Glenn D.; Murphy, R. Jay; Meyers, James F.

1989-01-01

A comparative and quantitative analysis of various laser velocimeter signal processors is difficult because standards for characterizing signal bursts have not been established. This leaves the researcher to select a signal processor based only on manufacturers' claims without the benefit of direct comparison. The present paper proposes the use of a database of digitized signal bursts obtained from a laser velocimeter under various configurations as a method for directly comparing signal processors.

Real-time co-registered ultrasound and photoacoustic imaging system based on FPGA and DSP architecture

NASA Astrophysics Data System (ADS)

Alqasemi, Umar; Li, Hai; Aguirre, Andres; Zhu, Quing

2011-03-01

Co-registering ultrasound (US) and photoacoustic (PA) imaging is a logical extension to conventional ultrasound because both modalities provide complementary information of tumor morphology, tumor vasculature and hypoxia for cancer detection and characterization. In addition, both modalities are capable of providing real-time images for clinical applications. In this paper, a Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) module-based real-time US/PA imaging system is presented. The system provides real-time US/PA data acquisition and image display for up to 5 fps* using the currently implemented DSP board. It can be upgraded to 15 fps, which is the maximum pulse repetition rate of the used laser, by implementing an advanced DSP module. Additionally, the photoacoustic RF data for each frame is saved for further off-line processing. The system frontend consists of eight 16-channel modules made of commercial and customized circuits. Each 16-channel module consists of two commercial 8-channel receiving circuitry boards and one FPGA board from Analog Devices. Each receiving board contains an IC† that combines. 8-channel low-noise amplifiers, variable-gain amplifiers, anti-aliasing filters, and ADC's‡ in a single chip with sampling frequency of 40MHz. The FPGA board captures the LVDSξ Double Data Rate (DDR) digital output of the receiving board and performs data conditioning and subbeamforming. A customized 16-channel transmission circuitry is connected to the two receiving boards for US pulseecho (PE) mode data acquisition. A DSP module uses External Memory Interface (EMIF) to interface with the eight 16-channel modules through a customized adaptor board. The DSP transfers either sub-beamformed data (US pulse-echo mode or PAI imaging mode) or raw data from FPGA boards to its DDR-2 memory through the EMIF link, then it performs additional processing, after that, it transfer the data to the PC** for further image processing. The PC code performs image processing including demodulation, beam envelope detection and scan conversion. Additionally, the PC code pre-calculates the delay coefficients used for transmission focusing and receiving dynamic focusing for different types of transducers to speed up the imaging process. To further speed up the imaging process, a multi-threads technique is implemented in order to allow formation of previous image frame data and acquisition of the next one simultaneously. The system is also capable of doing semi-real-time automated SO2 imaging at 10 seconds per frame by changing the wavelength knob of the laser automatically using a stepper motor controlled by the system. Initial in vivo experiments were performed on animal tumors to map out its vasculature and hypoxia level, which were superimposed on co-registered US images. The real-time system allows capturing co-registered US/PA images free of motion artifacts and also provides dynamitic information when contrast agents are used.

Development of a Real-Time General-Purpose Digital Signal Processing Laboratory System.

DTIC Science & Technology

1983-12-01

should serve several important purposes: to familiarize students with the use of common DSP tools in an instructional environment, to serve as a research ...of Dayton Research Institute researchers for DSP software and DSP system design insight. 3. Formulation of statement of requirements for development...Neither the University of Dayton nor its Research Institute have a DSP computer system. While UD offered no software or DSP system design information

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

Real-time implementations of acoustic signal enhancement techniques for aerial based surveillance and rescue applications

NASA Astrophysics Data System (ADS)

Ramos, Antonio L. L.; Shao, Zhili; Holthe, Aleksander; Sandli, Mathias F.

2017-05-01

The introduction of the System-on-Chip (SoC) technology has brought exciting new opportunities for the development of smart low cost embedded systems spanning a wide range of applications. Currently available SoC devices are capable of performing high speed digital signal processing tasks in software while featuring relatively low development costs and reduced time-to-market. Unmanned aerial vehicles (UAV) are an application example that has shown tremendous potential in an increasing number of scenarios, ranging from leisure to surveillance as well as in search and rescue missions. Video capturing from UAV platforms is a relatively straightforward task that requires almost no preprocessing. However, that does not apply to audio signals, especially in cases where the data is to be used to support real-time decision making. In fact, the enormous amount of acoustic interference from the surroundings, including the noise from the UAVs propellers, becomes a huge problem. This paper discusses a real-time implementation of the NLMS adaptive filtering algorithm applied to enhancing acoustic signals captured from UAV platforms. The model relies on a combination of acoustic sensors and a computational inexpensive algorithm running on a digital signal processor. Given its simplicity, this solution can be incorporated into the main processing system of an UAV using the SoC technology, and run concurrently with other required tasks, such as flight control and communications. Simulations and real-time DSP-based implementations have shown significant signal enhancement results by efficiently mitigating the interference from the noise generated by the UAVs propellers as well as from other external noise sources.

Behavioral study and design of a digital interpolator filter for wireless reconfigurable transmitters

NASA Astrophysics Data System (ADS)

Ferragina, V.; Frassone, A.; Ghittori, N.; Malcovati, P.; Vigna, A.

2005-06-01

The behavioral analysis and the design in a 0.13 μm CMOS technology of a digital interpolator filter for wireless applications are presented. The proposed block is designed to be embedded in the baseband part of a reconfigurable transmitter (WLAN 802.11a, UMTS) to operate as a sampling frequency boost between the digital signal processor (DSP) and the digital-to-analog converter (DAC). In recent trends the DAC of such transmitters usually operates at high conversion frequencies (to allow a relaxed implementation of the following analog reconstruction filter), while the DSP output flows at low frequencies (typically Nyquist rate). Thus a block able to increase the digital data rate, like the one proposed, is needed before the DAC. For example, in the WLAN case, an interpolation factor of 4 has been used, allowing the digital data frequency to raise from 20 MHz to 80 MHz. Using a time-domain model of the TX chain, a behavioral analysis has been performed to determine the impact of the filter performance on the quality of the signal at the antenna. This study has led to the evaluation of the z-domain filter transfer function, together with the specifications concerning a finite precision implementation. A VHDL description has allowed an automatic synthesis of the circuit in a 0.13 μm CMOS technology (with a supply voltage of 1.2 V). Post-synthesis simulations have confirmed the effectiveness of the proposed study.

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2011-04-01 2011-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2012-04-01 2012-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2014-04-01 2014-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2013-04-01 2013-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

Design of a broadband active silencer using μ-synthesis

NASA Astrophysics Data System (ADS)

Bai, Mingsian R.; Zeung, Pingshun

2004-01-01

A robust spatially feedforward controller is developed for broadband attenuation of noise in ducts. To meet the requirements of robust performance and robust stability in the presence of plant uncertainties, a μ-synthesis procedure via D- K iteration is exploited to obtain the optimal controller. This approach considers uncertainties as modelling errors of the nominal plant in high frequency and is implemented using a floating point digital signal processor (DSP). Experimental investigation was undertaken on a finite-length duct to justify the proposed controller. The μ- controller is compared to other control algorithms such as the H2 method, the H∞ method and the filtered-U least mean square (FULMS) algorithm. Experimental results indicate that the proposed system has attained 25.8 dB maximal attenuation in the band 250-650 Hz.

Seamless integration of 57.2-Gb/s signal wireline transmission and 100-GHz wireless delivery.

PubMed

Li, Xinying; Yu, Jianjun; Dong, Ze; Cao, Zizheng; Chi, Nan; Zhang, Junwen; Shao, Yufeng; Tao, Li

2012-10-22

We experimentally demonstrated the seamless integration of 57.2-Gb/s signal wireline transmission and 100-GHz wireless delivery adopting polarization-division-multiplexing quadrature-phase-shift-keying (PDM-QPSK) modulation with 400-km single-mode fiber-28 (SMF-28) transmission and 1-m wireless delivery. The X- and Y-polarization components of optical PDM-QPSK baseband signal are simultaneously up-converted to 100 GHz by optical polarization-diversity heterodyne beating, and then independently transmitted and received by two pairs of transmitter and receiver antennas, which make up a 2x2 multiple-input multiple-output (MIMO) wireless link based on microwave polarization multiplexing. At the wireless receiver, a two-stage down conversion is firstly done in analog domain based on balanced mixer and sinusoidal radio frequency (RF) signal, and then in digital domain based on digital signal processing (DSP). Polarization de-multiplexing is realized by constant modulus algorithm (CMA) based on DSP in heterodyne coherent detection. Our experimental results show that more taps are required for CMA when the X- and Y-polarization antennas have different wireless distance.

Performance of the unique-word-reverse-modulation type demodulator for mobile satellite communications

NASA Technical Reports Server (NTRS)

Dohi, Tomohiro; Nitta, Kazumasa; Ueda, Takashi

1993-01-01

This paper proposes a new type of coherent demodulator, the unique-word (UW)-reverse-modulation type demodulator, for burst signal controlled by voice operated transmitter (VOX) in mobile satellite communication channels. The demodulator has three individual circuits: a pre-detection signal combiner, a pre-detection UW detector, and a UW-reverse-modulation type demodulator. The pre-detection signal combiner combines signal sequences received by two antennas and improves bit energy-to-noise power density ratio (E(sub b)/N(sub 0)) 2.5 dB to yield 10(exp -3) average bit error rate (BER) when carrier power-to-multipath power ratio (CMR) is 15 dB. The pre-detection UW detector improves UW detection probability when the frequency offset is large. The UW-reverse-modulation type demodulator realizes a maximum pull-in frequency of 3.9 kHz, the pull-in time is 2.4 seconds and frequency error is less than 20 Hz. The performances of this demodulator are confirmed through computer simulations and its effect is clarified in real-time experiments at a bit rate of 16.8 kbps using a digital signal processor (DSP).

Emergency product generation for disaster management using RISAT and DMSAR quick look SAR processors

NASA Astrophysics Data System (ADS)

Desai, Nilesh; Sharma, Ritesh; Kumar, Saravana; Misra, Tapan; Gujraty, Virendra; Rana, SurinderSingh

2006-12-01

Since last few years, ISRO has embarked upon the development of two complex Synthetic Aperture Radar (SAR) missions, viz. Spaceborne Radar Imaging Satellite (RISAT) and Airborne SAR for Disaster Mangement (DMSAR), as a capacity building measure under country's Disaster Management Support (DMS) Program, for estimating the extent of damage over large areas (~75 Km) and also assess the effectiveness of the relief measures undertaken during natural disasters such as cyclones, epidemics, earthquakes, floods and landslides, forest fires, crop diseases etc. Synthetic Aperture Radar (SAR) has an unique role to play in mapping and monitoring of large areas affected by natural disasters especially floods, owing to its unique capability to see through clouds as well as all-weather imaging capability. The generation of SAR images with quick turn around time is very essential to meet the above DMS objectives. Thus the development of SAR Processors, for these two SAR systems poses considerable challenges and design efforts. Considering the growing user demand and inevitable necessity for a full-fledged high throughput processor, to process SAR data and generate image in real or near-real time, the design and development of a generic SAR Processor has been taken up and evolved, which will meet the SAR processing requirements for both Airborne and Spaceborne SAR systems. This hardware SAR processor is being built, to the extent possible, using only Commercial-Off-The-Shelf (COTS) DSP and other hardware plug-in modules on a Compact PCI (cPCI) platform. Thus, the major thrust has been on working out Multi-processor Digital Signal Processor (DSP) architecture and algorithm development and optimization rather than hardware design and fabrication. For DMSAR, this generic SAR Processor operates as a Quick Look SAR Processor (QLP) on-board the aircraft to produce real time full swath DMSAR images and as a ground based Near-Real Time high precision full swath Processor (NRTP). It will generate full-swath (6 to 75 Kms) DMSAR images in 1m / 3m / 5m / 10m / 30m resolution SAR operating modes. For RISAT mission, this generic Quick Look SAR Processor will be mainly used for browse product generation at NRSA-Shadnagar (SAN) ground receive station. RISAT QLP/NRTP is also proposed to provide an alternative emergency SAR product generation chain. For this, the S/C aux data appended in Onboard SAR Frame Format (x, y, z, x', y', z', roll, pitch, yaw) and predicted orbit from previous days Orbit Determination data will be used. The QLP / NRTP will produce ground range images in real / near real time. For emergency data product generation, additional Off-line tasks like geo-tagging, masking, QC etc needs to be performed on the processed image. The QLP / NRTP would generate geo-tagged images from the annotation data available from the SAR P/L data itself. Since the orbit & attitude information are taken as it is, the location accuracy will be poorer compared to the product generated using ADIF, where smoothened attitude and orbit are made available. Additional tasks like masking, output formatting and Quality checking of the data product will be carried out at Balanagar, NRSA after the image annotated data from QLP / NRTP is sent to Balanagar. The necessary interfaces to the QLP/NRTP for Emergency product generation are also being worked out. As is widely acknowledged, QLP/NRTP for RISAT and DMSAR is an ambitious effort and the technology of future. It is expected that by the middle of next decade, the next generation SAR missions worldwide will have onboard SAR Processors of varying capabilities and generate SAR Data products and Information products onboard instead of SAR raw data. Thus, it is also envisaged that these activities related to QLP/NRTP implementation for RISAT ground segment and DMSAR will be a significant step which will directly feed into the development of onboard real time processing systems for ISRO's future space borne SAR missions. This paper describes the design requirements, configuration details and salient features, apart from highlighting the utility of these Quick Look SAR processors for RISAT and DMSAR, for generation of emergency products for Disaster management.

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units.

PubMed

Rath, N; Kato, S; Levesque, J P; Mauel, M E; Navratil, G A; Peng, Q

2014-04-01

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

DSP-based CSO cancellation technique for RoF transmission system implemented by using directly modulated laser.

PubMed

Kim, Byung Gon; Bae, Sung Hyun; Kim, Hoon; Chung, Yun C

2017-05-29

We propose and demonstrate a simple composite second-order (CSO) cancellation technique based on the digital signal processing (DSP) for the radio-over-fiber (RoF) transmission system implemented by using directly modulated lasers (DMLs). When the RoF transmission system is implemented by using DMLs, its performance could be limited by the CSO distortions caused by the interplay between the DML's chirp and fiber's chromatic dispersion. We present the theoretical analysis of these nonlinear distortions and show that they can be suppressed at the receiver by using a simple DSP. To verify the effectiveness of the proposed technique, we demonstrate the transmission of twenty-four 100-MHz filtered orthogonal frequency-division multiplexing (f-OFDM) signals in 64 quadrature amplitude modulation (QAM) format over 20 km of the standard single-mode fiber (SSMF). The results show that, by using the proposed technique, we can suppress the CSO distortion components by >10 dB and achieve the error-vector magnitude performance better than 6% even after the 20-km long SSMF transmission.

Adaptive and mobile ground sensor array.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holzrichter, Michael Warren; O'Rourke, William T.; Zenner, Jennifer

The goal of this LDRD was to demonstrate the use of robotic vehicles for deploying and autonomously reconfiguring seismic and acoustic sensor arrays with high (centimeter) accuracy to obtain enhancement of our capability to locate and characterize remote targets. The capability to accurately place sensors and then retrieve and reconfigure them allows sensors to be placed in phased arrays in an initial monitoring configuration and then to be reconfigured in an array tuned to the specific frequencies and directions of the selected target. This report reviews the findings and accomplishments achieved during this three-year project. This project successfully demonstrated autonomousmore » deployment and retrieval of a payload package with an accuracy of a few centimeters using differential global positioning system (GPS) signals. It developed an autonomous, multisensor, temporally aligned, radio-frequency communication and signal processing capability, and an array optimization algorithm, which was implemented on a digital signal processor (DSP). Additionally, the project converted the existing single-threaded, monolithic robotic vehicle control code into a multi-threaded, modular control architecture that enhances the reuse of control code in future projects.« less

Cloning and baculovirus expression of a desiccation stress gene from the beetle, Tenebrio molitor.

PubMed

Graham, L A; Bendena, W G; Walker, V K

1996-02-01

The cDNA sequence encoding a novel desiccation stress protein (dsp28) found in the hemolymph of the common yellow mealworm beetle, Tenebrio molitor, has been determined. The sequence encodes a 225 amino acid protein containing a 20 amino acid signal peptide. Dsp28 shows no significant similarity to any known nucleic acid or protein sequence. Levels of dsp28 mRNA were found to increase approx 5-fold following desiccation. Dsp28 cDNA has been cloned into a baculovirus expression vector and the expressed protein was compared to native dsp28. Both dsp28 expressed by recombinant baculovirus and native dsp28 are glycosylated and N-terminally processed. Although dsp28 is induced by cold in addition to desiccation stress, it does not contribute to the freezing point depression (thermal hysteresis) observed in Tenebrio hemolymph.

Research of real-time video processing system based on 6678 multi-core DSP

NASA Astrophysics Data System (ADS)

Li, Xiangzhen; Xie, Xiaodan; Yin, Xiaoqiang

2017-10-01

In the information age, the rapid development in the direction of intelligent video processing, complex algorithm proposed the powerful challenge on the performance of the processor. In this article, through the FPGA + TMS320C6678 frame structure, the image to fog, merge into an organic whole, to stabilize the image enhancement, its good real-time, superior performance, break through the traditional function of video processing system is simple, the product defects such as single, solved the video application in security monitoring, video, etc. Can give full play to the video monitoring effectiveness, improve enterprise economic benefits.

Dual Active Bridge based DC Transformer LabVIEW FPGA Control Code

DOE Office of Scientific and Technical Information (OSTI.GOV)

In the area of power electronics control, Field Programmable Gate Arrays (FPGAs) have the capability to outperform their Digital Signal Processor (DSP) counterparts due to the FPGA’s ability to implement true parallel processing and therefore facilitate higher switching frequencies, higher control bandwidth, and/or enhanced functionality. National Instruments (NI) has developed two platforms, Compact RIO (cRIO) and Single Board RIO (sbRIO), which combine a real-time processor with an FPGA. The FPGA can be programmed with a subset of the well-known LabVIEW graphical programming language. The candidate software implements complete control algorithms in LabVIEW FPGA for a DC Transformer (DCX) based onmore » a dual active bridge (DAB). A DCX is an isolated bi-directional DC-DC converter designed to operate at unity conversion ratio, M, defined by where Vin is the primary-side DC bus voltage, Vout is the secondary-side DC bus voltage, and n is the turns ratio of the embedded high frequency transformer (HFX). The DCX based on a DAB incorporates two H-bridges, a resonant inductor, and an HFX to provide this functionality. The candidate software employs phase-shift modulation of the two H-bridges and a feedback loop to regulate the conversion ratio at unity. The software also includes alarm-handling capabilities as well as debugging and tuning tools. The software fits on the Xilinx Virtex V LX110 FPGA embedded in the NI cRIO-9118 FPGA chassis, and with a 40 MHz base clock, supports a modulation update rate of 40 MHz, and user-settable switching frequencies and synchronized control loop update rates of tens of kHz.« less

A Virtual Laboratory for Digital Signal Processing

ERIC Educational Resources Information Center

Dow, Chyi-Ren; Li, Yi-Hsung; Bai, Jin-Yu

2006-01-01

This work designs and implements a virtual digital signal processing laboratory, VDSPL. VDSPL consists of four parts: mobile agent execution environments, mobile agents, DSP development software, and DSP experimental platforms. The network capability of VDSPL is created by using mobile agent and wrapper techniques without modifying the source code…

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processors with scanning CCD photodetectors

NASA Astrophysics Data System (ADS)

Esepkina, N. A.; Lavrov, A. P.; Anan'ev, M. N.; Blagodarnyi, V. S.; Ivanov, S. I.; Mansyrev, M. I.; Molodyakov, S. A.

1995-10-01

Two new types of optoelectronic radio-signal processors were investigated. Charge-coupled device (CCD) photodetectors are used in these processors under continuous scanning conditions, i.e. in a time delay and storage mode. One of these processors is based on a CCD photodetector array with a reference-signal amplitude transparency and the other is an adaptive acousto-optical signal processor with linear frequency modulation. The processor with the transparency performs multichannel discrete—analogue convolution of an input signal with a corresponding kernel of the transformation determined by the transparency. If a light source is an array of light-emitting diodes of special (stripe) geometry, the optical stages of the processor can be made from optical fibre components and the whole processor then becomes a rigid 'sandwich' (a compact hybrid optoelectronic microcircuit). A report is given also of a study of a prototype processor with optical fibre components for the reception of signals from a system with antenna aperture synthesis, which forms a radio image of the Earth.

Adaptive Suppression of Noise in Voice Communications

NASA Technical Reports Server (NTRS)

Kozel, David; DeVault, James A.; Birr, Richard B.

2003-01-01

A subsystem for the adaptive suppression of noise in a voice communication system effects a high level of reduction of noise that enters the system through microphones. The subsystem includes a digital signal processor (DSP) plus circuitry that implements voice-recognition and spectral- manipulation techniques. The development of the adaptive noise-suppression subsystem was prompted by the following considerations: During processing of the space shuttle at Kennedy Space Center, voice communications among test team members have been significantly impaired in several instances because some test participants have had to communicate from locations with high ambient noise levels. Ear protection for the personnel involved is commercially available and is used in such situations. However, commercially available noise-canceling microphones do not provide sufficient reduction of noise that enters through microphones and thus becomes transmitted on outbound communication links.

Moving Object Detection Using Scanning Camera on a High-Precision Intelligent Holder.

PubMed

Chen, Shuoyang; Xu, Tingfa; Li, Daqun; Zhang, Jizhou; Jiang, Shenwang

2016-10-21

During the process of moving object detection in an intelligent visual surveillance system, a scenario with complex background is sure to appear. The traditional methods, such as "frame difference" and "optical flow", may not able to deal with the problem very well. In such scenarios, we use a modified algorithm to do the background modeling work. In this paper, we use edge detection to get an edge difference image just to enhance the ability of resistance illumination variation. Then we use a "multi-block temporal-analyzing LBP (Local Binary Pattern)" algorithm to do the segmentation. In the end, a connected component is used to locate the object. We also produce a hardware platform, the core of which consists of the DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) platforms and the high-precision intelligent holder.

SpaceCubeX: A Framework for Evaluating Hybrid Multi-Core CPU FPGA DSP Architectures

NASA Technical Reports Server (NTRS)

Schmidt, Andrew G.; Weisz, Gabriel; French, Matthew; Flatley, Thomas; Villalpando, Carlos Y.

2017-01-01

The SpaceCubeX project is motivated by the need for high performance, modular, and scalable on-board processing to help scientists answer critical 21st century questions about global climate change, air quality, ocean health, and ecosystem dynamics, while adding new capabilities such as low-latency data products for extreme event warnings. These goals translate into on-board processing throughput requirements that are on the order of 100-1,000 more than those of previous Earth Science missions for standard processing, compression, storage, and downlink operations. To study possible future architectures to achieve these performance requirements, the SpaceCubeX project provides an evolvable testbed and framework that enables a focused design space exploration of candidate hybrid CPU/FPGA/DSP processing architectures. The framework includes ArchGen, an architecture generator tool populated with candidate architecture components, performance models, and IP cores, that allows an end user to specify the type, number, and connectivity of a hybrid architecture. The framework requires minimal extensions to integrate new processors, such as the anticipated High Performance Spaceflight Computer (HPSC), reducing time to initiate benchmarking by months. To evaluate the framework, we leverage a wide suite of high performance embedded computing benchmarks and Earth science scenarios to ensure robust architecture characterization. We report on our projects Year 1 efforts and demonstrate the capabilities across four simulation testbed models, a baseline SpaceCube 2.0 system, a dual ARM A9 processor system, a hybrid quad ARM A53 and FPGA system, and a hybrid quad ARM A53 and DSP system.

Design and evaluation of online arithmetic for signal processing applications on FPGAs

NASA Astrophysics Data System (ADS)

Galli, Reto; Tenca, Alexandre F.

2001-11-01

This paper shows the design and the evaluation of on-line arithmetic modules for the most common operators used in DSP applications, using FPGAs as the target technology. The designs are highly optimized for the target technology and the common range of precision in DSP. The results are based on experimental data collected using CAD tools. All designs are synthesized for the same type of devices (Xilinx XC4000) for comparison, avoiding rough estimates of the system performance, and generating a more reliable and detailed comparison of on-line signal processing solutions with other state of the art approaches, such as distributed arithmetic. We show that on-line designs have a hard stand for basic DSP applications that use only addition and multiplication. However, we also show that on-line designs are able to overtake other approaches as the applications become more sophisticated, e.g. when data dependencies exist, or when non constant multiplicands restrict the use of other approaches.

UWB radar technique for arc detection in coaxial cables and waveguides

NASA Astrophysics Data System (ADS)

Maggiora, R.; Salvador, S.

2009-11-01

As spread spectrum technology has revolutionized the communications industry, Ultra Wide Band (UWB) technology is dramatically improving radar performances. These advanced signal processing techniques have been adapted to coaxial cables and waveguides to provide new features and enhanced performance on arc detection. UWB signals constituted by a sequence of chips (properly chosen to reduce side lobes and to improve detection accuracy) are transmitted along the transmission lines at a specified Pulse Repetition Frequency (PRF) and their echoes are received by means of directional couplers. The core of the receiver is an ultra high-speed correlator implemented in a Digital Signal Processor (DSP). When a target (arc) is detected, its position and its "radar cross section" are calculated to be able to provide the arc position along the transmission line and to be able to classify the type of detected arc. The "background scattering" is routinely extracted from the received signal at any pulse. This permits to be resilient to the background structure of transmission lines (bends, junctions, windows, etc.). Thanks to the localization feature, segmentation is also possible for creating sensed and non-sensed zones (for example, to be insensitive to antenna load variations).

A new high-speed IR camera system

NASA Technical Reports Server (NTRS)

Travis, Jeffrey W.; Shu, Peter K.; Jhabvala, Murzy D.; Kasten, Michael S.; Moseley, Samuel H.; Casey, Sean C.; Mcgovern, Lawrence K.; Luers, Philip J.; Dabney, Philip W.; Kaipa, Ravi C.

1994-01-01

A multi-organizational team at the Goddard Space Flight Center is developing a new far infrared (FIR) camera system which furthers the state of the art for this type of instrument by the incorporating recent advances in several technological disciplines. All aspects of the camera system are optimized for operation at the high data rates required for astronomical observations in the far infrared. The instrument is built around a Blocked Impurity Band (BIB) detector array which exhibits responsivity over a broad wavelength band and which is capable of operating at 1000 frames/sec, and consists of a focal plane dewar, a compact camera head electronics package, and a Digital Signal Processor (DSP)-based data system residing in a standard 486 personal computer. In this paper we discuss the overall system architecture, the focal plane dewar, and advanced features and design considerations for the electronics. This system, or one derived from it, may prove useful for many commercial and/or industrial infrared imaging or spectroscopic applications, including thermal machine vision for robotic manufacturing, photographic observation of short-duration thermal events such as combustion or chemical reactions, and high-resolution surveillance imaging.

Embedded DSP-based telehealth radar system for remote in-door fall detection.

PubMed

Garripoli, Carmine; Mercuri, Marco; Karsmakers, Peter; Jack Soh, Ping; Crupi, Giovanni; Vandenbosch, Guy A E; Pace, Calogero; Leroux, Paul; Schreurs, Dominique

2015-01-01

Telehealth systems and applications are extensively investigated nowadays to enhance the quality-of-care and, in particular, to detect emergency situations and to monitor the well-being of elderly people, allowing them to stay at home independently as long as possible. In this paper, an embedded telehealth system for continuous, automatic, and remote monitoring of real-time fall emergencies is presented and discussed. The system, consisting of a radar sensor and base station, represents a cost-effective and efficient healthcare solution. The implementation of the fall detection data processing technique, based on the least-square support vector machines, through a digital signal processor and the management of the communication between radar sensor and base station are detailed. Experimental tests, for a total of 65 mimicked fall incidents, recorded with 16 human subjects (14 men and two women) that have been monitored for 320 min, have been used to validate the proposed system under real circumstances. The subjects' weight is between 55 and 90 kg with heights between 1.65 and 1.82 m, while their age is between 25 and 39 years. The experimental results have shown a sensitivity to detect the fall events in real time of 100% without reporting false positives. The tests have been performed in an area where the radar's operation was not limited by practical situations, namely, signal power, coverage of the antennas, and presence of obstacles between the subject and the antennas.

Generation and coherent detection of QPSK signal using a novel method of digital signal processing

NASA Astrophysics Data System (ADS)

Zhao, Yuan; Hu, Bingliang; He, Zhen-An; Xie, Wenjia; Gao, Xiaohui

2018-02-01

We demonstrate an optical quadrature phase-shift keying (QPSK) signal transmitter and an optical receiver for demodulating optical QPSK signal with homodyne detection and digital signal processing (DSP). DSP on the homodyne detection scheme is employed without locking the phase of the local oscillator (LO). In this paper, we present an extracting one-dimensional array of down-sampling method for reducing unwanted samples of constellation diagram measurement. Such a novel scheme embodies the following major advantages over the other conventional optical QPSK signal detection methods. First, this homodyne detection scheme does not need strict requirement on LO in comparison with linear optical sampling, such as having a flat spectral density and phase over the spectral support of the source under test. Second, the LabVIEW software is directly used for recovering the QPSK signal constellation without employing complex DSP circuit. Third, this scheme is applicable to multilevel modulation formats such as M-ary PSK and quadrature amplitude modulation (QAM) or higher speed signals by making minor changes.

Software Defined Radio (SDR) and Direct Digital Synthesizer (DDS) for NMR/MRI instruments at low-field.

PubMed

Asfour, Aktham; Raoof, Kosai; Yonnet, Jean-Paul

2013-11-27

A proof-of-concept of the use of a fully digital radiofrequency (RF) electronics for the design of dedicated Nuclear Magnetic Resonance (NMR) systems at low-field (0.1 T) is presented. This digital electronics is based on the use of three key elements: a Direct Digital Synthesizer (DDS) for pulse generation, a Software Defined Radio (SDR) for a digital receiving of NMR signals and a Digital Signal Processor (DSP) for system control and for the generation of the gradient signals (pulse programmer). The SDR includes a direct analog-to-digital conversion and a Digital Down Conversion (digital quadrature demodulation, decimation filtering, processing gain…). The various aspects of the concept and of the realization are addressed with some details. These include both hardware design and software considerations. One of the underlying ideas is to enable such NMR systems to "enjoy" from existing advanced technology that have been realized in other research areas, especially in telecommunication domain. Another goal is to make these systems easy to build and replicate so as to help research groups in realizing dedicated NMR desktops for a large palette of new applications. We also would like to give readers an idea of the current trends in this field. The performances of the developed electronics are discussed throughout the paper. First FID (Free Induction Decay) signals are also presented. Some development perspectives of our work in the area of low-field NMR/MRI will be finally addressed.

High-Speed Data Acquisition and Digital Signal Processing System for PET Imaging Techniques Applied to Mammography

NASA Astrophysics Data System (ADS)

Martinez, J. D.; Benlloch, J. M.; Cerda, J.; Lerche, Ch. W.; Pavon, N.; Sebastia, A.

2004-06-01

This paper is framed into the Positron Emission Mammography (PEM) project, whose aim is to develop an innovative gamma ray sensor for early breast cancer diagnosis. Currently, breast cancer is detected using low-energy X-ray screening. However, functional imaging techniques such as PET/FDG could be employed to detect breast cancer and track disease changes with greater sensitivity. Furthermore, a small and less expensive PET camera can be utilized minimizing main problems of whole body PET. To accomplish these objectives, we are developing a new gamma ray sensor based on a newly released photodetector. However, a dedicated PEM detector requires an adequate data acquisition (DAQ) and processing system. The characterization of gamma events needs a free-running analog-to-digital converter (ADC) with sampling rates of more than 50 Ms/s and must achieve event count rates up to 10 MHz. Moreover, comprehensive data processing must be carried out to obtain event parameters necessary for performing the image reconstruction. A new generation digital signal processor (DSP) has been used to comply with these requirements. This device enables us to manage the DAQ system at up to 80 Ms/s and to execute intensive calculi over the detector signals. This paper describes our designed DAQ and processing architecture whose main features are: very high-speed data conversion, multichannel synchronized acquisition with zero dead time, a digital triggering scheme, and high throughput of data with an extensive optimization of the signal processing algorithms.

Signal processing for a single detector MOEMS based NIR micro spectrometer

NASA Astrophysics Data System (ADS)

Heberer, Andreas; Grüger, Heinrich; Zimmer, Fabian; Schenk, Harald; Kenda, Andreas; Frank, Albert; Scherf, Werner

2005-10-01

The examination of spectra in the NIR range is necessary for applications like process control, element analysis or medical systems. Typically integrated NIR spectrometers are based on optical setups with diffraction grating and detector arrays. The main disadvantage is price and availability of NIR array InGaAs-based detectors. The implementation of a scanning grating chip realized in a MOEMS technology which integrates the diffractive element makes it possible to detect spectra with single detectors time resolved. Either simple InGaAs photodiodes or cooled detectors may be used. The set up is a shrinked Czerny-Turner spectrometer. The light is coupled in by an optical fibre. After focussing the light passes the scanning grating moving at 150-500 Hz in a sinusoidal way. There it is split off in the different wavelength, the monochrome intensity is caught by a second mirror and led to the detector. The detector signal is amplified by a transimpedance stage and converted to digital with 12 bit resolution. The main part of the signal processing is done by a digital signal processor, which is used to unfold the sinusoidal position and calculate the final spectra. The data rate can be up to 3 MHz, then a spectrum is acquired every 2ms by using a 500Hz Mirror. Using the DSP, the spectrometer can operate autarkic without any PC. Then the spectrum is display on a 160 x 80 pixel graphic LCD. A keypad is used to control the functions. For communication a USB port is included, additional interfaces can be realized by a 16-pin expansion port, which is freely programmable, by the system firmware.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Semiconductor-laser Fourier processors of electric signals

NASA Astrophysics Data System (ADS)

Blok, A. S.; Bukhenskii, A. F.; Krupitskii, É. I.; Morozov, S. V.; Pelevin, V. Yu; Sergeenko, T. N.; Yakovlev, V. I.

1995-10-01

An investigation is reported of acousto-optical and fibre-optic Fourier processors of electric signals, based on semiconductor lasers. A description is given of practical acousto-optical processors with an analysis band 120 MHz wide, a resolution of 200 kHz, and 7 cm × 8 cm × 18 cm dimensions. Fibre-optic Fourier processors are considered: they represent a new class of devices which are promising for the processing of gigahertz signals.

Digital signal processing techniques for coherent optical communication

NASA Astrophysics Data System (ADS)

Goldfarb, Gilad

Coherent detection with subsequent digital signal processing (DSP) is developed, analyzed theoretically and numerically and experimentally demonstrated in various fiber-optic transmission scenarios. The use of DSP in conjunction with coherent detection unleashes the benefits of coherent detection which rely on the preservaton of full information of the incoming field. These benefits include high receiver sensitivity, the ability to achieve high spectral-efficiency and the use of advanced modulation formats. With the immense advancements in DSP speeds, many of the problems hindering the use of coherent detection in optical transmission systems have been eliminated. Most notably, DSP alleviates the need for hardware phase-locking and polarization tracking, which can now be achieved in the digital domain. The complexity previously associated with coherent detection is hence significantly diminished and coherent detection is once gain considered a feasible detection alternative. In this thesis, several aspects of coherent detection (with or without subsequent DSP) are addressed. Coherent detection is presented as a means to extend the dispersion limit of a duobinary signal using an analog decision-directed phase-lock loop. Analytical bit-error ratio estimation for quadrature phase-shift keying signals is derived. To validate the promise for high spectral efficiency, the orthogonal-wavelength-division multiplexing scheme is suggested. In this scheme the WDM channels are spaced at the symbol rate, thus achieving the spectral efficiency limit. Theory, simulation and experimental results demonstrate the feasibility of this approach. Infinite impulse response filtering is shown to be an efficient alternative to finite impulse response filtering for chromatic dispersion compensation. Theory, design considerations, simulation and experimental results relating to this topic are presented. Interaction between fiber dispersion and nonlinearity remains the last major challenge deterministic effects pose for long-haul optical data transmission. Experimental results which demonstrate the possibility to digitally mitigate both dispersion and nonlinearity are presented. Impairment compensation is achieved using backward propagation by implementing the split-step method. Efficient realizations of the dispersion compensation operator used in this implementation are considered. Infinite-impulse response and wavelet-based filtering are both investigated as a means to reduce the required computational load associated with signal backward-propagation. Possible future research directions conclude this dissertation.

Phase coherence adaptive processor for automatic signal detection and identification

NASA Astrophysics Data System (ADS)

Wagstaff, Ronald A.

2006-05-01

A continuously adapting acoustic signal processor with an automatic detection/decision aid is presented. Its purpose is to preserve the signals of tactical interest, and filter out other signals and noise. It utilizes single sensor or beamformed spectral data and transforms the signal and noise phase angles into "aligned phase angles" (APA). The APA increase the phase temporal coherence of signals and leave the noise incoherent. Coherence thresholds are set, which are representative of the type of source "threat vehicle" and the geographic area or volume in which it is operating. These thresholds separate signals, based on the "quality" of their APA coherence. An example is presented in which signals from a submerged source in the ocean are preserved, while clutter signals from ships and noise are entirely eliminated. Furthermore, the "signals of interest" were identified by the processor's automatic detection aid. Similar performance is expected for air and ground vehicles. The processor's equations are formulated in such a manner that they can be tuned to eliminate noise and exploit signal, based on the "quality" of their APA temporal coherence. The mathematical formulation for this processor is presented, including the method by which the processor continuously self-adapts. Results show nearly complete elimination of noise, with only the selected category of signals remaining, and accompanying enhancements in spectral and spatial resolution. In most cases, the concept of signal-to-noise ratio looses significance, and "adaptive automated /decision aid" is more relevant.

Demodulator electronics for laser vibrometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dudzik, G.; Waz, A. T.; Kaczmarek, P. R.

2012-06-13

One of the most important parts of a fiber-laser vibrometer is demodulation electronic section. The distortion, nonlinearity, offset and added noise of measured signal come from electronic circuits and they have direct influence on finale measuring results. Two main parameters of an investigated vibrating object: velocity V(t) and displacement s(t), influence of detected beat signals. They are: the Doppler frequency deviation f(t) and phase shift {phi}(t), respectively. Because of wide range of deviations it is difficult to use just one demodulator. That is the reason why we use three different types of demodulators. The first one is the IQ demodulator,more » which is the most sensitive one and its output is proportional to the displacement. Each IQ channel is sampled simultaneously by an analog to digital converter (ADC) integrated in a digital signal processor (DSP). The output signals from the two FM demodulators are proportional to the frequency deviation of heterodyne signals. They are sensitive directly to the velocity of the object. The main disadvantage of scattered light interferometry system is a ''speckle effect'', appearing in relatively large amplitude fluctuation of a heterodyne signal. To minimize ''speckle effect'' influence on quality of beat signals we applied the automatic gain control (AGC) system. Data acquisition, further signal processing (e.g. vibration frequency spectra) and presentation of results is realized by PC via USB interface.« less

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang Meizhen; Shi Longzhao; Wang Yuxing

2006-08-15

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13x13 mm{sup 2}, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range ofmore » a 13x13 mm{sup 2} active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was {+-}20 {mu}m. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.« less

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

NASA Astrophysics Data System (ADS)

Huang, Mei-Zhen; Shi, Long-Zhao; Wang, Yu-Xing; Ni, Yi; Li, Zhen-Qing; Ding, Hai-Feng

2006-08-01

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13×13mm2, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range of a 13×13mm2 active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was ±20μm. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.

Integration of plug-in hybrid electric vehicles (PHEV) with grid connected residential photovoltaic energy systems

NASA Astrophysics Data System (ADS)

Nagarajan, Adarsh; Shireen, Wajiha

2013-06-01

This paper proposes an approach for integrating Plug-In Hybrid Electric Vehicles (PHEV) to an existing residential photovoltaic system, to control and optimize the power consumption of residential load. Control involves determining the source from which residential load will be catered, where as optimization of power flow reduces the stress on the grid. The system built to achieve the goal is a combination of the existing residential photovoltaic system, PHEV, Power Conditioning Unit (PCU), and a controller. The PCU involves two DC-DC Boost Converters and an inverter. This paper emphasizes on developing the controller logic and its implementation in order to accommodate the flexibility and benefits of the proposed integrated system. The proposed controller logic has been simulated using MATLAB SIMULINK and further implemented using Digital Signal Processor (DSP) microcontroller, TMS320F28035, from Texas Instruments

Moving Object Detection Using Scanning Camera on a High-Precision Intelligent Holder

PubMed Central

Chen, Shuoyang; Xu, Tingfa; Li, Daqun; Zhang, Jizhou; Jiang, Shenwang

2016-01-01

During the process of moving object detection in an intelligent visual surveillance system, a scenario with complex background is sure to appear. The traditional methods, such as “frame difference” and “optical flow”, may not able to deal with the problem very well. In such scenarios, we use a modified algorithm to do the background modeling work. In this paper, we use edge detection to get an edge difference image just to enhance the ability of resistance illumination variation. Then we use a “multi-block temporal-analyzing LBP (Local Binary Pattern)” algorithm to do the segmentation. In the end, a connected component is used to locate the object. We also produce a hardware platform, the core of which consists of the DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) platforms and the high-precision intelligent holder. PMID:27775671

Current signature sensor

NASA Technical Reports Server (NTRS)

Perotti, Jose M. (Inventor); Lucena, Angel (Inventor); Ihlefeld, Curtis (Inventor); Burns, Bradley (Inventor); Bassignani, Karin E. (Inventor)

2005-01-01

A solenoid health monitoring system uses a signal conditioner and controller assembly in one embodiment that includes analog circuitry and a DSP controller. The analog circuitry provides signal conditioning to the low-level raw signal coming from a signal acquisition assembly. Software running in a DSP analyzes the incoming data (recorded current signature) and determines the state of the solenoid whether it is energized, de-energized, or in a transitioning state. In one embodiment, the software identifies key features in the current signature during the transition phase and is able to determine the health of the solenoid.

Interactive Digital Signal Processor

NASA Technical Reports Server (NTRS)

Mish, W. H.

1985-01-01

Interactive Digital Signal Processor, IDSP, consists of set of time series analysis "operators" based on various algorithms commonly used for digital signal analysis. Processing of digital signal time series to extract information usually achieved by applications of number of fairly standard operations. IDSP excellent teaching tool for demonstrating application for time series operators to artificially generated signals.

Human factors considerations in the evaluation of processor-based signal and train control systems

DOT National Transportation Integrated Search

2007-06-01

In August 2001, the Federal Railroad Administration issued the notice of proposed rulemaking: Standards for Development and : Use of Processor-Based Signal and Train Control Systems (49 Code of Federal Regulations Part 236). This proposed rule addres...

Design and DSP implementation of star image acquisition and star point fast acquiring and tracking

NASA Astrophysics Data System (ADS)

Zhou, Guohui; Wang, Xiaodong; Hao, Zhihang

2006-02-01

Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper, the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing, a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design, the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory, DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme, DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us, the data in five expanded windows including stars are moved into the internal memory of DSP, and in 1.6ms, five star coordinates are achieved in the star tracking stage.

Accuracy-energy configurable sensor processor and IoT device for long-term activity monitoring in rare-event sensing applications.

PubMed

Park, Daejin; Cho, Jeonghun

2014-01-01

A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error.

A multi-channel low-power system-on-chip for single-unit recording and narrowband wireless transmission of neural signal.

PubMed

Bonfanti, A; Ceravolo, M; Zambra, G; Gusmeroli, R; Spinelli, A S; Lacaita, A L; Angotzi, G N; Baranauskas, G; Fadiga, L

2010-01-01

This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole system is designed to work with 64 channels demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. A digital data compression, based on the detection of action potentials and storage of correspondent waveforms, allows the use of a 1.25-Mbit/s binary FSK wireless transmission. This moderate bit-rate and a low frequency deviation, Manchester-coded modulation are crucial for exploiting a narrowband wireless link and an efficient embeddable antenna. The chip is realized in a 0.35- εm CMOS process with a power consumption of 105 εW per channel (269 εW per channel with an extended transmission range of 4 m) and an area of 3.1 × 2.7 mm(2). The transmitted signal is captured by a digital TV tuner and demodulated by a wideband phase-locked loop (PLL), and then sent to a PC via an FPGA module. The system has been tested for electrical specifications and its functionality verified in in-vivo neural recording experiments.

Mutational analysis of a predicted double β-propeller domain of the DspA/E effector of Erwinia amylovora.

PubMed

Siamer, Sabrina; Gaubert, Stéphane; Boureau, Tristan; Brisset, Marie-Noëlle; Barny, Marie-Anne

2013-05-01

The bacterium Erwinia amylovora causes fire blight, an invasive disease that threatens apple trees, pear trees and other plants of the Rosaceae family. Erwinia amylovora pathogenicity relies on a type III secretion system and on a single effector DspA/E. This effector belongs to the widespread AvrE family of effectors whose biological function is unknown. In this manuscript, we performed a bioinformatic analysis of DspA/E- and AvrE-related effectors. Motif search identified nuclear localization signals, peroxisome targeting signals, endoplasmic reticulum membrane retention signals and leucine zipper motifs, but none of these motifs were present in all the AvrE-related effectors analysed. Protein threading analysis, however, predicted a conserved double β-propeller domain in the N-terminal part of all the analysed effector sequences. We then performed a random pentapeptide mutagenesis of DspA/E, which led to the characterization of 13 new altered proteins with a five amino acids insertion. Eight harboured the insertion inside the predicted β-propeller domain and six of these eight insertions impaired DspA/E stability or function. Conversely, the two remaining insertions generated proteins that were functional and abundantly secreted in the supernatant suggesting that these two insertions stabilized the protein. © 2013 Federation of European Microbiological Societies. Published by Blackwell Publishing Ltd. All rights reserved.

Signal processing for molecular and cellular biological physics: an emerging field.

PubMed

Little, Max A; Jones, Nick S

2013-02-13

Recent advances in our ability to watch the molecular and cellular processes of life in action--such as atomic force microscopy, optical tweezers and Forster fluorescence resonance energy transfer--raise challenges for digital signal processing (DSP) of the resulting experimental data. This article explores the unique properties of such biophysical time series that set them apart from other signals, such as the prevalence of abrupt jumps and steps, multi-modal distributions and autocorrelated noise. It exposes the problems with classical linear DSP algorithms applied to this kind of data, and describes new nonlinear and non-Gaussian algorithms that are able to extract information that is of direct relevance to biological physicists. It is argued that these new methods applied in this context typify the nascent field of biophysical DSP. Practical experimental examples are supplied.

Signal processing for molecular and cellular biological physics: an emerging field

PubMed Central

Little, Max A.; Jones, Nick S.

2013-01-01

Recent advances in our ability to watch the molecular and cellular processes of life in action—such as atomic force microscopy, optical tweezers and Forster fluorescence resonance energy transfer—raise challenges for digital signal processing (DSP) of the resulting experimental data. This article explores the unique properties of such biophysical time series that set them apart from other signals, such as the prevalence of abrupt jumps and steps, multi-modal distributions and autocorrelated noise. It exposes the problems with classical linear DSP algorithms applied to this kind of data, and describes new nonlinear and non-Gaussian algorithms that are able to extract information that is of direct relevance to biological physicists. It is argued that these new methods applied in this context typify the nascent field of biophysical DSP. Practical experimental examples are supplied. PMID:23277603

Combined effects of dentin sialoprotein and bone morphogenetic protein-2 on differentiation in human cementoblasts.

PubMed

Lee, So-Youn; Auh, Q-Schick; Kang, Soo-Kyung; Kim, Hyung-Joon; Lee, Jung-Woo; Noh, Kwantae; Jang, Jun-Hyeog; Kim, Eun-Cheol

2014-07-01

The aim of this study is to determine the effects of the combination of recombinant human BMP-2 (rh-BMP-2) and dentin sialoprotein (rh-DSP) on growth and differentiation in human cementoblasts and determine the underlying signal transduction mechanism. Compared to treatment of cementoblasts with either rh-BMP-2 or rh-DSP alone, the combination of rh-BMP-2 and rh-DSP synergistically increased cell growth, ALP activity, nodule formation and expression of differentiation markers. The differentiation-promoting effect was also observed in periodontal ligament cells and an osteoblastic cell line. Likewise, combination of rh-DSP and rh-BMP-2 increased BMP-2 mRNA expression and Smad1/5/8 phosphorylation, which was blocked by the BMP antagonist noggin. The expression levels of α2β1 integrin and RhoA, as well as the phosphorylation status of FAK and Akt, were increased by the combination of rh-BMP-2 and rh-DSP in a time-dependent manner. In addition, rh-BMP-2 and rh-DSP enhanced expression of Wnt ligands, β-catenin activation and GSK-3β phosphorylation, all of which were inhibited by the Wnt receptor antagonist DKK1. Furthermore, treatment with rh-DSP plus rh-BMP-2 resulted in phosphorylation of extracellular signal-regulated kinase (ERK), c-Jun N-terminal kinase (JNK) and p38 and also induced the nuclear translocation of the NF-κB p65 subunit, which was blocked by noggin. This study demonstrates for the first time that rh-DSP and rh-BMP-2 act synergistically, enhancing each other's ability to stimulate cementoblastic cell growth and differentiation in vitro via autocrine BMP, integrin, Wnt/β-catenin, MAP kinase and NF-κB pathways. These results support the therapeutic potential of a combination strategy for aiding periodontal regeneration.

SpaceCube Version 1.5

NASA Technical Reports Server (NTRS)

Geist, Alessandro; Lin, Michael; Flatley, Tom; Petrick, David

2013-01-01

SpaceCube 1.5 is a high-performance and low-power system in a compact form factor. It is a hybrid processing system consisting of CPU (central processing unit), FPGA (field-programmable gate array), and DSP (digital signal processor) processing elements. The primary processing engine is the Virtex- 5 FX100T FPGA, which has two embedded processors. The SpaceCube 1.5 System was a bridge to the SpaceCube 2.0 and SpaceCube 2.0 Mini processing systems. The SpaceCube 1.5 system was the primary avionics in the successful SMART (Small Rocket/Spacecraft Technology) Sounding Rocket mission that was launched in the summer of 2011. For SMART and similar missions, an avionics processor is required that is reconfigurable, has high processing capability, has multi-gigabit interfaces, is low power, and comes in a rugged/compact form factor. The original SpaceCube 1.0 met a number of the criteria, but did not possess the multi-gigabit interfaces that were required and is a higher-cost system. The SpaceCube 1.5 was designed with those mission requirements in mind. The SpaceCube 1.5 features one Xilinx Virtex-5 FX100T FPGA and has excellent size, weight, and power characteristics [4×4×3 in. (approx. = 10×10×8 cm), 3 lb (approx. = 1.4 kg), and 5 to 15 W depending on the application]. The estimated computing power of the two PowerPC 440s in the Virtex-5 FPGA is 1100 DMIPS each. The SpaceCube 1.5 includes two Gigabit Ethernet (1 Gbps) interfaces as well as two SATA-I/II interfaces (1.5 to 3.0 Gbps) for recording to data drives. The SpaceCube 1.5 also features DDR2 SDRAM (double data rate synchronous dynamic random access memory); 4- Gbit Flash for storing application code for the CPU, FPGA, and DSP processing elements; and a Xilinx Platform Flash XL to store FPGA configuration files or application code. The system also incorporates a 12 bit analog to digital converter with the ability to read 32 discrete analog sensor inputs. The SpaceCube 1.5 design also has a built-in accelerometer. In addition, the system has 12 receive and transmit RS- 422 interfaces for legacy support. The SpaceCube 1.5 processor card represents the first NASA Goddard design in a compact form factor featuring the Xilinx Virtex- 5. The SpaceCube 1.5 incorporates backward compatibility with the Space- Cube 1.0 form factor and stackable architecture. It also makes use of low-cost commercial parts, but is designed for operation in harsh environments.

Accuracy-Energy Configurable Sensor Processor and IoT Device for Long-Term Activity Monitoring in Rare-Event Sensing Applications

PubMed Central

2014-01-01

A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error. PMID:25580458

Rapid prototyping of an EEG-based brain-computer interface (BCI).

PubMed

Guger, C; Schlögl, A; Neuper, C; Walterspacher, D; Strein, T; Pfurtscheller, G

2001-03-01

The electroencephalogram (EEG) is modified by motor imagery and can be used by patients with severe motor impairments (e.g., late stage of amyotrophic lateral sclerosis) to communicate with their environment. Such a direct connection between the brain and the computer is known as an EEG-based brain-computer interface (BCI). This paper describes a new type of BCI system that uses rapid prototyping to enable a fast transition of various types of parameter estimation and classification algorithms to real-time implementation and testing. Rapid prototyping is possible by using Matlab, Simulink, and the Real-Time Workshop. It is shown how to automate real-time experiments and perform the interplay between on-line experiments and offline analysis. The system is able to process multiple EEG channels on-line and operates under Windows 95 in real-time on a standard PC without an additional digital signal processor (DSP) board. The BCI can be controlled over the Internet, LAN or modem. This BCI was tested on 3 subjects whose task it was to imagine either left or right hand movement. A classification accuracy between 70% and 95% could be achieved with two EEG channels after some sessions with feedback using an adaptive autoregressive (AAR) model and linear discriminant analysis (LDA).

High-frequency ultrasound annular array imaging. Part II: digital beamformer design and imaging.

PubMed

Hu, Chang-Hong; Snook, Kevin A; Cao, Pei-Jie; Shung, K Kirk

2006-02-01

This is the second part of a two-paper series reporting a recent effort in the development of a high-frequency annular array ultrasound imaging system. In this paper an imaging system composed of a six-element, 43 MHz annular array transducer, a six-channel analog front-end, a field programmable gate array (FPGA)-based beamformer, and a digital signal processor (DSP) microprocessor-based scan converter will be described. A computer is used as the interface for image display. The beamformer that applies delays to the echoes for each channel is implemented with the strategy of combining the coarse and fine delays. The coarse delays that are integer multiples of the clock periods are achieved by using a first-in-first-out (FIFO) structure, and the fine delays are obtained with a fractional delay (FD) filter. Using this principle, dynamic receiving focusing is achieved. The image from a wire phantom obtained with the imaging system was compared to that from a prototype ultrasonic backscatter microscope with a 45 MHz single-element transducer. The improved lateral resolution and depth of field from the wire phantom image were observed. Images from an excised rabbit eye sample also were obtained, and fine anatomical structures were discerned.

Use of Field Programmable Gate Array Technology in Future Space Avionics

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

High-speed parallel implementation of a modified PBR algorithm on DSP-based EH topology

NASA Astrophysics Data System (ADS)

Rajan, K.; Patnaik, L. M.; Ramakrishna, J.

1997-08-01

Algebraic Reconstruction Technique (ART) is an age-old method used for solving the problem of three-dimensional (3-D) reconstruction from projections in electron microscopy and radiology. In medical applications, direct 3-D reconstruction is at the forefront of investigation. The simultaneous iterative reconstruction technique (SIRT) is an ART-type algorithm with the potential of generating in a few iterations tomographic images of a quality comparable to that of convolution backprojection (CBP) methods. Pixel-based reconstruction (PBR) is similar to SIRT reconstruction, and it has been shown that PBR algorithms give better quality pictures compared to those produced by SIRT algorithms. In this work, we propose a few modifications to the PBR algorithms. The modified algorithms are shown to give better quality pictures compared to PBR algorithms. The PBR algorithm and the modified PBR algorithms are highly compute intensive, Not many attempts have been made to reconstruct objects in the true 3-D sense because of the high computational overhead. In this study, we have developed parallel two-dimensional (2-D) and 3-D reconstruction algorithms based on modified PBR. We attempt to solve the two problems encountered by the PBR and modified PBR algorithms, i.e., the long computational time and the large memory requirements, by parallelizing the algorithm on a multiprocessor system. We investigate the possible task and data partitioning schemes by exploiting the potential parallelism in the PBR algorithm subject to minimizing the memory requirement. We have implemented an extended hypercube (EH) architecture for the high-speed execution of the 3-D reconstruction algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs) and dual-port random access memories (DPR) as channels between the PEs. We discuss and compare the performances of the PBR algorithm on an IBM 6000 RISC workstation, on a Silicon Graphics Indigo 2 workstation, and on an EH system. The results show that an EH(3,1) using DSP chips as PEs executes the modified PBR algorithm about 100 times faster than an LBM 6000 RISC workstation. We have executed the algorithms on a 4-node IBM SP2 parallel computer. The results show that execution time of the algorithm on an EH(3,1) is better than that of a 4-node IBM SP2 system. The speed-up of an EH(3,1) system with eight PEs and one network controller is approximately 7.85.

Development of a rapid cell-fusion-based phenotypic HIV-1 tropism assay

PubMed Central

Teeranaipong, Phairote; Hosoya, Noriaki; Kawana-Tachikawa, Ai; Fujii, Takeshi; Koibuchi, Tomohiko; Nakamura, Hitomi; Koga, Michiko; Kondo, Naoyuki; Gao, George F; Hoshino, Hiroo; Matsuda, Zene; Iwamoto, Aikichi

2013-01-01

Introduction A dual split reporter protein system (DSP), recombining Renilla luciferase (RL) and green fluorescent protein (GFP) split into two different constructs (DSP1–7 and DSP8–11), was adapted to create a novel rapid phenotypic tropism assay (PTA) for HIV-1 infection (DSP-Pheno). Methods DSP1–7 was stably expressed in the glioma-derived NP-2 cell lines, which expressed CD4/CXCR4 (N4X4) or CD4/CCR5 (N4R5), respectively. An expression vector with DSP8–11 (pRE11) was constructed. The HIV-1 envelope genes were subcloned in pRE11 (pRE11-env) and transfected into 293FT cells. Transfected 293FT cells were incubated with the indicator cell lines independently. In developing the assay, we selected the DSP1–7-positive clones that showed the highest GFP activity after complementation with DSP8–11. These cell lines, designated N4R5-DSP1–7, N4X4-DSP1–7 were used for subsequent assays. Results The env gene from the reference strains (BaL for R5 virus, NL4-3 for X4 virus, SF2 for dual tropic virus) subcloned in pRE11 and tested, was concordant with the expected co-receptor usage. Assay results were available in two ways (RL or GFP). The assay sensitivity by RL activity was comparable with those of the published phenotypic assays using pseudovirus. The shortest turnaround time was 5 days after obtaining the patient's plasma. All clinical samples gave positive RL signals on R5 indicator cells in the fusion assay. Median RLU value of the low CD4 group was significantly higher on X4 indicator cells and suggested the presence of more dual or X4 tropic viruses in this group of patients. Comparison of representative samples with Geno2Pheno [co-receptor] assay was concordant. Conclusions A new cell-fusion-based, high-throughput PTA for HIV-1, which would be suitable for in-house studies, was developed. Equipped with two-way reporter system, RL and GFP, DSP-Pheno is a sensitive test with short turnaround time. Although maintenance of cell lines and laboratory equipment is necessary, it provides a safe assay system without infectious viruses. With further validation against other conventional analyses, DSP-Pheno may prove to be a useful laboratory tool. The assay may be useful especially for the research on non-B subtype HIV-1 whose co-receptor usage has not been studied much. PMID:24050252

A microcomputer based frequency-domain processor for laser Doppler anemometry

NASA Technical Reports Server (NTRS)

Horne, W. Clifton; Adair, Desmond

1988-01-01

A prototype multi-channel laser Doppler anemometry (LDA) processor was assembled using a wideband transient recorder and a microcomputer with an array processor for fast Fourier transform (FFT) computations. The prototype instrument was used to acquire, process, and record signals from a three-component wind tunnel LDA system subject to various conditions of noise and flow turbulence. The recorded data was used to evaluate the effectiveness of burst acceptance criteria, processing algorithms, and selection of processing parameters such as record length. The recorded signals were also used to obtain comparative estimates of signal-to-noise ratio between time-domain and frequency-domain signal detection schemes. These comparisons show that the FFT processing scheme allows accurate processing of signals for which the signal-to-noise ratio is 10 to 15 dB less than is practical using counter processors.

Development of a wireless system for auditory neuroscience.

PubMed

Lukes, A J; Lear, A T; Snider, R K

2001-01-01

In order to study how the auditory cortex extracts communication sounds in a realistic acoustic environment, a wireless system is being developed that will transmit acoustic as well as neural signals. The miniature transmitter will be capable of transmitting two acoustic signals with 37.5 KHz bandwidths (75 KHz sample rate) and 56 neural signals with bandwidths of 9.375 KHz (18.75 KHz sample rate). These signals will be time-division multiplexed into one high bandwidth signal with a 1.2 MHz sample rate. This high bandwidth signal will then be frequency modulated onto a 2.4 GHz carrier, which resides in the industrial, scientic, and medical (ISM) band that is designed for low-power short-range wireless applications. On the receiver side, the signal will be demodulated from the 2.4 GHz carrier and then digitized by an analog-to-digital (A/D) converter. The acoustic and neural signals will be digitally demultiplexed from the multiplexed signal into their respective channels. Oversampling (20 MHz) will allow the reconstruction of the multiplexing clock by a digital signal processor (DSP) that will perform frame and bit synchronization. A frame is a subset of the signal that contains all the channels and several channels tied high and low will signal the start of a frame. This technological development will bring two benefits to auditory neuroscience. It will allow simultaneous recording of many neurons that will permit studies of population codes. It will also allow neural functions to be determined in higher auditory areas by correlating neural and acoustic signals without apriori knowledge of the necessary stimuli.

Using DSP technology to simplify deep space ranging

NASA Technical Reports Server (NTRS)

Bryant, S.

2000-01-01

Commercially available Digital Signal Processing (DSP) technology has enabled a new spacecraft ranging design. The new design reduces overall size, parts count, and complexity. The design implementation will also meet the Jet Propulsion Laboratory (JPL) requirements for both near-Earth and deep space ranging.

A rigorous analysis of digital pre-emphasis and DAC resolution for interleaved DAC Nyquist-WDM signal generation in high-speed coherent optical transmission systems

NASA Astrophysics Data System (ADS)

Weng, Yi; Wang, Junyi; He, Xuan; Pan, Zhongqi

2018-02-01

The Nyquist spectral shaping techniques facilitate a promising solution to enhance spectral efficiency (SE) and further reduce the cost-per-bit in high-speed wavelength-division multiplexing (WDM) transmission systems. Hypothetically, any Nyquist WDM signals with arbitrary shapes can be generated by the use of the digital signal processing (DSP) based electrical filters (E-filter). Nonetheless, in actual 100G/ 200G coherent systems, the performance as well as DSP complexity are increasingly restricted by cost and power consumption. Henceforward it is indispensable to optimize DSP to accomplish the preferred performance at the least complexity. In this paper, we systematically investigated the minimum requirements and challenges of Nyquist WDM signal generation, particularly for higher-order modulation formats, including 16 quadrature amplitude modulation (QAM) or 64QAM. A variety of interrelated parameters, such as channel spacing and roll-off factor, have been evaluated to optimize the requirements of the digital-to-analog converter (DAC) resolution and transmitter E-filter bandwidth. The impact of spectral pre-emphasis has been predominantly enhanced via the proposed interleaved DAC architecture by at least 4%, and hence reducing the required optical signal to noise ratio (OSNR) at a bit error rate (BER) of 10-3 by over 0.45 dB at a channel spacing of 1.05 symbol rate and an optimized roll-off factor of 0.1. Furthermore, the requirements of sampling rate for different types of super-Gaussian E-filters are discussed for 64QAM Nyquist WDM transmission systems. Finally, the impact of the non-50% duty cycle error between sub-DACs upon the quality of the generated signals for the interleaved DAC structure has been analyzed.

Servomotor and Controller Having Large Dynamic Range

NASA Technical Reports Server (NTRS)

Alhorn, Dean C.; Howard, David E.; Smith, Dennis A.; Dutton, Ken; Paulson, M. Scott

2007-01-01

A recently developed micro-commanding rotational-position-control system offers advantages of less mechanical complexity, less susceptibility to mechanical resonances, less power demand, less bulk, less weight, and lower cost, relative to prior rotational-position-control systems based on stepping motors and gear drives. This system includes a digital-signal- processor (DSP)-based electronic controller, plus a shaft-angle resolver and a servomotor mounted on the same shaft. Heretofore, micro-stepping has usually been associated with stepping motors, but in this system, the servomotor is micro-commanded in response to rotational-position feedback from the shaft-angle resolver. The shaft-angle resolver is of a four-speed type chosen because it affords four times the resolution of a single-speed resolver. A key innovative aspect of this system is its position-feedback signal- conditioning circuits, which condition the resolver output signal for multiple ranges of rotational speed. In the preferred version of the system, two rotational- speed ranges are included, but any number of ranges could be added to expand the speed range or increase resolution in particular ranges. In the preferred version, the resolver output is conditioned with two resolver-to-digital converters (RDCs). One RDC is used for speeds from 0.00012 to 2.5 rpm; the other RDC is used for speeds of 2.5 to 6,000 rpm. For the lower speed range, the number of discrete steps of RDC output per revolution was set at 262,144 (4 quadrants at 16 bits per quadrant). For the higher speed range, the number of discrete steps per revolution was set at 4,096 (4 quadrants at 10 bits per quadrant).

Analog Signal Correlating Using an Analog-Based Signal Conditioning Front End

NASA Technical Reports Server (NTRS)

Prokop, Norman; Krasowski, Michael

2013-01-01

This innovation is capable of correlating two analog signals by using an analog-based signal conditioning front end to hard-limit the analog signals through adaptive thresholding into a binary bit stream, then performing the correlation using a Hamming "similarity" calculator function embedded in a one-bit digital correlator (OBDC). By converting the analog signal into a bit stream, the calculation of the correlation function is simplified, and less hardware resources are needed. This binary representation allows the hardware to move from a DSP where instructions are performed serially, into digital logic where calculations can be performed in parallel, greatly speeding up calculations.

Coherent detection in optical fiber systems.

PubMed

Ip, Ezra; Lau, Alan Pak Tao; Barros, Daniel J F; Kahn, Joseph M

2008-01-21

The drive for higher performance in optical fiber systems has renewed interest in coherent detection. We review detection methods, including noncoherent, differentially coherent, and coherent detection, as well as a hybrid method. We compare modulation methods encoding information in various degrees of freedom (DOF). Polarization-multiplexed quadrature-amplitude modulation maximizes spectral efficiency and power efficiency, by utilizing all four available DOF, the two field quadratures in the two polarizations. Dual-polarization homodyne or heterodyne downconversion are linear processes that can fully recover the received signal field in these four DOF. When downconverted signals are sampled at the Nyquist rate, compensation of transmission impairments can be performed using digital signal processing (DSP). Linear impairments, including chromatic dispersion and polarization-mode dispersion, can be compensated quasi-exactly using finite impulse response filters. Some nonlinear impairments, such as intra-channel four-wave mixing and nonlinear phase noise, can be compensated partially. Carrier phase recovery can be performed using feedforward methods, even when phase-locked loops may fail due to delay constraints. DSP-based compensation enables a receiver to adapt to time-varying impairments, and facilitates use of advanced forward-error-correction codes. We discuss both single- and multi-carrier system implementations. For a given modulation format, using coherent detection, they offer fundamentally the same spectral efficiency and power efficiency, but may differ in practice, because of different impairments and implementation details. With anticipated advances in analog-to-digital converters and integrated circuit technology, DSP-based coherent receivers at bit rates up to 100 Gbit/s should become practical within the next few years.

78 FR 70888 - Need for Agency Approval of a Railroad's Use of Certain Technology That Has Been Previously...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-11-27

... technologies, namely safety-critical processor-based signal or train control systems, including subsystems and... or train control system (including a subsystem or component thereof) that was in service as of June 6... processor-based signal or train control system, subsystem, or component.'' See 49 CFR 236.903. Under Subpart...

Video sensor architecture for surveillance applications.

PubMed

Sánchez, Jordi; Benet, Ginés; Simó, José E

2012-01-01

This paper introduces a flexible hardware and software architecture for a smart video sensor. This sensor has been applied in a video surveillance application where some of these video sensors are deployed, constituting the sensory nodes of a distributed surveillance system. In this system, a video sensor node processes images locally in order to extract objects of interest, and classify them. The sensor node reports the processing results to other nodes in the cloud (a user or higher level software) in the form of an XML description. The hardware architecture of each sensor node has been developed using two DSP processors and an FPGA that controls, in a flexible way, the interconnection among processors and the image data flow. The developed node software is based on pluggable components and runs on a provided execution run-time. Some basic and application-specific software components have been developed, in particular: acquisition, segmentation, labeling, tracking, classification and feature extraction. Preliminary results demonstrate that the system can achieve up to 7.5 frames per second in the worst case, and the true positive rates in the classification of objects are better than 80%.

Video Sensor Architecture for Surveillance Applications

PubMed Central

Sánchez, Jordi; Benet, Ginés; Simó, José E.

2012-01-01

This paper introduces a flexible hardware and software architecture for a smart video sensor. This sensor has been applied in a video surveillance application where some of these video sensors are deployed, constituting the sensory nodes of a distributed surveillance system. In this system, a video sensor node processes images locally in order to extract objects of interest, and classify them. The sensor node reports the processing results to other nodes in the cloud (a user or higher level software) in the form of an XML description. The hardware architecture of each sensor node has been developed using two DSP processors and an FPGA that controls, in a flexible way, the interconnection among processors and the image data flow. The developed node software is based on pluggable components and runs on a provided execution run-time. Some basic and application-specific software components have been developed, in particular: acquisition, segmentation, labeling, tracking, classification and feature extraction. Preliminary results demonstrate that the system can achieve up to 7.5 frames per second in the worst case, and the true positive rates in the classification of objects are better than 80%. PMID:22438723

Kramers-Kronig receiver operable without digital upsampling.

PubMed

Bo, Tianwai; Kim, Hoon

2018-05-28

The Kramers-Kronig (KK) receiver is capable of retrieving the phase information of optical single-sideband (SSB) signal from the optical intensity when the optical signal satisfies the minimum phase condition. Thus, it is possible to direct-detect the optical SSB signal without suffering from the signal-signal beat interference and linear transmission impairments. However, due to the spectral broadening induced by nonlinear operations in the conventional KK algorithm, it is necessary to employ the digital upsampling at the beginning of the digital signal processing (DSP). The increased number of samples at the DSP would hinder the real-time implementation of this attractive receiver. Hence, we propose a new DSP algorithm for KK receiver operable at 2 samples per symbol. We adopt a couple of mathematical approximations to avoid the use of nonlinear operations such as logarithm and exponential functions. By using the proposed algorithm, we demonstrate the transmission of 112-Gb/s SSB orthogonal frequency-division-multiplexed signal over an 80-km fiber link. The results show that the proposed algorithm operating at 2 samples per symbol exhibits similar performance to the conventional KK one operating at 6 samples per symbol. We also present the error analysis of the proposed algorithm for KK receiver in comparison with the conventional one.

A new instantaneous torque control of PM synchronous motor for high-performance direct-drive applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chung, S.K.; Kim, H.S.; Kim, C.G.

1998-05-01

a new instantaneous torque-control strategy is presented for high-performance control of a permanent magnet (PM) synchronous motor. In order to deal with the torque pulsating problem of a PM synchronous motor in a low-speed region, new torque estimation and control techniques are proposed. The linkage flux of a PM synchronous motor is estimated using a model reference adaptive system technique, and the developed torque is instantaneously controlled by the proposed torque controller combining a variable structure control (VSC) with a space-vector pulse-width modulation (PWM). The proposed control provides the advantage of reducing the torque pulsation caused by the nonsinusoidal fluxmore » distribution. This control strategy is applied to the high-torque PM synchronous motor drive system for direct-drive applications and implemented by using a software of the digital signal processor (DSP) TMS320C30. The simulations and experiments are carried out for this system, and the results well demonstrate the effectiveness of the proposed control.« less

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

NASA Astrophysics Data System (ADS)

Verma, Bipin Kumar; Akashe, Shyam; Sharma, Sanjay

2015-09-01

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes - sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.

Electronic polarization-division demultiplexing based on digital signal processing in intensity-modulation direct-detection optical communication systems.

PubMed

Kikuchi, Kazuro

2014-01-27

We propose a novel configuration of optical receivers for intensity-modulation direct-detection (IM · DD) systems, which can cope with dual-polarization (DP) optical signals electrically. Using a Stokes analyzer and a newly-developed digital signal-processing (DSP) algorithm, we can achieve polarization tracking and demultiplexing in the digital domain after direct detection. Simulation results show that the power penalty stemming from digital polarization manipulations is negligibly small.

Video Guidance Sensor and Time-of-Flight Rangefinder

NASA Technical Reports Server (NTRS)

Bryan, Thomas; Howard, Richard; Bell, Joseph L.; Roe, Fred D.; Book, Michael L.

2007-01-01

A proposed video guidance sensor (VGS) would be based mostly on the hardware and software of a prior Advanced VGS (AVGS), with some additions to enable it to function as a time-of-flight rangefinder (in contradistinction to a triangulation or image-processing rangefinder). It would typically be used at distances of the order of 2 or 3 kilometers, where a typical target would appear in a video image as a single blob, making it possible to extract the direction to the target (but not the orientation of the target or the distance to the target) from a video image of light reflected from the target. As described in several previous NASA Tech Briefs articles, an AVGS system is an optoelectronic system that provides guidance for automated docking of two vehicles. In the original application, the two vehicles are spacecraft, but the basic principles of design and operation of the system are applicable to aircraft, robots, objects maneuvered by cranes, or other objects that may be required to be aligned and brought together automatically or under remote control. In a prior AVGS system of the type upon which the now-proposed VGS is largely based, the tracked vehicle is equipped with one or more passive targets that reflect light from one or more continuous-wave laser diode(s) on the tracking vehicle, a video camera on the tracking vehicle acquires images of the targets in the reflected laser light, the video images are digitized, and the image data are processed to obtain the direction to the target. The design concept of the proposed VGS does not call for any memory or processor hardware beyond that already present in the prior AVGS, but does call for some additional hardware and some additional software. It also calls for assignment of some additional tasks to two subsystems that are parts of the prior VGS: a field-programmable gate array (FPGA) that generates timing and control signals, and a digital signal processor (DSP) that processes the digitized video images. The additional timing and control signals generated by the FPGA would cause the VGS to alternate between an imaging (direction-finding) mode and a time-of-flight (range-finding mode) and would govern operation in the range-finding mode.

Real-time multisensor data fusion for target detection, classification, tracking, counting, and range estimates

NASA Astrophysics Data System (ADS)

Tsui, Eddy K.; Thomas, Russell L.

2004-09-01

As part of the Commanding General of Army Material Command's Research, Development & Engineering Command (RDECOM), the U.S. Army Research Development and Engineering Center (ARDEC), Picatinny funded a joint development effort with McQ Associates, Inc. to develop an Advanced Minefield Sensor (AMS) as a technology evaluation prototype for the Anti-Personnel Landmine Alternatives (APLA) Track III program. This effort laid the fundamental groundwork of smart sensors for detection and classification of targets, identification of combatant or noncombatant, target location and tracking at and between sensors, fusion of information across targets and sensors, and automatic situation awareness to the 1st responder. The efforts have culminated in developing a performance oriented architecture meeting the requirements of size, weight, and power (SWAP). The integrated digital signal processor (DSP) paradigm is capable of computing signals from sensor modalities to extract needed information within either a 360° or fixed field of view with acceptable false alarm rate. This paper discusses the challenges in the developments of such a sensor, focusing on achieving reasonable operating ranges, achieving low power, small size and low cost, and applications for extensions of this technology.

Pre-Hardware Optimization and Implementation Of Fast Optics Closed Control Loop Algorithms

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Lyon, Richard G.; Herman, Jay R.; Abuhassan, Nader

2004-01-01

One of the main heritage tools used in scientific and engineering data spectrum analysis is the Fourier Integral Transform and its high performance digital equivalent - the Fast Fourier Transform (FFT). The FFT is particularly useful in two-dimensional (2-D) image processing (FFT2) within optical systems control. However, timing constraints of a fast optics closed control loop would require a supercomputer to run the software implementation of the FFT2 and its inverse, as well as other image processing representative algorithm, such as numerical image folding and fringe feature extraction. A laboratory supercomputer is not always available even for ground operations and is not feasible for a night project. However, the computationally intensive algorithms still warrant alternative implementation using reconfigurable computing technologies (RC) such as Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA), which provide low cost compact super-computing capabilities. We present a new RC hardware implementation and utilization architecture that significantly reduces the computational complexity of a few basic image-processing algorithm, such as FFT2, image folding and phase diversity for the NASA Solar Viewing Interferometer Prototype (SVIP) using a cluster of DSPs and FPGAs. The DSP cluster utilization architecture also assures avoidance of a single point of failure, while using commercially available hardware. This, combined with the control algorithms pre-hardware optimization, or the first time allows construction of image-based 800 Hertz (Hz) optics closed control loops on-board a spacecraft, based on the SVIP ground instrument. That spacecraft is the proposed Earth Atmosphere Solar Occultation Imager (EASI) to study greenhouse gases CO2, C2H, H2O, O3, O2, N2O from Lagrange-2 point in space. This paper provides an advanced insight into a new type of science capabilities for future space exploration missions based on on-board image processing for control and for robotics missions using vision sensors. It presents a top-level description of technologies required for the design and construction of SVIP and EASI and to advance the spatial-spectral imaging and large-scale space interferometry science and engineering.

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

NASA Astrophysics Data System (ADS)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed to DDC block, which down converts the data to base-band. The DDC block has NCO, mixer and two chains of Bessel filters (fifth order cascaded integration comb filter, two FIR filters, two half band filters and programmable FIR filters) for in-phase (I) and Quadrature phase (Q) channels. The NCO has 32 bits and is set to match the output frequency of ADC. Further, DDC down samples (decimation) the data and reduces the data rate to 16 MSPS. This data is further decimated and the data rate is reduced down to 4/2/1/0.5/0.25/0.125/0.0625 MSPS for baud lengths 0.25/0.5/1/2/4/8/16 μs respectively. The down sampled data is then fed to decoding block, which performs cross correlation to achieve pulse compression of the binary-phase coded data to obtain better range resolution with maximum possible height coverage. This step improves the signal power by a factor equal to the length of the code. Coherent integration block integrates the decoded data coherently for successive pulses, which improves the signal to noise ratio and reduces the data volume. DDC, decoding and coherent integration blocks are implemented in Xilinx vertex5 FPGA. Till this point, function of all six channels is same for DBS mode and multi-receiver modes. Data from vertex5 FPGA is transferred to PC via GbE-1 interface for multi-modes or to two Analog devices make ADSP-TS201 DSP chips (A and B), via link port for DBS mode. ADSP-TS201 chips perform the normalization, DC removal, windowing, FFT computation and spectral averaging on the data, which is transferred to storage/display PC via GbE-2 interface for real-time data display and data storing. Physical layer of GbE interface is implemented in an external chip (Marvel 88E1111) and MAC layer is implemented internal to vertex5 FPGA. The MCDRx has total 4 GB of DDR2 memory for data storage. Spartan6 FPGA is used for generating timing signals, required for basic operation of the radar and testing of the MCDRx.

Electrochemical sensing using voltage-current time differential

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woo, Leta Yar-Li; Glass, Robert Scott; Fitzpatrick, Joseph Jay

2017-02-28

A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms.more » The processor also outputs the determined value.« less

Laser pulse coded signal frequency measuring device based on DSP and CPLD

NASA Astrophysics Data System (ADS)

Zhang, Hai-bo; Cao, Li-hua; Geng, Ai-hui; Li, Yan; Guo, Ru-hai; Wang, Ting-feng

2011-06-01

Laser pulse code is an anti-jamming measures used in semi-active laser guided weapons. On account of the laser-guided signals adopting pulse coding mode and the weak signal processing, it need complex calculations in the frequency measurement process according to the laser pulse code signal time correlation to meet the request in optoelectronic countermeasures in semi-active laser guided weapons. To ensure accurately completing frequency measurement in a short time, it needed to carry out self-related process with the pulse arrival time series composed of pulse arrival time, calculate the signal repetition period, and then identify the letter type to achieve signal decoding from determining the time value, number and rank number in a signal cycle by Using CPLD and DSP for signal processing chip, designing a laser-guided signal frequency measurement in the pulse frequency measurement device, improving the signal processing capability through the appropriate software algorithms. In this article, we introduced the principle of frequency measurement of the device, described the hardware components of the device, the system works and software, analyzed the impact of some system factors on the accuracy of the measurement. The experimental results indicated that this system improve the accuracy of the measurement under the premise of volume, real-time, anti-interference, low power of the laser pulse frequency measuring device. The practicality of the design, reliability has been demonstrated from the experimental point of view.

A plug-in to Eclipse for VHDL source codes: functionalities

NASA Astrophysics Data System (ADS)

Niton, B.; Poźniak, K. T.; Romaniuk, R. S.

The paper presents an original application, written by authors, which supports writing and edition of source codes in VHDL language. It is a step towards fully automatic, augmented code writing for photonic and electronic systems, also systems based on FPGA and/or DSP processors. An implementation is described, based on VEditor. VEditor is a free license program. Thus, the work presented in this paper supplements and extends this free license. The introduction characterizes shortly available tools on the market which serve for aiding the design processes of electronic systems in VHDL. Particular attention was put on plug-ins to the Eclipse environment and Emacs program. There are presented detailed properties of the written plug-in such as: programming extension conception, and the results of the activities of formatter, re-factorizer, code hider, and other new additions to the VEditor program.

The Status of the ACRF Millimeter Wave Cloud Radars (MMCRs), the Path Forward for Future MMCR Upgrades, the Concept of 3D Volume Imaging Radar and the UAV Radar

DOE Office of Scientific and Technical Information (OSTI.GOV)

P Kollias; MA Miller; KB Widener

2005-12-30

The United States (U.S.) Department of Energy (DOE) Atmospheric Radiation Measurement (ARM) Climate Research Facility (ACRF) operates millimeter wavelength cloud radars (MMCRs) in several climatological regimes. The MMCRs, are the primary observing tool for quantifying the properties of nearly all radiatively important clouds over the ACRF sites. The first MMCR was installed at the ACRF Southern Great Plains (SGP) site nine years ago and its original design can be traced to the early 90s. Since then, several MMCRs have been deployed at the ACRF sites, while no significant hardware upgrades have been performed. Recently, a two-stage upgrade (first C-40 Digitalmore » Signal Processors [DSP]-based, and later the PC-Integrated Radar AcQuisition System [PIRAQ-III] digital receiver) of the MMCR signal-processing units was completed. Our future MMCR related goals are: 1) to have a cloud radar system that continues to have high reliability and uptime and 2) to suggest potential improvements that will address increased sensitivity needs, superior sampling and low cost maintenance of the MMCRs. The Traveling Wave Tube (TWT) technology, the frequency (35-GHz), the radio frequency (RF) layout, antenna, the calibration and radar control procedure and the environmental enclosure of the MMCR remain assets for our ability to detect the profile of hydrometeors at all heights in the troposphere at the ACRF sites.« less

A distributed fault-tolerant signal processor /FTSP/

NASA Astrophysics Data System (ADS)

Bonneau, R. J.; Evett, R. C.; Young, M. J.

1980-01-01

A digital fault-tolerant signal processor (FTSP), an example of a self-repairing programmable system is analyzed. The design configuration is discussed in terms of fault tolerance, system-level fault detection, isolation and common memory. Special attention is given to the FDIR (fault detection isolation and reconfiguration) logic, noting that the reconfiguration decisions are based on configuration, summary status, end-around tests, and north marker/synchro data. Several mechanisms of fault detection are described which initiate reconfiguration at different levels. It is concluded that the reliability of a signal processor can be significantly enhanced by the use of fault-tolerant techniques.

An embedded multi-core parallel model for real-time stereo imaging

NASA Astrophysics Data System (ADS)

He, Wenjing; Hu, Jian; Niu, Jingyu; Li, Chuanrong; Liu, Guangyu

2018-04-01

The real-time processing based on embedded system will enhance the application capability of stereo imaging for LiDAR and hyperspectral sensor. The task partitioning and scheduling strategies for embedded multiprocessor system starts relatively late, compared with that for PC computer. In this paper, aimed at embedded multi-core processing platform, a parallel model for stereo imaging is studied and verified. After analyzing the computing amount, throughout capacity and buffering requirements, a two-stage pipeline parallel model based on message transmission is established. This model can be applied to fast stereo imaging for airborne sensors with various characteristics. To demonstrate the feasibility and effectiveness of the parallel model, a parallel software was designed using test flight data, based on the 8-core DSP processor TMS320C6678. The results indicate that the design performed well in workload distribution and had a speed-up ratio up to 6.4.

Parallel Implementation of the Wideband DOA Algorithm on the IBM Cell BE Processor

DTIC Science & Technology

2010-05-01

Abstract—The Multiple Signal Classification ( MUSIC ) algorithm is a powerful technique for determining the Direction of Arrival (DOA) of signals...Broadband Engine Processor (Cell BE). The process of adapting the serial based MUSIC algorithm to the Cell BE will be analyzed in terms of parallelism and...using Multiple Signal Classification MUSIC algorithm [4] • Computation of Focus matrix • Computation of number of sources • Separation of Signal

MASTERS: A Virtual Lab on Multimedia Systems for Telecommunications, Medical, and Remote Sensing Applications

ERIC Educational Resources Information Center

Alexiadis, D. S.; Mitianoudis, N.

2013-01-01

Digital signal processing (DSP) has been an integral part of most electrical, electronic, and computer engineering curricula. The applications of DSP in multimedia (audio, image, video) storage, transmission, and analysis are also widely taught at both the undergraduate and post-graduate levels, as digital multimedia can be encountered in most…

Prototyping scalable digital signal processing systems for radio astronomy using dataflow models

NASA Astrophysics Data System (ADS)

Sane, N.; Ford, J.; Harris, A. I.; Bhattacharyya, S. S.

2012-05-01

There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decimation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. First, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

Analytical estimation of laser phase noise induced BER floor in coherent receiver with digital signal processing.

PubMed

Vanin, Evgeny; Jacobsen, Gunnar

2010-03-01

The Bit-Error-Ratio (BER) floor caused by the laser phase noise in the optical fiber communication system with differential quadrature phase shift keying (DQPSK) and coherent detection followed by digital signal processing (DSP) is analytically evaluated. An in-phase and quadrature (I&Q) receiver with a carrier phase recovery using DSP is considered. The carrier phase recovery is based on a phase estimation of a finite sum (block) of the signal samples raised to the power of four and the phase unwrapping at transitions between blocks. It is demonstrated that errors generated at block transitions cause the dominating contribution to the system BER floor when the impact of the additive noise is negligibly small in comparison with the effect of the laser phase noise. Even the BER floor in the case when the phase unwrapping is omitted is analytically derived and applied to emphasize the crucial importance of this signal processing operation. The analytical results are verified by full Monte Carlo simulations. The BER for another type of DQPSK receiver operation, which is based on differential phase detection, is also obtained in the analytical form using the principle of conditional probability. The principle of conditional probability is justified in the case of differential phase detection due to statistical independency of the laser phase noise induced signal phase error and the additive noise contributions. Based on the achieved analytical results the laser linewidth tolerance is calculated for different system cases.

Electrochemical sensing using comparison of voltage-current time differential values during waveform generation and detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woo, Leta Yar-Li; Glass, Robert Scott; Fitzpatrick, Joseph Jay

2018-01-02

A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms.more » The processor also outputs the determined value.« less

Parallel Processing with Digital Signal Processing Hardware and Software

NASA Technical Reports Server (NTRS)

Swenson, Cory V.

1995-01-01

The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

Clinical study of hearing instruments: a cross-sectional longitudinal audit based on consumer experiences.

PubMed

Parving, A; Sibelle, P

2001-01-01

The objective of the present audit was to document improvements/changes in hearing instrument (HI) benefit in terms of use and satisfaction throughout the 1990s and compare the benefit in consumers fitted with analogue (A), programmable (P), and digital signal processing (DSP) HIs. The audit data are based on a questionnaire mailed to subjects fitted with HIs 3 to 4 months after the fitting, including questions concerning satisfaction with the HI, use of the HI, ability to manage the HI, and satisfaction with the overall services in the department. Information was obtained from 32,694 subjects (i.e., 71.2 per cent of those fitted with HIs throughout the last decade), with a median age at fitting of 78 years (range, 18-102), with a preponderance of females. No significant differences in age, gender distribution, and hearing instrument distribution were found between the respondents and non-respondents. The audit shows that there are no significant differences in any of the benefit parameters throughout the decade, irrespective of the introduction of P-HIs in 1995 and of the DSP-HIs in 1998. Thus, from the consumers' perspective, no changes have appeared in the last decade. A comparative analysis of the A-HIs, P-HIs, and DSP-HIs shows that among those provided with P-HIs and DSP-HIs, only 69.6 per cent (CI 68.1-71.0) and 65.5 per cent (CI 60.2-78.8), respectively, were very satisfied/satisfied with the HI, which is significantly less than the 73.5 per cent (CI 72.4-74.5) in those fitted with A-HIs. The daily/weekly use of all three types of HIs was similar. However, the group fitted with DSP-HIs was significantly less satisfied with the general services compared with those fitted with A-HIs and P-HIs, respectively. Based on these audit data, it is concluded that, according to the consumers, the outcome from HIs has not changed over the last decade, and a comparison between the traditional A-HIs with both P-HIs and DSP-HIs is in favour of the traditional A-HIs.

Low-Cutoff, High-Pass Digital Filtering of Neural Signals

NASA Technical Reports Server (NTRS)

Mojarradi,Mohammad; Johnson, Travis; Ortiz, Monico; Cunningham, Thomas; Andersen, Richard

2004-01-01

The figure depicts the major functional blocks of a system, now undergoing development, for conditioning neural signals acquired by electrodes implanted in a brain. The overall functions to be performed by this system can be summarized as preamplification, multiplexing, digitization, and high-pass filtering. Other systems under development for recording neural signals typically contain resistor-capacitor analog low-pass filters characterized by cutoff frequencies in the vicinity of 100 Hz. In the application for which this system is being developed, there is a requirement for a cutoff frequency of 5 Hz. Because the resistors needed to obtain such a low cutoff frequency would be impractically large, it was decided to perform low-pass filtering by use of digital rather than analog circuitry. In addition, it was decided to timemultiplex the digitized signals from the multiple input channels into a single stream of data in a single output channel. The signal in each input channel is first processed by a preamplifier having a voltage gain of approximately 50. Embedded in each preamplifier is a low-pass anti-aliasing filter having a cutoff frequency of approximately 10 kHz. The anti-aliasing filters make it possible to couple the outputs of the preamplifiers to the input ports of a multiplexer. The output of the multiplexer is a single stream of time-multiplexed samples of analog signals. This stream is processed by a main differential amplifier, the output of which is sent to an analog-to-digital converter (ADC). The output of the ADC is sent to a digital signal processor (DSP).

Fast neural net simulation with a DSP processor array.

PubMed

Muller, U A; Gunzinger, A; Guggenbuhl, W

1995-01-01

This paper describes the implementation of a fast neural net simulator on a novel parallel distributed-memory computer. A 60-processor system, named MUSIC (multiprocessor system with intelligent communication), is operational and runs the backpropagation algorithm at a speed of 330 million connection updates per second (continuous weight update) using 32-b floating-point precision. This is equal to 1.4 Gflops sustained performance. The complete system with 3.8 Gflops peak performance consumes less than 800 W of electrical power and fits into a 19-in rack. While reaching the speed of modern supercomputers, MUSIC still can be used as a personal desktop computer at a researcher's own disposal. In neural net simulation, this gives a computing performance to a single user which was unthinkable before. The system's real-time interfaces make it especially useful for embedded applications.

Terabit bandwidth-adaptive transmission using low-complexity format-transparent digital signal processing.

PubMed

Zhuge, Qunbi; Morsy-Osman, Mohamed; Chagnon, Mathieu; Xu, Xian; Qiu, Meng; Plant, David V

2014-02-10

In this paper, we propose a low-complexity format-transparent digital signal processing (DSP) scheme for next generation flexible and energy-efficient transceiver. It employs QPSK symbols as the training and pilot symbols for the initialization and tracking stage of the receiver-side DSP, respectively, for various modulation formats. The performance is numerically and experimentally evaluated in a dual polarization (DP) 11 Gbaud 64QAM system. Employing the proposed DSP scheme, we conduct a system-level study of Tb/s bandwidth-adaptive superchannel transmissions with flexible modulation formats including QPSK, 8QAM and 16QAM. The spectrum bandwidth allocation is realized in the digital domain instead of turning on/off sub-channels, which improves the performance of higher order QAM. Various transmission distances ranging from 240 km to 6240 km are demonstrated with a colorless detection for hardware complexity reduction.

A new FPGA architecture suitable for DSP applications

NASA Astrophysics Data System (ADS)

Liyun, Wang; Jinmei, Lai; Jiarong, Tong; Pushan, Tang; Xing, Chen; Xueyan, Duan; Liguang, Chen; Jian, Wang; Yuan, Wang

2011-05-01

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

Fiber-wireless transmission system of 108  Gb/sdata over 80 km fiber and 2×2multiple-input multiple-output wireless links at 100 GHz W-band frequency.

PubMed

Li, Xinying; Dong, Ze; Yu, Jianjun; Chi, Nan; Shao, Yufeng; Chang, G K

2012-12-15

We experimentally demonstrate a seamlessly integrated fiber-wireless system that delivers a 108  Gb/s signal through 80 km fiber and 1 m wireless transport over free space at 100 GHz adopting polarization-division-multiplexing quadrature-phase-shift-keying (PDM-QPSK) modulation and heterodyning coherent detection. The X- and Y-polarization components of the optical PDM-QPSK baseband signal are simultaneously upconverted to 100 GHz wireless carrier by optical polarization-diversity heterodyne beating, and then independently transmitted and received by two pairs of transmitter and receiver antennas, which form a 2×2 multiple-input multiple-output wireless link. At the wireless receiver, two-stage downconversion is performed firstly in the analog domain based on balanced mixer and sinusoidal radio frequency signal, and then in the digital domain based on digital signal processing (DSP). Polarization demultiplexing is realized by the constant modulus algorithm in the DSP part at the receiver. The bit-error ratio for the 108  Gb/s PDM-QPSK signal is less than the pre-forward-error-correction threshold of 3.8×10(-3) after both 1 m wireless delivery at 100 GHz and 80 km single-mode fiber-28 transmission. To our knowledge, this is the first demonstration to realize 100  Gb/s signal delivery through both fiber and wireless links at 100 GHz.

Noncoherent parallel optical processor for discrete two-dimensional linear transformations.

PubMed

Glaser, I

1980-10-01

We describe a parallel optical processor, based on a lenslet array, that provides general linear two-dimensional transformations using noncoherent light. Such a processor could become useful in image- and signal-processing applications in which the throughput requirements cannot be adequately satisfied by state-of-the-art digital processors. Experimental results that illustrate the feasibility of the processor by demonstrating its use in parallel optical computation of the two-dimensional Walsh-Hadamard transformation are presented.

HIV Glycoprotein Gp120 Impairs Fast Axonal Transport by Activating Tak1 Signaling Pathways

PubMed Central

Berth, Sarah H.; Mesnard-Hoaglin, Nichole; Wang, Bin; Kim, Hajwa; Song, Yuyu; Sapar, Maria; Morfini, Gerardo

2016-01-01

Sensory neuropathies are the most common neurological complication of HIV. Of these, distal sensory polyneuropathy (DSP) is directly caused by HIV infection and characterized by length-dependent axonal degeneration of dorsal root ganglion (DRG) neurons. Mechanisms for axonal degeneration in DSP remain unclear, but recent experiments revealed that the HIV glycoprotein gp120 is internalized and localized within axons of DRG neurons. Based on these findings, we investigated whether intra-axonal gp120 might impair fast axonal transport (FAT), a cellular process critical for appropriate maintenance of the axonal compartment. Significantly, we found that gp120 severely impaired both anterograde and retrograde FAT. Providing a mechanistic basis for these effects, pharmacological experiments revealed an involvement of various phosphotransferases in this toxic effect, including members of mitogen-activated protein kinase pathways (Tak-1, p38, and c-Jun N-terminal Kinase (JNK)), inhibitor of kappa-B-kinase 2 (IKK2), and PP1. Biochemical experiments and axonal outgrowth assays in cell lines and primary cultures extended these findings. Impairments in neurite outgrowth in DRG neurons by gp120 were rescued using a Tak-1 inhibitor, implicating a Tak-1 mitogen-activated protein kinase pathway in gp120 neurotoxicity. Taken together, these observations indicate that kinase-based impairments in FAT represent a novel mechanism underlying gp120 neurotoxicity consistent with the dying-back degeneration seen in DSP. Targeting gp120-based impairments in FAT with specific kinase inhibitors might provide a novel therapeutic strategy to prevent axonal degeneration in DSP. PMID:27872270

A low power biomedical signal processor ASIC based on hardware software codesign.

PubMed

Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

2009-01-01

A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

The Magnitude Response Learning Tool for DSP Education: A Case Study

ERIC Educational Resources Information Center

Kulmer, Florian; Wurzer, Christian Gun; Geiger, Bernhard C.

2016-01-01

Many concepts in digital signal processing are intuitive, despite being mathematically challenging. The lecturer not only has to teach the complicated math but should also help students develop intuition about the concept. To aid the lecturer in this task, the Magnitude Response Learning Tool has been introduced, a computer-based learning game…

Fpga based L-band pulse doppler radar design and implementation

NASA Astrophysics Data System (ADS)

Savci, Kubilay

As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed point arithmetic operations as it is fast and facilitates source requirement as it consumes less hardware than floating point arithmetic operations. The software uses floating point arithmetic operations, which ensure precision in processing at the expense of speed. The functionality of the radar system has been tested for experimental validation in the field with a moving car and the validation of submodules are tested with synthetic data simulated on MATLAB.

Advanced digital signal processing for short haul optical fiber transmission beyond 100G

NASA Astrophysics Data System (ADS)

Kikuchi, Nobuhiko

2017-01-01

Significant increase of intra and inter data center traffic has been expected by the rapid spread of various network applications like SNS, IoT, mobile and cloud computing, and the needs for ultra-high speed and cost-effective short- to medium-reach optical fiber links beyond 100-Gbit/s is becoming larger and larger. Such high-speed links typically use multilevel modulation to lower signaling speed, which in turn face serious challenges in limited loss budget and waveform distortion tolerance. One of the promising techniques to overcome them is the use of advanced digital signal processing (DSP) and we review various DSP applications for short-to-medium reach applications.

Analysis and simulation tools for solar array power systems

NASA Astrophysics Data System (ADS)

Pongratananukul, Nattorn

This dissertation presents simulation tools developed specifically for the design of solar array power systems. Contributions are made in several aspects of the system design phases, including solar source modeling, system simulation, and controller verification. A tool to automate the study of solar array configurations using general purpose circuit simulators has been developed based on the modeling of individual solar cells. Hierarchical structure of solar cell elements, including semiconductor properties, allows simulation of electrical properties as well as the evaluation of the impact of environmental conditions. A second developed tool provides a co-simulation platform with the capability to verify the performance of an actual digital controller implemented in programmable hardware such as a DSP processor, while the entire solar array including the DC-DC power converter is modeled in software algorithms running on a computer. This "virtual plant" allows developing and debugging code for the digital controller, and also to improve the control algorithm. One important task in solar arrays is to track the maximum power point on the array in order to maximize the power that can be delivered. Digital controllers implemented with programmable processors are particularly attractive for this task because sophisticated tracking algorithms can be implemented and revised when needed to optimize their performance. The proposed co-simulation tools are thus very valuable in developing and optimizing the control algorithm, before the system is built. Examples that demonstrate the effectiveness of the proposed methodologies are presented. The proposed simulation tools are also valuable in the design of multi-channel arrays. In the specific system that we have designed and tested, the control algorithm is implemented on a single digital signal processor. In each of the channels the maximum power point is tracked individually. In the prototype we built, off-the-shelf commercial DC-DC converters were utilized. At the end, the overall performance of the entire system was evaluated using solar array simulators capable of simulating various I-V characteristics, and also by using an electronic load. Experimental results are presented.

Methodology for creating dedicated machine and algorithm on sunflower counting

NASA Astrophysics Data System (ADS)

Muracciole, Vincent; Plainchault, Patrick; Mannino, Maria-Rosaria; Bertrand, Dominique; Vigouroux, Bertrand

2007-09-01

In order to sell grain lots in European countries, seed industries need a government certification. This certification requests purity testing, seed counting in order to quantify specified seed species and other impurities in lots, and germination testing. These analyses are carried out within the framework of international trade according to the methods of the International Seed Testing Association. Presently these different analyses are still achieved manually by skilled operators. Previous works have already shown that seeds can be characterized by around 110 visual features (morphology, colour, texture), and thus have presented several identification algorithms. Until now, most of the works in this domain are computer based. The approach presented in this article is based on the design of dedicated electronic vision machine aimed to identify and sort seeds. This machine is composed of a FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor) and a PC bearing the GUI (Human Machine Interface) of the system. Its operation relies on the stroboscopic image acquisition of a seed falling in front of a camera. A first machine was designed according to this approach, in order to simulate all the vision chain (image acquisition, feature extraction, identification) under the Matlab environment. In order to perform this task into dedicated hardware, all these algorithms were developed without the use of the Matlab toolbox. The objective of this article is to present a design methodology for a special purpose identification algorithm based on distance between groups into dedicated hardware machine for seed counting.

Optimized design of embedded DSP system hardware supporting complex algorithms

NASA Astrophysics Data System (ADS)

Li, Yanhua; Wang, Xiangjun; Zhou, Xinling

2003-09-01

The paper presents an optimized design method for a flexible and economical embedded DSP system that can implement complex processing algorithms as biometric recognition, real-time image processing, etc. It consists of a floating-point DSP, 512 Kbytes data RAM, 1 Mbytes FLASH program memory, a CPLD for achieving flexible logic control of input channel and a RS-485 transceiver for local network communication. Because of employing a high performance-price ratio DSP TMS320C6712 and a large FLASH in the design, this system permits loading and performing complex algorithms with little algorithm optimization and code reduction. The CPLD provides flexible logic control for the whole DSP board, especially in input channel, and allows convenient interface between different sensors and DSP system. The transceiver circuit can transfer data between DSP and host computer. In the paper, some key technologies are also introduced which make the whole system work efficiently. Because of the characters referred above, the hardware is a perfect flat for multi-channel data collection, image processing, and other signal processing with high performance and adaptability. The application section of this paper presents how this hardware is adapted for the biometric identification system with high identification precision. The result reveals that this hardware is easy to interface with a CMOS imager and is capable of carrying out complex biometric identification algorithms, which require real-time process.

Real-time phase correlation based integrated system for seizure detection

NASA Astrophysics Data System (ADS)

Romaine, James B.; Delgado-Restituto, Manuel; Leñero-Bardallo, Juan A.; Rodríguez-Vázquez, Ángel

2017-05-01

This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.

An accuracy aware low power wireless EEG unit with information content based adaptive data compression.

PubMed

Tolbert, Jeremy R; Kabali, Pratik; Brar, Simeranjit; Mukhopadhyay, Saibal

2009-01-01

We present a digital system for adaptive data compression for low power wireless transmission of Electroencephalography (EEG) data. The proposed system acts as a base-band processor between the EEG analog-to-digital front-end and RF transceiver. It performs a real-time accuracy energy trade-off for multi-channel EEG signal transmission by controlling the volume of transmitted data. We propose a multi-core digital signal processor for on-chip processing of EEG signals, to detect signal information of each channel and perform real-time adaptive compression. Our analysis shows that the proposed approach can provide significant savings in transmitter power with minimal impact on the overall signal accuracy.

SVM-based multisensor data fusion for phase concentration measurement in biomass-coal co-combustion

NASA Astrophysics Data System (ADS)

Wang, Xiaoxin; Hu, Hongli; Jia, Huiqin; Tang, Kaihao

2018-05-01

In this paper, the electrical method combines the electrostatic sensor and capacitance sensor to measure the phase concentration of pulverized coal/biomass/air three-phase flow through data fusion technology. In order to eliminate the effects of flow regimes and improve the accuracy of the phase concentration measurement, the mel frequency cepstrum coefficient features extracted from electrostatic signals are used to train the Continuous Gaussian Mixture Hidden Markov Model (CGHMM) for flow regime identification. Support Vector Machine (SVM) is introduced to establish the concentration information fusion model under identified flow regimes. The CGHMM models and SVM models are transplanted on digital signal processing (DSP) to realize on-line accurate measurement. The DSP flow regime identification time is 1.4 ms, and the concentration predict time is 164 μs, which can fully meet the real-time requirement. The average absolute value of the relative error of the pulverized coal is about 1.5% and that of the biomass is about 2.2%.

Progress in video immersion using Panospheric imaging

NASA Astrophysics Data System (ADS)

Bogner, Stephen L.; Southwell, David T.; Penzes, Steven G.; Brosinsky, Chris A.; Anderson, Ron; Hanna, Doug M.

1998-09-01

Having demonstrated significant technical and marketplace advantages over other modalities for video immersion, PanosphericTM Imaging (PI) continues to evolve rapidly. This paper reports on progress achieved since AeroSense 97. The first practical field deployment of the technology occurred in June-August 1997 during the NASA-CMU 'Atacama Desert Trek' activity, where the Nomad mobile robot was teleoperated via immersive PanosphericTM imagery from a distance of several thousand kilometers. Research using teleoperated vehicles at DRES has also verified the exceptional utility of the PI technology for achieving high levels of situational awareness, operator confidence, and mission effectiveness. Important performance enhancements have been achieved with the completion of the 4th Generation PI DSP-based array processor system. The system is now able to provide dynamic full video-rate generation of spatial and computational transformations, resulting in a programmable and fully interactive immersive video telepresence. A new multi- CCD camera architecture has been created to exploit the bandwidth of this processor, yielding a well-matched PI system with greatly improved resolution. While the initial commercial application for this technology is expected to be video tele- conferencing, it also appears to have excellent potential for application in the 'Immersive Cockpit' concept. Additional progress is reported in the areas of Long Wave Infrared PI Imaging, Stereo PI concepts, PI based Video-Servoing concepts, PI based Video Navigation concepts, and Foveation concepts (to merge localized high-resolution views with immersive views).

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G.; Salapura, Valentina

2012-07-24

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Homology-based modeling of the Erwinia amylovora type III secretion chaperone DspF used to identify amino acids required for virulence and interaction with the effector DspE.

PubMed

Triplett, Lindsay R; Wedemeyer, William J; Sundin, George W

2010-09-01

The structure of DspF, a type III secretion system (T3SS) chaperone required for virulence of the fruit tree pathogen Erwinia amylovora, was modeled based on predicted structural homology to characterized T3SS chaperones. This model guided the selection of 11 amino acid residues that were individually mutated to alanine via site-directed mutagenesis. Each mutant was assessed for its effect on virulence complementation, dimerization and interaction with the N-terminal chaperone-binding site of DspE. Four amino acid residues were identified that did not complement the virulence defect of a dspF knockout mutant, and three of these residues were required for interaction with the N-terminus of DspE. This study supports the significance of the predicted beta-sheet helix-binding groove in DspF chaperone function. Copyright 2010 Elsevier Masson SAS. All rights reserved.

Development of a material processing plant for lunar soil

NASA Technical Reports Server (NTRS)

Goettsch, Ulix; Ousterhout, Karl

1992-01-01

Currently there is considerable interest in developing in-situ materials processing plants for both the Moon and Mars. Two of the most important aspects of developing such a materials processing plant is the overall system design and the integration of the different technologies into a reliable, lightweight, and cost-effective unit. The concept of an autonomous materials processing plant that is capable of producing useful substances from lunar regolith was developed. In order for such a materials processing plant to be considered as a viable option, it must be totally self-contained, able to operate autonomously, cost effective, light weight, and fault tolerant. In order to assess the impact of different technologies on the overall systems design and integration, a one-half scale model was constructed that is capable of scooping up (or digging) lunar soil, transferring the soil to a solar furnace, heating the soil in the furnace to liberate the gasses, and transferring the spent soil to a 'tile' processing center. All aspects of the control system are handled by a 386 class PC via D/A, A/D, and DSP (Digital Signal Processor) control cards.

Model predictive controller design for boost DC-DC converter using T-S fuzzy cost function

NASA Astrophysics Data System (ADS)

Seo, Sang-Wha; Kim, Yong; Choi, Han Ho

2017-11-01

This paper proposes a Takagi-Sugeno (T-S) fuzzy method to select cost function weights of finite control set model predictive DC-DC converter control algorithms. The proposed method updates the cost function weights at every sample time by using T-S type fuzzy rules derived from the common optimal control engineering knowledge that a state or input variable with an excessively large magnitude can be penalised by increasing the weight corresponding to the variable. The best control input is determined via the online optimisation of the T-S fuzzy cost function for all the possible control input sequences. This paper implements the proposed model predictive control algorithm in real time on a Texas Instruments TMS320F28335 floating-point Digital Signal Processor (DSP). Some experimental results are given to illuminate the practicality and effectiveness of the proposed control system under several operating conditions. The results verify that our method can yield not only good transient and steady-state responses (fast recovery time, small overshoot, zero steady-state error, etc.) but also insensitiveness to abrupt load or input voltage parameter variations.

Architecture, Design and Implementation of RC64, a Many-Core High-Performance DSP for Space Applications

NASA Astrophysics Data System (ADS)

Ginosar, Ran; Aviely, Peleg; Liran, Tuvia; Alon, Dov; Dobkin, Reuven; Goldberg, Michael

2013-08-01

RC64, a novel 64-core many-core signal processing chip targets DSP performance of 12.8 GIPS, 100 GOPS and 12.8 single precision GFLOS while dissipating only 3 Watts. RC64 employs advanced DSP cores, a multi-bank shared memory and a hardware scheduler, supports DDR2 memory and communicates over five proprietary 6.4 Gbps channels. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 200 MHz ASIC on Tower 130nm CMOS technology, assembled in hermetically sealed ceramic QFP package and qualified to the highest space standards.

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, W.K.; Hubbard, B.

1997-11-04

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a ``hardwired`` processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer. 19 figs.

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Hubbard, Bradley

1997-01-01

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a "hardwired" processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer.

Automatic generation of Web mining environments

NASA Astrophysics Data System (ADS)

Cibelli, Maurizio; Costagliola, Gennaro

1999-02-01

The main problem related to the retrieval of information from the world wide web is the enormous number of unstructured documents and resources, i.e., the difficulty of locating and tracking appropriate sources. This paper presents a web mining environment (WME), which is capable of finding, extracting and structuring information related to a particular domain from web documents, using general purpose indices. The WME architecture includes a web engine filter (WEF), to sort and reduce the answer set returned by a web engine, a data source pre-processor (DSP), which processes html layout cues in order to collect and qualify page segments, and a heuristic-based information extraction system (HIES), to finally retrieve the required data. Furthermore, we present a web mining environment generator, WMEG, that allows naive users to generate a WME specific to a given domain by providing a set of specifications.

Low-cost detection of RC-IED activation signals in VHF band

NASA Astrophysics Data System (ADS)

Camargo Suarez, Victor Hugo; Marulanda B., Jose Ignacio

2014-05-01

The proliferation of Radio Controlled Improvised Explosive Devices (RC-IED) is a growing threat around the world. The ease of construction and low cost of these devices are transforming common things in lethal tramps. The fight against this threats normally involves the use of sophisticated and expensive equipment of Electronic Warfare based on high speed DSP systems, just to detect the presence of detonation signals. In this work is showed how to find activation signals based on the characteristic of the power in a specific band and the previous knowledge about the detonation signals. As proof of concept we have taken the information about the RC-IEDs used in the Colombian conflict and develop an algorithm to find detonation signals based on the measured power in frequencies between 136 MHz and 174 MHz (2 meter civil band)

Real-time experimental demonstrations of software reconfigurable optical OFDM transceivers utilizing DSP-based digital orthogonal filters for SDN PONs.

PubMed

Duan, X; Giddings, R P; Bolea, M; Ling, Y; Cao, B; Mansoor, S; Tang, J M

2014-08-11

Real-time optical OFDM (OOFDM) transceivers with on-line software-controllable channel reconfigurability and transmission performance adaptability are experimentally demonstrated, for the first time, utilizing Hilbert-pair-based 32-tap digital orthogonal filters implemented in FPGAs. By making use of an 8-bit DAC/ADC operating at 2GS/s, an oversampling factor of 2 and an EML intensity modulator, the demonstrated RF conversion-free transceiver supports end-to-end real-time simultaneous adaptive transmissions, within a 1GHz signal spectrum region, of a 2.03Gb/s in-phase OOFDM channel and a 1.41Gb/s quadrature-phase OOFDM channel over a 25km SSMF IMDD system. In addition, detailed experimental explorations are also undertaken of key physical mechanisms limiting the maximum achievable transmission performance, impacts of transceiver's channel multiplexing/demultiplexing operations on the system BER performance, and the feasibility of utilizing adaptive modulation to combat impairments associated with low-complexity digital filter designs. Furthermore, experimental results indicate that the transceiver incorporating a fixed digital orthogonal filter DSP architecture can be made transparent to various signal modulation formats up to 64-QAM.

Virtual and flexible digital signal processing system based on software PnP and component works

NASA Astrophysics Data System (ADS)

He, Tao; Wu, Qinghua; Zhong, Fei; Li, Wei

2005-05-01

An idea about software PnP (Plug & Play) is put forward according to the hardware PnP. And base on this idea, a virtual flexible digital signal processing system (FVDSPS) is carried out. FVDSPS is composed of a main control center, many sub-function modules and other hardware I/O modules. Main control center sends out commands to sub-function modules, and manages running orders, parameters and results of sub-functions. The software kernel of FVDSPS is DSP (Digital Signal Processing) module, which communicates with the main control center through some protocols, accept commands or send requirements. The data sharing and exchanging between the main control center and the DSP modules are carried out and managed by the files system of the Windows Operation System through the effective communication. FVDSPS real orients objects, orients engineers and orients engineering problems. With FVDSPS, users can freely plug and play, and fast reconfigure a signal process system according to engineering problems without programming. What you see is what you get. Thus, an engineer can orient engineering problems directly, pay more attention to engineering problems, and promote the flexibility, reliability and veracity of testing system. Because FVDSPS orients TCP/IP protocol, through Internet, testing engineers, technology experts can be connected freely without space. Engineering problems can be resolved fast and effectively. FVDSPS can be used in many fields such as instruments and meter, fault diagnosis, device maintenance and quality control.

Integrated Advanced Microwave Sounding Unit-A(AMSU-A). Engineering Test Report: METSAT A1 Signal Processor, (P/N 1331670-2, S /N F05)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the AI METSAT Signal Processor Assembly P/N 1331670-2, S/N F05. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N 1331670-2, S/N F03)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F03. This assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Design and testing of a 750MHz CW-EPR digital console for small animal imaging.

PubMed

Sato-Akaba, Hideo; Emoto, Miho C; Hirata, Hiroshi; Fujii, Hirotada G

2017-11-01

This paper describes the development of a digital console for three-dimensional (3D) continuous wave electron paramagnetic resonance (CW-EPR) imaging of a small animal to improve the signal-to-noise ratio and lower the cost of the EPR imaging system. A RF generation board, an RF acquisition board and a digital signal processing (DSP) & control board were built for the digital EPR detection. Direct sampling of the reflected RF signal from a resonator (approximately 750MHz), which contains the EPR signal, was carried out using a band-pass subsampling method. A direct automatic control system to reduce the reflection from the resonator was proposed and implemented in the digital EPR detection scheme. All DSP tasks were carried out in field programmable gate array ICs. In vivo 3D imaging of nitroxyl radicals in a mouse's head was successfully performed. Copyright © 2017 Elsevier Inc. All rights reserved.

Design and testing of a 750 MHz CW-EPR digital console for small animal imaging

NASA Astrophysics Data System (ADS)

Sato-Akaba, Hideo; Emoto, Miho C.; Hirata, Hiroshi; Fujii, Hirotada G.

2017-11-01

This paper describes the development of a digital console for three-dimensional (3D) continuous wave electron paramagnetic resonance (CW-EPR) imaging of a small animal to improve the signal-to-noise ratio and lower the cost of the EPR imaging system. A RF generation board, an RF acquisition board and a digital signal processing (DSP) & control board were built for the digital EPR detection. Direct sampling of the reflected RF signal from a resonator (approximately 750 MHz), which contains the EPR signal, was carried out using a band-pass subsampling method. A direct automatic control system to reduce the reflection from the resonator was proposed and implemented in the digital EPR detection scheme. All DSP tasks were carried out in field programmable gate array ICs. In vivo 3D imaging of nitroxyl radicals in a mouse's head was successfully performed.

Compact VLSI neural computer integrated with active pixel sensor for real-time ATR applications

NASA Astrophysics Data System (ADS)

Fang, Wai-Chi; Udomkesmalee, Gabriel; Alkalai, Leon

1997-04-01

A compact VLSI neural computer integrated with an active pixel sensor has been under development to mimic what is inherent in biological vision systems. This electronic eye- brain computer is targeted for real-time machine vision applications which require both high-bandwidth communication and high-performance computing for data sensing, synergy of multiple types of sensory information, feature extraction, target detection, target recognition, and control functions. The neural computer is based on a composite structure which combines Annealing Cellular Neural Network (ACNN) and Hierarchical Self-Organization Neural Network (HSONN). The ACNN architecture is a programmable and scalable multi- dimensional array of annealing neurons which are locally connected with their local neurons. Meanwhile, the HSONN adopts a hierarchical structure with nonlinear basis functions. The ACNN+HSONN neural computer is effectively designed to perform programmable functions for machine vision processing in all levels with its embedded host processor. It provides a two order-of-magnitude increase in computation power over the state-of-the-art microcomputer and DSP microelectronics. A compact current-mode VLSI design feasibility of the ACNN+HSONN neural computer is demonstrated by a 3D 16X8X9-cube neural processor chip design in a 2-micrometers CMOS technology. Integration of this neural computer as one slice of a 4'X4' multichip module into the 3D MCM based avionics architecture for NASA's New Millennium Program is also described.

Design and initial validation of a wireless control system based on WSN

NASA Astrophysics Data System (ADS)

Yu, Yan; Li, Luyu; Li, Peng; Wang, Xu; Liu, Hang; Ou, Jinping

2013-04-01

At present, cantilever structure used widely in civil structures will generate continuous vibration by external force due to their low damping characteristic, which leads to a serious impact on the working performance and service time. Therefore, it is very important to control the vibration of these structures. The active vibration control is the primary means of controlling the vibration with high precision and strong adaptive ability. Nowadays, there are many researches using piezoelectric materials in the structural vibration control. Piezoelectric materials are cheap, reliable and they can provide braking and sensing method harmless to the structure, therefore they have broad usage. They are used for structural vibration control in a lot of civil engineering research currently. In traditional sensor applications, information exchanges with the monitoring center or a computer system through wires. If wireless sensor networks(WSN) technology is used, cabling links is not needed, thus the cost of the whole system is greatly reduced. Based on the above advantages, a wireless control system is designed and validated through preliminary tests. The system consists of a cantilever, PVDF as sensor, signal conditioning circuit(SCM), A/D acquisition board, control arithmetic unit, D/A output board, power amplifier, piezoelectric bimorph as actuator. DSP chip is used as the control arithmetic unit and PD control algorithm is embedded in it. PVDF collects the parameters of vibration, sends them to the SCM after A/D conversion. SCM passes the data to the DSP through wireless technology, and DSP calculates and outputs the control values according to the control algorithm. The output signal is amplified by the power amplifier to drive the piezoelectric bimorph for vibration control. The structural vibration duration reduces to 1/4 of the uncontrolled case, which verifies the feasibility of the system.

Shuttle orbiter S-band payload communications equipment design evaluation

NASA Technical Reports Server (NTRS)

Springett, J. C.; Maronde, R. G.

1979-01-01

The analysis of the design, and the performance assessment of the Orbiter S-band communication equipment are reported. The equipment considered include: network transponder, network signal processor, FM transmitter, FM signal processor, payload interrogator, and payload signal processor.

Compact ion chamber based neutron detector

DOEpatents

Derzon, Mark S.; Galambos, Paul C.; Renzi, Ronald F.

2015-10-27

A directional neutron detector has an ion chamber formed in a dielectric material; a signal electrode and a ground electrode formed in the ion chamber; a neutron absorbing material filling the ion chamber; readout circuitry which is electrically coupled to the signal and ground electrodes; and a signal processor electrically coupled to the readout circuitry. The ion chamber has a pair of substantially planar electrode surfaces. The chamber pressure of the neutron absorbing material is selected such that the reaction particle ion trail length for neutrons absorbed by the neutron absorbing material is equal to or less than the distance between the electrode surfaces. The signal processor is adapted to determine a path angle for each absorbed neutron based on the rise time of the corresponding pulse in a time-varying detector signal.

Real Time Phase Noise Meter Based on a Digital Signal Processor

NASA Technical Reports Server (NTRS)

Angrisani, Leopoldo; D'Arco, Mauro; Greenhall, Charles A.; Schiano Lo Morille, Rosario

2006-01-01

A digital signal-processing meter for phase noise measurement on sinusoidal signals is dealt with. It enlists a special hardware architecture, made up of a core digital signal processor connected to a data acquisition board, and takes advantage of a quadrature demodulation-based measurement scheme, already proposed by the authors. Thanks to an efficient measurement process and an optimized implementation of its fundamental stages, the proposed meter succeeds in exploiting all hardware resources in such an effective way as to gain high performance and real-time operation. For input frequencies up to some hundreds of kilohertz, the meter is capable both of updating phase noise power spectrum while seamlessly capturing the analyzed signal into its memory, and granting as good frequency resolution as few units of hertz.

RC64, a Rad-Hard Many-Core High- Performance DSP for Space Applications

NASA Astrophysics Data System (ADS)

Ginosar, Ran; Aviely, Peleg; Gellis, Hagay; Liran, Tuvia; Israeli, Tsvika; Nesher, Roy; Lange, Fredy; Dobkin, Reuven; Meirov, Henri; Reznik, Dror

2015-09-01

RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

RC64, a Rad-Hard Many-Core High-Performance DSP for Space Applications

NASA Astrophysics Data System (ADS)

Ginosar, Ran; Aviely, Peleg; Liran, Tuvia; Alon, Dov; Mandler, Alberto; Lange, Fredy; Dobkin, Reuven; Goldberg, Miki

2014-08-01

RC64, a novel rad-hard 64-core signal processing chip targets DSP performance of 75 GMACs (16bit), 150 GOPS and 20 single precision GFLOPS while dissipating less than 10 Watts. RC64 integrates advanced DSP cores with a multi-bank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 2.5 Gbps full duplex high speed serial links using SpaceFibre and other protocols. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 300 MHz integrated circuit on a 65nm CMOS technology, assembled in hermetically sealed ceramic CCGA624 package and qualified to the highest space standards.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N: 1331670-2, S/N: F04)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Multimedia systems in ultrasound image boundary detection and measurements

NASA Astrophysics Data System (ADS)

Pathak, Sayan D.; Chalana, Vikram; Kim, Yongmin

1997-05-01

Ultrasound as a medical imaging modality offers the clinician a real-time of the anatomy of the internal organs/tissues, their movement, and flow noninvasively. One of the applications of ultrasound is to monitor fetal growth by measuring biparietal diameter (BPD) and head circumference (HC). We have been working on automatic detection of fetal head boundaries in ultrasound images. These detected boundaries are used to measure BPD and HC. The boundary detection algorithm is based on active contour models and takes 32 seconds on an external high-end workstation, SUN SparcStation 20/71. Our goal has been to make this tool available within an ultrasound machine and at the same time significantly improve its performance utilizing multimedia technology. With the advent of high- performance programmable digital signal processors (DSP), the software solution within an ultrasound machine instead of the traditional hardwired approach or requiring an external computer is now possible. We have integrated our boundary detection algorithm into a programmable ultrasound image processor (PUIP) that fits into a commercial ultrasound machine. The PUIP provides both the high computing power and flexibility needed to support computationally-intensive image processing algorithms within an ultrasound machine. According to our data analysis, BPD/HC measurements made on PUIP lie within the interobserver variability. Hence, the errors in the automated BPD/HC measurements using the algorithm are on the same order as the average interobserver differences. On PUIP, it takes 360 ms to measure the values of BPD/HC on one head image. When processing multiple head images in sequence, it takes 185 ms per image, thus enabling 5.4 BPD/HC measurements per second. Reduction in the overall execution time from 32 seconds to a fraction of a second and making this multimedia system available within an ultrasound machine will help this image processing algorithm and other computer-intensive imaging applications become a practical tool for the sonographers in the feature.

Implantable electronics: emerging design issues and an ultra light-weight security solution.

PubMed

Narasimhan, Seetharam; Wang, Xinmu; Bhunia, Swarup

2010-01-01

Implantable systems that monitor biological signals require increasingly complex digital signal processing (DSP) electronics for real-time in-situ analysis and compression of the recorded signals. While it is well-known that such signal processing hardware needs to be implemented under tight area and power constraints, new design requirements emerge with their increasing complexity. Use of nanoscale technology shows tremendous benefits in implementing these advanced circuits due to dramatic improvement in integration density and power dissipation per operation. However, it also brings in new challenges such as reliability and large idle power (due to higher leakage current). Besides, programmability of the device as well as security of the recorded information are rapidly becoming major design considerations of such systems. In this paper, we analyze the emerging issues associated with the design of the DSP unit in an implantable system. Next, we propose a novel ultra light-weight solution to address the information security issue. Unlike the conventional information security approaches like data encryption, which come at large area and power overhead and hence are not amenable for resource-constrained implantable systems, we propose a multilevel key-based scrambling algorithm, which exploits the nature of the biological signal to effectively obfuscate it. Analysis of the proposed algorithm in the context of neural signal processing and its hardware implementation shows that we can achieve high level of security with ∼ 13X lower power and ∼ 5X lower area overhead than conventional cryptographic solutions.

Advances in optical information processing IV; Proceedings of the Meeting, Orlando, FL, Apr. 18-20, 1990

NASA Astrophysics Data System (ADS)

Pape, Dennis R.

1990-09-01

The present conference discusses topics in optical image processing, optical signal processing, acoustooptic spectrum analyzer systems and components, and optical computing. Attention is given to tradeoffs in nonlinearly recorded matched filters, miniature spatial light modulators, detection and classification using higher-order statistics of optical matched filters, rapid traversal of an image data base using binary synthetic discriminant filters, wideband signal processing for emitter location, an acoustooptic processor for autonomous SAR guidance, and sampling of Fresnel transforms. Also discussed are an acoustooptic RF signal-acquisition system, scanning acoustooptic spectrum analyzers, the effects of aberrations on acoustooptic systems, fast optical digital arithmetic processors, information utilization in analog and digital processing, optical processors for smart structures, and a self-organizing neural network for unsupervised learning.

An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems

NASA Astrophysics Data System (ADS)

Gunay, Omer; Ozsarac, Ismail; Kamisli, Fatih

2017-05-01

Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA's lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.

Frequency domain laser velocimeter signal processor: A new signal processing scheme

NASA Technical Reports Server (NTRS)

Meyers, James F.; Clemmons, James I., Jr.

1987-01-01

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a smart instrument that is able to configure itself, based on the characteristics of the input signals, for optimum measurement accuracy. The signal processor is composed of a high-speed 2-bit transient recorder for signal capture and a combination of adaptive digital filters with energy and/or zero crossing detection signal processing. The system is designed to accept signals with frequencies up to 100 MHz with standard deviations up to 20 percent of the average signal frequency. Results from comparative simulation studies indicate measurement accuracies 2.5 times better than with a high-speed burst counter, from signals with as few as 150 photons per burst.

Efficient nonlinear equalizer for intra-channel nonlinearity compensation for next generation agile and dynamically reconfigurable optical networks.

PubMed

Malekiha, Mahdi; Tselniker, Igor; Plant, David V

2016-02-22

In this work, we propose and experimentally demonstrate a novel low-complexity technique for fiber nonlinearity compensation. We achieved a transmission distance of 2818 km for a 32-GBaud dual-polarization 16QAM signal. For efficient implantation, and to facilitate integration with conventional digital signal processing (DSP) approaches, we independently compensate fiber nonlinearities after linear impairment equalization. Therefore this algorithm can be easily implemented in currently deployed transmission systems after using linear DSP. The proposed equalizer operates at one sample per symbol and requires only one computation step. The structure of the algorithm is based on a first-order perturbation model with quantized perturbation coefficients. Also, it does not require any prior calculation or detailed knowledge of the transmission system. We identified common symmetries between perturbation coefficients to avoid duplicate and unnecessary operations. In addition, we use only a few adaptive filter coefficients by grouping multiple nonlinear terms and dedicating only one adaptive nonlinear filter coefficient to each group. Finally, the complexity of the proposed algorithm is lower than previously studied nonlinear equalizers by more than one order of magnitude.

Representation of DNA sequences in genetic codon context with applications in exon and intron prediction.

PubMed

Yin, Changchuan

2015-04-01

To apply digital signal processing (DSP) methods to analyze DNA sequences, the sequences first must be specially mapped into numerical sequences. Thus, effective numerical mappings of DNA sequences play key roles in the effectiveness of DSP-based methods such as exon prediction. Despite numerous mappings of symbolic DNA sequences to numerical series, the existing mapping methods do not include the genetic coding features of DNA sequences. We present a novel numerical representation of DNA sequences using genetic codon context (GCC) in which the numerical values are optimized by simulation annealing to maximize the 3-periodicity signal to noise ratio (SNR). The optimized GCC representation is then applied in exon and intron prediction by Short-Time Fourier Transform (STFT) approach. The results show the GCC method enhances the SNR values of exon sequences and thus increases the accuracy of predicting protein coding regions in genomes compared with the commonly used 4D binary representation. In addition, this study offers a novel way to reveal specific features of DNA sequences by optimizing numerical mappings of symbolic DNA sequences.

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

NASA Astrophysics Data System (ADS)

Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

1995-02-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

The AD and ELENA orbit, trajectory and intensity measurement systems

NASA Astrophysics Data System (ADS)

Marco-Hernández, R.; Alves, D.; Angoletta, M. E.; Marqversen, O.; Molendijk, J.; Oponowicz, E.; Ruffieux, R.; Sánchez-Quesada, J.; SØby, L.

2017-07-01

This paper describes the new Antiproton Decelerator (AD) orbit measurement system and the Extra Low ENergy Antiproton ring (ELENA) orbit, trajectory and intensity measurement system. The AD machine at European Organization for Nuclear Research (CERN) is presently being used to decelerate antiprotons from 3.57 GeV/c to 100 MeV/c for matter vs anti-matter comparative studies. The ELENA machine, presently under commissioning, has been designed to provide an extra deceleration stage down to 13.7 MeV/c. The AD orbit system is based on 32 horizontal and 27 vertical electrostatic Beam Position Monitor (BPM) fitted with existing low noise front-end amplifiers while the ELENA system consists of 24 \\gls{BPM}s equipped with new low-noise head amplifiers. In both systems the front-end amplifiers generate a difference (delta) and a sum (sigma) signal which are sent to the digital acquisition system, placed tens of meters away from the AD or ELENA rings, where they are digitized and further processed. The beam position is calculated by dividing the difference signal by the sum signal either using directly the raw digitized data for measuring the turn-by-turn trajectory in the ELENA system or after down-mixing the signals to baseband for the orbit measurement in both machines. The digitized sigma signal will be used in the ELENA system to calculate the bunched beam intensity and the Schottky parameters with coasting beam after passing through different signal processing chain. The digital acquisition arrangement for both systems is based on the same hardware, also used in the ELENA Low Level Radio Frequency (LLRF) system, which follows the VME Switched Serial (VXS) enhancement of the Versa Module Eurocard 64x extension (VME64x) standard and includes VITA 57 standard Field Programmable Gate Array Mezzanine Card (FMC). The digital acquisition Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) firmware shares many common functionalities with the LLRF system but has been tailored for this measurement application in particular. Specific control and acquisition software has been developed for these systems. Both systems are installed in AD and ELENA. The AD orbit system currently measures the orbit in AD while the ELENA system is being used in the commissioning of the ELENA ring.

Development of an 8000 bps voice codec for AvSat

NASA Technical Reports Server (NTRS)

Clark, Joseph F.

1988-01-01

Air-mobile speech communication applications share robustness and noise immunity requirements with other mobile applications. The quality requirements are stringent, especially in the cockpit where air safety is involved. Based on these considerations, a decision was made to test an intermediate data rate such as 8.0 and 9.6 kb/s as proven technologies. A number of vocoders and codec technologies were investigated at rates ranging from 2.4 kb/s up to and including 9.6 kb/s. The proven vocoders operating at 2.4 and 4.8 kb/s lacked the noise immunity or the robustness to operate reliably in a cabin noise environment. One very attractive alternative approach was Spectrally Encoded Residual Excited LPC (SE-RELP) which is used in a multi-rate voice processor (MRP) developed at the Naval Research Lab (NRL). The MRP uses SE-RELP at rates of 9.6 and 16 kb/s. The 9.6 kb/s rate can be lowered to 8.0 kb/s without loss of information by modifying the frame. An 8.0 kb/s vocoder was developed using SE-RELP as a demonstrator and testbed. This demonstrator is implemented in real time using two Compaq 2 portable computers, each equipped with an ARIEL DSP016 Data Acquisition Processor.

Electronic working length determination in primary teeth by ProPex and Digital Signal Processing.

PubMed

Nelson-Filho, Paulo; Lucisano, Marcela Pacífico; Leonardo, Mário Roberto; da Silva, Raquel Assed Bezerra; da Silva, Léa Assed Bezerra

2010-12-01

The purpose of this study was to evaluate the accuracy of electronic apex locators Digital Signal Processing (DSP) and ProPex, for root canal length determination in primary teeth. Fifteen primary molars (a total of 34 root canals) were divided into two groups: Group I - without physiological resorption (n = 16); and Group II - with physiological resorption (n = 18). The length of each canal was measured by introducing a file until its tip was visible and then it was retracted 1 mm. For electronic measurement, the devices were set to 1 mm short of the apical resorption. The data were analysed statistically using the intraclass correlation coefficient (ICC). Results showed that the ICC was high for both electronic apex locators in all situations - with (ICC: DSP = 0.82 and Propex = 0.89) or without resorption (ICC: DSP = 0.92 and Propex = 0.90). Both apex locators were extremely accurate in determining the working length in primary teeth, both with or without physiological resorption. © 2010 The Authors. Australian Endodontic Journal © 2010 Australian Society of Endodontology.

Multipath interference test method using synthesized chirped signal from directly modulated DFB-LD with digital-signal-processing technique.

PubMed

Aida, Kazuo; Sugie, Toshihiko

2011-12-12

We propose a method of testing transmission fiber lines and distributed amplifiers. Multipath interference (MPI) is detected as a beat spectrum between a multipath signal and a direct signal using a synthesized chirped test signal with lightwave frequencies of f(1) and f(2) periodically emitted from a distributed feedback laser diode (DFB-LD). This chirped test pulse is generated using a directly modulated DFB-LD with a drive signal calculated using a digital signal processing technique (DSP). A receiver consisting of a photodiode and an electrical spectrum analyzer (ESA) detects a baseband power spectrum peak appearing at the frequency of the test signal frequency deviation (f(1)-f(2)) as a beat spectrum of self-heterodyne detection. Multipath interference is converted from the spectrum peak power. This method improved the minimum detectable MPI to as low as -78 dB. We discuss the detailed design and performance of the proposed test method, including a DFB-LD drive signal calculation algorithm with DSP for synthesis of the chirped test signal and experiments on single-mode fibers with discrete reflections. © 2011 Optical Society of America

Real-time Enhancement, Registration, and Fusion for a Multi-Sensor Enhanced Vision System

NASA Technical Reports Server (NTRS)

Hines, Glenn D.; Rahman, Zia-ur; Jobson, Daniel J.; Woodell, Glenn A.

2006-01-01

Over the last few years NASA Langley Research Center (LaRC) has been developing an Enhanced Vision System (EVS) to aid pilots while flying in poor visibility conditions. The EVS captures imagery using two infrared video cameras. The cameras are placed in an enclosure that is mounted and flown forward-looking underneath the NASA LaRC ARIES 757 aircraft. The data streams from the cameras are processed in real-time and displayed on monitors on-board the aircraft. With proper processing the camera system can provide better-than- human-observed imagery particularly during poor visibility conditions. However, to obtain this goal requires several different stages of processing including enhancement, registration, and fusion, and specialized processing hardware for real-time performance. We are using a real-time implementation of the Retinex algorithm for image enhancement, affine transformations for registration, and weighted sums to perform fusion. All of the algorithms are executed on a single TI DM642 digital signal processor (DSP) clocked at 720 MHz. The image processing components were added to the EVS system, tested, and demonstrated during flight tests in August and September of 2005. In this paper we briefly discuss the EVS image processing hardware and algorithms. We then discuss implementation issues and show examples of the results obtained during flight tests. Keywords: enhanced vision system, image enhancement, retinex, digital signal processing, sensor fusion

Passive fetal heart rate monitoring apparatus and method with enhanced fetal heart beat discrimination

NASA Technical Reports Server (NTRS)

Zahorian, Stephen A. (Inventor); Livingston, David L. (Inventor); Pretlow, III, Robert A. (Inventor)

1996-01-01

An apparatus for acquiring signals emitted by a fetus, identifying fetal heart beats and determining a fetal heart rate. Multiple sensor signals are outputted by a passive fetal heart rate monitoring sensor. Multiple parallel nonlinear filters filter these multiple sensor signals to identify fetal heart beats in the signal data. A processor determines a fetal heart rate based on these identified fetal heart beats. The processor includes the use of a figure of merit weighting of heart rate estimates based on the identified heart beats from each filter for each signal. The fetal heart rate thus determined is outputted to a display, storage, or communications channel. A method for enhanced fetal heart beat discrimination includes acquiring signals from a fetus, identifying fetal heart beats from the signals by multiple parallel nonlinear filtering, and determining a fetal heart rate based on the identified fetal heart beats. A figure of merit operation in this method provides for weighting a plurality of fetal heart rate estimates based on the identified fetal heart beats and selecting the highest ranking fetal heart rate estimate.

Passive fetal heart rate monitoring apparatus and method with enhanced fetal heart beat discrimination

NASA Technical Reports Server (NTRS)

Zahorian, Stephen A. (Inventor); Livingston, David L. (Inventor); Pretlow, Robert A., III (Inventor)

1994-01-01

An apparatus for acquiring signals emitted by a fetus, identifying fetal heart beats and determining a fetal heart rate is presented. Multiple sensor signals are outputted by a passive fetal heart rate monitoring sensor. Multiple parallel nonlinear filters filter these multiple sensor signals to identify fetal heart beats in the signal data. A processor determines a fetal heart rate based on these identified fetal heart beats. The processor includes the use of a figure of merit weighting of heart rate estimates based on the identified heart beats from each filter for each signal. The fetal heart rate thus determined is outputted to a display, storage, or communications channel. A method for enhanced fetal heart beat discrimination includes acquiring signals from a fetus, identifying fetal heart beats from the signals by multiple parallel nonlinear filtering, and determining a fetal heart rate based on the identified fetal heart beats. A figure of merit operation in this method provides for weighting a plurality of fetal heart rate estimates based on the identified fetal heart beats and selecting the highest ranking fetal heart rate estimate.

Advanced linear and nonlinear compensations for 16QAM SC-400G unrepeatered transmission system

NASA Astrophysics Data System (ADS)

Zhang, Junwen; Yu, Jianjun; Chien, Hung-Chang

2018-02-01

Digital signal processing (DSP) with both linear equalization and nonlinear compensations are studied in this paper for the single-carrier 400G system based on 65-GBaud 16-quadrature amplitude modulation (QAM) signals. The 16-QAM signals are generated and pre-processed with pre-equalization (Pre-EQ) and Look-up-Table (LUT) based pre-distortion (Pre-DT) at the transmitter (Tx)-side. The implementation principle of training-based equalization and pre-distortion are presented here in this paper with experimental studies. At the receiver (Rx)-side, fiber-nonlinearity compensation based on digital backward propagation (DBP) are also utilized to further improve the transmission performances. With joint LUT-based Pre-DT and DBP-based post-compensation to mitigate the opto-electronic components and fiber nonlinearity impairments, we demonstrate the unrepeatered transmission of 1.6Tb/s based on 4-lane 400G single-carrier PDM-16QAM over 205-km SSMF without distributed amplifier.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rodenbeck, Christopher T.; Young, Derek; Chou, Tina

A combined radar and telemetry system is described. The combined radar and telemetry system includes a processing unit that executes instructions, where the instructions define a radar waveform and a telemetry waveform. The processor outputs a digital baseband signal based upon the instructions, where the digital baseband signal is based upon the radar waveform and the telemetry waveform. A radar and telemetry circuit transmits, simultaneously, a radar signal and telemetry signal based upon the digital baseband signal.

Automobile Crash Sensor Signal Processor

DOT National Transportation Integrated Search

1973-11-01

The crash sensor signal processor described interfaces between an automobile-installed doppler radar and an air bag activating solenoid or equivalent electromechanical device. The processor utilizes both digital and analog techniques to produce an ou...

Cancer Secretome May Influence BSP and DSP Expression in Human Salivary Gland Cells

PubMed Central

Hamilton, Samantha Lynn; Ferando, Blake; Eapen, Asha Sarah; Yu, Jennifer Chian; Joy, Anita Rose

2016-01-01

One of the biggest challenges in managing head and neck cancers, especially salivary gland cancers, is the identification of secreted biomarkers of the disease that can be evaluated noninvasively. A relevant source of enriched tumor markers could potentially be found in the tumor secretome. Although numerous studies have evaluated secretomes from various cancers, the influence of the cancer secretome derived from salivary gland cancers on the behavior of normal cells has not yet been elucidated. Our data indicate that secretome derived from salivary gland cancer cells can influence the expression of two potential biomarkers of oral cancer—namely, bone sialoprotein (BSP) and dentin sialoprotein (DSP)—in normal salivary gland cells. Using routine immunohistochemistry, immunofluorescence, and immunoblotting techniques, we demonstrate an enrichment of BSP and DSP in human salivary gland (HSG) cancer tissue, unique localizations of BSP and DSP in HSG cancer cells, and enriched expression of BSP and DSP in normal salivary gland cells exposed to a cancer secretome. The secretome domain of the cancer microenvironment could alter signaling cascades responsible for normal cell proliferation, migration, and invasion, thus enhancing cancer cell survival and the potential for cancer progression. The cancer secretome may be critical in maintaining and stimulating “cancer-ness,” thus potentially promoting specific hallmarks of metastasis. PMID:27881474

Cancer Secretome May Influence BSP and DSP Expression in Human Salivary Gland Cells.

PubMed

Hamilton, Samantha Lynn; Ferando, Blake; Eapen, Asha Sarah; Yu, Jennifer Chian; Joy, Anita Rose

2017-03-01

One of the biggest challenges in managing head and neck cancers, especially salivary gland cancers, is the identification of secreted biomarkers of the disease that can be evaluated noninvasively. A relevant source of enriched tumor markers could potentially be found in the tumor secretome. Although numerous studies have evaluated secretomes from various cancers, the influence of the cancer secretome derived from salivary gland cancers on the behavior of normal cells has not yet been elucidated. Our data indicate that secretome derived from salivary gland cancer cells can influence the expression of two potential biomarkers of oral cancer-namely, bone sialoprotein (BSP) and dentin sialoprotein (DSP)-in normal salivary gland cells. Using routine immunohistochemistry, immunofluorescence, and immunoblotting techniques, we demonstrate an enrichment of BSP and DSP in human salivary gland (HSG) cancer tissue, unique localizations of BSP and DSP in HSG cancer cells, and enriched expression of BSP and DSP in normal salivary gland cells exposed to a cancer secretome. The secretome domain of the cancer microenvironment could alter signaling cascades responsible for normal cell proliferation, migration, and invasion, thus enhancing cancer cell survival and the potential for cancer progression. The cancer secretome may be critical in maintaining and stimulating "cancer-ness," thus potentially promoting specific hallmarks of metastasis.

An LFMCW detector with new structure and FRFT based differential distance estimation method.

PubMed

Yue, Kai; Hao, Xinhong; Li, Ping

2016-01-01

This paper describes a linear frequency modulated continuous wave (LFMCW) detector which is designed for a collision avoidance radar. This detector can estimate distance between the detector and pedestrians or vehicles, thereby it will help to reduce the likelihood of traffic accidents. The detector consists of a transceiver and a signal processor. A novel structure based on the intermediate frequency signal (IFS) is designed for the transceiver which is different from the traditional LFMCW transceiver using the beat frequency signal (BFS) based structure. In the signal processor, a novel fractional Fourier transform (FRFT) based differential distance estimation (DDE) method is used to detect the distance. The new IFS based structure is beneficial for the FRFT based DDE method to reduce the computation complexity, because it does not need the scan of the optimal FRFT order. Low computation complexity ensures the feasibility of practical applications. Simulations are carried out and results demonstrate the efficiency of the detector designed in this paper.

Low-complexity camera digital signal imaging for video document projection system

NASA Astrophysics Data System (ADS)

Hsia, Shih-Chang; Tsai, Po-Shien

2011-04-01

We present high-performance and low-complexity algorithms for real-time camera imaging applications. The main functions of the proposed camera digital signal processing (DSP) involve color interpolation, white balance, adaptive binary processing, auto gain control, and edge and color enhancement for video projection systems. A series of simulations demonstrate that the proposed method can achieve good image quality while keeping computation cost and memory requirements low. On the basis of the proposed algorithms, the cost-effective hardware core is developed using Verilog HDL. The prototype chip has been verified with one low-cost programmable device. The real-time camera system can achieve 1270 × 792 resolution with the combination of extra components and can demonstrate each DSP function.

A Cochlear Implant Signal Processing Lab: Exploration of a Problem-Based Learning Exercise

ERIC Educational Resources Information Center

Bhatti, P. T.; McClellan, J. H.

2011-01-01

This paper presents an introductory signal processing laboratory and examines this laboratory exercise in the context of problem-based learning (PBL). Centered in a real-world application, a cochlear implant, the exercise challenged students to demonstrate a working software-based signal processor. Partnering in groups of two or three, second-year…

An advanced real-time digital signal processing system for linear systems emulation, with special emphasis on network and acoustic response characterization

NASA Astrophysics Data System (ADS)

Gaydecki, Patrick; Fernandes, Bosco

2003-11-01

A fast digital signal processing (DSP) system is described that can perform real-time emulation of a wide variety of linear audio-bandwidth systems and networks, such as reverberant spaces, musical instrument bodies and very high order filter networks. The hardware design is based upon a Motorola DSP56309 operating at 110 million multiplication-accumulations per second and a dual-channel 24 bit codec with a maximum sampling frequency of 192 kHz. High level software has been developed to express complex vector frequency responses as both infinite impulse response (IIR) and finite impulse response (FIR) coefficients, in a form suitable for real-time convolution by the firmware installed in the DSP system memory. An algorithm has also been devised to express IIR filters as equivalent FIR structures, thereby obviating the potential instabilities associated with recursive equations and negating the traditional deficiencies of FIR filters respecting equivalent analogue designs. The speed and dynamic range of the system is such that, when sampling at 48 kHz, the frequency response can be specified to a spectral precision of 22 Hz when sampling at 10 kHz, this resolution increases to 0.9 Hz. Moreover, it is also possible to control the phase of any frequency band with a theoretical precision of 10-5 degrees in all cases. The system has been applied in the study of analogue filter networks, real-time Hilbert transformation, phase-shift systems and musical instrument body emulation, where it is providing valuable new insights into the understanding of psychoacoustic mechanisms.

JPRS Report, Science & Technology, Europe.

DTIC Science & Technology

1991-04-30

processor in collaboration with Intel . The processor , christened Touchstone, will be used as the core of a parallel computer with 2,000 processors . One of...ELECTRONIQUE HEBDO in French 24 Jan 91 pp 14-15 [Article by Claire Remy: "Everything Set for Neural Signal Processors " first paragraph is ELECTRONIQUE...paving the way for neural signal processors in so doing. The principal advantage of this specific circuit over a neuromimetic software program is

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

Stanford Hardware Development Program

NASA Technical Reports Server (NTRS)

Peterson, A.; Linscott, I.; Burr, J.

1986-01-01

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Method of implementation of optoelectronic multiparametric signal processing systems based on multivalued-logic principles

NASA Astrophysics Data System (ADS)

Arestova, M. L.; Bykovskii, A. Yu

1995-10-01

An architecture is proposed for a specialised optoelectronic multivalued logic processor based on the Allen—Givone algebra. The processor is intended for multiparametric processing of data arriving from a large number of sensors or for tackling spectral analysis tasks. The processor architecture makes it possible to obtain an approximate general estimate of the state of an object being diagnosed on a p-level scale. Optoelectronic systems are proposed for MAXIMUM, MINIMUM, and LITERAL logic gates, based on optical-frequency encoding of logic levels. Corresponding logic gates form a complete set of logic functions in the Allen—Givone algebra.

Method and system for selecting data sampling phase for self timed interface logic

DOEpatents

Hoke, Joseph Michael; Ferraiolo, Frank D.; Lo, Tin-Chee; Yarolin, John Michael

2005-01-04

An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.

Diabetic neuropathy: mechanisms, emerging treatments, and subtypes.

PubMed

Albers, James W; Pop-Busui, Rodica

2014-08-01

Diabetic neuropathies (DNs) differ in clinical course, distribution, fiber involvement (type and size), and pathophysiology, the most typical type being a length-dependent distal symmetric polyneuropathy (DSP) with differing degrees of autonomic involvement. The pathogenesis of diabetic DSP is multifactorial, including increased mitochondrial production of free radicals due to hyperglycemia-induced oxidative stress. Mechanisms that impact neuronal activity, mitochondrial function, membrane permeability, and endothelial function include formation of advanced glycosylation end products, activation of polyol aldose reductase signaling, activation of poly(ADP ribose) polymerase, and altered function of the Na(+)/K(+)-ATPase pump. Hyperglycemia-induced endoplasmic reticulum stress triggers several neuronal apoptotic processes. Additional mechanisms include impaired nerve perfusion, dyslipidemia, altered redox status, low-grade inflammation, and perturbation of calcium balance. Successful therapies require an integrated approach targeting these mechanisms. Intensive glycemic control is essential but is insufficient to prevent onset or progression of DSP, and disease-modifying treatments for DSP have been disappointing. Atypical forms of DN include subacute-onset sensory (symmetric) or motor (asymmetric) predominant conditions that are frequently painful but generally self-limited. DNs are a major cause of disability, associated with reduced quality of life and increased mortality.

Coherent detection and digital signal processing for fiber optic communications

NASA Astrophysics Data System (ADS)

Ip, Ezra

The drive towards higher spectral efficiency in optical fiber systems has generated renewed interest in coherent detection. We review different detection methods, including noncoherent, differentially coherent, and coherent detection, as well as hybrid detection methods. We compare the modulation methods that are enabled and their respective performances in a linear regime. An important system parameter is the number of degrees of freedom (DOF) utilized in transmission. Polarization-multiplexed quadrature-amplitude modulation maximizes spectral efficiency and power efficiency as it uses all four available DOF contained in the two field quadratures in the two polarizations. Dual-polarization homodyne or heterodyne downconversion are linear processes that can fully recover the received signal field in these four DOF. When downconverted signals are sampled at the Nyquist rate, compensation of transmission impairments can be performed using digital signal processing (DSP). Software based receivers benefit from the robustness of DSP, flexibility in design, and ease of adaptation to time-varying channels. Linear impairments, including chromatic dispersion (CD) and polarization-mode dispersion (PMD), can be compensated quasi-exactly using finite impulse response filters. In practical systems, sampling the received signal at 3/2 times the symbol rate is sufficient to enable an arbitrary amount of CD and PMD to be compensated for a sufficiently long equalizer whose tap length scales linearly with transmission distance. Depending on the transmitted constellation and the target bit error rate, the analog-to-digital converter (ADC) should have around 5 to 6 bits of resolution. Digital coherent receivers are naturally suited for the implementation of feedforward carrier recovery, which has superior linewidth tolerance than phase-locked loops, and does not suffer from feedback delay constraints. Differential bit encoding can be used to prevent catastrophic receiver failure due to cycle slips. In systems where nonlinear effects are concentrated mostly at fiber locations with small accumulated dispersion, nonlinear phase de-rotation is a low-complexity algorithm that can partially mitigate nonlinear effects. For systems with arbitrary dispersion maps, however, backpropagation is the only universal technique that can jointly compensate dispersion and fiber nonlinearity. Backpropagation requires solving the nonlinear Schrodinger equation at the receiver, and has high computational cost. Backpropagation is most effective when dispersion compensation fibers are removed, and when signal processing is performed at three times oversampling. Backpropagation can improve system performance and increase transmission distance. With anticipated advances in analog-to-digital converters and integrated circuit technology, DSP-based coherent receivers at bit rates up to 100 Gb/s should become practical in the near future.

Method of Enhancing On-Board State Estimation Using Communication Signals

NASA Technical Reports Server (NTRS)

Anzalone, Evan J. (Inventor); Chuang, Jason C. H. (Inventor)

2015-01-01

A method of enhancing on-board state estimation for a spacecraft utilizes a network of assets to include planetary-based assets and space-based assets. Communication signals transmitted from each of the assets into space are defined by a common protocol. Data is embedded in each communication signal transmitted by the assets. The data includes a time-of-transmission for a corresponding one of the communication signals and a position of a corresponding one of the assets at the time-of-transmission. A spacecraft is equipped to receive the communication signals, has a clock synchronized to the space-wide time reference frame, and has a processor programmed to generate state estimates of the spacecraft. Using its processor, the spacecraft determines a one-dimensional range from itself to at least one of the assets and then updates its state estimates using each one-dimensional range.

Implementation of medical monitor system based on networks

NASA Astrophysics Data System (ADS)

Yu, Hui; Cao, Yuzhen; Zhang, Lixin; Ding, Mingshi

2006-11-01

In this paper, the development trend of medical monitor system is analyzed and portable trend and network function become more and more popular among all kinds of medical monitor devices. The architecture of medical network monitor system solution is provided and design and implementation details of medical monitor terminal, monitor center software, distributed medical database and two kind of medical information terminal are especially discussed. Rabbit3000 system is used in medical monitor terminal to implement security administration of data transfer on network, human-machine interface, power management and DSP interface while DSP chip TMS5402 is used in signal analysis and data compression. Distributed medical database is designed for hospital center according to DICOM information model and HL7 standard. Pocket medical information terminal based on ARM9 embedded platform is also developed to interactive with center database on networks. Two kernels based on WINCE are customized and corresponding terminal software are developed for nurse's routine care and doctor's auxiliary diagnosis. Now invention patent of the monitor terminal is approved and manufacture and clinic test plans are scheduled. Applications for invention patent are also arranged for two medical information terminals.

Development of Fast Measurement System of Neutron Emission Profile Using a Digital Signal Processing Technique in JT-60U

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ishikawa, M.; Shinohara, K.; Itoga, T.

2008-03-12

Neutron emission profiles are routinely measured in JT-60U Tokamak. Stinbene neuron detectors (SNDs), which combine a Stilbene organic crystal scintillation detector (Stilbene detector) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure neutron flux efficiently. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to {approx}1x 10{sup 5} counts/s due to the dead time of the analog PSD circuit. To overcome this issue, a digital signal processing (DSP) system using a Flash-ADC has been developed. In this system, anode signals from the photomultiplier of the Stilbene detectormore » are fed to the Flash ADC and digitized. Then, the PSD between neutrons and gamma-rays are performed using software. The photomultiplier tube is also modified to suppress and correct gain fluctuation of the photomultiplier. The DSP system has been installed in the center channel of the vertical neutron collimator system in JT-60U and applied to measurements of neutron flux in JT-60U experiments. Neutron flux are successfully measured with count rate up to {approx}1x 10{sup 6} counts/s without the effect of pile up of detected pulses. The performance of the DSP system as a neutron detector is demonstrated.« less

A Novel Dual Separate Paths (DSP) Algorithm Providing Fault-Tolerant Communication for Wireless Sensor Networks.

PubMed

Tien, Nguyen Xuan; Kim, Semog; Rhee, Jong Myung; Park, Sang Yoon

2017-07-25

Fault tolerance has long been a major concern for sensor communications in fault-tolerant cyber physical systems (CPSs). Network failure problems often occur in wireless sensor networks (WSNs) due to various factors such as the insufficient power of sensor nodes, the dislocation of sensor nodes, the unstable state of wireless links, and unpredictable environmental interference. Fault tolerance is thus one of the key requirements for data communications in WSN applications. This paper proposes a novel path redundancy-based algorithm, called dual separate paths (DSP), that provides fault-tolerant communication with the improvement of the network traffic performance for WSN applications, such as fault-tolerant CPSs. The proposed DSP algorithm establishes two separate paths between a source and a destination in a network based on the network topology information. These paths are node-disjoint paths and have optimal path distances. Unicast frames are delivered from the source to the destination in the network through the dual paths, providing fault-tolerant communication and reducing redundant unicast traffic for the network. The DSP algorithm can be applied to wired and wireless networks, such as WSNs, to provide seamless fault-tolerant communication for mission-critical and life-critical applications such as fault-tolerant CPSs. The analyzed and simulated results show that the DSP-based approach not only provides fault-tolerant communication, but also improves network traffic performance. For the case study in this paper, when the DSP algorithm was applied to high-availability seamless redundancy (HSR) networks, the proposed DSP-based approach reduced the network traffic by 80% to 88% compared with the standard HSR protocol, thus improving network traffic performance.

Experiments with Sensor Motes and Java-DSP

ERIC Educational Resources Information Center

Kwon, Homin; Berisha, V.; Atti, V.; Spanias, A.

2009-01-01

Distributed wireless sensor networks (WSNs) are being proposed for various applications including defense, security, and smart stages. The introduction of hardware wireless sensors in a signal processing education setting can serve as a paradigm for data acquisition, collaborative signal processing, or simply as a platform for obtaining,…

Wnt signaling regulates pulp volume and dentin thickness

PubMed Central

Lim, Won Hee; Liu, Bo; Cheng, Du; Hunter, Daniel J; Zhong, Zhendong; Ramos, Daniel M; Williams, Bart O; Sharpe, Paul T; Bardet, Claire; Mah, Su-jung; Helms, Jill A

2015-01-01

Odontoblasts, cementoblasts, ameloblasts and osteoblasts all form mineralized tissues in the craniofacial complex, and all these cell types exhibit active Wnt signaling during postnatal life. We set out to understand the functions of this Wnt signaling, by evaluating the phenotypes of mice in which the essential Wnt chaperone protein, Wingless was eliminated. The deletion of Wls was restricted to cells expressing Osteocalcin, which in addition to osteoblasts includes odontoblasts, cementoblasts, and ameloblasts. Dentin, cementum, enamel, and bone all formed in OCN-Cre;Wlsfl/fl mice but their homeostasis was dramatically affected. The most notable feature was a significant increase in dentin volume and density. We attribute this gain in dentin volume to a Wnt-mediated mis-regulation of Runx2. Normally, Wnt signaling stimulates Runx2, which in turn inhibits DSP; this inhibition must be relieved for odontoblasts to differentiate. In OCN-Cre;Wlsfl/fl mice, Wnt pathway activation is reduced and Runx2 levels decline. The Runx2-mediated repression of DSP is relieved and odontoblast differentiation is accordingly enhanced. This study demonstrates the importance of Wnt signaling in the homeostasis of mineralized tissues of the craniofacial complex. PMID:23996396

Equalization of nonlinear transmission impairments by maximum-likelihood-sequence estimation in digital coherent receivers.

PubMed

Khairuzzaman, Md; Zhang, Chao; Igarashi, Koji; Katoh, Kazuhiro; Kikuchi, Kazuro

2010-03-01

We describe a successful introduction of maximum-likelihood-sequence estimation (MLSE) into digital coherent receivers together with finite-impulse response (FIR) filters in order to equalize both linear and nonlinear fiber impairments. The MLSE equalizer based on the Viterbi algorithm is implemented in the offline digital signal processing (DSP) core. We transmit 20-Gbit/s quadrature phase-shift keying (QPSK) signals through a 200-km-long standard single-mode fiber. The bit-error rate performance shows that the MLSE equalizer outperforms the conventional adaptive FIR filter, especially when nonlinear impairments are predominant.

Design of a dataway processor for a parallel image signal processing system

NASA Astrophysics Data System (ADS)

Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

1995-04-01

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G; Salapura, Valentina

2014-12-02

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Electro-optic voltage sensor for sensing voltage in an E-field

DOEpatents

Woods, G.K.; Renak, T.W.

1999-04-06

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages is disclosed. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam`s polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured. 18 figs.

Electro-optical voltage sensor head

DOEpatents

Woods, Gregory K.

1998-01-01

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Electro-optic voltage sensor for sensing voltage in an E-field

DOEpatents

Woods, Gregory K.; Renak, Todd W.

1999-01-01

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Electro-optical voltage sensor head

DOEpatents

Woods, G.K.

1998-03-24

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages is disclosed. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam`s polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured. 6 figs.

Convergent optical wired and wireless long-reach access network using high spectral-efficient modulation.

PubMed

Chow, C W; Lin, Y H

2012-04-09

To provide broadband services in a single and low cost perform, the convergent optical wired and wireless access network is promising. Here, we propose and demonstrate a convergent optical wired and wireless long-reach access networks based on orthogonal wavelength division multiplexing (WDM). Both the baseband signal and the radio-over-fiber (ROF) signal are multiplexed and de-multiplexed in optical domain, hence it is simple and the operation speed is not limited by the electronic bottleneck caused by the digital signal processing (DSP). Error-free de-multiplexing and down-conversion can be achieved for all the signals after 60 km (long-reach) fiber transmission. The scalability of the system for higher bit-rate (60 GHz) is also simulated and discussed.

Fault detection and bypass in a sequence information signal processor

NASA Technical Reports Server (NTRS)

Peterson, John C. (Inventor); Chow, Edward T. (Inventor)

1992-01-01

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

Signal generation and mixing electronics for frequency-domain lifetime and spectral fluorometry

NASA Technical Reports Server (NTRS)

Cruce, Tommy Clay (Inventor); Hallidy, William H. (Inventor); Chin, Robert C. (Inventor)

2007-01-01

The present invention additionally comprises a method and apparatus for generating and mixing signals for frequency-domain lifetime and spectral fluorometry. The present invention comprises a plurality of signal generators that generate a plurality of signals where the signal generators modulate the amplitude and/or the frequency of the signals. The present invention uses one of these signals to drive an excitation signal that the present invention then directs and transmits at a target mixture, which absorbs the energy from the excitation signal. The property of fluorescence causes the target mixture to emit an emitted signal that the present invention detects with a signal detector. The present invention uses a plurality of mixers to produce a processor reference signal and a data signal. The present invention then uses a processor to compare the processor reference signal with the data signal by analyzing the differences in the phase and the differences in the amplitude between the two signals. The processor then extracts the fluorescence lifetime and fluorescence spectrum of the emitted signal from the phase and amplitude information using a chemometric analysis.

Research on moving object detection based on frog's eyes

NASA Astrophysics Data System (ADS)

Fu, Hongwei; Li, Dongguang; Zhang, Xinyuan

2008-12-01

On the basis of object's information processing mechanism with frog's eyes, this paper discussed a bionic detection technology which suitable for object's information processing based on frog's vision. First, the bionics detection theory by imitating frog vision is established, it is an parallel processing mechanism which including pick-up and pretreatment of object's information, parallel separating of digital image, parallel processing, and information synthesis. The computer vision detection system is described to detect moving objects which has special color, special shape, the experiment indicates that it can scheme out the detecting result in the certain interfered background can be detected. A moving objects detection electro-model by imitating biologic vision based on frog's eyes is established, the video simulative signal is digital firstly in this system, then the digital signal is parallel separated by FPGA. IN the parallel processing, the video information can be caught, processed and displayed in the same time, the information fusion is taken by DSP HPI ports, in order to transmit the data which processed by DSP. This system can watch the bigger visual field and get higher image resolution than ordinary monitor systems. In summary, simulative experiments for edge detection of moving object with canny algorithm based on this system indicate that this system can detect the edge of moving objects in real time, the feasibility of bionic model was fully demonstrated in the engineering system, and it laid a solid foundation for the future study of detection technology by imitating biologic vision.

Digital signal processor and processing method for GPS receivers

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1989-01-01

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

A comparison between the first-fit settings of two multichannel digital signal-processing strategies: music quality ratings and speech-in-noise scores.

PubMed

Higgins, Paul; Searchfield, Grant; Coad, Gavin

2012-06-01

The aim of this study was to determine which level-dependent hearing aid digital signal-processing strategy (DSP) participants preferred when listening to music and/or performing a speech-in-noise task. Two receiver-in-the-ear hearing aids were compared: one using 32-channel adaptive dynamic range optimization (ADRO) and the other wide dynamic range compression (WDRC) incorporating dual fast (4 channel) and slow (15 channel) processing. The manufacturers' first-fit settings based on participants' audiograms were used in both cases. Results were obtained from 18 participants on a quick speech-in-noise (QuickSIN; Killion, Niquette, Gudmundsen, Revit, & Banerjee, 2004) task and for 3 music listening conditions (classical, jazz, and rock). Participants preferred the quality of music and performed better at the QuickSIN task using the hearing aids with ADRO processing. A potential reason for the better performance of the ADRO hearing aids was less fluctuation in output with change in sound dynamics. ADRO processing has advantages for both music quality and speech recognition in noise over the multichannel WDRC processing that was used in the study. Further evaluations of which DSP aspects contribute to listener preference are required.

Technologies of high-performance thermography systems

NASA Astrophysics Data System (ADS)

Breiter, R.; Cabanski, Wolfgang A.; Mauk, K. H.; Kock, R.; Rode, W.

1997-08-01

A family of 2 dimensional detection modules based on 256 by 256 and 486 by 640 platinum silicide (PtSi) focal planes, or 128 by 128 and 256 by 256 mercury cadmium telluride (MCT) focal planes for applications in either the 3 - 5 micrometer (MWIR) or 8 - 10 micrometer (LWIR) range was recently developed by AIM. A wide variety of applications is covered by the specific features unique for these two material systems. The PtSi units provide state of the art correctability with long term stable gain and offset coefficients. The MCT units provide extremely fast frame rates like 400 Hz with snapshot integration times as short as 250 microseconds and with a thermal resolution NETD less than 20 mK for e.g. the 128 by 128 LWIR module. The unique design idea general for all of these modules is the exclusively digital interface, using 14 bit analog to digital conversion to provide state of the art correctability, access to highly dynamic scenes without any loss of information and simplified exchangeability of the units. Device specific features like bias voltages etc. are identified during the final test and stored in a memory on the driving electronics. This concept allows an easy exchange of IDCAs of the same type without any need for tuning or e.g. the possibility to upgrade a PtSi based unit to an MCT module by just loading the suitable software. Miniaturized digital signal processor (DSP) based image correction units were developed for testing and operating the units with output data rates of up to 16 Mpixels/s. These boards provide the ability for freely programmable realtime functions like two point correction and various data manipulations in thermography applications.

Watchdog activity monitor (WAM) for use wth high coverage processor self-test

NASA Technical Reports Server (NTRS)

Tulpule, Bhalchandra R. (Inventor); Crosset, III, Richard W. (Inventor); Versailles, Richard E. (Inventor)

1988-01-01

A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.

The GF-3 SAR Data Processor

PubMed Central

Han, Bing; Ding, Chibiao; Zhong, Lihua; Liu, Jiayin; Qiu, Xiaolan; Hu, Yuxin; Lei, Bin

2018-01-01

The Gaofen-3 (GF-3) data processor was developed as a workstation-based GF-3 synthetic aperture radar (SAR) data processing system. The processor consists of two vital subsystems of the GF-3 ground segment, which are referred to as data ingesting subsystem (DIS) and product generation subsystem (PGS). The primary purpose of DIS is to record and catalogue GF-3 raw data with a transferring format, and PGS is to produce slant range or geocoded imagery from the signal data. This paper presents a brief introduction of the GF-3 data processor, including descriptions of the system architecture, the processing algorithms and its output format. PMID:29534464

New sensorless, efficient optimized and stabilized v/f control for pmsm machines

NASA Astrophysics Data System (ADS)

Jafari, Seyed Hesam

With the rapid advances in power electronics and motor drive technologies in recent decades, permanent magnet synchronous machines (PMSM) have found extensive applications in a variety of industrial systems due to its many desirable features such as high power density, high efficiency, and high torque to current ratio, low noise, and robustness. In low dynamic applications like pumps, fans and compressors where the motor speed is nearly constant, usage of a simple control algorithm that can be implemented with least number of the costly external hardware can be highly desirable for industry. In recent published works, for low power PMSMs, a new sensorless volts-per-hertz (V/f) controlling method has been proposed which can be used for PMSM drive applications where the motor speed is constant. Moreover, to minimize the cost of motor implementation, the expensive rotor damper winding was eliminated. By removing the damper winding, however, instability problems normally occur inside of the motor which in some cases can be harmful for a PMSM drive. As a result, to address the instability issue, a stabilizing loop was developed and added to the conventional V/f. By further studying the proposed sensorless stabilized V/f, and calculating power loss, it became known that overall motor efficiency still is needed to be improved and optimized. This thesis suggests a new V/f control method for PMSMs, where both efficiency and stability problems are addressed. Also, although in nearly all recent related research, methods have been applied to low power PMSM, for the first time, in this thesis, the suggested method is implemented for a medium power 15 kW PMSM. A C2000 F2833x Digital Signal Processor (DSP) is used as controller part for the student custom built PMSM drive, but instead of programming the DSP in Assembly or C, the main control algorithm was developed in a rapid prototype software environment which here Matlab Simulink embedded code library is used.

A universal computer control system for motors

NASA Technical Reports Server (NTRS)

Szakaly, Zoltan F. (Inventor)

1991-01-01

A control system for a multi-motor system such as a space telerobot, having a remote computational node and a local computational node interconnected with one another by a high speed data link is described. A Universal Computer Control System (UCCS) for the telerobot is located at each node. Each node is provided with a multibus computer system which is characterized by a plurality of processors with all processors being connected to a common bus, and including at least one command processor. The command processor communicates over the bus with a plurality of joint controller cards. A plurality of direct current torque motors, of the type used in telerobot joints and telerobot hand-held controllers, are connected to the controller cards and responds to digital control signals from the command processor. Essential motor operating parameters are sensed by analog sensing circuits and the sensed analog signals are converted to digital signals for storage at the controller cards where such signals can be read during an address read/write cycle of the command processing processor.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report: METSAT A2 Signal Processor (P/N 1331120-2, S/N F03) S/N 107

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F03. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report, METSAT A2 Signal Processor (P/N 1331120-2, S/N F04) S/N 108

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

Circuitry, systems and methods for detecting magnetic fields

DOEpatents

Kotter, Dale K [Shelley, ID; Spencer, David F [Idaho Falls, ID; Roybal, Lyle G [Idaho Falls, ID; Rohrbaugh, David T [Idaho Falls, ID

2010-09-14

Circuitry for detecting magnetic fields includes a first magnetoresistive sensor and a second magnetoresistive sensor configured to form a gradiometer. The circuitry includes a digital signal processor and a first feedback loop coupled between the first magnetoresistive sensor and the digital signal processor. A second feedback loop which is discrete from the first feedback loop is coupled between the second magnetoresistive sensor and the digital signal processor.

Chronic administration of DSP-7238, a novel, potent, specific and substrate-selective DPP IV inhibitor, improves glycaemic control and beta-cell damage in diabetic mice.

PubMed

Furuta, Y; Horiguchi, M; Sugaru, E; Ono-Kishino, M; Otani, M; Sakai, M; Masui, Y; Tsuchida, A; Sato, Y; Takubo, K; Hochigai, H; Kimura, H; Nakahira, H; Nakagawa, T; Taiji, M

2010-05-01

The purpose of this study is to assess the in vitro enzyme inhibition profile of DSP-7238, a novel non-cyanopyrrolidine dipeptidyl peptidase (DPP) IV inhibitor and to evaluate the acute and chronic effects of this compound on glucose metabolism in two different mouse models of type 2 diabetes. The in vitro enzyme inhibition profile of DSP-7238 was assessed using plasma and recombinant enzymes including DPP IV, DPP II, DPP8, DPP9 and fibroblast activation protein alpha (FAPalpha) with fluorogenic substrates. The inhibition type was evaluated based on the Lineweaver-Burk plot. Substrate selectivity of DSP-7238 and comparator DPP IV inhibitors (vildagliptin, sitagliptin, saxagliptin and linagliptin) was evaluated by mass spectrometry based on the changes in molecular weight of peptide substrates caused by release of N-terminal dipeptides. In the in vivo experiments, high-fat diet-induced obese (DIO) mice were subjected to oral glucose tolerance test (OGTT) following a single oral administration of DSP-7238. To assess the chronic effects of DSP-7238 on glycaemic control and pancreatic beta-cell damage, DSP-7238 was administered for 11 weeks to mice made diabetic by a combination of high-fat diet (HFD) and a low-dose of streptozotocin (STZ). After the dosing period, HbA1c was measured and pancreatic damage was evaluated by biological and histological analyses. DSP-7238 and sitagliptin both competitively inhibited recombinant human DPP IV (rhDPP IV) with K(i) values of 0.60 and 2.1 nM respectively. Neither vildagliptin nor saxagliptin exhibited competitive inhibition of rhDPP IV. DSP-7238 did not inhibit DPP IV-related enzymes including DPP8, DPP9, DPP II and FAPalpha, whereas vildagliptin and saxagliptin showed inhibition of DPP8 and DPP9. Inhibition of glucagon-like peptide-1 (GLP-1) degradation by DSP-7238 was apparently more potent than its inhibition of chemokine (C-X-C motif) ligand 10 (IP-10) or chemokine (C-X-C motif) ligand 12 (SDF-1alpha) degradation. In contrast, vildagliptin and saxagliptin showed similar degree of inhibition of degradation for all the substrates tested. Compared to treatment with the vehicle, single oral administration of DSP-7238 dose-dependently decreased plasma DPP IV activity and improved glucose tolerance in DIO mice. In addition, DSP-7238 significantly decreased HbA1c and ameliorated pancreatic damage following 11 weeks of chronic treatment in HFD/STZ mice. We have shown in this study that DSP-7238 is a potent DPP IV inhibitor that has high specificity for DPP IV and substrate selectivity against GLP-1. We have also found that chronic treatment with DSP-7238 improves glycaemic control and ameliorates beta-cell damage in a mouse model with impaired insulin sensitivity and secretion. These findings indicate that DSP-7238 may be a new therapeutic agent for the treatment of type 2 diabetes.

Evaluation of commercial video-based intersection signal actuation systems.

DOT National Transportation Integrated Search

2008-12-01

Video cameras and computer image processors have come into widespread use for the detection of : vehicles for signal actuation at controlled intersections. Video is considered both a cost-saving and : convenient alternative to conventional stop-line ...

High-performance ultra-low power VLSI analog processor for data compression

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1996-01-01

An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.

Global synchronization of parallel processors using clock pulse width modulation

DOEpatents

Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

2013-04-02

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

A seismic signal processor suitable for use with the NOAA/GOES satellite data collection system

NASA Technical Reports Server (NTRS)

Webster, W. J., Jr.; Miller, W. H.; Whitley, R.; Allenby, R. J.; Dennison, R. T.

1981-01-01

Because of the high data-rate requirements, a practical system capable of collecting seismic information in the field and relaying it, via satellite, to a central collection point is not yet available. A seismic signal processor has been developed and tested for use with the NOAA/GOES satellite data collection system. Performance tests on recorded, as well as real time, short period signals indicate that the event recognition technique used is nearly perfect in its rejection of environmental noise and other non-seismic signals and that, with the use of solid state buffer memories, data can be acquired in many swarm situations. The design of a complete field data collection platform is discussed based on the prototype evaluation.

Detection of underground pipeline based on Golay waveform design

NASA Astrophysics Data System (ADS)

Dai, Jingjing; Xu, Dazhuan

2017-08-01

The detection of underground pipeline is an important problem in the development of the city, but the research about it is not mature at present. In this paper, based on the principle of waveform design in wireless communication, we design an acoustic signal detection system to detect the location of underground pipelines. According to the principle of acoustic localization, we chose DSP-F28335 as the development board, and use DA and AD module as the master control chip. The DA module uses complementary Golay sequence as emission signal. The AD module acquisiting data synchronously, so that the echo signals which containing position information of the target is recovered through the signal processing. The test result shows that the method in this paper can not only calculate the sound velocity of the soil, but also can locate the location of underground pipelines accurately.

On the efficacy of using the transfer-controlled procedure during periods of STP processor overloads in SS7 networks

NASA Astrophysics Data System (ADS)

Rumsewicz, Michael

1994-04-01

In this paper, we examine call completion performance, rather than message throughput, in a Common Channel Signaling network in which the processing resources, and not transmission resources, of a Signaling Transfer Point (STP) are overloaded. Specifically, we perform a transient analysis, via simulation, of a network consisting of a single Central Processor-based STP connecting many local exchanges. We consider the efficacy of using the Transfer Controlled (TFC) procedure when the network call attempt rate exceeds the processing capability of the STP. We find the following: (1) the success of the control depends critically on the rate at which TFC's are sent; (2) use of the TFC procedure in theevent of processor overload can provide reasonable call completion rates.

Diabetic Neuropathy: Mechanisms, Emerging Treatments, and Subtypes

PubMed Central

Pop-Busui, Rodica

2016-01-01

Diabetic neuropathies (DNs) differ in clinical course, distribution, fiber involvement (type and size), and pathophysiology, the most typical type being a length-dependent distal symmetric polyneuropathy (DSP) with differing degrees of autonomic involvement. The pathogenesis of diabetic DSP is multifactorial, including increased mitochondrial production of free radicals due to hyperglycemia-induced oxidative stress. Mechanisms that impact neuronal activity, mitochondrial function, membrane permeability, and endothelial function include formation of advanced glycosylation end products, activation of polyol aldose reductase signaling, activation of poly(ADP ribose) polymerase, and altered function of the Na+/K+-ATPase pump. Hyperglycemia-induced endoplasmic reticulum stress triggers several neuronal apoptotic processes. Additional mechanisms include impaired nerve perfusion, dyslipidemia, altered redox status, low-grade inflammation, and perturbation of calcium balance. Successful therapies require an integrated approach targeting these mechanisms. Intensive glycemic control is essential but is insufficient to prevent onset or progression of DSP, and disease-modifying treatments for DSP have been disappointing. Atypical forms of DN include subacute-onset sensory (symmetric) or motor (asymmetric) predominant conditions that are frequently painful but generally self-limited. DNs are a major cause of disability, associated with reduced quality of life and increased mortality. PMID:24954624

EGR distribution and fluctuation probe based on CO2 measurements

DOEpatents

Parks, II, James E.; Partridge, Jr., William P.; Yoo, Ji Hyung

2015-06-30

A diagnostic system having a laser, an EGR probe, a detector and a processor. The laser may be a swept-.lamda. laser having a sweep range including a significant CO.sub.2 feature and substantially zero absorption regions. The sweep range may extend from about 2.708 .mu.m to about 2.7085 .mu.m. The processor may determine CO.sub.2 concentration as a function of the detector output signal. The processor may normalize the output signal as a function of the zero absorption regions. The system may include a plurality of EGR probes receiving light from a single laser. The system may include a separate detector for each probe. Alternatively, the system may combine the light returning from the different probes into a composite beam that is measured by a single detector. A unique modulation characteristic may be introduced into each light beam before combination so that the processor can discriminate between them in the composite beam.

Quinoxalinylurea derivatives as a novel class of JSP-1 inhibitors.

PubMed

Zhang, Li; Qiu, Beiying; Xiong, Bing; Li, Xin; Li, Jingya; Wang, Xin; Li, Jia; Shen, Jingkang

2007-04-15

A series of quinoxalinylurea-based inhibitors are synthesized and shown to be the novel and potent inhibitors against Jnk Stimulatory Phosphatase-1 (JSP-1), which is a special member of dual-specificity protein phosphatase (DSP) family. Biological assay and computational modeling studies showed the compounds were reversible and noncompetitive inhibitors of JSP-1. JSP-1 inhibitors may be useful for the treatment of inflammatory, vascular, neurodegenerative, metabolic, and oncological diseases in humans associated with dysfunctional Jnk signaling.

Preface

NASA Astrophysics Data System (ADS)

Zhuge, Qunbi; Chen, Xi

2018-02-01

Global IP traffic is predicted to increase nearly threefold over the next 5 years, driven by emerging high-bandwidth-demanding applications, such as cloud computing, 5G wireless, high-definition video streaming, and virtual reality. This results in a continuously increasing demand on the capacity of backbone optical networks. During the past decade, advanced digital signal processing (DSP), modulation formats, and forward error correction (FEC) were commercially realized to exploit the capacity potential of long-haul fiber channels, and have increased per channel data rate from 10 Gb/s to 400 Gb/s. DSP has played a crucial role in coherent transceivers to accommodate channel impairments including chromatic dispersion (CD), polarization mode dispersion (PMD), laser phase noise, fiber nonlinearities, clock jitter, and so forth. The advance of DSP has also enabled innovations in modulation formats to increase spectral efficiency, improve linear/nonlinear noise tolerance, and realize flexible bandwidth. Moving forward to next generation 1 Tb/s systems on conventional single mode fiber (SMF) platform, more innovations in DSP techniques are needed to further reduce cost per bit, increase network efficiency, and close the gap to the Shannon limit. To further increase capacity per fiber, spatial-division multiplexing (SDM) systems can be used. DSP techniques such as advanced channel equalization methods and distortion compensation can help SDM systems to achieve higher system capacity. In the area of short-reach transmission, the rapid increase of data center network traffic has driven the development of optical technologies for both intra- and inter-data center interconnects (DCI). In particular, DSP has been exploited in intensity-modulation direct detection (IM/DD) systems to realize 400 Gb/s pluggable optical transceivers. In addition, multi-dimensional direct detection modulation schemes are being investigated to increase the data rate per wavelength targeting 1 Tb/s interface.

Experimental testing of the noise-canceling processor.

PubMed

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

New Modular Ultrasonic Signal Processing Building Blocks for Real-Time Data Acquisition and Post Processing

NASA Astrophysics Data System (ADS)

Weber, Walter H.; Mair, H. Douglas; Jansen, Dion

2003-03-01

A suite of basic signal processors has been developed. These basic building blocks can be cascaded together to form more complex processors without the need for programming. The data structures between each of the processors are handled automatically. This allows a processor built for one purpose to be applied to any type of data such as images, waveform arrays and single values. The processors are part of Winspect Data Acquisition software. The new processors are fast enough to work on A-scan signals live while scanning. Their primary use is to extract features, reduce noise or to calculate material properties. The cascaded processors work equally well on live A-scan displays, live gated data or as a post-processing engine on saved data. Researchers are able to call their own MATLAB or C-code from anywhere within the processor structure. A built-in formula node processor that uses a simple algebraic editor may make external user programs unnecessary. This paper also discusses the problems associated with ad hoc software development and how graphical programming languages can tie up researchers writing software rather than designing experiments.

Real Time Calibration Method for Signal Conditioning Amplifiers

NASA Technical Reports Server (NTRS)

Medelius, Pedro J. (Inventor); Mata, Carlos T. (Inventor); Eckhoff, Anthony (Inventor); Perotti, Jose (Inventor); Lucena, Angel (Inventor)

2004-01-01

A signal conditioning amplifier receives an input signal from an input such as a transducer. The signal is amplified and processed through an analog to digital converter and sent to a processor. The processor estimates the input signal provided by the transducer to the amplifier via a multiplexer. The estimated input signal is provided as a calibration voltage to the amplifier immediately following the receipt of the amplified input signal. The calibration voltage is amplified by the amplifier and provided to the processor as an amplified calibration voltage. The amplified calibration voltage is compared to the amplified input signal, and if a significant error exists, the gain and/or offset of the amplifier may be adjusted as necessary.

Implementation of orthogonal frequency division multiplexing (OFDM) and advanced signal processing for elastic optical networking in accordance with networking and transmission constraints

NASA Astrophysics Data System (ADS)

Johnson, Stanley

An increasing adoption of digital signal processing (DSP) in optical fiber telecommunication has brought to the fore several interesting DSP enabled modulation formats. One such format is orthogonal frequency division multiplexing (OFDM), which has seen great success in wireless and wired RF applications, and is being actively investigated by several research groups for use in optical fiber telecom. In this dissertation, I present three implementations of OFDM for elastic optical networking and distributed network control. The first is a field programmable gate array (FPGA) based real-time implementation of a version of OFDM conventionally known as intensity modulation and direct detection (IMDD) OFDM. I experimentally demonstrate the ability of this transmission system to dynamically adjust bandwidth and modulation format to meet networking constraints in an automated manner. To the best of my knowledge, this is the first real-time software defined networking (SDN) based control of an OFDM system. In the second OFDM implementation, I experimentally demonstrate a novel OFDM transmission scheme that supports both direct detection and coherent detection receivers simultaneously using the same OFDM transmitter. This interchangeable receiver solution enables a trade-off between bit rate and equipment cost in network deployment and upgrades. I show that the proposed transmission scheme can provide a receiver sensitivity improvement of up to 1.73 dB as compared to IMDD OFDM. I also present two novel polarization analyzer based detection schemes, and study their performance using experiment and simulation. In the third implementation, I present an OFDM pilot-tone based scheme for distributed network control. The first instance of an SDN-based OFDM elastic optical network with pilot-tone assisted distributed control is demonstrated. An improvement in spectral efficiency and a fast reconfiguration time of 30 ms have been achieved in this experiment. Finally, I experimentally demonstrate optical re-timing of a 10.7 Gb/s data stream utilizing the property of bound soliton pairs (or "soliton molecules") to relax to an equilibrium temporal separation after propagation through a nonlinear dispersion alternating fiber span. Pulses offset up to 16 ps from bit center are successfully re-timed. The optical re-timing scheme studied here is a good example of signal processing in the optical domain and such a technique can overcome the bandwidth bottleneck present in DSP. An enhanced version of this re-timing scheme is analyzed using numerical simulations.

Broadband set-top box using MAP-CA processor

NASA Astrophysics Data System (ADS)

Bush, John E.; Lee, Woobin; Basoglu, Chris

2001-12-01

Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

Multichannel photonic Hilbert transformers based on complex modulated integrated Bragg gratings.

PubMed

Cheng, Rui; Chrostowski, Lukas

2018-03-01

Multichannel photonic Hilbert transformers (MPHTs) are reported. The devices are based on single compact spiral integrated Bragg gratings on silicon with coupling coefficients precisely modulated by the phase of each grating period. MPHTs with up to nine wavelength channels and a single-channel bandwidth of up to ∼625  GHz are achieved. The potential of the devices for multichannel single-sideband signal generation is suggested. The work offers a new possibility of utilizing wavelength as an extra degree of freedom in designing radio-frequency photonic signal processors. Such multichannel processors are expected to possess improved capacities and a potential to greatly benefit current widespread wavelength division multiplexed systems.

Expression of the bacterial type III effector DspA/E in Saccharomyces cerevisiae down-regulates the sphingolipid biosynthetic pathway leading to growth arrest.

PubMed

Siamer, Sabrina; Guillas, Isabelle; Shimobayashi, Mitsugu; Kunz, Caroline; Hall, Michael N; Barny, Marie-Anne

2014-06-27

Erwinia amylovora, the bacterium responsible for fire blight, relies on a type III secretion system and a single injected effector, DspA/E, to induce disease in host plants. DspA/E belongs to the widespread AvrE family of type III effectors that suppress plant defense responses and promote bacterial growth following infection. Ectopic expression of DspA/E in plant or in Saccharomyces cerevisiae is toxic, indicating that DspA/E likely targets a cellular process conserved between yeast and plant. To unravel the mode of action of DspA/E, we screened the Euroscarf S. cerevisiae library for mutants resistant to DspA/E-induced growth arrest. The most resistant mutants (Δsur4, Δfen1, Δipt1, Δskn1, Δcsg1, Δcsg2, Δorm1, and Δorm2) were impaired in the sphingolipid biosynthetic pathway. Exogenously supplied sphingolipid precursors such as the long chain bases (LCBs) phytosphingosine and dihydrosphingosine also suppressed the DspA/E-induced yeast growth defect. Expression of DspA/E in yeast down-regulated LCB biosynthesis and induced a rapid decrease in LCB levels, indicating that serine palmitoyltransferase (SPT), the first and rate-limiting enzyme of the sphingolipid biosynthetic pathway, was repressed. SPT down-regulation was mediated by dephosphorylation and activation of Orm proteins that negatively regulate SPT. A Δcdc55 mutation affecting Cdc55-PP2A protein phosphatase activity prevented Orm dephosphorylation and suppressed DspA/E-induced growth arrest. © 2014 by The American Society for Biochemistry and Molecular Biology, Inc.

Underwater optical communications using orbital angular momentum-based spatial division multiplexing

NASA Astrophysics Data System (ADS)

Willner, Alan E.; Zhao, Zhe; Ren, Yongxiong; Li, Long; Xie, Guodong; Song, Haoqian; Liu, Cong; Zhang, Runzhou; Bao, Changjing; Pang, Kai

2018-02-01

In this paper, we review high-capacity underwater optical communications using orbital angular momentum (OAM)-based spatial division multiplexing. We discuss methods to generate and detect blue-green optical data-carrying OAM beams as well as various underwater effects, including attenuation, scattering, current, and thermal gradients on OAM beams. Attention is also given to the system performance of high-capacity underwater optical communication links using OAM-based space division multiplexing. The paper closes with a discussion of a digital signal processing (DSP) algorithm to mitigate the inter-mode crosstalk caused by thermal gradients.

Hardware multiplier processor

DOEpatents

Pierce, Paul E.

1986-01-01

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Hardware multiplier processor

DOEpatents

Pierce, P.E.

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Automated digital magnetofluidics

NASA Astrophysics Data System (ADS)

Schneider, J.; Garcia, A. A.; Marquez, M.

2008-08-01

Drops can be moved in complex patterns on superhydrophobic surfaces using a reconfigured computer-controlled x-y metrology stage with a high degree of accuracy, flexibility, and reconfigurability. The stage employs a DMC-4030 controller which has a RISC-based, clock multiplying processor with DSP functions, accepting encoder inputs up to 22 MHz, provides servo update rates as high as 32 kHz, and processes commands at rates as fast as 40 milliseconds. A 6.35 mm diameter cylindrical NdFeB magnet is translated by the stage causing water drops to move by the action of induced magnetization of coated iron microspheres that remain in the drop and are attracted to the rare earth magnet through digital magnetofluidics. Water drops are easily moved in complex patterns in automated digital magnetofluidics at an average speed of 2.8 cm/s over a superhydrophobic polyethylene surface created by solvent casting. With additional components, some potential uses for this automated microfluidic system include characterization of superhydrophobic surfaces, water quality analysis, and medical diagnostics.

The mathematical theory of signal processing and compression-designs

NASA Astrophysics Data System (ADS)

Feria, Erlan H.

2006-05-01

The mathematical theory of signal processing, named processor coding, will be shown to inherently arise as the computational time dual of Shannon's mathematical theory of communication which is also known as source coding. Source coding is concerned with signal source memory space compression while processor coding deals with signal processor computational time compression. Their combination is named compression-designs and referred as Conde in short. A compelling and pedagogically appealing diagram will be discussed highlighting Conde's remarkable successful application to real-world knowledge-aided (KA) airborne moving target indicator (AMTI) radar.

The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance

NASA Astrophysics Data System (ADS)

Åsman, B.; Achenbach, R.; Allbrooke, B. M. M.; Anders, G.; Andrei, V.; Büscher, V.; Bansil, H. S.; Barnett, B. M.; Bauss, B.; Bendtz, K.; Bohm, C.; Bracinik, J.; Brawn, I. P.; Brock, R.; Buttinger, W.; Caputo, R.; Caughron, S.; Cerrito, L.; Charlton, D. G.; Childers, J. T.; Curtis, C. J.; Daniells, A. C.; Davis, A. O.; Davygora, Y.; Dorn, M.; Eckweiler, S.; Edmunds, D.; Edwards, J. P.; Eisenhandler, E.; Ellis, K.; Ermoline, Y.; Föhlisch, F.; Faulkner, P. J. W.; Fedorko, W.; Fleckner, J.; French, S. T.; Gee, C. N. P.; Gillman, A. R.; Goeringer, C.; Hülsing, T.; Hadley, D. R.; Hanke, P.; Hauser, R.; Heim, S.; Hellman, S.; Hickling, R. S.; Hidvégi, A.; Hillier, S. J.; Hofmann, J. I.; Hristova, I.; Ji, W.; Johansen, M.; Keller, M.; Khomich, A.; Kluge, E.-E.; Koll, J.; Laier, H.; Landon, M. P. J.; Lang, V. S.; Laurens, P.; Lepold, F.; Lilley, J. N.; Linnemann, J. T.; Müller, F.; Müller, T.; Mahboubi, K.; Martin, T. A.; Mass, A.; Meier, K.; Meyer, C.; Middleton, R. P.; Moa, T.; Moritz, S.; Morris, J. D.; Mudd, R. D.; Narayan, R.; zur Nedden, M.; Neusiedl, A.; Newman, P. R.; Nikiforov, A.; Ohm, C. C.; Perera, V. J. O.; Pfeiffer, U.; Plucinski, P.; Poddar, S.; Prieur, D. P. F.; Qian, W.; Rieck, P.; Rizvi, E.; Sankey, D. P. C.; Schäfer, U.; Scharf, V.; Schmitt, K.; Schröder, C.; Schultz-Coulon, H.-C.; Schumacher, C.; Schwienhorst, R.; Silverstein, S. B.; Simioni, E.; Snidero, G.; Staley, R. J.; Stamen, R.; Stock, P.; Stockton, M. C.; Tan, C. L. A.; Tapprogge, S.; Thomas, J. P.; Thompson, P. D.; Thomson, M.; True, P.; Watkins, P. M.; Watson, A. T.; Watson, M. F.; Weber, P.; Wessels, M.; Wiglesworth, C.; Williams, S. L.

2012-12-01

The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS first level trigger decision. This paper describes the architecture of the PreProcessor, its hardware realisation, functionality, and performance.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Smoke detection

DOEpatents

Warmack, Robert J. Bruce; Wolf, Dennis A.; Frank, Steven Shane

2016-09-06

Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDA training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.

Smoke detection

DOEpatents

Warmack, Robert J. Bruce; Wolf, Dennis A.; Frank, Steven Shane

2015-10-27

Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDA training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.

Digital Receiver Phase Meter

NASA Technical Reports Server (NTRS)

Marcin, Martin; Abramovici, Alexander

2008-01-01

The software of a commercially available digital radio receiver has been modified to make the receiver function as a two-channel low-noise phase meter. This phase meter is a prototype in the continuing development of a phase meter for a system in which radiofrequency (RF) signals in the two channels would be outputs of a spaceborne heterodyne laser interferometer for detecting gravitational waves. The frequencies of the signals could include a common Doppler-shift component of as much as 15 MHz. The phase meter is required to measure the relative phases of the signals in the two channels at a sampling rate of 10 Hz at a root power spectral density <5 microcycle/(Hz)1/2 and to be capable of determining the power spectral density of the phase difference over the frequency range from 1 mHz to 1 Hz. Such a phase meter could also be used on Earth to perform similar measurements in laser metrology of moving bodies. To illustrate part of the principle of operation of the phase meter, the figure includes a simplified block diagram of a basic singlechannel digital receiver. The input RF signal is first fed to the input terminal of an analog-to-digital converter (ADC). To prevent aliasing errors in the ADC, the sampling rate must be at least twice the input signal frequency. The sampling rate of the ADC is governed by a sampling clock, which also drives a digital local oscillator (DLO), which is a direct digital frequency synthesizer. The DLO produces samples of sine and cosine signals at a programmed tuning frequency. The sine and cosine samples are mixed with (that is, multiplied by) the samples from the ADC, then low-pass filtered to obtain in-phase (I) and quadrature (Q) signal components. A digital signal processor (DSP) computes the ratio between the Q and I components, computes the phase of the RF signal (relative to that of the DLO signal) as the arctangent of this ratio, and then averages successive such phase values over a time interval specified by the user.

A miniature on-chip multi-functional ECG signal processor with 30 µW ultra-low power consumption.

PubMed

Liu, Xin; Zheng, Yuan Jin; Phyu, Myint Wai; Zhao, Bin; Je, Minkyu; Yuan, Xiao Jun

2010-01-01

In this paper, a miniature low-power Electrocardiogram (ECG) signal processing application specific integrated circuit (ASIC) chip is proposed. This chip provides multiple critical functions for ECG analysis using a systematic wavelet transform algorithm and a novel SRAM-based ASIC architecture, while achieves low cost and high performance. Using 0.18 µm CMOS technology and 1 V power supply, this ASIC chip consumes only 29 µW and occupies an area of 3 mm(2). This on-chip ECG processor is highly suitable for reliable real-time cardiac status monitoring applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rey, D.; Ryan, W.; Ross, M.

A method for more efficiently utilizing the frequency bandwidth allocated for data transmission is presented. Current space and range communication systems use modulation and coding schemes that transmit 0.5 to 1.0 bits per second per Hertz of radio frequency bandwidth. The goal in this LDRD project is to increase the bandwidth utilization by employing advanced digital communications techniques. This is done with little or no increase in the transmit power which is usually very limited on airborne systems. Teaming with New Mexico State University, an implementation of trellis coded modulation (TCM), a coding and modulation scheme pioneered by Ungerboeck, wasmore » developed for this application and simulated on a computer. TCM provides a means for reliably transmitting data while simultaneously increasing bandwidth efficiency. The penalty is increased receiver complexity. In particular, the trellis decoder requires high-speed, application-specific digital signal processing (DSP) chips. A system solution based on the QualComm Viterbi decoder and the Graychip DSP receiver chips is presented.« less

Electro-optic voltage sensor with Multiple Beam Splitting

DOEpatents

Woods, Gregory K.; Renak, Todd W.; Crawford, Thomas M.; Davidson, James R.

2000-01-01

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages without use of the dedicated voltage dividing hardware. The invention achieves voltage measurement without significant error contributions from neighboring conductors or environmental perturbations. The invention employs a transmitter, a sensor, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor. Within the sensor the beam undergoes the Pockels electro-optic effect. The electro-optic effect produces a modulation of the beam's polarization, which is in turn converted to a pair of independent conversely-amplitude-modulated signals, from which the voltage of the E-field is determined by the signal processor. The use of converse AM signals enables the signal processor to better distinguish signal from noise. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Method and apparatus for combinatorial logic signal processor in a digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Zhou, Zhiquing

1999-01-01

A high speed, digitally based, signal processing system which accepts a digitized input signal and detects the presence of step-like pulses in the this data stream, extracts filtered estimates of their amplitudes, inspects for pulse pileup, and records input pulse rates and system livetime. The system has two parallel processing channels: a slow channel, which filters the data stream with a long time constant trapezoidal filter for good energy resolution; and a fast channel which filters the data stream with a short time constant trapezoidal filter, detects pulses, inspects for pileups, and captures peak values from the slow channel for good events. The presence of a simple digital interface allows the system to be easily integrated with a digital processor to produce accurate spectra at high count rates and allow all spectrometer functions to be fully automated. Because the method is digitally based, it allows pulses to be binned based on time related values, as well as on their amplitudes, if desired.

Design and implementation of new control room system in Damavand tokamak

NASA Astrophysics Data System (ADS)

Rasouli, H.; Zamanian, H.; Gheidi, M.; Kheiri-Fard, M.; Kouhi, A.

2017-07-01

The aim of this paper is design and implementation of an up-to-date control room. The previous control room had a lot of constraints and it was not apposite to the sophisticated diagnostic systems as well as to the modern control and multivariable systems. Although it provided the best output for the considered experiments and implementing offline algorithms among all similar plants, it needed to be developed to provide more capability for complex algorithm mechanisms and this work introduces our efforts in this area. Accordingly, four leading systems were designed and implemented, including real-time control system, online Data Acquisition System (DAS), offline DAS, monitoring and data transmission system. In the control system, three real-time control modules were established based on Digital Signal Processor (DSP). Thanks to them, implementation of the classic and linear and nonlinear intelligent controllers was possible to control the plasma position and its elongation. Also, online DAS was constructed in two modules. Using them, voltages and currents of charge for the capacitor banks and pressure of different parts in vacuum vessel were measured and monitored. Likewise, by real-time processing of the online data, the safety protocol of plant performance was accomplished. In addition, the offline DAS was organized in 13 modules based on Field Programmable Gate Array (FPGA). This system can be used for gathering all diagnostic, control, and performance data in 156 channels. Data transmission system and storing mechanism in the server was provided by data transmitting network and MDSplus standard protocol. Moreover, monitoring software was designed so that it could display the required plots for physical analyses. Taking everything into account, this new platform can improve the quality and quantity of research activities in plasma physics for Damavand tokamak.

Multi-Velocity Component LDV

NASA Technical Reports Server (NTRS)

Johnson, Dennis A. (Inventor)

1996-01-01

A laser doppler velocimeter uses frequency shifting of a laser beam to provide signal information for each velocity component. A composite electrical signal generated by a light detector is digitized and a processor produces a discrete Fourier transform based on the digitized electrical signal. The transform includes two peak frequencies corresponding to the two velocity components.

A Brain-Machine-Brain Interface for Rewiring of Cortical Circuitry after Traumatic Brain Injury

DTIC Science & Technology

2015-11-01

asymmetric biphasic current pulses up to ~100 A with passive discharge , and W-level digital signal processing 6 (DSP) unit for real-time SAR based on...compliance of 4.68 V with a 5 V supply, when configured for monophasic stimulation with passive discharge . The programmable microstimulator could also...severely disrupted. While the underlying white matter was intact, distortion of the most superficial aspects of the corona radiate was evident. In the

Interactive Computing and Graphics in Undergraduate Digital Signal Processing. Microcomputing Working Paper Series F 84-9.

ERIC Educational Resources Information Center

Onaral, Banu; And Others

This report describes the development of a Drexel University electrical and computer engineering course on digital filter design that used interactive computing and graphics, and was one of three courses in a senior-level sequence on digital signal processing (DSP). Interactive and digital analysis/design routines and the interconnection of these…

Teaching Earth Signals Analysis Using the Java-DSP Earth Systems Edition: Modern and Past Climate Change

ERIC Educational Resources Information Center

Ramamurthy, Karthikeyan Natesan; Hinnov, Linda A.; Spanias, Andreas S.

2014-01-01

Modern data collection in the Earth Sciences has propelled the need for understanding signal processing and time-series analysis techniques. However, there is an educational disconnect in the lack of instruction of time-series analysis techniques in many Earth Science academic departments. Furthermore, there are no platform-independent freeware…

Glycosaminoglycan chain of dentin sialoprotein proteoglycan.

PubMed

Zhu, Q; Sun, Y; Prasad, M; Wang, X; Yamoah, A K; Li, Y; Feng, J; Qin, C

2010-08-01

Dentin sialophosphoprotein (DSPP) is processed into dentin sialoprotein (DSP) and dentin phosphoprotein. A molecular variant of rat DSP, referred to as "HMW-DSP", has been speculated to be a proteoglycan form of DSP. To determine if HMW-DSP is the proteoglycan form of DSP and to identify the glycosaminoglycan side-chain attachment site(s), we further characterized HMW-DSP. Chondroitinase ABC treatment reduced the migration rate for portions of rat HMW-DSP to the level of DSP. Disaccharide analysis showed that rat HMW-DSP contains glycosaminoglycan chains made of chondroitin-4-sulfate and has an average of 31-32 disaccharides/mol. These observations confirmed that HMW-DSP is the proteoglycan form of DSP (renamed "DSP-PG"). Edman degradation and mass spectrometric analyses of tryptic peptides from rat DSP-PG, along with substitution analyses of candidate Ser residues in mouse DSPP, confirmed that 2 glycosaminoglycan chains are attached to Ser(241) and Ser(253) in the rat, or Ser(242) and Ser(254) in the mouse DSPP sequence.

Multitask neurovision processor with extensive feedback and feedforward connections

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1991-11-01

A multi-task neuro-vision parameter which performs a variety of information processing operations associated with the early stages of biological vision is presented. The network architecture of this neuro-vision processor, called the positive-negative (PN) neural processor, is loosely based on the neural activity fields exhibited by thalamic and cortical nervous tissue layers. The computational operation performed by the processor arises from the strength of the recurrent feedback among the numerous positive and negative neural computing units. By adjusting the feedback connections it is possible to generate diverse dynamic behavior that may be used for short-term visual memory (STVM), spatio-temporal filtering (STF), and pulse frequency modulation (PFM). The information attributes that are to be processes may be regulated by modifying the feedforward connections from the signal space to the neural processor.

Real-time Enhancement, Registration, and Fusion for an Enhanced Vision System

NASA Technical Reports Server (NTRS)

Hines, Glenn D.; Rahman, Zia-ur; Jobson, Daniel J.; Woodell, Glenn A.

2006-01-01

Over the last few years NASA Langley Research Center (LaRC) has been developing an Enhanced Vision System (EVS) to aid pilots while flying in poor visibility conditions. The EVS captures imagery using two infrared video cameras. The cameras are placed in an enclosure that is mounted and flown forward-looking underneath the NASA LaRC ARIES 757 aircraft. The data streams from the cameras are processed in real-time and displayed on monitors on-board the aircraft. With proper processing the camera system can provide better-than-human-observed imagery particularly during poor visibility conditions. However, to obtain this goal requires several different stages of processing including enhancement, registration, and fusion, and specialized processing hardware for real-time performance. We are using a real-time implementation of the Retinex algorithm for image enhancement, affine transformations for registration, and weighted sums to perform fusion. All of the algorithms are executed on a single TI DM642 digital signal processor (DSP) clocked at 720 MHz. The image processing components were added to the EVS system, tested, and demonstrated during flight tests in August and September of 2005. In this paper we briefly discuss the EVS image processing hardware and algorithms. We then discuss implementation issues and show examples of the results obtained during flight tests.

Academic performance in adolescents with delayed sleep phase.

PubMed

Sivertsen, Børge; Glozier, Nick; Harvey, Allison G; Hysing, Mari

2015-09-01

Delayed sleep phase (DSP) in adolescence has been linked to reduced academic performance, but there are few population-based studies examining this association using validated sleep measures and objective outcomes. The youth@hordaland-survey, a large population-based study from Norway conducted in 2012, surveyed 8347 high-school students aged 16-19 years (54% girls). DSP was assessed by self-report sleep measures, and it was operationalized according to the International Classification of Sleep Disorders - Second Edition. School performance (grade point average, GPA) was obtained from official administrative registries, and it was linked individually to health data. DSP was associated with increased odds for poor school performance. After adjusting for age and gender, DSP was associated with a threefold increased odds of poor GPA (lowest quartile) [odds ratio (OR) = 2.95; 95% confidence interval (CI): 2.03-4.30], and adjustment for sociodemographics and lifestyle factors did not, or only slightly, attenuate this association. Adjustment for nonattendance at school reduced the association substantially, and in the fully adjusted model, the effect of DSP on poor academic performance was reduced to a non-significant level. Mediation analyses confirmed both direct and significant indirect effects of DSP on school performance based on school absence, daytime sleepiness, and sleep duration. Poor academic performance may reflect an independent effect of underlying circadian disruption, which in part could be mediated by school attendance, as well as daytime sleepiness and short sleep duration. This suggests that careful assessment of sleep is warranted in addressing educational difficulties. Copyright © 2015 Elsevier B.V. All rights reserved.

Evidence Base Update for Autism Spectrum Disorder.

PubMed

Smith, Tristram; Iadarola, Suzannah

2015-01-01

This evidence base update examines the level of empirical support for interventions for children with autism spectrum disorder (ASD) younger than 5 years old. It focuses on research published since a previous review in this journal (Rogers & Vismara, 2008 ). We identified psychological or behavioral interventions that had been manualized and evaluated in either (a) experimental or quasi-experimental group studies or (b) systematic reviews of single-subject studies. We extracted data from all studies that met these criteria and were published after the previous review. Interventions were categorized across two dimensions. First, primary theoretical principles included applied behavior analysis (ABA), developmental social-pragmatic (DSP), or both. Second, practice elements included scope (comprehensive or focused), modality (individual intervention with the child, parent training, or classrooms), and intervention targets (e.g., spoken language or alternative and augmentative communication). We classified two interventions as well-established (individual, comprehensive ABA and teacher-implemented, focused ABA + DSP), 3 as probably efficacious (individual, focused ABA for augmentative and alternative communication; individual, focused ABA + DSP; and focused DSP parent training), and 5 as possibly efficacious (individual, comprehensive ABA + DSP; comprehensive ABA classrooms; focused ABA for spoken communication; focused ABA parent training; and teacher-implemented, focused DSP). The evidence base for ASD interventions has grown substantially since 2008. An increasing number of interventions have some empirical support; others are emerging as potentially efficacious. Priorities for future research include improving outcome measures, developing interventions for understudied ASD symptoms (e.g., repetitive behaviors), pinpointing mechanisms of action in interventions, and adapting interventions for implementation with fidelity by community providers.

Digital active material processing platform effort (DAMPER), SBIR phase 2

NASA Technical Reports Server (NTRS)

Blackburn, John; Smith, Dennis

1992-01-01

Applied Technology Associates, Inc., (ATA) has demonstrated that inertial actuation can be employed effectively in digital, active vibration isolation systems. Inertial actuation involves the use of momentum exchange to produce corrective forces which act directly on the payload being actively isolated. In a typical active vibration isolation system, accelerometers are used to measure the inertial motion of the payload. The signals from the accelerometers are then used to calculate the corrective forces required to counteract, or 'cancel out' the payload motion. Active vibration isolation is common technology, but the use of inertial actuation in such systems is novel, and is the focus of the DAMPER project. A May 1991 report was completed which documented the successful demonstration of inertial actuation, employed in the control of vibration in a single axis. In the 1 degree-of-freedom (1DOF) experiment a set of air bearing rails was used to suspend the payload, simulating a microgravity environment in a single horizontal axis. Digital Signal Processor (DSP) technology was used to calculate in real time, the control law between the accelerometer signals and the inertial actuators. The data obtained from this experiment verified that as much as 20 dB of rejection could be realized by this type of system. A discussion is included of recent tests performed in which vibrations were actively controlled in three axes simultaneously. In the three degree-of-freedom (3DOF) system, the air bearings were designed in such a way that the payload is free to rotate about the azimuth axis, as well as translate in the two horizontal directions. The actuator developed for the DAMPER project has applications beyond payload isolation, including structural damping and source vibration isolation. This report includes a brief discussion of these applications, as well as a commercialization plan for the actuator.

Digital active material processing platform effort (DAMPER), SBIR phase 2

NASA Astrophysics Data System (ADS)

Blackburn, John; Smith, Dennis

1992-11-01

Applied Technology Associates, Inc., (ATA) has demonstrated that inertial actuation can be employed effectively in digital, active vibration isolation systems. Inertial actuation involves the use of momentum exchange to produce corrective forces which act directly on the payload being actively isolated. In a typical active vibration isolation system, accelerometers are used to measure the inertial motion of the payload. The signals from the accelerometers are then used to calculate the corrective forces required to counteract, or 'cancel out' the payload motion. Active vibration isolation is common technology, but the use of inertial actuation in such systems is novel, and is the focus of the DAMPER project. A May 1991 report was completed which documented the successful demonstration of inertial actuation, employed in the control of vibration in a single axis. In the 1 degree-of-freedom (1DOF) experiment a set of air bearing rails was used to suspend the payload, simulating a microgravity environment in a single horizontal axis. Digital Signal Processor (DSP) technology was used to calculate in real time, the control law between the accelerometer signals and the inertial actuators. The data obtained from this experiment verified that as much as 20 dB of rejection could be realized by this type of system. A discussion is included of recent tests performed in which vibrations were actively controlled in three axes simultaneously. In the three degree-of-freedom (3DOF) system, the air bearings were designed in such a way that the payload is free to rotate about the azimuth axis, as well as translate in the two horizontal directions. The actuator developed for the DAMPER project has applications beyond payload isolation, including structural damping and source vibration isolation. This report includes a brief discussion of these applications, as well as a commercialization plan for the actuator.

Rapid Prototyping of High Performance Signal Processing Applications

NASA Astrophysics Data System (ADS)

Sane, Nimish

Advances in embedded systems for digital signal processing (DSP) are enabling many scientific projects and commercial applications. At the same time, these applications are key to driving advances in many important kinds of computing platforms. In this region of high performance DSP, rapid prototyping is critical for faster time-to-market (e.g., in the wireless communications industry) or time-to-science (e.g., in radio astronomy). DSP system architectures have evolved from being based on application specific integrated circuits (ASICs) to incorporate reconfigurable off-the-shelf field programmable gate arrays (FPGAs), the latest multiprocessors such as graphics processing units (GPUs), or heterogeneous combinations of such devices. We, thus, have a vast design space to explore based on performance trade-offs, and expanded by the multitude of possibilities for target platforms. In order to allow systematic design space exploration, and develop scalable and portable prototypes, model based design tools are increasingly used in design and implementation of embedded systems. These tools allow scalable high-level representations, model based semantics for analysis and optimization, and portable implementations that can be verified at higher levels of abstractions and targeted toward multiple platforms for implementation. The designer can experiment using such tools at an early stage in the design cycle, and employ the latest hardware at later stages. In this thesis, we have focused on dataflow-based approaches for rapid DSP system prototyping. This thesis contributes to various aspects of dataflow-based design flows and tools as follows: 1. We have introduced the concept of topological patterns, which exploits commonly found repetitive patterns in DSP algorithms to allow scalable, concise, and parameterizable representations of large scale dataflow graphs in high-level languages. We have shown how an underlying design tool can systematically exploit a high-level application specification consisting of topological patterns in various aspects of the design flow. 2. We have formulated the core functional dataflow (CFDF) model of computation, which can be used to model a wide variety of deterministic dynamic dataflow behaviors. We have also presented key features of the CFDF model and tools based on these features. These tools provide support for heterogeneous dataflow behaviors, an intuitive and common framework for functional specification, support for functional simulation, portability from several existing dataflow models to CFDF, integrated emphasis on minimally-restricted specification of actor functionality, and support for efficient static, quasi-static, and dynamic scheduling techniques. 3. We have developed a generalized scheduling technique for CFDF graphs based on decomposition of a CFDF graph into static graphs that interact at run-time. Furthermore, we have refined this generalized scheduling technique using a new notion of "mode grouping," which better exposes the underlying static behavior. We have also developed a scheduling technique for a class of dynamic applications that generates parameterized looped schedules (PLSs), which can handle dynamic dataflow behavior without major limitations on compile-time predictability. 4. We have demonstrated the use of dataflow-based approaches for design and implementation of radio astronomy DSP systems using an application example of a tunable digital downconverter (TDD) for spectrometers. Design and implementation of this module has been an integral part of this thesis work. This thesis demonstrates a design flow that consists of a high-level software prototype, analysis, and simulation using the dataflow interchange format (DIF) tool, and integration of this design with the existing tool flow for the target implementation on an FPGA platform, called interconnect break-out board (IBOB). We have also explored the trade-off between low hardware cost for fixed configurations of digital downconverters and flexibility offered by TDD designs. 5. This thesis has contributed significantly to the development and release of the latest version of a graph package oriented toward models of computation (MoCGraph). Our enhancements to this package include support for tree data structures, and generalized schedule trees (GSTs), which provide a useful data structure for a wide variety of schedule representations. Our extensions to the MoCGraph package provided key support for the CFDF model, and functional simulation capabilities in the DIF package.

A Bayesian sequential processor approach to spectroscopic portal system decisions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sale, K; Candy, J; Breitfeller, E

The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waitingmore » for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.« less

2-D Acousto-Optic Signal Processors for Simultaneous Spectrum Analysis and Direction Finding

DTIC Science & Technology

1990-11-01

National Dfense Defence nationale 2-D ACOUSTO - OPTIC SIGNAL PROCESSORS FOR SIMULTANEOUS SPECTRUM ANALYSIS 00 AND DIRECTION FINDING (U) by NM Jim P.Y...Wr pdft .1w I0~1111191 3 05089 National DIfense Defence nationale 2-D ACOUSTO - OPTIC SIGNAL PROCESSORS FOR SIMULTANEOUS SPECTRUM ANALYSIS AND DIRECTION...Processing, J.T. Tippet et al., Eds., Chapter 38, pp. 715-748, MIT Press, Cambridge 1965. [6] A.E. Spezio," Acousto - optics for Electronic Warfare

An autonomous receiver/digital signal processor applied to ground-based and rocket-borne wave experiments

NASA Astrophysics Data System (ADS)

Dombrowski, M. P.; LaBelle, J.; McGaw, D. G.; Broughton, M. C.

2016-07-01

The programmable combined receiver/digital signal processor platform presented in this article is designed for digital downsampling and processing of general waveform inputs with a 66 MHz initial sampling rate and multi-input synchronized sampling. Systems based on this platform are capable of fully autonomous low-power operation, can be programmed to preprocess and filter the data for preselection and reduction, and may output to a diverse array of transmission or telemetry media. We describe three versions of this system, one for deployment on sounding rockets and two for ground-based applications. The rocket system was flown on the Correlation of High-Frequency and Auroral Roar Measurements (CHARM)-II mission launched from Poker Flat Research Range, Alaska, in 2010. It measured auroral "roar" signals at 2.60 MHz. The ground-based systems have been deployed at Sondrestrom, Greenland, and South Pole Station, Antarctica. The Greenland system synchronously samples signals from three spaced antennas providing direction finding of 0-5 MHz waves. It has successfully measured auroral signals and man-made broadcast signals. The South Pole system synchronously samples signals from two crossed antennas, providing polarization information. It has successfully measured the polarization of auroral kilometric radiation-like signals as well as auroral hiss. Further systems are in development for future rocket missions and for installation in Antarctic Automatic Geophysical Observatories.

Fault tolerant, radiation hard, high performance digital signal processor

NASA Technical Reports Server (NTRS)

Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke

1990-01-01

An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

49 CFR 236.921 - Training and qualification program, general.

Code of Federal Regulations, 2010 CFR

2010-10-01

... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.921 Training and qualification program..., wayside, or onboard subsystems; (2) Persons who dispatch train operations (issue or communicate any...

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Glycosaminoglycan Chain of Dentin Sialoprotein Proteoglycan

PubMed Central

Zhu, Q.; Sun, Y.; Prasad, M.; Wang, X.; Yamoah, A.K.; Li, Y.; Feng, J.; Qin, C.

2010-01-01

Dentin sialophosphoprotein (DSPP) is processed into dentin sialoprotein (DSP) and dentin phosphoprotein. A molecular variant of rat DSP, referred to as “HMW-DSP”, has been speculated to be a proteoglycan form of DSP. To determine if HMW-DSP is the proteoglycan form of DSP and to identify the glycosaminoglycan side-chain attachment site(s), we further characterized HMW-DSP. Chondroitinase ABC treatment reduced the migration rate for portions of rat HMW-DSP to the level of DSP. Disaccharide analysis showed that rat HMW-DSP contains glycosaminoglycan chains made of chondroitin-4-sulfate and has an average of 31-32 disaccharides/mol. These observations confirmed that HMW-DSP is the proteoglycan form of DSP (renamed “DSP-PG”). Edman degradation and mass spectrometric analyses of tryptic peptides from rat DSP-PG, along with substitution analyses of candidate Ser residues in mouse DSPP, confirmed that 2 glycosaminoglycan chains are attached to Ser241 and Ser253 in the rat, or Ser242 and Ser254 in the mouse DSPP sequence. PMID:20400719

Signal Detection Theory-Based Information Processing for the Detection of Breast Cancer at Microwave Frequencies

DTIC Science & Technology

2002-08-01

the measurement noise, as well as the physical model of the forward scattered electric field. The Bayesian algorithms for the Uncertain Permittivity...received at multiple sensors. In this research project a tissue- model -based signal-detection theory approach for the detection of mammary tumors in the...oriented information processors. In this research project a tissue- model - based signal detection theory approach for the detection of mammary tumors in the

Colt: an experiment in wormhole run-time reconfiguration

NASA Astrophysics Data System (ADS)

Bittner, Ray; Athanas, Peter M.; Musgrove, Mark

1996-10-01

Wormhole run-time reconfiguration (RTR) is an attempt to create a refined computing paradigm for high performance computational tasks. By combining concepts from field programmable gate array (FPGA) technologies with data flow computing, the Colt/Stallion architecture achieves high utilization of hardware resources, and facilitates rapid run-time reconfiguration. Targeted mainly at DSP-type operations, the Colt integrated circuit -- a prototype wormhole RTR device -- compares favorably to contemporary DSP alternatives in terms of silicon area consumed per unit computation and in computing performance. Although emphasis has been placed on signal processing applications, general purpose computation has not been overlooked. Colt is a prototype that defines an architecture not only at the chip level but also in terms of an overall system design. As this system is realized, the concept of wormhole RTR will be applied to numerical computation and DSP applications including those common to image processing, communications systems, digital filters, acoustic processing, real-time control systems and simulation acceleration.

A low cost Doppler system for vascular dialysis access surveillance.

PubMed

Molina, P S C; Moraes, R; Baggio, J F R; Tognon, E A

2004-01-01

The National Kidney Foundation guidelines for vascular access recommend access surveillance to avoid morbidity among patients undergoing hemodialysis. Methods to detect access failure based on CW Doppler system are being proposed to implement surveillance programs at lower cost. This work describes a low cost Doppler system implemented in a PC notebook designed to carry out this task. A Doppler board samples the blood flow velocity and delivers demodulated quadrature Doppler signals. These signals are sampled by a notebook sound card. Software for Windows OS (running at the notebook) applies CFFT to consecutive 11.6 ms intervals of Doppler signals. The sonogram is presented on the screen in real time. The software also calculates the maximum and the intensity weighted mean frequency envelopes. Since similar systems employ DSP boards to process the Doppler signals, cost reduction was achieved. The Doppler board electronic circuits and routines to process the Doppler signals are presented.

A Real-Time Capable Software-Defined Receiver Using GPU for Adaptive Anti-Jam GPS Sensors

PubMed Central

Seo, Jiwon; Chen, Yu-Hsuan; De Lorenzo, David S.; Lo, Sherman; Enge, Per; Akos, Dennis; Lee, Jiyun

2011-01-01

Due to their weak received signal power, Global Positioning System (GPS) signals are vulnerable to radio frequency interference. Adaptive beam and null steering of the gain pattern of a GPS antenna array can significantly increase the resistance of GPS sensors to signal interference and jamming. Since adaptive array processing requires intensive computational power, beamsteering GPS receivers were usually implemented using hardware such as field-programmable gate arrays (FPGAs). However, a software implementation using general-purpose processors is much more desirable because of its flexibility and cost effectiveness. This paper presents a GPS software-defined radio (SDR) with adaptive beamsteering capability for anti-jam applications. The GPS SDR design is based on an optimized desktop parallel processing architecture using a quad-core Central Processing Unit (CPU) coupled with a new generation Graphics Processing Unit (GPU) having massively parallel processors. This GPS SDR demonstrates sufficient computational capability to support a four-element antenna array and future GPS L5 signal processing in real time. After providing the details of our design and optimization schemes for future GPU-based GPS SDR developments, the jamming resistance of our GPS SDR under synthetic wideband jamming is presented. Since the GPS SDR uses commercial-off-the-shelf hardware and processors, it can be easily adopted in civil GPS applications requiring anti-jam capabilities. PMID:22164116

A real-time capable software-defined receiver using GPU for adaptive anti-jam GPS sensors.

PubMed

Seo, Jiwon; Chen, Yu-Hsuan; De Lorenzo, David S; Lo, Sherman; Enge, Per; Akos, Dennis; Lee, Jiyun

2011-01-01

Due to their weak received signal power, Global Positioning System (GPS) signals are vulnerable to radio frequency interference. Adaptive beam and null steering of the gain pattern of a GPS antenna array can significantly increase the resistance of GPS sensors to signal interference and jamming. Since adaptive array processing requires intensive computational power, beamsteering GPS receivers were usually implemented using hardware such as field-programmable gate arrays (FPGAs). However, a software implementation using general-purpose processors is much more desirable because of its flexibility and cost effectiveness. This paper presents a GPS software-defined radio (SDR) with adaptive beamsteering capability for anti-jam applications. The GPS SDR design is based on an optimized desktop parallel processing architecture using a quad-core Central Processing Unit (CPU) coupled with a new generation Graphics Processing Unit (GPU) having massively parallel processors. This GPS SDR demonstrates sufficient computational capability to support a four-element antenna array and future GPS L5 signal processing in real time. After providing the details of our design and optimization schemes for future GPU-based GPS SDR developments, the jamming resistance of our GPS SDR under synthetic wideband jamming is presented. Since the GPS SDR uses commercial-off-the-shelf hardware and processors, it can be easily adopted in civil GPS applications requiring anti-jam capabilities.

Energy efficient sensor network implementations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Frigo, Janette R; Raby, Eric Y; Brennan, Sean M

In this paper, we discuss a low power embedded sensor node architecture we are developing for distributed sensor network systems deployed in a natural environment. In particular, we examine the sensor node for energy efficient processing-at-the-sensor. We analyze the following modes of operation; event detection, sleep(wake-up), data acquisition, data processing modes using low power, high performance embedded technology such as specialized embedded DSP processors and a low power FPGAs at the sensing node. We use compute intensive sensor node applications: an acoustic vehicle classifier (frequency domain analysis) and a video license plate identification application (learning algorithm) as a case study.more » We report performance and total energy usage for our system implementations and discuss the system architecture design trade offs.« less

New design environment for defect detection in web inspection systems

NASA Astrophysics Data System (ADS)

Hajimowlana, S. Hossain; Muscedere, Roberto; Jullien, Graham A.; Roberts, James W.

1997-09-01

One of the aims of industrial machine vision is to develop computer and electronic systems destined to replace human vision in the process of quality control of industrial production. In this paper we discuss the development of a new design environment developed for real-time defect detection using reconfigurable FPGA and DSP processor mounted inside a DALSA programmable CCD camera. The FPGA is directly connected to the video data-stream and outputs data to a low bandwidth output bus. The system is targeted for web inspection but has the potential for broader application areas. We describe and show test results of the prototype system board, mounted inside a DALSA camera and discuss some of the algorithms currently simulated and implemented for web inspection applications.

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

The Development of a Portable ECG Monitor Based on DSP

NASA Astrophysics Data System (ADS)

Nan, CHI Jian; Tao, YAN Yan; Meng Chen, LIU; Li, YANG

With the advent of global information, researches of Smart Home system are in the ascendant, the ECG real-time detection, and wireless transmission of ECG become more useful. In order to achieve the purpose we developed a portable ECG monitor which achieves the purpose of cardiac disease remote monitoring, and will be used in the physical and psychological disease surveillance in smart home system, we developed this portable ECG Monitor, based on the analysis of existing ECG Monitor, using TMS320F2812 as the core controller, which complete the signal collection, storage, processing, waveform display and transmission.

A method for compression of intra-cortically-recorded neural signals dedicated to implantable brain-machine interfaces.

PubMed

Shaeri, Mohammad Ali; Sodagar, Amir M

2015-05-01

This paper proposes an efficient data compression technique dedicated to implantable intra-cortical neural recording devices. The proposed technique benefits from processing neural signals in the Discrete Haar Wavelet Transform space, a new spike extraction approach, and a novel data framing scheme to telemeter the recorded neural information to the outside world. Based on the proposed technique, a 64-channel neural signal processor was designed and prototyped as a part of a wireless implantable extra-cellular neural recording microsystem. Designed in a 0.13- μ m standard CMOS process, the 64-channel neural signal processor reported in this paper occupies ∼ 0.206 mm(2) of silicon area, and consumes 94.18 μW when operating under a 1.2-V supply voltage at a master clock frequency of 1.28 MHz.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warmack, Robert J. Bruce; Wolf, Dennis A.; Frank, Steven Shane

Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDAmore » training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.« less

Digital signal processing in microwave radiometers

NASA Technical Reports Server (NTRS)

Lawrence, R. W.; Stanley, W. D.; Harrington, R. F.

1980-01-01

A microprocessor based digital signal processing unit has been proposed to replace analog sections of a microwave radiometer. A brief introduction to the radiometer system involved and a description of problems encountered in the use of digital techniques in radiometer design are discussed. An analysis of the digital signal processor as part of the radiometer is then presented.

Control apparatus and method for efficiently heating a fuel processor in a fuel cell system

DOEpatents

Doan, Tien M.; Clingerman, Bruce J.

2003-08-05

A control apparatus and method for efficiently controlling the amount of heat generated by a fuel cell processor in a fuel cell system by determining a temperature error between actual and desired fuel processor temperatures. The temperature error is converted to a combustor fuel injector command signal or a heat dump valve position command signal depending upon the type of temperature error. Logic controls are responsive to the combustor fuel injector command signals and the heat dump valve position command signal to prevent the combustor fuel injector command signal from being generated if the heat dump valve is opened or, alternately, from preventing the heat dump valve position command signal from being generated if the combustor fuel injector is opened.

Electro-optic voltage sensor with beam splitting

DOEpatents

Woods, Gregory K.; Renak, Todd W.; Davidson, James R.; Crawford, Thomas M.

2002-01-01

The invention is a miniature electro-optic voltage sensor system capable of accurate operation at high voltages without use of the dedicated voltage dividing hardware typically found in the prior art. The invention achieves voltage measurement without significant error contributions from neighboring conductors or environmental perturbations. The invention employs a transmitter, a sensor, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor. Within the sensor the beam undergoes the Pockels electro-optic effect. The electro-optic effect produces a modulation of the beam's polarization, which is in turn converted to a pair of independent conversely-amplitude-modulated signals, from which the voltage of the E-field is determined by the signal processor. The use of converse AM signals enables the signal processor to better distinguish signal from noise. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Adaptive control for accelerators

DOEpatents

Eaton, Lawrie E.; Jachim, Stephen P.; Natter, Eckard F.

1991-01-01

An adaptive feedforward control loop is provided to stabilize accelerator beam loading of the radio frequency field in an accelerator cavity during successive pulses of the beam into the cavity. A digital signal processor enables an adaptive algorithm to generate a feedforward error correcting signal functionally determined by the feedback error obtained by a beam pulse loading the cavity after the previous correcting signal was applied to the cavity. Each cavity feedforward correcting signal is successively stored in the digital processor and modified by the feedback error resulting from its application to generate the next feedforward error correcting signal. A feedforward error correcting signal is generated by the digital processor in advance of the beam pulse to enable a composite correcting signal and the beam pulse to arrive concurrently at the cavity.

A Fully Integrated Materials Framework for Enabling the Wireless Detection of Micro-defects in Aging and Battle-worn Structures

DTIC Science & Technology

2012-05-01

field-programmable gate array (FPGA) uses digital signal processing (DSP) algorithms to decode echo-location information from the backscattered signal ...characterizing and understanding of the physical properties of the BST and PZT thin films. Using microwave reflection spectroscopy, the complex...acoustic data, , would be encoded in the reflected MW signal by means of phase modulation (PM). By using high-Q resonators as the reactive

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2013 CFR

2013-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2014 CFR

2014-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2010 CFR

2010-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2012 CFR

2012-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

High-temperature optical fiber instrumentation for gas flow monitoring in gas turbine engines

NASA Astrophysics Data System (ADS)

Roberts, Adrian; May, Russell G.; Pickrell, Gary R.; Wang, Anbo

2002-02-01

In the design and testing of gas turbine engines, real-time data about such physical variables as temperature, pressure and acoustics are of critical importance. The high temperature environment experienced in the engines makes conventional electronic sensors devices difficult to apply. Therefore, there is a need for innovative sensors that can reliably operate under the high temperature conditions and with the desirable resolution and frequency response. A fiber optic high temperature sensor system for dynamic pressure measurement is presented in this paper. This sensor is based on a new sensor technology - the self-calibrated interferometric/intensity-based (SCIIB) sensor, recently developed at Virginia Tech. State-of-the-art digital signal processing (DSP) methods are applied to process the signal from the sensor to acquire high-speed frequency response.

Real time SAR processing

NASA Technical Reports Server (NTRS)

Premkumar, A. B.; Purviance, J. E.

1990-01-01

A simplified model for the SAR imaging problem is presented. The model is based on the geometry of the SAR system. Using this model an expression for the entire phase history of the received SAR signal is formulated. From the phase history, it is shown that the range and the azimuth coordinates for a point target image can be obtained by processing the phase information during the intrapulse and interpulse periods respectively. An architecture for a VLSI implementation for the SAR signal processor is presented which generates images in real time. The architecture uses a small number of chips, a new correlation processor, and an efficient azimuth correlation process.

Development of a compact and cost effective multi-input digital signal processing system

NASA Astrophysics Data System (ADS)

Darvish-Molla, Sahar; Chin, Kenrick; Prestwich, William V.; Byun, Soo Hyun

2018-01-01

A prototype digital signal processing system (DSP) was developed using a microcontroller interfaced with a 12-bit sampling ADC, which offers a considerably inexpensive solution for processing multiple detectors with high throughput. After digitization of the incoming pulses, in order to maximize the output counting rate, a simple algorithm was employed for pulse height analysis. Moreover, an algorithm aiming at the real-time pulse pile-up deconvolution was implemented. The system was tested using a NaI(Tl) detector in comparison with a traditional analogue and commercial digital systems for a variety of count rates. The performance of the prototype system was consistently superior to the analogue and the commercial digital systems up to the input count rate of 61 kcps while was slightly inferior to the commercial digital system but still superior to the analogue system in the higher input rates. Considering overall cost, size and flexibility, this custom made multi-input digital signal processing system (MMI-DSP) was the best reliable choice for the purpose of the 2D microdosimetric data collection, or for any measurement in which simultaneous multi-data collection is required.

Passive coherent location system simulation and evaluation

NASA Astrophysics Data System (ADS)

Slezák, Libor; Kvasnička, Michael; Pelant, Martin; Vávra, Jiř; Plšek, Radek

2006-02-01

Passive Coherent Location (PCL) is going to be important and perspective system of passive location of non cooperative and stealth targets. It works with the sources of irradiation of opportunity. PCL is intended to be a part of mobile Air Command and Control System (ACCS) as a Deployable ACCS Component (DAC). The company ERA works on PCL system parameters verification program by complete PCL simulator development since the year 2003. The Czech DoD takes financial participation on this program. The moving targets scenario, the RCS calculation by method of moment, ground clutter scattering and signal processing method (the bottle neck of the PCL) are available up to now in simulator tool. The digital signal (DSP) processing algorithms are performed both on simulated data and on real data measured at NATO C3 Agency in their Haag experiment. The Institute of Information Theory and Automation of the Academy of Sciences of the Czech Republic takes part on the implementation of the DSP algorithms in FPGA. The paper describes the simulator and signal processing structure and results both on simulated and measured data.

Real-time implementation of second generation of audio multilevel information coding

NASA Astrophysics Data System (ADS)

Ali, Murtaza; Tewfik, Ahmed H.; Viswanathan, V.

1994-03-01

This paper describes real-time implementation of a novel wavelet- based audio compression method. This method is based on the discrete wavelet (DWT) representation of signals. A bit allocation procedure is used to allocate bits to the transform coefficients in an adaptive fashion. The bit allocation procedure has been designed to take advantage of the masking effect in human hearing. The procedure minimizes the number of bits required to represent each frame of audio signals at a fixed distortion level. The real-time implementation provides almost transparent compression of monophonic CD quality audio signals (samples at 44.1 KHz and quantized using 16 bits/sample) at bit rates of 64-78 Kbits/sec. Our implementation uses two ASPI Elf boards, each of which is built around a TI TMS230C31 DSP chip. The time required for encoding of a mono CD signal is about 92 percent of real time and that for decoding about 61 percent.

Variable word length encoder reduces TV bandwith requirements

NASA Technical Reports Server (NTRS)

Sivertson, W. E., Jr.

1965-01-01

Adaptive variable resolution encoding technique provides an adaptive compression pseudo-random noise signal processor for reducing television bandwidth requirements. Complementary processors are required in both the transmitting and receiving systems. The pretransmission processor is analog-to-digital, while the postreception processor is digital-to-analog.

Feasibility study of a microprocessor based oculometer system

NASA Technical Reports Server (NTRS)

Varanasi, M. R.

1981-01-01

The elimination of redundancy in data to maximize processing speed and minimize storage requirements were objectives in a feasibility study of a microprocessor based oculometer system that would be portable in size and flexible in use. The appropriate architectural design of the signal processor, improved optics, and the reduction of size, weight, and power to the system were investigated. A flow chart is presented showing the strategy of the design. The simulation for developing microroutines for the high speed algorithmic processor subsystem is discussed as well as the Karhunen-Loeve transform technique for data compression.

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2013 CFR

2013-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2011 CFR

2011-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2012 CFR

2012-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2010 CFR

2010-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2014 CFR

2014-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.901 - Purpose and scope.

Code of Federal Regulations, 2010 CFR

2010-10-01

... control systems, subsystems, and components that are safety-critical products, as defined in § 236.903..., MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.901 Purpose and scope. (a) What is the purpose of this...

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.