Flexible single-crystal silicon nanomembrane photonic crystal cavity.

PubMed

Xu, Xiaochuan; Subbaraman, Harish; Chakravarty, Swapnajit; Hosseini, Amir; Covey, John; Yu, Yalin; Kwong, David; Zhang, Yang; Lai, Wei-Cheng; Zou, Yi; Lu, Nanshu; Chen, Ray T

2014-12-23

Flexible inorganic electronic devices promise numerous applications, especially in fields that could not be covered satisfactorily by conventional rigid devices. Benefits on a similar scale are also foreseeable for silicon photonic components. However, the difficulty in transferring intricate silicon photonic devices has deterred widespread development. In this paper, we demonstrate a flexible single-crystal silicon nanomembrane photonic crystal microcavity through a bonding and substrate removal approach. The transferred cavity shows a quality factor of 2.2×10(4) and could be bent to a curvature of 5 mm radius without deteriorating the performance compared to its counterparts on rigid substrates. A thorough characterization of the device reveals that the resonant wavelength is a linear function of the bending-induced strain. The device also shows a curvature-independent sensitivity to the ambient index variation.

Hybrid Integration of Solid-State Quantum Emitters on a Silicon Photonic Chip.

PubMed

Kim, Je-Hyung; Aghaeimeibodi, Shahriar; Richardson, Christopher J K; Leavitt, Richard P; Englund, Dirk; Waks, Edo

2017-12-13

Scalable quantum photonic systems require efficient single photon sources coupled to integrated photonic devices. Solid-state quantum emitters can generate single photons with high efficiency, while silicon photonic circuits can manipulate them in an integrated device structure. Combining these two material platforms could, therefore, significantly increase the complexity of integrated quantum photonic devices. Here, we demonstrate hybrid integration of solid-state quantum emitters to a silicon photonic device. We develop a pick-and-place technique that can position epitaxially grown InAs/InP quantum dots emitting at telecom wavelengths on a silicon photonic chip deterministically with nanoscale precision. We employ an adiabatic tapering approach to transfer the emission from the quantum dots to the waveguide with high efficiency. We also incorporate an on-chip silicon-photonic beamsplitter to perform a Hanbury-Brown and Twiss measurement. Our approach could enable integration of precharacterized III-V quantum photonic devices into large-scale photonic structures to enable complex devices composed of many emitters and photons.

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE PAGES

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine; ...

2016-08-01

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter, E-mail: johannes.seif@alumni.epfl.ch; Ballif, Christophe; De Wolf, Stefaan

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation ofmore » such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Silicon Carbide (SiC) Device and Module Reliability, Performance of a Loop Heat Pipe Subjected to a Phase-Coupled Heat Input to an Acceleration Field

DTIC Science & Technology

2016-05-01

AFRL-RQ-WP-TR-2016-0108 SILICON CARBIDE (SiC) DEVICE AND MODULE RELIABILITY Performance of a Loop Heat Pipe Subjected to a Phase-Coupled... Heat Input to an Acceleration Field Kirk L. Yerkes (AFRL/RQQI) and James D. Scofield (AFRL/RQQE) Flight Systems Integration Branch (AFRL/RQQI...CARBIDE (SiC) DEVICE AND MODULE RELIABILITY Performance of a Loop Heat Pipe Subjected to a Phase-Coupled Heat Input to an Acceleration Field 5a

Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

Optical interconnection networks for high-performance computing systems

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr; Bergman, Keren

2012-04-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

Silicon photonics for high-performance interconnection networks

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr

2011-12-01

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow.

R&D issues in scale-up and manufacturing of amorphous silicon tandem modules

NASA Astrophysics Data System (ADS)

Arya, R. R.; Carlson, D. E.; Chen, L. F.; Ganguly, G.; He, M.; Lin, G.; Middya, R.; Wood, G.; Newton, J.; Bennett, M.; Jackson, F.; Willing, F.

1999-03-01

R & D on amorphous silicon based tandem junction devices has improved the throughtput, the material utilization, and the performance of devices on commercial tin oxide coated glass. The tandem junction technology has been scaled-up to produce 8.6 Ft2 monolithically integrated modules in manufacturing at the TF1 plant. Optimization of performance and stability of these modules is ongoing.

Variable temperature performance of a fully screen printed transistor switch

NASA Astrophysics Data System (ADS)

Zambou, Serges; Magunje, Batsirai; Rhyme, Setshedi; Walton, Stanley D.; Idowu, M. Florence; Unuigbe, David; Britton, David T.; Härting, Margit

2016-12-01

This article reports on the variable temperature performance of a flexible printed transistor which works as a current driven switch. In this work, electronic ink is formulated from nanostructured silicon produced by milling polycrystalline silicon. The study of the silicon active layer shows that its conductivity is based on thermal activation of carriers, and could be used as active layers in active devices. We further report on the transistors switching operation and their electrical performance under variable temperature. The reliability of the transistors at constant current bias was also investigated. Analysis of the electrical transfer characteristics from 340 to 10 K showed that the printed devices' current ON/OFF ratio increases as temperature decreases making it a better switch at lower temperatures. A constant current bias on a terminal for up to six hours shows extraordinary stability in electrical performance of the device.

Hybrid Silicon Nanocrystal/Poly(3-hexylthiophene-2,5-diyl) Solar Cells from a Chlorinated Silicon Precursor

NASA Astrophysics Data System (ADS)

Ding, Yi; Gresback, Ryan; Yamada, Riku; Okazaki, Ken; Nozaki, Tomohiro

2013-11-01

Freestanding silicon nanocrystals (Si NCs) synthesized by a nonthermal plasma from silicon tetrachloride (SiCl4) were successfully employed in hybrid Si NC/poly(3-hexylthiophene-2,5-diyl) (P3HT) bulk-hetrojunction (BHJ) solar cells. The weight fraction of Si NCs in P3HT greatly influences device performance. As the weight fraction increases up to 50 wt %, short-circuit current dramatically increases, while open-circuit voltage (Voc) and fill factor (FF) do not change significantly. The improvement in device performance is attributed to both increased probability of exciton dissociation in P3HT and an enhancement in the light conversion of wavelengths where P3HT is a poor absorber. These results demonstrate an alternative approach to synthesizing Si NCs from SiCl4 instead of silane (SiH4) for optoelectronic devices.

Silicon Carbide Technology

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2006-01-01

Silicon carbide based semiconductor electronic devices and circuits are presently being developed for use in high-temperature, high-power, and high-radiation conditions under which conventional semiconductors cannot adequately perform. Silicon carbide's ability to function under such extreme conditions is expected to enable significant improvements to a far-ranging variety of applications and systems. These range from greatly improved high-voltage switching for energy savings in public electric power distribution and electric motor drives to more powerful microwave electronics for radar and communications to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC power MOSFET's and diode rectifiers would operate over higher voltage and temperature ranges, have superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly rated silicon-based devices [8]. However, these tremendous theoretical advantages have yet to be widely realized in commercially available SiC devices, primarily owing to the fact that SiC's relatively immature crystal growth and device fabrication technologies are not yet sufficiently developed to the degree required for reliable incorporation into most electronic systems. This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences (both good and bad) between SiC electronics technology and the well-known silicon VLSI technology are highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale applications. Key crystal growth and device-fabrication issues that presently limit the performance and capability of high-temperature and high-power SiC electronics are identified.

Inverse design engineering of all-silicon polarization beam splitters

NASA Astrophysics Data System (ADS)

Frandsen, Lars H.; Sigmund, Ole

2016-03-01

Utilizing the inverse design engineering method of topology optimization, we have realized high-performing all-silicon ultra-compact polarization beam splitters. We show that the device footprint of the polarization beam splitter can be as compact as ~2 μm2 while performing experimentally with a polarization splitting loss lower than ~0.82 dB and an extinction ratio larger than ~15 dB in the C-band. We investigate the device performance as a function of the device length and find a lower length above which the performance only increases incrementally. Imposing a minimum feature size constraint in the optimization is shown to affect the performance negatively and reveals the necessity for light to scatter on a sub-wavelength scale to obtain functionalities in compact photonic devices.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications - SiC, GaN, Ga2O3, and Diamond.

PubMed

Wellmann, Peter J

2017-11-17

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications – SiC, GaN, Ga2O3, and Diamond

PubMed Central

2017-01-01

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies. PMID:29200530

Silicon Carbide Diodes Performance Characterization at High Temperatures

NASA Technical Reports Server (NTRS)

Lebron-Velilla, Ramon C.; Schwarze, Gene E.; Gardner, Brent G.; Adams, Jerry

2004-01-01

NASA Glenn Research center's Electrical Systems Development branch is working to demonstrate and test the advantages of Silicon Carbide (SiC) devices in actual power electronics applications. The first step in this pursuit is to obtain commercially available SiC Schottky diodes and to individually test them under both static and dynamic conditions, and then compare them with current state of the art silicon Schottky and ultra fast p-n diodes of similar voltage and current ratings. This presentation covers the results of electrical tests performed at NASA Glenn. Steady state forward and reverse current-volt (I-V) curves were generated for each device to compare performance and to measure their forward voltage drop at rated current, as well as the reverse leakage current at rated voltage. In addition, the devices were individually connected as freewheeling diodes in a Buck (step down) DC to DC converter to test their reverse recovery characteristics and compare their transient performance in a typical converter application. Both static and transient characterization tests were performed at temperatures ranging from 25 C to 300 C, in order to test and demonstrate the advantages of SiC over Silicon at high temperatures.

Review Application of Nanostructured Black Silicon

NASA Astrophysics Data System (ADS)

Lv, Jian; Zhang, Ting; Zhang, Peng; Zhao, Yingchun; Li, Shibin

2018-04-01

As a widely used semiconductor material, silicon has been extensively used in many areas, such as photodiode, photodetector, and photovoltaic devices. However, the high surface reflectance and large bandgap of traditional bulk silicon restrict the full use of the spectrum. To solve this problem, many methods have been developed. Among them, the surface nanostructured silicon, namely black silicon, is the most efficient and widely used. Due to its high absorption in the wide range from UV-visible to infrared, black silicon is very attractive for using as sensitive layer of photodiodes, photodetector, solar cells, field emission, luminescence, and other photoelectric devices. Intensive study has been performed to understand the enhanced absorption of black silicon as well as the response extended to infrared spectrum range. In this paper, the application of black silicon is systematically reviewed. The limitations and challenges of black silicon material are also discussed. This article will provide a meaningful introduction to black silicon and its unique properties.

High-sensitivity silicon nanowire phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Dan, Yaping

2014-08-01

Silicon nanowires (SiNWs) have emerged as a promising material for high-sensitivity photodetection in the UV, visible and near-infrared spectral ranges. In this work, we demonstrate novel planar SiNW phototransistors on silicon-oninsulator (SOI) substrate using CMOS-compatible processes. The device consists of a bipolar transistor structure with an optically-injected base region. The electronic and optical properties of the SiNW phototransistors are investigated. Preliminary simulation and experimental results show that nanowire geometry, doping densities and surface states have considerable effects on the device performance, and that a device with optimized parameters can potentially outperform conventional Si photodetectors.

Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Gu, Jian

This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at pattern center is observed due to substrate enhanced edge heating. Single-grain silicon is obtained in a 50 nm x 100 nm rectangular pattern by super lateral growth (SLG). Narrow lines (such as 20-nm-wide) can serve as artificial heterogeneous nucleation sites during crystallization of large patterns, which could lead to the formation of single-crystal silicon islands in a controlled fashion. In addition to eximer laser annealing, NanoPAtterning and nickel-induced lateral C&barbelow;rystallization (NanoPAC) of a-Si lines is presented. Single-crystal silicon is achieved by NanoPAC. The line width of a-Si affects the grain structure of crystallized silicon lines significantly. Statistics show that single-crystal silicon is formed for all lines with width between 50 nm to 200 nm. Using in situ transmission electron microscopy (TEM), nickel-induced lateral crystallization (Ni-ILC) of a-Si inside a pattern is revealed; lithography-constrained single seeding (LISS) is proposed to explain the single-crystal formation. Intragrain line and two-dimensional defects are also studied. To test the electrical properties of NanoPAC silicon films, sub-100 nm thin-film transistors (TFTs) are fabricated using Patten-controlled crystallization of Ṯhin a-Si channel layer and H&barbelow;igh temperature (850°C) annealing, coined PaTH process. PaTH TFTs show excellent device performance over traditional solid phase crystallized (SPC) TFTs in terms of threshold voltage, threshold voltage roll-off, leakage current, subthreshold swing, on/off current ratio, device-to-device uniformity etc. Two-dimensional device simulations show that PaTH TFTs are comparable to silicon-on-insulator (SOI) devices, making it a promising candidate for the fabrication of future high performance, low-power 3D integrated circuits. Finally, an ultrafast nanolithography technique, laser-assisted direct imprint (LADI) is introduced. LADI shows the ability of patterning nanostructures directly in silicon in nanoseconds with sub-10 nm resolution. The process has potential applications in multiple disciplines, and could be extended to other materials and processes.

Infrared charge-injection-device array performance at low background

NASA Technical Reports Server (NTRS)

Mccreight, C. R.; Goebel, J. H.

1981-01-01

Low-background tests of a 1 x 32 Si:Bi charge-injection-device (CID) IR detector are carried out to evaluate its feasibility for space-based astronomical observations. Optimum performance is obtained at a temperature of 11 K. The sensitivity is found to compare well with that of discrete extrinsic silicon photoconductors. The measured sensitivity and the apparent absence of anomalous effects make extrinsic silicon CID arrays very promising for astronomical applications.

R&D issues in scale-up and manufacturing of amorphous silicon tandem modules

DOE Office of Scientific and Technical Information (OSTI.GOV)

Arya, R.R.; Carlson, D.E.; Chen, L.F.

1999-03-01

R & D on amorphous silicon based tandem junction devices has improved the throughtput, the material utilization, and the performance of devices on commercial tin oxide coated glass. The tandem junction technology has been scaled-up to produce 8.6&hthinsp;Ft{sup 2} monolithically integrated modules in manufacturing at the TF1 plant. Optimization of performance and stability of these modules is ongoing. {copyright} {ital 1999 American Institute of Physics.}

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Inkjet 3D printing of UV and thermal cure silicone elastomers for dielectric elastomer actuators

NASA Astrophysics Data System (ADS)

McCoul, David; Rosset, Samuel; Schlatter, Samuel; Shea, Herbert

2017-12-01

Dielectric elastomer actuators (DEAs) are an attractive form of electromechanical transducer, possessing high energy densities, an efficient design, mechanical compliance, high speed, and noiseless operation. They have been incorporated into a wide variety of devices, such as microfluidic systems, cell bioreactors, tunable optics, haptic displays, and actuators for soft robotics. Fabrication of DEA devices is complex, and the majority are inefficiently made by hand. 3D printing offers an automated and flexible manufacturing alternative that can fabricate complex, multi-material, integrated devices consistently and in high resolution. We present a novel additive manufacturing approach to DEA devices in which five commercially available, thermal and UV-cure DEA silicone rubber materials have been 3D printed with a drop-on-demand, piezoelectric inkjet system. Using this process, 3D structures and high-quality silicone dielectric elastomer membranes as thin as 2 μm have been printed that exhibit mechanical and actuation performance at least as good as conventionally blade-cast membranes. Printed silicone membranes exhibited maximum tensile strains of up to 727%, and DEAs with printed silicone dielectrics were actuated up to 6.1% area strain at a breakdown strength of 84 V μm-1 and also up to 130 V μm-1 at 2.4% strain. This approach holds great potential to manufacture reliable, high-performance DEA devices with high throughput.

Atomic Scale Understanding of Poly-Si/SiO2/c-Si Passivated Contacts: Passivation Degradation Due to Metallization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aguiar, Jeffery A.; Young, David; Lee, Benjamin

2016-11-21

The key attributes for achieving high efficiency crystalline silicon solar cells include class leading developments in the ability to approach the theoretical limits of silicon solar technology (29.4% efficiency). The push for high efficiency devices is further compounded with the clear need for passivation to reduce recombination at the metal contacts. At the same time there is stringent requirement to retain the same material device quality, surface passivation, and performance characteristics following subsequent processing. The development of passivated silicon cell structures that retain active front and rear surface passivation and overall material cell quality is therefore a relevant and activemore » area of development. To address the potential outcomes of metallization on passivated silicon stack, we report on some common microstructural features of degradation due to metallization for a series of silicon device stacks. A fundamental materials understanding of the metallization process on retaining high-efficiency passivated Si devices is therefore gained over these series of results.« less

Materials and processing approaches for foundry-compatible transient electronics.

PubMed

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A; Song, Enming; Yu, Xinge; Rogers, John A

2017-07-11

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for "green" electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are ( i ) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, ( ii ) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and ( iii ) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Materials and processing approaches for foundry-compatible transient electronics

NASA Astrophysics Data System (ADS)

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-07-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

A two-axis micromachined silicon actuator with micrometer range electrostatic actuation and picometer sensitive capacitive detection

NASA Astrophysics Data System (ADS)

Ayela, F.; Bret, J. L.; Chaussy, J.; Fournier, T.; Ménégaz, E.

2000-05-01

This article presents an innovative micromachined silicon actuator. A 50-μm-thick silicon foil is anodically bonded onto a broached Pyrex substrate. A free standing membrane and four coplanar electrodes in close proximity are then lithographied and etched. The use of phosphorus doped silicon with low electrical resistivity allows the application of an electrostatic force between one electrode and the moving diaphragm. This plane displacement and the induced interelectrode variation are capacitively detected. Due to the very low electrical resistivity of the doped silicon, there is no need to metallize the vertical trenches of the device. No piezoelectric transducer takes place so that the mechanical device is free from any hysteretic or temperature dependance. The range of the possible actuation along the x and y axis is around 5 μm. The actual sensitivity is xn=0.54 Å/Hz1/2 and yn=0.14 Å/Hz1/2. The microengineering steps and the electronic setup devoted to design the actuator and to perform relative capacitive measurements ΔC/C=10-6 from an initial value C≈10-13 F are described. The elaborated tests and performances of the device are presented. As a conclusion, some experimental projects using this subnanometric sensitive device are mentioned.

Heterogeneously integrated silicon photonics for the mid-infrared and spectroscopic sensing.

PubMed

Chen, Yu; Lin, Hongtao; Hu, Juejun; Li, Mo

2014-07-22

Besides being the foundational material for microelectronics, crystalline silicon has long been used for the production of infrared lenses and mirrors. More recently, silicon has become the key material to achieve large-scale integration of photonic devices for on-chip optical interconnect and signal processing. For optics, silicon has significant advantages: it offers a very high refractive index and is highly transparent in the spectral range from 1.2 to 8 μm. To fully exploit silicon’s superior performance in a remarkably broad range and to enable new optoelectronic functionalities, here we describe a general method to integrate silicon photonic devices on arbitrary foreign substrates. In particular, we apply the technique to integrate silicon microring resonators on mid-infrared compatible substrates for operation in the mid-infrared. These high-performance mid-infrared optical resonators are utilized to demonstrate, for the first time, on-chip cavity-enhanced mid-infrared spectroscopic analysis of organic chemicals with a limit of detection of less than 0.1 ng.

Small area silicon diffused junction X-ray detectors

NASA Technical Reports Server (NTRS)

Walton, J. T.; Pehl, R. H.; Larsh, A. E.

1982-01-01

The low-temperature performance of silicon diffused junction detectors in the measurement of low energy X-rays is reported. The detectors have an area of 0.04 sq cm and a thickness of 100 microns. The spectral resolutions of these detectors were found to be in close agreement with expected values, indicating that the defects introduced by the high-temperature processing required in the device fabrication were not deleteriously affecting the detection of low-energy X-rays. Device performance over a temperature range of 77 K to 150 K is given. These detectors were designed to detect low-energy X-rays in the presence of minimum ionizing electrons. The successful application of silicon-diffused junction technology to X-ray detector fabrication may facilitate the development of other novel silicon X-ray detector designs.

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

Plastic-Syringe Induced Silicone Contamination in Organic Photvoltaic Fabrication: Implications for Small-Volume Additives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carr, John A.; Nalwa, Kanwar S.; Mahadevapuram, Rakesh

Herein, the implications of silicone contamination found in solution-processed conjugated polymer solar cells are explored. Similar to a previous work based on molecular cells, we find this contamination as a result of the use of plastic syringes during fabrication. However, in contrast to the molecular case, we find that glass-syringe fabricated devices give superior performance than plastic-syringe fabricated devices in poly(3-hexylthiophene)-based cells. We find that the unintentional silicone addition alters the solution’s wettability, which translates to a thinner, less absorbent film on spinning. With many groups studying the effects of small-volume additives, this work should be closely considered as manymore » of these additives may also directly alter the solutions’ wettability, or the amount of silicone dissolved off the plastic syringes, or both. Thereby, film thickness, which generally is not reported in detail, can vary significantly from device to device.« less

Sinusoidal nanotextures for light management in silicon thin-film solar cells.

PubMed

Köppel, G; Rech, B; Becker, C

2016-04-28

Recent progresses in liquid phase crystallization enabled the fabrication of thin wafer quality crystalline silicon layers on low-cost glass substrates enabling conversion efficiencies up to 12.1%. Because of its indirect band gap, a thin silicon absorber layer demands for efficient measures for light management. However, the combination of high quality crystalline silicon and light trapping structures is still a critical issue. Here, we implement hexagonal 750 nm pitched sinusoidal and pillar shaped nanostructures at the sun-facing glass-silicon interface into 10 μm thin liquid phase crystallized silicon thin-film solar cell devices on glass. Both structures are experimentally studied regarding their optical and optoelectronic properties. Reflection losses are reduced over the entire wavelength range outperforming state of the art anti-reflective planar layer systems. In case of the smooth sinusoidal nanostructures these optical achievements are accompanied by an excellent electronic material quality of the silicon absorber layer enabling open circuit voltages above 600 mV and solar cell device performances comparable to the planar reference device. For wavelengths smaller than 400 nm and higher than 700 nm optical achievements are translated into an enhanced quantum efficiency of the solar cell devices. Therefore, sinusoidal nanotextures are a well-balanced compromise between optical enhancement and maintained high electronic silicon material quality which opens a promising route for future optimizations in solar cell designs for silicon thin-film solar cells on glass.

Nonlinear silicon photonics

NASA Astrophysics Data System (ADS)

Borghi, M.; Castellan, C.; Signorini, S.; Trenti, A.; Pavesi, L.

2017-09-01

Silicon photonics is a technology based on fabricating integrated optical circuits by using the same paradigms as the dominant electronics industry. After twenty years of fervid development, silicon photonics is entering the market with low cost, high performance and mass-manufacturable optical devices. Until now, most silicon photonic devices have been based on linear optical effects, despite the many phenomenologies associated with nonlinear optics in both bulk materials and integrated waveguides. Silicon and silicon-based materials have strong optical nonlinearities which are enhanced in integrated devices by the small cross-section of the high-index contrast silicon waveguides or photonic crystals. Here the photons are made to strongly interact with the medium where they propagate. This is the central argument of nonlinear silicon photonics. It is the aim of this review to describe the state-of-the-art in the field. Starting from the basic nonlinearities in a silicon waveguide or in optical resonator geometries, many phenomena and applications are described—including frequency generation, frequency conversion, frequency-comb generation, supercontinuum generation, soliton formation, temporal imaging and time lensing, Raman lasing, and comb spectroscopy. Emerging quantum photonics applications, such as entangled photon sources, heralded single-photon sources and integrated quantum photonic circuits are also addressed at the end of this review.

Heavily Boron-Doped Silicon Layer for the Fabrication of Nanoscale Thermoelectric Devices

PubMed Central

Liu, Yang; Deng, Lingxiao; Zhang, Mingliang; Zhang, Shuyuan; Ma, Jing; Song, Peishuai; Liu, Qing; Ji, An; Yang, Fuhua; Wang, Xiaodong

2018-01-01

Heavily boron-doped silicon layers and boron etch-stop techniques have been widely used in the fabrication of microelectromechanical systems (MEMS). This paper provides an introduction to the fabrication process of nanoscale silicon thermoelectric devices. Low-dimensional structures such as silicon nanowire (SiNW) have been considered as a promising alternative for thermoelectric applications in order to achieve a higher thermoelectric figure of merit (ZT) than bulk silicon. Here, heavily boron-doped silicon layers and boron etch-stop processes for the fabrication of suspended SiNWs will be discussed in detail, including boron diffusion, electron beam lithography, inductively coupled plasma (ICP) etching and tetramethylammonium hydroxide (TMAH) etch-stop processes. A 7 μm long nanowire structure with a height of 280 nm and a width of 55 nm was achieved, indicating that the proposed technique is useful for nanoscale fabrication. Furthermore, a SiNW thermoelectric device has also been demonstrated, and its performance shows an obvious reduction in thermal conductivity. PMID:29385759

Influence of deep defects on device performance of thin-film polycrystalline silicon solar cells

NASA Astrophysics Data System (ADS)

Fehr, M.; Simon, P.; Sontheimer, T.; Leendertz, C.; Gorka, B.; Schnegg, A.; Rech, B.; Lips, K.

2012-09-01

Employing quantitative electron-paramagnetic resonance analysis and numerical simulations, we investigate the performance of thin-film polycrystalline silicon solar cells as a function of defect density. We find that the open-circuit voltage is correlated to the density of defects, which we assign to coordination defects at grain boundaries and in dislocation cores. Numerical device simulations confirm the observed correlation and indicate that the device performance is limited by deep defects in the absorber bulk. Analyzing the defect density as a function of grain size indicates a high concentration of intra-grain defects. For large grains (>2 μm), we find that intra-grain defects dominate over grain boundary defects and limit the solar cell performance.

Light-emitting diodes based on colloidal silicon quantum dots

NASA Astrophysics Data System (ADS)

Zhao, Shuangyi; Liu, Xiangkai; Pi, Xiaodong; Yang, Deren

2018-06-01

Colloidal silicon quantum dots (Si QDs) hold great promise for the development of printed Si electronics. Given their novel electronic and optical properties, colloidal Si QDs have been intensively investigated for optoelectronic applications. Among all kinds of optoelectronic devices based on colloidal Si QDs, QD light-emitting diodes (LEDs) play an important role. It is encouraging that the performance of LEDs based on colloidal Si QDs has been significantly increasing in the past decade. In this review, we discuss the effects of the QD size, QD surface and device structure on the performance of colloidal Si-QD LEDs. The outlook on the further optimization of the device performance is presented at the end.

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

PubMed Central

Makey, Ghaith; Elahi, Parviz; Çolakoğlu, Tahir; Ergeçen, Emre; Yavuz, Özgün; Hübner, René; Borra, Mona Zolfaghari; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ömer

2017-01-01

Silicon is an excellent material for microelectronics and integrated photonics1–3 with untapped potential for mid-IR optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realised with techniques like reactive ion etching. Embedded optical elements, like in glass7, electronic devices, and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1 µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has a different optical index than unmodified parts, which enables numerous photonic devices. Optionally, these parts are chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface, i.e., “in-chip” microstructures for microfluidic cooling of chips, vias, MEMS, photovoltaic applications and photonic devices that match or surpass the corresponding state-of-the-art device performances. PMID:28983323

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

NASA Astrophysics Data System (ADS)

Tokel, Onur; Turnalı, Ahmet; Makey, Ghaith; Elahi, Parviz; ćolakoǧlu, Tahir; Ergeçen, Emre; Yavuz, Ã.-zgün; Hübner, René; Zolfaghari Borra, Mona; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ã.-mer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3, with untapped potential for mid-infrared optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow the fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realized with techniques like reactive ion etching. Embedded optical elements7, electronic devices and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1-µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has an optical index different to that in unmodified parts, enabling the creation of numerous photonic devices. Optionally, these parts can be chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface—that is, `in-chip'—microstructures for microfluidic cooling of chips, vias, micro-electro-mechanical systems, photovoltaic applications and photonic devices that match or surpass corresponding state-of-the-art device performances.

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

SiC Technology

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

1998-01-01

Silicon carbide (SiC)-based semiconductor electronic devices and circuits are presently being developed for use in high-temperature, high-power, and/or high-radiation conditions under which conventional semiconductors cannot adequately perform. Silicon carbide's ability to function under such extreme conditions is expected to enable significant improvements to a far-ranging variety of applications and systems. These range from greatly improved high-voltage switching [1- 4] for energy savings in public electric power distribution and electric motor drives to more powerful microwave electronics for radar and communications [5-7] to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC power MOSFET's and diode rectifiers would operate over higher voltage and temperature ranges, have superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly rated silicon-based devices [8]. However, these tremendous theoretical advantages have yet to be realized in experimental SiC devices, primarily due to the fact that SiC's relatively immature crystal growth and device fabrication technologies are not yet sufficiently developed to the degree required for reliable incorporation into most electronic systems [9]. This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences (both good and bad) between SiC electronics technology and well-known silicon VLSI technology are highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale applications. Key crystal growth and device-fabrication issues that presently limit the performance and capability of high temperature and/or high power SiC electronics are identified.

Core-shell heterojunction of silicon nanowire arrays and carbon quantum dots for photovoltaic devices and self-driven photodetectors.

PubMed

Xie, Chao; Nie, Biao; Zeng, Longhui; Liang, Feng-Xia; Wang, Ming-Zheng; Luo, Linbao; Feng, Mei; Yu, Yongqiang; Wu, Chun-Yan; Wu, Yucheng; Yu, Shu-Hong

2014-04-22

Silicon nanostructure-based solar cells have lately intrigued intensive interest because of their promising potential in next-generation solar energy conversion devices. Herein, we report a silicon nanowire (SiNW) array/carbon quantum dot (CQD) core-shell heterojunction photovoltaic device by directly coating Ag-assisted chemical-etched SiNW arrays with CQDs. The heterojunction with a barrier height of 0.75 eV exhibited excellent rectifying behavior with a rectification ratio of 10(3) at ±0.8 V in the dark and power conversion efficiency (PCE) as high as 9.10% under AM 1.5G irradiation. It is believed that such a high PCE comes from the improved optical absorption as well as the optimized carrier transfer and collection capability. Furthermore, the heterojunction could function as a high-performance self-driven visible light photodetector operating in a wide switching wavelength with good stability, high sensitivity, and fast response speed. It is expected that the present SiNW array/CQD core-shell heterojunction device could find potential applications in future high-performance optoelectronic devices.

Materials and processing approaches for foundry-compatible transient electronics

PubMed Central

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-01-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries. PMID:28652373

Proton exchange membrane micro fuel cells on 3D porous silicon gas diffusion layers

NASA Astrophysics Data System (ADS)

Kouassi, S.; Gautier, G.; Thery, J.; Desplobain, S.; Borella, M.; Ventura, L.; Laurent, J.-Y.

2012-10-01

Since the 90's, porous silicon has been studied and implemented in many devices, especially in MEMS technology. In this article, we present a new approach to build miniaturized proton exchange membrane micro-fuel cells using porous silicon as a hydrogen diffusion layer. In particular, we propose an innovative process to build micro fuel cells from a “corrugated iron like” 3D structured porous silicon substrates. This structure is able to increase up to 40% the cell area keeping a constant footprint on the silicon wafer. We propose here a process route to perform electrochemically 3D porous gas diffusion layers and to deposit fuel cell active layers on such substrates. The prototype peak power performance was measured to be 90 mW cm-2 in a “breathing configuration” at room temperature. These performances are less than expected if we compare with a reference 2D micro fuel cell. Actually, the active layer deposition processes are not fully optimized but this prototype demonstrates the feasibility of these 3D devices.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Silicon bulk micromachined, symmetric, degenerate vibratorygyroscope, accelerometer and sensor and method for using the same

NASA Technical Reports Server (NTRS)

Tang, Tony K. (Inventor); Kaiser, William J. (Inventor); Bartman, Randall K. (Inventor); Wilcox, Jaroslava Z. (Inventor); Gutierrez, Roman C. (Inventor); Calvet, Robert J. (Inventor)

1999-01-01

When embodied in a microgyroscope, the invention is comprised of a silicon, four-leaf clover structure with a post attached to the center. The whole structure is suspended by four silicon cantilevers or springs. The device is electrostatically actuated and capacitively detects Coriolis induced motions of the leaves of the leaf clover structure. In the case where the post is not symmetric with the plane of the clover leaves, the device can is usable as an accelerometer. If the post is provided in the shape of a dumb bell or an asymmetric post, the center of gravity is moved out of the plane of clover leaf structure and a hybrid device is provided. When the clover leaf structure is used without a center mass, it performs as a high Q resonator usable as a sensor of any physical phenomena which can be coupled to the resonant performance.

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors

PubMed Central

Marrs, Michael A.; Raupp, Gregory B.

2016-01-01

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm2 and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate. PMID:27472329

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors.

PubMed

Marrs, Michael A; Raupp, Gregory B

2016-07-26

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm² and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate.

Imaging of the native inversion layer in Silicon-On-Insulator wafers via Scanning Surface Photovoltage: Implications for RF device performance

NASA Astrophysics Data System (ADS)

Dahanayaka, Daminda; Wong, Andrew; Kaszuba, Philip; Moszkowicz, Leon; Slinkman, James; IBM SPV Lab Team

2014-03-01

Silicon-On-Insulator (SOI) technology has proved beneficial for RF cell phone technologies, which have equivalent performance to GaAs technologies. However, there is evident parasitic inversion layer under the Buried Oxide (BOX) at the interface with the high resistivity Si substrate. The latter is inferred from capacitance-voltage measurements on MOSCAPs. The inversion layer has adverse effects on RF device performance. We present data which, for the first time, show the extent of the inversion layer in the underlying substrate. This knowledge has driven processing techniques to suppress the inversion.

Crystal growth for high-efficiency silicon solar cells workshop: Summary

NASA Technical Reports Server (NTRS)

Dumas, K. A.

1985-01-01

The state of the art in the growth of silicon crystals for high-efficiency solar cells are reviewed, sheet requirements are defined, and furture areas of research are identified. Silicon sheet material characteristics that limit cell efficiencies and yields were described as well as the criteria for the ideal sheet-growth method. The device engineers wish list to the material engineer included: silicon sheet with long minority carrier lifetime that is uniform throughout the sheet, and which doesn't change during processing; and sheet material that stays flat throughout device processing, has uniform good mechanical strength, and is low cost. Impurities in silicon solar cells depreciate cell performance by reducing diffusion length and degrading junctions. The impurity behavior, degradation mechanisms, and variations in degradation threshold with diffusion length for silicon solar cells were described.

3D Integration for Wireless Multimedia

NASA Astrophysics Data System (ADS)

Kimmich, Georg

The convergence of mobile phone, internet, mapping, gaming and office automation tools with high quality video and still imaging capture capability is becoming a strong market trend for portable devices. High-density video encode and decode, 3D graphics for gaming, increased application-software complexity and ultra-high-bandwidth 4G modem technologies are driving the CPU performance and memory bandwidth requirements close to the PC segment. These portable multimedia devices are battery operated, which requires the deployment of new low-power-optimized silicon process technologies and ultra-low-power design techniques at system, architecture and device level. Mobile devices also need to comply with stringent silicon-area and package-volume constraints. As for all consumer devices, low production cost and fast time-to-volume production is key for success. This chapter shows how 3D architectures can bring a possible breakthrough to meet the conflicting power, performance and area constraints. Multiple 3D die-stacking partitioning strategies are described and analyzed on their potential to improve the overall system power, performance and cost for specific application scenarios. Requirements and maturity of the basic process-technology bricks including through-silicon via (TSV) and die-to-die attachment techniques are reviewed. Finally, we highlight new challenges which will arise with 3D stacking and an outlook on how they may be addressed: Higher power density will require thermal design considerations, new EDA tools will need to be developed to cope with the integration of heterogeneous technologies and to guarantee signal and power integrity across the die stack. The silicon/wafer test strategies have to be adapted to handle high-density IO arrays, ultra-thin wafers and provide built-in self-test of attached memories. New standards and business models have to be developed to allow cost-efficient assembly and testing of devices from different silicon and technology providers.

Silicone-Based Triboelectric Nanogenerator for Water Wave Energy Harvesting.

PubMed

Xiao, Tian Xiao; Jiang, Tao; Zhu, Jian Xiong; Liang, Xi; Xu, Liang; Shao, Jia Jia; Zhang, Chun Lei; Wang, Jie; Wang, Zhong Lin

2018-01-31

Triboelectric nanogenerator (TENG) has been proven to be efficient for harvesting water wave energy, which is one of the most promising renewable energy sources. In this work, a TENG with a silicone rubber/carbon black composite electrode was designed for converting the water wave energy into electricity. The silicone-based electrode with a soft texture provides a better contact with the dielectric film. Furthermore, a spring structure is introduced to transform low-frequency water wave motions into high-frequency vibrations. They together improve the output performance and efficiency of TENG. The output performances of TENGs are further enhanced by optimizing the triboelectric material pair and tribo-surface area. A spring-assisted TENG device with the segmented silicone rubber-based electrode structure was sealed into a waterproof box, which delivers a maximum power density of 2.40 W m -3 , as triggered by the water waves. The present work provides a new strategy for fabricating high-performance TENG devices by coupling flexible electrodes and spring structure for harvesting water wave energy.

An overview of silicon carbide device technology

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Matus, Lawrence G.

1992-01-01

Recent progress in the development of silicon carbide (SiC) as a semiconductor is briefly reviewed. This material shows great promise towards providing electronic devices that can operate under the high-temperature, high-radiation, and/or high-power conditions where current semiconductor technologies fail. High quality single crystal wafers have become available, and techniques for growing high quality epilayers have been refined to the point where experimental SiC devices and circuits can be developed. The prototype diodes and transistors that have been produced to date show encouraging characteristics, but by the same token they also exhibit some device-related problems that are not unlike those faced in the early days of silicon technology development. Although these problems will not prevent the implementation of some useful circuits, the performance and operating regime of SiC electronics will be limited until these device-related issues are solved.

Passively aligned multichannel fiber-pigtailing of planar integrated optical waveguides

NASA Astrophysics Data System (ADS)

Kremmel, Johannes; Lamprecht, Tobias; Crameri, Nino; Michler, Markus

2017-02-01

A silicon device to simplify the coupling of multiple single-mode fibers to embedded single-mode waveguides has been developed. The silicon device features alignment structures that enable a passive alignment of fibers to integrated waveguides. For passive alignment, precisely machined V-grooves on a silicon device are used and the planar lightwave circuit board features high-precision structures acting as a mechanical stop. The approach has been tested for up to eight fiber-to-waveguide connections. The alignment approach, the design, and the fabrication of the silicon device as well as the assembly process are presented. The characterization of the fiber-to-waveguide link reveals total coupling losses of (0.45±0.20 dB) per coupling interface, which is significantly lower than the values reported in earlier works. Subsequent climate tests reveal that the coupling losses remain stable during thermal cycling but increases significantly during an 85°C/85 Rh-test. All applied fabrication and bonding steps have been performed using standard MOEMS fabrication and packaging processes.

A computational workflow for designing silicon donor qubits

DOE PAGES

Humble, Travis S.; Ericson, M. Nance; Jakowski, Jacek; ...

2016-09-19

Developing devices that can reliably and accurately demonstrate the principles of superposition and entanglement is an on-going challenge for the quantum computing community. Modeling and simulation offer attractive means of testing early device designs and establishing expectations for operational performance. However, the complex integrated material systems required by quantum device designs are not captured by any single existing computational modeling method. We examine the development and analysis of a multi-staged computational workflow that can be used to design and characterize silicon donor qubit systems with modeling and simulation. Our approach integrates quantum chemistry calculations with electrostatic field solvers to performmore » detailed simulations of a phosphorus dopant in silicon. We show how atomistic details can be synthesized into an operational model for the logical gates that define quantum computation in this particular technology. In conclusion, the resulting computational workflow realizes a design tool for silicon donor qubits that can help verify and validate current and near-term experimental devices.« less

The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2016-05-01

Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I-V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

Finite Element Study of a Lumbar Intervertebral Disc Nucleus Replacement Device.

PubMed

Coogan, Jessica S; Francis, W Loren; Eliason, Travis D; Bredbenner, Todd L; Stemper, Brian D; Yoganandan, Narayan; Pintar, Frank A; Nicolella, Daniel P

2016-01-01

Nucleus replacement technologies are a minimally invasive alternative to spinal fusion and total disc replacement that have the potential to reduce pain and restore motion for patients with degenerative disc disease. Finite element modeling can be used to determine the biomechanics associated with nucleus replacement technologies. The current study focuses on a new nucleus replacement device designed as a conforming silicone implant with an internal void. A validated finite element model of the human lumbar L3-L4 motion segment was developed and used to investigate the influence of the nucleus replacement device on spine biomechanics. In addition, the effect of device design changes on biomechanics was determined. A 3D, L3-L4 finite element model was constructed from medical imaging data. Models were created with the normal intact nucleus, the nucleus replacement device, and a solid silicone implant. Probabilistic analysis was performed on the normal model to provide quantitative validation metrics. Sensitivity analysis was performed on the silicone Shore A durometer of the device. Models were loaded under axial compression followed by flexion/extension, lateral bending, or axial rotation. Compressive displacement, endplate stresses, reaction moment, and annulus stresses were determined and compared between the different models. The novel nucleus replacement device resulted in similar compressive displacement, endplate stress, and annulus stress and slightly higher reaction moment compared with the normal nucleus. The solid implant resulted in decreased displacement, increased endplate stress, decreased annulus stress, and decreased reaction moment compared with the novel device. With increasing silicone durometer, compressive displacement decreased, endplate stress increased, reaction moment increased, and annulus stress decreased. Finite element analysis was used to show that the novel nucleus replacement device results in similar biomechanics compared with the normal intact nucleus.

Finite Element Study of a Lumbar Intervertebral Disc Nucleus Replacement Device

PubMed Central

Coogan, Jessica S.; Francis, W. Loren; Eliason, Travis D.; Bredbenner, Todd L.; Stemper, Brian D.; Yoganandan, Narayan; Pintar, Frank A.; Nicolella, Daniel P.

2016-01-01

Nucleus replacement technologies are a minimally invasive alternative to spinal fusion and total disc replacement that have the potential to reduce pain and restore motion for patients with degenerative disc disease. Finite element modeling can be used to determine the biomechanics associated with nucleus replacement technologies. The current study focuses on a new nucleus replacement device designed as a conforming silicone implant with an internal void. A validated finite element model of the human lumbar L3–L4 motion segment was developed and used to investigate the influence of the nucleus replacement device on spine biomechanics. In addition, the effect of device design changes on biomechanics was determined. A 3D, L3–L4 finite element model was constructed from medical imaging data. Models were created with the normal intact nucleus, the nucleus replacement device, and a solid silicone implant. Probabilistic analysis was performed on the normal model to provide quantitative validation metrics. Sensitivity analysis was performed on the silicone Shore A durometer of the device. Models were loaded under axial compression followed by flexion/extension, lateral bending, or axial rotation. Compressive displacement, endplate stresses, reaction moment, and annulus stresses were determined and compared between the different models. The novel nucleus replacement device resulted in similar compressive displacement, endplate stress, and annulus stress and slightly higher reaction moment compared with the normal nucleus. The solid implant resulted in decreased displacement, increased endplate stress, decreased annulus stress, and decreased reaction moment compared with the novel device. With increasing silicone durometer, compressive displacement decreased, endplate stress increased, reaction moment increased, and annulus stress decreased. Finite element analysis was used to show that the novel nucleus replacement device results in similar biomechanics compared with the normal intact nucleus. PMID:27990418

Carbon Nanotube-Silicon Nanowire Heterojunction Solar Cells with Gas-Dependent Photovoltaic Performances and Their Application in Self-Powered NO2 Detecting.

PubMed

Jia, Yi; Zhang, Zexia; Xiao, Lin; Lv, Ruitao

2016-12-01

A multifunctional device combining photovoltaic conversion and toxic gas sensitivity is reported. In this device, carbon nanotube (CNT) membranes are used to cover onto silicon nanowire (SiNW) arrays to form heterojunction. The porous structure and large specific surface area in the heterojunction structure are both benefits for gas adsorption. In virtue of these merits, gas doping is a feasible method to improve cell's performance and the device can also work as a self-powered gas sensor beyond a solar cell. It shows a significant improvement in cell efficiency (more than 200 times) after NO2 molecules doping (device working as a solar cell) and a fast, reversible response property for NO2 detection (device working as a gas sensor). Such multifunctional CNT-SiNW structure can be expected to open a new avenue for developing self-powered, efficient toxic gas-sensing devices in the future.

Heterojunction Solar Cells Based on Silicon and Composite Films of Graphene Oxide and Carbon Nanotubes.

PubMed

Yu, LePing; Tune, Daniel; Shearer, Cameron; Shapter, Joseph

2015-09-07

Graphene oxide (GO) sheets have been used as the surfactant to disperse single-walled carbon nanotubes (CNT) in water to prepare GO/CNT electrodes that are applied to silicon to form a heterojunction that can be used in solar cells. GO/CNT films with different ratios of the two components and with various thicknesses have been used as semitransparent electrodes, and the influence of both factors on the performance of the solar cell has been studied. The degradation rate of the GO/CNT-silicon devices under ambient conditions has also been explored. The influence of the film thickness on the device performance is related to the interplay of two competing factors, namely, sheet resistance and transmittance. CNTs help to improve the conductivity of the GO/CNT film, and GO is able to protect the silicon from oxidation in the atmosphere. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Silicon nanowires for photovoltaic solar energy conversion.

PubMed

Peng, Kui-Qing; Lee, Shuit-Tong

2011-01-11

Semiconductor nanowires are attracting intense interest as a promising material for solar energy conversion for the new-generation photovoltaic (PV) technology. In particular, silicon nanowires (SiNWs) are under active investigation for PV applications because they offer novel approaches for solar-to-electric energy conversion leading to high-efficiency devices via simple manufacturing. This article reviews the recent developments in the utilization of SiNWs for PV applications, the relationship between SiNW-based PV device structure and performance, and the challenges to obtaining high-performance cost-effective solar cells.

Silicon coupled with plasmon nanocavities generates bright visible hot luminescence

NASA Astrophysics Data System (ADS)

Cho, Chang-Hee; Aspetti, Carlos O.; Park, Joohee; Agarwal, Ritesh

2013-04-01

To address the limitations in device speed and performance in silicon-based electronics, there have been extensive studies on silicon optoelectronics with a view to achieving ultrafast optical data processing. The biggest challenge has been to develop an efficient silicon-based light source, because the indirect bandgap of silicon gives rise to extremely low emission efficiencies. Although light emission in quantum-confined silicon at sub-10 nm length scales has been demonstrated, there are difficulties in integrating quantum structures with conventional electronics. It is desirable to develop new concepts to obtain emission from silicon at length scales compatible with current electronic devices (20-100 nm), which therefore do not utilize quantum-confinement effects. Here, we demonstrate an entirely new method to achieve bright visible light emission in `bulk-sized' silicon coupled with plasmon nanocavities at room temperature, from non-thermalized carrier recombination. The highly enhanced emission (internal quantum efficiency of >1%) in plasmonic silicon, together with its size compatibility with current silicon electronics, provides new avenues for developing monolithically integrated light sources on conventional microchips.

Monolithically interconnected silicon-film™ module technology

NASA Astrophysics Data System (ADS)

DelleDonne, E. J.; Ford, D. H.; Hall, R. B.; Ingram, A. E.; Rand, J. A.; Barnett, A. M.

1999-03-01

AstroPower is developing an advanced thin-silicon-based, photovoltaic module product. A low-cost monolithic interconnected device is being integrated into a module that combines the design and process features of advanced light trapped, thin-silicon solar cells. This advanced product incorporates a low-cost substrate, a nominally 50-μm thick grown silicon layer with minority carrier diffusion lengths exceeding the active layer thickness, light trapping due to back-surface reflection, and back-surface passivation. The thin silicon layer enables high solar cell performance and can lead to a module conversion efficiency as high as 19%. These performance design features, combined with low-cost manufacturing using relatively low-cost capital equipment, continuous processing and a low-cost substrate, will lead to high-performance, low-cost photovoltaic panels.

Development of a novel precision instrument for high-resolution simultaneous normal and shear force measurements between small planar samples

NASA Astrophysics Data System (ADS)

Lundstrom, Troy; Clark, William; Jalili, Nader

2017-05-01

In the design and development of end effector pads for silicon wafer handling robots, it is imperative that the static friction/adhesion force properties of the pads with respect to a variety of planar surfaces be characterized. In this work, the overall design, calibration, and data acquisition procedure of an instrument developed for performing these measurements on small (<10 mm × 10 mm) planar samples is presented. This device was used to perform adhesion/maximum shear force measurements on polydimethylsiloxane, a silicon wafer, and custom carbon nanotubes forest surfaces. The device was successfully able to measure an effective, mean profile adhesion force of 715 μN between a silicon wafer and a polydimethylsiloxane (2.768 × 10-6 m2) sample. In addition, a nonlinear maximum shear over normal force relationship was also measured between custom carbon nanotubes forest and the silicon wafer surfaces. The maximum shear over a normal force coefficient was found to decrease with increasing initial normal force. Currently, there are numerous devices for measuring normal/shear forces at the nano/micro- and macroscales; however, this device allows for the consistent measurement of these same types of forces on components with surface dimensions ranging from 0.1 mm to 10 mm.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Postfabrication Phase Error Correction of Silicon Photonic Circuits by Single Femtosecond Laser Pulses

DOE PAGES

Bachman, Daniel; Chen, Zhijiang; Wang, Christopher; ...

2016-11-29

Phase errors caused by fabrication variations in silicon photonic integrated circuits are an important problem, which negatively impacts device yield and performance. This study reports our recent progress in the development of a method for permanent, postfabrication phase error correction of silicon photonic circuits based on femtosecond laser irradiation. Using beam shaping technique, we achieve a 14-fold enhancement in the phase tuning resolution of the method with a Gaussian-shaped beam compared to a top-hat beam. The large improvement in the tuning resolution makes the femtosecond laser method potentially useful for very fine phase trimming of silicon photonic circuits. Finally, wemore » also show that femtosecond laser pulses can directly modify silicon photonic devices through a SiO 2 cladding layer, making it the only permanent post-fabrication method that can tune silicon photonic circuits protected by an oxide cladding.« less

Molecular Monolayers for Electrical Passivation and Functionalization of Silicon-Based Solar Energy Devices.

PubMed

Veerbeek, Janneke; Firet, Nienke J; Vijselaar, Wouter; Elbersen, Rick; Gardeniers, Han; Huskens, Jurriaan

2017-01-11

Silicon-based solar fuel devices require passivation for optimal performance yet at the same time need functionalization with (photo)catalysts for efficient solar fuel production. Here, we use molecular monolayers to enable electrical passivation and simultaneous functionalization of silicon-based solar cells. Organic monolayers were coupled to silicon surfaces by hydrosilylation in order to avoid an insulating silicon oxide layer at the surface. Monolayers of 1-tetradecyne were shown to passivate silicon micropillar-based solar cells with radial junctions, by which the efficiency increased from 8.7% to 9.9% for n + /p junctions and from 7.8% to 8.8% for p + /n junctions. This electrical passivation of the surface, most likely by removal of dangling bonds, is reflected in a higher shunt resistance in the J-V measurements. Monolayers of 1,8-nonadiyne were still reactive for click chemistry with a model catalyst, thus enabling simultaneous passivation and future catalyst coupling.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Impact of Total Ionizing Dose Radiation Testing and Long-Term Thermal Cycling on the Operation of CMF20120D Silicon Carbide Power MOSFET

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Scheidegger, Robert J.; Lauenstein, Jean-Marie; Casey, Megan; Scheick, Leif; Hammoud, Ahmad

2013-01-01

Power systems designed for use in NASA space missions are required to work reliably under harsh conditions including radiation, thermal cycling, and extreme temperature exposures. Silicon carbide devices show great promise for use in future power electronics systems, but information pertaining to performance of the devices in the space environment is very scarce. A silicon carbide N-channel enhancement-mode power MOSFET called the CMF20120 is of interest for use in space environments. Samples of the device were exposed to radiation followed by long-term thermal cycling to address their reliability for use in space applications. The results of the experimental work are presentd and discussed.

Progress in performance enhancement methods for capacitive silicon resonators

NASA Astrophysics Data System (ADS)

Van Toan, Nguyen; Ono, Takahito

2017-11-01

In this paper, we review the progress in recent studies on the performance enhancement methods for capacitive silicon resonators. We provide information on various fabrication technologies and design considerations that can be employed to improve the performance of capacitive silicon resonators, including low motional resistance, small insertion loss, and high quality factor (Q). This paper contains an overview of device structures and working principles, fabrication technologies consisting of hermetic packaging, deep reactive-ion etching and neutral beam etching, and design considerations including mechanically coupled, movable electrode structures and piezoresistive heat engines.

Multiple wavelength silicon photonic 200 mm R+D platform for 25Gb/s and above applications

NASA Astrophysics Data System (ADS)

Szelag, B.; Blampey, B.; Ferrotti, T.; Reboud, V.; Hassan, K.; Malhouitre, S.; Grand, G.; Fowler, D.; Brision, S.; Bria, T.; Rabillé, G.; Brianceau, P.; Hartmann, J. M.; Hugues, V.; Myko, A.; Elleboode, F.; Gays, F.; Fédéli, J. M.; Kopp, C.

2016-05-01

A silicon photonics platform that uses a CMOS foundry line is described. Fabrication process is following a modular integration scheme which leads to a flexible platform, allowing different device combinations. A complete device library is demonstrated for 1310 nm applications with state of the art performances. A PDK which includes specific photonic features and which is compatible with commercial EDA tools has been developed allowing an MPW shuttle service. Finally platform evolutions such as device offer extension to 1550 nm or new process modules introduction are presented.

Reduced adherence of Candida to silane-treated silicone rubber.

PubMed

Price, C L; Williams, D W; Waters, M G J; Coulthwaite, L; Verran, J; Taylor, R L; Stickler, D; Lewis, M A O

2005-07-01

Silicone rubber is widely used in the construction of medical devices that can provide an essential role in the treatment of human illness. However, subsequent microbial colonization of silicone rubber can result in clinical infection or device failure. The objective of this study was to determine the effectiveness of a novel silane-treated silicone rubber in inhibiting microbial adherence and material penetration. Test material was prepared by a combination of argon plasma discharge treatment and fluorinated silane coupling. Chemicophysical changes were then confirmed by X-ray photoelectron spectroscopy, contact-angle measurement, and atomic force microscopy. Two separate adherence assays and a material penetration assay assessed the performance of the new material against four strains of Candida species. Results showed a significant reduction (p < 0.01) of Candida albicans GDH 2346 adherence to silane-treated silicone compared with untreated controls. This reduction was still evident after the incorporation of saliva into the assay. Adherence inhibition also occurred with Candida tropicalis MMU and Candida krusei NCYC, although this was assay dependent. Reduced penetration of silane-treated silicone by Candida was evident when compared to untreated controls, plaster-processed silicone, and acrylic-processed silicone. To summarize, a novel silicone rubber material is described that inhibits both candidal adherence and material penetration. The clinical benefit and performance of this material remains to be determined. Copyright 2005 Wiley Periodicals, Inc.

Polycrystalline silicon thin-film transistors with location-controlled crystal grains fabricated by excimer laser crystallization

NASA Astrophysics Data System (ADS)

Tsai, Chun-Chien; Lee, Yao-Jen; Chiang, Ko-Yu; Wang, Jyh-Liang; Lee, I.-Che; Chen, Hsu-Hsin; Wei, Kai-Fang; Chang, Ting-Kuo; Chen, Bo-Ting; Cheng, Huang-Chung

2007-11-01

In this paper, location-controlled silicon crystal grains are fabricated by the excimer laser crystallization method which employs amorphous silicon spacer structure and prepatterned thin films. The amorphous silicon spacer in nanometer-sized width formed using spacer technology is served as seed crystal to artificially control superlateral growth phenomenon during excimer laser irradiation. An array of 1.8-μm-sized disklike silicon grains is formed, and the n-channel thin-film transistors whose channels located inside the artificially-controlled crystal grains exhibit higher performance of field-effect-mobility reaching 308cm2/Vs as compared with the conventional ones. This position-manipulated silicon grains are essential to high-performance and good uniformity devices.

Seventh workshop on the role of impurities and defects in silicon device processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

1997-08-01

This workshop is the latest in a series which has looked at technological issues related to the commercial development and success of silicon based photovoltaic (PV) modules. PV modules based on silicon are the most common at present, but face pressure from other technologies in terms of cell performance and cell cost. This workshop addresses a problem which is a factor in the production costs of silicon based PV modules.

Athermal Photonic Devices and Circuits on a Silicon Platform

NASA Astrophysics Data System (ADS)

Raghunathan, Vivek

In recent years, silicon based optical interconnects has been pursued as an effective solution that can offer cost, energy, distance and bandwidth density improvements over copper. Monolithic integration of optics and electronics has been enabled by silicon photonic devices that can be fabricated using CMOS technology. However, high levels of device integration result in significant local and global temperature fluctuations that prove problematic for silicon based photonic devices. In particular, high temperature dependence of Si refractive index (thermo-optic (TO) coefficient) shifts the filter response of resonant devices that limit wavelength resolution in various applications. Active thermal compensation using heaters and thermo-electric coolers are the legacy solution for low density integration. However, the required electrical power, device foot print and number of input/output (I/O) lines limit the integration density. We present a passive approach to an athermal design that involves compensation of positive TO effects from a silicon core by negative TO effects of the polymer cladding. In addition, the design rule involves engineering the waveguide core geometry depending on the resonance wavelength under consideration to ensure desired amount of light in the polymer. We develop exact design requirements for a TO peak stability of 0 pm/K and present prototype performance of 0.5 pm/K. We explore the material design space through initiated chemical vapor deposition (iCVD) of 2 polymer cladding choices. We study the effect of cross-linking on the optical properties of a polymer and establish the superior performance of the co-polymer cladding compared to the homo-polymer. Integration of polymer clad devices in an electronic-photonic architecture requires the possibility of multi-layer stacking capability. We use a low temperature, high density plasma chemical vapor deposition of SiO2/SiN x to hermetically seal the athermal. Further, we employ visible light for post-fabrication trimming of athermal rings by sandwiching a thin photosensitive layer of As2S3 in between amorphous Si core and polymer top cladding. System design of an add-drop filter requires an optimum combination of channel counts performance and power handling capacity for maximum aggregate bandwidth. We establish the superior performance of athermal add-drop filter compared to a standard filter treating bandwidth as the figure-of-merit. (Copies available exclusively from MIT Libraries, libraries.mit.edu/docs - docs mit.edu)

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

NASA Astrophysics Data System (ADS)

Ghaffari, Majid; Orouji, Ali A.

2018-06-01

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

Synthesis and properties of silicon nanowire devices

NASA Astrophysics Data System (ADS)

Byon, Kumhyo

Silicon nanowire (SiNW) is a very attractive one-dimensional material for future nanoelectronic applications. Reliable control of key field effect transistor (FET) parameters such as conductance, mobility, threshold voltage and on/off ratio is crucial to the applications of SiNW to working logic devices and integrated circuits. In this thesis, we fabricated silicon nanowire field effect transistors (SiNW FETs) and studied the dependence of their electrical transport properties upon various parameters including SiNW growth conditions, post-growth doping, and contact annealing. From these studies, we found how different processes control important FET characteristics. Key accomplishments of this thesis include p-channel enhancement mode FETs, n-channel FETs by post-growth vapor doping and high performance ambipolar devices. In the first part of this work, single crystalline SiNWs were synthesized by thermal evaporation without gold catalysts. FETs were fabricated using both as-grown SiNWs and post-growth n-doped SiNWs. FET from p-type source materials behaves as a p-channel enhancement mode FET which is predominant in logic devices due to its fast operation and low power consumption. Using bismuth vapor, the as-grown SiNWs were doped into n-type materials. The majority carriers in SiNWs can therefore be controlled by proper choice of the vapor phase dopant species. Post-growth doping using vapor phase is applicable to other nanowire systems. In the second part, high performance ambipolar FETs were fabricated. A two step annealing process was used to control the Schottky barrier between SiNW and metal contacts in order to enhance device performance. Initial p-channel SiNW FETs were converted into ambipolar SiNW FETs after contact annealing. Furthermore, significant increases in both on/off ratio and channel mobilities were achieved after contact annealing. Promising device structures to implement ambipolar devices into large scale integrated circuits were proposed. The contributions of this study are to further understanding of the electrical transport properties of SiNWs and to provide optimized processes to fabricate emerging high performance nanoelectronic devices using SiNWs for future generation beyond bulk silicon.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bachman, Daniel; Chen, Zhijiang; Wang, Christopher

Phase errors caused by fabrication variations in silicon photonic integrated circuits are an important problem, which negatively impacts device yield and performance. This study reports our recent progress in the development of a method for permanent, postfabrication phase error correction of silicon photonic circuits based on femtosecond laser irradiation. Using beam shaping technique, we achieve a 14-fold enhancement in the phase tuning resolution of the method with a Gaussian-shaped beam compared to a top-hat beam. The large improvement in the tuning resolution makes the femtosecond laser method potentially useful for very fine phase trimming of silicon photonic circuits. Finally, wemore » also show that femtosecond laser pulses can directly modify silicon photonic devices through a SiO 2 cladding layer, making it the only permanent post-fabrication method that can tune silicon photonic circuits protected by an oxide cladding.« less

A scalable silicon photonic chip-scale optical switch for high performance computing systems.

PubMed

Yu, Runxiang; Cheung, Stanley; Li, Yuliang; Okamoto, Katsunari; Proietti, Roberto; Yin, Yawei; Yoo, S J B

2013-12-30

This paper discusses the architecture and provides performance studies of a silicon photonic chip-scale optical switch for scalable interconnect network in high performance computing systems. The proposed switch exploits optical wavelength parallelism and wavelength routing characteristics of an Arrayed Waveguide Grating Router (AWGR) to allow contention resolution in the wavelength domain. Simulation results from a cycle-accurate network simulator indicate that, even with only two transmitter/receiver pairs per node, the switch exhibits lower end-to-end latency and higher throughput at high (>90%) input loads compared with electronic switches. On the device integration level, we propose to integrate all the components (ring modulators, photodetectors and AWGR) on a CMOS-compatible silicon photonic platform to ensure a compact, energy efficient and cost-effective device. We successfully demonstrate proof-of-concept routing functions on an 8 × 8 prototype fabricated using foundry services provided by OpSIS-IME.

Area Reports. Advanced materials and devices research area. Silicon materials research task, and advanced silicon sheet task

NASA Technical Reports Server (NTRS)

1986-01-01

The objectives of the Silicon Materials Task and the Advanced Silicon Sheet Task are to identify the critical technical barriers to low-cost silicon purification and sheet growth that must be overcome to produce a PV cell substrate material at a price consistent with Flat-plate Solar Array (FSA) Project objectives and to overcome these barriers by performing and supporting appropriate R&D. Progress reports are given on silicon refinement using silane, a chemical vapor transport process for purifying metallurgical grade silicon, silicon particle growth research, and modeling of silane pyrolysis in fluidized-bed reactors.

Enhancing the Efficiency of Silicon-Based Solar Cells by the Piezo-Phototronic Effect.

PubMed

Zhu, Laipan; Wang, Longfei; Pan, Caofeng; Chen, Libo; Xue, Fei; Chen, Baodong; Yang, Leijing; Su, Li; Wang, Zhong Lin

2017-02-28

Although there are numerous approaches for fabricating solar cells, the silicon-based photovoltaics are still the most widely used in industry and around the world. A small increase in the efficiency of silicon-based solar cells has a huge economic impact and practical importance. We fabricate a silicon-based nanoheterostructure (p + -Si/p-Si/n + -Si (and n-Si)/n-ZnO nanowire (NW) array) photovoltaic device and demonstrate the enhanced device performance through significantly enhanced light absorption by NW array and effective charge carrier separation by the piezo-phototronic effect. The strain-induced piezoelectric polarization charges created at n-doped Si-ZnO interfaces can effectively modulate the corresponding band structure and electron gas trapped in the n + -Si/n-ZnO NW nanoheterostructure and thus enhance the transport process of local charge carriers. The efficiency of the solar cell was improved from 8.97% to 9.51% by simply applying a static compress strain. This study indicates that the piezo-phototronic effect can enhance the performance of a large-scale silicon-based solar cell, with great potential for industrial applications.

Top-Down Nanofabrication and Characterization of 20 nm Silicon Nanowires for Biosensing Applications

PubMed Central

M. N, M. Nuzaihan; Hashim, U.; Md Arshad, M. K.; Ruslinda, A. Rahim; Rahman, S. F. A.; Fathil, M. F. M.; Ismail, Mohd. H.

2016-01-01

A top-down nanofabrication approach is used to develop silicon nanowires from silicon-on-insulator (SOI) wafers and involves direct-write electron beam lithography (EBL), inductively coupled plasma-reactive ion etching (ICP-RIE) and a size reduction process. To achieve nanometer scale size, the crucial factors contributing to the EBL and size reduction processes are highlighted. The resulting silicon nanowires, which are 20 nm in width and 30 nm in height (with a triangular shape) and have a straight structure over the length of 400 μm, are fabricated precisely at the designed location on the device. The device is applied in biomolecule detection based on the changes in drain current (Ids), electrical resistance and conductance of the silicon nanowires upon hybridization to complementary target deoxyribonucleic acid (DNA). In this context, the scaled-down device exhibited superior performances in terms of good specificity and high sensitivity, with a limit of detection (LOD) of 10 fM, enables for efficient label-free, direct and higher-accuracy DNA molecules detection. Thus, this silicon nanowire can be used as an improved transducer and serves as novel biosensor for future biomedical diagnostic applications. PMID:27022732

ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon

NASA Astrophysics Data System (ADS)

Tracy, Lisa; Luhman, Dwight; Carr, Stephen; Borchardt, John; Bishop, Nathaniel; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Witzel, Wayne; Blume-Kohout, Robin; Nielsen, Erik; Lilly, Michael; Carroll, Malcolm

In this talk we will discuss electron spin resonance experiments in single donor silicon qubit devices fabricated at Sandia National Labs. A self-aligned device structure consisting of a polysilicon gate SET located adjacent to the donor is used for donor electron spin readout. Using a cryogenic HEMT amplifier next to the silicon device, we demonstrate spin readout at 100 kHz bandwidth and Rabi oscillations with 0.96 visibility. Electron spin resonance measurements on these devices show a linewidth of 30 kHz and coherence times T2* = 10 us and T2 = 0.3 ms. We also discuss estimates of the fidelity of our donor electron spin qubit measurements using gate set tomography. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Energy correlations of photon pairs generated by a silicon microring resonator probed by Stimulated Four Wave Mixing.

PubMed

Grassani, Davide; Simbula, Angelica; Pirotta, Stefano; Galli, Matteo; Menotti, Matteo; Harris, Nicholas C; Baehr-Jones, Tom; Hochberg, Michael; Galland, Christophe; Liscidini, Marco; Bajoni, Daniele

2016-04-01

Compact silicon integrated devices, such as micro-ring resonators, have recently been demonstrated as efficient sources of quantum correlated photon pairs. The mass production of integrated devices demands the implementation of fast and reliable techniques to monitor the device performances. In the case of time-energy correlations, this is particularly challenging, as it requires high spectral resolution that is not currently achievable in coincidence measurements. Here we reconstruct the joint spectral density of photons pairs generated by spontaneous four-wave mixing in a silicon ring resonator by studying the corresponding stimulated process, namely stimulated four wave mixing. We show that this approach, featuring high spectral resolution and short measurement times, allows one to discriminate between nearly-uncorrelated and highly-correlated photon pairs.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2004-12-07

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process For Direct Integration Of A Thin-Film Silicon P-N Junction Diode With A Magnetic Tunnel Junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2005-08-23

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2003-01-01

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

III-V-on-silicon solar cells reaching 33% photoconversion efficiency in two-terminal configuration

NASA Astrophysics Data System (ADS)

Cariou, Romain; Benick, Jan; Feldmann, Frank; Höhn, Oliver; Hauser, Hubert; Beutel, Paul; Razek, Nasser; Wimplinger, Markus; Bläsi, Benedikt; Lackner, David; Hermle, Martin; Siefer, Gerald; Glunz, Stefan W.; Bett, Andreas W.; Dimroth, Frank

2018-04-01

Silicon dominates the photovoltaic industry but the conversion efficiency of silicon single-junction solar cells is intrinsically constrained to 29.4%, and practically limited to around 27%. It is possible to overcome this limit by combining silicon with high-bandgap materials, such as III-V semiconductors, in a multi-junction device. Significant challenges associated with this material combination have hindered the development of highly efficient III-V/Si solar cells. Here, we demonstrate a III-V/Si cell reaching similar performances to standard III-V/Ge triple-junction solar cells. This device is fabricated using wafer bonding to permanently join a GaInP/GaAs top cell with a silicon bottom cell. The key issues of III-V/Si interface recombination and silicon's weak absorption are addressed using poly-silicon/SiOx passivating contacts and a novel rear-side diffraction grating for the silicon bottom cell. With these combined features, we demonstrate a two-terminal GaInP/GaAs//Si solar cell reaching a 1-sun AM1.5G conversion efficiency of 33.3%.

Development of large-area monolithically integrated silicon-film photovoltaic modules

NASA Astrophysics Data System (ADS)

Rand, J. A.; Cotter, J. E.; Ingram, A. E.; Ruffins, T. R.; Shreve, K. P.; Hall, R. B.; Barnett, A. M.

1993-06-01

This report describes work to develop Silicon-Film (trademark) Product 3 into a low-cost, stable solar cell for large-scale terrestrial power applications. The Product 3 structure is a thin (less than 100 micron) polycrystalline layer of silicon on a durable, insulating, ceramic substrate. The insulating substrate allows the silicon layer to be isolated and metallized to form a monolithically interconnected array of solar cells. High efficiency is achievable with the use of light trapping and a passivated back surface. The long-term goal for the product is a 1200 sq cm, 18%-efficient, monolithic array. The short-term objectives are to improve material quality and to fabricate 100 sq cm monolithically interconnected solar cell arrays. Low minority-carrier diffusion length in the silicon film and series resistance in the interconnected device structure are presently limiting device performance. Material quality is continually improving through reduced impurity contamination. Metallization schemes, such as a solder-dipped interconnection process, have been developed that will allow low-cost production processing and minimize R(sub s) effects. Test data for a nine-cell device (16 sq cm) indicated a V(sub oc) of 3.72 V. These first-reported monolithically interconnected multicrystalline silicon-on-ceramic devices show low shunt conductance (less than 0.1 mA/sq cm) due to limited conduction through the ceramic and no process-related metallization shunts.

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

High performance SONOS flash memory with in-situ silicon nanocrystals embedded in silicon nitride charge trapping layer

NASA Astrophysics Data System (ADS)

Lim, Jae-Gab; Yang, Seung-Dong; Yun, Ho-Jin; Jung, Jun-Kyo; Park, Jung-Hyun; Lim, Chan; Cho, Gyu-seok; Park, Seong-gye; Huh, Chul; Lee, Hi-Deok; Lee, Ga-Won

2018-02-01

In this paper, SONOS-type flash memory device with highly improved charge-trapping efficiency is suggested by using silicon nanocrystals (Si-NCs) embedded in silicon nitride (SiNX) charge trapping layer. The Si-NCs were in-situ grown by PECVD without additional post annealing process. The fabricated device shows high program/erase speed and retention property which is suitable for multi-level cell (MLC) application. Excellent performance and reliability for MLC are demonstrated with large memory window of ∼8.5 V and superior retention characteristics of 7% charge loss for 10 years. High resolution transmission electron microscopy image confirms the Si-NC formation and the size is around 1-2 nm which can be verified again in X-ray photoelectron spectroscopy (XPS) where pure Si bonds increase. Besides, XPS analysis implies that more nitrogen atoms make stable bonds at the regular lattice point. Photoluminescence spectra results also illustrate that Si-NCs formation in SiNx is an effective method to form deep trap states.

Embedding solar cell materials with on-board integrated energy storage for load-leveling and dark power delivery (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pint, Cary L.; Westover, Andrew S.; Cohn, Adam P.; Erwin, William R.; Share, Keith; Metke, Thomas; Bardhan, Rizia

2015-10-01

This work will discuss our recent advances focused on integrating high power energy storage directly into the native materials of both conventional photovoltaics (PV) and dye-sensitized solar cells (DSSCs). In the first case (PV), we demonstrate the ability to etch high surface-area porous silicon charge storage interfaces directly into the backside of a conventional polycrystalline silicon photovoltaic device exhibiting over 14% efficiency. These high surface area materials are then coupled with solid-state ionic liquid-polymer electrolytes to produce solid-state fully integrated devices where the PV device can directly inject charge into an on-board supercapacitor that can be separately discharged under dark conditions with a Coulombic efficiency of 84%. In a similar manner, we further demonstrate that surface engineered silicon materials can be utilized to replace Pt counterelectrodes in conventional DSSC energy conversion devices. As the silicon counterelectrodes rely strictly on surface Faradaic chemical reactions with the electrolyte on one side of the wafer electrode, we demonstrate double-sided processing of electrodes that enables dual-function of the material for simultaneous energy storage and conversion, each on opposing sides. In both of these devices, we demonstrate the ability to produce an all-silicon coupled energy conversion and storage system through the common ability to convert unused silicon in solar cells into high power silicon-based supercapacitors. Beyond the proof-of-concept design and performance of this integrated solar-storage system, this talk will conclude with a brief discussion of the hurdles and challenges that we envision for this emerging area both from a fundamental and technological viewpoint.

Single-Event Effects in Silicon and Silicon Carbide Power Devices

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2014-01-01

NASA Electronics Parts and Packaging program-funded activities over the past year on single-event effects in silicon and silicon carbide power devices are presented, with focus on SiC device failure signatures.

A static induction device manufactured by silicon direct bonding

NASA Astrophysics Data System (ADS)

Chen, Xin'an; Liu, Su; Huang, Qing'an

2004-07-01

It is always a key problem how to improve the gate-source breakdown voltage (VGK) of static induction devices during manufacturing. By using a silicon direct bonding process to replace the high resistivity epitaxy process, a bonding buried gate structure is formed, which is different from an epitaxy buried gate structure. The new structure can improve the gate-source breakdown voltage from the process and the structure. It is shown that the bonding buried gate structure is a promising structure, that can improve the VGK and other performances of devices, by manufacture of a static induction thyristor.

Silicon Carbide Power Device Performance Under Heavy-Ion Irradiation

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan; Topper, Alyson; Wilcox, Edward; Phan, Anthony; Ikpe, Stanley; LaBel, Ken

2015-01-01

Heavy-ion induced degradation and catastrophic failure data for SiC power MOSFETs and Schottky diodes are examined to provide insight into the challenge of single-event effect hardening of SiC power devices.

High-performance silicon photonics technology for telecommunications applications.

PubMed

Yamada, Koji; Tsuchizawa, Tai; Nishi, Hidetaka; Kou, Rai; Hiraki, Tatsurou; Takeda, Kotaro; Fukuda, Hiroshi; Ishikawa, Yasuhiko; Wada, Kazumi; Yamamoto, Tsuyoshi

2014-04-01

By way of a brief review of Si photonics technology, we show that significant improvements in device performance are necessary for practical telecommunications applications. In order to improve device performance in Si photonics, we have developed a Si-Ge-silica monolithic integration platform, on which compact Si-Ge-based modulators/detectors and silica-based high-performance wavelength filters are monolithically integrated. The platform features low-temperature silica film deposition, which cannot damage Si-Ge-based active devices. Using this platform, we have developed various integrated photonic devices for broadband telecommunications applications.

High-performance silicon photonics technology for telecommunications applications

PubMed Central

Yamada, Koji; Tsuchizawa, Tai; Nishi, Hidetaka; Kou, Rai; Hiraki, Tatsurou; Takeda, Kotaro; Fukuda, Hiroshi; Ishikawa, Yasuhiko; Wada, Kazumi; Yamamoto, Tsuyoshi

2014-01-01

By way of a brief review of Si photonics technology, we show that significant improvements in device performance are necessary for practical telecommunications applications. In order to improve device performance in Si photonics, we have developed a Si-Ge-silica monolithic integration platform, on which compact Si-Ge–based modulators/detectors and silica-based high-performance wavelength filters are monolithically integrated. The platform features low-temperature silica film deposition, which cannot damage Si-Ge–based active devices. Using this platform, we have developed various integrated photonic devices for broadband telecommunications applications. PMID:27877659

High-performance silicon photonics technology for telecommunications applications

NASA Astrophysics Data System (ADS)

Yamada, Koji; Tsuchizawa, Tai; Nishi, Hidetaka; Kou, Rai; Hiraki, Tatsurou; Takeda, Kotaro; Fukuda, Hiroshi; Ishikawa, Yasuhiko; Wada, Kazumi; Yamamoto, Tsuyoshi

2014-04-01

By way of a brief review of Si photonics technology, we show that significant improvements in device performance are necessary for practical telecommunications applications. In order to improve device performance in Si photonics, we have developed a Si-Ge-silica monolithic integration platform, on which compact Si-Ge-based modulators/detectors and silica-based high-performance wavelength filters are monolithically integrated. The platform features low-temperature silica film deposition, which cannot damage Si-Ge-based active devices. Using this platform, we have developed various integrated photonic devices for broadband telecommunications applications.

3D-FBK Pixel Sensors: Recent Beam Tests Results with Irradiated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Micelli, A.; /INFN, Trieste /Udine U.; Helle, K.

2012-04-30

The Pixel Detector is the innermost part of the ATLAS experiment tracking device at the Large Hadron Collider, and plays a key role in the reconstruction of the primary vertices from the collisions and secondary vertices produced by short-lived particles. To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology ismore » an innovative combination of very-large-scale integration and Micro-Electro-Mechanical-Systems where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. This paper reports on the 2010 June beam test results for irradiated 3D devices produced at FBK (Trento, Italy). The performance of these devices, all bump-bonded with the ATLAS pixel FE-I3 read-out chip, is compared to that observed before irradiation in a previous beam test.« less

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

All-solid-state supercapacitors on silicon using graphene from silicon carbide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca, E-mail: f.iacopi@griffith.edu.au

2016-05-02

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitancemore » behavior with a specific area capacitance of up to 174 μF cm{sup −2} with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.« less

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Defects and device performance

NASA Technical Reports Server (NTRS)

Storti, G.; Armstrong, R.; Johnson, S.; Lin, H. C.; Regnault, W.; Yoo, K. C.

1985-01-01

The necessity for a low-cost crystalline silicon sheet material for photovoltaics has generated a number of alternative crystal growth techniques that would replace Czochralski (Cz) and float-zone (FZ) technologies. Efficiencies of devices fabricated from low resistivity FZ silicon are approaching 20%, and it is highly likely that this value will be superseded in the near future. However, FZ silicon is expensive, and is unlikely ever to be used for photovoltaics. Cz silicon has many of the desirable qualities of FZ except that minority-carrier lifetimes at lower resistivities are significantly less than those of FZ silicon. Even with Cz silicon, it is unlikely that cost goals can be met because of the poor-material yield that results from sawing and other aspects of the crystal rowth. Although other silicon sheet technologies have been investigated, almost all have characteristics that limit efficiency to approx. 16%. In summary, 20% efficient solar cells can likely be fabricated from both FZ and Cz silicon, but costs are likely to be ultimately unacceptable. Alternate silicon technologies are not likely to achieve this goal, but cost per watt figures may be eventually better than either of the single crystal technologies and may rival any thin-film technology.

Electroless epitaxial etching for semiconductor applications

DOEpatents

McCarthy, Anthony M.

2002-01-01

A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.

Silicon detectors for combined MR-PET and MR-SPECT imaging

NASA Astrophysics Data System (ADS)

Studen, A.; Brzezinski, K.; Chesi, E.; Cindro, V.; Clinthorne, N. H.; Cochran, E.; Grošičar, B.; Grkovski, M.; Honscheid, K.; Kagan, H.; Lacasta, C.; Llosa, G.; Mikuž, M.; Stankova, V.; Weilhammer, P.; Žontar, D.

2013-02-01

Silicon based devices can extend PET-MR and SPECT-MR imaging to applications, where their advantages in performance outweigh benefits of high statistical counts. Silicon is in many ways an excellent detector material with numerous advantages, among others: excellent energy and spatial resolution, mature processing technology, large signal to noise ratio, relatively low price, availability, versatility and malleability. The signal in silicon is also immune to effects of magnetic field at the level normally used in MR devices. Tests in fields up to 7 T were performed in a study to determine effects of magnetic field on positron range in a silicon PET device. The curvature of positron tracks in direction perpendicular to the field's orientation shortens the distance between emission and annihilation point of the positron. The effect can be fully appreciated for a rotation of the sample for a fixed field direction, compressing range in all dimensions. A popular Ga-68 source was used showing a factor of 2 improvement in image noise compared to zero field operation. There was also a little increase in noise as the reconstructed resolution varied between 2.5 and 1.5 mm. A speculative applications can be recognized in both emission modalities, SPECT and PET. Compton camera is a subspecies of SPECT, where a silicon based scatter as a MR compatible part could inserted into the MR bore and the secondary detector could operate in less constrained environment away from the magnet. Introducing a Compton camera also relaxes requirements of the radiotracers used, extending the range of conceivable photon energies beyond 140.5 keV of the Tc-99m. In PET, one could exploit the compressed sub-millimeter range of positrons in the magnetic field. To exploit the advantage, detectors with spatial resolution commensurate to the effect must be used with silicon being an excellent candidate. Measurements performed outside of the MR achieving spatial resolution below 1 mm are reported.

Vertical power MOS transistor as a thermoelectric quasi-nanowire device

NASA Astrophysics Data System (ADS)

Roizin, Gregory; Beeri, Ofer; Peretz, Mor Mordechai; Gelbstein, Yaniv

2016-12-01

Nano-materials exhibit superior performance over bulk materials in a variety of applications such as direct heat to electricity thermoelectric generators (TEGs) and many more. However, a gap still exists for the integration of these nano-materials into practical applications. This study explores the feasibility of utilizing the advantages of nano-materials' thermo-electric properties, using regular bulk technology. Present-day TEGs are often applied by dedicated thermoelectric materials such as semiconductor alloys (e.g., PbTe, BiTe) whereas the standard semiconductor materials such as the doped silicon have not been widely addressed, with limited exceptions of nanowires. This study attempts to close the gap between the nano-materials' properties and the well-established bulk devices, approached for the first time by exploiting the nano-metric dimensions of the conductive channel in metal-oxide-semiconductor (MOS) structures. A significantly higher electrical current than expected from a bulk silicon device has been experimentally measured as a result of the application of a positive gate voltage and a temperature gradient between the "source" and the "drain" terminals of a commercial NMOS transistor. This finding implies on a "quasi-nanowire" behaviour of the transistor channel, which can be easily controlled by the transistor's gate voltage that is applied. This phenomenon enables a considerable improvement of silicon based TEGs, fabricated by traditional silicon technology. Four times higher ZT values (TEG quality factor) compared to conventional bulk silicon have been observed for an off-the-shelf silicon device. By optimizing the device, it is believed that even higher ZT values can be achieved.

Field Performance versus Standard Test Condition Efficiency of Tandem Solar Cells and the Singular Case of Perovskites/Silicon Devices.

PubMed

Dupré, Olivier; Niesen, Bjoern; De Wolf, Stefaan; Ballif, Christophe

2018-01-18

Multijunction cells may offer a cost-effective route to boost the efficiency of industrial photovoltaics. For any technology to be deployed in the field, its performance under actual operating conditions is extremely important. In this perspective, we evaluate the impact of spectrum, light intensity, and module temperature variations on the efficiency of tandem devices with crystalline silicon bottom cells with a particular focus on perovskite top cells. We consider devices with different efficiencies and calculate their energy yields using field data from Denver. We find that annual losses due to differences between operating conditions and standard test conditions are similar for single-junction and four-terminal tandem devices. The additional loss for the two-terminal tandem configuration caused by current mismatch reduces its performance ratio by only 1.7% when an optimal top cell bandgap is used. Additionally, the unusual bandgap temperature dependence of perovskites is shown to have a positive, compensating effect on current mismatch.

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

A silicon carbide array for electrocorticography and peripheral nerve recording.

PubMed

Diaz-Botia, C A; Luna, L E; Neely, R M; Chamanzar, M; Carraro, C; Carmena, J M; Sabes, P N; Maboudian, R; Maharbiz, M M

2017-10-01

Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

A silicon carbide array for electrocorticography and peripheral nerve recording

NASA Astrophysics Data System (ADS)

Diaz-Botia, C. A.; Luna, L. E.; Neely, R. M.; Chamanzar, M.; Carraro, C.; Carmena, J. M.; Sabes, P. N.; Maboudian, R.; Maharbiz, M. M.

2017-10-01

Objective. Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. Approach. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. Main results. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Significance. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

NASA Astrophysics Data System (ADS)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

An evaluation of strain measuring devices for ceramic composites

NASA Technical Reports Server (NTRS)

Gyekenyesi, John Z.; Bartolotta, Paul A.

1991-01-01

A series of tensile tests was conducted on SiC/reaction bonded silicon nitrides (RBSN) composites using different methods of strain measurement. The tests were used to find the optimum strain sensing device for use with continuous fiber reinforced ceramic matrix composites in ambient and high temperature environments. Bonded resistance gages were found to offer excellent performance for room temperature tests. The clip-on gage offers the same performance, but less time is required for mounting it to the specimen. Low contact force extensometers track the strain with acceptable results at high specimen temperatures. Silicon carbide rods with knife edges are preferred. The edges must be kept sharp. The strain measuring devices should be mounted on the flat side of the specimen. This is in contrast to mounting on the rough thickness side.

Numerical simulations: Toward the design of 27.6% efficient four-terminal semi-transparent perovskite/SiC passivated rear contact silicon tandem solar cell

NASA Astrophysics Data System (ADS)

Pandey, Rahul; Chaujar, Rishu

2016-12-01

In this work, a novel four-terminal perovskite/SiC-based rear contact silicon tandem solar cell device has been proposed and simulated to achieve 27.6% power conversion efficiency (PCE) under single AM1.5 illumination. 20.9% efficient semitransparent perovskite top subcell has been used for perovskite/silicon tandem architecture. The tandem structure of perovskite-silicon solar cells is a promising method to achieve efficient solar energy conversion at low cost. In the four-terminal tandem configuration, the cells are connected independently and hence avoids the need for current matching between top and bottom subcell, thus giving greater design flexibility. The simulation analysis shows, PCE of 27.6% and 22.4% with 300 μm and 10 μm thick rear contact Si bottom subcell, respectively. This is a substantial improvement comparing to transparent perovskite solar cell and c-Si solar cell operated individually. The impact of perovskite layer thickness, monomolecular, bimolecular, and trimolecular recombination have also been obtained on the performance of perovskite top subcell. Reported PCEs of 27.6% and 22.4% are 1.25 times and 1.42 times higher as compared to experimentally available efficiencies of 22.1% and 15.7% in 300 μm and 10 μm thick stand-alone silicon solar cell devices, respectively. The presence of SiC significantly suppressed the interface recombination in bottom silicon subcell. Detailed realistic technology computer aided design (TCAD) analysis has been performed to predict the behaviour of the device.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

PubMed

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Solution-processed polycrystalline silicon on paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Trifunovic, M.; Ishihara, R., E-mail: r.ishihara@tudelft.nl; Shimoda, T.

Printing electronics has led to application areas which were formerly impossible with conventional electronic processes. Solutions are used as inks on top of large areas at room temperatures, allowing the production of fully flexible circuitry. Commonly, research in these inks have focused on organic and metal-oxide ink materials due to their printability, while these materials lack in the electronic performance when compared to silicon electronics. Silicon electronics, on the other hand, has only recently found their way in solution processes. Printing of cyclopentasilane as the silicon ink has been conducted and devices with far superior electric performance have been mademore » when compared to other ink materials. A thermal annealing step of this material, however, was necessary, which prevented its usage on inexpensive substrates with a limited thermal budget. In this work, we introduce a method that allows polycrystalline silicon (poly-Si) production directly from the same liquid silicon ink using excimer laser irradiation. In this way, poly-Si could be formed directly on top of paper even with a single laser pulse. Using this method, poly-Si transistors were created at a maximum temperature of only 150 °C. This method allows silicon device formation on inexpensive, temperature sensitive substrates such as polyethylene terephthalate, polyethylene naphthalate or paper, which leads to applications that require low-cost but high-speed electronics.« less

Active phase correction of high resolution silicon photonic arrayed waveguide gratings.

PubMed

Gehl, M; Trotter, D; Starbuck, A; Pomerene, A; Lentine, A L; DeRose, C

2017-03-20

Arrayed waveguide gratings provide flexible spectral filtering functionality for integrated photonic applications. Achieving narrow channel spacing requires long optical path lengths which can greatly increase the footprint of devices. High index contrast waveguides, such as those fabricated in silicon-on-insulator wafers, allow tight waveguide bends which can be used to create much more compact designs. Both the long optical path lengths and the high index contrast contribute to significant optical phase error as light propagates through the device. Therefore, silicon photonic arrayed waveguide gratings require active or passive phase correction following fabrication. Here we present the design and fabrication of compact silicon photonic arrayed waveguide gratings with channel spacings of 50, 10 and 1 GHz. The largest device, with 11 channels of 1 GHz spacing, has a footprint of only 1.1 cm². Using integrated thermo-optic phase shifters, the phase error is actively corrected. We present two methods of phase error correction and demonstrate state-of-the-art cross-talk performance for high index contrast arrayed waveguide gratings. As a demonstration of possible applications, we perform RF channelization with 1 GHz resolution. Additionally, we generate unique spectral filters by applying non-zero phase offsets calculated by the Gerchberg Saxton algorithm.

Electron-beam-induced information storage in hydrogenated amorphous silicon devices

DOEpatents

Yacobi, B.G.

1985-03-18

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge collection efficiency and thus in the charge collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage.

Low loss poly-silicon for high performance capacitive silicon modulators.

PubMed

Douix, Maurin; Baudot, Charles; Marris-Morini, Delphine; Valéry, Alexia; Fowler, Daivid; Acosta-Alba, Pablo; Kerdilès, Sébastien; Euvrard, Catherine; Blanc, Romuald; Beneyton, Rémi; Souhaité, Aurélie; Crémer, Sébastien; Vulliet, Nathalie; Vivien, Laurent; Boeuf, Frédéric

2018-03-05

Optical properties of poly-silicon material are investigated to be integrated in new silicon photonics devices, such as capacitive modulators. Test structure fabrication is done on 300 mm wafer using LPCVD deposition: 300 nm thick amorphous silicon layers are deposited on thermal oxide, followed by solid phase crystallization anneal. Rib waveguides are fabricated and optical propagation losses measured at 1.31 µm. Physical analysis (TEM ASTAR, AFM and SIMS) are used to assess the origin of losses. Optimal deposition and annealing conditions have been defined, resulting in 400 nm-wide rib waveguides with only 9.2-10 dB/cm losses.

Towards nanometer-spaced silicon contacts to proteins.

PubMed

Schukfeh, Muhammed I; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-18

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p(+) silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices' electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes' edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions' conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein's denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Strain effects in low-dimensional silicon MOS and AlGaN/GaN HEMT devices

NASA Astrophysics Data System (ADS)

Baykan, Mehmet Onur

Strained silicon technology is a well established method to enhance sub-100nm MOSFET performance. With the scalability of process-induced strain, strained silicon channels have been used in every advanced CMOS technology since the 90nm node. At the 22nm node, due to the detrimental short channel effects, non-planar silicon CMOS has emerged as a viable solution to sustain transistor scaling without compromising the device performance. Therefore, it is necessary to conduct a physics based investigation of the effects of mechanical strain in silicon MOS device performance enhancement, as the transverse and longitudinal device dimensions scale down for future technology nodes. While silicon is widely used as the material basis for logic transistors, AlGaN/GaN HEMTs promise a superior device platform over silicon based power MOSFETs for high-frequency and high-power applications. In contrast to the mature Si crystal growth technology, the abundance of defects in the GaN material system creates obstacles for the realization of a reliable AlGaN/GaN HEMT device technology. Due to the high levels of internal mechanical strain present in AlGaN/GaN HEMTs, it is of utmost importance to understand the impact of mechanical stress on AlGaN/GaN trap generation. First, we have investigated the underlying physics of the comparable electron mobility observed in (100) and (110) sidewall silicon double-gate FinFETs, which is different from the observed planar (100) and (110) electron mobility. By conducting a systematic experimental study, it is shown that the undoped body, metal gate induced stress, and volume-inversion effects do not explain the comparable electron mobility. Using a self-consistent double-gate FinFET simulator, we have showed that for (110) FinFETs, an increased population of electrons is obtained for the Delta2 valley due to the heavy nonparabolic confinement mass, leading to a comparable average electron transport effective mass for both orientations. The width dependent strain response of tri-gate p-type FinFETs are experimentally extracted using a 4-point bending jig. It is found that the low-field piezoresistance coefficient of p-type FinFETs can be modeled by using a weighted conductance average of the top and sidewall bulk piezoresistance coefficients. Next, the strain enhancement of p-type ballistic silicon nanowire MOSFETs is studied using sp3d 5s* basis nearest-neighbor tight-binding simulations coupled with a semiclassical top-of-the-barrier transport model. Size and orientation dependent strain enhancement of ballistic hole transport is explained by the strain-induced modification of the 1D nanowire valence band density-of-states. Further insights are provided for future p-type high-performance silicon nanowire logic devices. A physics based investigation is conducted to understand the strain effects on surface roughness limited electron mobility in silicon inversion layers. Based on the evidence from electrical and material characterization, a strain-induced surface morphology change is hypothesized. To model the observed electrical characteristics, we have employed a self-consistent MOSFET mobility simulator coupled with an ad hoc strain-induced roughness modification. The strain induced surface morphology change is found to be consistent among electrical and materials characterization, as well as transport simulations. In order to bridge the gap between the drift-diffusion based models for long-channel devices and the quasi-ballistic models for nanoscale channels, a unified carrier transport model is developed using an updated one-flux theory. Including the high-field and carrier confinement effects, a surface-potential based analytical transmission expression is obtained for the entire MOSFET operation range. With the new channel transmission equation and average carrier drift velocity, a new expression for channel ballisticity is defined. Impact of mechanical strain on carrier transport for both nMOSFETs and pMOSFETs in both linear and saturation regimes is explained using the new channel transmission definitions. To understand the impact of mechanical strain on AlGaN/GaN HEMT trap generation, we have devised an experimental method to obtain the photon flux-normalized relative areal trap density distribution using photoionization spectroscopy technique. The details of the trap extraction method and the experimental setup are given. Using this setup, the trap characteristics are extracted for both ungated transmission line module (TLM) and gated HEMT devices from both Si and SiC substrates. The changes in the device trap characteristics are emphasized before and after electrical stressing. It is found through the step-voltage stressing of the AlGaN/GaN HEMT gate stack that the device degradation is due to the near bandgap trap generation, which are shown to be related to the structural defects in GaN.

A precision device needs precise simulation: Software description of the CBM Silicon Tracking System

NASA Astrophysics Data System (ADS)

Malygina, Hanna; Friese, Volker; CBM Collaboration

2017-10-01

Precise modelling of detectors in simulations is the key to the understanding of their performance, which, in turn, is a prerequisite for the proper design choice and, later, for the achievement of valid physics results. In this report, we describe the implementation of the Silicon Tracking System (STS), the main tracking device of the CBM experiment, in the CBM software environment. The STS makes uses of double-sided silicon micro-strip sensors with double metal layers. We present a description of transport and detector response simulation, including all relevant physical effects like charge creation and drift, charge collection, cross-talk and digitization. Of particular importance and novelty is the description of the time behaviour of the detector, since its readout will not be externally triggered but continuous. We also cover some aspects of local reconstruction, which in the CBM case has to be performed in real-time and thus requires high-speed algorithms.

Comparative analysis for evaluating the traceability of interventional devices using blood vessel phantom models made of PVA-H or silicone.

PubMed

Yu, Chang-Ho; Kwon, Tae-Kyu; Park, Chan Hee; Ohta, Makoto; Kim, Sung Hoon

2015-01-01

In this paper, we investigated the parameters with effective traceability to assess the mechanical properties of interventional devices. In our evaluation system, a box-shaped poly (vinyl alcohol) hydrogel (PVA-H) and silicone were prepared with realistic geometry, and the measurement and evaluation of traceability were carried out on devices using load hand force. The phantom models had a total of five curve pathways to reach the aneurysm sac. Traceability depends on the performance of the interventional devices in order to pass through the curved part of the model simulation track. The traceability of the guide wire was found to be much better than that of the balloon and stent loading catheter, as it reached the aneurysm sac in both phantom models. Observation using the video record is another advantage of our system, because the high transparency of the materials with silicone and PVA-H can allow visualization of the inside of an artery.

Modeling and Simulation of - and Silicon Germanium-Base Bipolar Transistors Operating at a Wide Range of Temperatures.

NASA Astrophysics Data System (ADS)

Shaheed, M. Reaz

1995-01-01

Higher speed at lower cost and at low power consumption is a driving force for today's semiconductor technology. Despite a substantial effort toward achieving this goal via alternative technologies such as III-V compounds, silicon technology still dominates mainstream electronics. Progress in silicon technology will continue for some time with continual scaling of device geometry. However, there are foreseeable limits on achievable device performance, reliability and scaling for room temperature technologies. Thus, reduced temperature operation is commonly viewed as a means for continuing the progress towards higher performance. Although silicon CMOS will be the first candidate for low temperature applications, bipolar devices will be used in a hybrid fashion, as line drivers or in limited critical path elements. Silicon -germanium-base bipolar transistors look especially attractive for low-temperature bipolar applications. At low temperatures, various new physical phenomena become important in determining device behavior. Carrier freeze-out effects which are negligible at room temperature, become of crucial importance for analyzing the low temperature device characteristics. The conventional Pearson-Bardeen model of activation energy, used for calculation of carrier freeze-out, is based on an incomplete picture of the physics that takes place and hence, leads to inaccurate results at low temperatures. Plasma -induced bandgap narrowing becomes more pronounced in device characteristics at low temperatures. Even with modern numerical simulators, this effect is not well modeled or simulated. In this dissertation, improved models for such physical phenomena are presented. For accurate simulation of carrier freeze-out, the Pearson-Bardeen model has been extended to include the temperature dependence of the activation energy. The extraction of the model is based on the rigorous, first-principle theoretical calculations available in the literature. The new model is shown to provide consistently accurate values for base sheet resistance for both Si- and SiGe-base transistors over a wide range of temperatures. A model for plasma-induced bandgap narrowing suitable for implementation in a numerical simulator has been developed. The appropriate method of incorporating this model in a drift -diffusion solver is described. The importance of including this model for low temperature simulation is demonstrated. With these models in place, the enhanced simulator has been used for evaluating and designing the Si- and SiGe-base bipolar transistors. Silicon-germanium heterojunction bipolar transistors offer significant performance and cost advantages over conventional technologies in the production of integrated circuits for communications, computer and transportation applications. Their high frequency performance at low cost, will find widespread use in the currently exploding wireless communication market. However, the high performance SiGe-base transistors are prone to have a low common-emitter breakdown voltage. In this dissertation, a modification in the collector design is proposed for improving the breakdown voltage without sacrificing the high frequency performance. A comprehensive simulation study of p-n-p SiGe-base transistors has been performed. Different figures of merit such as drive current, current gain, cut -off frequency and Early voltage were compared between a graded germanium profile and an abrupt germanium profile. The differences in the performance level between the two profiles diminishes as the base width is scaled down.

Electron-beam-induced information storage in hydrogenated amorphous silicon device

DOEpatents

Yacobi, Ben G.

1986-01-01

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge-collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge-collection efficiency; and thus in the charge-collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage, in the device, which darkened areas can be restored to their original charge-collection efficiency by heating the hydrogenated amorphous silicon to a temperature of about 100.degree. C. to 250.degree. C. for a sufficient period of time to provide for such restoration.

Biocompatible materials developments for new medical implants.

PubMed

Hodgins, Diana; Wasikiewicz, J M; Grahn, M F; Paul, D; Roohpour, N; Vadgama, P; Silmon, Angela M; Cousins, Bernard; Verdon, Brian

2007-10-01

Recent work on modifying silicone rubber to improve water permeability and biocompatibility is described. In addition, modifications to the interface between an active implanted device and the body are reported, which have led to reduced power consumption and improved device performance.

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices

PubMed Central

Bi, Lei; Hu, Juejun; Jiang, Peng; Kim, Hyun Suk; Kim, Dong Hun; Onbasli, Mehmet Cengiz; Dionne, Gerald F.; Ross, Caroline A.

2013-01-01

Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4)O3−δ and polycrystalline (CeY2)Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2)Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates. PMID:28788379

Extreme High and Low Temperature Operation of the Silicon-On-Insulator Type CHT-OPA Operational Amplifier

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

A new operational amplifier chip based on silicon-on-insulator technology was evaluated for potential use in extreme temperature environments. The CHT-OPA device is a low power, precision operational amplifier with rail-to-rail output swing capability, and it is rated for operation between -55 C and +225 C. A unity gain inverting circuit was constructed utilizing the CHT-OPA chip and a few passive components. The circuit was evaluated in the temperature range from -190 C to +200 C in terms of signal gain and phase shift, and supply current. The investigations were carried out to determine suitability of this device for use in space exploration missions and aeronautic applications under wide temperature incursion. Re-restart capability at extreme temperatures, i.e. power switched on while the device was soaked at extreme temperatures, was also investigated. In addition, the effects of thermal cycling under a wide temperature range on the operation of this high performance amplifier were determined. The results from this work indicate that this silicon-on-insulator amplifier chip maintained very good operation between +200 C and -190 C. The limited thermal cycling had no effect on the performance of the amplifier, and it was able to re-start at both -190 C and +200 C. In addition, no physical degradation or packaging damage was introduced due to either extreme temperature exposure or thermal cycling. The good performance demonstrated by this silicon-on-insulator operational amplifier renders it a potential candidate for use in space exploration missions or other environments under extreme temperatures. Additional and more comprehensive characterization is, however, required to establish the reliability and suitability of such devices for long term use in extreme temperature applications.

Integrated optical silicon IC compatible nanodevices for biosensing applications

NASA Astrophysics Data System (ADS)

Lechuga, Laura M.; Sepulveda, Borja; Llobera, Andreu; Calle, Ana; Dominguez, Carlos M.

2003-04-01

Biological and chemical sensing is one of the application fields where integrated optical nanodevices can play an important role [1]. We present a Silicon Integrated Mach-Zehnder Interferometer Nanodevice using a Total Internal Refraction waveguide configuration. The induced changes due to a biomolecular interactions in the effective refractive index of the waveguide,is monitored by the measurement of the change in the properties of the propagating light. For using this device as a biosensor, the waveguides of the structure must verify two conditions: work in the monomode regime and to have a Surface Sensivity as high as possible in the sensing arm. The MZI device structure is: (i) a Si wafer with a 500 mm thickness (ii) a 2 mm thick thermal Silicon-Oxide layer with a refractive index of 1.46 (iii) a LPCVD Silicon Nitride layer of 100 nm thickness and a refractive index of 2.00, which is used as the guiding layer. To achieve monomode behavior is needed to define a rib structure, with a depth of only 3 nm, on the Silicon Nitride layer by a lithographic step. This rib structure is performed by RIE and is the most critical step in the microfabrication of the device. Over the structure a protective layer of LPCVD SiO2 is deposited, with a 2 mm thickness and a refractive index of 1.46, which is patterned (photolithography) and etched (RIE) to define the sensing arm. The high sensivity of these devices makes them quite suitable for biosensing applications. For that, without loosing their activity the receptors biomolecules are covanlently immobilized, at nanometer scale , on the sensor area surface. Biospecific molecular recognition takes places when the complementary analyte to the receptor is flowed over the receptor using a flow system. Several biosensing applications have been performed with this device as enviromental pollutant control, immunosensing or genetic detection.

Study of silicone-based materials for the packaging of optoelectronic devices

NASA Astrophysics Data System (ADS)

Lin, Yeong-Her

The first part of this work is to evaluate the main materials used for the packaging of high power light-emitting diodes (LEDs), i.e., the die attach materials, the encapsulant materials, and high color rendering index(CRI) sol-gel composite materials. All of these materials had been discussed the performance, reliability, and issues in high power LED packages. High power white LEDs are created either from blue or near-ultraviolet chips encapsulated with a yellow phosphor, or from red-green-blue LED light mixing systems. The phosphor excited by blue LED chip was mostly used in experiment of this dissertation. The die attach materials contains filler particles possessing a maximum particle size less than 1.5 mum in diameter blended with epoxy polymer matrix. Such compositions enable thin bond line thickness, which decreases thermal resistance that exists between thermal interface materials and the corresponding mating surfaces. The thermal conductivity of nano silver die attach materials is relatively low, the thermal resistance from the junction to board is just 1.6 KW-1 in the bond line thickness of 5.3 mum, which is much lower than the thermal resistance using conventional die attach materials. The silicone die attach adhesive made in the lab cures through the free radical reaction of epoxy-functional organopolysiloxane and through the hydrosilylation reaction between alkenyl-functional organopolysiloxane and silicone-boned hydrogen-functional organopolysiloxane. By the combination of the free radical reaction and the hydrosilylation reaction, the low-molecular-weight silicone oil will not be out-migrated and not contaminate wire bondability to the LED chip and lead frame. Hence, the silicone die attach adhesive made in the lab can pass all reliability tests, such as operating life test JEDEC 85°C/85RH and room temperature operating life test. For LED encapsulating materials, most of commercial silicone encapsulants still suffer thermal/radiation induced degradations, and thus cause reliability issues and shorten the lifetime. A new high performance silicone has been developed and its performance has been compared with other commercial silicone products in the packaging of high power white LEDs. The high performance silicone also has better results than commercial high refractive index silicone and optical grade epoxy under JEDEC reliability standard for moisture sensitivity test. In synthesis of red dye-doped particles by sol-gel method, it is a novel method to get high color rendering index (CRI) LEDs. These red dye-doped particles, with average diameter of 5 mum, can be mixed with liquid encapsulants to form a uniform distribution in polymer matrix. The red dye-doped particles can be excited by phosphor-emitted yellow light instead of blue light from LED chip. Therefore, warm white LEDs with high CRI can be gotten at high lumen efficiency. The second part of this work is silicone elastomer for biomedical applications, especially in making urological implantable devices. A cross-linked, heat curable, addition-reaction silicone material is prepared. The material may be molded or formed into one or more medical devices. One such medical device could be a catheter used in urological applications. The material is a long term indwelling material that resists encrustation like a metal stent, but is more comfortable because it is silicone-based. The material can be made relatively cheaply compared to metal stents. Furthermore, the material is biocompatible with bladder epithelial cells.

Effect of tetramethylammonium hydroxide/isopropyl alcohol wet etching on geometry and surface roughness of silicon nanowires fabricated by AFM lithography

PubMed Central

Yusoh, Siti Noorhaniah

2016-01-01

Summary The optimization of etchant parameters in wet etching plays an important role in the fabrication of semiconductor devices. Wet etching of tetramethylammonium hydroxide (TMAH)/isopropyl alcohol (IPA) on silicon nanowires fabricated by AFM lithography is studied herein. TMAH (25 wt %) with different IPA concentrations (0, 10, 20, and 30 vol %) and etching time durations (30, 40, and 50 s) were investigated. The relationships between etching depth and width, and etching rate and surface roughness of silicon nanowires were characterized in detail using atomic force microscopy (AFM). The obtained results indicate that increased IPA concentration in TMAH produced greater width of the silicon nanowires with a smooth surface. It was also observed that the use of a longer etching time causes more unmasked silicon layers to be removed. Importantly, throughout this study, wet etching with optimized parameters can be applied in the design of the devices with excellent performance for many applications. PMID:27826521

High-Performance and Omnidirectional Thin-Film Amorphous Silicon Solar Cell Modules Achieved by 3D Geometry Design.

PubMed

Yu, Dongliang; Yin, Min; Lu, Linfeng; Zhang, Hanzhong; Chen, Xiaoyuan; Zhu, Xufei; Che, Jianfei; Li, Dongdong

2015-11-01

High-performance thin-film hydrogenated amorphous silicon solar cells are achieved by combining macroscale 3D tubular substrates and nanoscaled 3D cone-like antireflective films. The tubular geometry delivers a series of advantages for large-scale deployment of photovoltaics, such as omnidirectional performance, easier encapsulation, decreased wind resistance, and easy integration with a second device inside the glass tube. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

NASA Astrophysics Data System (ADS)

Kim, Jong Cheol; Kim, Jongsik; Xin, Yan; Lee, Jinhyung; Kim, Young-Gyun; Subhash, Ghatu; Singh, Rajiv K.; Arjunan, Arul C.; Lee, Haigun

2018-05-01

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (˜3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

PubMed

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Strain-Induced Spin-Resonance Shifts in Silicon Devices

NASA Astrophysics Data System (ADS)

Pla, J. J.; Bienfait, A.; Pica, G.; Mansir, J.; Mohiyaddin, F. A.; Zeng, Z.; Niquet, Y. M.; Morello, A.; Schenkel, T.; Morton, J. J. L.; Bertet, P.

2018-04-01

In spin-based quantum-information-processing devices, the presence of control and detection circuitry can change the local environment of a spin by introducing strain and electric fields, altering its resonant frequencies. These resonance shifts can be large compared to intrinsic spin linewidths, and it is therefore important to study, understand, and model such effects in order to better predict device performance. We investigate a sample of bismuth donor spins implanted in a silicon chip, on top of which a superconducting aluminum microresonator is fabricated. The on-chip resonator provides two functions: it produces local strain in the silicon due to the larger thermal contraction of the aluminum, and it enables sensitive electron spin-resonance spectroscopy of donors close to the surface that experience this strain. Through finite-element strain simulations, we are able to reconstruct key features of our experiments, including the electron spin-resonance spectra. Our results are consistent with a recently observed mechanism for producing shifts of the hyperfine interaction for donors in silicon, which is linear with the hydrostatic component of an applied strain.

Increasing Stabilized Performance Of Amorphous Silicon Based Devices Produced By Highly Hydrogen Diluted Lower Temperature Plasma Deposition.

DOEpatents

Li, Yaun-Min; Bennett, Murray S.; Yang, Liyou

1999-08-24

High quality, stable photovoltaic and electronic amorphous silicon devices which effectively resist light-induced degradation and current-induced degradation, are produced by a special plasma deposition process. Powerful, efficient single and multi-junction solar cells with high open circuit voltages and fill factors and with wider bandgaps, can be economically fabricated by the special plasma deposition process. The preferred process includes relatively low temperature, high pressure, glow discharge of silane in the presence of a high concentration of hydrogen gas.

Increased Stabilized Performance Of Amorphous Silicon Based Devices Produced By Highly Hydrogen Diluted Lower Temperature Plasma Deposition.

DOEpatents

Li, Yaun-Min; Bennett, Murray S.; Yang, Liyou

1997-07-08

High quality, stable photovoltaic and electronic amorphous silicon devices which effectively resist light-induced degradation and current-induced degradation, are produced by a special plasma deposition process. Powerful, efficient single and multi-junction solar cells with high open circuit voltages and fill factors and with wider bandgaps, can be economically fabricated by the special plasma deposition process. The preferred process includes relatively low temperature, high pressure, glow discharge of silane in the presence of a high concentration of hydrogen gas.

Protection of microelectronic devices during packaging

DOEpatents

Peterson, Kenneth A.; Conley, William R.

2002-01-01

The present invention relates to a method of protecting a microelectronic device during device packaging, including the steps of applying a water-insoluble, protective coating to a sensitive area on the device; performing at least one packaging step; and then substantially removing the protective coating, preferably by dry plasma etching. The sensitive area can include a released MEMS element. The microelectronic device can be disposed on a wafer. The protective coating can be a vacuum vapor-deposited parylene polymer, silicon nitride, metal (e.g. aluminum or tungsten), a vapor deposited organic material, cynoacrylate, a carbon film, a self-assembled monolayered material, perfluoropolyether, hexamethyldisilazane, or perfluorodecanoic carboxylic acid, silicon dioxide, silicate glass, or combinations thereof. The present invention also relates to a method of packaging a microelectronic device, including: providing a microelectronic device having a sensitive area; applying a water-insoluble, protective coating to the sensitive area; providing a package; attaching the device to the package; electrically interconnecting the device to the package; and substantially removing the protective coating from the sensitive area.

Temporary coatings for protection of microelectronic devices during packaging

DOEpatents

Peterson, Kenneth A.; Conley, William R.

2005-01-18

The present invention relates to a method of protecting a microelectronic device during device packaging, including the steps of applying a water-insoluble, temporary protective coating to a sensitive area on the device; performing at least one packaging step; and then substantially removing the protective coating, preferably by dry plasma etching. The sensitive area can include a released MEMS element. The microelectronic device can be disposed on a wafer. The protective coating can be a vacuum vapor-deposited parylene polymer, silicon nitride, metal (e.g. aluminum or tungsten), a vapor deposited organic material, cynoacrylate, a carbon film, a self-assembled monolayered material, perfluoropolyether, hexamethyldisilazane, or perfluorodecanoic carboxylic acid, silicon dioxide, silicate glass, or combinations thereof. The present invention also relates to a method of packaging a microelectronic device, including: providing a microelectronic device having a sensitive area; applying a water-insoluble, protective coating to the sensitive area; providing a package; attaching the device to the package; electrically interconnecting the device to the package; and substantially removing the protective coating from the sensitive area.

Development of an Extreme High Temperature n-type Ohmic Contact to Silicon Carbide

NASA Technical Reports Server (NTRS)

Evans, Laura J.; Okojie, Robert S.; Lukco, Dorothy

2011-01-01

We report on the initial demonstration of a tungsten-nickel (75:25 at. %) ohmic contact to silicon carbide (SiC) that performed for up to fifteen hours of heat treatment in argon at 1000 C. The transfer length method (TLM) test structure was used to evaluate the contacts. Samples showed consistent ohmic behavior with specific contact resistance values averaging 5 x 10-4 -cm2. The development of this contact metallization should allow silicon carbide devices to operate more reliably at the present maximum operating temperature of 600 C while potentially extending operations to 1000 C. Introduction Silicon Carbide (SiC) is widely recognized as one of the materials of choice for high temperature, harsh environment sensors and electronics due to its ability to survive and continue normal operation in such environments [1]. Sensors and electronics in SiC have been developed that are capable of operating at temperatures of 600 oC. However operating these devices at the upper reliability temperature threshold increases the potential for early degradation. Therefore, it is important to raise the reliability temperature ceiling higher, which would assure increased device reliability when operated at nominal temperature. There are also instances that require devices to operate and survive for prolonged periods of time above 600 oC [2, 3]. This is specifically needed in the area of hypersonic flight where robust sensors are needed to monitor vehicle performance at temperature greater than 1000 C, as well as for use in the thermomechanical characterization of high temperature materials (e.g. ceramic matrix composites). While SiC alone can withstand these temperatures, a major challenge is to develop reliable electrical contacts to the device itself in order to facilitate signal extraction

Nano-islands integrated evanescence-based lab-on-a-chip on silica-on-silicon and polydimethylsiloxane hybrid platform for detection of recombinant growth hormone

PubMed Central

Ozhikandathil, J.; Packirisamy, M.

2012-01-01

Integration of nano-materials in optical microfluidic devices facilitates the realization of miniaturized analytical systems with enhanced sensing abilities for biological and chemical substances. In this work, a novel method of integration of gold nano-islands in a silica-on-silicon-polydimethylsiloxane microfluidic device is reported. The device works based on the nano-enhanced evanescence technique achieved by interacting the evanescent tail of propagating wave with the gold nano-islands integrated on the core of the waveguide resulting in the modification of the propagating UV-visible spectrum. The biosensing ability of the device is investigated by finite-difference time-domain simulation with a simplified model of the device. The performance of the proposed device is demonstrated for the detection of recombinant growth hormone based on antibody-antigen interaction. PMID:24106526

Micrometer size polarization independent depletion-type photonic modulator in Silicon On Insulator

NASA Astrophysics Data System (ADS)

Gardes, F. Y.; Tsakmakidis, K. L.; Thomson, D.; Reed, G. T.; Mashanovich, G. Z.; Hess, O.; Avitabile, D.

2007-04-01

The trend in silicon photonics, in the last few years has been to reduce waveguide size to obtain maximum gain in the real estate of devices as well as to increase the performance of active devices. Using different methods for the modulation, optical modulators in silicon have seen their bandwidth increased to reach multi GHz frequencies. In order to simplify fabrication, one requirement for a waveguide, as well as for a modulator, is to retain polarisation independence in any state of operation and to be as small as possible. In this paper we provide a way to obtain polarization independence and improve the efficiency of an optical modulator using a V-shaped pn junction base on the natural etch angle of silicon, 54.7 deg. This modulator is compared to a flat junction depletion type modulator of the same size and doping concentration.

Probing Photocurrent Nonuniformities in the Subcells of Monolithic Perovskite/Silicon Tandem Solar Cells.

PubMed

Song, Zhaoning; Werner, Jérémie; Shrestha, Niraj; Sahli, Florent; De Wolf, Stefaan; Niesen, Björn; Watthage, Suneth C; Phillips, Adam B; Ballif, Christophe; Ellingson, Randy J; Heben, Michael J

2016-12-15

Perovskite/silicon tandem solar cells with high power conversion efficiencies have the potential to become a commercially viable photovoltaic option in the near future. However, device design and optimization is challenging because conventional characterization methods do not give clear feedback on the localized chemical and physical factors that limit performance within individual subcells, especially when stability and degradation is a concern. In this study, we use light beam induced current (LBIC) to probe photocurrent collection nonuniformities in the individual subcells of perovskite/silicon tandems. The choices of lasers and light biasing conditions allow efficiency-limiting effects relating to processing defects, optical interference within the individual cells, and the evolution of water-induced device degradation to be spatially resolved. The results reveal several types of microscopic defects and demonstrate that eliminating these and managing the optical properties within the multilayer structures will be important for future optimization of perovskite/silicon tandem solar cells.

3D hybrid integrated lasers for silicon photonics

NASA Astrophysics Data System (ADS)

Song, B.; Pinna, S.; Liu, Y.; Megalini, L.; Klamkin, J.

2018-02-01

A novel 3D hybrid integration platform combines group III-V materials and silicon photonics to yield high-performance lasers is presented. This platform is based on flip-chip bonding and vertical optical coupling integration. In this work, indium phosphide (InP) devices with monolithic vertical total internal reflection turning mirrors were bonded to active silicon photonic circuits containing vertical grating couplers. Greater than 2 mW of optical power was coupled into a silicon waveguide from an InP laser. The InP devices can also be bonded directly to the silicon substrate, providing an efficient path for heat dissipation owing to the higher thermal conductance of silicon compared to InP. Lasers realized with this technique demonstrated a thermal impedance as low as 6.2°C/W, allowing for high efficiency and operation at high temperature. InP reflective semiconductor optical amplifiers were also integrated with 3D hybrid integration to form integrated external cavity lasers. These lasers demonstrated a wavelength tuning range of 30 nm, relative intensity noise lower than -135 dB/Hz and laser linewidth of 1.5 MHz. This platform is promising for integration of InP lasers and photonic integrated circuits on silicon photonics.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Surface chemistry relevant to material processing for semiconductor devices

NASA Astrophysics Data System (ADS)

Okada, Lynne Aiko

Metal-oxide-semiconductor (MOS) structures are the core of many modern integrated circuit (IC) devices. Each material utilized in the different regions of the device has its own unique chemistry. Silicon is the base semiconductor material used in the majority of these devices. With IC device complexity increasing and device dimensions decreasing, understanding material interactions and processing becomes increasingly critical. Hsb2 desorption is the rate-limiting step in silicon growth using silane under low temperature conditions. Activation energies for Hsb2 desorption measured during Si chemical vapor deposition (CVD) versus single-crystal studies are found to be significantly lower. It has been proposed that defect sites on the silicon surface could explain the observed differences. Isothermal Hsb2 desorption studies using laser induced thermal desorption (LITD) techniques have addressed this issue. The growth of low temperature oxides is another relevant issue for fabrication of IC devices. Recent studies using 1,4-disilabutane (DSB) (SiHsb3CHsb2CHsb2SiHsb3) at 100sp°C in ambient Osb2 displayed the successful low temperature growth of silicon dioxide (SiOsb2). However, these studies provided no information about the deposition mechanism. We performed LITD and Fourier transform infrared (FTIR) studies on single-crystal and porous silicon surfaces to examine the adsorption, decomposition, and desorption processes to determine the deposition mechanism. Titanium nitride (TiN) diffusion barriers are necessary in modern metallization structures. Controlled deposition using titanium tetrachloride (TiClsb4) and ammonia (NHsb3) has been demonstrated using atomic layered processing (ALP) techniques. We intended to study the sequential deposition method by monitoring the surface intermediates using LITD techniques. However, formation of a Cl impurity source, ammonium chloride (NHsb4sp+Clsp-), was observed, thereby, limiting our ability for effective studies. Tetrakis(dimethylamino)titanium (Tilbrack N\\{CHsb3\\}sb2rbracksb4) (TDMAT) is another precursor used in the CVD deposition of TiN films in IC devices. Thermal decomposition studies have demonstrated deviations from conformal deposition. Successful conformal deposition may be affected by readsorption of the reaction product, dimethylamine (HNlbrack CHsb3rbracksb2). Detailed studies were performed using LITD techniques in order to understand the adsorption and desorption kinetics of TDMAT and dimethylamine to gain insights about the conformal deposition of TiN.

High-Bandgap Silicon Nanocrystal Solar Cells: Device Fabrication, Characterization, and Modeling

NASA Astrophysics Data System (ADS)

Löper, Philipp; Canino, Mariaconcetta; Schnabel, Manuel; Summonte, Caterina; Janz, Stefan; Zacharias, Margit

Silicon nanocrystals (Si NCs) embedded in Si-based dielectrics provide a Si-based high-bandgap material (1.7 eV) and enable the construction of crystalline Si tandem solar cells. This chapter focusses on Si NC embedded in silicon carbide, because silicon carbide offers electrical conduction through the matrix material. The material development is reviewed, and optical modeling is introduced as a powerful method to monitor the four material components, amorphous and crystalline silicon as well as amorphous and crystalline silicon carbide. In the second part of this chapter, recent device developments for the photovoltaic characterization of Si NCs are examined. The controlled growth of Si NCs involves high-temperature annealing which deteriorates the properties of any previously established selective contacts. A membrane-based device is presented to overcome these limitations. In this approach, the formation of both selective contacts is carried out after high-temperature annealing and is therefore not affected by the latter. We examine p-i-n solar cells with an intrinsic region made of Si NCs embedded in silicon carbide. Device failure due to damaged insulation layers is analyzed by light beam-induced current measurements. An optical model of the device is presented for improving the cell current. A characterization scheme for Si NC p-i-n solar cells is presented which aims at determining the fundamental transport and recombination properties, i.e., the effective mobility lifetime product, of the nanocrystal layer at device level. For this means, an illumination-dependent analysis of Si NC p-i-n solar cells is carried out within the framework of the constant field approximation. The analysis builds on an optical device model, which is used to assess the photogenerated current in each of the device layers. Illumination-dependent current-voltage curves are modelled with a voltage-dependent current collection function with only two free parameters, and excellent agreement is found between theory and experiment. An effective mobility lifetime product of 10-10 cm2/V is derived and confirmed independently from an alternative method. The procedure discussed in this chapter is proposed as a characterization scheme for further material development, providing an optimization parameter (the effective mobility lifetime product) relevant for the photovoltaic performance of Si NC films.

Nanostructured Silicon Used for Flexible and Mobile Electricity Generation.

PubMed

Sun, Baoquan; Shao, Mingwang; Lee, Shuitong

2016-12-01

The use of nanostructured silicon for the generation of electricity in flexible and mobile devices is reviewed. This field has attracted widespread interest in recent years due to the emergence of plastic electronics. Such developments are likely to alter the nature of power sources in the near future. For example, flexible photovoltaic cells can supply electricity to rugged and collapsible electronics, biomedical devices, and conformable solar panels that are integrated with the curved surfaces of vehicles or buildings. Here, the unique optical and electrical properties of nanostructured silicon are examined, with regard to how they can be exploited in flexible photovoltaics, thermoelectric generators, and piezoelectric devices, which serve as power generators. Particular emphasis is placed on organic-silicon heterojunction photovoltaic devices, silicon-nanowire-based thermoelectric generators, and core-shell silicon/silicon oxide nanowire-based piezoelectric devices, because they are flexible, lightweight, and portable. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Determination of a Definition of Solar Grade Silicon

NASA Technical Reports Server (NTRS)

Hill, D. E.; Gutsche, H. W.

1975-01-01

A definition of solar grade silicon was determined by investigating the singular and the combined effect of the impurities usually found in metallurgical grade silicon on solar cell device performance. The impurity matrix was defined by Jet Propulsion Laboratory Technical Direction Memorandum. The initial work was focussed on standardizing the solar cell process and test procedure, growing baseline crystals, growing crystals contaminated with carbon, iron, nickel, zirconium, aluminum and vanadium, solar blank preparation, and material characterization.

Performance Evaluation of an Automotive-Grade, High Speed Gate Driver for SiC FETs, Type UCC27531, Over a Wide Temperature Range

NASA Technical Reports Server (NTRS)

Boomer, Kristen; Hammoud, Ahmad

2015-01-01

Silicon carbide (SiC) devices are becoming widely used in electronic power circuits as replacement for conventional silicon parts due to their attractive properties that include low on-state resistance, high temperature tolerance, and high frequency operation. These attributes have a significant impact by reducing system weight, saving board space, and conserving power. In this work, the performance of an automotive-grade high speed gate driver with potential use in controlling SiC FETs (field-Effect Transistors) in converters or motor control applications was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Mode-converting coupler for silicon-on-sapphire devices

NASA Astrophysics Data System (ADS)

Zlatanovic, S.; Offord, B. W.; Owen, M.; Shimabukuro, R.; Jacobs, E. W.

2015-02-01

Silicon-on-sapphire devices are attractive for the mid-infrared optical applications up to 5 microns due to the low loss of both silicon and sapphire in this wavelength band. Designing efficient couplers for silicon-on-sapphire devices presents a challenge due to a highly confined mode in silicon and large values of refractive index of both silicon and sapphire. Here, we present design, fabrication, and measurements of a mode-converting coupler for silicon-on-sapphire waveguides. We utilize a mode converter layout that consists of a large waveguide that is overlays a silicon inverse tapered waveguide. While this geometry was previously utilized for silicon-on-oxide devices, the novelty is in using materials that are compatible with the silicon-on-sapphire platform. In the current coupler the overlaying waveguide is made of silicon nitride. Silicon nitride is the material of choice because of the large index of refraction and low absorption from near-infrared to mid-infrared. The couplers were fabricated using a 0.25 micron silicon-on-sapphire process. The measured coupling loss from tapered lensed silica fibers to the silicon was 4.8dB/coupler. We will describe some challenges in fabrication process and discuss ways to overcome them.

An extensive investigation of work function modulated trapezoidal recessed channel MOSFET

NASA Astrophysics Data System (ADS)

Lenka, Annada Shankar; Mishra, Sikha; Mishra, Satyaranjan; Bhanja, Urmila; Mishra, Guru Prasad

2017-11-01

The concept of silicon on insulator (SOI) and grooved gate help to lessen the short channel effects (SCEs). Again the work function modulation along the metal gate gives a better drain current due to the uniform electric field along the channel. So all these concepts are combined and used in the proposed MOSFET structure for more improved performance. In this work, trapezoidal recessed channel silicon on insulator (TRC-SOI) MOSFET and work function modulated trapezoidal recessed channel silicon on insulator (WFM-TRC-SOI) MOSFET are compared with DC and RF parameters and later linearity of both the devices is tested. An analytical model is formulated by using a 2-D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. In this work we analyze the effect of negative junction depth and the corner angle on various device parameters such as minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage. The analysis interprets that the switching performance of WFM-TRC-SOI MOSFET surpasses TRC-SOI MOSFET in terms of high Ion/Ioff ratio and also the proposed structure can minimize the short channel effects (SCEs) in RF application. The validity of proposed model has been verified with simulation result performed on Sentaurus TCAD device simulator.

A flexible piezoresistive carbon black network in silicone rubber for wide range deformation and strain sensing

NASA Astrophysics Data System (ADS)

Zhu, Jianxiong; Wang, Hai; Zhu, Yali

2018-01-01

This work presents the design, fabrication, and measurement of a piezoresistive device with a carbon black (CB) particle network in a highly flexible silicone rubber for large deformation and wide range strain sensing. The piezoresistive composite film was fabricated with a mixture of silicone rubber and CB filler particles. The test results showed that the CB particle network in the silicone rubber strongly affected the resistance of the device during the process of drawing and its recovery. We found that the 50% volume ratio of CB filler particles showed a lower relative resistance than the 33.3% volume ratio of CB filler particles, but with an advantage of good resistance recovery stability and a smaller perturbation error (smaller changed resistance) during the periodic back and forth linear motor test. With both having a 50% volume ratio of CB filler particles and a 33.3% volume ratio of CB filler particles, one can reach up to 200% strain with resistances 18 kΩ and 110 kΩ, respectively. We also found that the relative resistance increased in an approximately linear relationship corresponding to the value of step-increased instantaneous length for the reported device. Moreover, an application test through hand drawing was used to demonstrate the piezoresistive performance of the device, which showed that the reported device was capable of measuring the instantaneous length with large deformation.

Near-infrared sub-bandgap all-silicon photodetectors: state of the art and perspectives.

PubMed

Casalino, Maurizio; Coppola, Giuseppe; Iodice, Mario; Rendina, Ivo; Sirleto, Luigi

2010-01-01

Due to recent breakthroughs, silicon photonics is now the most active discipline within the field of integrated optics and, at the same time, a present reality with commercial products available on the market. Silicon photodiodes are excellent detectors at visible wavelengths, but the development of high-performance photodetectors on silicon CMOS platforms at wavelengths of interest for telecommunications has remained an imperative but unaccomplished task so far. In recent years, however, a number of near-infrared all-silicon photodetectors have been proposed and demonstrated for optical interconnect and power-monitoring applications. In this paper, a review of the state of the art is presented. Devices based on mid-bandgap absorption, surface-state absorption, internal photoemission absorption and two-photon absorption are reported, their working principles elucidated and their performance discussed and compared.

Near-Infrared Sub-Bandgap All-Silicon Photodetectors: State of the Art and Perspectives

PubMed Central

Casalino, Maurizio; Coppola, Giuseppe; Iodice, Mario; Rendina, Ivo; Sirleto, Luigi

2010-01-01

Due to recent breakthroughs, silicon photonics is now the most active discipline within the field of integrated optics and, at the same time, a present reality with commercial products available on the market. Silicon photodiodes are excellent detectors at visible wavelengths, but the development of high-performance photodetectors on silicon CMOS platforms at wavelengths of interest for telecommunications has remained an imperative but unaccomplished task so far. In recent years, however, a number of near-infrared all-silicon photodetectors have been proposed and demonstrated for optical interconnect and power-monitoring applications. In this paper, a review of the state of the art is presented. Devices based on mid-bandgap absorption, surface-state absorption, internal photoemission absorption and two-photon absorption are reported, their working principles elucidated and their performance discussed and compared. PMID:22163487

Use of silicon oxynitride as a sacrificial material for microelectromechanical devices

DOEpatents

Habermehl, Scott D.; Sniegowski, Jeffry J.

2001-01-01

The use of silicon oxynitride (SiO.sub.x N.sub.y) as a sacrificial material for forming a microelectromechanical (MEM) device is disclosed. Whereas conventional sacrificial materials such as silicon dioxide and silicate glasses are compressively strained, the composition of silicon oxynitride can be selected to be either tensile-strained or substantially-stress-free. Thus, silicon oxynitride can be used in combination with conventional sacrificial materials to limit an accumulation of compressive stress in a MEM device; or alternately the MEM device can be formed entirely with silicon oxynitride. Advantages to be gained from the use of silicon oxynitride as a sacrificial material for a MEM device include the formation of polysilicon members that are substantially free from residual stress, thereby improving the reliability of the MEM device; an ability to form the MEM device with a higher degree of complexity and more layers of structural polysilicon than would be possible using conventional compressively-strained sacrificial materials; and improved manufacturability resulting from the elimination of wafer distortion that can arise from an excess of accumulated stress in conventional sacrificial materials. The present invention is useful for forming many different types of MEM devices including accelerometers, sensors, motors, switches, coded locks, and flow-control devices, with or without integrated electronic circuitry.

Silicon Carbide High-Temperature Power Rectifiers Fabricated and Characterized

NASA Technical Reports Server (NTRS)

1996-01-01

The High Temperature Integrated Electronics and Sensors (HTIES) team at the NASA Lewis Research Center is developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. Silicon carbide's demonstrated ability to function under extreme high-temperature, high power, and/or high-radiation conditions will enable significant improvements to a far ranging variety of applications and systems. These improvements range from improved high-voltage switching for energy savings in public electric power distribution and electric vehicles, to more powerful microwave electronics for radar and cellular communications, to sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. In the case of jet engines, uncooled operation of 300 to 600 C SiC power actuator electronics mounted in key high-temperature areas would greatly enhance system performance and reliability. Because silicon cannot function at these elevated temperatures, the semiconductor device circuit components must be made of SiC. Lewis' HTIES group recently fabricated and characterized high-temperature SiC rectifier diodes whose record-breaking characteristics represent significant progress toward the realization of advanced high-temperature actuator control circuits. The first figure illustrates the 600 C probe-testing of a Lewis SiC pn-junction rectifier diode sitting on top of a glowing red-hot heating element. The second figure shows the current-versus voltage rectifying characteristics recorded at 600 C. At this high temperature, the diodes were able to "turn-on" to conduct 4 A of current when forward biased, and yet block the flow of current ($quot;turn-off") when reverse biases as high as 150 V were applied. This device represents a new record for semiconductor device operation, in that no previous semiconductor electronic device has ever simultaneously demonstrated 600 C functionality, and 4-A turn-on and 150-V rectification. The high operating current was achieved despite severe device size limitations imposed by present-day SiC wafer defect densities. Further substantial increases in device performance can be expected when SiC wafer defect densities decrease as SiC wafer production technology matures.

Ultrafast and sensitive photodetector based on a PtSe2/silicon nanowire array heterojunction with a multiband spectral response from 200 to 1550 nm

NASA Astrophysics Data System (ADS)

Zeng, Longhui; Lin, Shenghuang; Lou, Zhenhua; Yuan, Huiyu; Long, Hui; Li, Yanyong; Lu, Wei; Lau, Shu Ping; Wu, Di; Tsang, Yuen Hong

2018-04-01

The newly discovered Group-10 transition metal dichalcogenides (TMDs) like PtSe2 have promising applications in high-performance microelectronic and optoelectronic devices due to their high carrier mobilities, widely tunable bandages and ultrastabilities. However, the optoelectronic performance of broadband PtSe2 photodetectors integrated with silicon remains undiscovered. Here, we report the successful preparation of large-scale, uniform and vertically grown PtSe2 films by simple selenization method for the design of a PtSe2/Si nanowire array heterostructure, which exhibited a very good photoresponsivity of 12.65 A/W, a high specific detectivity of 2.5 × 1013 Jones at -5 V and fast rise/fall times of 10.1/19.5 μs at 10 kHz without degradation while being capable of responding to high frequencies of up to 120 kHz. Our work has demonstrated the compatibility of PtSe2 with the existing silicon technology and ultrabroad band detection ranging from deep ultraviolet to optical telecommunication wavelengths, which can largely cover the limitations of silicon detectors. Further investigation of the device revealed pronounced photovoltaic behavior at 0 V, making it capable of operating as a self-powered photodetector. Overall, this representative PtSe2/Si nanowire array-based photodetector offers great potential for applications in next-generation optoelectronic and electronic devices.

Hybrid quantum and molecular mechanics embedded cluster models for chemistry on silicon and silicon carbide surfaces

NASA Astrophysics Data System (ADS)

Shoemaker, James Richard

Fabrication of silicon carbide (SiC) semiconductor devices are of interest for aerospace applications because of their high-temperature tolerance. Growth of an insulating SiO2 layer on SiC by oxidation is a poorly understood process, and sometimes produces interface defects that degrade device performance. Accurate theoretical models of surface chemistry, using quantum mechanics (QM), do not exist because of the huge computational cost of solving Schrodinger's equation for a molecular cluster large enough to represent a surface. Molecular mechanics (MM), which describes a molecule as a collection of atoms interacting through classical potentials, is a fast computational method, good at predicting molecular structure, but cannot accurately model chemical reactions. A new hybrid QM/MM computational method for surface chemistry was developed and applied to silicon and SiC surfaces. The addition of MM steric constraints was shown to have a large effect on the energetics of O atom adsorption on SiC. Adsorption of O atoms on Si-terminated SiC(111) favors above surface sites, in contrast to Si(111), but favors subsurface adsorption sites on C- terminated SiC(111). This difference, and the energetics of C atom etching via CO2 desorption, can explain the observed poor performance of SiC devices in which insulating layers were grown on C-terminated surfaces.

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

Review: Semiconductor Piezoresistance for Microsystems.

PubMed

Barlian, A Alvin; Park, Woo-Tae; Mallon, Joseph R; Rastegar, Ali J; Pruitt, Beth L

2009-01-01

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

Evaluation of transition metal oxide as carrier-selective contacts for silicon heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ding, L.; Boccard, Matthieu; Holman, Zachary

2015-04-06

"Reducing light absorption in the non-active solar cell layers, while enabling the extraction of the photogenerated minority carriers at quasi-Fermi levels are two key factors to improve current generation and voltage, and therefore efficiency of silicon heterojunction solar devices. To address these two critical aspects, transition metal oxide materials have been proposed as alternative to the n- and p-type amorphous silicon used as electron and hole selective contacts, respectively. Indeed, transition metal oxides such as molybdenum oxide, titanium oxide, nickel oxide or tungsten oxide combine a wide band gap typically over 3 eV with a band structure and theoretical bandmore » alignment with silicon that results in high transparency to the solar spectrum and in selectivity for the transport of only one carrier type. Improving carrier extraction or injection using transition metal oxide has been a topic of investigation in the field of organic solar cells and organic LEDs; from these pioneering works a lot of knowledge has been gained on materials properties, ways to control these during synthesis and deposition, and their impact on device performance. Recently, the transfer of some of this knowledge to silicon solar cells and the successful application of some metal oxide to contact heterojunction devices have gained much attention. In this contribution, we investigate the suitability of various transition metal oxide films (molybdenum oxide, titanium oxide, and tungsten oxide) deposited either by thermal evaporation or sputtering as transparent hole or electron selective transport layer for silicon solar cells. In addition to systematically characterize their optical and structural properties, we use photoemission spectroscopy to relate compound stoichiometry to band structure and characterize band alignment to silicon. The direct silicon/metal oxide interface is further analyzed by quasi-steady state photoconductance decay method to assess the quality of surface passivation. In complement, we construct full device structures incorporating in some cases surface passivation schemes, with measured initial conversion efficiency over 15% and evaluate the carrier transport properties using temperature-dependent current-voltage and capacitance-voltage measurements. With this detailed characterization study, we aim at providing the framework to assess the potential of a material as a carrier selective contact and the understanding of how each of the aforementioned parameters on the metal oxide films influence the full solar cell operating performances.« less

Germanium: From Its Discovery to SiGe Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haller, E.E.

2006-06-14

Germanium, element No.32, was discovered in 1886 by Clemens Winkler. Its first broad application was in the form of point contact Schottky diodes for radar reception during WWII. The addition of a closely spaced second contact led to the first all-solid-state electronic amplifier device, the transistor. The relatively low bandgap, the lack of a stable oxide and large surface state densities relegated germanium to the number 2 position behind silicon. The discovery of the lithium drift process, which made possible the formation of p-i-n diodes with fully depletable i-regions several centimeters thick, led germanium to new prominence as the premiermore » gamma-ray detector. The development of ultra-pure germanium yielded highly stable detectors which have remained unsurpassed in their performance. New acceptors and donors were discovered and the electrically active role of hydrogen was clearly established several years before similar findings in silicon. Lightly doped germanium has found applications as far infrared detectors and heavily Neutron Transmutation Doped (NTD) germanium is used in thermistor devices operating at a few milliKelvin. Recently germanium has been rediscovered by the silicon device community because of its superior electron and hole mobility and its ability to induce strains when alloyed with silicon. Germanium is again a mainstream electronic material.« less

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

Towards substrate engineering of graphene-silicon Schottky diode photodetectors.

PubMed

Selvi, Hakan; Unsuree, Nawapong; Whittaker, Eric; Halsall, Matthew P; Hill, Ernie W; Thomas, Andrew; Parkinson, Patrick; Echtermeyer, Tim J

2018-02-15

Graphene-silicon Schottky diode photodetectors possess beneficial properties such as high responsivities and detectivities, broad spectral wavelength operation and high operating speeds. Various routes and architectures have been employed in the past to fabricate devices. Devices are commonly based on the removal of the silicon-oxide layer on the surface of silicon by wet-etching before deposition of graphene on top of silicon to form the graphene-silicon Schottky junction. In this work, we systematically investigate the influence of the interfacial oxide layer, the fabrication technique employed and the silicon substrate on the light detection capabilities of graphene-silicon Schottky diode photodetectors. The properties of devices are investigated over a broad wavelength range from near-UV to short-/mid-infrared radiation, radiation intensities covering over five orders of magnitude as well as the suitability of devices for high speed operation. Results show that the interfacial layer, depending on the required application, is in fact beneficial to enhance the photodetection properties of such devices. Further, we demonstrate the influence of the silicon substrate on the spectral response and operating speed. Fabricated devices operate over a broad spectral wavelength range from the near-UV to the short-/mid-infrared (thermal) wavelength regime, exhibit high photovoltage responses approaching 10 6 V W -1 and short rise- and fall-times of tens of nanoseconds.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics.

Aerospace Sensor Component and Subsystem Investigation and Innovation-2 Component Exploration and Development (ASCSII-2 CED) Delivery Order 0003: Hermetically Sealed Cavities in 3-D GaAs-Silicon and Silicon-Silicon Packages for Microelectromechanical System (MEMS) Devices Using Selective and Large-Scale Bonding

DTIC Science & Technology

2003-03-01

and silicon-to-silicon to produce cavities for 3-D assembly of MEMS devices has been demonstrated using SnAgCu and eutectic SnPb solders. Laser and...of GaAs-to-silicon and silicon-to-silicon to produce cavities for 3-D assembly of MEMS devices has been demonstrated using SnAgCu and euctectic...research_images/ 3.2 Solder Reflow The reflow profile for SnAgCu solder was developed on the Sikama convection/ conduction reflow oven using a continuous

Low-stress photosensitive polyimide suspended membrane for improved thermal isolation performance

NASA Astrophysics Data System (ADS)

Fan, J.; Xing, R. Y.; Wu, W. J.; Liu, H. F.; Liu, J. Q.; Tu, L. C.

2017-11-01

In this paper, we introduce a method of isolating thermal conduction from silicon substrate for accommodating thermal-sensitive micro-devices. This method lies in fabrication of a low-stress photosensitive polyimide (PSPI) suspension structure which has lower thermal conductivity than silicon. First, a PSPI layer was patterned on a silicon wafer and hard baked. Then, a cavity was etched from the backside of the silicon substrate to form a membrane or a bridge-shape PSPI structure. After releasing, a slight deformation of about 20 nm was observed in the suspended structures, suggesting ultralow residual stress which is essential for accommodating micro-devices. In order to investigate the thermal isolation performance of the suspended PSPI structures, micro Pirani vacuum gauges, which are thermal-sensitive, had been fabricated on the PSPI structures. The measurement results illustrated that the Pirani gauges worked as expected in the range from 1- 470 Pa. Moreover, the results of the Pirani gauges based on the membrane and bridge structures were comparable, indicating that the commonly used bridge-shape structure for further reducing thermal conduction was unnecessary. Due to the excellent thermal isolation performance of PSPI, the suspended PSPI membrane is promising to be an outstanding candidate for thermal isolation applications.

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

NASA Astrophysics Data System (ADS)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Measurements of Raman crystallinity profiles in thin-film microcrystalline silicon solar cells

NASA Astrophysics Data System (ADS)

Choong, G.; Vallat-Sauvain, E.; Multone, X.; Fesquet, L.; Kroll, U.; Meier, J.

2013-06-01

Wedge-polished thin film microcrystalline silicon solar cells are prepared and used for micro-Raman measurements. Thereby, the variations of the Raman crystallinity with depth are accessed easily. Depth resolution limits of the measurement set-up are established and calculations evidencing the role of optical limits are presented. Due to this new technique, Raman crystallinity profiles of two microcrystalline silicon cells give first hints for the optimization of the profile leading to improved electrical performance of such devices.

Towards nanometer-spaced silicon contacts to proteins

NASA Astrophysics Data System (ADS)

Schukfeh, Muhammed I.; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

A hybrid ferroelectric-flash memory cells

NASA Astrophysics Data System (ADS)

Park, Jae Hyo; Byun, Chang Woo; Seok, Ki Hwan; Kim, Hyung Yoon; Chae, Hee Jae; Lee, Sol Kyu; Son, Se Wan; Ahn, Donghwan; Joo, Seung Ki

2014-09-01

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V-1 s-1 of field-effect mobility, 190 mV dec-1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to -5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

High-Temperature Performance of Stacked Silicon Nanowires for Thermoelectric Power Generation

NASA Astrophysics Data System (ADS)

Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2013-07-01

Deep reactive-ion etching at cryogenic temperatures (cryo-DRIE) has been used to produce arrays of silicon nanowires (NWs) for thermoelectric (TE) power generation devices. Using cryo-DRIE, we were able to fabricate NWs of large aspect ratios (up to 32) using a photoresist mask. Roughening of the NW sidewalls occurred, which has been recognized as beneficial for low thermal conductivity. Generated NWs, which were 7 μm in length and 220 nm to 270 nm in diameter, were robust enough to be stacked with a bulk silicon chip as a common top contact to the NWs. Mechanical support of the NW array, which can be created by filling the free space between the NWs using silicon oxide or polyimide, was not required. The Seebeck voltage, measured across multiple stacks of up to 16 bulk silicon dies, revealed negligible thermal interface resistance. With stacked silicon NWs, we observed Seebeck voltages that were an order of magnitude higher than those observed for bulk silicon. Degradation of the TE performance of silicon NWs was not observed for temperatures up to 470°C and temperature gradients up to 170 K.

A practical guide for the fabrication of microfluidic devices using glass and silicon

PubMed Central

Iliescu, Ciprian; Taylor, Hayden; Avram, Marioara; Miao, Jianmin; Franssila, Sami

2012-01-01

This paper describes the main protocols that are used for fabricating microfluidic devices from glass and silicon. Methods for micropatterning glass and silicon are surveyed, and their limitations are discussed. Bonding methods that can be used for joining these materials are summarized and key process parameters are indicated. The paper also outlines techniques for forming electrical connections between microfluidic devices and external circuits. A framework is proposed for the synthesis of a complete glass/silicon device fabrication flow. PMID:22662101

Long-Term Stability of Mold Compounds and the Influence on Semiconductor Device Reliability

NASA Astrophysics Data System (ADS)

Mahler, Joachim; Mengel, Manfred

2012-07-01

Lifetimes of semiconductor devices are specified according to the products and their applications to ensure safe operation, for instance as part of an automobile product. The long-term stability of the device is strongly dependent on the chip encapsulation and its adhesion to the chip and substrate. Molded silicon strips that act as a model system for molded chips inside semiconductor devices were investigated. Four commercially available mold compounds were applied on silicon strips and stored over 5 years at room temperature (RT), and changes in the thermomechanical behavior were analyzed. After storage, all molded strips exhibited warpage reduction in the range of 11% to 14% at RT with respect to the initial warpage. The temperatures for the stress-free state also changed during storage and were located between 228°C and 235°C for each mold. Additional stress applied to the stored modules, by temperature cycling as well as high-temperature storage, increased the warpage of the molded silicon samples. For further interpretation of measured results, finite-element method calculations were performed.

Energy-Conversion Properties of Vapor-Liquid-Solid-Grown Silicon Wire-Array Photocathodes

NASA Astrophysics Data System (ADS)

Boettcher, Shannon W.; Spurgeon, Joshua M.; Putnam, Morgan C.; Warren, Emily L.; Turner-Evans, Daniel B.; Kelzenberg, Michael D.; Maiolo, James R.; Atwater, Harry A.; Lewis, Nathan S.

2010-01-01

Silicon wire arrays, though attractive materials for use in photovoltaics and as photocathodes for hydrogen generation, have to date exhibited poor performance. Using a copper-catalyzed, vapor-liquid-solid-growth process, SiCl4 and BCl3 were used to grow ordered arrays of crystalline p-type silicon (p-Si) microwires on p+-Si(111) substrates. When these wire arrays were used as photocathodes in contact with an aqueous methyl viologen2+/+ electrolyte, energy-conversion efficiencies of up to 3% were observed for monochromatic 808-nanometer light at fluxes comparable to solar illumination, despite an external quantum yield at short circuit of only 0.2. Internal quantum yields were at least 0.7, demonstrating that the measured photocurrents were limited by light absorption in the wire arrays, which filled only 4% of the incident optical plane in our test devices. The inherent performance of these wires thus conceptually allows the development of efficient photovoltaic and photoelectrochemical energy-conversion devices based on a radial junction platform.

Energy-conversion properties of vapor-liquid-solid-grown silicon wire-array photocathodes.

PubMed

Boettcher, Shannon W; Spurgeon, Joshua M; Putnam, Morgan C; Warren, Emily L; Turner-Evans, Daniel B; Kelzenberg, Michael D; Maiolo, James R; Atwater, Harry A; Lewis, Nathan S

2010-01-08

Silicon wire arrays, though attractive materials for use in photovoltaics and as photocathodes for hydrogen generation, have to date exhibited poor performance. Using a copper-catalyzed, vapor-liquid-solid-growth process, SiCl4 and BCl3 were used to grow ordered arrays of crystalline p-type silicon (p-Si) microwires on p+-Si(111) substrates. When these wire arrays were used as photocathodes in contact with an aqueous methyl viologen(2+/+) electrolyte, energy-conversion efficiencies of up to 3% were observed for monochromatic 808-nanometer light at fluxes comparable to solar illumination, despite an external quantum yield at short circuit of only 0.2. Internal quantum yields were at least 0.7, demonstrating that the measured photocurrents were limited by light absorption in the wire arrays, which filled only 4% of the incident optical plane in our test devices. The inherent performance of these wires thus conceptually allows the development of efficient photovoltaic and photoelectrochemical energy-conversion devices based on a radial junction platform.

Dopant atoms as quantum components in silicon nanoscale devices

NASA Astrophysics Data System (ADS)

Zhao, Xiaosong; Han, Weihua; Wang, Hao; Ma, Liuhong; Li, Xiaoming; Zhang, Wang; Yan, Wei; Yang, Fuhua

2018-06-01

Recent progress in nanoscale fabrication allows many fundamental studies of the few dopant atoms in various semiconductor nanostructures. Since the size of nanoscale devices has touched the limit of the nature, a single dopant atom may dominate the performance of the device. Besides, the quantum computing considered as a future choice beyond Moore's law also utilizes dopant atoms as functional units. Therefore, the dopant atoms will play a significant role in the future novel nanoscale devices. This review focuses on the study of few dopant atoms as quantum components in silicon nanoscale device. The control of the number of dopant atoms and unique quantum transport characteristics induced by dopant atoms are presented. It can be predicted that the development of nanoelectronics based on dopant atoms will pave the way for new possibilities in quantum electronics. Project supported by National Key R&D Program of China (No. 2016YFA0200503).

Advances in Single and Multijunction III-V Photovoltaics on Silicon for Space Power

NASA Technical Reports Server (NTRS)

Wilt, David M.; Fitzgerald, Eugene A.; Ringel, Steven A.

2005-01-01

A collaborative research effort at MIT, Ohio State University and NASA has resulted in the demonstration of record quality gallium arsenide (GaAs) based single junction photovoltaic devices on silicon (Si) substrates. The ability to integrate highly efficient, radiation hard III-V based devices on silicon offers the potential for dramatic reductions in cell mass (approx.2x) and increases in cell area. Both of these improvements offer the potential for dramatic reductions in the cost of on-orbit electrical power. Recently, lattice matched InGaP/GaAs and metamorphic InGaP/InGaAs dual junction solar cells were demonstrated by MBE and OMVPE, respectively. Single junction GaAs on Si devices have been integrated into a space flight experiment (MISSES), scheduled to be launched to the International Space Station in March of 2005. I-V performance data from the GaAs/Si will be collected on-orbit and telemetered to ground stations daily. Microcracks in the GaAs epitaxial material, generated because of differences in the thermal expansion coefficient between GaAs and Si, are of concern in the widely varying thermal environment encountered in low Earth orbit. Ground based thermal life cycling (-80 C to + 80 C) equivalent to 1 year in LEO has been conducted on GaAs/Si devices with no discernable degradation in device performance, suggesting that microcracks may not limit the ability to field GaAs/Si in harsh thermal environments. Recent advances in the development and testing of III-V photovoltaic devices on Si will be presented.

Custom 3D Printable Silicones with Tunable Stiffness.

PubMed

Durban, Matthew M; Lenhardt, Jeremy M; Wu, Amanda S; Small, Ward; Bryson, Taylor M; Perez-Perez, Lemuel; Nguyen, Du T; Gammon, Stuart; Smay, James E; Duoss, Eric B; Lewicki, James P; Wilson, Thomas S

2018-02-01

Silicone elastomers have broad versatility within a variety of potential advanced materials applications, such as soft robotics, biomedical devices, and metamaterials. A series of custom 3D printable silicone inks with tunable stiffness is developed, formulated, and characterized. The silicone inks exhibit excellent rheological behavior for 3D printing, as observed from the printing of porous structures with controlled architectures. Herein, the capability to tune the stiffness of printable silicone materials via careful control over the chemistry, network formation, and crosslink density of the ink formulations in order to overcome the challenging interplay between ink development, post-processing, material properties, and performance is demonstrated. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-03-21

A method is disclosed for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics. 7 figures.

Efficient Monolithic Perovskite/Silicon Tandem Solar Cell with Cell Area >1 cm(2).

PubMed

Werner, Jérémie; Weng, Ching-Hsun; Walter, Arnaud; Fesquet, Luc; Seif, Johannes Peter; De Wolf, Stefaan; Niesen, Bjoern; Ballif, Christophe

2016-01-07

Monolithic perovskite/crystalline silicon tandem solar cells hold great promise for further performance improvement of well-established silicon photovoltaics; however, monolithic tandem integration is challenging, evidenced by the modest performances and small-area devices reported so far. Here we present first a low-temperature process for semitransparent perovskite solar cells, yielding efficiencies of up to 14.5%. Then, we implement this process to fabricate monolithic perovskite/silicon heterojunction tandem solar cells yielding efficiencies of up to 21.2 and 19.2% for cell areas of 0.17 and 1.22 cm(2), respectively. Both efficiencies are well above those of the involved subcells. These single-junction perovskite and tandem solar cells are hysteresis-free and demonstrate steady performance under maximum power point tracking for several minutes. Finally, we present the effects of varying the intermediate recombination layer and hole transport layer thicknesses on tandem cell photocurrent generation, experimentally and by transfer matrix simulations.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crowder, M.A.; Sposili, R.S.; Cho, H.S.

Nonhydrogenated, n-channel, low-temperature-processed, single-crystal Si thin-film transistors (TFT`s) have been fabricated on Si thin films prepared via sequential lateral solidification (SLS). The device characteristics of the resulting SLS TFT`s exhibit properties and a level of performance that are superior to polycrystalline Si-based TFT`s and are comparable to similar devices fabricated on silicon-on-insulator (SOI) substrates or bulk-Si wafers. The authors attribute these high-performance device characteristics to the absence of high-angle grain-boundaries within the active channel portion of the TFT`s.

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

A wearable strain sensor based on a carbonized nano-sponge/silicone composite for human motion detection.

PubMed

Yu, Xiao-Guang; Li, Yuan-Qing; Zhu, Wei-Bin; Huang, Pei; Wang, Tong-Tong; Hu, Ning; Fu, Shao-Yun

2017-05-25

Melamine sponge, also known as nano-sponge, is widely used as an abrasive cleaner in our daily life. In this work, the fabrication of a wearable strain sensor for human motion detection is first demonstrated with a commercially available nano-sponge as a starting material. The key resistance sensitive material in the wearable strain sensor is obtained by the encapsulation of a carbonized nano-sponge (CNS) with silicone resin. The as-fabricated CNS/silicone sensor is highly sensitive to strain with a maximum gauge factor of 18.42. In addition, the CNS/silicone sensor exhibits a fast and reliable response to various cyclic loading within a strain range of 0-15% and a loading frequency range of 0.01-1 Hz. Finally, the CNS/silicone sensor as a wearable device for human motion detection including joint motion, eye blinking, blood pulse and breathing is demonstrated by attaching the sensor to the corresponding parts of the human body. In consideration of the simple fabrication technique, low material cost and excellent strain sensing performance, the CNS/silicone sensor is believed to have great potential in the next-generation of wearable devices for human motion detection.

Amorphous silicon Schottky barrier solar cells incorporating a thin insulating layer and a thin doped layer

DOEpatents

Carlson, David E.

1980-01-01

Amorphous silicon Schottky barrier solar cells which incorporate a thin insulating layer and a thin doped layer adjacent to the junction forming metal layer exhibit increased open circuit voltages compared to standard rectifying junction metal devices, i.e., Schottky barrier devices, and rectifying junction metal insulating silicon devices, i.e., MIS devices.

Carrier transport and sensitivity issues in heterojunction with intrinsic thin layer solar cells on N-type crystalline silicon: A computer simulation study

NASA Astrophysics Data System (ADS)

Rahmouni, M.; Datta, A.; Chatterjee, P.; Damon-Lacoste, J.; Ballif, C.; Roca i Cabarrocas, P.

2010-03-01

Heterojunction with intrinsic thin layer or "HIT" solar cells are considered favorable for large-scale manufacturing of solar modules, as they combine the high efficiency of crystalline silicon (c-Si) solar cells, with the low cost of amorphous silicon technology. In this article, based on experimental data published by Sanyo, we simulate the performance of a series of HIT cells on N-type crystalline silicon substrates with hydrogenated amorphous silicon (a-Si:H) emitter layers, to gain insight into carrier transport and the general functioning of these devices. Both single and double HIT structures are modeled, beginning with the initial Sanyo cells having low open circuit voltages but high fill factors, right up to double HIT cells exhibiting record values for both parameters. The one-dimensional numerical modeling program "Amorphous Semiconductor Device Modeling Program" has been used for this purpose. We show that the simulations can correctly reproduce the electrical characteristics and temperature dependence for a set of devices with varying I-layer thickness. Under standard AM1.5 illumination, we show that the transport is dominated by the diffusion mechanism, similar to conventional P/N homojunction solar cells, and tunneling is not required to describe the performance of state-of-the art devices. Also modeling has been used to study the sensitivity of N-c-Si HIT solar cell performance to various parameters. We find that the solar cell output is particularly sensitive to the defect states on the surface of the c-Si wafer facing the emitter, to the indium tin oxide/P-a-Si:H front contact barrier height and to the band gap and activation energy of the P-a-Si:H emitter, while the I-a-Si:H layer is necessary to achieve both high Voc and fill factor, as it passivates the defects on the surface of the c-Si wafer. Finally, we describe in detail for most parameters how they affect current transport and cell properties.

High-performance axicon lenses based on high-contrast, multilayer gratings

NASA Astrophysics Data System (ADS)

Doshay, Sage; Sell, David; Yang, Jianji; Yang, Rui; Fan, Jonathan A.

2018-01-01

Axicon lenses are versatile optical elements that can convert Gaussian beams to Bessel-like beams. In this letter, we demonstrate that axicons operating with high efficiencies and at large angles can be produced using high-contrast, multilayer gratings made from silicon. Efficient beam deflection of incident monochromatic light is enabled by higher-order optical modes in the silicon structure. Compared to diffractive devices made from low-contrast materials such as silicon dioxide, our multilayer devices have a relatively low spatial profile, reducing shadowing effects and enabling high efficiencies at large deflection angles. In addition, the feature sizes of these structures are relatively large, making the fabrication of near-infrared devices accessible with conventional optical lithography. Experimental lenses with deflection angles as large as 40° display field profiles that agree well with theory. Our concept can be used to design optical elements that produce higher-order Bessel-like beams, and the combination of high-contrast materials with multilayer architectures will more generally enable new classes of diffractive photonic structures.

FDTD modeling of anisotropic nonlinear optical phenomena in silicon waveguides.

PubMed

Dissanayake, Chethiya M; Premaratne, Malin; Rukhlenko, Ivan D; Agrawal, Govind P

2010-09-27

A deep insight into the inherent anisotropic optical properties of silicon is required to improve the performance of silicon-waveguide-based photonic devices. It may also lead to novel device concepts and substantially extend the capabilities of silicon photonics in the future. In this paper, for the first time to the best of our knowledge, we present a three-dimensional finite-difference time-domain (FDTD) method for modeling optical phenomena in silicon waveguides, which takes into account fully the anisotropy of the third-order electronic and Raman susceptibilities. We show that, under certain realistic conditions that prevent generation of the longitudinal optical field inside the waveguide, this model is considerably simplified and can be represented by a computationally efficient algorithm, suitable for numerical analysis of complex polarization effects. To demonstrate the versatility of our model, we study polarization dependence for several nonlinear effects, including self-phase modulation, cross-phase modulation, and stimulated Raman scattering. Our FDTD model provides a basis for a full-blown numerical simulator that is restricted neither by the single-mode assumption nor by the slowly varying envelope approximation.

Intimate effects of surface functionalization of porous silicon microcavities on biosensing performance

NASA Astrophysics Data System (ADS)

Martin, M.; Massif, L.; Estephan, E.; Saab, M.-b.; Cloitre, T.; Larroque, C.; Agarwal, V.; Cuisinier, F. J. G.; Le Lay, G.; Gergely, C.

2011-10-01

We study the effect of different surface functionalization methods on the sensing performances of porous silicon (PSi) microcavities when used for detection of biomolecules. Previous research on porous silicon demonstrated versatility of these devices for sensor applications based on their photonic responses. The interface between biological molecules and the Si semiconductor surface is a key issue for improving biomolecular recognition in these devices. PSi microcavities were fabricated to reveal reflectivity pass-band spectra in the visible and near-infrared domain. To assure uniform infiltration of proteins the number of layers of Bragg mirrors was limited to five, the first layer being of high porosity. In one approach the devices were thermally oxidized and functionalized to assure covalent binding of molecules. Secondly, the as etched PSi surface was modified with adhesion peptides isolated via phage display technology and presenting high binding capacity for Si. Functionalization and molecular binding events were monitored via reflectometric interference spectra as shifts in the resonance peaks of the cavity structure due to changes in the refractive index when a biomolecule is attached to the large internal surface of PSi. Improved sensitivity is obtained due to the peptide interface linkers between the PSi and biological molecules compared to the silanized devices. We investigate the formation of peptide-Si interface layer via X-ray photoelectron spectroscopy, scanning tunneling microscopy and scanning electron microscopy.

Virtual design and optimization studies for industrial silicon microphones applying tailored system-level modeling

NASA Astrophysics Data System (ADS)

Kuenzig, Thomas; Dehé, Alfons; Krumbein, Ulrich; Schrag, Gabriele

2018-05-01

Maxing out the technological limits in order to satisfy the customers’ demands and obtain the best performance of micro-devices and-systems is a challenge of today’s manufacturers. Dedicated system simulation is key to investigate the potential of device and system concepts in order to identify the best design w.r.t. the given requirements. We present a tailored, physics-based system-level modeling approach combining lumped with distributed models that provides detailed insight into the device and system operation at low computational expense. The resulting transparent, scalable (i.e. reusable) and modularly composed models explicitly contain the physical dependency on all relevant parameters, thus being well suited for dedicated investigation and optimization of MEMS devices and systems. This is demonstrated for an industrial capacitive silicon microphone. The performance of such microphones is determined by distributed effects like viscous damping and inhomogeneous capacitance variation across the membrane as well as by system-level phenomena like package-induced acoustic effects and the impact of the electronic circuitry for biasing and read-out. The here presented model covers all relevant figures of merit and, thus, enables to evaluate the optimization potential of silicon microphones towards high fidelity applications. This work was carried out at the Technical University of Munich, Chair for Physics of Electrotechnology. Thomas Kuenzig is now with Infineon Technologies AG, Neubiberg.

Silicon-graphene photonic devices

NASA Astrophysics Data System (ADS)

Yin, Yanlong; Li, Jiang; Xu, Yang; Tsang, Hon Ki; Dai, Daoxin

2018-06-01

Silicon photonics has attracted much attention because of the advantages of CMOS (complementary-metal-oxide-semiconductor) compatibility, ultra-high integrated density, etc. Great progress has been achieved in the past decades. However, it is still not easy to realize active silicon photonic devices and circuits by utilizing the material system of pure silicon due to the limitation of the intrinsic properties of silicon. Graphene has been regarded as a promising material for optoelectronics due to its unique properties and thus provides a potential option for realizing active photonic integrated devices on silicon. In this paper, we present a review on recent progress of some silicon-graphene photonic devices for photodetection, all-optical modulation, as well as thermal-tuning. Project supported by the National Major Research and Development Program (No. 2016YFB0402502), the National Natural Science Foundation of China (Nos. 11374263, 61422510, 61431166001, 61474099, 61674127), and the National Key Research and Development Program (No. 2016YFA0200200).

Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsam (Inventor); Manohara, Harish (Inventor); Mobasser, Sohrab (Inventor); Lee, Choonsup (Inventor)

2011-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Anti- reflective device having an anti-reflection surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsman (Inventor); Mooasser, Sohrab (Inventor); Manohara, Harish (Inventor); Lee, Choonsup (Inventor); Bae, Kungsam (Inventor)

2009-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Review: Semiconductor Piezoresistance for Microsystems

PubMed Central

Barlian, A. Alvin; Park, Woo-Tae; Mallon, Joseph R.; Rastegar, Ali J.; Pruitt, Beth L.

2010-01-01

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers. PMID:20198118

Optimized optical devices for edge-coupling-enabled silicon photonics platform

NASA Astrophysics Data System (ADS)

Png, Ching Eng; Ang, Thomas Y. L.; Ong, Jun Rong; Lim, Soon Thor; Sahin, Ezgi; Chen, G. F. R.; Tan, D. T. H.; Guo, Tina X.; Wang, Hong

2018-02-01

We present a library of high-performance passive and active silicon photonic devices at the C-band that is specifically designed and optimized for edge-coupling-enabled silicon photonics platform. These devices meet the broadband (100 nm), low-loss (< 2dB per device), high speed (>= 25 Gb/s), and polarization diversity requirements (TE and TM polarization extinction ratio <= 25 dB) for optical communication applications. Ultra-low loss edge couplers, broadband directional couplers, high-extinction ratio polarization beam splitters (PBSs), and high-speed modulators are some of the devices within our library. In particular, we have designed and fabricated inverse taper fiber-to-waveguide edge couplers of tip widths ranging from 120 nm to 200 nm, and we obtained a low coupling loss of 1.80+/-0.28 dB for 160 nm tip width. To achieve polarization diversity operation for inverse tapers, we have experimentally realized different designs of polarization beam splitters (PBS). Our optimized PBS has a measured extinction ratio of <= 25 dB for both the quasiTE modes, and quasi-TM modes. Additionally, a broadband (100 nm) directional coupler with a 50/50 power splitting ratio was experimentally realized on a small footprint of 20×3 μm2 . Last but not least, high-speed silicon modulators with a range of carrier doping concentrations and offset of the PN junction can be used to optimise the modulation efficiency, and insertion losses for operation at 25 GHz.

Assessment of a new silicone tri-leaflet valve seamlessly assembled with blood chamber for a low-cost ventricular assist device.

PubMed

Hirai, S; Fukunaga, S; Sueshiro, M; Watari, M; Sueda, T; Matsuura, Y

1998-06-01

We have developed a practical, low-cost ventricular assist device (VAD) comprising a newly designed blood chamber with a silicone lenticular sac and two silicone tri-leaflet valves (STV), made en bloc. This new VAD is seamless, can be made cost-effectively and assembled with the blood chamber and valve as one body. This novel design should reduce the incident of thrombus formation because of the absence of a junction at the connecting ring and because of the use of flexible silicone materials which have both antithrombogenecity and biocompatibility. In in vitro hemodynamics testing, a batch of 3 consecutively manufactured VADs with STVs underwent hydrodynamic functional testing. These showed less regurgitation, a lower value of water hammer phenomenon, and a slightly greater pressure gradient across the valves than a mechanical valve (MV) [Björk-Shiley monostrut valve]. The flow and pulsatile efficiency were adequate and similar to that of a VAD with MVs. In in vitro durability and hemolysis tests, a VAD with STV functioned well for 54 days and showed similar hemolytic profiles to a VAD with MVs. In an in vivo acute experiment using an adult sheep, our device was problem-free providing sufficient output as a left ventricular assist device (LVAD). Although it will be necessary to decrease the pressure gradient across this STV in the future, our device showed efficient performance as a practical land cost-effective VAD for short term use.

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

Method for sputtering a PIN microcrystalline/amorphous silicon semiconductor device with the P and N-layers sputtered from boron and phosphorous heavily doped targets

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-04-02

A silicon PIN microcrystalline/amorphous silicon semiconductor device is constructed by the sputtering of N, and P layers of silicon from silicon doped targets and the I layer from an undoped target, and at least one semi-transparent ohmic electrode.

Deposition of hydrogenated silicon clusters for efficient epitaxial growth.

PubMed

Le, Ha-Linh Thi; Jardali, Fatme; Vach, Holger

2018-06-13

Epitaxial silicon thin films grown from the deposition of plasma-born hydrogenated silicon nanoparticles using plasma-enhanced chemical vapor deposition have widely been investigated due to their potential applications in photovoltaic and nanoelectronic device technologies. However, the optimal experimental conditions and the underlying growth mechanisms leading to the high-speed epitaxial growth of thin silicon films from hydrogenated silicon nanoparticles remain far from being understood. In the present work, extensive molecular dynamics simulations were performed to study the epitaxial growth of silicon thin films resulting from the deposition of plasma-born hydrogenated silicon clusters at low substrate temperatures under realistic reactor conditions. There is strong evidence that a temporary phase transition of the substrate area around the cluster impact site to the liquid state is necessary for the epitaxial growth to take place. We predict further that a non-normal incidence angle for the cluster impact significantly facilitates the epitaxial growth of thin crystalline silicon films.

Single-Event Effects in Silicon Carbide Power Devices

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2015-01-01

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

Applications of Photonic Crystals to Photovoltaic Devices

NASA Astrophysics Data System (ADS)

Foster, Stephen

Photonic crystals are structures that exhibit wavelength-scale spatial periodicity in their dielectric function. They are best known for their ability to exhibit complete photonic band gaps (PBGs) - spectral regions over which no light can propagate within the crystal. PBGs are specific instances of a more general phenomenon, in which the local photonic density of states can be enhanced or suppressed over different frequency ranges by tuning the properties of the crystal. This can be used to redirect, concentrate, or even trap light incident on the crystal. In this thesis, we investigate how photonic crystals can be used to enhance the efficiency of photovoltaic devices by trapping light. Due to the many different types of photovoltaic devices in existence (varying widely in materials used, modes of operation, and internal structure), there is no single light trapping architecture that can be applied to all photovoltaics. In this work we study a number of different devices: dye-sensitized solar cells, polymer solar cells, silicon-perovskite tandem cells, and single-junction silicon cells. We propose novel photonic crystal-based light trapping designs for each type of device, and evaluate these designs numerically to demonstrate their effectiveness. Full-field optical simulations of the cell are performed for each design, using either finite element method (FEM) or finite-difference time-domain (FDTD) techniques. Where appropriate, electrical modelling of the cell is also performed, through either the use of a simple one-diode model, or by obtaining full solutions to the semiconductor drift-diffusion equations within the cell. In all cases we find that the photonic crystal-based designs significantly outperform their non-nanostructured counterparts. In the case of dye-sensitized and polymer cells, enhancements in light absorption of 33% and 40% (respectively) are seen, relative to reference cells with planar geometries. In the case of silicon-perovskite tandem cells and silicon cells, projected power conversion efficiencies of over 30% are obtained, well beyond the current world record for silicon-based cells. We conclude the thesis with a discussion on the overall prospects for photonic crystal-based solar cells, with a focus on the factors that make solar cell technologies amenable to light trapping.

CMOS Imager Has Better Cross-Talk and Full-Well Performance

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas J.

2011-01-01

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Solid state microdosimetry.

PubMed

Bradley, P D; Rosenfeld, A B; Zaider, M

2001-09-01

A review of solid state microdosimetry is presented with an emphasis on silicon-based devices. The historical foundations and basics of microdosimetry are briefly provided. Various methods of experimental regional microdosimetry are discussed to facilitate a comparison with the more recent development of silicon microdosimetry. In particular, the performance characteristics of a proportional gas counter and a silicon microdosimeter are compared. Recent improvements in silicon microdosimetry address the issues of requirement specification, non-spherical shape, tissue equivalence, sensitive volume definition (charge collection complexity) and low noise requirements which have previously impeded the implementation of silicon-based microdosimetry. A prototype based on silicon-on-insulator technology is described along with some example results from clinical high LET radiotherapy facilities. A brief summary of the applications of microdosimetry is included. c2001 Elsevier Science B.V. All rights reserved.

Semiconductor technology program: Progress briefs

NASA Technical Reports Server (NTRS)

Galloway, K. F.; Scace, R. I.; Walters, E. J.

1981-01-01

Measurement technology for semiconductor materials, process control, and devices, is discussed. Silicon and silicon based devices are emphasized. Highlighted activities include semiinsulating GaAs characterization, an automatic scanning spectroscopic ellipsometer, linewidth measurement and coherence, bandgap narrowing effects in silicon, the evaluation of electrical linewidth uniformity, and arsenicomplanted profiles in silicon.

Design, fabrication, and characterization of 4H-silicon carbide rectifiers for power switching applications

NASA Astrophysics Data System (ADS)

Sheridan, David Charles

Silicon Carbide has received a substantial increase in research interest over the past few years as a base material system for high-frequency and high-power semiconductor devices. Of the over 1200 polytypes, 4H-SiC is the most attractive polytype for power devices due to its wide band gap (3.2eV), excellent thermal conductivity (4.9 W/cm·K), and high critical field strength (˜2 x 106 V/cm). Important for power devices, the 10x increase in critical field strength of SiC allows high voltage blocking layers to be fabricated significantly thinner than for comparable Si devices. For power rectifiers, this reduces device on-resistance, while maintaining the same high voltage blocking capability. In this work, 4H-SiC Schottky, pn, and junction barrier Schottky (JBS) rectifiers for use in high voltage switching applications have been designed, fabricated, and extensively characterized. First, a detailed review of 4H-SiC material parameters was performed and SiC models were implemented into a standard Si drift-diffusion numerical simulator. Using these models, a SiC simulation methodology was developed in order to enable predictive SiC device design. A wide variety of rectifier and edge termination designs were investigated and optimized with respect to breakdown efficiency, area consumption, resistance to interface charge, and fabrication practicality. Simulated termination methods include: field plates, floating guard rings, and a variety of junction termination extensions (JTE). Using the device simulation results, both Schottky and JBS rectifiers were fabricated with a novel self-aligned edge termination design, and fabricated with process elements developed at the Alabama Microelectronics Science and Technology Center facility. These rectifiers exhibited near-ideal forward characteristics and had blocking voltages in excess of 2.5kV. The SiC diodes were subjected to inductive switching tests, and were found to have superior reverse recovery characteristics compared to a similar Si diode. Finally, the performance of these SiC rectifiers were tested in inductive switching circuits and in high dose gamma radiation environments. In both cases, these devices were shown to be superior to their silicon counterparts. The details of this work was presented and published in the proceedings of the 45th International Meeting of the American Vacuum Society [1], the 1999 International Conference on Silicon Carbide and Related Materials [2, 3] and the 2000 European Conference on Silicon Carbide and Related Materials [4]. The expanded conference papers were published in the international journal. Solid-State Electronics [5, 6].

Observation of a photoinduced, resonant tunneling effect in a carbon nanotube–silicon heterojunction

PubMed Central

Ambrosio, Antonio; Boscardin, Maurizio; Castrucci, Paola; Crivellari, Michele; Cilmo, Marco; De Crescenzi, Maurizio; De Nicola, Francesco; Fiandrini, Emanuele; Grossi, Valentina; Maddalena, Pasqualino; Passacantando, Maurizio; Santucci, Sandro; Scarselli, Manuela; Valentini, Antonio

2015-01-01

Summary A significant resonant tunneling effect has been observed under the 2.4 V junction threshold in a large area, carbon nanotube–silicon (CNT–Si) heterojunction obtained by growing a continuous layer of multiwall carbon nanotubes on an n-doped silicon substrate. The multiwall carbon nanostructures were grown by a chemical vapor deposition (CVD) technique on a 60 nm thick, silicon nitride layer, deposited on an n-type Si substrate. The heterojunction characteristics were intensively studied on different substrates, resulting in high photoresponsivity with a large reverse photocurrent plateau. In this paper, we report on the photoresponsivity characteristics of the device, the heterojunction threshold and the tunnel-like effect observed as a function of applied voltage and excitation wavelength. The experiments are performed in the near-ultraviolet to near-infrared wavelength range. The high conversion efficiency of light radiation into photoelectrons observed with the presented layout allows the device to be used as a large area photodetector with very low, intrinsic dark current and noise. PMID:25821710

Observation of a photoinduced, resonant tunneling effect in a carbon nanotube-silicon heterojunction.

PubMed

Aramo, Carla; Ambrosio, Antonio; Ambrosio, Michelangelo; Boscardin, Maurizio; Castrucci, Paola; Crivellari, Michele; Cilmo, Marco; De Crescenzi, Maurizio; De Nicola, Francesco; Fiandrini, Emanuele; Grossi, Valentina; Maddalena, Pasqualino; Passacantando, Maurizio; Santucci, Sandro; Scarselli, Manuela; Valentini, Antonio

2015-01-01

A significant resonant tunneling effect has been observed under the 2.4 V junction threshold in a large area, carbon nanotube-silicon (CNT-Si) heterojunction obtained by growing a continuous layer of multiwall carbon nanotubes on an n-doped silicon substrate. The multiwall carbon nanostructures were grown by a chemical vapor deposition (CVD) technique on a 60 nm thick, silicon nitride layer, deposited on an n-type Si substrate. The heterojunction characteristics were intensively studied on different substrates, resulting in high photoresponsivity with a large reverse photocurrent plateau. In this paper, we report on the photoresponsivity characteristics of the device, the heterojunction threshold and the tunnel-like effect observed as a function of applied voltage and excitation wavelength. The experiments are performed in the near-ultraviolet to near-infrared wavelength range. The high conversion efficiency of light radiation into photoelectrons observed with the presented layout allows the device to be used as a large area photodetector with very low, intrinsic dark current and noise.

Silicon-Based Quantum MOS Technology Development

DTIC Science & Technology

2000-03-07

resonant interband tunnel diodes were demonstrated with peak current density greater than 104 A/cm2; peak-to-valley current ratio exceeding 2 was...photon emission reduce the peak-to-valley current ratio and device performance. Therefore, interband tunnel devices should be more resilient to...Comparison of bipolar interband tunnel and optical devices: (a) Esaki diode biased into the valley current region and (b) optical light emitter. The Esaki

Effect of silicide/silicon hetero-junction structure on thermal conductivity and Seebeck coefficient.

PubMed

Choi, Wonchul; Park, Young-Sam; Hyun, Younghoon; Zyung, Taehyoung; Kim, Jaehyeon; Kim, Soojung; Jeon, Hyojin; Shin, Mincheol; Jang, Moongyu

2013-12-01

We fabricated a thermoelectric device with a silicide/silicon laminated hetero-structure by using RF sputtering and rapid thermal annealing. The device was observed to have Ohmic characteristics by I-V measurement. The temperature differences and Seebeck coefficients of the proposed silicide/silicon laminated and bulk structure were measured. The laminated thermoelectric device shows suppression of heat flow from the hot to cold side. This is supported by the theory that the atomic mass difference between silicide and silicon creates a scattering center for phonons. The major impact of our work is that phonon transmission is suppressed at the interface between silicide and silicon without degrading electrical conductivity. The estimated thermal conductivity of the 3-layer laminated device is 126.2 +/- 3.7 W/m. K. Thus, by using the 3-layer laminated structure, thermal conductivity is reduced by around 16% compared to bulk silicon. However, the Seebeck coefficient of the thermoelectric device is degraded compared to that of bulk silicon. It is understood that electrical conductivity is improved by using silicide as a scattering center.

Effects of Temperature on the Performance and Stability of Recent COTS Silicon Oscillators

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2010-01-01

Silicon oscillators have lately emerged to serve as potential replacement for crystal and ceramic resonators to provide timing and clock signals in electronic systems. These semiconductor-based devices, including those that are based on MEMS technology, are reported to be resistant to vibration and shock (an important criteria for systems to be deployed in space), immune to EMI, consume very low current, require few or no external components, and cover a wide range of frequency for analog and digital circuits. In this work, the performance of five recently-developed COTS silicon oscillator chips from different manufacturers was determined within a temperature range that extended beyond the individual specified range of operation. In addition, restart capability at extreme temperatures, i.e. power switched on while the device was soaking at extreme (hot or cold) temperature, and the effects of thermal cycling under a wide temperature range on the operation of these silicon oscillators were also investigated. Performance characterization of each oscillator was obtained in terms of its output frequency, duty cycle, rise and fall times, and supply current at specific test temperatures. The five different oscillators tested operated beyond their specified temperature region, with some displaying excellent stability throughout the whole test temperature range. Others experienced some instability at certain temperature test points as evidenced by fluctuation in the output frequency. Recovery from temperature-induced changes took place when excessive temperatures were removed. It should also be pointed out that all oscillators were able to restart at the extreme test temperatures and to withstand the limited thermal cycling without undergoing any significant changes in their characteristics. In addition, no physical damage was observed in the packaging material of any of these silicon oscillators due to extreme temperature exposure and thermal cycling. It is recommended that additional and more comprehensive testing under long term cycling be carried out to fully establish the reliability of these devices and to determine their suitability for use in space exploration missions under extreme temperature conditions.

Initial steps toward the realization of large area arrays of single photon counting pixels based on polycrystalline silicon TFTs

NASA Astrophysics Data System (ADS)

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Jiang, Hao; Street, Robert A.; Lu, Jeng Ping

2014-03-01

The thin-film semiconductor processing methods that enabled creation of inexpensive liquid crystal displays based on amorphous silicon transistors for cell phones and televisions, as well as desktop, laptop and mobile computers, also facilitated the development of devices that have become ubiquitous in medical x-ray imaging environments. These devices, called active matrix flat-panel imagers (AMFPIs), measure the integrated signal generated by incident X rays and offer detection areas as large as ~43×43 cm2. In recent years, there has been growing interest in medical x-ray imagers that record information from X ray photons on an individual basis. However, such photon counting devices have generally been based on crystalline silicon, a material not inherently suited to the cost-effective manufacture of monolithic devices of a size comparable to that of AMFPIs. Motivated by these considerations, we have developed an initial set of small area prototype arrays using thin-film processing methods and polycrystalline silicon transistors. These prototypes were developed in the spirit of exploring the possibility of creating large area arrays offering single photon counting capabilities and, to our knowledge, are the first photon counting arrays fabricated using thin film techniques. In this paper, the architecture of the prototype pixels is presented and considerations that influenced the design of the pixel circuits, including amplifier noise, TFT performance variations, and minimum feature size, are discussed.

Nanophotonic Devices in Silicon for Nonlinear Optics

DTIC Science & Technology

2010-10-15

record performance  Demonstration of world‟s lowest loss slot waveguides, made in a DOD-trusted foundry (BAE Systems)  Design study showing...highly-cited design study.  Design study on analog links using the above modulators.  Demonstration of the first silicon waveguides for the mid...Hochberg. Design of transmission line driven slot waveguide Mach-Zehnder interferometers and application to analog optical links. Optics Express 2010

Conformal chemically resistant coatings for microflow devices

DOEpatents

Folta, James A.; Zdeblick, Mark

2003-05-13

A process for coating the inside surfaces of silicon microflow devices, such as electrophoresis microchannels, with a low-stress, conformal (uniform) silicon nitride film which has the ability to uniformly coat deeply-recessed cavities with, for example, aspect ratios of up to 40:1 or higher. The silicon nitride coating allows extended exposure to caustic solutions. The coating enables a microflow device fabricated in silicon to be resistant to all classes of chemicals: acids, bases, and solvents. The process involves low-pressure (vacuum) chemical vapor deposition. The ultra-low-stress silicon nitride deposition process allows 1-2 .mu.m thick films without cracks, and so enables extended chemical protection of a silicon microflow device against caustics for up to 1 year. Tests have demonstrated the resistance of the films to caustic solutions at both ambient and elevated temperatures to 65.degree. C.

Fabrication and testing of freestanding Si nanogratings for UV filtration on space-based particle sensors.

PubMed

Mukherjee, Pran; Zurbuchen, Thomas H; Guo, L Jay

2009-08-12

We demonstrate complete fabrication process integration and device performance of sturdy, self-supported transmission gratings in silicon. Gratings are patterned with nanoimprint lithography and aluminum liftoff on silicon-on-insulator wafers. Double-sided deep reactive ion etching (DRIE) creates freestanding 120 nm half-pitch gratings with 2000 nm depth and built-in 1 mm pitch bulk silicon support structures. Optical characterization demonstrates 10(-4) transmission of UV in the 190-250 nm band while a 25-30% geometric transparency allows particles to pass unimpeded for space plasma measurements.

Improved Devices for Collecting Sweat for Chemical Analysis

NASA Technical Reports Server (NTRS)

Feeback, Daniel L.; Clarke, Mark S. F.

2011-01-01

Improved devices have been proposed for collecting sweat for biochemical analysis especially for determination of the concentration of Ca2+ ions in sweat as a measure of loss of Ca from bones. Unlike commercially available sweat-collection patches used previously in monitoring osteoporosis and in qualitative screening for some drugs, the proposed devices would not allow evaporation of the volatile chemical components (mostly water) of sweat. Moreover, the proposed devices would be designed to enable determination of the volumes of collected sweat. From these volumes and the quantities of Ca2+ and/or other analytes as determined by other means summarized below, one could determine the concentrations of the analytes in sweat. A device according to the proposal would be flexible and would be worn like a commercial sweat-collection patch. It would be made of molded polydimethylsiloxane (silicone rubber) or other suitable material having properties that, for the purpose of analyzing sweat, are similar to those of glass. The die for molding the silicone rubber would be fabricated by a combination of lithography and electroplating. The die would reproducibly form, in the silicone rubber, a precisely defined number of capillary channels per unit area, each channel having a precisely defined volume. Optionally, electrodes for measuring the Ca2+ content of the sweat could be incorporated into the device. The volume of sweat collected in the capillary channels of the device would be determined from (1) the amount of light or radio waves of a given wavelength absorbed by the device and (2) the known geometry of the array of capillary channels. Then, in one of two options, centrifugation would be performed to move the sweat from the capillary tubes to the region containing the electrodes, which would be used to measure the Ca2+ content by a standard technique. In the other option, centrifugation would be performed to remove the sweat from the device to make the sweat available to other analytical instruments for measuring concentrations of substances other than Ca2+.

Improved Devices for Collecting Sweat for Chemical Analysis

NASA Technical Reports Server (NTRS)

Feedback, Daniel L.; Clarke, Mark S. F.

2011-01-01

Improved devices have been proposed for collecting sweat for biochemical analysis - especially for determination of the concentration of Ca2+ ions in sweat as a measure of loss of Ca from bones. Unlike commercially available sweat-collection patches used previously in monitoring osteoporosis and in qualitative screening for some drugs, the proposed devices would not allow evaporation of the volatile chemical components (mostly water) of sweat. Moreover, the proposed devices would be designed to enable determination of the volumes of collected sweat. From these volumes and the quantities of Ca(2+) and/or other analytes as determined by other means summarized below, one could determine the concentrations of the analytes in sweat. A device according to the proposal would be flexible and would be worn like a commercial sweat-collection patch. It would be made of molded polydimethylsiloxane (silicone rubber) or other suitable material having properties that, for the purpose of analyzing sweat, are similar to those of glass. The die for molding the silicone rubber would be fabricated by a combination of lithography and electroplating. The die would reproducibly form, in the silicone rubber, a precisely defined number of capillary channels per unit area, each channel having a precisely defined volume. Optionally, electrodes for measuring the Ca(2+) content of the sweat could be incorporated into the device. The volume of sweat collected in the capillary channels of the device would be determined from (1) the amount of light or radio waves of a given wavelength absorbed by the device and (2) the known geometry of the array of capillary channels. Then, in one of two options, centrifugation would be performed to move the sweat from the capillary tubes to the region containing the electrodes, which would be used to measure the Ca(2+) content by a standard technique. In the other option, centrifugation would be performed to remove the sweat from the device to make the sweat available to other analytical instruments for measuring concentrations of substances other than Ca(2+).

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Thermal and Power Challenges in High Performance Computing Systems

NASA Astrophysics Data System (ADS)

Natarajan, Venkat; Deshpande, Anand; Solanki, Sudarshan; Chandrasekhar, Arun

2009-05-01

This paper provides an overview of the thermal and power challenges in emerging high performance computing platforms. The advent of new sophisticated applications in highly diverse areas such as health, education, finance, entertainment, etc. is driving the platform and device requirements for future systems. The key ingredients of future platforms are vertically integrated (3D) die-stacked devices which provide the required performance characteristics with the associated form factor advantages. Two of the major challenges to the design of through silicon via (TSV) based 3D stacked technologies are (i) effective thermal management and (ii) efficient power delivery mechanisms. Some of the key challenges that are articulated in this paper include hot-spot superposition and intensification in a 3D stack, design/optimization of thermal through silicon vias (TTSVs), non-uniform power loading of multi-die stacks, efficient on-chip power delivery, minimization of electrical hotspots etc.

Performance and breakdown characteristics of irradiated vertical power GaN P-i-N diodes

DOE PAGES

King, M. P.; Armstrong, A. M.; Dickerson, J. R.; ...

2015-10-29

Electrical performance and defect characterization of vertical GaN P-i-N diodes before and after irradiation with 2.5 MeV protons and neutrons is investigated. Devices exhibit increase in specific on-resistance following irradiation with protons and neutrons, indicating displacement damage introduces defects into the p-GaN and n- drift regions of the device that impact on-state device performance. The breakdown voltage of these devices, initially above 1700 V, is observed to decrease only slightly for particle fluence <; 10 13 cm -2. Furthermore, the unipolar figure of merit for power devices indicates that while the on-resistance and breakdown voltage degrade with irradiation, vertical GaNmore » P-i-Ns remain superior to the performance of the best available, unirradiated silicon devices and on-par with unirradiated modern SiC-based power devices.« less

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.; Archer, Leo B.; Brown, George A.; Wallace, Robert M.

2000-01-01

An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.

Active phase correction of high resolution silicon photonic arrayed waveguide gratings

DOE PAGES

Gehl, M.; Trotter, D.; Starbuck, A.; ...

2017-03-10

Arrayed waveguide gratings provide flexible spectral filtering functionality for integrated photonic applications. Achieving narrow channel spacing requires long optical path lengths which can greatly increase the footprint of devices. High index contrast waveguides, such as those fabricated in silicon-on-insulator wafers, allow tight waveguide bends which can be used to create much more compact designs. Both the long optical path lengths and the high index contrast contribute to significant optical phase error as light propagates through the device. Thus, silicon photonic arrayed waveguide gratings require active or passive phase correction following fabrication. We present the design and fabrication of compact siliconmore » photonic arrayed waveguide gratings with channel spacings of 50, 10 and 1 GHz. The largest device, with 11 channels of 1 GHz spacing, has a footprint of only 1.1 cm 2. Using integrated thermo-optic phase shifters, the phase error is actively corrected. We present two methods of phase error correction and demonstrate state-of-the-art cross-talk performance for high index contrast arrayed waveguide gratings. As a demonstration of possible applications, we perform RF channelization with 1 GHz resolution. In addition, we generate unique spectral filters by applying non-zero phase offsets calculated by the Gerchberg Saxton algorithm.« less

Designing 3D Multihierarchical Heteronanostructures for High-Performance On-Chip Hybrid Supercapacitors: Poly(3,4-(ethylenedioxy)thiophene)-Coated Diamond/Silicon Nanowire Electrodes in an Aprotic Ionic Liquid.

PubMed

Aradilla, David; Gao, Fang; Lewes-Malandrakis, Georgia; Müller-Sebert, Wolfgang; Gentile, Pascal; Boniface, Maxime; Aldakov, Dmitry; Iliev, Boyan; Schubert, Thomas J S; Nebel, Christoph E; Bidan, Gérard

2016-07-20

A versatile and robust hierarchically multifunctionalized nanostructured material made of poly(3,4-(ethylenedioxy)thiophene) (PEDOT)-coated diamond@silicon nanowires has been demonstrated to be an excellent capacitive electrode for supercapacitor devices. Thus, the electrochemical deposition of nanometric PEDOT films on diamond-coated silicon nanowire (SiNW) electrodes using N-methyl-N-propylpyrrolidinium bis((trifluoromethyl)sulfonyl)imide ionic liquid displayed a specific capacitance value of 140 F g(-1) at a scan rate of 1 mV s(-1). The as-grown functionalized electrodes were evaluated in a symmetric planar microsupercapacitor using butyltrimethylammonium bis((trifluoromethyl)sulfonyl)imide aprotic ionic liquid as the electrolyte. The device exhibited extraordinary energy and power density values of 26 mJ cm(-2) and 1.3 mW cm(-2) within a large voltage cell of 2.5 V, respectively. In addition, the system was able to retain 80% of its initial capacitance after 15 000 galvanostatic charge-discharge cycles at a high current density of 1 mA cm(-2) while maintaining a Coulombic efficiency around 100%. Therefore, this multifunctionalized hybrid device represents one of the best electrochemical performances concerning coated SiNW electrodes for a high-energy advanced on-chip supercapacitor.

Short wavelength HgCdTe staring focal plane for low background astronomy applications

NASA Technical Reports Server (NTRS)

Hall, D.; Stobie, J.; Hartle, N.; Lacroix, D.; Maschhoff, K.

1989-01-01

The design of a 128x128 staring short wave infrared (SWIR) HgCdTe focal plane incorporating charge integrating transimpedance input preamplifiers is presented. The preamplifiers improve device linearity and uniformity, and provide signal gain ahead of the miltiplexer and readout circuitry. Detector's with cutoff wavelength of 2.5 microns and operated at 80 K have demonstrated impedances in excess of 10(exp 16) ohms with 60 percent quantum efficiency. Focal plane performance using a smaller format device is presented which demonstrates the potential of this approach. Although the design is capable of achieving less than 30 rms electrons with todays technology, initial small format devices demonstrated a read noise of 100 rms electrons and were limited by the atypical high noise performance of the silicon process run. Luminescence from the active silicon circuitry in the multiplexer limits the minimum detector current to a few hundred electrons per second. Approaches to eliminate this excessive source of current is presented which should allow the focal plane to achieve detector background limited performance.

Editorial

NASA Astrophysics Data System (ADS)

Bruzzi, Mara; Cartiglia, Nicolo; Pace, Emanuele; Talamonti, Cinzia

2015-10-01

The 10th edition of the International Conference on Radiation Effects on Semiconductor Materials, Detectors and Devices (RESMDD) was held in Florence, at Dipartimento di Fisica ed Astronomia on October 8-10, 2014. It has been aimed at discussing frontier research activities in several application fields as nuclear and particle physics, astrophysics, medical and solid-state physics. Main topics discussed in this conference concern performance of heavily irradiated silicon detectors, developments required for the luminosity upgrade of the Large Hadron Collider (HL-LHC), ultra-fast silicon detectors design and manufacturing, high-band gap semiconductor detectors, novel semiconductor-based devices for medical applications, radiation damage issues in semiconductors and related radiation-hardening technologies.

Photovoltaic device using single wall carbon nanotubes and method of fabricating the same

DOEpatents

Biris, Alexandru S.; Li, Zhongrui

2012-11-06

A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.

Hybrid graphene/silicon integrated optical isolators with photonic spin–orbit interaction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ma, Jingwen; Sun, Xiankai, E-mail: xksun@cuhk.edu.hk; Shun Hing Institute of Advanced Engineering, The Chinese University of Hong Kong, Shatin, New Territories

2016-04-11

Optical isolators are an important building block in photonic computation and communication. In traditional optics, isolators are realized with magneto-optical garnets. However, it remains challenging to incorporate such materials on an integrated platform because of the difficulty in material growth and bulky device footprint. Here, we propose an ultracompact integrated isolator by exploiting graphene's magneto-optical property on a silicon-on-insulator platform. The photonic nonreciprocity is achieved because the cyclotrons in graphene experiencing different optical spins exhibit different responses to counterpropagating light. Taking advantage of cavity resonance effects, we have numerically optimized a device design, which shows excellent isolation performance with themore » extinction ratio over 45 dB and the insertion loss around 12 dB at a wavelength near 1.55 μm. Featuring graphene's CMOS compatibility and substantially reduced device footprint, our proposal sheds light on monolithic integration of nonreciprocal photonic devices.« less

Design and fabrication of MEMS devices using the integration of MUMPs, trench-refilled molding, DRIE and bulk silicon etching processes

NASA Astrophysics Data System (ADS)

Wu, Mingching; Fang, Weileun

2005-03-01

This work integrates multi-depth DRIE etching, trench-refilled molding, two poly-Si layers MUMPs and bulk releasing to improve the variety and performance of MEMS devices. In summary, the present fabrication process, named MOSBE II, has three merits. First, this process can monolithically fabricate and integrate poly-Si thin-film structures with different thicknesses and stiffnesses, such as the flexible spring and the stiff mirror plate. Second, multi-depth structures, such as vertical comb electrodes, are available from the DRIE processes. Third, a cavity under the micromachined device is provided by the bulk silicon etching process, so that a large out-of-plane motion is allowed. In application, an optical scanner driven by the self-aligned vertical comb actuator was demonstrated. The poly-Si micromachined components fabricated by MOSBE II can further integrate with the MUMPs devices to establish a more powerful MOEMS platform.

High Performance Molybdenum Disulfide Amorphous Silicon Heterojunction Photodetector

PubMed Central

Esmaeili-Rad, Mohammad R.; Salahuddin, Sayeef

2013-01-01

One important use of layered semiconductors such as molybdenum disulfide (MoS2) could be in making novel heterojunction devices leading to functionalities unachievable using conventional semiconductors. Here we demonstrate a metal-semiconductor-metal heterojunction photodetector, made of MoS2 and amorphous silicon (a-Si), with rise and fall times of about 0.3 ms. The transient response does not show persistent (residual) photoconductivity, unlike conventional a-Si devices where it may last 3–5 ms, thus making this heterojunction roughly 10X faster. A photoresponsivity of 210 mA/W is measured at green light, the wavelength used in commercial imaging systems, which is 2−4X larger than that of a-Si and best reported MoS2 devices. The device could find applications in large area electronics, such as biomedical imaging, where a fast response is critical. PMID:23907598

Exploring the Short-Channel Characteristics of Asymmetric Junctionless Double-Gate Silicon-on-Nothing MOSFET

NASA Astrophysics Data System (ADS)

Saha, Priyanka; Banerjee, Pritha; Dash, Dinesh Kumar; Sarkar, Subir Kumar

2018-03-01

This paper presents an analytical model of an asymmetric junctionless double-gate (asymmetric DGJL) silicon-on-nothing metal-oxide-semiconductor field-effect transistor (MOSFET). Solving the 2-D Poisson's equation, the expressions for center potential and threshold voltage are calculated. In addition, the response of the device toward the various short-channel effects like hot carrier effect, drain-induced barrier lowering and threshold voltage roll-off has also been examined along with subthreshold swing and drain current characteristics. Performance analysis of the present model is also demonstrated by comparing its short-channel behavior with conventional DGJL MOSFET. The effect of variation of the device features due to the variation of device parameters is also studied. The simulated results obtained using 2D device simulator, namely ATLAS, are in good agreement with the analytical results, hence validating our derived model.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Plasmonic engineering of spontaneous emission from silicon nanocrystals.

PubMed

Goffard, Julie; Gérard, Davy; Miska, Patrice; Baudrion, Anne-Laure; Deturche, Régis; Plain, Jérôme

2013-01-01

Silicon nanocrystals offer huge advantages compared to other semi-conductor quantum dots as they are made from an abundant, non-toxic material and are compatible with silicon devices. Besides, among a wealth of extraordinary properties ranging from catalysis to nanomedicine, metal nanoparticles are known to increase the radiative emission rate of semiconductor quantum dots. Here, we use gold nanoparticles to accelerate the emission of silicon nanocrystals. The resulting integrated hybrid emitter is 5-fold brighter than bare silicon nanocrystals. We also propose an in-depth analysis highlighting the role of the different physical parameters in the photoluminescence enhancement phenomenon. This result has important implications for the practical use of silicon nanocrystals in optoelectronic devices, for instance for the design of efficient down-shifting devices that could be integrated within future silicon solar cells.

Bolometric Array Detectors for Space-Borne Astronomy

NASA Technical Reports Server (NTRS)

Lange, Andrew E.

2000-01-01

Funding from the NASA Innovative Research Grant was used to develop bolometric detectors. As described in the proposal, silicon nitride micromesh ('spider-web') absorbers had been demonstrated at U.C. Berkeley but not developed to be flight-worthy devices. We proceeded to first fabricate bolometers with Neutron Transmutation Doped (NTD) Ge thermistors that demonstrated high optical coupling (Church et al. 1996) and were developed for a ground-based millimeter-wave receiver (Mauskopf et al. 1997). The next generation of devices used In bump-bonded thermistors to achieve devices with performance product NEP*sqrt(tau) = 3e - 18 j at 300 mK, demonstrating a full order of magnitude improvement over pervious devices. These devices achieved an NEP = 1e-18 W/rtHz (Murray et al. 1996) as promised in the proposal. Sensitivities as good as 1e - 19 W/rtHz appear achievable with the silicon nitride architecture (Bock et al. 1997). Finally, arrays of micromesh bolometers were shown to be feasible in the last year of the program by etching a large number of devices on a single silicon wafer (75 mm). Full arrays were subsequently demonstrated for selection on the ESA/NASA Far-Infrared Space Telescope (FIRST) in competition with detectors provided by CEA in France and GSFC in the US Micromesh bolometer arrays are now baselined for both the ESA/NASA Planck and FIRST missions.

Charge-injection-device 2 x 64 element infrared array performance

NASA Technical Reports Server (NTRS)

Mckelvey, M. E.; Mccreight, C. R.; Goebel, J. H.; Reeves, A. A.

1985-01-01

Three 2 x 64 element Si:Bi accumulation-mode charge-injection-device (CID) arrays were tested at low and moderate background to evaluate their usefulness for space-based astronomical observations. Testing was conducted both in the laboratory and in ground-based telescope IR observations. The devices showed an average readout noise level below 200 equivalent electrons, a peak responsivity of 4 A/W, and a noise equivalent power of 3 x 10 to the -17th W/sq rt Hz. This sensitivity compares well with that of nonintegrating discrete extrinsic silicon photoconductors. The array well capacity was significantly smaller than predicted. The measured sensitivity makes extrinsic silicon CID arrays useful for certain astronomical applications. However, their readout efficiency and frequency response represent serious limitations in low-background applications.

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Raichoudhury, P.; Mollenkopf, H. C.

1981-01-01

The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly solar grade silicon. Cr is highly mobile in silicon even at temperatures as low as 600 C. Contrasting with earlier data for Mo, Ti, and V, Cr concentrations vary from place to place in polycrystalline silicon wafers and the electrically-active Cr concentration in the polysilicon is more than an order of magnitude smaller than would be projected from single crystal impurity data. We hypothesize that Cr diffuses during ingot cooldown after growth, preferentially segregates to grain and becomes electrically deactivated. Accelerated aging data from Ni-contaminated silicon imply that no significant impurity-induced cell performance reduction should be expected over a twenty year device lifetime.

Process for forming a porous silicon member in a crystalline silicon member

DOEpatents

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

Magneto-optical non-reciprocal devices in silicon photonics

PubMed Central

Shoji, Yuya; Mizumoto, Tetsuya

2014-01-01

Silicon waveguide optical non-reciprocal devices based on the magneto-optical effect are reviewed. The non-reciprocal phase shift caused by the first-order magneto-optical effect is effective in realizing optical non-reciprocal devices in silicon waveguide platforms. In a silicon-on-insulator waveguide, the low refractive index of the buried oxide layer enhances the magneto-optical phase shift, which reduces the device footprints. A surface activated direct bonding technique was developed to integrate a magneto-optical garnet crystal on the silicon waveguides. A silicon waveguide optical isolator based on the magneto-optical phase shift was demonstrated with an optical isolation of 30 dB and insertion loss of 13 dB at a wavelength of 1548 nm. Furthermore, a four port optical circulator was demonstrated with maximum isolations of 15.3 and 9.3 dB in cross and bar ports, respectively, at a wavelength of 1531 nm. PMID:27877640

Development of UItra-Low Temperature Motor Controllers: Ultra Low Temperatures Evaluation and Characterization of Semiconductor Technologies For The Next Generation Space Telescope

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.

2003-01-01

Electronics designed for low temperature operation will result in more efficient systems than room temperature. This improvement is a result of better electronic, electrical, and thermal properties of materials at low temperatures. In particular, the performance of certain semiconductor devices improves with decreasing temperature down to ultra-low temperature (-273 'C). The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components and systems suitable for applications in deep space missions. Research is being conducted on devices and systems for use down to liquid helium temperatures (-273 'C). Some of the components that are being characterized include semiconductor switching devices, resistors, magnetics, and capacitors. The work performed this summer has focused on the evaluation of silicon-, silicon-germanium- and gallium-Arsenide-based (GaAs) bipolar, MOS and CMOS discrete components and integrated circuits (ICs), from room temperature (23 'C) down to ultra low temperatures (-263 'C).

A self-assembled microbonded germanium/silicon heterojunction photodiode for 25 Gb/s high-speed optical interconnects

PubMed Central

Tseng, Chih-Kuo; Chen, Wei-Ting; Chen, Ku-Hung; Liu, Han-Din; Kang, Yimin; Na, Neil; Lee, Ming-Chang M.

2013-01-01

A novel technique using surface tension to locally bond germanium (Ge) on silicon (Si) is presented for fabricating high performance Ge/Si photodiodes. Surface tension is a cohesive force among liquid molecules that tends to bring contiguous objects in contact to maintain a minimum surface energy. We take advantage of this phenomenon to fabricate a heterojunction optoelectronic device where the lattice constants of joined semiconductors are different. A high-speed Ge/Si heterojunction waveguide photodiode is presented by microbonding a beam-shaped Ge, first grown by rapid-melt-growth (RMG) method, on top of a Si waveguide via surface tension. Excellent device performances such as an operating bandwidth of 17 GHz and a responsivity of 0.66 and 0.70 A/W at the reverse bias of −4 and −6 V, respectively, are demonstrated. This technique can be simply implemented via modern complementary metal-oxide-semiconductor (CMOS) fabrication technologies for integrating Ge on Si devices. PMID:24232956

Micro-opto-mechanical devices and systems using epitaxial lift off

NASA Technical Reports Server (NTRS)

Camperi-Ginestet, C.; Kim, Young W.; Wilkinson, S.; Allen, M.; Jokerst, N. M.

1993-01-01

The integration of high quality, single crystal thin film gallium arsenide (GaAs) and indium phosphide (InP) based photonic and electronic materials and devices with host microstructures fabricated from materials such as silicon (Si), glass, and polymers will enable the fabrication of the next generation of micro-opto-mechanical systems (MOMS) and optoelectronic integrated circuits. Thin film semiconductor devices deposited onto arbitrary host substrates and structures create hybrid (more than one material) near-monolithic integrated systems which can be interconnected electrically using standard inexpensive microfabrication techniques such as vacuum metallization and photolithography. These integrated systems take advantage of the optical and electronic properties of compound semiconductor devices while still using host substrate materials such as silicon, polysilicon, glass and polymers in the microstructures. This type of materials optimization for specific tasks creates higher performance systems than those systems which must use trade-offs in device performance to integrate all of the function in a single material system. The low weight of these thin film devices also makes them attractive for integration with micromechanical devices which may have difficulty supporting and translating the full weight of a standard device. These thin film devices and integrated systems will be attractive for applications, however, only when the development of low cost, high yield fabrication and integration techniques makes their use economically feasible. In this paper, we discuss methods for alignment, selective deposition, and interconnection of thin film epitaxial GaAs and InP based devices onto host substrates and host microstructures.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Rapid Prototyping of Nanofluidic Slits in a Silicone Bilayer

PubMed Central

Kole, Thomas P.; Liao, Kuo-Tang; Schiffels, Daniel; Ilic, B. Robert; Strychalski, Elizabeth A.; Kralj, Jason G.; Liddle, J. Alexander; Dritschilo, Anatoly; Stavis, Samuel M.

2015-01-01

This article reports a process for rapidly prototyping nanofluidic devices, particularly those comprising slits with microscale widths and nanoscale depths, in silicone. This process consists of designing a nanofluidic device, fabricating a photomask, fabricating a device mold in epoxy photoresist, molding a device in silicone, cutting and punching a molded silicone device, bonding a silicone device to a glass substrate, and filling the device with aqueous solution. By using a bilayer of hard and soft silicone, we have formed and filled nanofluidic slits with depths of less than 400 nm and aspect ratios of width to depth exceeding 250 without collapse of the slits. An important attribute of this article is that the description of this rapid prototyping process is very comprehensive, presenting context and details which are highly relevant to the rational implementation and reliable repetition of the process. Moreover, this process makes use of equipment commonly found in nanofabrication facilities and research laboratories, facilitating the broad adaptation and application of the process. Therefore, while this article specifically informs users of the Center for Nanoscale Science and Technology (CNST) at the National Institute of Standards and Technology (NIST), we anticipate that this information will be generally useful for the nanofabrication and nanofluidics research communities at large, and particularly useful for neophyte nanofabricators and nanofluidicists. PMID:26958449

Device research task (processing and high-efficiency solar cells)

NASA Technical Reports Server (NTRS)

1986-01-01

This task has been expanded since the last 25th Project Integration Meeting (PIM) to include process research in addition to device research. The objective of this task is to assist the Flat-plate Solar Array (FSA) Project in meeting its near- and long-term goals by identifying and implementing research in the areas of device physics, device structures, measurement techniques, material-device interactions, and cell processing. The research efforts of this task are described and reflect the deversity of device research being conducted. All of the contracts being reported are either completed or near completion and culminate the device research efforts of the FSA Project. Optimazation methods and silicon solar cell numerical models, carrier transport and recombination parameters in heavily doped silicon, development and analysis of silicon solar cells of near 20% efficiency, and SiN sub x passivation of silicon surfaces are discussed.

Sputtered pin amorphous silicon semi-conductor device and method therefor

DOEpatents

Moustakas, Theodore D.; Friedman, Robert A.

1983-11-22

A high efficiency amorphous silicon PIN semi-conductor device is constructed by the sequential sputtering of N, I and P layers of amorphous silicon and at least one semi-transparent ohmic electrode. A method of construction produces a PIN device, exhibiting enhanced physical integrity and facilitates ease of construction in a singular vacuum system and vacuum pump down procedure.

A Manufacturing Cost and Supply Chain Analysis of SiC Power Electronics Applicable to Medium-Voltage Motor Drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horowitz, Kelsey; Remo, Timothy; Reese, Samantha

Wide bandgap (WBG) semiconductor devices are increasingly being considered for use in certain power electronics applications, where they can improve efficiency, performance, footprint, and, potentially, total system cost compared to systems using traditional silicon (Si) devices. Silicon carbide (SiC) devices in particular -- which are currently more mature than other WBG devices -- are poised for growth in the coming years. Today, the manufacturing of SiC wafers is concentrated in the United States, and chip production is split roughly equally between the United States, Japan, and Europe. Established contract manufacturers located throughout Asia typically carry out manufacturing of WBG powermore » modules. We seek to understand how global manufacturing of SiC components may evolve over time by illustrating the regional cost drivers along the supply chain and providing an overview of other factors that influence where manufacturing is sited. We conduct this analysis for a particular case study where SiC devices are used in a medium-voltage motor drive.« less

Nanohole Structuring for Improved Performance of Hydrogenated Amorphous Silicon Photovoltaics.

PubMed

Johlin, Eric; Al-Obeidi, Ahmed; Nogay, Gizem; Stuckelberger, Michael; Buonassisi, Tonio; Grossman, Jeffrey C

2016-06-22

While low hole mobilities limit the current collection and efficiency of hydrogenated amorphous silicon (a-Si:H) photovoltaic devices, attempts to improve mobility of the material directly have stagnated. Herein, we explore a method of utilizing nanostructuring of a-Si:H devices to allow for improved hole collection in thick absorber layers. This is achieved by etching an array of 150 nm diameter holes into intrinsic a-Si:H and then coating the structured material with p-type a-Si:H and a conformal zinc oxide transparent conducting layer. The inclusion of these nanoholes yields relative power conversion efficiency (PCE) increases of ∼45%, from 7.2 to 10.4% PCE for small area devices. Comparisons of optical properties, time-of-flight mobility measurements, and internal quantum efficiency spectra indicate this efficiency is indeed likely occurring from an improved collection pathway provided by the nanostructuring of the devices. Finally, we estimate that through modest optimizations of the design and fabrication, PCEs of beyond 13% should be obtainable for similar devices.

Surface engineered porous silicon for stable, high performance electrochemical supercapacitors

PubMed Central

Oakes, Landon; Westover, Andrew; Mares, Jeremy W.; Chatterjee, Shahana; Erwin, William R.; Bardhan, Rizia; Weiss, Sharon M.; Pint, Cary L.

2013-01-01

Silicon materials remain unused for supercapacitors due to extreme reactivity of silicon with electrolytes. However, doped silicon materials boast a low mass density, excellent conductivity, a controllably etched nanoporous structure, and combined earth abundance and technological presence appealing to diverse energy storage frameworks. Here, we demonstrate a universal route to transform porous silicon (P-Si) into stable electrodes for electrochemical devices through growth of an ultra-thin, conformal graphene coating on the P-Si surface. This graphene coating simultaneously passivates surface charge traps and provides an ideal electrode-electrolyte electrochemical interface. This leads to 10–40X improvement in energy density, and a 2X wider electrochemical window compared to identically-structured unpassivated P-Si. This work demonstrates a technique generalizable to mesoporous and nanoporous materials that decouples the engineering of electrode structure and electrochemical surface stability to engineer performance in electrochemical environments. Specifically, we demonstrate P-Si as a promising new platform for grid-scale and integrated electrochemical energy storage. PMID:24145684

Surface engineered porous silicon for stable, high performance electrochemical supercapacitors.

PubMed

Oakes, Landon; Westover, Andrew; Mares, Jeremy W; Chatterjee, Shahana; Erwin, William R; Bardhan, Rizia; Weiss, Sharon M; Pint, Cary L

2013-10-22

Silicon materials remain unused for supercapacitors due to extreme reactivity of silicon with electrolytes. However, doped silicon materials boast a low mass density, excellent conductivity, a controllably etched nanoporous structure, and combined earth abundance and technological presence appealing to diverse energy storage frameworks. Here, we demonstrate a universal route to transform porous silicon (P-Si) into stable electrodes for electrochemical devices through growth of an ultra-thin, conformal graphene coating on the P-Si surface. This graphene coating simultaneously passivates surface charge traps and provides an ideal electrode-electrolyte electrochemical interface. This leads to 10-40X improvement in energy density, and a 2X wider electrochemical window compared to identically-structured unpassivated P-Si. This work demonstrates a technique generalizable to mesoporous and nanoporous materials that decouples the engineering of electrode structure and electrochemical surface stability to engineer performance in electrochemical environments. Specifically, we demonstrate P-Si as a promising new platform for grid-scale and integrated electrochemical energy storage.

Surface engineered porous silicon for stable, high performance electrochemical supercapacitors

NASA Astrophysics Data System (ADS)

Oakes, Landon; Westover, Andrew; Mares, Jeremy W.; Chatterjee, Shahana; Erwin, William R.; Bardhan, Rizia; Weiss, Sharon M.; Pint, Cary L.

2013-10-01

Silicon materials remain unused for supercapacitors due to extreme reactivity of silicon with electrolytes. However, doped silicon materials boast a low mass density, excellent conductivity, a controllably etched nanoporous structure, and combined earth abundance and technological presence appealing to diverse energy storage frameworks. Here, we demonstrate a universal route to transform porous silicon (P-Si) into stable electrodes for electrochemical devices through growth of an ultra-thin, conformal graphene coating on the P-Si surface. This graphene coating simultaneously passivates surface charge traps and provides an ideal electrode-electrolyte electrochemical interface. This leads to 10-40X improvement in energy density, and a 2X wider electrochemical window compared to identically-structured unpassivated P-Si. This work demonstrates a technique generalizable to mesoporous and nanoporous materials that decouples the engineering of electrode structure and electrochemical surface stability to engineer performance in electrochemical environments. Specifically, we demonstrate P-Si as a promising new platform for grid-scale and integrated electrochemical energy storage.

Programmable 2-D Addressable Cryogenic Aperture Masks

NASA Technical Reports Server (NTRS)

Kutyrev, A. S.; Moseley, S. H.; Jhabvala, M.; Li, M.; Schwinger, D. S.; Silverberg, R. F.; Wesenberg, R. P.

2004-01-01

We are developing a two-dimensional array of square microshutters (programmable aperture mask) for a multi-object spectrometer for the James Webb Space Telescope (JWST). This device will provide random access selection of the areas in the field to be studied. The device is in essence a close packed array of square slits, each of which can be opened independently to select areas of the sky for detailed study.The device is produced using a 100-micron thick silicon wafer as a substrate with 0.5-micron thick silicon nitride shutters on top of it. Silicon nitride has been selected as the blade and flexure material because its stiffness allows thinner and lighter structures than single crystal Si, the chief alternative, and because of its ease of manufacture. The 100 micron silicon wafer is backetched in a high aspect ratio Deep Reactive Ion Etching (Deep RIE) to leave only a support grid for the shutters and the address electronics. The shutter actuation is done magnetically whereas addressing is electrostatic. 128x128 format microshutter arrays have been produced. Their operation has been demostarted on 32x32 subarrays. Good reliability of the fabrication process and good quality of the microshutters has been achieved. The mechanical behavior and optical performance of the fabricated arrays at cryogenic temperature are being studied.

Characterization of Si (sub X)Ge (sub 1-x)/Si Heterostructures for Device Applications Using Spectroscopic Ellipsometry

NASA Technical Reports Server (NTRS)

Sieg, R. M.; Alterovitz, S. A.; Croke, E. T.; Harrell, M. J.; Tanner, M.; Wang, K. L.; Mena, R. A.; Young, P. G.

1993-01-01

Spectroscopic ellipsometry (SE) characterization of several complex Si (sub X)Ge (sub 1-x)/Si heterostructures prepared for device fabrication, including structures for heterojunction bipolar transistors (HBT), p-type and n-type heterostructure modulation doped field effect transistors, has been performed. We have shown that SE can simultaneously determine all active layer thicknesses, Si (sub X)Ge (sub 1-x) compositions, and the oxide overlayer thickness, with only a general knowledge of the structure topology needed a priori. The characterization of HBT material included the SE analysis of a Si (sub X)Ge (sub 1-x) layer deeply buried (600 nanometers) under the silicon emitter and cap layers. In the SE analysis of n-type heterostructures, we examined for the first time a silicon layer under tensile strain. We found that an excellent fit can be obtained using optical constants of unstrained silicon to represent the strained silicon conduction layer. We also used SE to measure lateral sample homogeneity, providing quantitative identification of the inhomogeneous layer. Surface overlayers resulting from prior sample processing were also detected and measured quantitatively. These results should allow SE to be used extensively as a non-destructive means of characterizing Si (sub X)Ge (sub 1-x)/Si heterostructures prior to device fabrication and testing.

Back contact to film silicon on metal for photovoltaic cells

DOEpatents

Branz, Howard M.; Teplin, Charles; Stradins, Pauls

2013-06-18

A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

PubMed Central

Rossi, Alessandro; Tanttu, Tuomo; Hudson, Fay E.; Sun, Yuxin; Möttönen, Mikko; Dzurak, Andrew S.

2015-01-01

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization. PMID:26067215

Energy Storage Materials from Nature through Nanotechnology: A Sustainable Route from Reed Plants to a Silicon Anode for Lithium-Ion Batteries.

PubMed

Liu, Jun; Kopold, Peter; van Aken, Peter A; Maier, Joachim; Yu, Yan

2015-08-10

Silicon is an attractive anode material in energy storage devices, as it has a ten times higher theoretical capacity than its state-of-art carbonaceous counterpart. However, the common process to synthesize silicon nanostructured electrodes is complex, costly, and energy-intensive. Three-dimensional (3D) porous silicon-based anode materials have been fabricated from natural reed leaves by calcination and magnesiothermic reduction. This sustainable and highly abundant silica source allows for facile production of 3D porous silicon with very good electrochemical performance. The obtained silicon anode retains the 3D hierarchical architecture of the reed leaf. Impurity leaching and gas release during the fabrication process leads to an interconnected porosity and the reductive treatment to an inside carbon coating. Such anodes show a remarkable Li-ion storage performance: even after 4000 cycles and at a rate of 10 C, a specific capacity of 420 mA h g(-1) is achieved. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Infrared bolometers with silicon nitride micromesh absorbers

NASA Technical Reports Server (NTRS)

Bock, J. J.; Turner, A. D.; DelCastillo, H. M.; Beeman, J. W.; Lange, A. E.; Mauskopf, P. D.

1996-01-01

Sensitive far infrared and millimeter wave bolometers fabricated from a freestanding membrane of low stress silicon nitride are reported. The absorber, consisting of a metallized silicon nitride micromesh thermally isolated by radial legs of silicon nitride, is placed in an integrating cavity to efficiently couple to single mode or multiple mode infrared radiation. This structure provides low heat capacity, low thermal conduction and minimal cross section to energetic particles. A neutron transmutation doped Ge thermister is bump bonded to the center of the device and read out with evaporated Cr-Au leads. The limiting performance of the micromesh absorber is discussed and the recent results obtained from a 300 mK cold stage are summarized.

The effect of dry shear aligning of nanotube thin films on the photovoltaic performance of carbon nanotube-silicon solar cells.

PubMed

Stolz, Benedikt W; Tune, Daniel D; Flavel, Benjamin S

2016-01-01

Recent results in the field of carbon nanotube-silicon solar cells have suggested that the best performance is obtained when the nanotube film provides good coverage of the silicon surface and when the nanotubes in the film are aligned parallel to the surface. The recently developed process of dry shear aligning - in which shear force is applied to the surface of carbon nanotube thin films in the dry state, has been shown to yield nanotube films that are very flat and in which the surface nanotubes are very well aligned in the direction of shear. It is thus reasonable to expect that nanotube films subjected to dry shear aligning should outperform otherwise identical films formed by other processes. In this work, the fabrication and characterisation of carbon nanotube-silicon solar cells using such films is reported, and the photovoltaic performance of devices produced with and without dry shear aligning is compared.

The effect of dry shear aligning of nanotube thin films on the photovoltaic performance of carbon nanotube–silicon solar cells

PubMed Central

Stolz, Benedikt W; Tune, Daniel D

2016-01-01

Summary Recent results in the field of carbon nanotube–silicon solar cells have suggested that the best performance is obtained when the nanotube film provides good coverage of the silicon surface and when the nanotubes in the film are aligned parallel to the surface. The recently developed process of dry shear aligning – in which shear force is applied to the surface of carbon nanotube thin films in the dry state, has been shown to yield nanotube films that are very flat and in which the surface nanotubes are very well aligned in the direction of shear. It is thus reasonable to expect that nanotube films subjected to dry shear aligning should outperform otherwise identical films formed by other processes. In this work, the fabrication and characterisation of carbon nanotube–silicon solar cells using such films is reported, and the photovoltaic performance of devices produced with and without dry shear aligning is compared. PMID:27826524

Noise performance of 0.35-(mu)m SOI CMOS devices and micropower preamplifier following 63-MeV, 1-Mrad (Si) proton irradiation

NASA Technical Reports Server (NTRS)

Binkley, D. M.; Hopper, C. E.; Cressler, J. D.; Mojarradi, M. M.; Blalock, B. J.

2004-01-01

This paper presents measured noise for 0.35(mu)m, silicon-on-insulator devices and a micropower preamplifier following 63-MeV, 1-Mrad (Si) proton irradiation. Flicker noise voltage, important for gyros having low frequency output, increases less than 32% after irradiation.

Reduced Moment-Based Models for Oxygen Precipitates and Dislocation Loops in Silicon

NASA Astrophysics Data System (ADS)

Trzynadlowski, Bart

The demand for ever smaller, higher-performance integrated circuits and more efficient, cost-effective solar cells continues to push the frontiers of process technology. Fabrication of silicon devices requires extremely precise control of impurities and crystallographic defects. Failure to do so not only reduces performance, efficiency, and yield, it threatens the very survival of commercial enterprises in today's fiercely competitive and price-sensitive global market. The presence of oxygen in silicon is an unavoidable consequence of the Czochralski process, which remains the most popular method for large-scale production of single-crystal silicon. Oxygen precipitates that form during thermal processing cause distortion of the surrounding silicon lattice and can lead to the formation of dislocation loops. Localized deformation caused by both of these defects introduces potential wells that trap diffusing impurities such as metal atoms, which is highly desirable if done far away from sensitive device regions. Unfortunately, dislocations also reduce the mechanical strength of silicon, which can cause wafer warpage and breakage. Engineers must negotiate this and other complex tradeoffs when designing fabrication processes. Accomplishing this in a complex, modern process involving a large number of thermal steps is impossible without the aid of computational models. In this dissertation, new models for oxygen precipitation and dislocation loop evolution are described. An oxygen model using kinetic rate equations to evolve the complete precipitate size distribution was developed first. This was then used to create a reduced model tracking only the moments of the size distribution. The moment-based model was found to run significantly faster than its full counterpart while accurately capturing the evolution of oxygen precipitates. The reduced model was fitted to experimental data and a sensitivity analysis was performed to assess the robustness of the results. Source code for both models is included. A moment-based model for dislocation loop formation from {311} defects in ion-implanted silicon was also developed and validated against experimental data. Ab initio density functional theory calculations of stacking faults and edge dislocations were performed to extract energies and elastic properties. This allowed the effect of applied stress on the evolution of {311} defects and dislocation loops to be investigated.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Bioresorbable silicon electronics for transient spatiotemporal mapping of electrical activity from the cerebral cortex.

PubMed

Yu, Ki Jun; Kuzum, Duygu; Hwang, Suk-Won; Kim, Bong Hoon; Juul, Halvor; Kim, Nam Heon; Won, Sang Min; Chiang, Ken; Trumpis, Michael; Richardson, Andrew G; Cheng, Huanyu; Fang, Hui; Thomson, Marissa; Bink, Hank; Talos, Delia; Seo, Kyung Jin; Lee, Hee Nam; Kang, Seung-Kyun; Kim, Jae-Hwan; Lee, Jung Yup; Huang, Younggang; Jensen, Frances E; Dichter, Marc A; Lucas, Timothy H; Viventi, Jonathan; Litt, Brian; Rogers, John A

2016-07-01

Bioresorbable silicon electronics technology offers unprecedented opportunities to deploy advanced implantable monitoring systems that eliminate risks, cost and discomfort associated with surgical extraction. Applications include postoperative monitoring and transient physiologic recording after percutaneous or minimally invasive placement of vascular, cardiac, orthopaedic, neural or other devices. We present an embodiment of these materials in both passive and actively addressed arrays of bioresorbable silicon electrodes with multiplexing capabilities, which record in vivo electrophysiological signals from the cortical surface and the subgaleal space. The devices detect normal physiologic and epileptiform activity, both in acute and chronic recordings. Comparative studies show sensor performance comparable to standard clinical systems and reduced tissue reactivity relative to conventional clinical electrocorticography (ECoG) electrodes. This technology offers general applicability in neural interfaces, with additional potential utility in treatment of disorders where transient monitoring and modulation of physiologic function, implant integrity and tissue recovery or regeneration are required.

Infrared photocurrent management in monolithic perovskite/silicon heterojunction tandem solar cells by using a nanocrystalline silicon oxide interlayer.

PubMed

Mazzarella, Luana; Werth, Matteo; Jäger, Klaus; Jošt, Marko; Korte, Lars; Albrecht, Steve; Schlatmann, Rutger; Stannowski, Bernd

2018-05-14

We performed optical simulations using hydrogenated nanocrystalline silicon oxide (nc-SiO x :H) as n-doped interlayer in monolithic perovskite/c-Si heterojunction tandem solar cells. Depending on the adjustable value of its refractive index (2.0 - 2.7) and thickness, nc-SiO x :H allows to optically manage the infrared light absorption in the c-Si bottom cell minimizing reflection losses. We give guidelines for nc-SiO x :H optimization in tandem devices in combination with a systematic investigation of the effect of the surface morphology (flat or textured) on the photocurrent density. For full-flat and rear textured devices, we found matched photocurrents higher than 19 and 20 mA/cm 2 , respectively, using a 90 nm nc-SiO x :H interlayer with a refractive index of 2.7.

Growth of low temperature silicon nano-structures for electronic and electrical energy generation applications.

PubMed

Gabrielyan, Nare; Saranti, Konstantina; Manjunatha, Krishna Nama; Paul, Shashi

2013-02-15

This paper represents the lowest growth temperature for silicon nano-wires (SiNWs) via a vapour-liquid-solid method, which has ever been reported in the literature. The nano-wires were grown using plasma-enhanced chemical vapour deposition technique at temperatures as low as 150°C using gallium as the catalyst. This study investigates the structure and the size of the grown silicon nano-structure as functions of growth temperature and catalyst layer thickness. Moreover, the choice of the growth temperature determines the thickness of the catalyst layer to be used.The electrical and optical characteristics of the nano-wires were tested by incorporating them in photovoltaic solar cells, two terminal bistable memory devices and Schottky diode. With further optimisation of the growth parameters, SiNWs, grown by our method, have promising future for incorporation into high performance electronic and optical devices.

Growth of low temperature silicon nano-structures for electronic and electrical energy generation applications

PubMed Central

2013-01-01

This paper represents the lowest growth temperature for silicon nano-wires (SiNWs) via a vapour-liquid–solid method, which has ever been reported in the literature. The nano-wires were grown using plasma-enhanced chemical vapour deposition technique at temperatures as low as 150°C using gallium as the catalyst. This study investigates the structure and the size of the grown silicon nano-structure as functions of growth temperature and catalyst layer thickness. Moreover, the choice of the growth temperature determines the thickness of the catalyst layer to be used. The electrical and optical characteristics of the nano-wires were tested by incorporating them in photovoltaic solar cells, two terminal bistable memory devices and Schottky diode. With further optimisation of the growth parameters, SiNWs, grown by our method, have promising future for incorporation into high performance electronic and optical devices. PMID:23413969

Investigation of silicide-induced-dopant-activation for steep tunnel junction in tunnel field effect transistor (TFET)

NASA Astrophysics Data System (ADS)

Kim, Sihyun; Kwon, Dae Woong; Park, Euyhwan; Lee, Junil; Lee, Roongbin; Lee, Jong-Ho; Park, Byung-Gook

2018-02-01

Numerous researches for making steep tunnel junction within tunnel field-effect transistor (TFET) have been conducted. One of the ways to make an abrupt junction is source/drain silicidation, which uses the phenomenon often called silicide-induced-dopant-segregation. It is revealed that the silicide process not only helps dopants to pile up adjacent to the metal-silicon alloy, also induces the dopant activation, thereby making it possible to avoid additional high temperature process. In this report, the availability of dopant activation induced by metal silicide process was thoroughly investigated by diode measurement and device simulation. Metal-silicon (MS) diodes having p+ and n+ silicon formed on the p- substrate exhibit the characteristics of ohmic and pn diodes respectively, for both the samples with and without high temperature annealing. The device simulation for TFETs with dopant-segregated source was also conducted, which verified enhanced DC performance.

Integrating a dual-silicon photoelectrochemical cell into a redox flow battery for unassisted photocharging.

PubMed

Liao, Shichao; Zong, Xu; Seger, Brian; Pedersen, Thomas; Yao, Tingting; Ding, Chunmei; Shi, Jingying; Chen, Jian; Li, Can

2016-05-04

Solar rechargeable flow cells (SRFCs) provide an attractive approach for in situ capture and storage of intermittent solar energy via photoelectrochemical regeneration of discharged redox species for electricity generation. However, overall SFRC performance is restricted by inefficient photoelectrochemical reactions. Here we report an efficient SRFC based on a dual-silicon photoelectrochemical cell and a quinone/bromine redox flow battery for in situ solar energy conversion and storage. Using narrow bandgap silicon for efficient photon collection and fast redox couples for rapid interface charge injection, our device shows an optimal solar-to-chemical conversion efficiency of ∼5.9% and an overall photon-chemical-electricity energy conversion efficiency of ∼3.2%, which, to our knowledge, outperforms previously reported SRFCs. The proposed SRFC can be self-photocharged to 0.8 V and delivers a discharge capacity of 730 mAh l(-1). Our work may guide future designs for highly efficient solar rechargeable devices.

Stress Analysis of SiC MEMS Using Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Ness, Stanley J.; Marciniak, M. A.; Lott, J. A.; Starman, L. A.; Busbee, J. D.; Melzak, J. M.

2003-03-01

During the fabrication of Micro-Electro-Mechanical Systems (MEMS), residual stress is often induced in the thin films that are deposited to create these systems. These stresses can cause the device to fail due to buckling, curling, or fracture. Industry is looking for ways to characterize the stress during the deposition of thin films in order to reduce or eliminate device failure. Micro-Raman spectroscopy has been successfully used to characterize poly-Si MEMS devices made with the MUMPS® process. Raman spectroscopy was selected because it is nondestructive, fast and has the potential for in situ stress monitoring. This research attempts to use Raman spectroscopy to analyze the stress in SiC MEMS made with the MUSiC® process. Raman spectroscopy is performed on 1-2-micron-thick SiC thin films deposited on silicon, silicon nitride, and silicon oxide substrates. The most common poly-type of SiC found in thin film MEMS made with the MUSiC® process is 3C-SiC. Research also includes baseline spectra of 6H, 4H, and 15R poly-types of bulk SiC.

Strategies to improve electrode positioning and safety in cochlear implants.

PubMed

Rebscher, S J; Heilmann, M; Bruszewski, W; Talbot, N H; Snyder, R L; Merzenich, M M

1999-03-01

An injection-molded internal supporting rib has been produced to control the flexibility of silicone rubber encapsulated electrodes designed to electrically stimulate the auditory nerve in human subjects with severe to profound hearing loss. The rib molding dies, and molds for silicone rubber encapsulation of the electrode, were designed and machined using AutoCad and MasterCam software packages in a PC environment. After molding, the prototype plastic ribs were iteratively modified based on observations of the performance of the rib/silicone composite insert in a clear plastic model of the human scala tympani cavity. The rib-based electrodes were reliably inserted farther into these models, required less insertion force and were positioned closer to the target auditory neural elements than currently available cochlear implant electrodes. With further design improvements the injection-molded rib may also function to accurately support metal stimulating contacts and wire leads during assembly to significantly increase the manufacturing efficiency of these devices. This method to reliably control the mechanical properties of miniature implantable devices with multiple electrical leads may be valuable in other areas of biomedical device design.

Questing and the application for silicon based ternary compound within ultra-thin layer of SIS intermediate region

NASA Astrophysics Data System (ADS)

Chen, Shumin; Gao, Ming; Wan, Yazhou; Du, Huiwei; Li, Yong; Ma, Zhongquan

2016-12-01

A silicon based ternary compound was supposed to be solid synthesized with In, Si and O elements by magnetron sputtering of indium tin oxide target (ITO) onto crystal silicon substrate at 250 °C. To make clear the configuration of the intermediate region, a potential method to obtain the chemical bonding of Si with other existing elements was exploited by X-ray photoelectron spectroscopy (XPS) instrument combined with other assisted techniques. The phase composition and solid structure of the interfacial region between ITO and Si substrate were investigated by X-ray diffraction (XRD) and high resolution cross sectional transmission electron microscope (HR-TEM). A photovoltaic device with structure of Al/Ag/ITO/SiOx/p-Si/Al was assembled by depositing ITO films onto the p-Si substrate by using magnetron sputtering. The new matter has been assumed to be a buffer layer for semiconductor-insulator-semiconductor (SIS) photovoltaic device and plays critical role for the promotion of optoelectronic conversion performance from the view point of device physics.

Nucleation and atomic layer reaction in nickel silicide for defect-engineered Si nanochannels.

PubMed

Tang, Wei; Picraux, S Tom; Huang, Jian Yu; Gusak, Andriy M; Tu, King-Ning; Dayeh, Shadi A

2013-06-12

At the nanoscale, defects can significantly impact phase transformation processes and change materials properties. The material nickel silicide has been the industry standard electrical contact of silicon microelectronics for decades and is a rich platform for scientific innovation at the conjunction of materials and electronics. Its formation in nanoscale silicon devices that employ high levels of strain, intentional, and unintentional twins or grain boundaries can be dramatically different from the commonly conceived bulk processes. Here, using in situ high-resolution transmission electron microscopy (HRTEM), we capture single events during heterogeneous nucleation and atomic layer reaction of nickel silicide at various crystalline boundaries in Si nanochannels for the first time. We show through systematic experiments and analytical modeling that unlike other typical face-centered cubic materials such as copper or silicon the twin defects in NiSi2 have high interfacial energies. We observe that these twin defects dramatically change the behavior of new phase nucleation and can have direct implications for ultrascaled devices that are prone to defects or may utilize them to improve device performance.

Development of a silicone-membrane passive sampler for monitoring cylindrospermopsin and microcystin LR-YR-RR in natural waters

NASA Astrophysics Data System (ADS)

Nyoni, Hlengilizwe; Mamba, Bhekie B.; Msagati, Titus A. M.

2017-08-01

Silicone membrane tubes were functionalised by filling them with synthesised γ-Fe2O3 nanoparticles and used as a passive sampling device for monitoring microcystins and cylindrospermopsin in aquatic environments. This novel device was calibrated for the measurement of microcystin and cylindrospermopsin concentrations in water. The effect of temperature and hydrodynamics on the sampler performance was studied in a flow-through system under controlled conditions. The chemical uptake of microcystins (MCs) and cylindrospermopsin (CYN) into the passive sampler remained linear and integrative throughout the exposure period. The rate of accumulation of most of the MC compounds tested was dependent on temperature and flow velocity. The use of 13C labelled polychlorinated biphenyls as performance reference compounds (PRCs) in silicone membrane/γ-Fe2O3 nanoparticle passive sampler, Chemcatcher and polar organic chemical integrative sampler (POCIS) was evaluated. The majority of PRCs improved the semi quantitative nature of water concentration estimated by the three samplers. The corrected sampling rate values of model biotoxin compounds were used to estimate the time-weighted average concentrations in natural cyanobacterial water blooms of the Hartbeespoort dam. The corrected sampling rates RScorr values varied from 0.1140 to 0.5628 Ld-1 between samplers with silicone membrane having the least RScorr values compared to the Chemcatcher and POCIS. The three passive sampling devises provided a more relevant picture of the biotoxin concentration in the Hartbeespoort dam. The results suggested that the three sampling devices are suitable for use in monitoring microcystins and cylindrospermopsin concentrations in aquatic environments.

Vertex detectors: The state of the art and future prospects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Damerell, C.J.S.

1997-01-01

We review the current status of vertex detectors (tracking microscopes for the recognition of charm and bottom particle decays). The reasons why silicon has become the dominant detector medium are explained. Energy loss mechanisms are reviewed, as well as the physics and technology of semiconductor devices, emphasizing the areas of most relevance for detectors. The main design options (microstrips and pixel devices, both CCD`s and APS`s) are discussed, as well as the issue of radiation damage, which probably implies the need to change to detector media beyond silicon for some vertexing applications. Finally, the evolution of key performance parameters overmore » the past 15 years is reviewed, and an attempt is made to extrapolate to the likely performance of detectors working at the energy frontier ten years from now.« less

The bipolar silicon microstrip detector: A proposal for a novel precision tracking device

NASA Astrophysics Data System (ADS)

Horisberger, R.

1990-03-01

It is proposed to combine the technology of fully depleted silicon microstrip detectors fabricated on n doped high resistivity silicon with the concept of the bipolar transistor. This is done by adding a n ++ doped region inside the normal p + implanted region of the reverse biased p + n diode. Teh resulting structure has amplifying properties and is referred to as bipolar pixel transistor. The simplest readout scheme of a bipolar pixel array by an aluminium strip bus leads to the bipolar microstrip detector. The bipolar pixel structure is expected to give a better signal-to-noise performance for the detection of minimum ionizing charged particle tracks than the normal silicon diode strip detector and therefore should allow in future the fabrication of thinner silicon detectors for precision tracking.

Crystalline silicon photovoltaics via low-temperature TiO 2/Si and PEDOT/Si heterojunctions

NASA Astrophysics Data System (ADS)

Nagamatsu, Ken Alfred

The most important goals in developing solar cell technology are to achieve high power conversion efficiencies and lower costs of manufacturing. Solar cells based on crystalline silicon currently dominate the market because they can achieve high efficiency. However, conventional p-n junction solar cells require high-temperature diffusions of dopants, and conventional heterojunction cells based on amorphous silicon require plasma-enhanced deposition, both of which can add manufacturing costs. This dissertation investigates an alternative approach, which is to form crystalline-silicon-based solar cells using heterojunctions with materials that are easily deposited at low temperatures and without plasma enhancement, such as organic semiconductors and metal oxides. We demonstrate a heterojunction between the organic polymer, poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT), and crystalline silicon, which acts as a hole-selective contact and an alternative to a diffused p-n junction. We also present the use of a heterojunction between titanium dioxide and crystalline silicon as a passivating electron-selective contact. The Si/TiO2 heterojunction is demonstrated for the first time as a back-surface field in a crystalline silicon solar cell, and is incorporated into a PEDOT/Si device. The resulting PEDOT/Si/TiO2 solar cell represents an alternative to conventional silicon solar cells that rely on thermally-diffused junctions or plasma-deposited heterojunctions. Finally, we investigate the merits of using conductive networks of silver nanowires to enhance the photovoltaic performance of PEDOT/Si solar cells. The investigation of these materials and devices contributes to the growing body of work regarding crystalline silicon solar cells made with selective contacts.

Microbiopsy/precision cutting devices

DOEpatents

Krulevitch, Peter A.; Lee, Abraham P.; Northrup, M. Allen; Benett, William J.

1999-01-01

Devices for performing tissue biopsy on a small scale (microbiopsy). By reducing the size of the biopsy tool and removing only a small amount of tissue or other material in a minimally invasive manner, the risks, costs, injury and patient discomfort associated with traditional biopsy procedures can be reduced. By using micromachining and precision machining capabilities, it is possible to fabricate small biopsy/cutting devices from silicon. These devices can be used in one of four ways 1) intravascularly, 2) extravascularly, 3) by vessel puncture, and 4) externally. Additionally, the devices may be used in precision surgical cutting.

Whatever happened to silicon carbide. [semiconductor devices

NASA Technical Reports Server (NTRS)

Campbell, R. B.

1981-01-01

The progress made in silicon carbide semiconductor devices in the 1955 to 1975 time frame is examined and reasons are given for the present lack of interest in the material. Its physical and chemical properties and methods of preparation are discussed. Fabrication techniques and the characteristics of silicon carbide devices are reviewed. It is concluded that a combination of economic factors and the lack of progress in fabrication techniques leaves no viable market for SiC devices in the near future.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

An all-silicon passive optical diode.

PubMed

Fan, Li; Wang, Jian; Varghese, Leo T; Shen, Hao; Niu, Ben; Xuan, Yi; Weiner, Andrew M; Qi, Minghao

2012-01-27

A passive optical diode effect would be useful for on-chip optical information processing but has been difficult to achieve. Using a method based on optical nonlinearity, we demonstrate a forward-backward transmission ratio of up to 28 decibels within telecommunication wavelengths. Our device, which uses two silicon rings 5 micrometers in radius, is passive yet maintains optical nonreciprocity for a broad range of input power levels, and it performs equally well even if the backward input power is higher than the forward input. The silicon optical diode is ultracompact and is compatible with current complementary metal-oxide semiconductor processing.

Properties of piezoresistive silicon nano-scale cantilevers with applications to BioNEMS

NASA Astrophysics Data System (ADS)

Arlett, Jessica Lynn

Over the last decade a great deal of interest has been raised in applications of Microelectromechanical Sensors [MEMS] for the detection of biological molecules and to the study of their forces of interaction. Experiments in these areas have included Force Spectroscopy (Chemical Force Microscopy), MEMS patch clamp technology, and surface stress sensors. All of these technologies suffer from limitations on temporal response and involve devices with active surface areas that are large compared to molecular dimensions. Biofunctionalized nanoelectromechanical systems (BioNEMS) have the potential to overcome both of these hurdles, offering important new prospects for single-molecule force assays that are amenable to large scale integration. Results are presented here on the characterization of piezoresistive silicon cantilevers with applications to BioNEMS devices. The cantilevers were characterized by studying their response in gaseous ambients under a number of drive conditions including magnetic, piezoelectric, and thermal actuation, in addition to passive detection of the thermomechanical response. The measurements were performed at liquid helium temperature, at room temperature, and over a range of pressures (atmospheric pressure to 30mT). Theoretical studies have been performed on the response of these devices to Brownian fluctuations in fluid, on the feasibility of these devices as surface stress sensors, and on improvements in device design as compared to piezoresistive surface stress sensors currently discussed in the literature. The devices were encapsulated in microfluidics and measurements were performed to show the noise floor in fluid. The piezoresistive response of the device in fluid was shown through the use of pulsatory fluidic drive. As a proof of concept, biodetection experiments are presented for biotin labeled beads. The biofunctionalization for the latter experiment was performed entirely within the microfluidics. A discussion of how these experiments can be extended to other cells, spores, and molecules is presented.

Comparison of Six Different Silicones In Vitro for Application as Glaucoma Drainage Device

PubMed Central

Windhövel, Claudia; Harder, Lisa; Bach, Jan-Peter; Teske, Michael; Grabow, Niels; Eickner, Thomas; Chichkov, Boris; Nolte, Ingo

2018-01-01

Silicones are widely used in medical applications. In ophthalmology, glaucoma drainage devices are utilized if conservative therapies are not applicable or have failed. Long-term success of these devices is limited by failure to control intraocular pressure due to fibrous encapsulation. Therefore, different medical approved silicones were tested in vitro for cell adhesion, cell proliferation and viability of human Sclera (hSF) and human Tenon fibroblasts (hTF). The silicones were analysed also depending on the sample preparation according to the manufacturer’s instructions. The surface quality was characterized with environmental scanning electron microscope (ESEM) and water contact angle measurements. All silicones showed homogeneous smooth and hydrophobic surfaces. Cell adhesion was significantly reduced on all silicones compared to the negative control. Proliferation index and cell viability were not influenced much. For development of a new glaucoma drainage device, the silicones Silbione LSR 4330 and Silbione LSR 4350, in this study, with low cell counts for hTF and low proliferation indices for hSF, and silicone Silastic MDX4-4210, with low cell counts for hSF and low proliferation indices for hTF, have shown the best results in vitro. Due to the high cell adhesion shown on Silicone LSR 40, 40,026, this material is unsuitable. PMID:29495462

Deformable devices with integrated functional nanomaterials for wearable electronics.

PubMed

Kim, Jaemin; Lee, Jongsu; Son, Donghee; Choi, Moon Kee; Kim, Dae-Hyeong

2016-01-01

As the market and related industry for wearable electronics dramatically expands, there are continuous and strong demands for flexible and stretchable devices to be seamlessly integrated with soft and curvilinear human skin or clothes. However, the mechanical mismatch between the rigid conventional electronics and the soft human body causes many problems. Therefore, various prospective nanomaterials that possess a much lower flexural rigidity than their bulk counterparts have rapidly established themselves as promising electronic materials replacing rigid silicon and/or compound semiconductors in next-generation wearable devices. Many hybrid structures of multiple nanomaterials have been also developed to pursue both high performance and multifunctionality. Here, we provide an overview of state-of-the-art wearable devices based on one- or two-dimensional nanomaterials (e.g., carbon nanotubes, graphene, single-crystal silicon and oxide nanomembranes, organic nanomaterials and their hybrids) in combination with zero-dimensional functional nanomaterials (e.g., metal/oxide nanoparticles and quantum dots). Starting from an introduction of materials strategies, we describe device designs and the roles of individual ones in integrated systems. Detailed application examples of wearable sensors/actuators, memories, energy devices, and displays are also presented.

Deformable devices with integrated functional nanomaterials for wearable electronics

NASA Astrophysics Data System (ADS)

Kim, Jaemin; Lee, Jongsu; Son, Donghee; Choi, Moon Kee; Kim, Dae-Hyeong

2016-03-01

As the market and related industry for wearable electronics dramatically expands, there are continuous and strong demands for flexible and stretchable devices to be seamlessly integrated with soft and curvilinear human skin or clothes. However, the mechanical mismatch between the rigid conventional electronics and the soft human body causes many problems. Therefore, various prospective nanomaterials that possess a much lower flexural rigidity than their bulk counterparts have rapidly established themselves as promising electronic materials replacing rigid silicon and/or compound semiconductors in next-generation wearable devices. Many hybrid structures of multiple nanomaterials have been also developed to pursue both high performance and multifunctionality. Here, we provide an overview of state-of-the-art wearable devices based on one- or two-dimensional nanomaterials (e.g., carbon nanotubes, graphene, single-crystal silicon and oxide nanomembranes, organic nanomaterials and their hybrids) in combination with zero-dimensional functional nanomaterials (e.g., metal/oxide nanoparticles and quantum dots). Starting from an introduction of materials strategies, we describe device designs and the roles of individual ones in integrated systems. Detailed application examples of wearable sensors/actuators, memories, energy devices, and displays are also presented.

Silicon superlattices: Theory and application to semiconductor devices

NASA Technical Reports Server (NTRS)

Moriarty, J. A.

1981-01-01

Silicon superlattices and their applicability to improved semiconductor devices were studied. The device application potential of the atomic like dimension of III-V semiconductor superlattices fabricated in the form of ultrathin periodically layered heterostructures was examined. Whether this leads to quantum size effects and creates the possibility to alter familiar transport and optical properties over broad physical ranges was studied. Applications to improved semiconductor lasers and electrondevices were achieved. Possible application of silicon sperlattices to faster high speed computing devices was examined. It was found that the silicon lattices show features of smaller fundamental energyband gaps and reduced effective masses. The effects correlate strongly with both the chemical and geometrical nature of the superlattice.

Forecasting of the performance of MOS device for space applications

NASA Technical Reports Server (NTRS)

Fang, P. H.

1971-01-01

Analysis of radiation damage of MOSFET data from Explorer 34 (IMP-F), and radiation damage characteristics of MOSFET with boron diffused between a silicon semiconductor and silicon oxide are considered. The first subject is an interpretation of the discrepancy between the space data and the laboratory data. The second subject is an attempt to analyze the radiation damage characteristic of MOSFET when there is modification of electrical properties in the gate oxide region.

Design and performance study of a DC-DC flyback converter based on wide bandgap power devices for photovoltaic applications

NASA Astrophysics Data System (ADS)

Alharbi, Salah S.; Alharbi, Saleh S.; Al-bayati, Ali M. S.; Matin, Mohammad

2017-08-01

This paper presents a high-performance dc-dc flyback converter design based on wide bandgap (WBG) semiconductor devices for photovoltaic (PV) applications. Two different power devices, a gallium nitride (GaN)-transistor and a silicon (Si)-MOSFET, are implemented individually in the flyback converter to examine their impact on converter performance. The total power loss of the converter with different power devices is analyzed for various switching frequencies. Converter efficiency is evaluated at different switching frequencies, input voltages, and output power levels. The results reveal that the converter with the GaN-transistor has lower total power loss and better efficiency compared to the converter with the conventional Si-MOSFET.

Thermal and bias cycling stabilizes planar silicon devices

NASA Technical Reports Server (NTRS)

Harris, R. E.; Meinhard, J. E.

1967-01-01

Terminal burn-in or baking step time in the processing of planar silicon devices is extended to reduce their inversion tendencies. The collector-base junction of the device is also cyclically biased during the burn-in.

Through-silicon via-induced strain distribution in silicon interposer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vianne, B., E-mail: benjamin.vianne@st.com; STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles; Richard, M.-I.

2015-04-06

Strain in silicon induced by Through-Silicon Via (TSV) integration is of particular interest in the frame of the integration of active devices in silicon interposer. Nano-focused X-ray beam diffraction experiments were conducted using synchrotron radiation to investigate the thermally induced strain field in silicon around copper filled TSVs. Measurements were performed on thinned samples at room temperature and during in situ annealing at 400 °C. In order to correlate the 2D strain maps with finite elements analysis, an analytical model was developed, which takes into account beam absorption in the sample for a given diffraction geometry. The strain field along themore » [335] direction is found to be in the 10{sup −5} range at room temperature and around 10{sup −4} at 400 °C. Simulations support the expected plastification in some regions of the TSV during the annealing step.« less

A novel simple external fixation for securing silicone stent in patients with upper tracheal stenosis

PubMed Central

Lin, Xiaoxiao; Ye, Min; Li, Yuping

2018-01-01

Upper tracheal stenosis is considered as a potentially life-threatening condition. Silicone stenting is an attractive treatment option for patients with upper tracheal stenosis. However, its use has been compromised by a major complication, stent migration. In the report, we introduced a novel external fixation of silicone stent which only needed one puncture site and involved a silicon chip as an anchoring device. All equipment and materials including the silicon chip were available in routine bronchoscopy suite. The method had been successfully performed in three patients with upper tracheal stenosis at our institution. And the patients were monitored for over 20 months after the intervention, and no spontaneous stent migration occurred. Therefore, we believe this is a simple and reliable approach for improving the outcome of silicone stenting in patients with upper tracheal stenosis and should be introduced in clinical practice.

Glass-embedded two-dimensional silicon photonic crystal devices with a broad bandwidth waveguide and a high quality nanocavity.

PubMed

Jeon, Seung-Woo; Han, Jin-Kyu; Song, Bong-Shik; Noda, Susumu

2010-08-30

To enhance the mechanical stability of a two-dimensional photonic crystal slab structure and maintain its excellent performance, we designed a glass-embedded silicon photonic crystal device consisting of a broad bandwidth waveguide and a nanocavity with a high quality (Q) factor, and then fabricated the structure using spin-on glass (SOG). Furthermore, we showed that the refractive index of the SOG could be tuned from 1.37 to 1.57 by varying the curing temperature of the SOG. Finally, we demonstrated a glass-embedded heterostructured cavity with an ultrahigh Q factor of 160,000 by adjusting the refractive index of the SOG.

All-optical switching in silicon-on-insulator photonic wire nano-cavities.

PubMed

Belotti, Michele; Galli, Matteo; Gerace, Dario; Andreani, Lucio Claudio; Guizzetti, Giorgio; Md Zain, Ahmad R; Johnson, Nigel P; Sorel, Marc; De La Rue, Richard M

2010-01-18

We report on experimental demonstration of all-optical switching in a silicon-on-insulator photonic wire nanocavity operating at telecom wavelengths. The switching is performed with a control pulse energy as low as approximately 0.1 pJ on a cavity device that presents very high signal transmission, an ultra-high quality-factor, almost diffraction-limited modal volume and a footprint of only 5 microm(2). High-speed modulation of the cavity mode is achieved by means of optical injection of free carriers using a nanosecond pulsed laser. Experimental results are interpreted by means of finite-difference time-domain simulations. The possibility of using this device as a logic gate is also demonstrated.

Colloidal Engineering for Infrared-Bandgap Solution-Processed Quantum Dot Solar Cells

NASA Astrophysics Data System (ADS)

Kiani, Amirreza

Ever-increasing global energy demand and a diminishing fossil fuel supply have prompted the development of technologies for sustainable energy production. Solar photovoltaic (PV) devices have huge potential for energy harvesting and production since the sun delivers more energy to the earth in one hour than the global population consumes in one year. The solar cell industry is now dominated by silicon PV devices. The cost of silicon modules has decreased substantially over the past two decades and the number of installed silicon PV devices has increased dramatically. There remains a need for emerging solar technologies that can harvest the untapped portion of the solar spectrum and can be integrated on flexible and curved surfaces. This thesis focuses on colloidal quantum dot (CQD) PV devices. CQDs are nanoparticles fabricated using a low-temperature and cost-effective solution technique. These materials suffer from a high density of surface traps derived from the large surface-to-volume ratio of CQD nanoparticles, combined with limited carrier mobility. These result in a short carrier diffusion length, a main limiting factor in CQD solar cell performance. This thesis seeks to address the poor diffusion length in lead sulfide (PbS) CQD films and pave the way for new applications for CQD PV devices in infrared solar harvesting and waste heat recovery. A two-fold reduction in surface trap density is demonstrated using molecular halide treatment. Iodine molecules introduced prior to the film formation replace the otherwise unpassivated surface sulfur atoms. This results in a 35% increase in the diffusion length and enables charge extraction over thicker active layer leading to the world's most efficient CQD PV devices from June 2015 to July 2016 with the certified power conversion efficiency of 9.9%. This represents a 30% increase over the best-certified PCE (7.5%) prior to this thesis. The colloidal engineering highlighted herein enables infrared (IR) solar harvesting for the first time. Addition of short bromothiol ligands during the synthesis significantly reduces the agglomeration of 1 eV bandgap CQDs and maintains efficient charge extraction into the selective electrodes. The devices can augment the performance of the best silicon cells by 7 power points where 0.8 additive power points are demonstrated experimentally. A tailored solution exchanged process developed for 1 eV bandgap CQDs results in air-stable IR PV devices with improved manufacturability. The process utilizes a tailored combination of lead iodide (PbI2) and ammonium acetate for the solution exchange and hexylamine + MEK as the final solvent to yield solar thick films with the filtered (1100 nm and beyond) performance of 0.4%. This thesis pushes the limit of CQD device applications to waste heat recovery. I demonstrate successful harvesting of low energy photons emitted from a hot object by designing and developing the first solution-processed thermophotovoltaic devices. These devices are comprised of 0.7 eV bandgap CQDs that successfully harvest photons emitted from an 800°C heat source.

Silicon Carbide Solar Cells Investigated

NASA Technical Reports Server (NTRS)

Bailey, Sheila G.; Raffaelle, Ryne P.

2001-01-01

The semiconductor silicon carbide (SiC) has long been known for its outstanding resistance to harsh environments (e.g., thermal stability, radiation resistance, and dielectric strength). However, the ability to produce device-quality material is severely limited by the inherent crystalline defects associated with this material and their associated electronic effects. Much progress has been made recently in the understanding and control of these defects and in the improved processing of this material. Because of this work, it may be possible to produce SiC-based solar cells for environments with high temperatures, light intensities, and radiation, such as those experienced by solar probes. Electronics and sensors based on SiC can operate in hostile environments where conventional silicon-based electronics (limited to 350 C) cannot function. Development of this material will enable large performance enhancements and size reductions for a wide variety of systems--such as high-frequency devices, high-power devices, microwave switching devices, and high-temperature electronics. These applications would supply more energy-efficient public electric power distribution and electric vehicles, more powerful microwave electronics for radar and communications, and better sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. The 6H-SiC polytype is a promising wide-bandgap (Eg = 3.0 eV) semiconductor for photovoltaic applications in harsh solar environments that involve high-temperature and high-radiation conditions. The advantages of this material for this application lie in its extremely large breakdown field strength, high thermal conductivity, good electron saturation drift velocity, and stable electrical performance at temperatures as high as 600 C. This behavior makes it an attractive photovoltaic solar cell material for devices that can operate within three solar radii of the Sun.

In situ arsenic-doped polycrystalline silicon as a low thermal budget emitter contact for Si/Si1 - xGex heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

King, C. A.; Johnson, R. W.; Pinto, M. R.; Luftman, H. S.; Munanka, J.

1996-01-01

A low thermal budget emitter contact with low specific contact resistivity (ρc) with the absence of transient enhanced diffusion (TED) effects is essential to fabricate integratable high performance Si/SiGe heterojunction bipolar transistors (HBTs). We report the use of in situ As-doped polycrystalline silicon (polysilicon) from a low base pressure rapid thermal episystem for this purpose and find that it meets all the requirements. We used secondary ion mass spectrometry to find that 18 nm, heavily B-doped layers remain intact after implantation into the surface polysilicon and annealing at 800 °C for 40 s. Similar samples without the surface polylayer displayed extreme broadening of B profile. Kelvin crossbridge resistors together with 2D device simulations revealed that ρc is an extremely low value of 1.2×10-8 Ω cm2 in as-deposited material. Fabrication of simple 30×30 μm2 mesa isolated HBT devices showed IC to be more than two decades higher in devices with only an in situ As-doped polyemitter compared with devices that incorporated a surface implant into the single crystal portion of the emitter before polysilicon deposition. These results demonstrate that this doped polycrystalline silicon material is an excellent choice for emitter contacts to HBT devices.

Polycrystalline silicon study: Low-cost silicon refining technology prospects and semiconductor-grade polycrystalline silicon availability through 1988

NASA Technical Reports Server (NTRS)

Costogue, E. N.; Ferber, R.; Lutwack, R.; Lorenz, J. H.; Pellin, R.

1984-01-01

Photovoltaic arrays that convert solar energy into electrical energy can become a cost effective bulk energy generation alternative, provided that an adequate supply of low cost materials is available. One of the key requirements for economic photovoltaic cells is reasonably priced silicon. At present, the photovoltaic industry is dependent upon polycrystalline silicon refined by the Siemens process primarily for integrated circuits, power devices, and discrete semiconductor devices. This dependency is expected to continue until the DOE sponsored low cost silicon refining technology developments have matured to the point where they are in commercial use. The photovoltaic industry can then develop its own source of supply. Silicon material availability and market pricing projections through 1988 are updated based on data collected early in 1984. The silicon refining industry plans to meet the increasing demands of the semiconductor device and photovoltaic product industries are overviewed. In addition, the DOE sponsored technology research for producing low cost polycrystalline silicon, probabilistic cost analysis for the two most promising production processes for achieving the DOE cost goals, and the impacts of the DOE photovoltaics program silicon refining research upon the commercial polycrystalline silicon refining industry are addressed.

Amorphous silicon photovoltaic devices

DOEpatents

Carlson, David E.; Lin, Guang H.; Ganguly, Gautam

2004-08-31

This invention is a photovoltaic device comprising an intrinsic or i-layer of amorphous silicon and where the photovoltaic device is more efficient at converting light energy to electric energy at high operating temperatures than at low operating temperatures. The photovoltaic devices of this invention are suitable for use in high temperature operating environments.

Opening the band gap of graphene through silicon doping for the improved performance of graphene/GaAs heterojunction solar cells.

PubMed

Zhang, S J; Lin, S S; Li, X Q; Liu, X Y; Wu, H A; Xu, W L; Wang, P; Wu, Z Q; Zhong, H K; Xu, Z J

2016-01-07

Graphene has attracted increasing interest due to its remarkable properties. However, the zero band gap of monolayered graphene limits it's further electronic and optoelectronic applications. Herein, we have synthesized monolayered silicon-doped graphene (SiG) with large surface area using a chemical vapor deposition method. Raman and X-ray photoelectron spectroscopy measurements demonstrate that the silicon atoms are doped into graphene lattice at a doping level of 2.7-4.5 at%. Electrical measurements based on a field effect transistor indicate that the band gap of graphene has been opened via silicon doping without a clear degradation in carrier mobility, and the work function of SiG, deduced from ultraviolet photoelectron spectroscopy, was 0.13-0.25 eV larger than that of graphene. Moreover, when compared with the graphene/GaAs heterostructure, SiG/GaAs exhibits an enhanced performance. The performance of 3.4% silicon doped SiG/GaAs solar cell has been improved by 33.7% on average, which was attributed to the increased barrier height and improved interface quality. Our results suggest that silicon doping can effectively engineer the band gap of monolayered graphene and SiG has great potential in optoelectronic device applications.

Silicon Modulators, Switches and Sub-systems for Optical Interconnect

NASA Astrophysics Data System (ADS)

Li, Qi

Silicon photonics is emerging as a promising platform for manufacturing and integrating photonic devices for light generation, modulation, switching and detection. The compatibility with existing CMOS microelectronic foundries and high index contrast in silicon could enable low cost and high performance photonic systems, which find many applications in optical communication, data center networking and photonic network-on-chip. This thesis first develops and demonstrates several experimental work on high speed silicon modulators and switches with record performance and novel functionality. A 8x40 Gb/s transmitter based on silicon microrings is first presented. Then an end-to-end link using microrings for Binary Phase Shift Keying (BPSK) modulation and demodulation is shown, and its performance with conventional BPSK modulation/ demodulation techniques is compared. Next, a silicon traveling-wave Mach- Zehnder modulator is demonstrated at data rate up to 56 Gb/s for OOK modulation and 48 Gb/s for BPSK modulation, showing its capability at high speed communication systems. Then a single silicon microring is shown with 2x2 full crossbar switching functionality, enabling optical interconnects with ultra small footprint. Then several other experiments in the silicon platform are presented, including a fully integrated in-band Optical Signal to Noise Ratio (OSNR) monitor, characterization of optical power upper bound in a silicon microring modulator, and wavelength conversion in a dispersion-engineered waveguide. The last part of this thesis is on network-level application of photonics, specically a broadcast-and-select network based on star coupler is introduced, and its scalability performance is studied. Finally a novel switch architecture for data center networks is discussed, and its benefits as a disaggregated network are presented.

LABEL-FREE VIRUS CAPTURE AND RELEASE BY A MICROFLUIDIC DEVICE INTEGRATED WITH POROUS SILICON NANOWIRE FOREST

PubMed Central

Xia, Yiqiu; Tang, Yi; Yu, Xu; Wan, Yuan; Chen, Yizhu; Lu, Huaguang; Zheng, Si-Yang

2016-01-01

Viral diseases are perpetual threats to human and animal health. Detection and characterization of viral pathogens require accurate, sensitive and rapid diagnostic assays. For field and clinical samples, the sample preparation procedures limit the ultimate performance and utility of the overall virus diagnostic protocols. Here, we presented the development of a microfluidic device embedded with porous silicon nanowire (pSiNW) forest for label-free size-based point-of-care virus capture in a continuous curved flow design. The pSiNW forests with specific inter-wire spacing were synthesized in situ on both bottom and sidewalls of the microchannels in a batch process. With the enhancement effect of Dean flow, we demonstrated ~50% H5N2 avian influenza viruses were physically trapped without device clogging. A unique feature of the device is that captured viruses can be released by inducing self-degradation of the pSiNWs in physiological aqueous environment. About 60% of captured viruses can be released within 24 hours for virus culture, subsequent molecular diagnosis and other virus characterization and analyses. This device performs viable, unbiased and label-free virus isolation and release. It has great potentials for virus discovery, virus isolation and culture, functional studies of virus pathogenicity, transmission, drug screening, and vaccine development. PMID:27918640

Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Hsieh, I.-Wei

In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic devices are quite different from those of electronic devices. Minimizing propagation losses by reducing sidewall roughness to nanometer scale over a device length of several millimeters or even centimeters has prompted researchers in academia and industry to refine the fabrication process. Chapter 3 of this thesis summarizes our efforts in fabricating silicon photonic devices using standard CMOS technology. Chapter 4 describes the characterization of nonlinear effects, including self-phase modulation (SPM), cross-phase modulation (XPM), and supercontinuum generation in silicon-wire waveguides. Silicon-wire waveguides are strip waveguides with submicron transverse dimensions, which allow strong light confinement inside the silicon core. This strong optical confinement, in addition to the large third-order nonlinear optical susceptibility of crystalline silicon, leads to a net nonlinearity which is several orders of magnitude higher than the nonlinearity of silica fiber. Significant nonlinear effects can be observed and characterized over a device length of only several millimeters in silicon wires with very small input power. These effects provide opportunities for engineers to design active silicon photonic devices which are compact and energy-efficient. Chapter 5 presents a realization of an integrated SOI optical isolator, which is a critical yet often overlooked component in photonic integrated circuits. This study shows the feasibility to make a hybrid garnet/SOI active device with very promising results. Finally, Chapter 6 summarizes our demonstration of transmitting terabit-scale data streams in silicon-wire waveguides, which is an important first-step towards enabling intra-chip interconnection networks with ultra-high bandwidths. Although the scope of this thesis is limited to providing only fractional views of the whole silicon photonics area, it provides enough references for interested readers to conduct further literature research in other aspects of silicon photonics. It is the author's hope that the thesis would convey to its readers the significance and potential of this exciting emerging technology.

A macrochip interconnection network enabled by silicon nanophotonic devices.

PubMed

Zheng, Xuezhe; Cunningham, John E; Koka, Pranay; Schwetman, Herb; Lexau, Jon; Ho, Ron; Shubin, Ivan; Krishnamoorthy, Ashok V; Yao, Jin; Mekis, Attila; Pinguet, Thierry

2010-03-01

We present an advanced wavelength-division multiplexing point-to-point network enabled by silicon nanophotonic devices. This network offers strictly non-blocking all-to-all connectivity while maximizing bisection bandwidth, making it ideal for multi-core and multi-processor interconnections. We introduce one of the key components, the nanophotonic grating coupler, and discuss, for the first time, how this device can be useful for practical implementations of the wavelength-division multiplexing network using optical proximity communications. Finite difference time-domain simulation of the nanophotonic grating coupler device indicates that it can be made compact (20 microm x 50 microm), low loss (3.8 dB), and broadband (100 nm). These couplers require subwavelength material modulation at the nanoscale to achieve the desired functionality. We show that optical proximity communication provides unmatched optical I/O bandwidth density to electrical chips, which enables the application of wavelength-division multiplexing point-to-point network in macrochip with unprecedented bandwidth-density. The envisioned physical implementation is discussed. The benefits of such an interconnect network include a 5-6x improvement in latency when compared to a purely electronic implementation. Performance analysis shows that the wavelength-division multiplexing point-to-point network offers better overall performance over other optical network architectures.

Low temperature surface passivation of crystalline silicon and its application to interdigitated back contact silicon heterojunction (ibc-shj) solar cell

NASA Astrophysics Data System (ADS)

Shu, Zhan

With the absence of shading loss together with improved quality of surface passivation introduced by low temperature processed amorphous silicon crystalline silicon (a-Si:H/c-Si) heterojunction, the interdigitated back contact silicon heterojunction (IBC-SHJ) solar cell exhibits a potential for higher conversion efficiency and lower cost than a traditional front contact diffused junction solar cell. In such solar cells, the front surface passivation is of great importance to achieve both high open-circuit voltage (Voc) and short-circuit current (Jsc). Therefore, the motivation of this work is to develop a low temperature processed structure for the front surface passivation of IBC-SHJ solar cells, which must have an excellent and stable passivation quality as well as a good anti-reflection property. Four different thin film materials/structures were studied and evaluated for this purpose, namely: amorphous silicon nitride (a-SiNx:H), thick amorphous silicon film (a-Si:H), amorphous silicon/silicon nitride/silicon carbide (a-Si:H/a-SiN x:H/a-SiC:H) stack structure with an ultra-thin a-Si:H layer, and zinc sulfide (ZnS). It was demonstrated that the a-Si:H/a-SiNx:H/a-SiC:H stack surpasses other candidates due to both of its excellent surface passivation quality (SRV<5 cm/s) and lower absorption losses. The low recombination rate at the stack structure passivated c-Si surface is found to be resulted from (i) field effect passivation due to the positive fixed charge (Q fix~1x1011 cm-2 with 5 nm a-Si:H layer) in a-SiNx:H as measured from capacitance-voltage technique, and (ii) reduced defect state density (mid-gap Dit~4x1010 cm-2eV-1) at a-Si:H/c-Si interface provided by a 5 nm thick a-Si:H layer, as characterized by conductance-frequency measurements. Paralleled with the experimental studies, a computer program was developed in this work based on the extended Shockley-Read-Hall (SRH) model of surface recombination. With the help of this program, the experimental injection level dependent SRV curves of the stack passivated c-Si samples were successfully reproduced and the carrier capture cross sections of interface defect states were extracted. Additionally, anti-reflection properties of the stack structure were optimized and optical losses were analyzed. The Voc over 700 mV and Jsc over 38 mA/cm2 were achieved in IBC-SHJ solar cells using the stack structure for front surface passivation. Direct comparison shows that such low temperature deposited stack structure developed in this work achieves comparable device performance to the high temperature processed front surface passivation structure used in other high efficiency IBC solar cells. However, the lower fill factor (FF) of IBC-SHJ solar cell as compared with traditional front a-Si:H/c-Si heterojunction cell (HIT cell) greatly limits the overall performance of these devices. Two-dimensional (2D) simulations were used to comparatively model the HIT and IBC-SHJ solar cells to understand the underlying device physics which controls cell performance. The effects of a wide range of device parameters were investigated in the simulation, and pathways to improve the FF of IBC-SHJ solar cell were suggested.

Epitaxial growth of silicon for layer transfer

DOEpatents

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Evaluation of ion-implanted-silicon detectors for use in intraoperative positron-sensitive probes.

PubMed

Raylman, R R; Wahl, R L

1996-11-01

The continuing development of probes for use with beta (positron and electron) emitting radionuclides may result in more complete excision of tracer-avid tumors. Perhaps one of the most promising radiopharmaceuticals for this task is 18F-labeled-Fluoro-2-Deoxy-D-Glucose (FDG). This positron-emitting agent has been demonstrated to be avidly and rapidly absorbed by many human cancers. We have investigated the use of ion-implanted-silicon detectors in intraoperative positron-sensitive surgical probes for use with FDG. These detectors possess very high positron detection efficiency, while the efficiency for 511 keV photon detection is low. The spatial resolution, as well as positron and annihilation photon detection sensitivity, of an ion-implanted-silicon detector used with 18F was measured at several energy thresholds. In addition, the ability of the device to detect the presence of relatively small amounts of FDG during surgery was evaluated by simulating a surgical field in which some tumor was left intact following lesion excision. The performance of the ion-implanted-silicon detector was compared to the operating characteristics of a positron-sensitive surgical probe which utilizes plastic scintillator. In all areas of performance the ion-implanted-silicon detector proved superior to the plastic scintillator-based probe. At an energy threshold of 14 keV positron sensitivity measured for the ion-implanted-silicon detector was 101.3 cps/kBq, photon sensitivity was 7.4 cps/kBq. In addition, spatial resolution was found to be relatively unaffected by the presence of distant sources of annihilation photon flux. Finally, the detector was demonstrated to be able to localize small amounts of FDG in a simulated tumor bed; indicating that this device has promise as a probe to aid in FDG-guided surgery.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

All-silicon tandem solar cells: Practical limits for energy conversion and possible routes for improvement

NASA Astrophysics Data System (ADS)

Jia, Xuguang; Puthen-Veettil, Binesh; Xia, Hongze; Yang, Terry Chien-Jen; Lin, Ziyun; Zhang, Tian; Wu, Lingfeng; Nomoto, Keita; Conibeer, Gavin; Perez-Wurfl, Ivan

2016-06-01

Silicon nanocrystals (Si NCs) embedded in a dielectric matrix is regarded as one of the most promising materials for the third generation photovoltaics, owing to their tunable bandgap that allows fabrication of optimized tandem devices. Previous work has demonstrated fabrication of Si NCs based tandem solar cells by sputter-annealing of thin multi-layers of silicon rich oxide and SiO2. However, these device efficiencies were much lower than expected given that their theoretical values are much higher. Thus, it is necessary to understand the practical conversion efficiency limits for these devices. In this article, practical efficiency limits of Si NC based double junction tandem cells determined by fundamental material properties such as minority carrier, mobility, and lifetime are investigated. The practical conversion efficiency limits for these devices are significantly different from the reported efficiency limits which use Shockley-Queisser assumptions. Results show that the practical efficiency limit of a double junction cell (1.6 eV Si NC top cell and a 25% efficient c-Si PERL cell as the bottom cell) is 32%. Based on these results suggestions for improvement to the performance of Si nanocrystal based tandem solar cells in terms of the different parameters that were simulated are presented.

Technological processes of grating light valve as diffractive spatial light modulator in laser phototypesetting system

NASA Astrophysics Data System (ADS)

Zhang, Wei; Geng, Yu; Hou, Changlun; Yang, Guoguang; Bai, Jian

2008-11-01

Grating Light Valve (GLV) is a kind of optics device based on Micro-Opto-Electro-Mechanical System (MOEMS) technology, utilizing diffraction principle to switch, attenuate and modulate light. In this paper, traditional GLV device's structure and its working principle are illuminated, and a kind of modified GLV structure is presented, with details introduction of the fabrication technology. The GLV structure includes single crystal silicon substrate, silicon dioxide isolating layer, aluminum layer of fixed ribbons and silicon nitride of movable ribbons. In the fabrication, lots of techniques are adopted, such as low-pressure chemical vapor deposition (LPCVD), photolithography, etching and evaporation. During the fabrication processes, Photolithography is a fundamental and fatal technology, which determines etching result and GLV quality. Some methods are proposed through repeated experiments, to improve etching result greatly and guide the practical application. This kind of GLV device can be made both small and inexpensively, and has been tested to show proper range of actuation under DC bias, with good performance. The GLV device also has merits such as low cost, simple technology, high fill ratio and low driving voltage. It can properly be well used and match the demands of high light power needed in laser phototypesetting system, as a high-speed, high-resolution light modulator.

Porous silicon structures with high surface area/specific pore size

DOEpatents

Northrup, M.A.; Yu, C.M.; Raley, N.F.

1999-03-16

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gases in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters. 9 figs.

Porous silicon structures with high surface area/specific pore size

DOEpatents

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Demonstration of free space coherent optical communication using integrated silicon photonic orbital angular momentum devices.

PubMed

Su, Tiehui; Scott, Ryan P; Djordjevic, Stevan S; Fontaine, Nicolas K; Geisler, David J; Cai, Xinran; Yoo, S J B

2012-04-23

We propose and demonstrate silicon photonic integrated circuits (PICs) for free-space spatial-division-multiplexing (SDM) optical transmission with multiplexed orbital angular momentum (OAM) states over a topological charge range of -2 to +2. The silicon PIC fabricated using a CMOS-compatible process exploits tunable-phase arrayed waveguides with vertical grating couplers to achieve space division multiplexing and demultiplexing. The experimental results utilizing two silicon PICs achieve SDM mux/demux bit-error-rate performance for 1‑b/s/Hz, 10-Gb/s binary phase shifted keying (BPSK) data and 2-b/s/Hz, 20-Gb/s quadrature phase shifted keying (QPSK) data for individual and two simultaneous OAM states. © 2012 Optical Society of America

Development of high temperature, high radiation resistant silicon semiconductors

NASA Technical Reports Server (NTRS)

Whorl, C. A.; Evans, A. W.

1972-01-01

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents

NASA Astrophysics Data System (ADS)

Narimani, K.; Glass, S.; Bernardy, P.; von den Driesch, N.; Zhao, Q. T.; Mantl, S.

2018-05-01

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10-7 A/μm at Vds = Von = Vgs - Voff = -0.5 V for an Ioff = 1 nA/μm and an average SS of 55 mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Id beats the MOSFET performance at low currents.

Memory device using movement of protons

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Fleetwood, D.M.; Devine, R.A.B.

1998-11-03

An electrically written memory element is disclosed utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element. 19 figs.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

1998-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

2000-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

Mid-infrared integrated photonics on silicon: a perspective

NASA Astrophysics Data System (ADS)

Lin, Hongtao; Luo, Zhengqian; Gu, Tian; Kimerling, Lionel C.; Wada, Kazumi; Agarwal, Anu; Hu, Juejun

2017-12-01

The emergence of silicon photonics over the past two decades has established silicon as a preferred substrate platform for photonic integration. While most silicon-based photonic components have so far been realized in the near-infrared (near-IR) telecommunication bands, the mid-infrared (mid-IR, 2-20-μm wavelength) band presents a significant growth opportunity for integrated photonics. In this review, we offer our perspective on the burgeoning field of mid-IR integrated photonics on silicon. A comprehensive survey on the state-of-the-art of key photonic devices such as waveguides, light sources, modulators, and detectors is presented. Furthermore, on-chip spectroscopic chemical sensing is quantitatively analyzed as an example of mid-IR photonic system integration based on these basic building blocks, and the constituent component choices are discussed and contrasted in the context of system performance and integration technologies.

Fundamental device design considerations in the development of disruptive nanoelectronics.

PubMed

Singh, R; Poole, J O; Poole, K F; Vaidya, S D

2002-01-01

In the last quarter of a century silicon-based integrated circuits (ICs) have played a major role in the growth of the economy throughout the world. A number of new technologies, such as quantum computing, molecular computing, DNA molecules for computing, etc., are currently being explored to create a product to replace semiconductor transistor technology. We have examined all of the currently explored options and found that none of these options are suitable as silicon IC's replacements. In this paper we provide fundamental device criteria that must be satisfied for the successful operation of a manufacturable, not yet invented, device. The two fundamental limits are the removal of heat and reliability. The switching speed of any practical man-made computing device will be in the range of 10(-15) to 10(-3) s. Heisenberg's uncertainty principle and the computer architecture set the heat generation limit. The thermal conductivity of the materials used in the fabrication of a nanodimensional device sets the heat removal limit. In current electronic products, redundancy plays a significant part in improving the reliability of parts with macroscopic defects. In the future, microscopic and even nanoscopic defects will play a critical role in the reliability of disruptive nanoelectronics. The lattice vibrations will set the intrinsic reliability of future computing systems. The two critical limits discussed in this paper provide criteria for the selection of materials used in the fabrication of future devices. Our work shows that diamond contains the clue to providing computing devices that will surpass the performance of silicon-based nanoelectronics.

Effect of ultraviolet illumination and ambient gases on the photoluminescence and electrical properties of nanoporous silicon layer for organic vapor sensor.

PubMed

Atiwongsangthong, Narin

2012-08-01

The purpose of this research, the nanoporous silicon layer were fabricated and investigated the physical properties such as photoluminescence and the electrical properties in order to develop organic vapor sensor by using nanoporous silicon. The Changes in the photoluminescence intensity of nanoporous silicon samples are studied during ultraviolet illumination in various ambient gases such as nitrogen, oxigen and vacuum. In this paper, the nanoporous silicon layer was used as organic vapor adsorption and sensing element. The advantage of this device are simple process compatible in silicon technology and usable in room temperature. The structure of this device consists of nanoporous silicon layer which is formed by anodization of silicon wafer in hydrofluoric acid solution and aluminum electrode which deposited on the top of nanoporous silicon layer by evaporator. The nanoporous silicon sensors were placed in a gas chamber with various organic vapor such as ethanol, methanol and isopropyl alcohol. From studying on electrical characteristics of this device, it is found that the nanoporous silicon layer can detect the different organic vapor. Therefore, the nanoporous silicon is important material for organic vapor sensor and it can develop to other applications about gas sensors in the future.

High-performance solid state supercapacitors assembling graphene interconnected networks in porous silicon electrode by electrochemical methods using 2,6-dihydroxynaphthalen.

PubMed

Romanitan, Cosmin; Varasteanu, Pericle; Mihalache, Iuliana; Culita, Daniela; Somacescu, Simona; Pascu, Razvan; Tanasa, Eugenia; Eremia, Sandra A V; Boldeiu, Adina; Simion, Monica; Radoi, Antonio; Kusko, Mihaela

2018-06-25

The challenge for conformal modification of the ultra-high internal surface of nanoporous silicon was tackled by electrochemical polymerisation of 2,6-dihydroxynaphthalene using cyclic voltammetry or potentiometry and, notably, after the thermal treatment (800 °C, N 2 , 4 h) an assembly of interconnected networks of graphene strongly adhering to nanoporous silicon matrix resulted. Herein we demonstrate the achievement of an easy scalable technology for solid state supercapacitors on silicon, with excellent electrochemical properties. Accordingly, our symmetric supercapacitors (SSC) showed remarkable performance characteristics, comparable to many of the best high-power and/or high-energy carbon-based supercapacitors, their figures of merit matching under battery-like supercapacitor behaviour. Furthermore, the devices displayed high specific capacity values along with enhanced capacity retention even at ultra-high rates for voltage sweep, 5 V/s, or discharge current density, 100 A/g, respectively. The cycling stability tests performed at relatively high discharge current density of 10 A/g indicated good capacity retention, with a superior performance demonstrated for the electrodes obtained under cyclic voltammetry approach, which may be ascribed on the one hand to a better coverage of the porous silicon substrate and, on the other hand, to an improved resilience of the hybrid electrode to pore clogging.

Neutron radiation tolerance of Au-activated silicon

NASA Technical Reports Server (NTRS)

Joyner, W. T.

1987-01-01

Double injection devices prepared by the introduction of deep traps, using the Au activation method have been found to tolerate gamma irradiation into the Gigarad (Si) region without significant degradation of operating characteristics. Silicon double injection devices, using deep levels creacted by Au diffusion, can tolerate fast neutron irradiation up to 10 to the 15th n/sq cm. Significant parameter degradation occurs at 10 to the 16th n/sq cm. However, since the actual doping of the basic material begins to change as a result of the transmutation of silicon into phosphorus for neutron fluences greater than 10 to the 17th/sq cm, the radiation tolerance of these devices is approaching the limit possible for any device based on initially doped silicon.

Bis(tri-n-hexylsilyl oxide) silicon phthalocyanine: a unique additive in ternary bulk heterojunction organic photovoltaic devices.

PubMed

Lessard, Benoît H; Dang, Jeremy D; Grant, Trevor M; Gao, Dong; Seferos, Dwight S; Bender, Timothy P

2014-09-10

Previous studies have shown that the use of bis(tri-n-hexylsilyl oxide) silicon phthalocyanine ((3HS)2-SiPc) as an additive in a P3HT:PC61BM cascade ternary bulk heterojunction organic photovoltaic (BHJ OPV) device results in an increase in the short circuit current (J(SC)) and efficiency (η(eff)) of up to 25% and 20%, respectively. The previous studies have attributed the increase in performance to the presence of (3HS)2-SiPc at the BHJ interface. In this study, we explored the molecular characteristics of (3HS)2-SiPc which makes it so effective in increasing the OPV device J(SC) and η(eff. Initially, we synthesized phthalocyanine-based additives using different core elements such as germanium and boron instead of silicon, each having similar frontier orbital energies compared to (3HS)2-SiPc and tested their effect on BHJ OPV device performance. We observed that addition of bis(tri-n-hexylsilyl oxide) germanium phthalocyanine ((3HS)2-GePc) or tri-n-hexylsilyl oxide boron subphthalocyanine (3HS-BsubPc) resulted in a nonstatistically significant increase in JSC and η(eff). Secondly, we kept the silicon phthalocyanine core and substituted the tri-n-hexylsilyl solubilizing groups with pentadecyl phenoxy groups and tested the resulting dye in a BHJ OPV. While an increase in JSC and η(eff) was observed at low (PDP)2-SiPc loadings, the increase was not as significant as (3HS)2-SiPc; therefore, (3HS)2-SiPc is a unique additive. During our study, we observed that (3HS)2-SiPc had an extraordinary tendency to crystallize compared to the other compounds in this study and our general experience. On the basis of this observation, we have offered a hypothesis that when (3HS)2-SiPc migrates to the P3HT:PC61BM interface the reason for its unique performance is not solely due to its frontier orbital energies but also might be due to a high driving force for crystallization.

Pre-strain effect on frequency-based impact energy dissipation through a silicone foam pad for shock mitigation [Pre-strain effect on the frequency response of shock mitigation through a silicone foam pad

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanborn, Brett; Song, Bo; Smith, Scott

Silicone foams have been used in a variety of applications from gaskets to cushioning pads over a wide range of environments. Particularly, silicone foams are used as a shock mitigation material for shock and vibration applications. Understanding the shock mitigation response, particularly in the frequency domain, is critical for optimal designs to protect internal devices and components more effectively and efficiently. The silicone foams may be subjected to pre-strains during the assembly process which may consequently influence the frequency response with respect to shock mitigation performance. A Kolsky compression bar was modified with pre-compression capabilities to characterize the shock mitigationmore » response of silicone foam in the frequency domain to determine the effect of pre-strain. Lastly, a silicone sample was also intentionally subjected to repeated pre-strain and dynamic loadings to explore the effect of repeated loading on the frequency response of shock mitigation.« less

Pre-strain effect on frequency-based impact energy dissipation through a silicone foam pad for shock mitigation [Pre-strain effect on the frequency response of shock mitigation through a silicone foam pad

DOE PAGES

Sanborn, Brett; Song, Bo; Smith, Scott

2015-12-29

Silicone foams have been used in a variety of applications from gaskets to cushioning pads over a wide range of environments. Particularly, silicone foams are used as a shock mitigation material for shock and vibration applications. Understanding the shock mitigation response, particularly in the frequency domain, is critical for optimal designs to protect internal devices and components more effectively and efficiently. The silicone foams may be subjected to pre-strains during the assembly process which may consequently influence the frequency response with respect to shock mitigation performance. A Kolsky compression bar was modified with pre-compression capabilities to characterize the shock mitigationmore » response of silicone foam in the frequency domain to determine the effect of pre-strain. Lastly, a silicone sample was also intentionally subjected to repeated pre-strain and dynamic loadings to explore the effect of repeated loading on the frequency response of shock mitigation.« less

Design and performance of SiPM-based readout of PbF 2 crystals for high-rate, precision timing applications

DOE PAGES

Kaspar, J.; Fienberg, A. T.; Hertzog, D. W.; ...

2017-01-11

Here, we have developed a custom amplifier board coupled to a large-format 16-channel Hamamatsu silicon photomultiplier device for use as the light sensor for the electromagnetic calorimeters in the Muon g-2 experiment at Fermilab. The calorimeter absorber is an array of lead-fluoride crystals, which produces short-duration Cherenkov light. The detector sits in the high magnetic field of the muon storage ring. The SiPMs selected, and their accompanying custom electronics, must preserve the short pulse shape, have high quantum efficiency, be non-magnetic, exhibit gain stability under varying rate conditions, and cover a fairly large fraction of the crystal exit surface area.more » We describe an optimized design that employs the new-generation of thru-silicon via devices. As a result, the performance is documented in a series of bench and beam tests.« less

Simultaneous wavelength conversion of ASK and DPSK signals based on four-wave-mixing in dispersion engineered silicon waveguides.

PubMed

Xu, Lin; Ophir, Noam; Menard, Michael; Lau, Ryan Kin Wah; Turner-Foster, Amy C; Foster, Mark A; Lipson, Michal; Gaeta, Alexander L; Bergman, Keren

2011-06-20

We experimentally demonstrate four-wave-mixing (FWM)-based continuous wavelength conversion of optical differential-phase-shift-keyed (DPSK) signals with large wavelength conversion ranges as well as simultaneous wavelength conversion of dual-wavelength channels with mixed modulation formats in 1.1-cm-long dispersion-engineered silicon waveguides. We first validate up to 100-nm wavelength conversion range for 10-Gb/s DPSK signals, showcasing the capability to perform phase-preserving operations at high bit rates in chip-scale devices over wide conversion ranges. We further validate the wavelength conversion of dual-wavelength channels modulated with 10-Gb/s packetized phase-shift-keyed (PSK) and amplitude-shift-keyed (ASK) signals; demonstrate simultaneous operation on multiple channels with mixed formats in chip-scale devices. For both configurations, we measure the spectral and temporal responses and evaluate the performances using bit-error-rate (BER) measurements.

Qubit entanglement between ring-resonator photon-pair sources on a silicon chip

PubMed Central

Silverstone, J. W.; Santagati, R.; Bonneau, D.; Strain, M. J.; Sorel, M.; O'Brien, J. L.; Thompson, M. G.

2015-01-01

Entanglement—one of the most delicate phenomena in nature—is an essential resource for quantum information applications. Scalable photonic quantum devices must generate and control qubit entanglement on-chip, where quantum information is naturally encoded in photon path. Here we report a silicon photonic chip that uses resonant-enhanced photon-pair sources, spectral demultiplexers and reconfigurable optics to generate a path-entangled two-qubit state and analyse its entanglement. We show that ring-resonator-based spontaneous four-wave mixing photon-pair sources can be made highly indistinguishable and that their spectral correlations are small. We use on-chip frequency demultiplexers and reconfigurable optics to perform both quantum state tomography and the strict Bell-CHSH test, both of which confirm a high level of on-chip entanglement. This work demonstrates the integration of high-performance components that will be essential for building quantum devices and systems to harness photonic entanglement on the large scale. PMID:26245267

A miniature solar device for overall water splitting consisting of series-connected spherical silicon solar cells.

PubMed

Kageshima, Yosuke; Shinagawa, Tatsuya; Kuwata, Takaaki; Nakata, Josuke; Minegishi, Tsutomu; Takanabe, Kazuhiro; Domen, Kazunari

2016-04-18

A novel "photovoltaics (PV) + electrolyzer" concept is presented using a simple, small, and completely stand-alone non-biased device for solar-driven overall water splitting. Three or four spherical-shaped p-n junction silicon balls were successfully connected in series, named "SPHELAR." SPHELAR possessed small projected areas of 0.20 (3PVs) and 0.26 cm(2) (4PVs) and exhibited working voltages sufficient for water electrolysis. Impacts of the configuration on the PV module performance were carefully analyzed, revealing that a drastic increase in the photocurrent (≈20%) was attained by the effective utilization of a reflective sheet. Separate investigations on the electrocatalyst performance showed that non-noble metal based materials with reasonably small sizes (<0.80 cm(2)) exhibited substantial currents at the PV working voltage. By combining the observations of the PV characteristics, light management and electrocatalyst performance, solar-driven overall water splitting was readily achieved, reaching solar-to-hydrogen efficiencies of 7.4% (3PVs) and 6.4% (4PVs).

Fabrication and Characterization of Thermo-Optic Mach-Zehnder Silicon Modulator

NASA Astrophysics Data System (ADS)

Park, Yeongho

This thesis focuses on the modeling, design, and fabrication of the Thermo-Optic Mach-Zehnder Modulator, which is one of the simple active devices in silicon photonics. The Mach-Zehnder interferometer (MZI) was formed as an optical path on a silicon on insulator (SOI) wafer of 2040+/-80 nm thick, and the thermo-optic effect was used to modulate the infrared light of 1553 nm wavelength by controlling the temperature of the one arm of the MZI. To fabricate and understand the Si photonic device, the whole process from theory to the measurement setup is introduced. Additionally, all the fabrication details and some informative experiments which were performed during the fabrication are discussed for students who will study the more developed devices. The width of the designed waveguide is 4 mum, but the width of the fabricated waveguide is 3.0+/-0.2 mum due to the isotropic etching. For the lithography for both patterning waveguides and metal contacts, the AZ 5214 photoresist was used, and the details of the lithography was discussed. Furthermore, the lift-off method was performed and introduced to solve the over-etching problem. The fabricated metal contacts can withstand up to 1.6W, and the electric power 0.3W is required to make Pi phase difference according to the simulation result by the simulation software Lumerical. The optical output of the device was not detected due to the huge losses from the sidewall roughness and the insertion loss, so it is discussed in the experimental measurement chapter.

A Study on Organic-Metal Halide Perovskite Film Morphology, Interfacial Layers, Tandem Applications, and Encapsulation

NASA Astrophysics Data System (ADS)

Fisher, Dallas A.

Organic-metal halide perovskites have brought about a new wave of research in the photovoltaic community due to their ideally suited optical and electronic parameters. In less than a decade, perovskite solar cell performance has skyrocketed to unprecedented efficiencies with numerous reported methodologies. Perovskites face many challenges with high-quality film morphology, interfacial layers, and long-term stability. In this work, these active areas are explored through a combination of studies. First, the importance of perovskite film precursor ratios is explored with an in-depth study of carrier lifetime and solvent-grain effects. It was found that excess lead iodide precursor greatly improves the film morphology by reducing pinholes in the solar absorber. Dimethyl sulfoxide (DMSO) solvent was found to mend grains, as well as improve carrier lifetime and device performance, possibly by passivation of grain boundary traps. Second, applications of perovskite with tandem cells is investigated, with an emphasis for silicon devices. Perovskites can easily be integrated with silicon, which already has strong market presence. Additionally, both materials' bandgaps are ideally suited for maximum tandem efficiency. The silicon/perovskite tandem device structure necessitated the optimization of inverted (p-i-n) structure devices. PEDOT:PSS, copper oxide, and nickel oxide p-type layers were explored through a combination of photoluminescent, chemical reactivity, and solar simulation results. Results were hindered due to resistive ITO and rough silicon substrates, but tandem devices displayed Voc indicative of proper monolithic performance. Third, replacement of titanium dioxide n-type layer with iron oxide (Fe 2O3, common rust) was studied. Iron oxide experiences less ultraviolet instability than that of titanium dioxide under solar illumination. It was found that current density slightly decreased due to parasitic absorption from the rust, but that open circuit voltage decreased drastically due to poor band alignment. Fe2O3 appears to be better suited to a narrower band gap material than methylammonium lead iodide perovskite. Finally, encapsulation of perovskite devices with epoxy coatings is explored as a method to improve long-term stability. Perovskites are sensitive to a variety of conditions, but most importantly water and polar molecules. Encapsulants act as a moisture/oxygen barrier, but also prevent outgassing of the organic components. Three epoxies were tested in high heat and high humidity conditions. Important factors in the curing process were uncovered such as the sensitivity of UV-epoxies to amine functional groups found in common p-type dopants and perovskite layers. Moisture ingress was the failure point for high-humidity/heat devices which was confirmed through conversion to yellow lead iodide. A revised device fabrication method is proposed to reduce moisture ingress for future experiments.

Comparative studies of silicon photomultipliers and traditional vacuum photomultiplier tubes

NASA Astrophysics Data System (ADS)

Shi, Feng; Lü, Jun-Guang; Lu, Hong; Wang, Huan-Yu; Ma, Yu-Qian; Hu, Tao; Zhou, Li; Cai, Xiao; Sun, Li-Jun; Yu, Bo-Xiang; Fang, Jian; Xie, Yu-Guang; An, Zheng-Hua; Wang, Zhi-Gang; Gao, Min; Li, Xin-Qiao; Xu, Yan-Bing; Wang, Ping; Sun, Xi-Lei; Zhang, Ai-Wu; Xue, Zhen; Liu, Hong-Bang; Wang, Xiao-Dong; Zhao, Xiao-Yun; Zheng, Yang-Heng; Meng, Xiang-Cheng; Wang, Hui

2011-01-01

Silicon photomultipliers (SiPMs) are a new generation of semiconductor-based photon counting devices with the merits of low weight, low power consumption and low voltage operation, promising to meet the needs of space particle physics experiments. In this paper, comparative studies of SiPMs and traditional vacuum photomultiplier tubes (PMTs) have been performed regarding the basic properties of dark currents, dark counts and excess noise factors. The intrinsic optical crosstalk effect of SiPMs was evaluated.

Porous silicon carbide (SiC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS circuits with 500 nm thick Si, operating around 3.8 µm wavelength. Results on facet coupling and sub-wavelength engineered grating coupler solutions in the mid-IR regime will be compared.

Modeling and fabrication of 4H-SiC Schottky junction

NASA Astrophysics Data System (ADS)

Martychowiec, A.; Pedryc, A.; Kociubiński, A.

2017-08-01

The rapidly growing demand for electronic devices requires using of alternative semiconductor materials, which could replace conventional silicon. Silicon carbide has been proposed for these harsh environment applications (high temperature, high voltage, high power conditions) because of its wide bandgap, its high temperature operation ability, its excellent thermal and chemical stability, and its high breakdown electric field strength. The Schottky barrier diode (SBD) is known as one of the best refined SiC devices. This paper presents prepared model, simulations and description of technology of 4H-SiC Schottky junction as well as characterization of fabricated structures. The future aim of the application of the structures is an optical detection of an ultraviolet radiation. The model section contains a comparison of two different solutions of SBD's construction. Simulations - as a crucial process of designing electronic devices - have been performed using the ATLAS device of Silvaco TCAD software. As a final result the paper shows I-V characteristics of fabricated diodes.

ESD robustness improving for the low-voltage triggering silicon-controlled rectifier by adding NWell at cathode

NASA Astrophysics Data System (ADS)

Jin, Xiangliang; Zheng, Yifei; Wang, Yang; Guan, Jian; Hao, Shanwan; Li, Kan; Luo, Jun

2018-01-01

The low-voltage triggering silicon-controlled rectifier (LVTSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its low trigger voltage and strong current-tolerating capability per area. In this paper, an improved LVTSCR by adding a narrow NWell (NW2) under the source region of NMOS is discussed, which is realized in a 0.5-μm CMOS process. A 2-dimension (2D) device simulation platform and a transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the preliminary LVTSCR, the improved LVTSCR elevates the second breakdown current (It2) from 2.39 A to 5.54 A and increases the holding voltage (Vh) from 3.04 V to 4.09 V without expanding device area or sacrificing any ESD performances. Furthermore, the influence of the size of the narrow NWell under the source region of NMOS on holding voltage is also discussed.

Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

NASA Astrophysics Data System (ADS)

Trivedi, Nitin; Kumar, Manoj; Haldar, Subhasis; Deswal, S. S.; Gupta, Mridula; Gupta, R. S.

2017-09-01

A charge plasma technique based dopingless (DL) accumulation mode (AM) junctionless (JL) cylindrical surrounding gate (CSG) MOSFET has been proposed and extensively investigated. Proposed device has no physical junction at source to channel and channel to drain interface. The complete silicon pillar has been considered as undoped. The high free electron density or induced N+ region is designed by keeping the work function of source/drain metal contacts lower than the work function of undoped silicon. Thus, its fabrication complexity is drastically reduced by curbing the requirement of high temperature doping techniques. The electrical/analog characteristics for the proposed device has been extensively investigated using the numerical simulation and are compared with conventional junctionless cylindrical surrounding gate (JL-CSG) MOSFET with identical dimensions. For the numerical simulation purpose ATLAS-3D device simulator is used. The results show that the proposed device is more short channel immune to conventional JL-CSG MOSFET and suitable for faster switching applications due to higher I ON/ I OFF ratio.

Silicon Carbide Power Devices and Integrated Circuits

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan; Samsel, Isaak; LaBel, Ken; Chen, Yuan; Ikpe, Stanley; Wilcox, Ted; Phan, Anthony; Kim, Hak; Topper, Alyson

2017-01-01

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

Silicon nanowire device and method for its manufacture

DOEpatents

Okandan, Murat; Draper, Bruce L.; Resnick, Paul J.

2017-01-03

There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 .mu.m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pocha, Michael D.; Carey, Kent

The information age was maturing, and photonics was emerging as a significant technology with important'national security and commercial implications at the time of the CRADA. This was largely due to the vast information carrying capacity of optical beams and the availability of cheap.and effective optical fiber waveguides to guide the light. However, a major limitation to the widespread deployment of photonic systems was the high-cost (in an economic and performance sense) associated with coupling optical power between optoelectronic waveguide devices or between a device and an optical fiber. The problem was critical in the case of single-mode waveguide devices. Mitigatingmore » these costs would be a significant and pervasive enabler of the technology for a wide variety of applications that would have crucial defense and economic impact. The partners worked together to develop optical mode size converters on silicon substrates. Silicon was chosen because of its compatibility with the required photolithographic and micromachining techniques. By choosing silicon, these techniques could enable the close coupling of high-speed, high density silicon electronic circuitry to efficient low-cost photonics. The efficient coupling of electronics and photonics technologies would be important for many information age technologies. The joint nature of this project was intended to allow HP to benefit from some unique LLNL capabilities, and LLNL would be in a position to learn from HP and enhance its value to fundamental DP missions. Although the CRADA began as a hardware development project to develop the mode converter, it evolved into a software development venture. LLNL and HP researchers examined literature, performed some preliminary calculations, and evaluated production trade-offs of several known techniques to determine the best candidates for an integrated system.« less

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

NASA Astrophysics Data System (ADS)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper

PubMed Central

Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2014-01-01

A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM0 mode into the TE1 mode, which will output as the TE0 mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < −17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology. PMID:25402029

Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

PubMed

Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2014-11-17

A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < -17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology.

Advanced interface modelling of n-Si/HNO3 doped graphene solar cells to identify pathways to high efficiency

NASA Astrophysics Data System (ADS)

Zhao, Jing; Ma, Fa-Jun; Ding, Ke; Zhang, Hao; Jie, Jiansheng; Ho-Baillie, Anita; Bremner, Stephen P.

2018-03-01

In graphene/silicon solar cells, it is crucial to understand the transport mechanism of the graphene/silicon interface to further improve power conversion efficiency. Until now, the transport mechanism has been predominantly simplified as an ideal Schottky junction. However, such an ideal Schottky contact is never realised experimentally. According to literature, doped graphene shows the properties of a semiconductor, therefore, it is physically more accurate to model graphene/silicon junction as a Heterojunction. In this work, HNO3-doped graphene/silicon solar cells were fabricated with the power conversion efficiency of 9.45%. Extensive characterization and first-principles calculations were carried out to establish an advanced technology computer-aided design (TCAD) model, where p-doped graphene forms a straddling heterojunction with the n-type silicon. In comparison with the simple Schottky junction models, our TCAD model paves the way for thorough investigation on the sensitivity of solar cell performance to graphene properties like electron affinity. According to the TCAD heterojunction model, the cell performance can be improved up to 22.5% after optimizations of the antireflection coatings and the rear structure, highlighting the great potentials for fabricating high efficiency graphene/silicon solar cells and other optoelectronic devices.

Microbiopsy/precision cutting devices

DOEpatents

Krulevitch, P.A.; Lee, A.P.; Northrup, M.A.; Benett, W.J.

1999-07-27

Devices are disclosed for performing tissue biopsy on a small scale (microbiopsy). By reducing the size of the biopsy tool and removing only a small amount of tissue or other material in a minimally invasive manner, the risks, costs, injury and patient discomfort associated with traditional biopsy procedures can be reduced. By using micromachining and precision machining capabilities, it is possible to fabricate small biopsy/cutting devices from silicon. These devices can be used in one of four ways (1) intravascularly, (2) extravascularly, (3) by vessel puncture, and (4) externally. Additionally, the devices may be used in precision surgical cutting. 6 figs.

Phase sensitive amplification in integrated waveguides (Conference Presentation)

NASA Astrophysics Data System (ADS)

Schroeder, Jochen B.; Zhang, Youngbin; Husko, Chad A.; LeFrancois, Simon; Eggleton, Benjamin J.

2017-02-01

Phase sensitive amplification (PSA) is an attractive technology for integrated all-optical signal processing, due to it's potential for noiseless amplification, phase regeneration and generation of squeezed light. In this talk I will review our results on implementing four-wave-mixing based PSA inside integrated photonic devices. In particular I will discuss PSA in chalcogenide ridge waveguides and silicon slow-light photonic crystals. We achieve PSA in both pump- and signal-degenerate schemes with maximum extinction ratios of 11 (silicon) and 18 (chalcogenide) dB. I will further discuss the influence of two-photon absorption and free carrier effects on the performance of silicon-based PSAs.

CuO-Functionalized Silicon Photoanodes for Photoelectrochemical Water Splitting Devices.

PubMed

Shi, Yuanyuan; Gimbert-Suriñach, Carolina; Han, Tingting; Berardi, Serena; Lanza, Mario; Llobet, Antoni

2016-01-13

One main difficulty for the technological development of photoelectrochemical (PEC) water splitting (WS) devices is the fabrication of active, stable and cost-effective photoelectrodes that ensure high performance. Here, we report the development of a CuO/Silicon based photoanode, which shows an onset potential for the water oxidation of 0.53 V vs SCE at pH 9, that is, an overpotential of 75 mV, and high stability above 10 h. These values account for a photovoltage of 420 mV due to the absorbed photons by silicon, as proven by comparing with analogous CuO/FTO electrodes that are not photoactive. The photoanodes have been fabricated by sputtering a thin film of Cu(0) on commercially available n-type Si wafers, followed by a photoelectrochemical treatment in basic pH conditions. The resulting CuO/Cu layer acts as (1) protective layer to avoid the corrosion of nSi, (2) p-type hole conducting layer for efficient charge separation and transportation, and (3) electrocatalyst to reduce the overpotential of the water oxidation reaction. The low cost, low toxicity, and good performance of CuO-based coatings can be an attractive solution to functionalize unstable materials for solar energy conversion.

Performance of MEMS Silicon Oscillator, ASFLM1, under Wide Operating Temperature Range

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2008-01-01

Over the last few years, MEMS (Micro-Electro-Mechanical Systems) resonator-based oscillators began to be offered as commercial-off-the-shelf (COTS) parts by a few companies [1-2]. These quartz-free, miniature silicon devices could compete with the traditional crystal oscillators in providing the timing (clock function) for many digital and analog electronic circuits. They provide stable output frequency, offer great tolerance to shock and vibration, and are immune to electro-static discharge [1-2]. In addition, they are encapsulated in compact lead-free packages, cover a wide frequency range (1 MHz to 125 MHz), and are specified, depending on the grade, for extended temperature operation from -40 C to +85 C. The small size of the MEMS oscillators along with their reliability and thermal stability make them candidates for use in space exploration missions. Limited data, however, exist on the performance and reliability of these devices under operation in applications where extreme temperatures or thermal cycling swings, which are typical of space missions, are encountered. This report presents the results of the work obtained on the evaluation of an ABRACON Corporation MEMS silicon oscillator chip, type ASFLM1, under extreme temperatures.

Visual Sensor for Sterilization of Polymer Fixtures Using Embedded Mesoporous Silicon Photonic Crystals.

PubMed

Kumeria, Tushar; Wang, Joanna; Chan, Nicole; Harris, Todd J; Sailor, Michael J

2018-01-26

A porous photonic crystal is integrated with a plastic medical fixture (IV connector hub) to provide a visual colorimetric sensor to indicate the presence or absence of alcohol used to sterilize the fixture. The photonic crystal is prepared in porous silicon (pSi) by electrochemical anodization of single crystal silicon, and the porosity and the stop band of the material is engineered such that the integrated device visibly changes color (green to red or blue to green) when infiltrated with alcohol. Two types of self-reporting devices are prepared and their performance compared: the first type involves heat-assisted fusion of a freestanding pSi photonic crystal to the connector end of a preformed polycarbonate hub, forming a composite where the unfilled portion of the pSi film acts as the sensor; the second involves generation of an all-polymer replica of the pSi photonic crystal by complete thermal infiltration of the pSi film and subsequent chemical dissolution of the pSi portion. Both types of sensors visibly change color when wetted with alcohol, and the color reverts to the original upon evaporation of the liquid. The sensor performance is verified using E. coli-infected samples.

Betavoltaic device in por-SiC/Si C-Nuclear Energy Converter

NASA Astrophysics Data System (ADS)

Akimchenko, Alina; Chepurnov, Victor; Dolgopolov, Mikhail; Gurskaya, Albina; Kuznetsov, Oleg; Mashnin, Alikhan; Radenko, Vitaliy; Radenko, Alexander; Surnin, Oleg; Zanin, George

2017-10-01

The miniature and low-power devices with long service life in hard operating conditions like the Carbon-14 beta-decay energy converters indeed as eternal resource for integrated MEMS and NEMS are considered. Authors discuss how to create the power supply for MEMS/NEMS devices, based on porous SiC/Si structure, which are tested to be used as the beta-decay energy converters of radioactive C-14 into electrical energy. This is based on the silicon carbide obtaining by self-organizing mono 3C-SiC endotaxy on the Si substrate. The new idea is the C-14 atoms including in molecules in the silicon carbide porous structure by this technology, which will increase the efficiency of the converter due to the greater intensity of electron-hole pairs generation rate in the space charge region. The synthesis of C-14 can be also performed by using the electronically controlled magneto-optic chamber.

Perovskite Solar Cells with Large-Area CVD-Graphene for Tandem Solar Cells.

PubMed

Lang, Felix; Gluba, Marc A; Albrecht, Steve; Rappich, Jörg; Korte, Lars; Rech, Bernd; Nickel, Norbert H

2015-07-16

Perovskite solar cells with transparent contacts may be used to compensate for thermalization losses of silicon solar cells in tandem devices. This offers a way to outreach stagnating efficiencies. However, perovskite top cells in tandem structures require contact layers with high electrical conductivity and optimal transparency. We address this challenge by implementing large-area graphene grown by chemical vapor deposition as a highly transparent electrode in perovskite solar cells, leading to identical charge collection efficiencies. Electrical performance of solar cells with a graphene-based contact reached those of solar cells with standard gold contacts. The optical transmission by far exceeds that of reference devices and amounts to 64.3% below the perovskite band gap. Finally, we demonstrate a four-terminal tandem device combining a high band gap graphene-contacted perovskite top solar cell (Eg = 1.6 eV) with an amorphous/crystalline silicon bottom solar cell (Eg = 1.12 eV).

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Low temperature perovskite solar cells with an evaporated TiO 2 compact layer for perovskite silicon tandem solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bett, Alexander J.; Schulze, Patricia S. C.; Winkler, Kristina

Silicon-based tandem solar cells can overcome the efficiency limit of single junction silicon solar cells. Perovskite solar cells are particularly promising as a top cell in monolithic tandem devices due to their rapid development towards high efficiencies, a tunable band gap with a sharp optical absorption edge and a simple production process. In monolithic tandem devices, the perovskite solar cell is deposited directly on the silicon cell, requiring low-temperature processes (< 200 °C) to maintain functionality of under-lying layers of the silicon cell in case of highly efficient silicon hetero-junction (SHJ) bottom solar cell. In this work, we present amore » complete low-temperature process for perovskite solar cells including a mesoporous titanium oxide (TiO 2) scaffold - a structure yielding the highest efficiencies for single-junction perovskite solar cells. We show that evaporation of the compact TiO 2 hole blocking layer and ultra-violet (UV) curing for the mesoporous TiO 2 layer allows for good performance, comparable to high-temperature (> 500 °C) processes. With both manufacturing routes, we obtain short-circuit current densities (J SC) of about 20 mA/cm 2, open-circuit voltages (V OC) over 1 V, fill factors (FF) between 0.7 and 0.8 and efficiencies (n) of more than 15%. We further show that the evaporated TiO 2 layer is suitable for the application in tandem devices. The series resistance of the layer itself and the contact resistance to an indium doped tin oxide (ITO) interconnection layer between the two sub-cells are low. Additionally, the low parasitic absorption for wavelengths above the perovskite band gap allow a higher absorption in the silicon bottom solar cell, which is essential to achieve high tandem efficiencies.« less

Low temperature perovskite solar cells with an evaporated TiO 2 compact layer for perovskite silicon tandem solar cells

DOE PAGES

Bett, Alexander J.; Schulze, Patricia S. C.; Winkler, Kristina; ...

2017-09-21

Silicon-based tandem solar cells can overcome the efficiency limit of single junction silicon solar cells. Perovskite solar cells are particularly promising as a top cell in monolithic tandem devices due to their rapid development towards high efficiencies, a tunable band gap with a sharp optical absorption edge and a simple production process. In monolithic tandem devices, the perovskite solar cell is deposited directly on the silicon cell, requiring low-temperature processes (< 200 °C) to maintain functionality of under-lying layers of the silicon cell in case of highly efficient silicon hetero-junction (SHJ) bottom solar cell. In this work, we present amore » complete low-temperature process for perovskite solar cells including a mesoporous titanium oxide (TiO 2) scaffold - a structure yielding the highest efficiencies for single-junction perovskite solar cells. We show that evaporation of the compact TiO 2 hole blocking layer and ultra-violet (UV) curing for the mesoporous TiO 2 layer allows for good performance, comparable to high-temperature (> 500 °C) processes. With both manufacturing routes, we obtain short-circuit current densities (J SC) of about 20 mA/cm 2, open-circuit voltages (V OC) over 1 V, fill factors (FF) between 0.7 and 0.8 and efficiencies (n) of more than 15%. We further show that the evaporated TiO 2 layer is suitable for the application in tandem devices. The series resistance of the layer itself and the contact resistance to an indium doped tin oxide (ITO) interconnection layer between the two sub-cells are low. Additionally, the low parasitic absorption for wavelengths above the perovskite band gap allow a higher absorption in the silicon bottom solar cell, which is essential to achieve high tandem efficiencies.« less

Silicon device performance measurements to support temperature range enhancement

NASA Technical Reports Server (NTRS)

Bromstead, James; Weir, Bennett; Nelms, R. Mark; Johnson, R. Wayne; Askew, Ray

1994-01-01

Silicon based power devices can be used at 200 C. The device measurements made during this program show a predictable shift in device parameters with increasing temperature. No catastrophic or abrupt changes occurred in the parameters over the temperature range. As expected, the most dramatic change was the increase in leakage currents with increasing temperature. At 200 C the leakage current was in the milliAmp range but was still several orders of magnitude lower than the on-state current capabilities of the devices under test. This increase must be considered in the design of circuits using power transistors at elevated temperature. Three circuit topologies have been prototyped using MOSFET's and IGBT's. The circuits were designed using zero current or zero voltage switching techniques to eliminate or minimize hard switching of the power transistors. These circuits have functioned properly over the temperature range. One thousand hour life data have been collected for two power supplies with no failures and no significant change in operating efficiency. While additional reliability testing should be conducted, the feasibility of designing soft switched circuits for operation at 200 C has been successfully demonstrated.

Design optimization of beta- and photovoltaic conversion devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wichner, R.; Blum, A.; Fischer-Colbrie, E.

1976-01-08

This report presents the theoretical and experimental results of an LLL Electronics Engineering research program aimed at optimizing the design and electronic-material parameters of beta- and photovoltaic p-n junction conversion devices. To meet this objective, a comprehensive computer code has been developed that can handle a broad range of practical conditions. The physical model upon which the code is based is described first. Then, an example is given of a set of optimization calculations along with the resulting optimized efficiencies for silicon (Si) and gallium-arsenide (GaAs) devices. The model we have developed, however, is not limited to these materials. Itmore » can handle any appropriate material--single or polycrystalline-- provided energy absorption and electron-transport data are available. To check code validity, the performance of experimental silicon p-n junction devices (produced in-house) were measured under various light intensities and spectra as well as under tritium beta irradiation. The results of these tests were then compared with predicted results based on the known or best estimated device parameters. The comparison showed very good agreement between the calculated and the measured results.« less

Low-cost, high-efficiency organic/inorganic hetero-junction hybrid solar cells for next generation photovoltaic device

NASA Astrophysics Data System (ADS)

Pudasaini, P. R.; Ayon, A. A.

2013-12-01

Organic/inorganic hybrid structures are considered innovative alternatives for the next generation of low-cost photovoltaic devices because they combine advantages of the purely organic and inorganic versions. Here, we report an efficient hybrid solar cell based on sub-wavelength silicon nanotexturization in combination with the spin-coating of poly (3,4-ethylene-dioxythiophene):polystyrenesulfonate (PEDOT:PSS). The described devices were analyzed by collecting current-voltage and capacitance-voltage measurements in order to explore the organic/inorganic heterojunction properties. ALD deposited ultrathin aluminium oxide was used as a junction passivation layer between the nanotextured silicon surface and the organic polymer. The measured interface defect density of the device was observed to decrease with the inclusion of an ultrathin Al2O3 passivation layer leading to an improved electrical performance. This effect is thought to be ascribed to the suppression of charge recombination at the organic/inorganic interface. A maximum power conversion efficiency in excess of 10% has been achieved for the optimized geometry of the device, in spite of lacking an antireflection layer or back surface field enhancement schemes.

Method for implementation of back-illuminated CMOS or CCD imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2008-01-01

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Additives to silane for thin film silicon photovoltaic devices

DOEpatents

Hurley, Patrick Timothy; Ridgeway, Robert Gordon; Hutchison, Katherine Anne; Langan, John Giles

2013-09-17

Chemical additives are used to increase the rate of deposition for the amorphous silicon film (.alpha.Si:H) and/or the microcrystalline silicon film (.mu.CSi:H). The electrical current is improved to generate solar grade films as photoconductive films used in the manufacturing of Thin Film based Photovoltaic (TFPV) devices.

Ultra-Sensitive Magnetoresistive Displacement Sensing Device

NASA Technical Reports Server (NTRS)

Olivas, John D. (Inventor); Lairson, Bruce M. (Inventor); Ramesham, Rajeshuni (Inventor)

2003-01-01

An ultrasensitive displacement sensing device for use in accelerometers, pressure gauges, temperature transducers, and the like, comprises a sputter deposited, multilayer, magnetoresistive field sensor with a variable electrical resistance based on an imposed magnetic field. The device detects displacement by sensing changes in the local magnetic field about the magnetoresistive field sensor caused by the displacement of a hard magnetic film on a movable microstructure. The microstructure, which may be a cantilever, membrane, bridge, or other microelement, moves under the influence of an acceleration a known displacement predicted by the configuration and materials selected, and the resulting change in the electrical resistance of the MR sensor can be used to calculate the displacement. Using a micromachining approach, very thin silicon and silicon nitride membranes are fabricated in one preferred embodiment by means of anisotropic etching of silicon wafers. Other approaches include reactive ion etching of silicon on insulator (SOI), or Low Pressure Chemical Vapor Deposition of silicon nitride films over silicon substrates. The device is found to be improved with the use of giant magnetoresistive elements to detect changes in the local magnetic field.

EDITORIAL: Special issue on silicon photonics

NASA Astrophysics Data System (ADS)

Reed, Graham; Paniccia, Mario; Wada, Kazumi; Mashanovich, Goran

2008-06-01

The technology now known as silicon photonics can be traced back to the pioneering work of Soref in the mid-1980s (see, for example, Soref R A and Lorenzo J P 1985 Electron. Lett. 21 953). However, the nature of the research conducted today, whilst it builds upon that early work, is unrecognizable in terms of technology metrics such as device efficiency, device data rate and device dimensions, and even in targeted applications areas. Today silicon photonics is still evolving, and is enjoying a period of unprecedented attention in terms of research focus. This has resulted in orders-of-magnitude improvement in device performance over the last few years to levels many thought were impossible. However, despite the existence of the research field for more than two decades, silicon is still regarded as a 'new' optical material, one that is being manipulated and modified to satisfy the requirements of a range of applications. This is somewhat ironic since silicon is one of the best known and most thoroughly studied materials, thanks to the electronics industry that has made silicon its material of choice. The principal reasons for the lack of study of this 'late developer' are that (i) silicon is an indirect bandgap material and (ii) it does not exhibit a linear electro-optic (Pockels) effect. The former condition means that it is difficult to make a laser in silicon based on the intrinsic performance of the material, and consequently, in recent years, researchers have attempted to modify the material to artificially engineer the conditions for lasing to be viable (see, for example, the review text, Jalali B et al 2008 Silicon Lasers in Silicon Photonics: The State of the Art ed G T Reed (New York: Wiley)). The latter condition means that optical modulators are intrinsically less efficient in silicon than in some other materials, particularly when targeting the popular telecommunications wavelengths around 1.55 μm. Therefore researchers have sought alternative mechanisms for modulation in silicon that have yielded increasingly impressive results (see, for example, Liao L et al 2007 Electron. Lett. 43 issue 22). The convergence of computing and communications and the resultant demand for increased bandwidth has been one of the factors influencing the upsurge of interest in silicon, together with the requirement for photonic and electronic integration, all to be realized at low cost. Thus emerging applications such as short-reach communications links for optical interconnect and fibre to the home (FTTH) (as well as a multitude of other applications) are frequently offered as examples of where silicon photonics will have a significant, perhaps a revolutionary, impact. One of the major conclusions of the joint MIT-industry Communication Technology Roadmap (http://mph-roadmap.mit.edu/index.php), was that 'Photonics technology will be driven by electronic-photonic synergy and short (<1 km) reach interconnection. This direction will ignite a major shift in leadership of the optical component industry from information transmission (telecom) to information processing (computing imaging).' Thus the case is made for low-cost implementation, making silicon a prime candidate, particularly if true electronic/photonic integration is to be realized. Despite the limitations of silicon as an optical material, the intrinsic advantages of the most popular silicon optical platform, silicon-on-insulator (SOI), should not be overlooked. The very high confinement nature of this technology platform brings a host of advantages, including the possibility to miniaturize devices and circuits, to reduce power consumption, optical loss and cost, to increase yield, and to be compatible with CMOS-based intelligence. Thus the limitations of silicon as an optical material can be offset against the very significant advantages, to both commercial as well as technological success. Of course, there is still much to do, hence the increasing global investment in silicon technology and the massive increase in research activity in silicon photonics since the early work in the 1980s. Only time will tell if silicon can realize its potential to satisfy the ever-increasing array of applications. However, the indications are positive, and the contributors to this cause employ increasingly impressive levels of intellectual and technological capability to realize the desired goals. It is an interesting time to be involved in slicon photonics, and it will be equally fascinating to watch the evolution of the technology in the future. Whatever happens, silicon will make the transition from being regarded as purely an electronic material to recognition as an optoelectronic material. The evidence for this is represented in the collection of papers that form this special issue of Semiconductor Science and Technology. This special issue is, in turn, representative of the rapidly increasing body of literature that represents the field of silicon photonics. In a field of such rapid transition as silicon photonics, the hope is that this special issue takes a snapshot of the technology at the time of publication, to document the progress of the field for future reference, and in turn to stimulate further work. The Guest Editors are grateful for the tireless support of Clare Bedrock at IOP Publishing.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Transfer of micro and nano-photonic silicon nanomembrane waveguide devices on flexible substrates.

PubMed

Ghaffari, Afshin; Hosseini, Amir; Xu, Xiaochuan; Kwong, David; Subbaraman, Harish; Chen, Ray T

2010-09-13

This paper demonstrates transfer of optical devices without extra un-patterned silicon onto low-cost, flexible plastic substrates using single-crystal silicon nanomembranes. Employing this transfer technique, stacking two layers of silicon nanomembranes with photonic crystal waveguide in the first layer and multi mode interference couplers in the second layer is shown, respectively. This technique is promising to realize high density integration of multilayer hybrid structures on flexible substrates.

Effects of 22 MeV protons on single junction and silicon controlled rectifiers

NASA Technical Reports Server (NTRS)

Beatty, M. E., III

1972-01-01

The effects of 22-MeV protons on various types of silicon single junction and silicon controlled rectifiers were investigated. The results show that low-leakage devices and silicon controlled rectifiers are the most susceptable to radiation damage. There are also differences noted between single junction rectifiers of the same type made by different manufacturers, which emphasizes the need for better selection of devices used in spacecraft.

Periodically poled silicon

NASA Astrophysics Data System (ADS)

Hon, Nick K.; Tsia, Kevin K.; Solli, Daniel R.; Jalali, Bahram

2009-03-01

We propose a new class of photonic devices based on periodic stress fields in silicon that enable second-order nonlinearity as well as quasi-phase matching. Periodically poled silicon (PePSi) adds the periodic poling capability to silicon photonics and allows the excellent crystal quality and advanced manufacturing capabilities of silicon to be harnessed for devices based on second-order nonlinear effects. As an example of the utility of the PePSi technology, we present simulations showing that midwave infrared radiation can be efficiently generated through difference frequency generation from near-infrared with a conversion efficiency of 50%.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

DOEpatents

Tour, James M.; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2015-09-08

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the gap region between the first electrical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

DOEpatents

Tour, James M; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2013-11-26

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the the gap region between the first electical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Capacitive wearable tactile sensor based on smart textile substrate with carbon black /silicone rubber composite dielectric

NASA Astrophysics Data System (ADS)

Guo, Xiaohui; Huang, Ying; Cai, Xia; Liu, Caixia; Liu, Ping

2016-04-01

To achieve the wearable comfort of electronic skin (e-skin), a capacitive sensor printed on a flexible textile substrate with a carbon black (CB)/silicone rubber (SR) composite dielectric was demonstrated in this paper. Organo-silicone conductive silver adhesive serves as a flexible electrodes/shielding layer. The structure design, sensing mechanism and the influence of the conductive filler content and temperature variations on the sensor performance were investigated. The proposed device can effectively enhance the flexibility and comfort of wearing the device asthe sensing element has achieved a sensitivity of 0.02536%/KPa, a hysteresis error of 5.6%, and a dynamic response time of ~89 ms at the range of 0-700 KPa. The drift induced by temperature variations has been calibrated by presenting the temperature compensation model. The research on the time-space distribution of plantar pressure information and the experiment of the manipulator soft-grasping were implemented with the introduced device, and the experimental results indicate that the capacitive flexible textile tactile sensor has good stability and tactile perception capacity. This study provides a good candidate for wearable artificial skin.

High-performance silicon nanowire bipolar phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Chen, Kaixiang; Crozier, Kenneth B.; Dan, Yaping

2016-07-01

Silicon nanowires (SiNWs) have emerged as sensitive absorbing materials for photodetection at wavelengths ranging from ultraviolet (UV) to the near infrared. Most of the reports on SiNW photodetectors are based on photoconductor, photodiode, or field-effect transistor device structures. These SiNW devices each have their own advantages and trade-offs in optical gain, response time, operating voltage, and dark current noise. Here, we report on the experimental realization of single SiNW bipolar phototransistors on silicon-on-insulator substrates. Our SiNW devices are based on bipolar transistor structures with an optically injected base region and are fabricated using CMOS-compatible processes. The experimentally measured optoelectronic characteristics of the SiNW phototransistors are in good agreement with simulation results. The SiNW phototransistors exhibit significantly enhanced response to UV and visible light, compared with typical Si p-i-n photodiodes. The near infrared responsivities of the SiNW phototransistors are comparable to those of Si avalanche photodiodes but are achieved at much lower operating voltages. Compared with other reported SiNW photodetectors as well as conventional bulk Si photodiodes and phototransistors, the SiNW phototransistors in this work demonstrate the combined advantages of high gain, high photoresponse, low dark current, and low operating voltage.

Silicon MOS inductor

DOEpatents

Balberg, Isaac

1981-01-01

A device made of amorphous silicon which exhibits inductive properties at certain voltage biases and in certain frequency ranges in described. Devices of the type described can be made in integrated circuit form.

Performance tradeoff between lateral and interdigitated doping patterns for high speed carrier-depletion based silicon modulators.

PubMed

Yu, Hui; Pantouvaki, Marianna; Van Campenhout, Joris; Korn, Dietmar; Komorowska, Katarzyna; Dumon, Pieter; Li, Yanlu; Verheyen, Peter; Absil, Philippe; Alloatti, Luca; Hillerkuss, David; Leuthold, Juerg; Baets, Roel; Bogaerts, Wim

2012-06-04

Carrier-depletion based silicon modulators with lateral and interdigitated PN junctions are compared systematically on the same fabrication platform. The interdigitated diode is shown to outperform the lateral diode in achieving a low VπLπ of 0.62 V∙cm with comparable propagation loss at the expense of a higher depletion capacitance. The low VπLπ of the interdigitated PN junction is employed to demonstrate 10 Gbit/s modulation with 7.5 dB extinction ration from a 500 µm long device whose static insertion loss is 2.8 dB. In addition, up to 40 Gbit/s modulation is demonstrated for a 3 mm long device comprising a lateral diode and a co-designed traveling wave electrode.

First results of performance tests of the newly designed Vacuum Silicon Photo Multiplier Tube (VSiPMT).

NASA Astrophysics Data System (ADS)

de Asmundis, R.; Barbarino, G.; Barbato, F. C. T.; Campajola, L.; De Rosa, G.; Fiorillo, G.; Migliozzi, P.; Mollo, C. M.; Rossi, B.; Vivolo, D.

2014-04-01

We invented (2007) the VSiPMT, a novel, high-gain, photo detector device and we publically proposed this idea in an International Conference for the first time at the 11th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD08) in Siena, triggering deep discussions on the feasibility of the device itself and on the convenience of such a solution. After several years spent in designing, evaluation, tests and eventually negotiations with some suppliers, we finally got a couple of prototypes of the Vacuum Silicon Photo Multiplier Tube (VSiPMT) made under our specifications by Hamamatsu. We present in this paper the most important results of characterization tests of the first prototypes of the VSiPMT.

Low-voltage, high-extinction-ratio, Mach-Zehnder silicon optical modulator for CMOS-compatible integration.

PubMed

Ding, Jianfeng; Chen, Hongtao; Yang, Lin; Zhang, Lei; Ji, Ruiqiang; Tian, Yonghui; Zhu, Weiwei; Lu, Yangyang; Zhou, Ping; Min, Rui

2012-01-30

We demonstrate a carrier-depletion Mach-Zehnder silicon optical modulator, which is compatible with CMOS fabrication process and works well at a low driving voltage. This is achieved by the optimization of the coplanar waveguide electrode to reduce the electrical signal transmission loss. At the same time, the velocity and impedance matching are both considered. The 12.5 Gbit/s data transmission experiment of the fabricated device with a 2-mm-long phase shifter is performed. The driving voltages with the swing amplitudes of 1 V and 2 V and the reverse bias voltages of 0.5 V and 0.8 V are applied to the device, respectively. The corresponding extinction ratios are 7.67 and 12.79 dB.

High-speed polarization-encoded quantum key distribution based on silicon photonic integrated devices

NASA Astrophysics Data System (ADS)

Bunandar, Darius; Urayama, Junji; Boynton, Nicholas; Martinez, Nicholas; Derose, Christopher; Lentine, Anthony; Davids, Paul; Camacho, Ryan; Wong, Franco; Englund, Dirk

We present a compact polarization-encoded quantum key distribution (QKD) transmitter near a 1550-nm wavelength implemented on a CMOS-compatible silicon-on-insulator photonics platform. The transmitter generates arbitrary polarization qubits at gigahertz bandwidth with an extinction ratio better than 30 dB using high-speed carrier-depletion phase modulators. We demonstrate the performance of this device by generating secret keys at a rate of 1 Mbps in a complete QKD field test. Our work shows the potential of using advanced photonic integrated circuits to enable high-speed quantum-secure communications. This work was supported by the SECANT QKD Grand Challenge, the Samsung Global Research Outreach Program, and the Air Force Office of Scientific Research.

Micromachined modulator arrays for use in free-space optical communication systems

NASA Astrophysics Data System (ADS)

Lewis, Keith L.; Ridley, Kevin D.; McNie, Mark E.; Smith, Gilbert W.; Scott, Andrew M.

2004-12-01

A summary is presented of some of the design criteria relevant to the realisation of silicon micromachined modulator arrays for use in free-space optical communication systems. Theoretical performance levels achievable are compared with values measured on experimental devices produced using a modified Multi-User MEMS Process (MUMPS). Devices capable of realising modulation rates in excess of 300 kHz are described and their optical characteristics compared with published data on devices based on multiple quantum well technology.

The study of surface acoustic wave charge transfer device

NASA Technical Reports Server (NTRS)

Papanicolaou, N.; Lin, H. C.

1978-01-01

A surface acoustic wave-charge transfer device, consisting of an n-type silicon substrate, a thermally grown silicon dioxide layer, and a sputtered film of piezoelectric zinc oxide is proposed as a means of circumventing problems associated with charge-coupled device (CCD) applications in memory, signal processing, and imaging. The proposed device creates traveling longitudinal electric fields in the silicon and replaces the multiphase clocks in CCD's. The traveling electric fields create potential wells which carry along charges stored there. These charges may be injected into the wells by light or by using a p-n junction as in conventional CCD's.

High-Performance Ultrathin Organic-Inorganic Hybrid Silicon Solar Cells via Solution-Processed Interface Modification.

PubMed

Zhang, Jie; Zhang, Yinan; Song, Tao; Shen, Xinlei; Yu, Xuegong; Lee, Shuit-Tong; Sun, Baoquan; Jia, Baohua

2017-07-05

Organic-inorganic hybrid solar cells based on n-type crystalline silicon and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) exhibited promising efficiency along with a low-cost fabrication process. In this work, ultrathin flexible silicon substrates, with a thickness as low as tens of micrometers, were employed to fabricate hybrid solar cells to reduce the use of silicon materials. To improve the light-trapping ability, nanostructures were built on the thin silicon substrates by a metal-assisted chemical etching method (MACE). However, nanostructured silicon resulted in a large amount of surface-defect states, causing detrimental charge recombination. Here, the surface was smoothed by solution-processed chemical treatment to reduce the surface/volume ratio of nanostructured silicon. Surface-charge recombination was dramatically suppressed after surface modification with a chemical, associated with improved minority charge-carrier lifetime. As a result, a power conversion efficiency of 9.1% was achieved in the flexible hybrid silicon solar cells, with a substrate thickness as low as ∼14 μm, indicating that interface engineering was essential to improve the hybrid junction quality and photovoltaic characteristics of the hybrid devices.

Integrated MEMS-based variable optical attenuator and 10Gb/s receiver

NASA Astrophysics Data System (ADS)

Aberson, James; Cusin, Pierre; Fettig, H.; Hickey, Ryan; Wylde, James

2005-03-01

MEMS devices can be successfully commercialized in favour of competing technologies only if they offer an advantage to the customer in terms of lower cost or increased functionality. There are limited markets where MEMS can be manufactured cheaper than similar technologies due to large volumes: automotive, printing technology, wireless communications, etc. However, success in the marketplace can also be realized by adding significant value to a system at minimal cost or leverging MEMS technology when other solutions simply will not work. This paper describes a thermally actuated, MEMS based, variable optical attenuator that is co-packaged with existing opto-electronic devices to develop an integrated 10Gb/s SONET/SDH receiver. The configuration of the receiver opto-electronics and relatively low voltage availability (12V max) in optical systems bar the use of LCD, EO, and electro-chromic style attenuators. The device was designed and fabricated using a silicon-on-insulator (SOI) starting material. The design and performance of the device (displacement, power consumption, reliability, physical geometry) was defined by the receiver parameters geometry. This paper will describe how these design parameters (hence final device geometry) were determined in light of both the MEMS device fabrication process and the receiver performance. Reference will be made to the design tools used and the design flow which was a joint effort between the MEMS vendor and the end customer. The SOI technology offered a robust, manufacturable solution that gave the required performance in a cost-effective process. However, the singulation of the devices required the development of a new singulation technique that allowed large volumes of silicon to be removed during fabrication yet still offer high singulation yields.

Microdynamic Devices Fabricated on Silicon-On-Sapphire Substrates.

DTIC Science & Technology

Silicon-on-sapphire substrates are provided for the fabrication of micromechanical devices, such as micromotors . The high voltage stand-off...a consequence, the electrostatically driven devices, micromotors , can be incorporated in the integrated circuits and yet be powered at elevated voltages to increase their work potential.

Integrating a dual-silicon photoelectrochemical cell into a redox flow battery for unassisted photocharging

PubMed Central

Liao, Shichao; Zong, Xu; Seger, Brian; Pedersen, Thomas; Yao, Tingting; Ding, Chunmei; Shi, Jingying; Chen, Jian; Li, Can

2016-01-01

Solar rechargeable flow cells (SRFCs) provide an attractive approach for in situ capture and storage of intermittent solar energy via photoelectrochemical regeneration of discharged redox species for electricity generation. However, overall SFRC performance is restricted by inefficient photoelectrochemical reactions. Here we report an efficient SRFC based on a dual-silicon photoelectrochemical cell and a quinone/bromine redox flow battery for in situ solar energy conversion and storage. Using narrow bandgap silicon for efficient photon collection and fast redox couples for rapid interface charge injection, our device shows an optimal solar-to-chemical conversion efficiency of ∼5.9% and an overall photon–chemical–electricity energy conversion efficiency of ∼3.2%, which, to our knowledge, outperforms previously reported SRFCs. The proposed SRFC can be self-photocharged to 0.8 V and delivers a discharge capacity of 730 mAh l−1. Our work may guide future designs for highly efficient solar rechargeable devices. PMID:27142885

Broadband electromagnetic dipole scattering by coupled multiple nanospheres

NASA Astrophysics Data System (ADS)

Jing, Xufeng; Ye, Qiufeng; Hong, Zhi; Zhu, Dongshuo; Shi, Guohua

2017-11-01

With the development of nanotechnology, the ability to manipulate light at the nanoscale is critical to future optical functional devices. The use of high refractive index dielectric single silicon nanoparticle can achieve electromagnetic dipole resonant properties. Compared with single nanosphere, the use of dimer and trimer introduces an additional dimension (gap size) for improving the performance of dielectric optical devices through the coupling between closely connected silicon nanospheres. When changing the gap size between the nanospheres, the interaction between the particles can be from weak to strong. Compared with single nanospheres, dimerized or trimeric nanospheres exhibit more pronounced broadband scattering properties. In addition, by introducing more complex interaction, the trimericed silicon nanospheres exhibit a more significant increase in bandwidth than expected. In addition, the presence of the substrate will also contribute to the increase in the bandwidth of the nanospheres. The broadband response in dielectric nanostructures can be effectively applied to broadband applications such as dielectric nanoantennas or solar cells.

Influence of polarized bias and porous silicon morphology on the electrical behavior of Au-porous silicon contacts*

PubMed Central

Zhao, Yue; Li, Dong-sheng; Xing, Shou-xiang; Yang, De-ren; Jiang, Min-hua

2005-01-01

This paper reports the surface morphology and I-V curves of porous silicon (PS) samples and related devices. The observed fabrics on the PS surface were found to affect the electrical property of PS devices. When the devices were operated under different external bias (10 V or 3 V) for 10 min, their observed obvious differences in electrical properties may be due to the different control mechanisms in the Al/PS interface and PS matrix morphology. PMID:16252350

Silicon Solar Cell Efficiency Improvement Employing the Photoluminescent, Down-Shifting Effects of Carbon and CdTe Quantum Dots (Open Access Publisher’s Version)

DTIC Science & Technology

2016-03-21

ORIGINAL PAPER Silicon solar cell efficiency improvement employing the photoluminescent, down-shifting effects of carbon and CdTe quantum dots Elias...smaller influence on solar cell performance, they are con- sidered to be a more attractive option due to their afford- ability and minimal impact in the...Photovoltaics Solar cells Introduction There is a generalized trend to demonstrate higher solar cell efficiency with more affordable devices to promote

Total Ionizing Dose Test of Microsemi's Silicon Switching Transistors JANTXV2N2222AUB and 2N2907AUB

NASA Technical Reports Server (NTRS)

Campola, M.; Freeman, B.; Yau, K.

2017-01-01

Microsemi's silicon switching transistors, JANTXV2N2222AUB and 2N2907AUB, were tested for total ionizing dose (TID) response beginning on July 11, 2016. This test served as the radiation lot acceptance test (RLAT) for the lot date code (LDC) tested. Low dose rate (LDR) irradiations were performed in this test so that the device susceptibility to enhanced low dose rate sensitivity (ELDRS) could be determined.

Ultralow crosstalk nanosecond-scale nested 2 × 2 Mach-Zehnder silicon photonic switch.

PubMed

Dupuis, Nicolas; Rylyakov, Alexander V; Schow, Clint L; Kuchta, Daniel M; Baks, Christian W; Orcutt, Jason S; Gill, Douglas M; Green, William M J; Lee, Benjamin G

2016-07-01

We present the design and characterization of a novel electro-optic silicon photonic 2×2 nested Mach-Zehnder switch monolithically integrated with a CMOS driver and interface logic. The photonic device uses a variable optical attenuator in order to balance the power inside the Mach-Zehnder interferometer leading to ultralow crosstalk performance. We measured a crosstalk as low as -34.5  dB, while achieving ∼2  dB insertion loss and 4 ns transient response.

Porous silicon carbide (SIC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Solid state laser applications in photovoltaics manufacturing

NASA Astrophysics Data System (ADS)

Dunsky, Corey; Colville, Finlay

2008-02-01

Photovoltaic energy conversion devices are on a rapidly accelerating growth path driven by increasing government and societal pressure to use renewable energy as part of an overall strategy to address global warming attributed to greenhouse gas emissions. Initially supported in several countries by generous tax subsidies, solar cell manufacturers are relentlessly pushing the performance/cost ratio of these devices in a quest to reach true cost parity with grid electricity. Clearly this eventual goal will result in further acceleration in the overall market growth. Silicon wafer based solar cells are currently the mainstay of solar end-user installations with a cost up to three times grid electricity. But next-generation technology in the form of thin-film devices promises streamlined, high-volume manufacturing and greatly reduced silicon consumption, resulting in dramatically lower per unit fabrication costs. Notwithstanding the modest conversion efficiency of thin-film devices compared to wafered silicon products (around 6-10% versus 15-20%), this cost reduction is driving existing and start-up solar manufacturers to switch to thin-film production. A key aspect of these devices is patterning large panels to create a monolithic array of series-interconnected cells to form a low current, high voltage module. This patterning is accomplished in three critical scribing processes called P1, P2, and P3. Lasers are the technology of choice for these processes, delivering the desired combination of high throughput and narrow, clean scribes. This paper examines these processes and discusses the optimization of industrial lasers to meet their specific needs.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, K.H.

1998-06-30

A method is disclosed for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates. 1 fig.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, Kurt H.

1998-01-01

A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates.

Efficient Near-Infrared-Transparent Perovskite Solar Cells Enabling Direct Comparison of 4-Terminal and Monolithic Perovskite/Silicon Tandem Cells

DOE PAGES

Werner, Jeremie; Barraud, Loris; Walter, Arnaud; ...

2016-07-30

Combining market-proven silicon solar cell technology with an efficient wide band gap top cell into a tandem device is an attractive approach to reduce the cost of photovoltaic systems. For this, perovskite solar cells are promising high-efficiency top cell candidates, but their typical device size (<0.2 cm 2), is still far from standard industrial sizes. Here, we present a 1 cm 2 near-infrared transparent perovskite solar cell with 14.5% steadystate efficiency, as compared to 16.4% on 0.25 cm 2. By mechanically stacking these cells with silicon heterojunction cells, we experimentally demonstrate a 4-terminal tandem measurement with a steady-state efficiency ofmore » 25.2%, with a 0.25 cm 2 top cell. The developed top cell processing methods enable the fabrication of a 20.5% efficient and 1.43 cm 2 large monolithic perovskite/silicon heterojunction tandem solar cell, featuring a rear-side textured bottom cell to increase its near-infrared spectral response. Finally, we compare both tandem configurations to identify efficiency-limiting factors and discuss the potential for further performance improvement.« less

Efficient Near-Infrared-Transparent Perovskite Solar Cells Enabling Direct Comparison of 4-Terminal and Monolithic Perovskite/Silicon Tandem Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Werner, Jeremie; Barraud, Loris; Walter, Arnaud

Combining market-proven silicon solar cell technology with an efficient wide band gap top cell into a tandem device is an attractive approach to reduce the cost of photovoltaic systems. For this, perovskite solar cells are promising high-efficiency top cell candidates, but their typical device size (<0.2 cm 2), is still far from standard industrial sizes. Here, we present a 1 cm 2 near-infrared transparent perovskite solar cell with 14.5% steadystate efficiency, as compared to 16.4% on 0.25 cm 2. By mechanically stacking these cells with silicon heterojunction cells, we experimentally demonstrate a 4-terminal tandem measurement with a steady-state efficiency ofmore » 25.2%, with a 0.25 cm 2 top cell. The developed top cell processing methods enable the fabrication of a 20.5% efficient and 1.43 cm 2 large monolithic perovskite/silicon heterojunction tandem solar cell, featuring a rear-side textured bottom cell to increase its near-infrared spectral response. Finally, we compare both tandem configurations to identify efficiency-limiting factors and discuss the potential for further performance improvement.« less

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

NASA Technical Reports Server (NTRS)

Kaul, Anupama; Bumble, Bruce; Lee, Karen; LeDuc, Henry; Rice, Frank; Zmuidzinas, Jonas

2005-01-01

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Label-Free Virus Capture and Release by a Microfluidic Device Integrated with Porous Silicon Nanowire Forest.

PubMed

Xia, Yiqiu; Tang, Yi; Yu, Xu; Wan, Yuan; Chen, Yizhu; Lu, Huaguang; Zheng, Si-Yang

2017-02-01

Viral diseases are perpetual threats to human and animal health. Detection and characterization of viral pathogens require accurate, sensitive, and rapid diagnostic assays. For field and clinical samples, the sample preparation procedures limit the ultimate performance and utility of the overall virus diagnostic protocols. This study presents the development of a microfluidic device embedded with porous silicon nanowire (pSiNW) forest for label-free size-based point-of-care virus capture in a continuous curved flow design. The pSiNW forests with specific interwire spacing are synthesized in situ on both bottom and sidewalls of the microchannels in a batch process. With the enhancement effect of Dean flow, this study demonstrates that about 50% H5N2 avian influenza viruses are physically trapped without device clogging. A unique feature of the device is that captured viruses can be released by inducing self-degradation of the pSiNWs in physiological aqueous environment. About 60% of captured viruses can be released within 24 h for virus culture, subsequent molecular diagnosis, and other virus characterization and analyses. This device performs viable, unbiased, and label-free virus isolation and release. It has great potentials for virus discovery, virus isolation and culture, functional studies of virus pathogenicity, transmission, drug screening, and vaccine development. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effects of Asymmetric Local Joule Heating on Silicon Nanowire-Based Devices Formed by Dielectrophoresis Alignment Across Pt Electrodes

NASA Astrophysics Data System (ADS)

Ho, Hsiang-Hsi; Lin, Chun-Lung; Tsai, Wei-Che; Hong, Liang-Zheng; Lyu, Cheng-Han; Hsu, Hsun-Feng

2018-01-01

We demonstrate the fabrication and characterization of silicon nanowire-based devices in metal-nanowire-metal configuration using direct current dielectrophoresis. The current-voltage characteristics of the devices were found rectifying, and their direction of rectification could be determined by voltage sweep direction due to the asymmetric Joule heating effect that occurred in the electrical measurement process. The photosensing properties of the rectifying devices were investigated. It reveals that when the rectifying device was in reverse-biased mode, the excellent photoresponse was achieved due to the strong built-in electric field at the junction interface. It is expected that rectifying silicon nanowire-based devices through this novel and facile method can be potentially applied to other applications such as logic gates and sensors.

In-situ microscale through-silicon via strain measurements by synchrotron x-ray microdiffraction exploring the physics behind data interpretation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Xi; School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332; Thadesar, Paragkumar A.

2014-09-15

In-situ microscale thermomechanical strain measurements have been performed in combination with synchrotron x-ray microdiffraction to understand the fundamental cause of failures in microelectronics devices with through-silicon vias. The physics behind the raster scan and data analysis of the measured strain distribution maps is explored utilizing the energies of indexed reflections from the measured data and applying them for beam intensity analysis and effective penetration depth determination. Moreover, a statistical analysis is performed for the beam intensity and strain distributions along the beam penetration path to account for the factors affecting peak search and strain refinement procedure.

Nanostructure iron-silicon thin film deposition using plasma focus device

NASA Astrophysics Data System (ADS)

Kotb, M.; Saudy, A. H.; Hassaballa, S.; Eloker, M. M.

2013-03-01

The presented study in this paper reports the deposition of nano-structure iron-silicon thin film on a glass substrate using 3.3 KJ Mather-type plasma focus device. The iron-silicon powder was put on the top of hollow copper anode electrode. The deposition was done under different experimental conditions such as numbers of electric discharge shots and angular position of substrate. The film samples were exposed to energetic argon ions generated by plasma focus device at different distances from the top of the central electrode. The exposed samples were then analyzed for their structure and optical properties using X-ray diffraction (XRD) and UV-visible spectroscopy. The structure of iron-silicon thin films deposited using plasma focus device depends on the distance from the anode, the number of focus deposition shots and the angular position of the sample

Silicon carbide, an emerging high temperature semiconductor

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony

1991-01-01

In recent years, the aerospace propulsion and space power communities have expressed a growing need for electronic devices that are capable of sustained high temperature operation. Applications for high temperature electronic devices include development instrumentation within engines, engine control, and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Other earth-based applications include deep-well drilling instrumentation, nuclear reactor instrumentation and control, and automotive sensors. To meet the needs of these applications, the High Temperature Electronics Program at the Lewis Research Center is developing silicon carbide (SiC) as a high temperature semiconductor material. Research is focussed on developing the crystal growth, characterization, and device fabrication technologies necessary to produce a family of silicon carbide electronic devices and integrated sensors. The progress made in developing silicon carbide is presented, and the challenges that lie ahead are discussed.

Silicone metalization

DOEpatents

Maghribi, Mariam N [Livermore, CA; Krulevitch, Peter [Pleasanton, CA; Hamilton, Julie [Tracy, CA

2006-12-05

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Silicone metalization

DOEpatents

Maghribi, Mariam N.; Krulevitch, Peter; Hamilton, Julie

2008-12-09

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Technology computer aided design of 29.5% efficient perovskite/interdigitated back contact silicon heterojunction mechanically stacked tandem solar cell for energy-efficient applications

NASA Astrophysics Data System (ADS)

Pandey, Rahul; Chaujar, Rishu

2017-04-01

A 29.5% efficient perovskite/SiC passivated interdigitated back contact silicon heterojunction (IBC-SiHJ) mechanically stacked tandem solar cell device has been designed and simulated. This is a substantial improvement of 40% and 15%, respectively, compared to the transparent perovskite solar cell (21.1%) and Si solar cell (25.6%) operated individually. The perovskite solar cell has been used as a top subcell, whereas 250- and 25-μm-thick IBC-SiHJ solar cells have been used as bottom subcells. The realistic technology computer aided design analysis has been performed to understand the physical processes in the device and to make reliable predictions of the behavior. The performance of the top subcell has been obtained for different acceptor densities and hole mobility in Spiro-MeOTAD along with the impact of counter electrode work function. To incorporate the effect of material quality, the influence of carrier lifetimes has also been studied for perovskite top and IBC-SiHJ bottom subcells. The optical and electrical behavior of the devices has been obtained for both standalone as well as tandem configuration. Results reported in this study reveal that the proposed four-terminal tandem device may open a new door for cost-effective and energy-efficient applications.

A 5-μm pitch charge-coupled device optimized for resonant inelastic soft X-ray scattering

NASA Astrophysics Data System (ADS)

Andresen, N. C.; Denes, P.; Goldschmidt, A.; Joseph, J.; Karcher, A.; Tindall, C. S.

2017-08-01

We have developed a charge-coupled device (CCD) with 5 μm × 45 μm pixels on high-resistivity silicon. The fully depleted 200 μm-thick silicon detector is back-illuminated through a 10 nm-thick in situ doped polysilicon window and is thus highly efficient for soft through >8 keV hard X-rays. The device described here is a 1.5 megapixel CCD with 2496 × 620 pixels. The pixel and camera geometry was optimized for Resonant Inelastic X-ray Scattering (RIXS) and is particularly advantageous for spectrometers with limited arm lengths. In this article, we describe the device architecture, construction and operation, and its performance during tests at the Advance Light Source (ALS) 8.0.1 RIXS beamline. The improved spectroscopic performance, when compared with a current standard commercial camera, is demonstrated with a ˜280 eV (CK) X-ray beam on a graphite sample. Readout noise is typically 3-6 electrons and the point spread function for soft CK X-rays in the 5 μm direction is 4.0 μm ± 0.2 μm. The measured quantum efficiency of the CCD is greater than 75% in the range from 200 eV to 1 keV.

A 5-μm pitch charge-coupled device optimized for resonant inelastic soft X-ray scattering.

PubMed

Andresen, N C; Denes, P; Goldschmidt, A; Joseph, J; Karcher, A; Tindall, C S

2017-08-01

We have developed a charge-coupled device (CCD) with 5 μm × 45 μm pixels on high-resistivity silicon. The fully depleted 200 μm-thick silicon detector is back-illuminated through a 10 nm-thick in situ doped polysilicon window and is thus highly efficient for soft through >8 keV hard X-rays. The device described here is a 1.5 megapixel CCD with 2496 × 620 pixels. The pixel and camera geometry was optimized for Resonant Inelastic X-ray Scattering (RIXS) and is particularly advantageous for spectrometers with limited arm lengths. In this article, we describe the device architecture, construction and operation, and its performance during tests at the Advance Light Source (ALS) 8.0.1 RIXS beamline. The improved spectroscopic performance, when compared with a current standard commercial camera, is demonstrated with a ∼280 eV (C K ) X-ray beam on a graphite sample. Readout noise is typically 3-6 electrons and the point spread function for soft C K X-rays in the 5 μm direction is 4.0 μm ± 0.2 μm. The measured quantum efficiency of the CCD is greater than 75% in the range from 200 eV to 1 keV.

Silicon photonic Mach Zehnder modulators for next-generation short-reach optical communication networks

NASA Astrophysics Data System (ADS)

Lacava, C.; Liu, Z.; Thomson, D.; Ke, Li; Fedeli, J. M.; Richardson, D. J.; Reed, G. T.; Petropoulos, P.

2016-02-01

Communication traffic grows relentlessly in today's networks, and with ever more machines connected to the network, this trend is set to continue for the foreseeable future. It is widely accepted that increasingly faster communications are required at the point of the end users, and consequently optical transmission plays a progressively greater role even in short- and medium-reach networks. Silicon photonic technologies are becoming increasingly attractive for such networks, due to their potential for low cost, energetically efficient, high-speed optical components. A representative example is the silicon-based optical modulator, which has been actively studied. Researchers have demonstrated silicon modulators in different types of structures, such as ring resonators or slow light based devices. These approaches have shown remarkably good performance in terms of modulation efficiency, however their operation could be severely affected by temperature drifts or fabrication errors. Mach-Zehnder modulators (MZM), on the other hand, show good performance and resilience to different environmental conditions. In this paper we present a CMOS-compatible compact silicon MZM. We study the application of the modulator to short-reach interconnects by realizing data modulation using some relevant advanced modulation formats, such as 4-level Pulse Amplitude Modulation (PAM-4) and Discrete Multi-Tone (DMT) modulation and compare the performance of the different systems in transmission.

A Silicon-Chip Source of Bright Photon-Pair Comb

DTIC Science & Technology

2012-10-16

A silicon -chip source of bright photon-pair comb Wei C. Jiang,1, ∗ Xiyuan Lu,2, ∗ Jidong Zhang,3 Oskar Painter,4 and Qiang Lin1, 3, † 1Institute of...efficient monolithic photon-pair source for on-chip application. Here we report a device on the silicon -on-insulator platform that utilizes dramatic cavity...enhanced four-wave mixing in a high-Q silicon microdisk resonator. The device is able to produce high-purity photon pairs in a comb fashion, with an

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

DTIC Science & Technology

2011-11-01

stack between the GaN and Substrate layers. The University of Bristol recently reported that this TBR in commercial devices on Silicon Carbide ( SiC ...Circuit RF Radio Frequency PA Power Amplifier SiC Silicon Carbide FEA Finite Element Analysis heff Effective Heat transfer Coefficient (W/m 2 K...substrate material switched from sapphire to silicon , and by another factor of two from silicon to SiC . TABLE 1: SAMPLE RESULTS FROM DOUGLAS ET AL. FOR

Thermally tunable silicon racetrack resonators with ultralow tuning power.

PubMed

Dong, Po; Qian, Wei; Liang, Hong; Shafiiha, Roshanak; Feng, Dazeng; Li, Guoliang; Cunningham, John E; Krishnamoorthy, Ashok V; Asghari, Mehdi

2010-09-13

We present thermally tunable silicon racetrack resonators with an ultralow tuning power of 2.4 mW per free spectral range. The use of free-standing silicon racetrack resonators with undercut structures significantly enhances the tuning efficiency, with one order of magnitude improvement of that for previously demonstrated thermo-optic devices without undercuts. The 10%-90% switching time is demonstrated to be ~170 µs. Such low-power tunable micro-resonators are particularly useful as multiplexing devices and wavelength-tunable silicon microcavity modulators.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

University of Illinois

2009-04-21

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A [Champaign, IL; Khang, Dahl-Young [Seoul, KR; Sun, Yugang [Naperville, IL; Menard, Etienne [Durham, NC

2012-06-12

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A.; Khang, Dahl-Young; Sun, Yugang; Menard, Etienne

2014-06-17

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A.; Khang, Dahl-Young; Sun, Yugang; Menard, Etienne

2016-12-06

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

DOEpatents

Rogers, John A.; Khang, Dahl -Young; Sun, Yugang; Menard, Etienne

2015-08-11

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Silicon photonics and challenges for fabrication

NASA Astrophysics Data System (ADS)

Feilchenfeld, N. B.; Nummy, K.; Barwicz, T.; Gill, D.; Kiewra, E.; Leidy, R.; Orcutt, J. S.; Rosenberg, J.; Stricker, A. D.; Whiting, C.; Ayala, J.; Cucci, B.; Dang, D.; Doan, T.; Ghosal, M.; Khater, M.; McLean, K.; Porth, B.; Sowinski, Z.; Willets, C.; Xiong, C.; Yu, C.; Yum, S.; Giewont, K.; Green, W. M. J.

2017-03-01

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

Hybrid Silicon Photonic Integration using Quantum Well Intermixing

NASA Astrophysics Data System (ADS)

Jain, Siddharth R.

With the push for faster data transfer across all domains of telecommunication, optical interconnects are transitioning into shorter range applications such as in data centers and personal computing. Silicon photonics, with its economic advantages of leveraging well-established silicon manufacturing facilities, is considered the most promising approach to further scale down the cost and size of optical interconnects for chip-to-chip communication. Intrinsic properties of silicon however limit its ability to generate and modulate light, both of which are key to realizing on-chip optical data transfer. The hybrid silicon approach directly addresses this problem by using molecularly bonded III-V epitaxial layers on silicon for optical gain and absorption. This technology includes direct transfer of III-V wafer to a pre-patterned silicon-on-insulator wafer. Several discrete devices for light generation, modulation, amplification and detection have already been demonstrated on this platform. As in the case of electronics, multiple photonic elements can be integrated on a single chip to improve performance and functionality. However, scalable photonic integration requires the ability to control the bandgap for individual devices along with design changes to simplify fabrication. In the research presented here, quantum well intermixing is used as a technique to define multiple bandgaps for integration on the hybrid silicon platform. Implantation enhanced disordering is used to generate four bandgaps spread over 120+ nm. By combining these selectively intermixed III-V layers with pre-defined gratings and waveguides on silicon, we fabricate distributed feedback, distributed Bragg reflector, Fabry-Perot and mode-locked lasers along with photodetectors, electro-absorption modulators and other test structures, all on a single chip. We demonstrate a broadband laser source with continuous-wave operational lasers over a 200 nm bandwidth. Some of these lasers are integrated with modulators with a 3-dB bandwidth above 25 GHz, thus demonstrating coarse wavelength division multiplexing transmitter on silicon.

Lifetime laser damage performance of β -Ga2O3 for high power applications

NASA Astrophysics Data System (ADS)

Yoo, Jae-Hyuck; Rafique, Subrina; Lange, Andrew; Zhao, Hongping; Elhadj, Selim

2018-03-01

Gallium oxide (Ga2O3) is an emerging wide bandgap semiconductor with potential applications in power electronics and high power optical systems where gallium nitride and silicon carbide have already demonstrated unique advantages compared to gallium arsenide and silicon-based devices. Establishing the stability and breakdown conditions of these next-generation materials is critical to assessing their potential performance in devices subjected to large electric fields. Here, using systematic laser damage performance tests, we establish that β-Ga2O3 has the highest lifetime optical damage performance of any conductive material measured to date, above 10 J/cm2 (1.4 GW/cm2). This has direct implications for its use as an active component in high power laser systems and may give insight into its utility for high-power switching applications. Both heteroepitaxial and bulk β-Ga2O3 samples were benchmarked against a heteroepitaxial gallium nitride sample, revealing an order of magnitude higher optical lifetime damage threshold for β-Ga2O3. Photoluminescence and Raman spectroscopy results suggest that the exceptional damage performance of β-Ga2O3 is due to lower absorptive defect concentrations and reduced epitaxial stress.

Flexural plate wave devices fabricated from silicon carbide membrane

NASA Astrophysics Data System (ADS)

Diagne, Ndeye Fama

Flexural Plate Wave (FPW) devices fabricated from Silicon Carbide (SiC) membranes are presented here which exhibit electrical and mechanical characteristics in its transfer functions that makes it very useful as a low voltage probe device capable of functioning in small areas that are commonly inaccessible to ordinary devices. The low input impedance characteristic of this current driven device makes it possible for it to operate at very low voltages, thereby reducing the hazards for flammable or explosive areas to be probed. The Flexural Plate Wave (FPW) devices are of a family of gravimetric type sensors that permit direct measurements of the mass of the vibrating element. The primary objective was to study the suitability of Silicon Carbide (SiC) membranes as a replacement of Silicon Nitride (SiN) membrane in flexural plate wave devices developed by Sandia National Laboratories. Fabrication of the Flexural Plate Wave devices involves the overlaying a silicon wafer with membranes of 3C-SiC thin film upon which conducting meander lines are placed. The input excitation energy is in the form of an input current. The lines of current along the direction of the conducting Meander Lines Transducer (MLTs) and the applied perpendicular external magnetic field set up a mechanical wave perpendicular to both, exciting the membrane by means of a Lorentz force, which in turn sets up flexural waves that propagate along the thin membrane. The physical dimensions, the mass density, the tension in the membrane and the meander spacing are physical characteristics that determine resonance frequency of the Flexural Plate Wave (FPW) device. Of primary interest is the determination of the resonant frequency of the silicon carbide membrane as functions of the device physical characteristic parameters. The appropriate transduction scheme with Meander Line Transducers (IDTs) are used to excite the membrane. Equivalent circuit models characterizing the reflection response S11 (amplitude and phase) for a one-port Flexural PlateWave device and the transmission response S21 of a two-port device are used for the development of the equivalent mechanical characteristics.

Nonclassical light sources for silicon photonics

NASA Astrophysics Data System (ADS)

Bajoni, Daniele; Galli, Matteo

2017-09-01

Quantum photonics has recently attracted a lot of attention for its disruptive potential in emerging technologies like quantum cryptography, quantum communication and quantum computing. Driven by the impressive development in nanofabrication technologies and nanoscale engineering, silicon photonics has rapidly become the platform of choice for on-chip integration of high performing photonic devices, now extending their functionalities towards quantum-based applications. Focusing on quantum Information Technology (qIT) as a key application area, we review recent progress in integrated silicon-based sources of nonclassical states of light. We assess the state of the art in this growing field and highlight the challenges that need to be overcome to make quantum photonics a reliable and widespread technology.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

NASA Technical Reports Server (NTRS)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Iannello, Christopher J.; Del Castillo, Linda Y.; Fitzpatrick, Fred D.; Mojarradi, Mohammad M.;

Extreme Temperature Operation of a 10 MHz Silicon Oscillator Type STCL1100

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2008-01-01

The performance of STMicroelectronics 10 MHz silicon oscillator was evaluated under exposure to extreme temperatures. The oscillator was characterized in terms of its output frequency stability, output signal rise and fall times, duty cycle, and supply current. The effects of thermal cycling and re-start capability at extreme low and high temperatures were also investigated. The silicon oscillator chip operated well with good stability in its output frequency over the temperature region of -50 C to +130 C, a range that by far exceeded its recommended specified boundaries of -20 C to +85 C. In addition, this chip, which is a low-cost oscillator designed for use in applications where great accuracy is not required, continued to function at cryogenic temperatures as low as - 195 C but at the expense of drop in its output frequency. The STCL1100 silicon oscillator was also able to re-start at both -195 C and +130 C, and it exhibited no change in performance due to the thermal cycling. In addition, no physical damage was observed in the packaging material due to extreme temperature exposure and thermal cycling. Therefore, it can be concluded that this device could potentially be used in space exploration missions under extreme temperature conditions in microprocessor and other applications where tight clock accuracy is not critical. In addition to the aforementioned screening evaluation, additional testing, however, is required to fully establish the reliability of these devices and to determine their suitability for long-term use.

Analysis and Quantification of Coupling Mechanisms of External Signal Perturbations on Silicon Detectors for Particle Physics Experiments

NASA Astrophysics Data System (ADS)

Arteche, F.; Rivetta, C.; Iglesias, M.; Echeverria, I.

2016-05-01

Silicon detectors have been used in astrophysics satellites and particle detectors for high energy physics (HEP) experiments. For HEP applications, EMC studies have been conducted in silicon detectors to characterize the impact of external noise on the system. They have shown that problems associated with the new generation of silicon detectors are related with interferences generated by the power supplies and auxiliary equipment connected to the device. Characterization of these interferences along with the coupling and their propagation into the susceptible front-end circuits is required for a successful integration of these systems. This paper presents the analysis of the sensitivity curves and coupling mechanisms between the noise and the front-end electronics that have been observed during the characterization of two silicon detector prototypes: the CMS-Silicon tracker detector (CMS-ST) and Silicon Vertex Detector (Belle II-SVD). As a result of these studies, it is possible to identify critical elements in prototypes to take corrective actions in the design and improve the front-end electronics performance.

Degradation of GaAs/AlGaAs Quantized Hall Resistors With Alloyed AuGe/Ni Contacts.

PubMed

Lee, Kevin C

1998-01-01

Careful testing over a period of 6 years of a number of GaAs/AlGaAs quantized Hall resistors (QHR) made with alloyed AuGe/Ni contacts, both with and without passivating silicon nitride coatings, has resulted in the identification of important mechanisms responsible for degradation in the performance of the devices as resistance standards. Covering the contacts with a film, such as a low-temperature silicon nitride, that is impervious to humidity and other contaminants in the atmosphere prevents the contacts from degrading. The devices coated with silicon nitride used in this study, however, showed the effects of a conducting path in parallel with the 2-dimensional electron gas (2-DEG) at temperatures above 1.1 K which interferes with their use as resistance standards. Several possible causes of this parallel conduction are evaluated. On the basis of this work, two methods are proposed for protecting QHR devices with alloyed AuGe/Ni contacts from degradation: the heterostructure can be left unpassivated, but the alloyed contacts can be completely covered with a very thick (> 3 μm) coating of gold; or the GaAs cap layer can be carefully etched away after alloying the contacts and prior to depositing a passivating silicon nitride coating over the entire sample. Of the two, the latter is more challenging to effect, but preferable because both the contacts and the heterostructure are protected from corrosion and oxidation.

Recent progress on fabrication of memristor and transistor-based neuromorphic devices for high signal processing speed with low power consumption

NASA Astrophysics Data System (ADS)

Hadiyawarman; Budiman, Faisal; Goldianto Octensi Hernowo, Detiza; Pandey, Reetu Raj; Tanaka, Hirofumi

2018-03-01

The advanced progress of electronic-based devices for artificial neural networks and recent trends in neuromorphic engineering are discussed in this review. Recent studies indicate that the memristor and transistor are two types of devices that can be implemented as neuromorphic devices. The electrical switching characteristics and physical mechanism of neuromorphic devices based on metal oxide, metal sulfide, silicon, and carbon materials are broadly covered in this review. Moreover, the switching performance comparison of several materials mentioned above are well highlighted, which would be useful for the further development of memristive devices. Recent progress in synaptic devices and the application of a switching device in the learning process is also discussed in this paper.

Dielectric Metasurface as a Platform for Spatial Mode Conversion in Nanoscale Waveguides.

PubMed

Ohana, David; Desiatov, Boris; Mazurski, Noa; Levy, Uriel

2016-12-14

We experimentally demonstrate a nanoscale mode converter that performs coupling between the first two transverse electric-like modes of a silicon-on-insulator waveguide. The device operates by introducing a nanoscale periodic perturbation in its effective refractive index along the propagation direction and a graded effective index profile along its transverse direction. The periodic perturbation provides phase matching between the modes, while the graded index profile, which is realized by the implementation of nanoscale dielectric metasurface consisting of silicon features that are etched into the waveguide taking advantage of the effective medium concept, provides the overlap between the modes. Following the device design and numerical analysis using three-dimensional finite difference time domain simulations, we have fabricated the device and characterized it by directly measuring the modal content using optical imaging microscopy. From these measurements, the mode purity is estimated to be 95% and the transmission relative to an unperturbed strip waveguide is as high as 88%. Finally, we extend this approach to accommodate for the coupling between photonic and plasmonic modes. Specifically, we design and numerically demonstrate photonic to plasmonic mode conversion in a hybrid waveguide in which photonic and surface plasmon polariton modes can be guided in the silicon core and in the silicon/metal interface, respectively. The same method can also be used for coupling between symmetric and antisymmetric plasmonic modes in metal-insulator-metal or insulator-metal-insulator structures. On the basis of the current demonstration, we believe that such nanoscale dielectric metasurface-based mode converters can now be realized and become an important building block in future nanoscale photonic and plasmonic devices. Furthermore, the demonstrated platform can be used for the implementation of other chip scale components such as splitters, combiners couplers, and more.

A strong electro-optically active lead-free ferroelectric integrated on silicon

NASA Astrophysics Data System (ADS)

Abel, Stefan; Stöferle, Thilo; Marchiori, Chiara; Rossel, Christophe; Rossell, Marta D.; Erni, Rolf; Caimi, Daniele; Sousa, Marilyne; Chelnokov, Alexei; Offrein, Bert J.; Fompeyrine, Jean

2013-04-01

The development of silicon photonics could greatly benefit from the linear electro-optical properties, absent in bulk silicon, of ferroelectric oxides, as a novel way to seamlessly connect the electrical and optical domain. Of all oxides, barium titanate exhibits one of the largest linear electro-optical coefficients, which has however not yet been explored for thin films on silicon. Here we report on the electro-optical properties of thin barium titanate films epitaxially grown on silicon substrates. We extract a large effective Pockels coefficient of reff=148 pm V-1, which is five times larger than in the current standard material for electro-optical devices, lithium niobate. We also reveal the tensor nature of the electro-optical properties, as necessary for properly designing future devices, and furthermore unambiguously demonstrate the presence of ferroelectricity. The integration of electro-optical active films on silicon could pave the way towards power-efficient, ultra-compact integrated devices, such as modulators, tuning elements and bistable switches.

InP on SOI devices for optical communication and optical network on chip

NASA Astrophysics Data System (ADS)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Nine-Year Core Study Data for Sientra's FDA-Approved Round and Shaped Implants with High-Strength Cohesive Silicone Gel.

PubMed

Stevens, W Grant; Calobrace, M Bradley; Harrington, Jennifer; Alizadeh, Kaveh; Zeidler, Kamakshi R; d'Incelli, Rosalyn C

2016-04-01

Since approval in March 2012, data on Sientra's (Santa Barbara, CA) silicone gel implants have been updated and published regularly to provide immediate visibility to the continued safety and performance of these devices. The 9 year follow-up data support the previously published data confirming the ongoing safety and efficacy of Sientra silicone gel breast implants. The authors provide updated 9 year study data for Sientra's round and shaped silicone gel breast implants. The Core Study is an ongoing 10 year study that enrolled 1788 patients with 3506 Sientra implants across four indications (primary augmentation, revision-augmentation, primary reconstruction, and revision-reconstruction). For the safety analysis, Kaplan-Meier risk rates were calculated to evaluate postoperative complications, including all breast implant-related adverse effects. For the effectiveness analyses, results were presented through 8 years as patient satisfaction scores were assessed at even years. Through 9 years, the overall risk of capsular contracture was 12.6%. Smooth devices (16.6%, 95% CI, 14.2%, 19.5%) had a statistically significantly higher rate of capsular contracture compared to textured devices (8.0%, 95% CI, 6.2%, 10.4%). Out of the 610 reoperations in 477 patients, over half of all reoperations were due to cosmetic reasons (n = 315; 51.6%). Patient satisfaction remains high through 8 years, with 90% of primary augmentation patients indicating their breast implants look natural and feel soft. The 9-year follow-up data from the ongoing Core Study of the Sientra portfolio of HSC and HSC+ silicone gel breast implants reaffirm the very strong safety profile as well as continued patient satisfaction. 2 Therapeutic. © 2016 The American Society for Aesthetic Plastic Surgery, Inc. Reprints and permission: journals.permissions@oup.com.

Packaging of silicon photonic devices: from prototypes to production

NASA Astrophysics Data System (ADS)

Morrissey, Padraic E.; Gradkowski, Kamil; Carroll, Lee; O'Brien, Peter

2018-02-01

The challenges associated with the photonic packaging of silicon devices is often underestimated and remains technically challenging. In this paper, we review some key enabling technologies that will allow us to overcome the current bottleneck in silicon photonic packaging; while also describing the recent developments in standardisation, including the establishment of PIXAPP as the worlds first open-access PIC packaging and assembly Pilot Line. These developments will allow the community to move from low volume prototype photonic packaged devices to large scale volume manufacturing, where the full commercialisation of PIC technology can be realised.

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boccard, Mathieu; Holman, Zachary C.

Amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphous silicon carbide beingmore » shown to surpass amorphous silicon for temperatures above 300 °C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boccard, Mathieu; Holman, Zachary C.

With this study, amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphousmore » silicon carbide being shown to surpass amorphous silicon for temperatures above 300°C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE PAGES

Boccard, Mathieu; Holman, Zachary C.

2015-08-14

With this study, amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphousmore » silicon carbide being shown to surpass amorphous silicon for temperatures above 300°C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Opening the band gap of graphene through silicon doping for the improved performance of graphene/GaAs heterojunction solar cells

NASA Astrophysics Data System (ADS)

Zhang, S. J.; Lin, S. S.; Li, X. Q.; Liu, X. Y.; Wu, H. A.; Xu, W. L.; Wang, P.; Wu, Z. Q.; Zhong, H. K.; Xu, Z. J.

2015-12-01

Graphene has attracted increasing interest due to its remarkable properties. However, the zero band gap of monolayered graphene limits it's further electronic and optoelectronic applications. Herein, we have synthesized monolayered silicon-doped graphene (SiG) with large surface area using a chemical vapor deposition method. Raman and X-ray photoelectron spectroscopy measurements demonstrate that the silicon atoms are doped into graphene lattice at a doping level of 2.7-4.5 at%. Electrical measurements based on a field effect transistor indicate that the band gap of graphene has been opened via silicon doping without a clear degradation in carrier mobility, and the work function of SiG, deduced from ultraviolet photoelectron spectroscopy, was 0.13-0.25 eV larger than that of graphene. Moreover, when compared with the graphene/GaAs heterostructure, SiG/GaAs exhibits an enhanced performance. The performance of 3.4% silicon doped SiG/GaAs solar cell has been improved by 33.7% on average, which was attributed to the increased barrier height and improved interface quality. Our results suggest that silicon doping can effectively engineer the band gap of monolayered graphene and SiG has great potential in optoelectronic device applications.Graphene has attracted increasing interest due to its remarkable properties. However, the zero band gap of monolayered graphene limits it's further electronic and optoelectronic applications. Herein, we have synthesized monolayered silicon-doped graphene (SiG) with large surface area using a chemical vapor deposition method. Raman and X-ray photoelectron spectroscopy measurements demonstrate that the silicon atoms are doped into graphene lattice at a doping level of 2.7-4.5 at%. Electrical measurements based on a field effect transistor indicate that the band gap of graphene has been opened via silicon doping without a clear degradation in carrier mobility, and the work function of SiG, deduced from ultraviolet photoelectron spectroscopy, was 0.13-0.25 eV larger than that of graphene. Moreover, when compared with the graphene/GaAs heterostructure, SiG/GaAs exhibits an enhanced performance. The performance of 3.4% silicon doped SiG/GaAs solar cell has been improved by 33.7% on average, which was attributed to the increased barrier height and improved interface quality. Our results suggest that silicon doping can effectively engineer the band gap of monolayered graphene and SiG has great potential in optoelectronic device applications. Electronic supplementary information (ESI) available: Synthetic process of the SiG sheet; UPS spectra of SiG and graphene; J-V curves for the SiG/GaAs and graphene/GaAs solar cells under dark conditions and AM1.5 illumination at 100 mW cm-2, respectively; Statistic PCE of SiG/GaAs solar cells with different Si doping levels; EQE of SiG/GaAs and graphene/GaAs solar cells; a comparison of the parameters between the SiG and graphene/GaAs solar cells. See DOI: 10.1039/c5nr06345k

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Development of devices for self-injection: using tribological analysis to optimize injection force

PubMed Central

Lange, Jakob; Urbanek, Leos; Burren, Stefan

2016-01-01

This article describes the use of analytical models and physical measurements to characterize and optimize the tribological behavior of pen injectors for self-administration of biopharmaceuticals. One of the main performance attributes of this kind of device is its efficiency in transmitting the external force applied by the user on to the cartridge inside the pen in order to effectuate an injection. This injection force characteristic is heavily influenced by the frictional properties of the polymeric materials employed in the mechanism. Standard friction tests are available for characterizing candidate materials, but they use geometries and conditions far removed from the actual situation inside a pen injector and thus do not always generate relevant data. A new test procedure, allowing the direct measurement of the coefficient of friction between two key parts of a pen injector mechanism using real parts under simulated use conditions, is presented. In addition to the absolute level of friction, the test method provides information on expected evolution of friction over lifetime as well as on expected consistency between individual devices. Paired with an analytical model of the pen mechanism, the frictional data allow the expected overall injection system force efficiency to be estimated. The test method and analytical model are applied to a range of polymer combinations with different kinds of lubrication. It is found that material combinations used without lubrication generally have unsatisfactory performance, that the use of silicone-based internal lubricating additives improves performance, and that the best results can be achieved with external silicone-based lubricants. Polytetrafluoroethylene-based internal lubrication and external lubrication are also evaluated but found to provide only limited benefits unless used in combination with silicone. PMID:27274319

InGaAlAsPN: A Materials System for Silicon Based Optoelectronics and Heterostructure Device Technologies

NASA Technical Reports Server (NTRS)

Broekaert, T. P. E.; Tang, S.; Wallace, R. M.; Beam, E. A., III; Duncan, W. M.; Kao, Y. -C.; Liu, H. -Y.

1995-01-01

A new material system is proposed for silicon based opto-electronic and heterostructure devices; the silicon lattice matched compositions of the (In,Ga,Al)-(As,P)N 3-5 compounds. In this nitride alloy material system, the bandgap is expected to be direct at the silicon lattice matched compositions with a bandgap range most likely to be in the infrared to visible. At lattice constants ranging between those of silicon carbide and silicon, a wider bandgap range is expected to be available and the high quality material obtained through lattice matching could enable applications such as monolithic color displays, high efficiency multi-junction solar cells, opto-electronic integrated circuits for fiber communications, and the transfer of existing 3-5 technology to silicon.

InGaN pn-junctions grown by PA-MBE: Material characterization and fabrication of nanocolumn electroluminescent devices

NASA Astrophysics Data System (ADS)

Gherasoiu, I.; Yu, K. M.; Reichertz, L.; Walukiewicz, W.

2015-09-01

PN junctions are basic building blocks of many electronic devices and their performance depends on the structural properties of the component layers and on the type and the amount of the doping impurities incorporated. Magnesium is the common p-type dopant for nitride semiconductors while silicon and more recently germanium are the n-dopants of choice. In this paper, therefore we analyze the quantitative limits for Mg and Ge incorporation on GaN and InGaN with high In content. We also discuss the challenges posed by the growth and characterization of InGaN pn-junctions and we discuss the properties of large area, long wavelength nanocolumn LEDs grown on silicon (1 1 1) by PA-MBE.

Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2010-01-01

The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics.

PubMed

Rao, Sandro; Pangallo, Giovanni; Della Corte, Francesco Giuseppe

2016-01-06

Hydrogenated amorphous silicon (a-Si:H) shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34-40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

A miniature solar device for overall water splitting consisting of series-connected spherical silicon solar cells

PubMed Central

Kageshima, Yosuke; Shinagawa, Tatsuya; Kuwata, Takaaki; Nakata, Josuke; Minegishi, Tsutomu; Takanabe, Kazuhiro; Domen, Kazunari

2016-01-01

A novel “photovoltaics (PV) + electrolyzer” concept is presented using a simple, small, and completely stand-alone non-biased device for solar-driven overall water splitting. Three or four spherical-shaped p-n junction silicon balls were successfully connected in series, named “SPHELAR.” SPHELAR possessed small projected areas of 0.20 (3PVs) and 0.26 cm2 (4PVs) and exhibited working voltages sufficient for water electrolysis. Impacts of the configuration on the PV module performance were carefully analyzed, revealing that a drastic increase in the photocurrent (≈20%) was attained by the effective utilization of a reflective sheet. Separate investigations on the electrocatalyst performance showed that non-noble metal based materials with reasonably small sizes (<0.80 cm2) exhibited substantial currents at the PV working voltage. By combining the observations of the PV characteristics, light management and electrocatalyst performance, solar-driven overall water splitting was readily achieved, reaching solar-to-hydrogen efficiencies of 7.4% (3PVs) and 6.4% (4PVs). PMID:27087266

A miniature solar device for overall water splitting consisting of series-connected spherical silicon solar cells

NASA Astrophysics Data System (ADS)

Kageshima, Yosuke; Shinagawa, Tatsuya; Kuwata, Takaaki; Nakata, Josuke; Minegishi, Tsutomu; Takanabe, Kazuhiro; Domen, Kazunari

2016-04-01

A novel “photovoltaics (PV) + electrolyzer” concept is presented using a simple, small, and completely stand-alone non-biased device for solar-driven overall water splitting. Three or four spherical-shaped p-n junction silicon balls were successfully connected in series, named “SPHELAR.” SPHELAR possessed small projected areas of 0.20 (3PVs) and 0.26 cm2 (4PVs) and exhibited working voltages sufficient for water electrolysis. Impacts of the configuration on the PV module performance were carefully analyzed, revealing that a drastic increase in the photocurrent (≈20%) was attained by the effective utilization of a reflective sheet. Separate investigations on the electrocatalyst performance showed that non-noble metal based materials with reasonably small sizes (<0.80 cm2) exhibited substantial currents at the PV working voltage. By combining the observations of the PV characteristics, light management and electrocatalyst performance, solar-driven overall water splitting was readily achieved, reaching solar-to-hydrogen efficiencies of 7.4% (3PVs) and 6.4% (4PVs).

Core-shell silicon nanowire solar cells

PubMed Central

Adachi, M. M.; Anantram, M. P.; Karim, K. S.

2013-01-01

Silicon nanowires can enhance broadband optical absorption and reduce radial carrier collection distances in solar cell devices. Arrays of disordered nanowires grown by vapor-liquid-solid method are attractive because they can be grown on low-cost substrates such as glass, and are large area compatible. Here, we experimentally demonstrate that an array of disordered silicon nanowires surrounded by a thin transparent conductive oxide has both low diffuse and specular reflection with total values as low as < 4% over a broad wavelength range of 400 nm < λ < 650 nm. These anti-reflective properties together with enhanced infrared absorption in the core-shell nanowire facilitates enhancement in external quantum efficiency using two different active shell materials: amorphous silicon and nanocrystalline silicon. As a result, the core-shell nanowire device exhibits a short-circuit current enhancement of 15% with an amorphous Si shell and 26% with a nanocrystalline Si shell compared to their corresponding planar devices. PMID:23529071

High-speed all-optical logic inverter based on stimulated Raman scattering in silicon nanocrystal.

PubMed

Sen, Mrinal; Das, Mukul K

2015-11-01

In this paper, we propose a new device architecture for an all-optical logic inverter (NOT gate), which is cascadable with a similar device. The inverter is based on stimulated Raman scattering in silicon nanocrystal waveguides, which are embedded in a silicon photonic crystal structure. The Raman response function of silicon nanocrystal is evaluated to explore the transfer characteristic of the inverter. A maximum product criterion for the noise margin is taken to analyze the cascadability of the inverter. The time domain response of the inverter, which explores successful inversion operation at 100 Gb/s, is analyzed. Propagation delay of the inverter is on the order of 5 ps, which is less than the delay in most of the electronic logic families as of today. Overall dimension of the device is around 755  μm ×15  μm, which ensures integration compatibility with the matured silicon industry.

Gold-based electrical interconnections for microelectronic devices

DOEpatents

Peterson, Kenneth A.; Garrett, Stephen E.; Reber, Cathleen A.; Watson, Robert D.

2002-01-01

A method of making an electrical interconnection from a microelectronic device to a package, comprising ball or wedge compression bonding a gold-based conductor directly to a silicon surface, such as a polysilicon bonding pad in a MEMS or IMEMS device, without using layers of aluminum or titanium disposed in-between the conductor and the silicon surface. After compression bonding, optional heating of the bond above 363 C. allows formation of a liquid gold-silicon eutectic phase containing approximately 3% (by weight) silicon, which significantly improves the bond strength by reforming and enhancing the initial compression bond. The same process can be used for improving the bond strength of Au--Ge bonds by forming a liquid Au-12Ge eutectic phase.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2010-01-01

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Germanium Based Field-Effect Transistors: Challenges and Opportunities

PubMed Central

Goley, Patrick S.; Hudait, Mantu K.

2014-01-01

The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed. PMID:28788569

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

The mid-IR silicon photonics sensor platform (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kimerling, Lionel; Hu, Juejun; Agarwal, Anuradha M.

2017-02-01

Advances in integrated silicon photonics are enabling highly connected sensor networks that offer sensitivity, selectivity and pattern recognition. Cost, performance and the evolution path of the so-called `Internet of Things' will gate the proliferation of these networks. The wavelength spectral range of 3-8um, commonly known as the mid-IR, is critical to specificity for sensors that identify materials by detection of local vibrational modes, reflectivity and thermal emission. For ubiquitous sensing applications in this regime, the sensors must move from premium to commodity level manufacturing volumes and cost. Scaling performance/cost is critically dependent on establishing a minimum set of platform attributes for point, wearable, and physical sensing. Optical sensors are ideal for non-invasive applications. Optical sensor device physics involves evanescent or intra-cavity structures for applied to concentration, interrogation and photo-catalysis functions. The ultimate utility of a platform is dependent on sample delivery/presentation modalities; system reset, recalibration and maintenance capabilities; and sensitivity and selectivity performance. The attributes and performance of a unified Glass-on-Silicon platform has shown good prospects for heterogeneous integration on materials and devices using a low cost process flow. Integrated, single mode, silicon photonic platforms offer significant performance and cost advantages, but they require discovery and qualification of new materials and process integration schemes for the mid-IR. Waveguide integrated light sources based on rare earth dopants and Ge-pumped frequency combs have promise. Optical resonators and waveguide spirals can enhance sensitivity. PbTe materials are among the best choices for a standard, waveguide integrated photodetector. Chalcogenide glasses are capable of transmitting mid-IR signals with high transparency. Integrated sensor case studies of i) high sensitivity analyte detection in solution; ii) gas sensing in air and iii) on-chip spectrometry provide good insight into the tradeoffs being made en route to ubiquitous sensor deployment in an Internet of Things.

Imaging visible light with Medipix2.

PubMed

Mac Raighne, Aaron; Brownlee, Colin; Gebert, Ulrike; Maneuski, Dzmitry; Milnes, James; O'Shea, Val; Rügheimer, Tilman K

2010-11-01

A need exists for high-speed single-photon counting optical imaging detectors. Single-photon counting high-speed detection of x rays is possible by using Medipix2 with pixelated silicon photodiodes. In this article, we report on a device that exploits the Medipix2 chip for optical imaging. The fabricated device is capable of imaging at >3000 frames/s over a 256×256 pixel matrix. The imaging performance of the detector device via the modulation transfer function is measured, and the presence of ion feedback and its degradation of the imaging properties are discussed.

Performance analysis of junction-less double Gate n-p-n impact ionization MOS transistor (JLDG n-IMOS)

NASA Astrophysics Data System (ADS)

Chauhan, Manvendra Singh; Chauhan, R. K.

2018-04-01

This paper demonstrates a Junction-less Double Gate n-p-n Impact ionization MOS transistor (JLDG n-IMOS) on a very light doped p-type silicon body. Device structure proposed in the paper is based on charge plasma concept. There is no metallurgical junctions in the proposed device and does not need any impurity doping to create the drain and source regions. Due to doping-less nature, the fabrication process is simple for JLDG n-IMOS. The double gate engineering in proposed device leads to reduction in avalanche breakdown via impact ionization, generating large number of carriers in drain-body junction, resulting high ION current, small IOFF current and great improvement in ION/IOFF ratio. The simulation and examination of the proposed device have been performed on ATLAS device simulatorsoftware.

First-principles study of the effects of Silicon doping on the Schottky barrier of TiSi2/Si interfaces

NASA Astrophysics Data System (ADS)

Wang, Han; Silva, Eduardo; West, Damien; Sun, Yiyang; Restrepo, Oscar; Zhang, Shengbai; Kota, Murali

As scaling of semiconductor devices is pursued in order to improve power efficiency, quantum effects due to the reduced dimensions on devices have become dominant factors in power, performance, and area scaling. In particular, source/drain contact resistance has become a limiting factor in the overall device power efficiency and performance. As a consequence, techniques such as heavy doping of source and drain have been explored to reduce the contact resistance, thereby shrinking the width of depletion region and lowering the Schottky barrier height. In this work, we study the relation between doping in Silicon and the Schottky barrier of a TiSi2/Si interface with first-principles calculation. Virtual Crystal Approximation (VCA) is used to calculate the average potential of the interface with varying doping concentration, while the I-V curve for the corresponding interface is calculated with a generalized one-dimensional transfer matrix method. The relation between substitutional and interstitial Boron and Phosphorus dopant near the interface, and their effect on tuning the Schottky barrier is studied. These studies provide insight to the type of doping and the effect of dopant segregation to optimize metal-semiconductor interface resistance.

Another step towards photodetector innovation: The first 1-inch industrial VSiPMT

NASA Astrophysics Data System (ADS)

Barbarino, G.; Barbato, F. C. T.; Mollo, C. M.; Nocerino, E.; Vivolo, D.; Fukasawa, A.

2018-09-01

The VSiPMT (Vacuum Silicon PhotoMultiplier Tube) is an original design for an innovative light detector we proposed with the aim to create new scientific instrumentation for future missions of exploration and observation of the universe. The idea behind this device is to replace the classical dynode chain of a photomultiplier tube with a silicon photomultiplier, the latter acting as an electron detector and amplifier. In this way we obtain a large area photodetector with an excellent photon counting, proper of the SiPMs, but with the dark noise of only one SiPM (1-inch is equivalent to ∼ 54 SiPM 3 × 3 mm2). From this point of view, the VSiPMT offers very attractive features and unprecedented performance in large area detection, such as: negligible power consumption, excellent SPE resolution, easy low-voltage-based stabilization and very good time performance. Hamamatsu realized for our group a 1-inch prototype. The results of the full characterization of the device are presented in this work.

Hybrid solar cells from MDMO-PPV and silicon nanocrystals.

PubMed

Liu, Chin-Yi; Kortshagen, Uwe R

2012-07-07

Solution-processed bulk heterojunction solar cells from silicon nanocrystals (Si NCs) and poly(3-hexylthiophene) (P3HT) have shown promising power conversion efficiencies. Here we report on an attempt to enhance the performance of Si NC-polymer hybrid solar cells by using poly[2-methoxy-5-(3',7'-dimethyloctyloxy)-1,4-phenylenevinylene] (MDMO-PPV) as a hole conductor, which is expected to yield a higher open circuit voltage than P3HT due to its lower highest occupied molecular orbital (HOMO). Bulk heterojunction solar cells consisting of 3-5 nm silicon nanocrystals (Si NCs) and poly[2-methoxy-5-(3',7'-dimethyloctyloxy)-1,4-phenylenevinylene] (MDMO-PPV) have been fabricated. The properties of the hybrid Si NC/MDMO-PPV devices were studied as a function of the Si NC/MDMO-PPV weight ratio. Cells of 58 wt% 3-5 nm Si NCs showed the best overall performance under simulated one-sun AM 1.5 global illumination (100 mW cm(-2)). Compared to composite films of Si NCs and poly(3-hexylthiophene), we indeed observed an improved open circuit voltage but a lower power conversion efficiency from the Si NC/MDMO-PPV devices. The lower efficiency of Si NC/MDMO-PPV is correlated to the lower hole mobility and narrower absorption spectrum of MDMO-PPV compared to P3HT.

Torsional bridge setup for the characterization of integrated circuits and microsensors under mechanical shear stress.

PubMed

Herrmann, M; Gieschke, P; Ruther, P; Paul, O

2011-12-01

We present a torsional bridge setup for the electro-mechanical characterization of devices integrated in the surface of silicon beams under mechanical in-plane shear stress. It is based on the application of a torsional moment to the longitudinal axis of the silicon beams, which results in a homogeneous in-plane shear stress in the beam surface. The safely applicable shear stresses span the range of ±50 MPa. Thanks to a specially designed clamping mechanism, the unintended normal stress typically stays below 2.5% of the applied shear stress. An analytical model is presented to compute the induced shear stress. Numerical computations verify the analytical results and show that the homogeneity of the shear stress is very high on the beam surface in the region of interest. Measurements with piezoresistive microsensors fabricated using a complementary metal-oxide-semiconductor process show an excellent agreement with both the computational results and comparative measurements performed on a four-point bending bridge. The electrical connection to the silicon beam is performed with standard bond wires. This ensures that minimal forces are applied to the beam by the electrical interconnection to the external instrumentation and that devices with arbitrary bond pad layout can be inserted into the setup.

High-temperature electronics

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Seng, Gary T.

1990-01-01

To meet the needs of the aerospace propulsion and space power communities, the high temperature electronics program at the Lewis Research Center is developing silicon carbide (SiC) as a high temperature semiconductor material. This program supports a major element of the Center's mission - to perform basic and developmental research aimed at improving aerospace propulsion systems. Research is focused on developing the crystal growth, characterization, and device fabrication technologies necessary to produce a family of SiC devices.

In vivo Characterization of Amorphous Silicon Carbide As a Biomaterial for Chronic Neural Interfaces

PubMed Central

Knaack, Gretchen L.; McHail, Daniel G.; Borda, German; Koo, Beomseo; Peixoto, Nathalia; Cogan, Stuart F.; Dumas, Theodore C.; Pancrazio, Joseph J.

2016-01-01

Implantable microelectrode arrays (MEAs) offer clinical promise for prosthetic devices by enabling restoration of communication and control of artificial limbs. While proof-of-concept recordings from MEAs have been promising, work in animal models demonstrates that the obtained signals degrade over time. Both material robustness and tissue response are acknowledged to have a role in device lifetime. Amorphous Silicon carbide (a-SiC), a robust material that is corrosion resistant, has emerged as an alternative encapsulation layer for implantable devices. We systematically examined the impact of a-SiC coating on Si probes by immunohistochemical characterization of key markers implicated in tissue-device response. After implantation, we performed device capture immunohistochemical labeling of neurons, astrocytes, and activated microglia/macrophages after 4 and 8 weeks of implantation. Neuron loss and microglia activation were similar between Si and a-SiC coated probes, while tissue implanted with a-SiC displayed a reduction in astrocytes adjacent to the probe. These results suggest that a-SiC has a similar biocompatibility profile as Si, and may be suitable for implantable MEA applications as a hermetic coating to prevent material degradation. PMID:27445672

Tungsten coating for improved wear resistance and reliability of microelectromechanical devices

DOEpatents

Fleming, James G.; Mani, Seethambal S.; Sniegowski, Jeffry J.; Blewer, Robert S.

2001-01-01

A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 .degree. C. in the presence of gaseous nitrogen trifluoride (NF.sub.3). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF.sub.6) at an elevated temperature, preferably about 450.degree. C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact. The present invention can be applied to many different types of MEM devices including microrelays, micromirrors and microengines. Additionally, the tungsten wear-resistant coating of the present invention can be used to enhance the hardness, wear resistance, electrical conductivity, optical reflectivity and chemical inertness of one or more semiconductor surfaces within a MEM device.

In vivo Characterization of Amorphous Silicon Carbide As a Biomaterial for Chronic Neural Interfaces.

PubMed

Knaack, Gretchen L; McHail, Daniel G; Borda, German; Koo, Beomseo; Peixoto, Nathalia; Cogan, Stuart F; Dumas, Theodore C; Pancrazio, Joseph J

2016-01-01

Implantable microelectrode arrays (MEAs) offer clinical promise for prosthetic devices by enabling restoration of communication and control of artificial limbs. While proof-of-concept recordings from MEAs have been promising, work in animal models demonstrates that the obtained signals degrade over time. Both material robustness and tissue response are acknowledged to have a role in device lifetime. Amorphous Silicon carbide (a-SiC), a robust material that is corrosion resistant, has emerged as an alternative encapsulation layer for implantable devices. We systematically examined the impact of a-SiC coating on Si probes by immunohistochemical characterization of key markers implicated in tissue-device response. After implantation, we performed device capture immunohistochemical labeling of neurons, astrocytes, and activated microglia/macrophages after 4 and 8 weeks of implantation. Neuron loss and microglia activation were similar between Si and a-SiC coated probes, while tissue implanted with a-SiC displayed a reduction in astrocytes adjacent to the probe. These results suggest that a-SiC has a similar biocompatibility profile as Si, and may be suitable for implantable MEA applications as a hermetic coating to prevent material degradation.