Process For Direct Integration Of A Thin-Film Silicon P-N Junction Diode With A Magnetic Tunnel Junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2005-08-23

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2003-01-01

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

A cochlear implant fabricated using a bulk silicon-surface micromachining process

NASA Astrophysics Data System (ADS)

Bell, Tracy Elizabeth

1999-11-01

This dissertation presents the design and fabrication of two generations of a silicon microelectrode array for use in a cochlear implant. A cochlear implant is a device that is inserted into the inner ear and uses electrical stimulation to provide sound sensations to the profoundly deaf. The first-generation silicon cochlear implant is a passive device fabricated using silicon microprobe technology developed at the University of Michigan. It contains twenty-two iridium oxide (IrO) stimulating sites that are 250 mum in diameter and spaced at 750 mum intervals. In-vivo recordings were made in guinea pig auditory cortex in response to electrical stimulation with this device, verifying its ability to electrically evoke an auditory response. Auditory thresholds as low as 78 muA were recorded. The second-generation implant is a thirty-two site, four-channel device with on-chip CMOS site-selection circuitry and integrated position sensing. It was fabricated using a novel bulk silicon surface micromachining process which was developed as a part of this dissertation work. While the use of semiconductor technology offers many advantages in fabricating cochlear implants over the methods currently used, it was felt that even further advantages could be gained by developing a new micromachining process which would allow circuitry to be distributed along the full length of the cochlear implant substrate. The new process uses electropolishing of an n+ bulk silicon sacrificial layer to undercut and release n- epitaxial silicon structures from the wafer. An extremely abrupt etch-stop between the n+ and n- silicon is obtained, with no electropolishing taking place in the n-type silicon that is doped lower than 1 x 1017 cm-3 in concentration. Lateral electropolishing rates of up to 50 mum/min were measured using this technique, allowing one millimeter-wide structures to be fully undercut in as little as 10 minutes. The new micromachining process was integrated with a standard p-well CMOS integrated circuit process to fabricate the second-generation active silicon cochlear implants.

Porous silicon carbide (SIC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Polycrystalline silicon study: Low-cost silicon refining technology prospects and semiconductor-grade polycrystalline silicon availability through 1988

NASA Technical Reports Server (NTRS)

Costogue, E. N.; Ferber, R.; Lutwack, R.; Lorenz, J. H.; Pellin, R.

1984-01-01

Photovoltaic arrays that convert solar energy into electrical energy can become a cost effective bulk energy generation alternative, provided that an adequate supply of low cost materials is available. One of the key requirements for economic photovoltaic cells is reasonably priced silicon. At present, the photovoltaic industry is dependent upon polycrystalline silicon refined by the Siemens process primarily for integrated circuits, power devices, and discrete semiconductor devices. This dependency is expected to continue until the DOE sponsored low cost silicon refining technology developments have matured to the point where they are in commercial use. The photovoltaic industry can then develop its own source of supply. Silicon material availability and market pricing projections through 1988 are updated based on data collected early in 1984. The silicon refining industry plans to meet the increasing demands of the semiconductor device and photovoltaic product industries are overviewed. In addition, the DOE sponsored technology research for producing low cost polycrystalline silicon, probabilistic cost analysis for the two most promising production processes for achieving the DOE cost goals, and the impacts of the DOE photovoltaics program silicon refining research upon the commercial polycrystalline silicon refining industry are addressed.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Atomic Scale Understanding of Poly-Si/SiO2/c-Si Passivated Contacts: Passivation Degradation Due to Metallization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aguiar, Jeffery A.; Young, David; Lee, Benjamin

2016-11-21

The key attributes for achieving high efficiency crystalline silicon solar cells include class leading developments in the ability to approach the theoretical limits of silicon solar technology (29.4% efficiency). The push for high efficiency devices is further compounded with the clear need for passivation to reduce recombination at the metal contacts. At the same time there is stringent requirement to retain the same material device quality, surface passivation, and performance characteristics following subsequent processing. The development of passivated silicon cell structures that retain active front and rear surface passivation and overall material cell quality is therefore a relevant and activemore » area of development. To address the potential outcomes of metallization on passivated silicon stack, we report on some common microstructural features of degradation due to metallization for a series of silicon device stacks. A fundamental materials understanding of the metallization process on retaining high-efficiency passivated Si devices is therefore gained over these series of results.« less

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.; Archer, Leo B.; Brown, George A.; Wallace, Robert M.

2000-01-01

An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.

Materials and processing approaches for foundry-compatible transient electronics.

PubMed

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A; Song, Enming; Yu, Xinge; Rogers, John A

2017-07-11

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for "green" electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are ( i ) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, ( ii ) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and ( iii ) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Materials and processing approaches for foundry-compatible transient electronics

NASA Astrophysics Data System (ADS)

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-07-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

A Silicon Nanocrystal Schottky Junction Solar Cell produced from Colloidal Silicon Nanocrystals

PubMed Central

2010-01-01

Solution-processed semiconductors are seen as a promising route to reducing the cost of the photovoltaic device manufacture. We are reporting a single-layer Schottky photovoltaic device that was fabricated by spin-coating intrinsic silicon nanocrystals (Si NCs) from colloidal suspension. The thin-film formation process was based on Si NCs without any ligand attachment, exchange, or removal reactions. The Schottky junction device showed a photovoltaic response with a power conversion efficiency of 0.02%, a fill factor of 0.26, short circuit-current density of 0.148 mA/cm2, and open-circuit voltage of 0.51 V. PMID:20676200

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Materials and processing approaches for foundry-compatible transient electronics

PubMed Central

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-01-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries. PMID:28652373

Development of large-area monolithically integrated silicon-film photovoltaic modules

NASA Astrophysics Data System (ADS)

Rand, J. A.; Cotter, J. E.; Ingram, A. E.; Ruffins, T. R.; Shreve, K. P.; Hall, R. B.; Barnett, A. M.

1993-06-01

This report describes work to develop Silicon-Film (trademark) Product 3 into a low-cost, stable solar cell for large-scale terrestrial power applications. The Product 3 structure is a thin (less than 100 micron) polycrystalline layer of silicon on a durable, insulating, ceramic substrate. The insulating substrate allows the silicon layer to be isolated and metallized to form a monolithically interconnected array of solar cells. High efficiency is achievable with the use of light trapping and a passivated back surface. The long-term goal for the product is a 1200 sq cm, 18%-efficient, monolithic array. The short-term objectives are to improve material quality and to fabricate 100 sq cm monolithically interconnected solar cell arrays. Low minority-carrier diffusion length in the silicon film and series resistance in the interconnected device structure are presently limiting device performance. Material quality is continually improving through reduced impurity contamination. Metallization schemes, such as a solder-dipped interconnection process, have been developed that will allow low-cost production processing and minimize R(sub s) effects. Test data for a nine-cell device (16 sq cm) indicated a V(sub oc) of 3.72 V. These first-reported monolithically interconnected multicrystalline silicon-on-ceramic devices show low shunt conductance (less than 0.1 mA/sq cm) due to limited conduction through the ceramic and no process-related metallization shunts.

Porous silicon carbide (SiC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Cleaning up Silicon

NASA Technical Reports Server (NTRS)

2000-01-01

A development program that started in 1975 between Union Carbide and JPL, led to Advanced Silicon Materials LLC's, formerly ASiMI, commercial process for producing silane in viable quantities. The process was expanded to include the production of high-purity polysilicon for electronic devices. The technology came out of JPL's Low Cost Silicon Array Project.

The study of surface acoustic wave charge transfer device

NASA Technical Reports Server (NTRS)

Papanicolaou, N.; Lin, H. C.

1978-01-01

A surface acoustic wave-charge transfer device, consisting of an n-type silicon substrate, a thermally grown silicon dioxide layer, and a sputtered film of piezoelectric zinc oxide is proposed as a means of circumventing problems associated with charge-coupled device (CCD) applications in memory, signal processing, and imaging. The proposed device creates traveling longitudinal electric fields in the silicon and replaces the multiphase clocks in CCD's. The traveling electric fields create potential wells which carry along charges stored there. These charges may be injected into the wells by light or by using a p-n junction as in conventional CCD's.

HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

NASA Astrophysics Data System (ADS)

Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

2000-08-01

Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

Crystal growth for high-efficiency silicon solar cells workshop: Summary

NASA Technical Reports Server (NTRS)

Dumas, K. A.

1985-01-01

The state of the art in the growth of silicon crystals for high-efficiency solar cells are reviewed, sheet requirements are defined, and furture areas of research are identified. Silicon sheet material characteristics that limit cell efficiencies and yields were described as well as the criteria for the ideal sheet-growth method. The device engineers wish list to the material engineer included: silicon sheet with long minority carrier lifetime that is uniform throughout the sheet, and which doesn't change during processing; and sheet material that stays flat throughout device processing, has uniform good mechanical strength, and is low cost. Impurities in silicon solar cells depreciate cell performance by reducing diffusion length and degrading junctions. The impurity behavior, degradation mechanisms, and variations in degradation threshold with diffusion length for silicon solar cells were described.

Passively aligned multichannel fiber-pigtailing of planar integrated optical waveguides

NASA Astrophysics Data System (ADS)

Kremmel, Johannes; Lamprecht, Tobias; Crameri, Nino; Michler, Markus

2017-02-01

A silicon device to simplify the coupling of multiple single-mode fibers to embedded single-mode waveguides has been developed. The silicon device features alignment structures that enable a passive alignment of fibers to integrated waveguides. For passive alignment, precisely machined V-grooves on a silicon device are used and the planar lightwave circuit board features high-precision structures acting as a mechanical stop. The approach has been tested for up to eight fiber-to-waveguide connections. The alignment approach, the design, and the fabrication of the silicon device as well as the assembly process are presented. The characterization of the fiber-to-waveguide link reveals total coupling losses of (0.45±0.20 dB) per coupling interface, which is significantly lower than the values reported in earlier works. Subsequent climate tests reveal that the coupling losses remain stable during thermal cycling but increases significantly during an 85°C/85 Rh-test. All applied fabrication and bonding steps have been performed using standard MOEMS fabrication and packaging processes.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2011-06-08

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Memory device using movement of protons

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Fleetwood, D.M.; Devine, R.A.B.

1998-11-03

An electrically written memory element is disclosed utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element. 19 figs.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

1998-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

2000-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

THz-wave generation via difference frequency mixing in strained silicon based waveguide utilizing its second order susceptibility χ((2)).

PubMed

Saito, Kyosuke; Tanabe, Tadao; Oyama, Yutaka

2014-07-14

Terahertz (THz) wave generation via difference frequency mixing (DFM) process in strain silicon membrane waveguides by introducing the straining layer is theoretically investigated. The Si(3)N(4) straining layer induces anisotropic compressive strain in the silicon core and results in the appearance of the bulk second order nonlinear susceptibility χ((2)) by breaking the crystal symmetry. We have proposed waveguide structures for THz wave generation under the DFM process by .using the modal birefringence in the waveguide core. Our simulations show that an output power of up to 0.95 mW can be achieved at 9.09 THz. The strained silicon optical device may open a widow in the field of the silicon-based active THz photonic device applications.

Porous silicon structures with high surface area/specific pore size

DOEpatents

Northrup, M.A.; Yu, C.M.; Raley, N.F.

1999-03-16

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gases in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters. 9 figs.

Porous silicon structures with high surface area/specific pore size

DOEpatents

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

A static induction device manufactured by silicon direct bonding

NASA Astrophysics Data System (ADS)

Chen, Xin'an; Liu, Su; Huang, Qing'an

2004-07-01

It is always a key problem how to improve the gate-source breakdown voltage (VGK) of static induction devices during manufacturing. By using a silicon direct bonding process to replace the high resistivity epitaxy process, a bonding buried gate structure is formed, which is different from an epitaxy buried gate structure. The new structure can improve the gate-source breakdown voltage from the process and the structure. It is shown that the bonding buried gate structure is a promising structure, that can improve the VGK and other performances of devices, by manufacture of a static induction thyristor.

Development of Si(1-x)Ge(x) technology for microwave sensing applications

NASA Technical Reports Server (NTRS)

Mena, Rafael A.; Taub, Susan R.; Alterovitz, Samuel A.; Young, Paul E.; Simons, Rainee N.; Rosenfeld, David

1993-01-01

The progress for the first year of the work done under the Director's Discretionary Fund (DDF) research project entitled, 'Development of Si(1-x)Ge(x) Technology for Microwave Sensing Applications.' This project includes basic material characterization studies of silicon-germanium (SiGe), device processing on both silicon (Si) and SiGe substrates, and microwave characterization of transmission lines on silicon substrates. The material characterization studies consisted of ellipsometric and magneto-transport measurements and theoretical calculations of the SiGe band-structure. The device fabrication efforts consisted of establishing SiGe device processing capabilities in the Lewis cleanroom. The characterization of microwave transmission lines included studying the losses of various coplanar transmission lines and the development of transitions on silicon. Each part of the project is discussed individually and the findings for each part are presented. Future directions are also discussed.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Accomplishments include the determination of the reasons for differences in measurements of transistor delay time, identification of an energy level model for gold-doped silicon, and the finding of evidence that it does not appear to be necessary for an ultrasonic bonding tool to grip the wire and move it across the substrate metallization to make the bond. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; measurement of thermal properties of semiconductor devices, delay time, and related carrier transport properties in junction devices, and noise properties of microwave diodes; and characterization of silicon nuclear radiation detectors.

Ion implantation reduces radiation sensitivity of metal oxide silicon /MOS/ devices

NASA Technical Reports Server (NTRS)

1971-01-01

Implanting nitrogen ions improves hardening of silicon oxides 30 percent to 60 percent against ionizing radiation effects. Process reduces sensitivity, but retains stability normally shown by interfaces between silicon and thermally grown oxides.

Silicon-on-ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Whitehead, A. B.; Zook, J. D.; Grung, B. L.; Heaps, J. D.; Schmit, F.; Schuldt, S. B.; Chapman, P. W.

1981-01-01

The technical feasibility of producing solar cell quality sheet silicon to meet the DOE 1986 cost goal of 70 cents/watt was investigated. The silicon on ceramic approach is to coat a low cost ceramic substrate with large grain polycrystalline silicon by unidirectional solidification of molten silicon. Results and accomplishments are summarized.

Alternative process for thin layer etching: Application to nitride spacer etching stopping on silicon germanium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Posseme, N., E-mail: nicolas.posseme@cea.fr; Pollet, O.; Barnola, S.

2014-08-04

Silicon nitride spacer etching realization is considered today as one of the most challenging of the etch process for the new devices realization. For this step, the atomic etch precision to stop on silicon or silicon germanium with a perfect anisotropy (no foot formation) is required. The situation is that none of the current plasma technologies can meet all these requirements. To overcome these issues and meet the highly complex requirements imposed by device fabrication processes, we recently proposed an alternative etching process to the current plasma etch chemistries. This process is based on thin film modification by light ionsmore » implantation followed by a selective removal of the modified layer with respect to the non-modified material. In this Letter, we demonstrate the benefit of this alternative etch method in term of film damage control (silicon germanium recess obtained is less than 6 A), anisotropy (no foot formation), and its compatibility with other integration steps like epitaxial. The etch mechanisms of this approach are also addressed.« less

Multiple wavelength silicon photonic 200 mm R+D platform for 25Gb/s and above applications

NASA Astrophysics Data System (ADS)

Szelag, B.; Blampey, B.; Ferrotti, T.; Reboud, V.; Hassan, K.; Malhouitre, S.; Grand, G.; Fowler, D.; Brision, S.; Bria, T.; Rabillé, G.; Brianceau, P.; Hartmann, J. M.; Hugues, V.; Myko, A.; Elleboode, F.; Gays, F.; Fédéli, J. M.; Kopp, C.

2016-05-01

A silicon photonics platform that uses a CMOS foundry line is described. Fabrication process is following a modular integration scheme which leads to a flexible platform, allowing different device combinations. A complete device library is demonstrated for 1310 nm applications with state of the art performances. A PDK which includes specific photonic features and which is compatible with commercial EDA tools has been developed allowing an MPW shuttle service. Finally platform evolutions such as device offer extension to 1550 nm or new process modules introduction are presented.

Polymer taper bridge for silicon waveguide to single mode waveguide coupling

NASA Astrophysics Data System (ADS)

Kruse, Kevin; Middlebrook, Christopher T.

2016-03-01

Coupling of optical power from high-density silicon waveguides to silica optical fibers for signal routing can incur high losses and often requires complex end-face preparation/processing. Novel coupling device taper structures are proposed for low coupling loss between silicon photonic waveguides and single mode fibers are proposed and devices are fabricated and measured in terms of performance. Theoretical mode conversion models for waveguide tapers are derived for optimal device structure design and performance. Commercially viable vertical and multi-layer taper designs using polymer waveguide materials are proposed as innovative, cost-efficient, and mass-manufacturable optical coupling devices. The coupling efficiency for both designs is determined to evaluate optimal device dimensions and alignment tolerances with both silicon rib waveguides and silicon nanowire waveguides. Propagation loss as a function of waveguide roughness and metallic loss are determined and correlated to waveguide dimensions to obtain total insertion loss for the proposed taper designs. Multi-layer tapers on gold-sputtered substrates are fabricated through photolithography as proof-of-concept devices and evaluated for device loss optimization. Tapered waveguide coupling loss with Si WGs (2.74 dB) was experimentally measured with high correlation to theoretical results.

Effects of Asymmetric Local Joule Heating on Silicon Nanowire-Based Devices Formed by Dielectrophoresis Alignment Across Pt Electrodes

NASA Astrophysics Data System (ADS)

Ho, Hsiang-Hsi; Lin, Chun-Lung; Tsai, Wei-Che; Hong, Liang-Zheng; Lyu, Cheng-Han; Hsu, Hsun-Feng

2018-01-01

We demonstrate the fabrication and characterization of silicon nanowire-based devices in metal-nanowire-metal configuration using direct current dielectrophoresis. The current-voltage characteristics of the devices were found rectifying, and their direction of rectification could be determined by voltage sweep direction due to the asymmetric Joule heating effect that occurred in the electrical measurement process. The photosensing properties of the rectifying devices were investigated. It reveals that when the rectifying device was in reverse-biased mode, the excellent photoresponse was achieved due to the strong built-in electric field at the junction interface. It is expected that rectifying silicon nanowire-based devices through this novel and facile method can be potentially applied to other applications such as logic gates and sensors.

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

PubMed Central

Hazut, Ori; Agarwala, Arunava; Subramani, Thangavel; Waichman, Sharon; Yerushalmi, Roie

2013-01-01

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms. In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station. PMID:24326774

Top-Down Nanofabrication and Characterization of 20 nm Silicon Nanowires for Biosensing Applications

PubMed Central

M. N, M. Nuzaihan; Hashim, U.; Md Arshad, M. K.; Ruslinda, A. Rahim; Rahman, S. F. A.; Fathil, M. F. M.; Ismail, Mohd. H.

2016-01-01

A top-down nanofabrication approach is used to develop silicon nanowires from silicon-on-insulator (SOI) wafers and involves direct-write electron beam lithography (EBL), inductively coupled plasma-reactive ion etching (ICP-RIE) and a size reduction process. To achieve nanometer scale size, the crucial factors contributing to the EBL and size reduction processes are highlighted. The resulting silicon nanowires, which are 20 nm in width and 30 nm in height (with a triangular shape) and have a straight structure over the length of 400 μm, are fabricated precisely at the designed location on the device. The device is applied in biomolecule detection based on the changes in drain current (Ids), electrical resistance and conductance of the silicon nanowires upon hybridization to complementary target deoxyribonucleic acid (DNA). In this context, the scaled-down device exhibited superior performances in terms of good specificity and high sensitivity, with a limit of detection (LOD) of 10 fM, enables for efficient label-free, direct and higher-accuracy DNA molecules detection. Thus, this silicon nanowire can be used as an improved transducer and serves as novel biosensor for future biomedical diagnostic applications. PMID:27022732

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Silicon nanowire biologically sensitive field effect transistors: electrical characteristics and applications.

PubMed

Rim, Taiuk; Baek, Chang-Ki; Kim, Kihyun; Jeong, Yoon-Ha; Lee, Jeong-Soo; Meyyappan, M

2014-01-01

The interest in biologically sensitive field effect transistors (BioFETs) is growing explosively due to their potential as biosensors in biomedical, environmental monitoring and security applications. Recently, adoption of silicon nanowires in BioFETs has enabled enhancement of sensitivity, device miniaturization, decreasing power consumption and emerging applications such as the 3D cell probe. In this review, we describe the device physics and operation of the silicon nanowire BioFETs along with recent advances in the field. The silicon nanowire BioFETs are basically the same as the conventional field-effect transistors (FETs) with the exceptions of nanowire channel instead of thin film and a liquid gate instead of the conventional gate. Therefore, the silicon device physics is important to understand the operation of the BioFETs. Herein, physical characteristics of the silicon nanowire FETs are described and the operational principles of the BioFETs are classified according to the number of gates and the analysis domain of the measured signal. Even the bottom-up process has merits on low-cost fabrication; the top-down process technique is highlighted here due to its reliability and reproducibility. Finally, recent advances in the silicon nanowire BioFETs in the literature are described and key features for commercialization are discussed.

High-sensitivity silicon nanowire phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Dan, Yaping

2014-08-01

Silicon nanowires (SiNWs) have emerged as a promising material for high-sensitivity photodetection in the UV, visible and near-infrared spectral ranges. In this work, we demonstrate novel planar SiNW phototransistors on silicon-oninsulator (SOI) substrate using CMOS-compatible processes. The device consists of a bipolar transistor structure with an optically-injected base region. The electronic and optical properties of the SiNW phototransistors are investigated. Preliminary simulation and experimental results show that nanowire geometry, doping densities and surface states have considerable effects on the device performance, and that a device with optimized parameters can potentially outperform conventional Si photodetectors.

Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Gu, Jian

This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at pattern center is observed due to substrate enhanced edge heating. Single-grain silicon is obtained in a 50 nm x 100 nm rectangular pattern by super lateral growth (SLG). Narrow lines (such as 20-nm-wide) can serve as artificial heterogeneous nucleation sites during crystallization of large patterns, which could lead to the formation of single-crystal silicon islands in a controlled fashion. In addition to eximer laser annealing, NanoPAtterning and nickel-induced lateral C&barbelow;rystallization (NanoPAC) of a-Si lines is presented. Single-crystal silicon is achieved by NanoPAC. The line width of a-Si affects the grain structure of crystallized silicon lines significantly. Statistics show that single-crystal silicon is formed for all lines with width between 50 nm to 200 nm. Using in situ transmission electron microscopy (TEM), nickel-induced lateral crystallization (Ni-ILC) of a-Si inside a pattern is revealed; lithography-constrained single seeding (LISS) is proposed to explain the single-crystal formation. Intragrain line and two-dimensional defects are also studied. To test the electrical properties of NanoPAC silicon films, sub-100 nm thin-film transistors (TFTs) are fabricated using Patten-controlled crystallization of Ṯhin a-Si channel layer and H&barbelow;igh temperature (850°C) annealing, coined PaTH process. PaTH TFTs show excellent device performance over traditional solid phase crystallized (SPC) TFTs in terms of threshold voltage, threshold voltage roll-off, leakage current, subthreshold swing, on/off current ratio, device-to-device uniformity etc. Two-dimensional device simulations show that PaTH TFTs are comparable to silicon-on-insulator (SOI) devices, making it a promising candidate for the fabrication of future high performance, low-power 3D integrated circuits. Finally, an ultrafast nanolithography technique, laser-assisted direct imprint (LADI) is introduced. LADI shows the ability of patterning nanostructures directly in silicon in nanoseconds with sub-10 nm resolution. The process has potential applications in multiple disciplines, and could be extended to other materials and processes.

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology.

PubMed

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-12-03

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm(2), and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p(+-)n homojunction through the formation of re-grown crystalline silicon layer (~5-10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method.

Lithographic fabrication of nanoapertures

DOEpatents

Fleming, James G.

2003-01-01

A new class of silicon-based lithographically defined nanoapertures and processes for their fabrication using conventional silicon microprocessing technology have been invented. The new ability to create and control such structures should significantly extend our ability to design and implement chemically selective devices and processes.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Gold-based electrical interconnections for microelectronic devices

DOEpatents

Peterson, Kenneth A.; Garrett, Stephen E.; Reber, Cathleen A.; Watson, Robert D.

2002-01-01

A method of making an electrical interconnection from a microelectronic device to a package, comprising ball or wedge compression bonding a gold-based conductor directly to a silicon surface, such as a polysilicon bonding pad in a MEMS or IMEMS device, without using layers of aluminum or titanium disposed in-between the conductor and the silicon surface. After compression bonding, optional heating of the bond above 363 C. allows formation of a liquid gold-silicon eutectic phase containing approximately 3% (by weight) silicon, which significantly improves the bond strength by reforming and enhancing the initial compression bond. The same process can be used for improving the bond strength of Au--Ge bonds by forming a liquid Au-12Ge eutectic phase.

Effect of ultraviolet illumination and ambient gases on the photoluminescence and electrical properties of nanoporous silicon layer for organic vapor sensor.

PubMed

Atiwongsangthong, Narin

2012-08-01

The purpose of this research, the nanoporous silicon layer were fabricated and investigated the physical properties such as photoluminescence and the electrical properties in order to develop organic vapor sensor by using nanoporous silicon. The Changes in the photoluminescence intensity of nanoporous silicon samples are studied during ultraviolet illumination in various ambient gases such as nitrogen, oxigen and vacuum. In this paper, the nanoporous silicon layer was used as organic vapor adsorption and sensing element. The advantage of this device are simple process compatible in silicon technology and usable in room temperature. The structure of this device consists of nanoporous silicon layer which is formed by anodization of silicon wafer in hydrofluoric acid solution and aluminum electrode which deposited on the top of nanoporous silicon layer by evaporator. The nanoporous silicon sensors were placed in a gas chamber with various organic vapor such as ethanol, methanol and isopropyl alcohol. From studying on electrical characteristics of this device, it is found that the nanoporous silicon layer can detect the different organic vapor. Therefore, the nanoporous silicon is important material for organic vapor sensor and it can develop to other applications about gas sensors in the future.

Increasing Stabilized Performance Of Amorphous Silicon Based Devices Produced By Highly Hydrogen Diluted Lower Temperature Plasma Deposition.

DOEpatents

Li, Yaun-Min; Bennett, Murray S.; Yang, Liyou

1999-08-24

High quality, stable photovoltaic and electronic amorphous silicon devices which effectively resist light-induced degradation and current-induced degradation, are produced by a special plasma deposition process. Powerful, efficient single and multi-junction solar cells with high open circuit voltages and fill factors and with wider bandgaps, can be economically fabricated by the special plasma deposition process. The preferred process includes relatively low temperature, high pressure, glow discharge of silane in the presence of a high concentration of hydrogen gas.

Increased Stabilized Performance Of Amorphous Silicon Based Devices Produced By Highly Hydrogen Diluted Lower Temperature Plasma Deposition.

DOEpatents

Li, Yaun-Min; Bennett, Murray S.; Yang, Liyou

1997-07-08

High quality, stable photovoltaic and electronic amorphous silicon devices which effectively resist light-induced degradation and current-induced degradation, are produced by a special plasma deposition process. Powerful, efficient single and multi-junction solar cells with high open circuit voltages and fill factors and with wider bandgaps, can be economically fabricated by the special plasma deposition process. The preferred process includes relatively low temperature, high pressure, glow discharge of silane in the presence of a high concentration of hydrogen gas.

Plastic-Syringe Induced Silicone Contamination in Organic Photvoltaic Fabrication: Implications for Small-Volume Additives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carr, John A.; Nalwa, Kanwar S.; Mahadevapuram, Rakesh

Herein, the implications of silicone contamination found in solution-processed conjugated polymer solar cells are explored. Similar to a previous work based on molecular cells, we find this contamination as a result of the use of plastic syringes during fabrication. However, in contrast to the molecular case, we find that glass-syringe fabricated devices give superior performance than plastic-syringe fabricated devices in poly(3-hexylthiophene)-based cells. We find that the unintentional silicone addition alters the solution’s wettability, which translates to a thinner, less absorbent film on spinning. With many groups studying the effects of small-volume additives, this work should be closely considered as manymore » of these additives may also directly alter the solutions’ wettability, or the amount of silicone dissolved off the plastic syringes, or both. Thereby, film thickness, which generally is not reported in detail, can vary significantly from device to device.« less

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Design and fabrication of MEMS devices using the integration of MUMPs, trench-refilled molding, DRIE and bulk silicon etching processes

NASA Astrophysics Data System (ADS)

Wu, Mingching; Fang, Weileun

2005-03-01

This work integrates multi-depth DRIE etching, trench-refilled molding, two poly-Si layers MUMPs and bulk releasing to improve the variety and performance of MEMS devices. In summary, the present fabrication process, named MOSBE II, has three merits. First, this process can monolithically fabricate and integrate poly-Si thin-film structures with different thicknesses and stiffnesses, such as the flexible spring and the stiff mirror plate. Second, multi-depth structures, such as vertical comb electrodes, are available from the DRIE processes. Third, a cavity under the micromachined device is provided by the bulk silicon etching process, so that a large out-of-plane motion is allowed. In application, an optical scanner driven by the self-aligned vertical comb actuator was demonstrated. The poly-Si micromachined components fabricated by MOSBE II can further integrate with the MUMPs devices to establish a more powerful MOEMS platform.

Fluidized-Bed Cleaning of Silicon Particles

NASA Technical Reports Server (NTRS)

Rohatgi, Naresh K.; Hsu, George C.

1987-01-01

Fluidized-bed chemical cleaning process developed to remove metallic impurities from small silicon particles. Particles (250 micrometer in size) utilized as seed material in silane pyrolysis process for production of 1-mm-size silicon. Product silicon (1 mm in size) used as raw material for fabrication of solar cells and other semiconductor devices. Principal cleaning step is wash in mixture of hydrochloric and nitric acids, leaching out metals and carrying them away as soluble chlorides. Particles fluidized by cleaning solution to assure good mixing and uniform wetting.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

NASA Astrophysics Data System (ADS)

Bisadi, Zahra; Acerbi, Fabio; Fontana, Giorgio; Zorzi, Nicola; Piemonte, Claudio; Pucker, Georg; Pavesi, Lorenzo

2018-02-01

A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED) coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST) suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology

PubMed Central

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-01-01

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm2, and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p+−n homojunction through the formation of re-grown crystalline silicon layer (~5–10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method. PMID:26632759

Thermal ink-jet device using single-chip silicon microchannels

NASA Astrophysics Data System (ADS)

Wuu, DongSing; Cheng, Chen-Yue; Horng, RayHua; Chan, G. C.; Chiu, Sao-Ling; Wu, Yi-Yung

1998-06-01

We present a new method to fabricate silicon microfluidic channels by through-hole etching with subsequent planarization. The method is based on etching out the deep grooves through a perforated silicon carbide membrane, followed by sealing the membrane with plasma-enhanced chemical vapor deposition (PECVD). Low-pressure-chemical-vapor- deposited (LPCVD) polysilicon was used as a sacrificial layer to define the channel structure and only one etching step is required. This permits the realization of planarization after a very deep etching step in silicon and offers the possibility for film deposition, resist spinning and film patterning across deep grooves. The process technology was demonstrated on the fabrication of a monolithic silicon microchannel structure for thermal inkjet printing. The Ta-Al heater arrays are integrated on the top of each microchannel, which connect to a common on-chip front-end ink reservoir. The fabrication of this device requires six masks and no active nozzle-to-chip alignment. Moreover, the present micromachining process is compatible with the addition of on-chip circuitry for multiplexing the heater control signals. Heat transfer efficiency to the ink is enhanced by the high thermal conductivity of the silicon carbide in the channel ceiling, while the bulk silicon maintains high interchannel isolation. The fabricated inkjet devices show the droplet sizes of 20 - 50 micrometer in diameter with various channel dimensions and stable ejection of ink droplets more than 1 million.

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

NASA Technical Reports Server (NTRS)

Kaul, Anupama; Bumble, Bruce; Lee, Karen; LeDuc, Henry; Rice, Frank; Zmuidzinas, Jonas

2005-01-01

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Significant accomplishments during this reporting period include design of a plan to provide standard silicon wafers for four-probe resistivity measurements for the industry, publication of a summary report on the photoconductive decay method for measuring carrier lifetime, publication of a comprehensive review of the field of wire bond fabrication and testing, and successful completion of organizational activity leading to the establishment of a new group on quality and hardness assurance in ASTM Committee F-1 on Electronics. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers in silicon; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

Graded junction termination extensions for electronic devices

NASA Technical Reports Server (NTRS)

Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

2006-01-01

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Graded junction termination extensions for electronic devices

NASA Technical Reports Server (NTRS)

Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

2007-01-01

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Proton exchange membrane micro fuel cells on 3D porous silicon gas diffusion layers

NASA Astrophysics Data System (ADS)

Kouassi, S.; Gautier, G.; Thery, J.; Desplobain, S.; Borella, M.; Ventura, L.; Laurent, J.-Y.

2012-10-01

Since the 90's, porous silicon has been studied and implemented in many devices, especially in MEMS technology. In this article, we present a new approach to build miniaturized proton exchange membrane micro-fuel cells using porous silicon as a hydrogen diffusion layer. In particular, we propose an innovative process to build micro fuel cells from a “corrugated iron like” 3D structured porous silicon substrates. This structure is able to increase up to 40% the cell area keeping a constant footprint on the silicon wafer. We propose here a process route to perform electrochemically 3D porous gas diffusion layers and to deposit fuel cell active layers on such substrates. The prototype peak power performance was measured to be 90 mW cm-2 in a “breathing configuration” at room temperature. These performances are less than expected if we compare with a reference 2D micro fuel cell. Actually, the active layer deposition processes are not fully optimized but this prototype demonstrates the feasibility of these 3D devices.

Silicon insulator-based dielectrophoresis devices for minimized heating effects.

PubMed

Zellner, Phillip; Agah, Masoud

2012-08-01

Concentration of biological specimens that are extremely dilute in a solution is of paramount importance for their detection. Microfluidic chips based on insulator-based DEP (iDEP) have been used to selectively concentrate bacteria and viruses. iDEP biochips are currently fabricated with glass or polymer substrates to allow for high electric fields within the channels. Joule heating is a well-known problem in these substrates and can lead to decreased throughput and even device failure. In this work, we present, for the first time, highly efficient trapping and separation of particles in DC iDEP devices that are fabricated on silicon using a single-etch-step three-dimensional microfabrication process with greatly improved heat dissipation properties. Fabrication in silicon allows for greater heat dissipation for identical geometries and operating conditions. The 3D fabrication allows for higher performance at lower applied potentials. Thermal measurements were performed on both the presented silicon chips and previously published PDMS devices comprised of microposts. Trapping and separation of 1 and 2 μm polystyrene particles was demonstrated. These results demonstrate the feasibility of high-performance silicon iDEP devices for the next generation of sorting and concentration microsystems. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Simple processing of back-contacted silicon heterojunction solar cells using selective-area crystalline growth

NASA Astrophysics Data System (ADS)

Tomasi, Andrea; Paviet-Salomon, Bertrand; Jeangros, Quentin; Haschke, Jan; Christmann, Gabriel; Barraud, Loris; Descoeudres, Antoine; Seif, Johannes Peter; Nicolay, Sylvain; Despeisse, Matthieu; de Wolf, Stefaan; Ballif, Christophe

2017-04-01

For crystalline-silicon solar cells, voltages close to the theoretical limit are nowadays readily achievable when using passivating contacts. Conversely, maximal current generation requires the integration of the electron and hole contacts at the back of the solar cell to liberate its front from any shadowing loss. Recently, the world-record efficiency for crystalline-silicon single-junction solar cells was achieved by merging these two approaches in a single device; however, the complexity of fabricating this class of devices raises concerns about their commercial potential. Here we show a contacting method that substantially simplifies the architecture and fabrication of back-contacted silicon solar cells. We exploit the surface-dependent growth of silicon thin films, deposited by plasma processes, to eliminate the patterning of one of the doped carrier-collecting layers. Then, using only one alignment step for electrode definition, we fabricate a proof-of-concept 9-cm2 tunnel-interdigitated back-contact solar cell with a certified conversion efficiency >22.5%.

Proceedings of the Flat-plate Solar Array Project Research Forum on High-efficiency Crystalline Silicon Solar Cells

NASA Technical Reports Server (NTRS)

Kachare, R.

1985-01-01

The high-efficiency crystalline silicon solar cells research forum addressed high-efficiency concepts, surface-interface effects, bulk effects, modeling and device processing. The topics were arranged into six interactive sessions, which focused on the state-of-the-art of device structures, identification of barriers to achieve high-efficiency cells and potential ways to overcome these barriers.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids.

PubMed

Strobel, Sebastian; Hernández, Rocío Murcia; Hansen, Allan G; Tornow, Marc

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10(-18) farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications - SiC, GaN, Ga2O3, and Diamond.

PubMed

Wellmann, Peter J

2017-11-17

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications – SiC, GaN, Ga2O3, and Diamond

PubMed Central

2017-01-01

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies. PMID:29200530

Surface chemistry relevant to material processing for semiconductor devices

NASA Astrophysics Data System (ADS)

Okada, Lynne Aiko

Metal-oxide-semiconductor (MOS) structures are the core of many modern integrated circuit (IC) devices. Each material utilized in the different regions of the device has its own unique chemistry. Silicon is the base semiconductor material used in the majority of these devices. With IC device complexity increasing and device dimensions decreasing, understanding material interactions and processing becomes increasingly critical. Hsb2 desorption is the rate-limiting step in silicon growth using silane under low temperature conditions. Activation energies for Hsb2 desorption measured during Si chemical vapor deposition (CVD) versus single-crystal studies are found to be significantly lower. It has been proposed that defect sites on the silicon surface could explain the observed differences. Isothermal Hsb2 desorption studies using laser induced thermal desorption (LITD) techniques have addressed this issue. The growth of low temperature oxides is another relevant issue for fabrication of IC devices. Recent studies using 1,4-disilabutane (DSB) (SiHsb3CHsb2CHsb2SiHsb3) at 100sp°C in ambient Osb2 displayed the successful low temperature growth of silicon dioxide (SiOsb2). However, these studies provided no information about the deposition mechanism. We performed LITD and Fourier transform infrared (FTIR) studies on single-crystal and porous silicon surfaces to examine the adsorption, decomposition, and desorption processes to determine the deposition mechanism. Titanium nitride (TiN) diffusion barriers are necessary in modern metallization structures. Controlled deposition using titanium tetrachloride (TiClsb4) and ammonia (NHsb3) has been demonstrated using atomic layered processing (ALP) techniques. We intended to study the sequential deposition method by monitoring the surface intermediates using LITD techniques. However, formation of a Cl impurity source, ammonium chloride (NHsb4sp+Clsp-), was observed, thereby, limiting our ability for effective studies. Tetrakis(dimethylamino)titanium (Tilbrack N\\{CHsb3\\}sb2rbracksb4) (TDMAT) is another precursor used in the CVD deposition of TiN films in IC devices. Thermal decomposition studies have demonstrated deviations from conformal deposition. Successful conformal deposition may be affected by readsorption of the reaction product, dimethylamine (HNlbrack CHsb3rbracksb2). Detailed studies were performed using LITD techniques in order to understand the adsorption and desorption kinetics of TDMAT and dimethylamine to gain insights about the conformal deposition of TiN.

The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2016-05-01

Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I-V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

Scalloping minimization in deep Si etching on Unaxis DSE tools

NASA Astrophysics Data System (ADS)

Lai, Shouliang; Johnson, Dave J.; Westerman, Russ J.; Nolan, John J.; Purser, David; Devre, Mike

2003-01-01

Sidewall smoothness is often a critical requirement for many MEMS devices, such as microfludic devices, chemical, biological and optical transducers, while fast silicon etch rate is another. For such applications, the time division multiplex (TDM) etch processes, so-called "Bosch" processes are widely employed. However, in the conventional TDM processes, rough sidewalls result due to scallop formation. To date, the amplitude of the scalloping has been directly linked to the silicon etch rate. At Unaxis USA Inc., we have developed a proprietary fast gas switching technique that is effective for scalloping minimization in deep silicon etching processes. In this technique, process cycle times can be reduced from several seconds to as little as a fraction of second. Scallop amplitudes can be reduced with shorter process cycles. More importantly, as the scallop amplitude is progressively reduced, the silicon etch rate can be maintained relatively constant at high values. An optimized experiment has shown that at etch rate in excess of 7 μm/min, scallops with length of 116 nm and depth of 35 nm were obtained. The fast gas switching approach offers an ideal manufacturing solution for MEMS applications where extremely smooth sidewall and fast etch rate are crucial.

High-temperature electronics

NASA Technical Reports Server (NTRS)

Seng, Gary T.

1987-01-01

In recent years, there was a growing need for electronics capable of sustained high-temperature operation for aerospace propulsion system instrumentation, control and condition monitoring, and integrated sensors. The desired operating temperature in some applications exceeds 600 C, which is well beyond the capability of currently available semiconductor devices. Silicon carbide displays a number of properties which make it very attractive as a semiconductor material, one of which is the ability to retain its electronic integrity at temperatures well above 600 C. An IR-100 award was presented to NASA Lewis in 1983 for developing a chemical vapor deposition process to grow single crystals of this material on standard silicon wafers. Silicon carbide devices were demonstrated above 400 C, but much work remains in the areas of crystal growth, characterization, and device fabrication before the full potential of silicon carbide can be realized. The presentation will conclude with current and future high-temperature electronics program plans. Although the development of silicon carbide falls into the category of high-risk research, the future looks promising, and the potential payoffs are tremendous.

Superacid Passivation of Crystalline Silicon Surfaces.

PubMed

Bullock, James; Kiriya, Daisuke; Grant, Nicholas; Azcatl, Angelica; Hettick, Mark; Kho, Teng; Phang, Pheng; Sio, Hang C; Yan, Di; Macdonald, Daniel; Quevedo-Lopez, Manuel A; Wallace, Robert M; Cuevas, Andres; Javey, Ali

2016-09-14

The reduction of parasitic recombination processes commonly occurring within the silicon crystal and at its surfaces is of primary importance in crystalline silicon devices, particularly in photovoltaics. Here we explore a simple, room temperature treatment, involving a nonaqueous solution of the superacid bis(trifluoromethane)sulfonimide, to temporarily deactivate recombination centers at the surface. We show that this treatment leads to a significant enhancement in optoelectronic properties of the silicon wafer, attaining a level of surface passivation in line with state-of-the-art dielectric passivation films. Finally, we demonstrate its advantage as a bulk lifetime and process cleanliness monitor, establishing its compatibility with large area photoluminescence imaging in the process.

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Producing Silicon Carbide for Semiconductor Devices

NASA Technical Reports Server (NTRS)

Hsu, G. C.; Rohatgi, N. K.

1986-01-01

Processes proposed for production of SiC crystals for use in semiconductors operating at temperatures as high as 900 degrees C. Combination of new processes produce silicon carbide chips containing epitaxial layers. Chips of SiC first grown on porous carbon matrices, then placed in fluidized bed, where additional layer of SiC grows. Processes combined to yield complete process. Liquid crystallization process used to make SiC particles or chips for fluidized-bed process.

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

NASA Astrophysics Data System (ADS)

Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

2018-04-01

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

NASA Astrophysics Data System (ADS)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

Silicon coupled with plasmon nanocavities generates bright visible hot luminescence

NASA Astrophysics Data System (ADS)

Cho, Chang-Hee; Aspetti, Carlos O.; Park, Joohee; Agarwal, Ritesh

2013-04-01

To address the limitations in device speed and performance in silicon-based electronics, there have been extensive studies on silicon optoelectronics with a view to achieving ultrafast optical data processing. The biggest challenge has been to develop an efficient silicon-based light source, because the indirect bandgap of silicon gives rise to extremely low emission efficiencies. Although light emission in quantum-confined silicon at sub-10 nm length scales has been demonstrated, there are difficulties in integrating quantum structures with conventional electronics. It is desirable to develop new concepts to obtain emission from silicon at length scales compatible with current electronic devices (20-100 nm), which therefore do not utilize quantum-confinement effects. Here, we demonstrate an entirely new method to achieve bright visible light emission in `bulk-sized' silicon coupled with plasmon nanocavities at room temperature, from non-thermalized carrier recombination. The highly enhanced emission (internal quantum efficiency of >1%) in plasmonic silicon, together with its size compatibility with current silicon electronics, provides new avenues for developing monolithically integrated light sources on conventional microchips.

Second-harmonic generation in substoichiometric silicon nitride layers

NASA Astrophysics Data System (ADS)

Pecora, Emanuele; Capretti, Antonio; Miano, Giovanni; Dal Negro, Luca

2013-03-01

Harmonic generation in optical circuits offers the possibility to integrate wavelength converters, light amplifiers, lasers, and multiple optical signal processing devices with electronic components. Bulk silicon has a negligible second-order nonlinear optical susceptibility owing to its crystal centrosymmetry. Silicon nitride has its place in the microelectronic industry as an insulator and chemical barrier. In this work, we propose to take advantage of silicon excess in silicon nitride to increase the Second Harmonic Generation (SHG) efficiency. Thin films have been grown by reactive magnetron sputtering and their nonlinear optical properties have been studied by femtosecond pumping over a wide range of excitation wavelengths, silicon nitride stoichiometry and thermal processes. We demonstrate SHG in the visible range (375 - 450 nm) using a tunable 150 fs Ti:sapphire laser, and we optimize the SH emission at a silicon excess of 46 at.% demonstrating a maximum SHG efficiency of 4x10-6 in optimized films. Polarization properties, generation efficiency, and the second order nonlinear optical susceptibility are measured for all the investigated samples and discussed in terms of an effective theoretical model. Our findings show that the large nonlinear optical response demonstrated in optimized Si-rich silicon nitride materials can be utilized for the engineering of nonlinear optical functions and devices on a Si chip.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Solution-processed polycrystalline silicon on paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Trifunovic, M.; Ishihara, R., E-mail: r.ishihara@tudelft.nl; Shimoda, T.

Printing electronics has led to application areas which were formerly impossible with conventional electronic processes. Solutions are used as inks on top of large areas at room temperatures, allowing the production of fully flexible circuitry. Commonly, research in these inks have focused on organic and metal-oxide ink materials due to their printability, while these materials lack in the electronic performance when compared to silicon electronics. Silicon electronics, on the other hand, has only recently found their way in solution processes. Printing of cyclopentasilane as the silicon ink has been conducted and devices with far superior electric performance have been mademore » when compared to other ink materials. A thermal annealing step of this material, however, was necessary, which prevented its usage on inexpensive substrates with a limited thermal budget. In this work, we introduce a method that allows polycrystalline silicon (poly-Si) production directly from the same liquid silicon ink using excimer laser irradiation. In this way, poly-Si could be formed directly on top of paper even with a single laser pulse. Using this method, poly-Si transistors were created at a maximum temperature of only 150 °C. This method allows silicon device formation on inexpensive, temperature sensitive substrates such as polyethylene terephthalate, polyethylene naphthalate or paper, which leads to applications that require low-cost but high-speed electronics.« less

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1983-01-01

The feasibility of making non-volatile digital memory devices of barium titanate, BaTiO3, that are integrated onto a silicon substrate with the required ferroelectric film produced by processing, compatible with silicon technology was examined.

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

NASA Astrophysics Data System (ADS)

Shiota, Koki; Kai, Kazuho; Nagaoka, Shiro; Tsuji, Takuto; Wakahara, Akihiro; Rusop, Mohamad

2016-07-01

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As the result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.

Porous siliconformation and etching process for use in silicon micromachining

DOEpatents

Guilinger, Terry R.; Kelly, Michael J.; Martin, Jr., Samuel B.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

A reproducible process for uniformly etching silicon from a series of micromechanical structures used in electrical devices and the like includes providing a micromechanical structure having a silicon layer with defined areas for removal thereon and an electrochemical cell containing an aqueous hydrofluoric acid electrolyte. The micromechanical structure is submerged in the electrochemical cell and the defined areas of the silicon layer thereon are anodically biased by passing a current through the electrochemical cell for a time period sufficient to cause the defined areas of the silicon layer to become porous. The formation of the depth of the porous silicon is regulated by controlling the amount of current passing through the electrochemical cell. The micromechanical structure is then removed from the electrochemical cell and submerged in a hydroxide solution to remove the porous silicon. The process is subsequently repeated for each of the series of micromechanical structures to achieve a reproducibility better than 0.3%.

Low temperature perovskite solar cells with an evaporated TiO 2 compact layer for perovskite silicon tandem solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bett, Alexander J.; Schulze, Patricia S. C.; Winkler, Kristina

Silicon-based tandem solar cells can overcome the efficiency limit of single junction silicon solar cells. Perovskite solar cells are particularly promising as a top cell in monolithic tandem devices due to their rapid development towards high efficiencies, a tunable band gap with a sharp optical absorption edge and a simple production process. In monolithic tandem devices, the perovskite solar cell is deposited directly on the silicon cell, requiring low-temperature processes (< 200 °C) to maintain functionality of under-lying layers of the silicon cell in case of highly efficient silicon hetero-junction (SHJ) bottom solar cell. In this work, we present amore » complete low-temperature process for perovskite solar cells including a mesoporous titanium oxide (TiO 2) scaffold - a structure yielding the highest efficiencies for single-junction perovskite solar cells. We show that evaporation of the compact TiO 2 hole blocking layer and ultra-violet (UV) curing for the mesoporous TiO 2 layer allows for good performance, comparable to high-temperature (> 500 °C) processes. With both manufacturing routes, we obtain short-circuit current densities (J SC) of about 20 mA/cm 2, open-circuit voltages (V OC) over 1 V, fill factors (FF) between 0.7 and 0.8 and efficiencies (n) of more than 15%. We further show that the evaporated TiO 2 layer is suitable for the application in tandem devices. The series resistance of the layer itself and the contact resistance to an indium doped tin oxide (ITO) interconnection layer between the two sub-cells are low. Additionally, the low parasitic absorption for wavelengths above the perovskite band gap allow a higher absorption in the silicon bottom solar cell, which is essential to achieve high tandem efficiencies.« less

Low temperature perovskite solar cells with an evaporated TiO 2 compact layer for perovskite silicon tandem solar cells

DOE PAGES

Bett, Alexander J.; Schulze, Patricia S. C.; Winkler, Kristina; ...

2017-09-21

Silicon-based tandem solar cells can overcome the efficiency limit of single junction silicon solar cells. Perovskite solar cells are particularly promising as a top cell in monolithic tandem devices due to their rapid development towards high efficiencies, a tunable band gap with a sharp optical absorption edge and a simple production process. In monolithic tandem devices, the perovskite solar cell is deposited directly on the silicon cell, requiring low-temperature processes (< 200 °C) to maintain functionality of under-lying layers of the silicon cell in case of highly efficient silicon hetero-junction (SHJ) bottom solar cell. In this work, we present amore » complete low-temperature process for perovskite solar cells including a mesoporous titanium oxide (TiO 2) scaffold - a structure yielding the highest efficiencies for single-junction perovskite solar cells. We show that evaporation of the compact TiO 2 hole blocking layer and ultra-violet (UV) curing for the mesoporous TiO 2 layer allows for good performance, comparable to high-temperature (> 500 °C) processes. With both manufacturing routes, we obtain short-circuit current densities (J SC) of about 20 mA/cm 2, open-circuit voltages (V OC) over 1 V, fill factors (FF) between 0.7 and 0.8 and efficiencies (n) of more than 15%. We further show that the evaporated TiO 2 layer is suitable for the application in tandem devices. The series resistance of the layer itself and the contact resistance to an indium doped tin oxide (ITO) interconnection layer between the two sub-cells are low. Additionally, the low parasitic absorption for wavelengths above the perovskite band gap allow a higher absorption in the silicon bottom solar cell, which is essential to achieve high tandem efficiencies.« less

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Astrophysics Data System (ADS)

Dyer, L. D.

1985-08-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Technical Reports Server (NTRS)

Dyer, L. D.

1985-01-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Multijunction photovoltaic device and fabrication method

DOEpatents

Arya, Rajeewa R.; Catalano, Anthony W.

1993-09-21

A multijunction photovoltaic device includes first and second amorphous silicon PIN photovoltaic cells in a stacked arrangement. An interface layer, composed of a doped silicon compound, is disposed between the two cells and has a lower bandgap than the respective n- and p-type adjacent layers of the first and second cells. The interface layer forms an ohmic contact with the one or the adjacent cell layers of the same conductivity type, and a tunnel junction with the other of the adjacent cell layers. The disclosed device is fabricated by a glow discharge process.

Reduced adherence of Candida to silane-treated silicone rubber.

PubMed

Price, C L; Williams, D W; Waters, M G J; Coulthwaite, L; Verran, J; Taylor, R L; Stickler, D; Lewis, M A O

2005-07-01

Silicone rubber is widely used in the construction of medical devices that can provide an essential role in the treatment of human illness. However, subsequent microbial colonization of silicone rubber can result in clinical infection or device failure. The objective of this study was to determine the effectiveness of a novel silane-treated silicone rubber in inhibiting microbial adherence and material penetration. Test material was prepared by a combination of argon plasma discharge treatment and fluorinated silane coupling. Chemicophysical changes were then confirmed by X-ray photoelectron spectroscopy, contact-angle measurement, and atomic force microscopy. Two separate adherence assays and a material penetration assay assessed the performance of the new material against four strains of Candida species. Results showed a significant reduction (p < 0.01) of Candida albicans GDH 2346 adherence to silane-treated silicone compared with untreated controls. This reduction was still evident after the incorporation of saliva into the assay. Adherence inhibition also occurred with Candida tropicalis MMU and Candida krusei NCYC, although this was assay dependent. Reduced penetration of silane-treated silicone by Candida was evident when compared to untreated controls, plaster-processed silicone, and acrylic-processed silicone. To summarize, a novel silicone rubber material is described that inhibits both candidal adherence and material penetration. The clinical benefit and performance of this material remains to be determined. Copyright 2005 Wiley Periodicals, Inc.

Stress Analysis of SiC MEMS Using Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Ness, Stanley J.; Marciniak, M. A.; Lott, J. A.; Starman, L. A.; Busbee, J. D.; Melzak, J. M.

2003-03-01

During the fabrication of Micro-Electro-Mechanical Systems (MEMS), residual stress is often induced in the thin films that are deposited to create these systems. These stresses can cause the device to fail due to buckling, curling, or fracture. Industry is looking for ways to characterize the stress during the deposition of thin films in order to reduce or eliminate device failure. Micro-Raman spectroscopy has been successfully used to characterize poly-Si MEMS devices made with the MUMPS® process. Raman spectroscopy was selected because it is nondestructive, fast and has the potential for in situ stress monitoring. This research attempts to use Raman spectroscopy to analyze the stress in SiC MEMS made with the MUSiC® process. Raman spectroscopy is performed on 1-2-micron-thick SiC thin films deposited on silicon, silicon nitride, and silicon oxide substrates. The most common poly-type of SiC found in thin film MEMS made with the MUSiC® process is 3C-SiC. Research also includes baseline spectra of 6H, 4H, and 15R poly-types of bulk SiC.

Seventh workshop on the role of impurities and defects in silicon device processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

1997-08-01

This workshop is the latest in a series which has looked at technological issues related to the commercial development and success of silicon based photovoltaic (PV) modules. PV modules based on silicon are the most common at present, but face pressure from other technologies in terms of cell performance and cell cost. This workshop addresses a problem which is a factor in the production costs of silicon based PV modules.

Method of fabricating porous silicon carbide (SiC)

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Investigation of silicide-induced-dopant-activation for steep tunnel junction in tunnel field effect transistor (TFET)

NASA Astrophysics Data System (ADS)

Kim, Sihyun; Kwon, Dae Woong; Park, Euyhwan; Lee, Junil; Lee, Roongbin; Lee, Jong-Ho; Park, Byung-Gook

2018-02-01

Numerous researches for making steep tunnel junction within tunnel field-effect transistor (TFET) have been conducted. One of the ways to make an abrupt junction is source/drain silicidation, which uses the phenomenon often called silicide-induced-dopant-segregation. It is revealed that the silicide process not only helps dopants to pile up adjacent to the metal-silicon alloy, also induces the dopant activation, thereby making it possible to avoid additional high temperature process. In this report, the availability of dopant activation induced by metal silicide process was thoroughly investigated by diode measurement and device simulation. Metal-silicon (MS) diodes having p+ and n+ silicon formed on the p- substrate exhibit the characteristics of ohmic and pn diodes respectively, for both the samples with and without high temperature annealing. The device simulation for TFETs with dopant-segregated source was also conducted, which verified enhanced DC performance.

Review of silicon photonics: history and recent advances

NASA Astrophysics Data System (ADS)

Ye, Winnie N.; Xiong, Yule

2013-09-01

Silicon photonics has attracted tremendous attention and research effort as a promising technology in optoelectronic integration for computing, communications, sensing, and solar harvesting. Mainly due to the combination of its excellent material properties and the complementary metal-oxide semiconductor (CMOS) fabrication processing technology, silicon has becoming the material choice for photonic and optoelectronic circuits with low cost, ultra-compact device footprint, and high-density integration. This review paper provides an overview on silicon photonics, by highlighting the early work from the mid-1980s on the fundamental building blocks such as silicon platforms and waveguides, and the main milestones that have been achieved so far in the field. A summary of reported work on functional elements in both passive and active devices, as well as the applications of the technology in interconnect, sensing, and solar cells, is identified.

Area Reports. Advanced materials and devices research area. Silicon materials research task, and advanced silicon sheet task

NASA Technical Reports Server (NTRS)

1986-01-01

The objectives of the Silicon Materials Task and the Advanced Silicon Sheet Task are to identify the critical technical barriers to low-cost silicon purification and sheet growth that must be overcome to produce a PV cell substrate material at a price consistent with Flat-plate Solar Array (FSA) Project objectives and to overcome these barriers by performing and supporting appropriate R&D. Progress reports are given on silicon refinement using silane, a chemical vapor transport process for purifying metallurgical grade silicon, silicon particle growth research, and modeling of silane pyrolysis in fluidized-bed reactors.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Light trapping in a-Si/c-Si heterojunction solar cells by embedded ITO nanoparticles at rear surface

NASA Astrophysics Data System (ADS)

Dhar, Sukanta; Mandal, Sourav; Mitra, Suchismita; Ghosh, Hemanta; Mukherjee, Sampad; Banerjee, Chandan; Saha, Hiranmoy; Barua, A. K.

2017-12-01

The advantages of the amorphous silicon (a-Si)/crystalline silicon (c-Si) hetero junction technology are low temperature (<200 °C) processing and fewer process steps to fabricate the device. In this work, we used indium tin oxide (ITO) nanoparticles embedded in amorphous silicon material at the rear side of the crystalline wafer. The nanoparticles were embedded in silicon to have higher scattering efficiency, as has been established by simulation studies. It has been shown that significant photocurrent enhancements (32.8 mA cm-2 to 35.1 mA cm-2) are achieved because of high scattering and coupling efficiency of the embedded nanoparticles into the silicon device, leading to an increase in efficiency from 13.74% to 15.22%. In addition, we have observed a small increase in open circuit voltage. This may be due to the surface passivation during the ITO nanoparticle formation with hydrogen plasma treatment. We also support our experimental results by simulation, with the help of a commercial finite-difference time-domain (FDTD) software solution.

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

NASA Astrophysics Data System (ADS)

Tsutsumi, Toshiyuki

2018-06-01

The threshold voltage (V th) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the V th fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad V th distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the V th fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

All-optical lithography process for contacting nanometer precision donor devices

NASA Astrophysics Data System (ADS)

Ward, D. R.; Marshall, M. T.; Campbell, D. M.; Lu, T. M.; Koepke, J. C.; Scrymgeour, D. A.; Bussmann, E.; Misra, S.

2017-11-01

We describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

All-optical lithography process for contacting nanometer precision donor devices

DOE PAGES

Ward, Daniel Robert; Marshall, Michael Thomas; Campbell, DeAnna Marie; ...

2017-11-06

In this article, we describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

All-optical lithography process for contacting nanometer precision donor devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ward, Daniel Robert; Marshall, Michael Thomas; Campbell, DeAnna Marie

In this article, we describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

Chemical vapor deposition and characterization of polysilanes polymer based thin films and their applications in compound semiconductors and silicon devices

NASA Astrophysics Data System (ADS)

Oulachgar, El Hassane

As the semiconductors industry is moving toward nanodevices, there is growing need to develop new materials and thin films deposition processes which could enable strict control of the atomic composition and structure of thin film materials in order to achieve precise control on their electrical and optical properties. The accurate control of thin film characteristics will become increasingly important as the miniaturization of semiconductor devices continue. There is no doubt that chemical synthesis of new materials and their self assembly will play a major role in the design and fabrication of next generation semiconductor devices. The objective of this work is to investigate the chemical vapor deposition (CVD) process of thin film using a polymeric precursor as a source material. This process offers many advantages including low deposition cost, hazard free working environment, and most importantly the ability to customize the polymer source material through polymer synthesis and polymer functionalization. The combination between polymer synthesis and CVD process will enable the design of new generation of complex thin film materials with a wide range of improved chemical, mechanical, electrical and optical properties which cannot be easily achieved through conventional CVD processes based on gases and small molecule precursors. In this thesis we mainly focused on polysilanes polymers and more specifically poly(dimethylsilanes). The interest in these polymers is motivated by their distinctive electronic and photonic properties which are attributed to the delocalization of the sigma-electron along the Si-Si backbone chain. These characteristics make polysilane polymers very promising in a broad range of applications as a dielectric, a semiconductor and a conductor. The polymer-based CVD process could be eventually extended to other polymer source materials such as polygermanes, as well as and a variety of other inorganic and hybrid organic-inorganic polymers. This work has demonstrated that a polysilane polymeric source can be used to deposit a wide range of thin film materials exhibiting similar properties with conventional ceramic materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC) silicon dioxide (SiO2) and silicon nitride (Si3N4). The strict control of the deposition process allows precise control of the electrical, optical and chemical properties of polymer-based thin films within a broad range. This work has also demonstrated for the first time that poly(dimethylsilmaes) polymers deposited by CVD can be used to effectively passivate both silicon and gallium arsenide MOS devices. This finding makes polymer-based thin films obtained by CVD very promising for the development of high-kappa dielectric materials for next generation high-mobility CMOS technology. Keywords. Thin films, Polymers, Vapor Phase Deposition, CVD, Nanodielectrics, Organosilanes, Polysilanes, GaAs Passivation, MOSFET, Silicon Oxynitride, Integrated Waveguide, Silicon Carbide, Compound Semiconductors.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

PubMed Central

Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

2011-01-01

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

Ferroelectrics for semiconductor devices

NASA Astrophysics Data System (ADS)

Sayer, M.; Wu, Z.; Vasant Kumar, C. V. R.; Amm, D. T.; Griswold, E. M.

1992-11-01

The technology for the implementation of the integration of thin film ferroelectrics with silicon processing for various devices is described, and factors affecting the integration of ferroelectric films with semiconductor processing are discussed. Consideration is also given to film properties, the properties of electrode materials and structures, and the phenomena of ferroelectric fatigue and aging. Particular attention is given to the nonmemory device application of ferroelectrics.

Energy correlations of photon pairs generated by a silicon microring resonator probed by Stimulated Four Wave Mixing.

PubMed

Grassani, Davide; Simbula, Angelica; Pirotta, Stefano; Galli, Matteo; Menotti, Matteo; Harris, Nicholas C; Baehr-Jones, Tom; Hochberg, Michael; Galland, Christophe; Liscidini, Marco; Bajoni, Daniele

2016-04-01

Compact silicon integrated devices, such as micro-ring resonators, have recently been demonstrated as efficient sources of quantum correlated photon pairs. The mass production of integrated devices demands the implementation of fast and reliable techniques to monitor the device performances. In the case of time-energy correlations, this is particularly challenging, as it requires high spectral resolution that is not currently achievable in coincidence measurements. Here we reconstruct the joint spectral density of photons pairs generated by spontaneous four-wave mixing in a silicon ring resonator by studying the corresponding stimulated process, namely stimulated four wave mixing. We show that this approach, featuring high spectral resolution and short measurement times, allows one to discriminate between nearly-uncorrelated and highly-correlated photon pairs.

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Inkjet 3D printing of UV and thermal cure silicone elastomers for dielectric elastomer actuators

NASA Astrophysics Data System (ADS)

McCoul, David; Rosset, Samuel; Schlatter, Samuel; Shea, Herbert

2017-12-01

Dielectric elastomer actuators (DEAs) are an attractive form of electromechanical transducer, possessing high energy densities, an efficient design, mechanical compliance, high speed, and noiseless operation. They have been incorporated into a wide variety of devices, such as microfluidic systems, cell bioreactors, tunable optics, haptic displays, and actuators for soft robotics. Fabrication of DEA devices is complex, and the majority are inefficiently made by hand. 3D printing offers an automated and flexible manufacturing alternative that can fabricate complex, multi-material, integrated devices consistently and in high resolution. We present a novel additive manufacturing approach to DEA devices in which five commercially available, thermal and UV-cure DEA silicone rubber materials have been 3D printed with a drop-on-demand, piezoelectric inkjet system. Using this process, 3D structures and high-quality silicone dielectric elastomer membranes as thin as 2 μm have been printed that exhibit mechanical and actuation performance at least as good as conventionally blade-cast membranes. Printed silicone membranes exhibited maximum tensile strains of up to 727%, and DEAs with printed silicone dielectrics were actuated up to 6.1% area strain at a breakdown strength of 84 V μm-1 and also up to 130 V μm-1 at 2.4% strain. This approach holds great potential to manufacture reliable, high-performance DEA devices with high throughput.

Initial steps toward the realization of large area arrays of single photon counting pixels based on polycrystalline silicon TFTs

NASA Astrophysics Data System (ADS)

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Jiang, Hao; Street, Robert A.; Lu, Jeng Ping

2014-03-01

The thin-film semiconductor processing methods that enabled creation of inexpensive liquid crystal displays based on amorphous silicon transistors for cell phones and televisions, as well as desktop, laptop and mobile computers, also facilitated the development of devices that have become ubiquitous in medical x-ray imaging environments. These devices, called active matrix flat-panel imagers (AMFPIs), measure the integrated signal generated by incident X rays and offer detection areas as large as ~43×43 cm2. In recent years, there has been growing interest in medical x-ray imagers that record information from X ray photons on an individual basis. However, such photon counting devices have generally been based on crystalline silicon, a material not inherently suited to the cost-effective manufacture of monolithic devices of a size comparable to that of AMFPIs. Motivated by these considerations, we have developed an initial set of small area prototype arrays using thin-film processing methods and polycrystalline silicon transistors. These prototypes were developed in the spirit of exploring the possibility of creating large area arrays offering single photon counting capabilities and, to our knowledge, are the first photon counting arrays fabricated using thin film techniques. In this paper, the architecture of the prototype pixels is presented and considerations that influenced the design of the pixel circuits, including amplifier noise, TFT performance variations, and minimum feature size, are discussed.

Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

NASA Astrophysics Data System (ADS)

Bechtler, Laurie; Velidandla, Vamsi

2003-04-01

In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

Replacement for Silicon Devices Looms Big With ORNL Discovery

DOE Office of Scientific and Technical Information (OSTI.GOV)

Belianinov, Alex; Ovchinnikova, Olga

2016-04-05

Two-dimensional electronic devices could inch closer to their ultimate promise of low power, high efficiency and mechanical flexibility with a processing technique developed at the Department of Energy’s Oak Ridge National Laboratory.

Embedding solar cell materials with on-board integrated energy storage for load-leveling and dark power delivery (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pint, Cary L.; Westover, Andrew S.; Cohn, Adam P.; Erwin, William R.; Share, Keith; Metke, Thomas; Bardhan, Rizia

2015-10-01

This work will discuss our recent advances focused on integrating high power energy storage directly into the native materials of both conventional photovoltaics (PV) and dye-sensitized solar cells (DSSCs). In the first case (PV), we demonstrate the ability to etch high surface-area porous silicon charge storage interfaces directly into the backside of a conventional polycrystalline silicon photovoltaic device exhibiting over 14% efficiency. These high surface area materials are then coupled with solid-state ionic liquid-polymer electrolytes to produce solid-state fully integrated devices where the PV device can directly inject charge into an on-board supercapacitor that can be separately discharged under dark conditions with a Coulombic efficiency of 84%. In a similar manner, we further demonstrate that surface engineered silicon materials can be utilized to replace Pt counterelectrodes in conventional DSSC energy conversion devices. As the silicon counterelectrodes rely strictly on surface Faradaic chemical reactions with the electrolyte on one side of the wafer electrode, we demonstrate double-sided processing of electrodes that enables dual-function of the material for simultaneous energy storage and conversion, each on opposing sides. In both of these devices, we demonstrate the ability to produce an all-silicon coupled energy conversion and storage system through the common ability to convert unused silicon in solar cells into high power silicon-based supercapacitors. Beyond the proof-of-concept design and performance of this integrated solar-storage system, this talk will conclude with a brief discussion of the hurdles and challenges that we envision for this emerging area both from a fundamental and technological viewpoint.

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shiota, Koki, E-mail: a14510@sr.kagawa-nct.ac.jp; Kai, Kazuho; Nagaoka, Shiro, E-mail: nagaoka@es.kagawa-nct.ac.jp

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As themore » result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.« less

A fluid collection system for dermal wounds in clinical investigations

PubMed Central

Klopfer, Michael; Li, G.-P.; Widgerow, Alan; Bachman, Mark

2016-01-01

In this work, we demonstrate the use of a thin, self adherent, and clinically durable patch device that can collect fluid from a wound site for analysis. This device is manufactured from laminated silicone layers using a novel all-silicone double-molding process. In vitro studies for flow and delivery were followed by a clinical demonstration for exudate collection efficiency from a clinically presented partial thickness burn. The demonstrated utility of this device lends itself for use as a research implement used to clinically sample wound exudate for analysis. This device can serve as a platform for future integration of wearable technology into wound monitoring and care. The demonstrated fabrication method can be used for devices requiring thin membrane construction. PMID:27051470

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Growth of a delta-doped silicon layer by molecular beam epitaxy on a charge-coupled device for reflection-limited ultraviolet quantum efficiency

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Grunthaner, Paula J.; Grunthaner, Frank J.; Terhune, R. W.; Fattahi, Masoud; Tseng, Hsin-Fu

1992-01-01

Low-temperature silicon molecular beam epitaxy is used to grow a delta-doped silicon layer on a fully processed charge-coupled device (CCD). The measured quantum efficiency of the delta-doped backside-thinned CCD is in agreement with the reflection limit for light incident on the back surface in the spectral range of 260-600 nm. The 2.5 nm silicon layer, grown at 450 C, contained a boron delta-layer with surface density of about 2 x 10 exp 14/sq cm. Passivation of the surface was done by steam oxidation of a nominally undoped 1.5 nm Si cap layer. The UV quantum efficiency was found to be uniform and stable with respect to thermal cycling and illumination conditions.

Small area silicon diffused junction X-ray detectors

NASA Technical Reports Server (NTRS)

Walton, J. T.; Pehl, R. H.; Larsh, A. E.

1982-01-01

The low-temperature performance of silicon diffused junction detectors in the measurement of low energy X-rays is reported. The detectors have an area of 0.04 sq cm and a thickness of 100 microns. The spectral resolutions of these detectors were found to be in close agreement with expected values, indicating that the defects introduced by the high-temperature processing required in the device fabrication were not deleteriously affecting the detection of low-energy X-rays. Device performance over a temperature range of 77 K to 150 K is given. These detectors were designed to detect low-energy X-rays in the presence of minimum ionizing electrons. The successful application of silicon-diffused junction technology to X-ray detector fabrication may facilitate the development of other novel silicon X-ray detector designs.

3D Integration for Wireless Multimedia

NASA Astrophysics Data System (ADS)

Kimmich, Georg

The convergence of mobile phone, internet, mapping, gaming and office automation tools with high quality video and still imaging capture capability is becoming a strong market trend for portable devices. High-density video encode and decode, 3D graphics for gaming, increased application-software complexity and ultra-high-bandwidth 4G modem technologies are driving the CPU performance and memory bandwidth requirements close to the PC segment. These portable multimedia devices are battery operated, which requires the deployment of new low-power-optimized silicon process technologies and ultra-low-power design techniques at system, architecture and device level. Mobile devices also need to comply with stringent silicon-area and package-volume constraints. As for all consumer devices, low production cost and fast time-to-volume production is key for success. This chapter shows how 3D architectures can bring a possible breakthrough to meet the conflicting power, performance and area constraints. Multiple 3D die-stacking partitioning strategies are described and analyzed on their potential to improve the overall system power, performance and cost for specific application scenarios. Requirements and maturity of the basic process-technology bricks including through-silicon via (TSV) and die-to-die attachment techniques are reviewed. Finally, we highlight new challenges which will arise with 3D stacking and an outlook on how they may be addressed: Higher power density will require thermal design considerations, new EDA tools will need to be developed to cope with the integration of heterogeneous technologies and to guarantee signal and power integrity across the die stack. The silicon/wafer test strategies have to be adapted to handle high-density IO arrays, ultra-thin wafers and provide built-in self-test of attached memories. New standards and business models have to be developed to allow cost-efficient assembly and testing of devices from different silicon and technology providers.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

3D-FBK Pixel Sensors: Recent Beam Tests Results with Irradiated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Micelli, A.; /INFN, Trieste /Udine U.; Helle, K.

2012-04-30

The Pixel Detector is the innermost part of the ATLAS experiment tracking device at the Large Hadron Collider, and plays a key role in the reconstruction of the primary vertices from the collisions and secondary vertices produced by short-lived particles. To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology ismore » an innovative combination of very-large-scale integration and Micro-Electro-Mechanical-Systems where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. This paper reports on the 2010 June beam test results for irradiated 3D devices produced at FBK (Trento, Italy). The performance of these devices, all bump-bonded with the ATLAS pixel FE-I3 read-out chip, is compared to that observed before irradiation in a previous beam test.« less

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

3D printing for health & wealth: Fabrication of custom-made medical devices through additive manufacturing

NASA Astrophysics Data System (ADS)

Colpani, Alessandro; Fiorentino, Antonio; Ceretti, Elisabetta

2018-05-01

Additive Manufacturing (AM) differs from traditional manufacturing technologies by its ability to handle complex shapes with great design flexibility. These features make the technique suitable to fabricate customized components, particularly answering specific custom needs. Although AM mainly referred to prototyping, nowadays the interest in direct manufacturing of actual parts is growing. This article shows the application of AM within the project 3DP-4H&W (3D Printing for Health & Wealth) which involves engineers and physicians for developing pediatric custom-made medical devices to enhance the fulfilling of the patients specific needs. In the project, two types of devices made of a two-component biocompatible silicone are considered. The first application (dental field) consists in a device for cleft lip and palate. The second one (audiological field) consists in an acoustic prosthesis. The geometries of the devices are based on the anatomy of the patient that is obtained through a 3D body scan process. For both devices, two different approaches were planned, namely direct AM and indirect Rapid Tooling (RT). In particular, direct AM consists in the FDM processing of silicone, while RT consists in molds FDM fabrication followed by silicone casting. This paper presents the results of the RT method that is articulated in different phases: the acquisition of the geometry to be realized, the design of the molds taking into account the casting feasibility (as casting channel, vents, part extraction), the realization of molds produced through AM, molds surface chemical finishing, pouring and curing of the silicone. The fabricated devices were evaluated by the physicians team that confirmed the effectiveness of the proposed procedure in fabricating the desired devices. Moreover, the procedure can be used as a general method to extend the range of applications to any custom-made device for anatomic districts, especially where complex shapes are present (as tracheal or maxillary prostheses).

Heterogeneously integrated silicon photonics for the mid-infrared and spectroscopic sensing.

PubMed

Chen, Yu; Lin, Hongtao; Hu, Juejun; Li, Mo

2014-07-22

Besides being the foundational material for microelectronics, crystalline silicon has long been used for the production of infrared lenses and mirrors. More recently, silicon has become the key material to achieve large-scale integration of photonic devices for on-chip optical interconnect and signal processing. For optics, silicon has significant advantages: it offers a very high refractive index and is highly transparent in the spectral range from 1.2 to 8 μm. To fully exploit silicon’s superior performance in a remarkably broad range and to enable new optoelectronic functionalities, here we describe a general method to integrate silicon photonic devices on arbitrary foreign substrates. In particular, we apply the technique to integrate silicon microring resonators on mid-infrared compatible substrates for operation in the mid-infrared. These high-performance mid-infrared optical resonators are utilized to demonstrate, for the first time, on-chip cavity-enhanced mid-infrared spectroscopic analysis of organic chemicals with a limit of detection of less than 0.1 ng.

Monolithically interconnected silicon-film™ module technology

NASA Astrophysics Data System (ADS)

DelleDonne, E. J.; Ford, D. H.; Hall, R. B.; Ingram, A. E.; Rand, J. A.; Barnett, A. M.

1999-03-01

AstroPower is developing an advanced thin-silicon-based, photovoltaic module product. A low-cost monolithic interconnected device is being integrated into a module that combines the design and process features of advanced light trapped, thin-silicon solar cells. This advanced product incorporates a low-cost substrate, a nominally 50-μm thick grown silicon layer with minority carrier diffusion lengths exceeding the active layer thickness, light trapping due to back-surface reflection, and back-surface passivation. The thin silicon layer enables high solar cell performance and can lead to a module conversion efficiency as high as 19%. These performance design features, combined with low-cost manufacturing using relatively low-cost capital equipment, continuous processing and a low-cost substrate, will lead to high-performance, low-cost photovoltaic panels.

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Single-Event Effects in Silicon and Silicon Carbide Power Devices

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2014-01-01

NASA Electronics Parts and Packaging program-funded activities over the past year on single-event effects in silicon and silicon carbide power devices are presented, with focus on SiC device failure signatures.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Water Splitting Using Porous Silicon Photo-electrodes for Hydrogen Production

NASA Astrophysics Data System (ADS)

Ali, M.; Starkov, V. V.; Gosteva, E. A.; Druzhinin, A. V.; Sattar, S.

2017-11-01

This paper presents the efficiency study results of using gradient-porous silicon structures with different morphology, as photo-anodes for photo-electrochemical dissociation of water. The results of a study of the physicochemical properties of gradient-porous silicon structures show the relatively low cost and simplicity of the technological process, as well as the possibility of forming structures with predefined properties, allow the creation of effective devices for artificial photosynthesis based on porous silicon for subsequent use in hydrogen energy.

Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Hsieh, I.-Wei

In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic devices are quite different from those of electronic devices. Minimizing propagation losses by reducing sidewall roughness to nanometer scale over a device length of several millimeters or even centimeters has prompted researchers in academia and industry to refine the fabrication process. Chapter 3 of this thesis summarizes our efforts in fabricating silicon photonic devices using standard CMOS technology. Chapter 4 describes the characterization of nonlinear effects, including self-phase modulation (SPM), cross-phase modulation (XPM), and supercontinuum generation in silicon-wire waveguides. Silicon-wire waveguides are strip waveguides with submicron transverse dimensions, which allow strong light confinement inside the silicon core. This strong optical confinement, in addition to the large third-order nonlinear optical susceptibility of crystalline silicon, leads to a net nonlinearity which is several orders of magnitude higher than the nonlinearity of silica fiber. Significant nonlinear effects can be observed and characterized over a device length of only several millimeters in silicon wires with very small input power. These effects provide opportunities for engineers to design active silicon photonic devices which are compact and energy-efficient. Chapter 5 presents a realization of an integrated SOI optical isolator, which is a critical yet often overlooked component in photonic integrated circuits. This study shows the feasibility to make a hybrid garnet/SOI active device with very promising results. Finally, Chapter 6 summarizes our demonstration of transmitting terabit-scale data streams in silicon-wire waveguides, which is an important first-step towards enabling intra-chip interconnection networks with ultra-high bandwidths. Although the scope of this thesis is limited to providing only fractional views of the whole silicon photonics area, it provides enough references for interested readers to conduct further literature research in other aspects of silicon photonics. It is the author's hope that the thesis would convey to its readers the significance and potential of this exciting emerging technology.

Growing Cobalt Silicide Columns In Silicon

NASA Technical Reports Server (NTRS)

Fathauer, Obert W.

1991-01-01

Codeposition by molecular-beam epitaxy yields variety of structures. Proposed fabrication process produces three-dimensional nanometer-sized structures on silicon wafers. Enables control of dimensions of metal and semiconductor epitaxial layers in three dimensions instead of usual single dimension (perpendicular to the plane of the substrate). Process used to make arrays of highly efficient infrared sensors, high-speed transistors, and quantum wires. For fabrication of electronic devices, both shapes and locations of columns controlled. One possible technique for doing this electron-beam lithography, see "Making Submicron CoSi2 Structures on Silicon Substrates" (NPO-17736).

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Enhancement of green electroluminescence from nanocrystalline silicon by wet and dry processes.

PubMed

Sato, Keisuke; Hirakuri, Kenji

2006-01-01

Correlation between defects and luminescence property from electroluminescent (EL) device composed of nanocrystalline silicon (nc-Si) prepared by wet and dry processes such as hydrofluoric (HF) acid solution treatment and annealing have investigated using electron spin resonance and EL measurements. The EL device using HF-treated nc-Si emitted strong red light, because of existence of only P'ce-centers (radiative recombination centers) on the surface vicinity. On the other hand, the EL device using annealed nc-Si above 400 degrees C exhibited green luminescence by the reduction of particle size due to surface oxidation. When the annealing temperature was risen from 400 degrees C up to 600 degrees C, the green luminescence strengthened with increasing the P'ce-centers. These results indicate that the formation of many radiative recombination centers onto the nc-Si surface vicinity lead to the enhancement of green luminescence from the nc-Si based EL device.

A silicon carbide array for electrocorticography and peripheral nerve recording.

PubMed

Diaz-Botia, C A; Luna, L E; Neely, R M; Chamanzar, M; Carraro, C; Carmena, J M; Sabes, P N; Maboudian, R; Maharbiz, M M

2017-10-01

Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

A silicon carbide array for electrocorticography and peripheral nerve recording

NASA Astrophysics Data System (ADS)

Diaz-Botia, C. A.; Luna, L. E.; Neely, R. M.; Chamanzar, M.; Carraro, C.; Carmena, J. M.; Sabes, P. N.; Maboudian, R.; Maharbiz, M. M.

2017-10-01

Objective. Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. Approach. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. Main results. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Significance. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

Graphene field-effect devices

NASA Astrophysics Data System (ADS)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Synthesis and properties of silicon nanowire devices

NASA Astrophysics Data System (ADS)

Byon, Kumhyo

Silicon nanowire (SiNW) is a very attractive one-dimensional material for future nanoelectronic applications. Reliable control of key field effect transistor (FET) parameters such as conductance, mobility, threshold voltage and on/off ratio is crucial to the applications of SiNW to working logic devices and integrated circuits. In this thesis, we fabricated silicon nanowire field effect transistors (SiNW FETs) and studied the dependence of their electrical transport properties upon various parameters including SiNW growth conditions, post-growth doping, and contact annealing. From these studies, we found how different processes control important FET characteristics. Key accomplishments of this thesis include p-channel enhancement mode FETs, n-channel FETs by post-growth vapor doping and high performance ambipolar devices. In the first part of this work, single crystalline SiNWs were synthesized by thermal evaporation without gold catalysts. FETs were fabricated using both as-grown SiNWs and post-growth n-doped SiNWs. FET from p-type source materials behaves as a p-channel enhancement mode FET which is predominant in logic devices due to its fast operation and low power consumption. Using bismuth vapor, the as-grown SiNWs were doped into n-type materials. The majority carriers in SiNWs can therefore be controlled by proper choice of the vapor phase dopant species. Post-growth doping using vapor phase is applicable to other nanowire systems. In the second part, high performance ambipolar FETs were fabricated. A two step annealing process was used to control the Schottky barrier between SiNW and metal contacts in order to enhance device performance. Initial p-channel SiNW FETs were converted into ambipolar SiNW FETs after contact annealing. Furthermore, significant increases in both on/off ratio and channel mobilities were achieved after contact annealing. Promising device structures to implement ambipolar devices into large scale integrated circuits were proposed. The contributions of this study are to further understanding of the electrical transport properties of SiNWs and to provide optimized processes to fabricate emerging high performance nanoelectronic devices using SiNWs for future generation beyond bulk silicon.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Silicide/Silicon Hetero-Junction Structure for Thermoelectric Applications.

PubMed

Jun, Dongsuk; Kim, Soojung; Choi, Wonchul; Kim, Junsoo; Zyung, Taehyoung; Jang, Moongyu

2015-10-01

We fabricated silicide/silicon hetero-junction structured thermoelectric device by CMOS process for the reduction of thermal conductivity with the scatterings of phonons at silicide/silicon interfaces. Electrical conductivities, Seebeck coefficients, power factors, and temperature differences are evaluated using the steady state analysis method. Platinum silicide/silicon multilayered structure showed an enhanced Seebeck coefficient and power factor characteristics, which was considered for p-leg element. Also, erbium silicide/silicon structure showed an enhanced Seebeck coefficient, which was considered for an n-leg element. Silicide/silicon multilayered structure is promising for thermoelectric applications by reducing thermal conductivity with an enhanced Seebeck coefficient. However, because of the high thermal conductivity of the silicon packing during thermal gradient is not a problem any temperature difference. Therefore, requires more testing and analysis in order to overcome this problem. Thermoelectric generators are devices that based on the Seebeck effect, convert temperature differences into electrical energy. Although thermoelectric phenomena have been used for heating and cooling applications quite extensively, it is only in recent years that interest has increased in energy generation.

High-Performance Ultrathin Organic-Inorganic Hybrid Silicon Solar Cells via Solution-Processed Interface Modification.

PubMed

Zhang, Jie; Zhang, Yinan; Song, Tao; Shen, Xinlei; Yu, Xuegong; Lee, Shuit-Tong; Sun, Baoquan; Jia, Baohua

2017-07-05

Organic-inorganic hybrid solar cells based on n-type crystalline silicon and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) exhibited promising efficiency along with a low-cost fabrication process. In this work, ultrathin flexible silicon substrates, with a thickness as low as tens of micrometers, were employed to fabricate hybrid solar cells to reduce the use of silicon materials. To improve the light-trapping ability, nanostructures were built on the thin silicon substrates by a metal-assisted chemical etching method (MACE). However, nanostructured silicon resulted in a large amount of surface-defect states, causing detrimental charge recombination. Here, the surface was smoothed by solution-processed chemical treatment to reduce the surface/volume ratio of nanostructured silicon. Surface-charge recombination was dramatically suppressed after surface modification with a chemical, associated with improved minority charge-carrier lifetime. As a result, a power conversion efficiency of 9.1% was achieved in the flexible hybrid silicon solar cells, with a substrate thickness as low as ∼14 μm, indicating that interface engineering was essential to improve the hybrid junction quality and photovoltaic characteristics of the hybrid devices.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

N-Type delta Doping of High-Purity Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Blacksberg, Jordana; Hoenk, Michael; Nikzad, Shouleh

2005-01-01

A process for n-type (electron-donor) delta doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays. Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac delta function (impulse function): the dopant is highly concentrated in a very thin layer. Preferably, the dopant is concentrated in one or at most two atomic layers in a crystal plane and, therefore, delta doping is also known as atomic-plane doping. The use of doping to enable detection of high-energy photons and low-energy particles was reported in several prior NASA Tech Briefs articles. As described in more detail in those articles, the main benefit afforded by delta doping of a back-illuminated silicon detector is to eliminate a "dead" layer at the back surface of the silicon wherein high-energy photons and low-energy particles are absorbed without detection. An additional benefit is that the delta-doped layer can serve as a back-side electrical contact. Delta doping of p-type silicon detectors is well established. The development of the present process addresses concerns specific to the delta doping of high-purity silicon detectors, which are typically n-type. The present process involves relatively low temperatures, is fully compatible with other processes used to fabricate the detectors, and does not entail interruption of those processes. Indeed, this process can be the last stage in the fabrication of an imaging detector that has, in all other respects, already been fully processed, including metallized. This process includes molecular-beam epitaxy (MBE) for deposition of three layers, including metallization. The success of the process depends on accurate temperature control, surface treatment, growth of high-quality crystalline silicon, and precise control of thicknesses of layers. MBE affords the necessary nanometer- scale control of the placement of atoms for delta doping. More specifically, the process consists of MBE deposition of a thin silicon buffer layer, the n-type delta doping layer, and a thin silicon cap layer. The n dopant selected for initial experiments was antimony, but other n dopants as (phosphorus or arsenic) could be used. All n-type dopants in silicon tend to surface-segregate during growth, leading to a broadened dopant-concentration- versus-depth profile. In order to keep the profile as narrow as possible, the substrate temperature is held below 300 C during deposition of the silicon cap layer onto the antimony delta layer. The deposition of silicon includes a silicon- surface-preparation step, involving H-termination, that enables the growth of high-quality crystalline silicon at the relatively low temperature with close to full electrical activation of donors in the surface layer.

Solid state laser applications in photovoltaics manufacturing

NASA Astrophysics Data System (ADS)

Dunsky, Corey; Colville, Finlay

2008-02-01

Photovoltaic energy conversion devices are on a rapidly accelerating growth path driven by increasing government and societal pressure to use renewable energy as part of an overall strategy to address global warming attributed to greenhouse gas emissions. Initially supported in several countries by generous tax subsidies, solar cell manufacturers are relentlessly pushing the performance/cost ratio of these devices in a quest to reach true cost parity with grid electricity. Clearly this eventual goal will result in further acceleration in the overall market growth. Silicon wafer based solar cells are currently the mainstay of solar end-user installations with a cost up to three times grid electricity. But next-generation technology in the form of thin-film devices promises streamlined, high-volume manufacturing and greatly reduced silicon consumption, resulting in dramatically lower per unit fabrication costs. Notwithstanding the modest conversion efficiency of thin-film devices compared to wafered silicon products (around 6-10% versus 15-20%), this cost reduction is driving existing and start-up solar manufacturers to switch to thin-film production. A key aspect of these devices is patterning large panels to create a monolithic array of series-interconnected cells to form a low current, high voltage module. This patterning is accomplished in three critical scribing processes called P1, P2, and P3. Lasers are the technology of choice for these processes, delivering the desired combination of high throughput and narrow, clean scribes. This paper examines these processes and discusses the optimization of industrial lasers to meet their specific needs.

Integration of mask and silicon metrology in DFM

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Sugiyama, Akiyuki; Toyoda, Yasutaka

2009-03-01

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Conductor-gap-silicon plasmonic waveguides and passive components at subwavelength scale.

PubMed

Wu, Marcelo; Han, Zhanghua; Van, Vien

2010-05-24

Subwavelength conductor-gap-silicon plasmonic waveguides along with compact S-bends and Y-splitters were theoretically investigated and experimentally demonstrated on a silicon-on-insulator platform. A thin SiO2 gap between the conductor layer and silicon core provides subwavelength confinement of light while a long propagation length of 40 microm was achieved. Coupling of light between the plasmonic and conventional silicon photonic waveguides was also demonstrated with a high efficiency of 80%. The compact sizes, low loss operation, efficient input/output coupling, combined with a CMOS-compatible fabrication process, make these conductor-gap-silicon plasmonic devices a promising platform for realizing densely-integrated plasmonic circuits.

Silicon-on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell-quality silicon was investigated. This was done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Significant progress in the following areas was demonstrated: (1) fabricating a 10 sq cm cell having 9.9 percent conversion efficiency; (2) producing a 225 sq cm layer of sheet silicon; and (3) obtaining 100 microns thick coatings at pull speed of 0.15 cm/sec, although approximately 50 percent of the layer exhibited dendritic growth.

Process for utilizing low-cost graphite substrates for polycrystalline solar cells

NASA Technical Reports Server (NTRS)

Chu, T. L. (Inventor)

1978-01-01

Low cost polycrystalline silicon solar cells supported on substrates were prepared by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical grade polycrystalline silicon, graphite and steel coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures thereof such that p-n junction devices were formed which effectively convert solar energy to electrical energy. To improve the conversion efficiency of the polycrystalline silicon solar cells, the crystallite size in the silicon was substantially increased by melting and solidifying a base layer of polycrystalline silicon before depositing the layers which form the p-n junction.

Solar cells utilizing pulsed-energy crystallized microcrystalline/polycrystalline silicon

DOEpatents

Kaschmitter, J.L.; Sigmon, T.W.

1995-10-10

A process for producing multi-terminal devices such as solar cells wherein a pulsed high energy source is used to melt and crystallize amorphous silicon deposited on a substrate which is intolerant to high processing temperatures, whereby the amorphous silicon is converted into a microcrystalline/polycrystalline phase. Dopant and hydrogenation can be added during the fabrication process which provides for fabrication of extremely planar, ultra shallow contacts which results in reduction of non-current collecting contact volume. The use of the pulsed energy beams results in the ability to fabricate high efficiency microcrystalline/polycrystalline solar cells on the so-called low-temperature, inexpensive plastic substrates which are intolerant to high processing temperatures.

Solar cells utilizing pulsed-energy crystallized microcrystalline/polycrystalline silicon

DOEpatents

Kaschmitter, James L.; Sigmon, Thomas W.

1995-01-01

A process for producing multi-terminal devices such as solar cells wherein a pulsed high energy source is used to melt and crystallize amorphous silicon deposited on a substrate which is intolerant to high processing temperatures, whereby to amorphous silicon is converted into a microcrystalline/polycrystalline phase. Dopant and hydrogenization can be added during the fabrication process which provides for fabrication of extremely planar, ultra shallow contacts which results in reduction of non-current collecting contact volume. The use of the pulsed energy beams results in the ability to fabricate high efficiency microcrystalline/polycrystalline solar cells on the so-called low-temperature, inexpensive plastic substrates which are intolerant to high processing temperatures.

Light Absorption Enhancement of Silicon-Based Photovoltaic Devices with Multiple Bandgap Structures of Porous Silicon

PubMed Central

Wu, Kuen-Hsien; Li, Chong-Wei

2015-01-01

Porous-silicon (PS) multi-layered structures with three stacked PS layers of different porosity were prepared on silicon (Si) substrates by successively tuning the electrochemical-etching parameters in an anodization process. The three PS layers have different optical bandgap energy and construct a triple-layered PS (TLPS) structure with multiple bandgap energy. Photovoltaic devices were fabricated by depositing aluminum electrodes of Schottky contacts on the surfaces of the developed TLPS structures. The TLPS-based devices exhibit broadband photoresponses within the spectrum of the solar irradiation and get high photocurrent for the incident light of a tungsten lamp. The improved spectral responses of devices are owing to the multi-bandgap structures of TLPS, which are designed with a layered configuration analog to a tandem cell for absorbing a wider energy range of the incidental sun light. The large photocurrent is mainly ascribed to an enhanced light-absorption ability as a result of applying nanoporous-Si thin films as the surface layers to absorb the short-wavelength light and to improve the Schottky contacts of devices. Experimental results reveal that the multi-bandgap PS structures produced from electrochemical-etching of Si wafers are potentially promising for development of highly efficient Si-based solar cells. PMID:28793542

Electronic pictures from charged-coupled devices

NASA Technical Reports Server (NTRS)

Mccann, D. H.; Turly, A. P.; White, M.

1979-01-01

Imaging system uses charge-coupled devices (CCD's) to generate TV-like pictures with high resolution, sensitivity, and signal-to-noise ratio. It combines detectors for five spectral bands as well as processing and control circuitry all on single silicon chip.

Replacement for Silicon Devices Looms Big With ORNL Discovery

ScienceCinema

Belianinov, Alex; Ovchinnikova, Olga

2018-05-22

Two-dimensional electronic devices could inch closer to their ultimate promise of low power, high efficiency and mechanical flexibility with a processing technique developed at the Department of Energy’s Oak Ridge National Laboratory.

Fabrication of ultra-high aspect ratio (>160:1) silicon nanostructures by using Au metal assisted chemical etching

NASA Astrophysics Data System (ADS)

Li, Hailiang; Ye, Tianchun; Shi, Lina; Xie, Changqing

2017-12-01

We present a facile and effective approach for fabricating high aspect ratio, dense and vertical silicon nanopillar arrays, using a combination of metal etching following electron-beam lithography and Au metal assisted chemical etching (MacEtch). Ti/Au nanostructures used as catalysts in MacEtch are formed by single layer resist-based electron-beam exposure followed by ion beam etching. The effects of MacEtch process parameters, including half period, etching time, the concentrations of H2O2 and HF, etching temperature and drying method are systematically investigated. Especially, we demonstrate an enhancement of etching quality by employing cold MacEtch process, and an enhancement in preventing the collapse of high aspect ratio nanostructures by employing low surface tension rinse liquid and natural evaporation in the drying stage. Using an optimized MacEtch process, vertical silicon nanopillar arrays with a period of 250 nm and aspect ratio up to 160:1 are realized. Our results should be instructive for exploring the achievable aspect ratio limit in silicon nanostructures and may find potential applications in photovoltaic devices, thermoelectric devices and x-ray diffractive optics.

High-aspect ratio micro- and nanostructures enabled by photo-electrochemical etching for sensing and energy harvesting applications

NASA Astrophysics Data System (ADS)

Alhalaili, Badriyah; Dryden, Daniel M.; Vidu, Ruxandra; Ghandiparsi, Soroush; Cansizoglu, Hilal; Gao, Yang; Saif Islam, M.

2018-03-01

Photo-electrochemical (PEC) etching can produce high-aspect ratio features, such as pillars and holes, with high anisotropy and selectivity, while avoiding the surface and sidewall damage caused by traditional deep reactive ion etching (DRIE) or inductively coupled plasma (ICP) RIE. Plasma-based techniques lead to the formation of dangling bonds, surface traps, carrier leakage paths, and recombination centers. In pursuit of effective PEC etching, we demonstrate an optical system using long wavelength (λ = 975 nm) infra-red (IR) illumination from a high-power laser (1-10 W) to control the PEC etching process in n-type silicon. The silicon wafer surface was patterned with notches through a lithography process and KOH etching. Then, PEC etching was introduced by illuminating the backside of the silicon wafer to enhance depth, resulting in high-aspect ratio structures. The effect of the PEC etching process was optimized by varying light intensities and electrolyte concentrations. This work was focused on determining and optimizing this PEC etching technique on silicon, with the goal of expanding the method to a variety of materials including GaN and SiC that are used in designing optoelectronic and electronic devices, sensors and energy harvesting devices.

Nucleation and atomic layer reaction in nickel silicide for defect-engineered Si nanochannels.

PubMed

Tang, Wei; Picraux, S Tom; Huang, Jian Yu; Gusak, Andriy M; Tu, King-Ning; Dayeh, Shadi A

2013-06-12

At the nanoscale, defects can significantly impact phase transformation processes and change materials properties. The material nickel silicide has been the industry standard electrical contact of silicon microelectronics for decades and is a rich platform for scientific innovation at the conjunction of materials and electronics. Its formation in nanoscale silicon devices that employ high levels of strain, intentional, and unintentional twins or grain boundaries can be dramatically different from the commonly conceived bulk processes. Here, using in situ high-resolution transmission electron microscopy (HRTEM), we capture single events during heterogeneous nucleation and atomic layer reaction of nickel silicide at various crystalline boundaries in Si nanochannels for the first time. We show through systematic experiments and analytical modeling that unlike other typical face-centered cubic materials such as copper or silicon the twin defects in NiSi2 have high interfacial energies. We observe that these twin defects dramatically change the behavior of new phase nucleation and can have direct implications for ultrascaled devices that are prone to defects or may utilize them to improve device performance.

Towards nanometer-spaced silicon contacts to proteins.

PubMed

Schukfeh, Muhammed I; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-18

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p(+) silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices' electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes' edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions' conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein's denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Photonic crystal nanocavity assisted rejection ratio tunable notch microwave photonic filter

PubMed Central

Long, Yun; Xia, Jinsong; Zhang, Yong; Dong, Jianji; Wang, Jian

2017-01-01

Driven by the increasing demand on handing microwave signals with compact device, low power consumption, high efficiency and high reliability, it is highly desired to generate, distribute, and process microwave signals using photonic integrated circuits. Silicon photonics offers a promising platform facilitating ultracompact microwave photonic signal processing assisted by silicon nanophotonic devices. In this paper, we propose, theoretically analyze and experimentally demonstrate a simple scheme to realize ultracompact rejection ratio tunable notch microwave photonic filter (MPF) based on a silicon photonic crystal (PhC) nanocavity with fixed extinction ratio. Using a conventional modulation scheme with only a single phase modulator (PM), the rejection ratio of the presented MPF can be tuned from about 10 dB to beyond 60 dB. Moreover, the central frequency tunable operation in the high rejection ratio region is also demonstrated in the experiment. PMID:28067332

Photonic crystal nanocavity assisted rejection ratio tunable notch microwave photonic filter

NASA Astrophysics Data System (ADS)

Long, Yun; Xia, Jinsong; Zhang, Yong; Dong, Jianji; Wang, Jian

2017-01-01

Driven by the increasing demand on handing microwave signals with compact device, low power consumption, high efficiency and high reliability, it is highly desired to generate, distribute, and process microwave signals using photonic integrated circuits. Silicon photonics offers a promising platform facilitating ultracompact microwave photonic signal processing assisted by silicon nanophotonic devices. In this paper, we propose, theoretically analyze and experimentally demonstrate a simple scheme to realize ultracompact rejection ratio tunable notch microwave photonic filter (MPF) based on a silicon photonic crystal (PhC) nanocavity with fixed extinction ratio. Using a conventional modulation scheme with only a single phase modulator (PM), the rejection ratio of the presented MPF can be tuned from about 10 dB to beyond 60 dB. Moreover, the central frequency tunable operation in the high rejection ratio region is also demonstrated in the experiment.

Photonic crystal nanocavity assisted rejection ratio tunable notch microwave photonic filter.

PubMed

Long, Yun; Xia, Jinsong; Zhang, Yong; Dong, Jianji; Wang, Jian

2017-01-09

Driven by the increasing demand on handing microwave signals with compact device, low power consumption, high efficiency and high reliability, it is highly desired to generate, distribute, and process microwave signals using photonic integrated circuits. Silicon photonics offers a promising platform facilitating ultracompact microwave photonic signal processing assisted by silicon nanophotonic devices. In this paper, we propose, theoretically analyze and experimentally demonstrate a simple scheme to realize ultracompact rejection ratio tunable notch microwave photonic filter (MPF) based on a silicon photonic crystal (PhC) nanocavity with fixed extinction ratio. Using a conventional modulation scheme with only a single phase modulator (PM), the rejection ratio of the presented MPF can be tuned from about 10 dB to beyond 60 dB. Moreover, the central frequency tunable operation in the high rejection ratio region is also demonstrated in the experiment.

Sleeve reaction chamber system

DOEpatents

Northrup, M Allen [Berkeley, CA; Beeman, Barton V [San Mateo, CA; Benett, William J [Livermore, CA; Hadley, Dean R [Manteca, CA; Landre, Phoebe [Livermore, CA; Lehew, Stacy L [Livermore, CA; Krulevitch, Peter A [Pleasanton, CA

2009-08-25

A chemical reaction chamber system that combines devices such as doped polysilicon for heating, bulk silicon for convective cooling, and thermoelectric (TE) coolers to augment the heating and cooling rates of the reaction chamber or chambers. In addition the system includes non-silicon-based reaction chambers such as any high thermal conductivity material used in combination with a thermoelectric cooling mechanism (i.e., Peltier device). The heat contained in the thermally conductive part of the system can be used/reused to heat the device, thereby conserving energy and expediting the heating/cooling rates. The system combines a micromachined silicon reaction chamber, for example, with an additional module/device for augmented heating/cooling using the Peltier effect. This additional module is particularly useful in extreme environments (very hot or extremely cold) where augmented heating/cooling would be useful to speed up the thermal cycling rates. The chemical reaction chamber system has various applications for synthesis or processing of organic, inorganic, or biochemical reactions, including the polymerase chain reaction (PCR) and/or other DNA reactions, such as the ligase chain reaction.

Electron-beam-induced information storage in hydrogenated amorphous silicon devices

DOEpatents

Yacobi, B.G.

1985-03-18

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge collection efficiency and thus in the charge collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Porous silicon technology for integrated microsystems

NASA Astrophysics Data System (ADS)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially rough surface on the porous silicon sample without introducing significant thermal stress. (Abstract shortened by UMI.)

Investigation of Oxygen and Hydrogen Associated Charge Trapping and Electrical Characteristics of Silicon Nitride Films for Mnos Devices.

NASA Astrophysics Data System (ADS)

Xu, Dan

Silicon nitride (Si_3N _4) and silicon oxynitride (SiO _{rm x}N_ {rm y}) films in the form of metal -nitride-oxide-silicon (MNOS) structures were investigated to determine the correlation between their electrical characteristics and the nature of the chemical bonding so as to provide guidelines for the next generation of nonvolatile memory devices. The photoionization cross section of electron traps in the oxynitride films of MNOS devices were also measured as a function photon energy and oxygen concentration of the silicon oxynitride films. An effective photoionization cross section associated with electron traps was determined to be between 4.9 times 10 ^{-19} cm^2 to 10.8 times 10^ {-19} cm^2 over the photon energy of 2.06 eV to 3.1 eV for silicon oxynitride films containing 7 atomic % to 17 atomic % of oxygen. The interface state density of metal-nitride-oxide -silicon (MNOS) devices was investigated as a function of processing conditions. The interface state density around the midgap of the oxide-silicon interface of the MNOS structures for deposition temperature between 650^ circC to 850^circC increased from 1.1 to 8.2 times 10 ^{11} cm^ {-2}eV^{-1}, for as-deposited silicon nitride films; but decreased from 5.0 to 3.5 times 10^ {11} cm^{-2} eV^{-1}, for films annealed in nitrogen at 900^circC for 60 minutes; and further decreased and remained constant at 1.5 times 10^{11 } cm^{-2}eV ^{-1}, for films which were further annealed in hydrogen at 900^ circC for an additional 60 minutes. The interface state density increase was due to an increase in the loss of hydrogen at the interfacial region and also due to an increase in the thermal stress caused by differences in thermal expansion coefficients of silicon nitride and silicon dioxide films at higher deposition temperatures. The interface state density was subject to two opposing influences; an increase by thermal stress, and a reduction by hydrogen compensation of these states. The photocurrent-voltage (photoI-V) technique in combination with internal photo-electric technique were employed to determine the trapped charge density and its centroid as a function of processing conditions. Results showed that the trapped charge density was of the order of 10^{18} cm ^{-3}. However, the charge trapping density increased about 30% as the atomic percentage of hydrogen decreased from 6 to 2 atomic %.

Vacuum Microelectronic Field Emission Array Devices for Microwave Amplification.

NASA Astrophysics Data System (ADS)

Mancusi, Joseph Edward

This dissertation presents the design, analysis, and measurement of vacuum microelectronic devices which use field emission to extract an electron current from arrays of silicon cones. The arrays of regularly-spaced silicon cones, the field emission cathodes or emitters, are fabricated with an integrated gate electrode which controls the electric field at the tip of the cone, and thus the electron current. An anode or collector electrode is placed above the array to collect the emission current. These arrays, which are fabricated in a standard silicon processing facility, are developed for use as high power microwave amplifiers. Field emission has been studied extensively since it was first characterized in 1928, however due to the large electric fields required practical field emission devices are difficult to make. With the development of the semiconductor industry came the development of fabrication equipment and techniques which allow for the manufacture of the precision micron-scale structures necessary for practical field emission devices. The active region of a field emission device is a vacuum, therefore the electron travel is ballistic. This analysis of field emission devices includes electric field and electron emission modeling, development of a device equivalent circuit, analysis of the parameters in the equivalent circuit, and device testing. Variations in device structure are taken into account using a statistical model based upon device measurements. Measurements of silicon field emitter arrays at DC and RF are presented and analyzed. In this dissertation, the equivalent circuit is developed from the analysis of the device structure. The circuit parameters are calculated from geometrical considerations and material properties, or are determined from device measurements. It is necessary to include the emitter resistance in the equivalent circuit model since relatively high resistivity silicon wafers are used. As is demonstrated, the circuit model accurately predicts the magnitude of the emission current at a number of typical bias current levels when the device is operating at frequencies within the range of 10 MHz to 1 GHz. At low frequencies and at high frequencies within this range, certain parameters are negligible, and simplifications may be made in the equivalent circuit model.

Fabrication of a Cryogenic Terahertz Emitter for Bolometer Focal Plane Calibrations

NASA Technical Reports Server (NTRS)

Chervenak, James; Brown, Ari; Wollack, Edward

2012-01-01

A fabrication process is reported for prototype emitters of THz radiation, which operate cryogenically, and should provide a fast, stable blackbody source suitable for characterization of THz devices. The fabrication has been demonstrated and, at the time of this reporting, testing was underway. The emitter is similar to a monolithic silicon bolometer in design, using both a low-noise thermometer and a heater element on a thermally isolated stage. An impedance-matched, high-emissivity coat ing is also integrated to tune the blackbody properties. This emitter is designed to emit a precise amount of power as a blackbody spectrum centered on terahertz frequencies. The emission is a function of the blackbody temperature. An integrated resistive heater and thermometer system can control the temperature of the blackbody with greater precision than previous incarnations of calibration sources that relied on blackbody emission. The emitter is fabricated using a silicon- on-insulator substrate wafer. The buried oxide is chosen to be less than 1 micron thick, and the silicon device thickness is 1-2 microns. Layers of phosphorus compensated with boron are implanted into and diffused throughout the full thickness of the silicon device layer to create the thermometer and heater components. Degenerately doped wiring is implanted to connect the devices to wire-bondable contact pads at the edge of the emitter chip. Then the device is micromachined to remove the thick-handle silicon behind the thermometer and heater components, and to thermally isolate it on a silicon membrane. An impedance- matched emissive coating (ion assisted evaporated Bi) is applied to the back of the membrane to enable high-efficiency emission of the blackbody spectrum.

Laser desorption ionization and peptide sequencing on laser induced silicon microcolumn arrays

DOEpatents

Vertes, Akos [Reston, VA; Chen, Yong [San Diego, CA

2011-12-27

The present invention provides a method of producing a laser-patterned silicon surface, especially silicon wafers for use in laser desorption ionization (LDI-MS) (including MALDI-MS and SELDI-MS), devices containing the same, and methods of testing samples employing the same. The surface is prepared by subjecting a silicon substrate to multiple laser shots from a high-power picosecond or femtosecond laser while in a processing environment, e.g., underwater, and generates a remarkable homogenous microcolumn array capable of providing an improved substrate for LDI-MS.

An all-silicon passive optical diode.

PubMed

Fan, Li; Wang, Jian; Varghese, Leo T; Shen, Hao; Niu, Ben; Xuan, Yi; Weiner, Andrew M; Qi, Minghao

2012-01-27

A passive optical diode effect would be useful for on-chip optical information processing but has been difficult to achieve. Using a method based on optical nonlinearity, we demonstrate a forward-backward transmission ratio of up to 28 decibels within telecommunication wavelengths. Our device, which uses two silicon rings 5 micrometers in radius, is passive yet maintains optical nonreciprocity for a broad range of input power levels, and it performs equally well even if the backward input power is higher than the forward input. The silicon optical diode is ultracompact and is compatible with current complementary metal-oxide semiconductor processing.

Design, fabrication and characterization of a poly-silicon PN junction

NASA Astrophysics Data System (ADS)

Tower, Jason D.

This thesis details the design, fabrication, and characterization of a PN junction formed from p-type mono-crystalline silicon and n-type poly-crystalline silicon. The primary product of this project was a library of standard operating procedures (SOPs) for the fabrication of such devices, laying the foundations for future work and the development of a class in fabrication processes. The fabricated PN junction was characterized; in particular its current-voltage relationship was measured and fit to models. This characterization was to determine whether or not the fabrication process could produce working PN junctions with acceptable operational parameters.

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Surface Participation Effects in Titanium Nitride and Niobium Resonators

NASA Astrophysics Data System (ADS)

Dove, Allison; Kreikebaum, John Mark; Livingston, William; Delva, Remy; Qiu, Yanjie; Lolowang, Reinhard; Ramasesh, Vinay; O'Brien, Kevin; Siddiqi, Irfan

Improving the coherence time of superconducting qubits requires a precise understanding of the location and density of surface defects. Superconducting microwave resonators are commonly used for quantum state readout and are a versatile testbed to systematically characterize materials properties as a function of device geometry and fabrication method. We report on sputter deposited titanium nitride and niobium on silicon coplanar waveguide resonators patterned using reactive ion etches to define the device geometry. We discuss the impact of different growth conditions (temperature and electrical bias) and processing techniques on the internal quality factor (Q) of these devices. In particular, to investigate the effect of surface participation, we use a Bosch process to etch many-micron-deep trenches in the silicon substrate and quantify the impact of etch depth and profile on the internal Q. This research was supported by the ARO.

Silicon on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Pickering, C.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon was investigated. It was hoped this could be done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Work was directed towards the solution of unique cell processing/design problems encountered with the silicon-ceramic (SOC) material due to its intimate contact with the ceramic substrate. Significant progress was demonstrated in the following areas; (1) the continuous coater succeeded in producing small-area coatings exhibiting unidirectional solidification and substatial grain size; (2) dip coater succeeded in producing thick (more than 500 micron) dendritic layers at coating speeds of 0.2-0.3 cm/sec; and (3) a standard for producing total area SOC solar cells using slotted ceramic substrates was developed.

Electron-beam-induced information storage in hydrogenated amorphous silicon device

DOEpatents

Yacobi, Ben G.

1986-01-01

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge-collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge-collection efficiency; and thus in the charge-collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage, in the device, which darkened areas can be restored to their original charge-collection efficiency by heating the hydrogenated amorphous silicon to a temperature of about 100.degree. C. to 250.degree. C. for a sufficient period of time to provide for such restoration.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Silicon carbide, a semiconductor for space power electronics

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Matus, Lawrence G.

1991-01-01

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

REVIEW ARTICLE: How will physics be involved in silicon microelectronics

NASA Astrophysics Data System (ADS)

Kamarinos, Georges; Felix, Pierre

1996-03-01

By the year 2000 electronics will probably be the basis of the largest industry in the world. Silicon microelectronics will continue to keep a dominant place covering 99% of the `semiconductor market'. The aim of this review article is to indicate for the next decade the domains in which research work in `physics' is needed for a technological advance towards increasing speed, complexity and density of silicon ultra large scale integration (ULSI) integrated circuits (ICs). By `physics' we mean here not only condensed matter physics but also the basic physical chemistry and thermodynamics. The review begins with a brief and general introduction in which we elucidate the current state of the art and the trends in silicon microelectronics. Afterwards we examine the involvement of physics in silicon microelectronics in the two main sections. The first section concerns the processes of fabrication of ICs: lithography, oxidation, diffusion, chemical and physical vapour deposition, rapid thermal processing, etching, interconnections, ultra-clean processing and microcontamination. The second section concerns the electrical operation of the ULSI devices. It defines the integration scales and points out the importance of the intermediate scale of integration which is the scale of the next generation of ICs. The emergence of cryomicroelectronics is also reviewed and an extended paragraph is dedicated to the problem of reliability and ageing of devices and ICs: hot carrier degradation, interdevice coupling and noise are considered. It is shown, during our analysis, that the next generation of silicon ICs needs mainly: (i) `scientific' fabrication and (ii) microscopic modelling and simulation of the electrical characteristics of the scaled down devices. To attain the above objectives a return to the `first principles' of physics as well as a recourse to nonlinear and non-equilibrium thermodynamics are mandatory. In the references we list numerous review papers and references of specialized colloquia proceedings so that a more detailed survey of the subject is possible for the reader.

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

NASA Astrophysics Data System (ADS)

Kim, Jong Cheol; Kim, Jongsik; Xin, Yan; Lee, Jinhyung; Kim, Young-Gyun; Subhash, Ghatu; Singh, Rajiv K.; Arjunan, Arul C.; Lee, Haigun

2018-05-01

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (˜3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

Roll up nanowire battery from silicon chips

PubMed Central

Vlad, Alexandru; Reddy, Arava Leela Mohana; Ajayan, Anakha; Singh, Neelam; Gohy, Jean-François; Melinte, Sorin; Ajayan, Pulickel M.

2012-01-01

Here we report an approach to roll out Li-ion battery components from silicon chips by a continuous and repeatable etch-infiltrate-peel cycle. Vertically aligned silicon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as Li+ gel-electrolyte and electrode separator and peeled off to make multiple battery devices out of a single wafer. Porous, electrically interconnected copper nanoshells are conformally deposited around the silicon nanowires to stabilize the electrodes over extended cycles and provide efficient current collection. Using the above developed process we demonstrate an operational full cell 3.4 V lithium-polymer silicon nanowire (LIPOSIL) battery which is mechanically flexible and scalable to large dimensions. PMID:22949696

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

PubMed

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

Hybrid integration of carbon nanotubes in silicon photonic structures

NASA Astrophysics Data System (ADS)

Durán-Valdeiglesias, E.; Zhang, W.; Alonso-Ramos, C.; Le Roux, X.; Serna, S.; Hoang, H. C.; Marris-Morini, D.; Cassan, E.; Intonti, F.; Sarti, F.; Caselli, N.; La China, F.; Gurioli, M.; Balestrieri, M.; Vivien, L.; Filoramo, A.

2017-02-01

Silicon photonics, due to its compatibility with the CMOS platform and unprecedented integration capability, has become the preferred solution for the implementation of next generation optical interconnects to accomplish high efficiency, low energy consumption, low cost and device miniaturization in one single chip. However, it is restricted by silicon itself. Silicon does not have efficient light emission or detection in the telecommunication wavelength range (1.3 μm-1.5 μm) or any electro-optic effect (i.e. Pockels effect). Hence, silicon photonic needs to be complemented with other materials for the realization of optically-active devices, including III-V for lasing and Ge for detection. The very different requirement of these materials results in complex fabrication processes that offset the cost-effectiveness of the Si photonics approach. For this purpose, carbon nanotubes (CNTs) have recently been proposed as an attractive one-dimensional light emitting material. Interestingly, semiconducting single walled CNTs (SWNTs) exhibit room-temperature photo- and electro-luminescence in the near-IR that could be exploited for the implementation of integrated nano-sources. They can also be considered for the realization of photo-detectors and optical modulators, since they rely on intrinsically fast non-linear effects, such as Stark and Kerr effect. All these properties make SWNTs ideal candidates in order to fabricate a large variety of optoelectronic devices, including near-IR sources, modulators and photodetectors on Si photonic platforms. In addition, solution processed SWNTs can be integrated on Si using spin-coating or drop-casting techniques, obviating the need of complex epitaxial growth or chip bonding approaches. Here, we report on our recent progress in the coupling of SWNTs light emission into optical resonators implemented on the silicon-on-insulator (SOI) platform. .

Silicon Integrated Optics: Fabrication and Characterization

NASA Astrophysics Data System (ADS)

Shearn, Michael Joseph, II

For decades, the microelectronics industry has sought integration and miniaturization as canonized in Moore's Law, and has continued doubling transistor density about every two years. However, further miniaturization of circuit elements is creating a bandwidth problem as chip interconnect wires shrink as well. A potential solution is the creation of an on-chip optical network with low delays that would be impossible to achieve using metal buses. However, this technology requires integrating optics with silicon microelectronics. The lack of efficient silicon optical sources has stymied efforts of an all-Si optical platform. Instead, the integration of efficient emitter materials, such as III-V semiconductors, with Si photonic structures is a low-cost, CMOS-compatible alternative platform. This thesis focuses on making and measuring on-chip photonic structures suitable for on-chip optical networking. The first part of the thesis assesses processing techniques of silicon and other semiconductor materials. Plasmas for etching and surface modification are described and used to make bonded, hybrid Si/III-V structures. Additionally, a novel masking method using gallium implantation into silicon for pattern definition is characterized. The second part of the thesis focuses on demonstrations of fabricated optical structures. A dense array of silicon devices is measured, consisting of fully-etched grating couplers, low-loss waveguides and ring resonators. Finally, recent progress in the Si/III-V hybrid system is discussed. Supermode control of devices is described, which uses changing Si waveguide width to control modal overlap with the gain material. Hybrid Si/III-V, Fabry-Perot evanescent lasers are demonstrated, utilizing a CMOS-compatible process suitable for integration on in electronics platforms. Future prospects and ultimate limits of Si devices and the hybrid Si/III-V system are also considered.

Strain-Induced Spin-Resonance Shifts in Silicon Devices

NASA Astrophysics Data System (ADS)

Pla, J. J.; Bienfait, A.; Pica, G.; Mansir, J.; Mohiyaddin, F. A.; Zeng, Z.; Niquet, Y. M.; Morello, A.; Schenkel, T.; Morton, J. J. L.; Bertet, P.

2018-04-01

In spin-based quantum-information-processing devices, the presence of control and detection circuitry can change the local environment of a spin by introducing strain and electric fields, altering its resonant frequencies. These resonance shifts can be large compared to intrinsic spin linewidths, and it is therefore important to study, understand, and model such effects in order to better predict device performance. We investigate a sample of bismuth donor spins implanted in a silicon chip, on top of which a superconducting aluminum microresonator is fabricated. The on-chip resonator provides two functions: it produces local strain in the silicon due to the larger thermal contraction of the aluminum, and it enables sensitive electron spin-resonance spectroscopy of donors close to the surface that experience this strain. Through finite-element strain simulations, we are able to reconstruct key features of our experiments, including the electron spin-resonance spectra. Our results are consistent with a recently observed mechanism for producing shifts of the hyperfine interaction for donors in silicon, which is linear with the hydrostatic component of an applied strain.

A hybrid silicon membrane spatial light modulator for optical information processing

NASA Technical Reports Server (NTRS)

Pape, D. R.; Hornbeck, L. J.

1984-01-01

A new two dimensional, fast, analog, electrically addressable, silicon based membrane spatial light modulator (SLM) was developed for optical information processing applications. Coherent light reflected from the mirror elements is phase modulated producing an optical Fourier transform of an analog signal input to the device. The DMD architecture and operating parameters related to this application are presented. A model is developed that describes the optical Fourier transform properties of the DMD.

Fundamental Studies of the Mechanical Behavior of Microelectronic Thin Film Materials

DTIC Science & Technology

1991-01-01

scanning, wafer curvature technique to study the kinetics of crystallization of amorphous silicon. When a thin film of amorphous silicon crystallizes...the film and the kinetics of the crystallization process. We find the tensile stress in the film to increase by about 500 MPa when crystallization...occurs. This is a very large stress that could have significance for device processing and applications. By measuring the kinetics of this stress change

Technological processes of grating light valve as diffractive spatial light modulator in laser phototypesetting system

NASA Astrophysics Data System (ADS)

Zhang, Wei; Geng, Yu; Hou, Changlun; Yang, Guoguang; Bai, Jian

2008-11-01

Grating Light Valve (GLV) is a kind of optics device based on Micro-Opto-Electro-Mechanical System (MOEMS) technology, utilizing diffraction principle to switch, attenuate and modulate light. In this paper, traditional GLV device's structure and its working principle are illuminated, and a kind of modified GLV structure is presented, with details introduction of the fabrication technology. The GLV structure includes single crystal silicon substrate, silicon dioxide isolating layer, aluminum layer of fixed ribbons and silicon nitride of movable ribbons. In the fabrication, lots of techniques are adopted, such as low-pressure chemical vapor deposition (LPCVD), photolithography, etching and evaporation. During the fabrication processes, Photolithography is a fundamental and fatal technology, which determines etching result and GLV quality. Some methods are proposed through repeated experiments, to improve etching result greatly and guide the practical application. This kind of GLV device can be made both small and inexpensively, and has been tested to show proper range of actuation under DC bias, with good performance. The GLV device also has merits such as low cost, simple technology, high fill ratio and low driving voltage. It can properly be well used and match the demands of high light power needed in laser phototypesetting system, as a high-speed, high-resolution light modulator.

On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

NASA Astrophysics Data System (ADS)

Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

2018-04-01

The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

Very high-cycle fatigue failure in micron-scale polycrystalline silicon films: Effects of environment and surface oxide thickness

NASA Astrophysics Data System (ADS)

Alsem, D. H.; Timmerman, R.; Boyce, B. L.; Stach, E. A.; De Hosson, J. Th. M.; Ritchie, R. O.

2007-01-01

Fatigue failure in micron-scale polycrystalline silicon structural films, a phenomenon that is not observed in bulk silicon, can severely impact the durability and reliability of microelectromechanical system devices. Despite several studies on the very high-cycle fatigue behavior of these films (up to 1012cycles), there is still an on-going debate on the precise mechanisms involved. We show here that for devices fabricated in the multiuser microelectromechanical system process (MUMPs) foundry and Sandia Ultra-planar, Multi-level MEMS Technology (SUMMiT V™) process and tested under equi-tension/compression loading at ˜40kHz in different environments, stress-lifetime data exhibit similar trends in fatigue behavior in ambient room air, shorter lifetimes in higher relative humidity environments, and no fatigue failure at all in high vacuum. The transmission electron microscopy of the surface oxides in the test samples shows a four- to sixfold thickening of the surface oxide at stress concentrations after fatigue failure, but no thickening after overload fracture in air or after fatigue cycling in vacuo. We find that such oxide thickening and premature fatigue failure (in air) occur in devices with initial oxide thicknesses of ˜4nm (SUMMiT V™) as well as in devices with much thicker initial oxides ˜20nm (MUMPs). Such results are interpreted and explained by a reaction-layer fatigue mechanism. Specifically, moisture-assisted subcritical cracking within a cyclic stress-assisted thickened oxide layer occurs until the crack reaches a critical size to cause catastrophic failure of the entire device. The entirety of the evidence presented here strongly indicates that the reaction-layer fatigue mechanism is the governing mechanism for fatigue failure in micron-scale polycrystalline silicon thin films.

Determination of a Definition of Solar Grade Silicon

NASA Technical Reports Server (NTRS)

Hill, D. E.; Gutsche, H. W.

1975-01-01

A definition of solar grade silicon was determined by investigating the singular and the combined effect of the impurities usually found in metallurgical grade silicon on solar cell device performance. The impurity matrix was defined by Jet Propulsion Laboratory Technical Direction Memorandum. The initial work was focussed on standardizing the solar cell process and test procedure, growing baseline crystals, growing crystals contaminated with carbon, iron, nickel, zirconium, aluminum and vanadium, solar blank preparation, and material characterization.

Athermal Annealing of Silicon

NASA Astrophysics Data System (ADS)

Fischer, R. P.; Grun, J.; Ting, A.; Felix, C.; Peckerar, M.; Fatemi, M.; Manka, C. K.

1999-11-01

Current semiconductor annealing methods are based on thermal processes which are accompanied by diffusion that degrades the definition of device features or causes other problems. This will be a serious obstacle for the production of next-generation ultra-high density, low power semiconductor devices. Experiments underway at NRL utilize a new annealing method which is much faster than thermal annealing and does not depend upon thermal energy (J. Grun, et al)., Phys. Rev. Letters 78, 1584 (1997).. A 10 J, 30 nsec, 1.053 nm wavelength laser pulse is focussed to approximately 1 mm diameter on a silicon sample. Acoustic and shock waves propagate from the impact region, which deposit mechanical energy into the material and anneal the silicon. Experimental results will be presented on annealing neutron-transmutation-doped (NTD) and ion implanted silicon samples with impurity concentrations from 1 × 10^15-3 × 10^20/cm^3.

Probing Photocurrent Nonuniformities in the Subcells of Monolithic Perovskite/Silicon Tandem Solar Cells.

PubMed

Song, Zhaoning; Werner, Jérémie; Shrestha, Niraj; Sahli, Florent; De Wolf, Stefaan; Niesen, Björn; Watthage, Suneth C; Phillips, Adam B; Ballif, Christophe; Ellingson, Randy J; Heben, Michael J

2016-12-15

Perovskite/silicon tandem solar cells with high power conversion efficiencies have the potential to become a commercially viable photovoltaic option in the near future. However, device design and optimization is challenging because conventional characterization methods do not give clear feedback on the localized chemical and physical factors that limit performance within individual subcells, especially when stability and degradation is a concern. In this study, we use light beam induced current (LBIC) to probe photocurrent collection nonuniformities in the individual subcells of perovskite/silicon tandems. The choices of lasers and light biasing conditions allow efficiency-limiting effects relating to processing defects, optical interference within the individual cells, and the evolution of water-induced device degradation to be spatially resolved. The results reveal several types of microscopic defects and demonstrate that eliminating these and managing the optical properties within the multilayer structures will be important for future optimization of perovskite/silicon tandem solar cells.

Improved Starting Materials for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials. Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes: a) A device layer on the front side, typically between 2 and 20 m thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron); b) A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 m thick; and c) A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 m thick. After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

Custom 3D Printable Silicones with Tunable Stiffness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Durban, Matthew M.; Lenhardt, Jeremy M.; Wu, Amanda S.

Silicone elastomers have broad versatility within a variety of potential advanced materials applications, such as soft robotics, biomedical devices, and metamaterials. Furthermore, a series of custom 3D printable silicone inks with tunable stiffness is developed, formulated, and characterized. The silicone inks exhibit excellent rheological behavior for 3D printing, as observed from the printing of porous structures with controlled architectures. Here, the capability to tune the stiffness of printable silicone materials via careful control over the chemistry, network formation, and crosslink density of the ink formulations in order to overcome the challenging interplay between ink development, post-processing, material properties, and performancemore » is demonstrated.« less

Custom 3D Printable Silicones with Tunable Stiffness

DOE PAGES

Durban, Matthew M.; Lenhardt, Jeremy M.; Wu, Amanda S.; ...

2017-12-06

Silicone elastomers have broad versatility within a variety of potential advanced materials applications, such as soft robotics, biomedical devices, and metamaterials. Furthermore, a series of custom 3D printable silicone inks with tunable stiffness is developed, formulated, and characterized. The silicone inks exhibit excellent rheological behavior for 3D printing, as observed from the printing of porous structures with controlled architectures. Here, the capability to tune the stiffness of printable silicone materials via careful control over the chemistry, network formation, and crosslink density of the ink formulations in order to overcome the challenging interplay between ink development, post-processing, material properties, and performancemore » is demonstrated.« less

Silicon deposition in nanopores using a liquid precursor.

PubMed

Masuda, Takashi; Tatsuda, Narihito; Yano, Kazuhisa; Shimoda, Tatsuya

2016-11-22

Techniques for depositing silicon into nanosized spaces are vital for the further scaling down of next-generation devices in the semiconductor industry. In this study, we filled silicon into 3.5-nm-diameter nanopores with an aspect ratio of 70 by exploiting thermodynamic behaviour based on the van der Waals energy of vaporized cyclopentasilane (CPS). We originally synthesized CPS as a liquid precursor for semiconducting silicon. Here we used CPS as a gas source in thermal chemical vapour deposition under atmospheric pressure because vaporized CPS can fill nanopores spontaneously. Our estimation of the free energy of CPS based on Lifshitz van der Waals theory clarified the filling mechanism, where CPS vapour in the nanopores readily undergoes capillary condensation because of its large molar volume compared to those of other vapours such as water, toluene, silane, and disilane. Consequently, a liquid-specific feature was observed during the deposition process; specifically, condensed CPS penetrated into the nanopores spontaneously via capillary force. The CPS that filled the nanopores was then transformed into solid silicon by thermal decomposition at 400 °C. The developed method is expected to be used as a nanoscale silicon filling technology, which is critical for the fabrication of future quantum scale silicon devices.

Silicon deposition in nanopores using a liquid precursor

NASA Astrophysics Data System (ADS)

Masuda, Takashi; Tatsuda, Narihito; Yano, Kazuhisa; Shimoda, Tatsuya

2016-11-01

Techniques for depositing silicon into nanosized spaces are vital for the further scaling down of next-generation devices in the semiconductor industry. In this study, we filled silicon into 3.5-nm-diameter nanopores with an aspect ratio of 70 by exploiting thermodynamic behaviour based on the van der Waals energy of vaporized cyclopentasilane (CPS). We originally synthesized CPS as a liquid precursor for semiconducting silicon. Here we used CPS as a gas source in thermal chemical vapour deposition under atmospheric pressure because vaporized CPS can fill nanopores spontaneously. Our estimation of the free energy of CPS based on Lifshitz van der Waals theory clarified the filling mechanism, where CPS vapour in the nanopores readily undergoes capillary condensation because of its large molar volume compared to those of other vapours such as water, toluene, silane, and disilane. Consequently, a liquid-specific feature was observed during the deposition process; specifically, condensed CPS penetrated into the nanopores spontaneously via capillary force. The CPS that filled the nanopores was then transformed into solid silicon by thermal decomposition at 400 °C. The developed method is expected to be used as a nanoscale silicon filling technology, which is critical for the fabrication of future quantum scale silicon devices.

Materials Development for Auxiliary Components for Large Compact Mo/Au TES Arrays

NASA Technical Reports Server (NTRS)

Finkbeiner, F. m.; Chervenak, J. A.; Bandler, S. R.; Brekosky, R.; Brown, A. D.; Figueroa-Feliciano, E.; Iyomoto, N.; Kelley, R. L.; Kilbourne, C. A.; Porter, F. S.;

A flexible piezoresistive carbon black network in silicone rubber for wide range deformation and strain sensing

NASA Astrophysics Data System (ADS)

Zhu, Jianxiong; Wang, Hai; Zhu, Yali

2018-01-01

This work presents the design, fabrication, and measurement of a piezoresistive device with a carbon black (CB) particle network in a highly flexible silicone rubber for large deformation and wide range strain sensing. The piezoresistive composite film was fabricated with a mixture of silicone rubber and CB filler particles. The test results showed that the CB particle network in the silicone rubber strongly affected the resistance of the device during the process of drawing and its recovery. We found that the 50% volume ratio of CB filler particles showed a lower relative resistance than the 33.3% volume ratio of CB filler particles, but with an advantage of good resistance recovery stability and a smaller perturbation error (smaller changed resistance) during the periodic back and forth linear motor test. With both having a 50% volume ratio of CB filler particles and a 33.3% volume ratio of CB filler particles, one can reach up to 200% strain with resistances 18 kΩ and 110 kΩ, respectively. We also found that the relative resistance increased in an approximately linear relationship corresponding to the value of step-increased instantaneous length for the reported device. Moreover, an application test through hand drawing was used to demonstrate the piezoresistive performance of the device, which showed that the reported device was capable of measuring the instantaneous length with large deformation.

Spike train generation and current-to-frequency conversion in silicon diodes

NASA Technical Reports Server (NTRS)

Coon, D. D.; Perera, A. G. U.

1989-01-01

A device physics model is developed to analyze spontaneous neuron-like spike train generation in current driven silicon p(+)-n-n(+) devices in cryogenic environments. The model is shown to explain the very high dynamic range (0 to the 7th) current-to-frequency conversion and experimental features of the spike train frequency as a function of input current. The devices are interesting components for implementation of parallel asynchronous processing adjacent to cryogenically cooled focal planes because of their extremely low current and power requirements, their electronic simplicity, and their pulse coding capability, and could be used to form the hardware basis for neural networks which employ biologically plausible means of information coding.

Development of silicon carbide semiconductor devices for high temperature applications

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony; Petit, Jeremy B.

1991-01-01

The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

Nanostructured Silicon Used for Flexible and Mobile Electricity Generation.

PubMed

Sun, Baoquan; Shao, Mingwang; Lee, Shuitong

2016-12-01

The use of nanostructured silicon for the generation of electricity in flexible and mobile devices is reviewed. This field has attracted widespread interest in recent years due to the emergence of plastic electronics. Such developments are likely to alter the nature of power sources in the near future. For example, flexible photovoltaic cells can supply electricity to rugged and collapsible electronics, biomedical devices, and conformable solar panels that are integrated with the curved surfaces of vehicles or buildings. Here, the unique optical and electrical properties of nanostructured silicon are examined, with regard to how they can be exploited in flexible photovoltaics, thermoelectric generators, and piezoelectric devices, which serve as power generators. Particular emphasis is placed on organic-silicon heterojunction photovoltaic devices, silicon-nanowire-based thermoelectric generators, and core-shell silicon/silicon oxide nanowire-based piezoelectric devices, because they are flexible, lightweight, and portable. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nanophotonic applications for silicon-on-insulator (SOI)

NASA Astrophysics Data System (ADS)

de la Houssaye, Paul R.; Russell, Stephen D.; Shimabukuro, Randy L.

2004-07-01

Silicon-on-insulator is a proven technology for very large scale integration of microelectronic devices. The technology also offers the potential for development of nanophotonic devices and the ability to interface such devices to the macroscopic world. This paper will report on fabrication techniques used to form nano-structured silicon wires on an insulating structure that is amenable to interfacing nanostructured sensors with high-performance microelectronic circuitry for practical implementation. Nanostructures formed on silicon-on-sapphire can also exploit the transparent substrate for novel device geometries. This research harnesses the unique properties of a high-quality single crystal film of silicon on sapphire and uses the film thickness as one of the confinement dimensions. Lateral arrays of silicon nanowires were fabricated in the thin (5 to 20 nm) silicon layer and studied. This technique offers simplified contact to individual wires and provides wire surfaces that are more readily accessible for controlled alteration and device designs.

FSA future directions: FSA technology activities in FY86

NASA Technical Reports Server (NTRS)

Leipold, M. H.

1985-01-01

The silicon material, advanced silicon sheet, device research, and process research activities are explained. There will be no new initiatives. Many activities are targeted for completion and the emphasis will then be on technology transfer. Industrial development of the fluidized-bed reactor (FBR) deposition technology is proceeding. Technology transfer and industry funding of sheet development are continuing.

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

NASA Astrophysics Data System (ADS)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive electro-optic characterization of these components will be presented.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Review: Semiconductor Piezoresistance for Microsystems.

PubMed

Barlian, A Alvin; Park, Woo-Tae; Mallon, Joseph R; Rastegar, Ali J; Pruitt, Beth L

2009-01-01

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

Use of silicon oxynitride as a sacrificial material for microelectromechanical devices

DOEpatents

Habermehl, Scott D.; Sniegowski, Jeffry J.

2001-01-01

The use of silicon oxynitride (SiO.sub.x N.sub.y) as a sacrificial material for forming a microelectromechanical (MEM) device is disclosed. Whereas conventional sacrificial materials such as silicon dioxide and silicate glasses are compressively strained, the composition of silicon oxynitride can be selected to be either tensile-strained or substantially-stress-free. Thus, silicon oxynitride can be used in combination with conventional sacrificial materials to limit an accumulation of compressive stress in a MEM device; or alternately the MEM device can be formed entirely with silicon oxynitride. Advantages to be gained from the use of silicon oxynitride as a sacrificial material for a MEM device include the formation of polysilicon members that are substantially free from residual stress, thereby improving the reliability of the MEM device; an ability to form the MEM device with a higher degree of complexity and more layers of structural polysilicon than would be possible using conventional compressively-strained sacrificial materials; and improved manufacturability resulting from the elimination of wafer distortion that can arise from an excess of accumulated stress in conventional sacrificial materials. The present invention is useful for forming many different types of MEM devices including accelerometers, sensors, motors, switches, coded locks, and flow-control devices, with or without integrated electronic circuitry.

Fabrication Process of Silicone-based Dielectric Elastomer Actuators

PubMed Central

Rosset, Samuel; Araromi, Oluwaseun A.; Schlatter, Samuel; Shea, Herbert R.

2016-01-01

This contribution demonstrates the fabrication process of dielectric elastomer transducers (DETs). DETs are stretchable capacitors consisting of an elastomeric dielectric membrane sandwiched between two compliant electrodes. The large actuation strains of these transducers when used as actuators (over 300% area strain) and their soft and compliant nature has been exploited for a wide range of applications, including electrically tunable optics, haptic feedback devices, wave-energy harvesting, deformable cell-culture devices, compliant grippers, and propulsion of a bio-inspired fish-like airship. In most cases, DETs are made with a commercial proprietary acrylic elastomer and with hand-applied electrodes of carbon powder or carbon grease. This combination leads to non-reproducible and slow actuators exhibiting viscoelastic creep and a short lifetime. We present here a complete process flow for the reproducible fabrication of DETs based on thin elastomeric silicone films, including casting of thin silicone membranes, membrane release and prestretching, patterning of robust compliant electrodes, assembly and testing. The membranes are cast on flexible polyethylene terephthalate (PET) substrates coated with a water-soluble sacrificial layer for ease of release. The electrodes consist of carbon black particles dispersed into a silicone matrix and patterned using a stamping technique, which leads to precisely-defined compliant electrodes that present a high adhesion to the dielectric membrane on which they are applied. PMID:26863283

Germanium: From Its Discovery to SiGe Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haller, E.E.

2006-06-14

Germanium, element No.32, was discovered in 1886 by Clemens Winkler. Its first broad application was in the form of point contact Schottky diodes for radar reception during WWII. The addition of a closely spaced second contact led to the first all-solid-state electronic amplifier device, the transistor. The relatively low bandgap, the lack of a stable oxide and large surface state densities relegated germanium to the number 2 position behind silicon. The discovery of the lithium drift process, which made possible the formation of p-i-n diodes with fully depletable i-regions several centimeters thick, led germanium to new prominence as the premiermore » gamma-ray detector. The development of ultra-pure germanium yielded highly stable detectors which have remained unsurpassed in their performance. New acceptors and donors were discovered and the electrically active role of hydrogen was clearly established several years before similar findings in silicon. Lightly doped germanium has found applications as far infrared detectors and heavily Neutron Transmutation Doped (NTD) germanium is used in thermistor devices operating at a few milliKelvin. Recently germanium has been rediscovered by the silicon device community because of its superior electron and hole mobility and its ability to induce strains when alloyed with silicon. Germanium is again a mainstream electronic material.« less

The evolution of FDA policy on silicone breast implants: a case study of politics, bureaucracy, and business in the process of decision-making.

PubMed

Palley, H A

1995-01-01

The central issue facing federal regulation of breast implants is that while such devices are not functionally necessary or needed for survival, the side effects may be harmful and have not been proven unharmful. The Medical Device Amendments of 1976 appear to require such evidence prior to the FDA permitting the unrestricted marketing of these devices. However, only recently have such requirements been imposed by the FDA. The author examines the FDA's decision-making process, particularly as applied to silicone breast implants, and the factors that appears to have affected such decisions. In pursuing this study, the activities of a number of interest-group actors, as well as congressional responses and the role of federal bureaucratic actors, were examined. In 1992, the FDA established a regulatory protocol that effectively withdrew most silicone breast implants from the market for the purpose of breast augmentation and allows for the monitoring of the impact of new implants on women's health. This increase concern for determining the safety of breast implants is due to a number of factors, which are examined in this article.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Towards nanometer-spaced silicon contacts to proteins

NASA Astrophysics Data System (ADS)

Schukfeh, Muhammed I.; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Towards substrate engineering of graphene-silicon Schottky diode photodetectors.

PubMed

Selvi, Hakan; Unsuree, Nawapong; Whittaker, Eric; Halsall, Matthew P; Hill, Ernie W; Thomas, Andrew; Parkinson, Patrick; Echtermeyer, Tim J

2018-02-15

Graphene-silicon Schottky diode photodetectors possess beneficial properties such as high responsivities and detectivities, broad spectral wavelength operation and high operating speeds. Various routes and architectures have been employed in the past to fabricate devices. Devices are commonly based on the removal of the silicon-oxide layer on the surface of silicon by wet-etching before deposition of graphene on top of silicon to form the graphene-silicon Schottky junction. In this work, we systematically investigate the influence of the interfacial oxide layer, the fabrication technique employed and the silicon substrate on the light detection capabilities of graphene-silicon Schottky diode photodetectors. The properties of devices are investigated over a broad wavelength range from near-UV to short-/mid-infrared radiation, radiation intensities covering over five orders of magnitude as well as the suitability of devices for high speed operation. Results show that the interfacial layer, depending on the required application, is in fact beneficial to enhance the photodetection properties of such devices. Further, we demonstrate the influence of the silicon substrate on the spectral response and operating speed. Fabricated devices operate over a broad spectral wavelength range from the near-UV to the short-/mid-infrared (thermal) wavelength regime, exhibit high photovoltage responses approaching 10 6 V W -1 and short rise- and fall-times of tens of nanoseconds.

Area laser crystallized LTPS TFTs with implanted contacts for active matrix OLED displays

NASA Astrophysics Data System (ADS)

Persidis, Efstathios; Baur, Holger; Pieralisi, Fabio; Schalberger, Patrick; Fruehauf, Norbert

2008-03-01

We have developed a four mask low temperature poly-Si (LTPS) TFT process for p- and n-channel devices. Our PECVD deposited amorphous silicon is recrystallized to polycrystalline silicon with single area excimer laser crystallization while formation of drain and source is carried out with self aligned ion beam implantation. We have investigated implantation parameters, suitability of various metallizations as well as laser activation and annealing procedures. To prove the potential capability of our devices, which are suitable for conventional and inverted OLEDs alike, we have produced several functional active matrix backplanes implementing different pixel circuits. Our active matrix backplane process has been customized to drive small molecules as well as polymers, regardless if top or bottom emitting.

Aerospace Sensor Component and Subsystem Investigation and Innovation-2 Component Exploration and Development (ASCSII-2 CED) Delivery Order 0003: Hermetically Sealed Cavities in 3-D GaAs-Silicon and Silicon-Silicon Packages for Microelectromechanical System (MEMS) Devices Using Selective and Large-Scale Bonding

DTIC Science & Technology

2003-03-01

and silicon-to-silicon to produce cavities for 3-D assembly of MEMS devices has been demonstrated using SnAgCu and eutectic SnPb solders. Laser and...of GaAs-to-silicon and silicon-to-silicon to produce cavities for 3-D assembly of MEMS devices has been demonstrated using SnAgCu and euctectic...research_images/ 3.2 Solder Reflow The reflow profile for SnAgCu solder was developed on the Sikama convection/ conduction reflow oven using a continuous

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

NASA Astrophysics Data System (ADS)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

New Deep Reactive Ion Etching Process Developed for the Microfabrication of Silicon Carbide

NASA Technical Reports Server (NTRS)

Evans, Laura J.; Beheim, Glenn M.

2005-01-01

Silicon carbide (SiC) is a promising material for harsh environment sensors and electronics because it can enable such devices to withstand high temperatures and corrosive environments. Microfabrication techniques have been studied extensively in an effort to obtain the same flexibility of machining SiC that is possible for the fabrication of silicon devices. Bulk micromachining using deep reactive ion etching (DRIE) is attractive because it allows the fabrication of microstructures with high aspect ratios (etch depth divided by lateral feature size) in single-crystal or polycrystalline wafers. Previously, the Sensors and Electronics Branch of the NASA Glenn Research Center developed a DRIE process for SiC using the etchant gases sulfur hexafluoride (SF6) and argon (Ar). This process provides an adequate etch rate of 0.2 m/min and yields a smooth surface at the etch bottom. However, the etch sidewalls are rougher than desired, as shown in the preceding photomicrograph. Furthermore, the resulting structures have sides that slope inwards, rather than being precisely vertical. A new DRIE process for SiC was developed at Glenn that produces smooth, vertical sidewalls, while maintaining an adequately high etch rate.

Specific and selective target detection of supra-genome 21 Mers Salmonella via silicon nanowires biosensor

NASA Astrophysics Data System (ADS)

Mustafa, Mohammad Razif Bin; Dhahi, Th S.; Ehfaed, Nuri. A. K. H.; Adam, Tijjani; Hashim, U.; Azizah, N.; Mohammed, Mohammed; Noriman, N. Z.

2017-09-01

The nano structure based on silicon can be surface modified to be used as label-free biosensors that allow real-time measurements. The silicon nanowire surface was functionalized using 3-aminopropyltrimethoxysilane (APTES), which functions as a facilitator to immobilize biomolecules on the silicon nanowire surface. The process is simple, economical; this will pave the way for point-of-care applications. However, the surface modification and subsequent detection mechanism still not clear. Thus, study proposed step by step process of silicon nano surface modification and its possible in specific and selective target detection of Supra-genome 21 Mers Salmonella. The device captured the molecule with precisely; the approach took the advantages of strong binding chemistry created between APTES and biomolecule. The results indicated how modifications of the nanowires provide sensing capability with strong surface chemistries that can lead to specific and selective target detection.

Development of processes for the production of low cost silicon dendritic web for solar cells

NASA Technical Reports Server (NTRS)

Duncan, C. S.; Seidensticker, R. G.; Mchugh, J. P.; Hopkins, R. H.; Skutch, M. E.; Driggers, J. M.; Hill, F. E.

1980-01-01

High area output rates and continuous, automated growth are two key technical requirements for the growth of low-cost silicon ribbons for solar cells. By means of computer-aided furnace design, silicon dendritic web output rates as high as 27 sq cm/min have been achieved, a value in excess of that projected to meet a $0.50 per peak watt solar array manufacturing cost. The feasibility of simultaneous web growth while the melt is replenished with pelletized silicon has also been demonstrated. This step is an important precursor to the development of an automated growth system. Solar cells made on the replenished material were just as efficient as devices fabricated on typical webs grown without replenishment. Moreover, web cells made on a less-refined, pelletized polycrystalline silicon synthesized by the Battelle process yielded efficiencies up to 13% (AM1).

Custom 3D Printable Silicones with Tunable Stiffness.

PubMed

Durban, Matthew M; Lenhardt, Jeremy M; Wu, Amanda S; Small, Ward; Bryson, Taylor M; Perez-Perez, Lemuel; Nguyen, Du T; Gammon, Stuart; Smay, James E; Duoss, Eric B; Lewicki, James P; Wilson, Thomas S

2018-02-01

Silicone elastomers have broad versatility within a variety of potential advanced materials applications, such as soft robotics, biomedical devices, and metamaterials. A series of custom 3D printable silicone inks with tunable stiffness is developed, formulated, and characterized. The silicone inks exhibit excellent rheological behavior for 3D printing, as observed from the printing of porous structures with controlled architectures. Herein, the capability to tune the stiffness of printable silicone materials via careful control over the chemistry, network formation, and crosslink density of the ink formulations in order to overcome the challenging interplay between ink development, post-processing, material properties, and performance is demonstrated. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Imaging of the native inversion layer in Silicon-On-Insulator wafers via Scanning Surface Photovoltage: Implications for RF device performance

NASA Astrophysics Data System (ADS)

Dahanayaka, Daminda; Wong, Andrew; Kaszuba, Philip; Moszkowicz, Leon; Slinkman, James; IBM SPV Lab Team

2014-03-01

Silicon-On-Insulator (SOI) technology has proved beneficial for RF cell phone technologies, which have equivalent performance to GaAs technologies. However, there is evident parasitic inversion layer under the Buried Oxide (BOX) at the interface with the high resistivity Si substrate. The latter is inferred from capacitance-voltage measurements on MOSCAPs. The inversion layer has adverse effects on RF device performance. We present data which, for the first time, show the extent of the inversion layer in the underlying substrate. This knowledge has driven processing techniques to suppress the inversion.

Medicine Delivery Device with Integrated Sterilization and Detection

NASA Technical Reports Server (NTRS)

Shearn, Michael J.; Greer, Harold F.; Manohara, Harish

2013-01-01

Sterile delivery devices can be created by integrating a medicine delivery instrument with surfaces that are coated with germicidal and anti-fouling material. This requires that a large-surface-area template be developed within a constrained volume to ensure good contact between the delivered medicine and the germicidal material. Both of these can be integrated using JPL-developed silicon nanotip or cryo-etch black silicon technologies with atomic layer deposition (ALD) coating of specific germicidal layers. The application of semiconductor processing techniques and technologies to the problems of fluid manipulation and delivery has enabled the integration of chemical, electrical, and mechanical manipulation of samples all within a single microfluidic device. This approach has been successfully applied at JPL to the automated processing, detection, and analysis of minute quantities (parts per trillion level) of biomaterials to develop instruments for in situ exploration or extraterrestrial bodies. The same nanofabrication techniques that are used to produce a microfluidics device are also capable of synthesizing extremely high-surface-area templates in precise locations, and coating those surfaces with conformal films to manipulate their surface properties. This methodology has been successfully applied at JPL to produce patterned and coated silicon nanotips (also known as black silicon) to manipulate the hydrophilicity of surfaces to direct the spreading of fluids in microdevices. JPL's ALD technique is an ideal method to produce the highly conformal coatings required for this type of application. Certain materials, such as TiO2, have germicidal and anti-fouling properties when they are illuminated with UV light. The proposed delivery device contacts medicine with this high-surface-area black silicon surface coated with a thin-film germicidal deposited conformally with ALD. The coating can also be illuminated with ultraviolet light for the purpose of sterilization or identification of the medicine itself. This constrained volume that is located immediately prior to delivery into a patient, ensures that the medicine delivery device is inherently sterile. An additional benefit to integrating a high-surface-area template within the fluid channel of a medicine delivery device is that one can envision a number of different functional coatings that could facilitate the capture and analysis of either microbial contaminants or the medicine itself. For example, one could attach antibodies or some other binding agent with a specific affinity to the silicon nanotip template. Once a target molecule or microbe is bound to the high-surface- area template, one could use an optical analytical technique such as fluorescence or adsorption to determine the identity and potentially the concentration of the species of interest. By illuminating the bound species from the back, it may also be possible to probe only the molecules with an evanescent wave, making detection of the species from the front side of the device much simpler.

Mid-infrared materials and devices on a Si platform for optical sensing

PubMed Central

Singh, Vivek; Lin, Pao Tai; Patel, Neil; Lin, Hongtao; Li, Lan; Zou, Yi; Deng, Fei; Ni, Chaoying; Hu, Juejun; Giammarco, James; Soliani, Anna Paola; Zdyrko, Bogdan; Luzinov, Igor; Novak, Spencer; Novak, Jackie; Wachtel, Peter; Danto, Sylvain; Musgraves, J David; Richardson, Kathleen; Kimerling, Lionel C; Agarwal, Anuradha M

2014-01-01

In this article, we review our recent work on mid-infrared (mid-IR) photonic materials and devices fabricated on silicon for on-chip sensing applications. Pedestal waveguides based on silicon are demonstrated as broadband mid-IR sensors. Our low-loss mid-IR directional couplers demonstrated in SiNx waveguides are useful in differential sensing applications. Photonic crystal cavities and microdisk resonators based on chalcogenide glasses for high sensitivity are also demonstrated as effective mid-IR sensors. Polymer-based functionalization layers, to enhance the sensitivity and selectivity of our sensor devices, are also presented. We discuss the design of mid-IR chalcogenide waveguides integrated with polycrystalline PbTe detectors on a monolithic silicon platform for optical sensing, wherein the use of a low-index spacer layer enables the evanescent coupling of mid-IR light from the waveguides to the detector. Finally, we show the successful fabrication processing of our first prototype mid-IR waveguide-integrated detectors. PMID:27877641

Rapid Selective Annealing of Cu Thin Films on Si Using Microwaves

NASA Technical Reports Server (NTRS)

Brain, R. A.; Atwater, H. A.; Watson, T. J.; Barmatz, M.

1994-01-01

A major goal of the semiconductor indurstry is to lower the processing temperatures needed for interconnects in silicon integrated circuits. Typical rapid thermal annealing processes heat the film as well as the substrate, creating device problems.

Integration of lateral porous silicon membranes into planar microfluidics.

PubMed

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

Enhancing the Efficiency of Silicon-Based Solar Cells by the Piezo-Phototronic Effect.

PubMed

Zhu, Laipan; Wang, Longfei; Pan, Caofeng; Chen, Libo; Xue, Fei; Chen, Baodong; Yang, Leijing; Su, Li; Wang, Zhong Lin

2017-02-28

Although there are numerous approaches for fabricating solar cells, the silicon-based photovoltaics are still the most widely used in industry and around the world. A small increase in the efficiency of silicon-based solar cells has a huge economic impact and practical importance. We fabricate a silicon-based nanoheterostructure (p + -Si/p-Si/n + -Si (and n-Si)/n-ZnO nanowire (NW) array) photovoltaic device and demonstrate the enhanced device performance through significantly enhanced light absorption by NW array and effective charge carrier separation by the piezo-phototronic effect. The strain-induced piezoelectric polarization charges created at n-doped Si-ZnO interfaces can effectively modulate the corresponding band structure and electron gas trapped in the n + -Si/n-ZnO NW nanoheterostructure and thus enhance the transport process of local charge carriers. The efficiency of the solar cell was improved from 8.97% to 9.51% by simply applying a static compress strain. This study indicates that the piezo-phototronic effect can enhance the performance of a large-scale silicon-based solar cell, with great potential for industrial applications.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Inorganic Photovoltaics Materials and Devices: Past, Present, and Future

NASA Technical Reports Server (NTRS)

Hepp, Aloysius F.; Bailey, Sheila G.; Rafaelle, Ryne P.

2005-01-01

This report describes recent aspects of advanced inorganic materials for photovoltaics or solar cell applications. Specific materials examined will be high-efficiency silicon, gallium arsenide and related materials, and thin-film materials, particularly amorphous silicon and (polycrystalline) copper indium selenide. Some of the advanced concepts discussed include multi-junction III-V (and thin-film) devices, utilization of nanotechnology, specifically quantum dots, low-temperature chemical processing, polymer substrates for lightweight and low-cost solar arrays, concentrator cells, and integrated power devices. While many of these technologies will eventually be used for utility and consumer applications, their genesis can be traced back to challenging problems related to power generation for aerospace and defense. Because this overview of inorganic materials is included in a monogram focused on organic photovoltaics, fundamental issues and metrics common to all solar cell devices (and arrays) will be addressed.

Review: Semiconductor Piezoresistance for Microsystems

PubMed Central

Barlian, A. Alvin; Park, Woo-Tae; Mallon, Joseph R.; Rastegar, Ali J.; Pruitt, Beth L.

2010-01-01

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers. PMID:20198118

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

Amorphous silicon Schottky barrier solar cells incorporating a thin insulating layer and a thin doped layer

DOEpatents

Carlson, David E.

1980-01-01

Amorphous silicon Schottky barrier solar cells which incorporate a thin insulating layer and a thin doped layer adjacent to the junction forming metal layer exhibit increased open circuit voltages compared to standard rectifying junction metal devices, i.e., Schottky barrier devices, and rectifying junction metal insulating silicon devices, i.e., MIS devices.

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Atomic-Layer-Deposited Transparent Electrodes for Silicon Heterojunction Solar Cells

DOE PAGES

Demaurex, Benedicte; Seif, Johannes P.; Smit, Sjoerd; ...

2014-11-01

We examine damage-free transparent-electrode deposition to fabricate high-efficiency amorphous silicon/crystalline silicon heterojunction solar cells. Such solar cells usually feature sputtered transparent electrodes, the deposition of which may damage the layers underneath. Using atomic layer deposition, we insert thin protective films between the amorphous silicon layers and sputtered contacts and investigate their effect on device operation. We find that a 20-nm-thick protective layer suffices to preserve, unchanged, the amorphous silicon layers beneath. Insertion of such protective atomic-layer-deposited layers yields slightly higher internal voltages at low carrier injection levels. However, we identify the presence of a silicon oxide layer, formed during processing,more » between the amorphous silicon and the atomic-layer-deposited transparent electrode that acts as a barrier, impeding hole and electron collection.« less

Thin Carbon Layers on Nanostructured Silicon-Properties and Applications

NASA Astrophysics Data System (ADS)

Angelescu, Anca; Kleps, Irina; Miu, Mihaela; Simion, Monica; Bragaru, Adina; Petrescu, Stefana; Paduraru, Crina; Raducanu, Aurelia

Thin carbon layers such as silicon carbide (SiC) and diamond like carbon (DLC) layers on silicon, or on nanostructured silicon substrats were obtained by different methods. This paper is a review of our results in the areas of carbon layer microfabrication technologies and their properties related to different microsystem apllications. So, silicon membranes using a-SiC or DLC layers as etching mask, as well as silicon carbide membranes using a combined porous silicon — DLC structure were fabricated for sensor applications. A detailed evaluation of the field emission (FE) properties of these films was done to demonstrate their capability to be used in field emission devices. Carbon thin layers on nanostructured silicon samples were also investigated with respect to the living cell adhesion on these structures. The experiments indicate that the cell attachment on the surface of carbon coatings can be controlled by deposition parameters during the technological process.

Silicon-graphene photonic devices

NASA Astrophysics Data System (ADS)

Yin, Yanlong; Li, Jiang; Xu, Yang; Tsang, Hon Ki; Dai, Daoxin

2018-06-01

Silicon photonics has attracted much attention because of the advantages of CMOS (complementary-metal-oxide-semiconductor) compatibility, ultra-high integrated density, etc. Great progress has been achieved in the past decades. However, it is still not easy to realize active silicon photonic devices and circuits by utilizing the material system of pure silicon due to the limitation of the intrinsic properties of silicon. Graphene has been regarded as a promising material for optoelectronics due to its unique properties and thus provides a potential option for realizing active photonic integrated devices on silicon. In this paper, we present a review on recent progress of some silicon-graphene photonic devices for photodetection, all-optical modulation, as well as thermal-tuning. Project supported by the National Major Research and Development Program (No. 2016YFB0402502), the National Natural Science Foundation of China (Nos. 11374263, 61422510, 61431166001, 61474099, 61674127), and the National Key Research and Development Program (No. 2016YFA0200200).

Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsam (Inventor); Manohara, Harish (Inventor); Mobasser, Sohrab (Inventor); Lee, Choonsup (Inventor)

2011-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Anti- reflective device having an anti-reflection surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsman (Inventor); Mooasser, Sohrab (Inventor); Manohara, Harish (Inventor); Lee, Choonsup (Inventor); Bae, Kungsam (Inventor)

2009-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

Method for sputtering a PIN microcrystalline/amorphous silicon semiconductor device with the P and N-layers sputtered from boron and phosphorous heavily doped targets

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-04-02

A silicon PIN microcrystalline/amorphous silicon semiconductor device is constructed by the sputtering of N, and P layers of silicon from silicon doped targets and the I layer from an undoped target, and at least one semi-transparent ohmic electrode.

Reduced Moment-Based Models for Oxygen Precipitates and Dislocation Loops in Silicon

NASA Astrophysics Data System (ADS)

Trzynadlowski, Bart

The demand for ever smaller, higher-performance integrated circuits and more efficient, cost-effective solar cells continues to push the frontiers of process technology. Fabrication of silicon devices requires extremely precise control of impurities and crystallographic defects. Failure to do so not only reduces performance, efficiency, and yield, it threatens the very survival of commercial enterprises in today's fiercely competitive and price-sensitive global market. The presence of oxygen in silicon is an unavoidable consequence of the Czochralski process, which remains the most popular method for large-scale production of single-crystal silicon. Oxygen precipitates that form during thermal processing cause distortion of the surrounding silicon lattice and can lead to the formation of dislocation loops. Localized deformation caused by both of these defects introduces potential wells that trap diffusing impurities such as metal atoms, which is highly desirable if done far away from sensitive device regions. Unfortunately, dislocations also reduce the mechanical strength of silicon, which can cause wafer warpage and breakage. Engineers must negotiate this and other complex tradeoffs when designing fabrication processes. Accomplishing this in a complex, modern process involving a large number of thermal steps is impossible without the aid of computational models. In this dissertation, new models for oxygen precipitation and dislocation loop evolution are described. An oxygen model using kinetic rate equations to evolve the complete precipitate size distribution was developed first. This was then used to create a reduced model tracking only the moments of the size distribution. The moment-based model was found to run significantly faster than its full counterpart while accurately capturing the evolution of oxygen precipitates. The reduced model was fitted to experimental data and a sensitivity analysis was performed to assess the robustness of the results. Source code for both models is included. A moment-based model for dislocation loop formation from {311} defects in ion-implanted silicon was also developed and validated against experimental data. Ab initio density functional theory calculations of stacking faults and edge dislocations were performed to extract energies and elastic properties. This allowed the effect of applied stress on the evolution of {311} defects and dislocation loops to be investigated.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

High performance SONOS flash memory with in-situ silicon nanocrystals embedded in silicon nitride charge trapping layer

NASA Astrophysics Data System (ADS)

Lim, Jae-Gab; Yang, Seung-Dong; Yun, Ho-Jin; Jung, Jun-Kyo; Park, Jung-Hyun; Lim, Chan; Cho, Gyu-seok; Park, Seong-gye; Huh, Chul; Lee, Hi-Deok; Lee, Ga-Won

2018-02-01

In this paper, SONOS-type flash memory device with highly improved charge-trapping efficiency is suggested by using silicon nanocrystals (Si-NCs) embedded in silicon nitride (SiNX) charge trapping layer. The Si-NCs were in-situ grown by PECVD without additional post annealing process. The fabricated device shows high program/erase speed and retention property which is suitable for multi-level cell (MLC) application. Excellent performance and reliability for MLC are demonstrated with large memory window of ∼8.5 V and superior retention characteristics of 7% charge loss for 10 years. High resolution transmission electron microscopy image confirms the Si-NC formation and the size is around 1-2 nm which can be verified again in X-ray photoelectron spectroscopy (XPS) where pure Si bonds increase. Besides, XPS analysis implies that more nitrogen atoms make stable bonds at the regular lattice point. Photoluminescence spectra results also illustrate that Si-NCs formation in SiNx is an effective method to form deep trap states.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Recent progress on fabrication of memristor and transistor-based neuromorphic devices for high signal processing speed with low power consumption

NASA Astrophysics Data System (ADS)

Hadiyawarman; Budiman, Faisal; Goldianto Octensi Hernowo, Detiza; Pandey, Reetu Raj; Tanaka, Hirofumi

2018-03-01

The advanced progress of electronic-based devices for artificial neural networks and recent trends in neuromorphic engineering are discussed in this review. Recent studies indicate that the memristor and transistor are two types of devices that can be implemented as neuromorphic devices. The electrical switching characteristics and physical mechanism of neuromorphic devices based on metal oxide, metal sulfide, silicon, and carbon materials are broadly covered in this review. Moreover, the switching performance comparison of several materials mentioned above are well highlighted, which would be useful for the further development of memristive devices. Recent progress in synaptic devices and the application of a switching device in the learning process is also discussed in this paper.

Reconfigurable silicon thermo-optical device based on spectral tuning of ring resonators.

PubMed

Fegadolli, William S; Almeida, Vilson R; Oliveira, José Edimar Barbosa

2011-06-20

A novel tunable and reconfigurable thermo-optical device is theoretically proposed and analyzed in this paper. The device is designed to be entirely compatible with CMOS process and to work as a thermo-optical filter or modulator. Numerical results, made by means of analytical and Finite-Difference Time-Domain (FDTD) methods, show that a compact device enables a broad bandwidth operation, of up to 830 GHz, which allows the device to work under a large temperature variation, of up to 96 K.

Ultralow-power all-optical processing of high-speed data signals in deposited silicon waveguides.

PubMed

Wang, Ke-Yao; Petrillo, Keith G; Foster, Mark A; Foster, Amy C

2012-10-22

Utilizing a 6-mm-long hydrogenated amorphous silicon nanowaveguide, we demonstrate error-free (BER < 10(-9)) 160-to-10 Gb/s OTDM demultiplexing using ultralow switching peak powers of 50 mW. This material is deposited at low temperatures enabling a path toward multilayer integration and therefore massive scaling of the number of devices in a single photonic chip.

Reconfigurable Cellular Photonic Crystal Arrays (RCPA)

DTIC Science & Technology

2013-03-01

signal processing based on reconfigurable integrated optics devices. This technology has the potential to revolutionize the design circle of optical...Accomplishments III.A. Design and fabrication of an accumulation-mode modulator Figure 1(a) shows the schematic of a compact resonator on the double-Si... integration of silicon nitride on silicon-on-insulator platform to enhance the arsenal of photonic circuit designers . The coherent integration of

Lateral hydrogen microsensors prepared on-chip by local oxidation of platinum-decorated titanium films

NASA Astrophysics Data System (ADS)

Herbertz, S.; Welk, D.; Heinzel, T.

2018-05-01

Titanium microstripes on silicon dioxide substrates are oxidized locally by applying voltages on-chip to lateral electrodes under ambient conditions. This technique enables profound modifications of the electronic circuit. As an example, we transform Ti films decorated by a sub-monolayer of platinum into hydrogen gas microsensors in an otherwise completed device by a silicon-MOS compatible process.

Single-Event Effects in Silicon Carbide Power Devices

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2015-01-01

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

Colloidal Engineering for Infrared-Bandgap Solution-Processed Quantum Dot Solar Cells

NASA Astrophysics Data System (ADS)

Kiani, Amirreza

Ever-increasing global energy demand and a diminishing fossil fuel supply have prompted the development of technologies for sustainable energy production. Solar photovoltaic (PV) devices have huge potential for energy harvesting and production since the sun delivers more energy to the earth in one hour than the global population consumes in one year. The solar cell industry is now dominated by silicon PV devices. The cost of silicon modules has decreased substantially over the past two decades and the number of installed silicon PV devices has increased dramatically. There remains a need for emerging solar technologies that can harvest the untapped portion of the solar spectrum and can be integrated on flexible and curved surfaces. This thesis focuses on colloidal quantum dot (CQD) PV devices. CQDs are nanoparticles fabricated using a low-temperature and cost-effective solution technique. These materials suffer from a high density of surface traps derived from the large surface-to-volume ratio of CQD nanoparticles, combined with limited carrier mobility. These result in a short carrier diffusion length, a main limiting factor in CQD solar cell performance. This thesis seeks to address the poor diffusion length in lead sulfide (PbS) CQD films and pave the way for new applications for CQD PV devices in infrared solar harvesting and waste heat recovery. A two-fold reduction in surface trap density is demonstrated using molecular halide treatment. Iodine molecules introduced prior to the film formation replace the otherwise unpassivated surface sulfur atoms. This results in a 35% increase in the diffusion length and enables charge extraction over thicker active layer leading to the world's most efficient CQD PV devices from June 2015 to July 2016 with the certified power conversion efficiency of 9.9%. This represents a 30% increase over the best-certified PCE (7.5%) prior to this thesis. The colloidal engineering highlighted herein enables infrared (IR) solar harvesting for the first time. Addition of short bromothiol ligands during the synthesis significantly reduces the agglomeration of 1 eV bandgap CQDs and maintains efficient charge extraction into the selective electrodes. The devices can augment the performance of the best silicon cells by 7 power points where 0.8 additive power points are demonstrated experimentally. A tailored solution exchanged process developed for 1 eV bandgap CQDs results in air-stable IR PV devices with improved manufacturability. The process utilizes a tailored combination of lead iodide (PbI2) and ammonium acetate for the solution exchange and hexylamine + MEK as the final solvent to yield solar thick films with the filtered (1100 nm and beyond) performance of 0.4%. This thesis pushes the limit of CQD device applications to waste heat recovery. I demonstrate successful harvesting of low energy photons emitted from a hot object by designing and developing the first solution-processed thermophotovoltaic devices. These devices are comprised of 0.7 eV bandgap CQDs that successfully harvest photons emitted from an 800°C heat source.

Pulsed deposition of silicate films

NASA Astrophysics Data System (ADS)

He, W.; Solanki, R.; Conley, J. F.; Ono, Y.

2003-09-01

A sequential pulsed process is utilized for deposition of nonstoichiometric silicate films without employing an oxidizing agent. The metal precursors were HfCl4, AlCl3, and ZrCl4, as well as Hf(NO3)4 and the silicon source was tris(tert-butoxy)silanol. Unlike atomic layer deposition, the growth per cycle was several monolayers thick, where the enhancement in growth was due to a catalytic reaction. The bulk and electrical properties of these films are similar to those of silicon dioxide. Silicon carbide devices coated with these films show good insulating characteristics.

Fabrication and testing of freestanding Si nanogratings for UV filtration on space-based particle sensors.

PubMed

Mukherjee, Pran; Zurbuchen, Thomas H; Guo, L Jay

2009-08-12

We demonstrate complete fabrication process integration and device performance of sturdy, self-supported transmission gratings in silicon. Gratings are patterned with nanoimprint lithography and aluminum liftoff on silicon-on-insulator wafers. Double-sided deep reactive ion etching (DRIE) creates freestanding 120 nm half-pitch gratings with 2000 nm depth and built-in 1 mm pitch bulk silicon support structures. Optical characterization demonstrates 10(-4) transmission of UV in the 190-250 nm band while a 25-30% geometric transparency allows particles to pass unimpeded for space plasma measurements.

Development of advanced second-generation micromirror devices fabricated in a four-level planarized surface-micromachined polycrystalline silicon process

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Comtois, John H.; Schriner, Heather K.

1998-04-01

This paper describes the design and characterization of several types of micromirror devices to include process capabilities, device modeling, and test data resulting in deflection versus applied potential curves and surface contour measurements. These devices are the first to be fabricated in the state-of-the-art four-level planarized polysilicon process available at Sandia National Laboratories known as the Sandia Ultra-planar Multi-level MEMS Technology. This enabling process permits the development of micromirror devices with near-ideal characteristics which have previously been unrealizable in standard three-layer polysilicon processes. This paper describes such characteristics which have previously been unrealizable in standard three-layer polysilicon processes. This paper describes such characteristics as elevated address electrodes, various address wiring techniques, planarized mirror surfaces suing Chemical Mechanical Polishing, unique post-process metallization, and the best active surface area to date.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

A 4H Silicon Carbide Gate Buffer for Integrated Power Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ericson, N; Frank, S; Britton, C

2014-02-01

A gate buffer fabricated in a 2-mu m 4H silicon carbide (SiC) process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into anmore » isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC.« less

Effect of silicide/silicon hetero-junction structure on thermal conductivity and Seebeck coefficient.

PubMed

Choi, Wonchul; Park, Young-Sam; Hyun, Younghoon; Zyung, Taehyoung; Kim, Jaehyeon; Kim, Soojung; Jeon, Hyojin; Shin, Mincheol; Jang, Moongyu

2013-12-01

We fabricated a thermoelectric device with a silicide/silicon laminated hetero-structure by using RF sputtering and rapid thermal annealing. The device was observed to have Ohmic characteristics by I-V measurement. The temperature differences and Seebeck coefficients of the proposed silicide/silicon laminated and bulk structure were measured. The laminated thermoelectric device shows suppression of heat flow from the hot to cold side. This is supported by the theory that the atomic mass difference between silicide and silicon creates a scattering center for phonons. The major impact of our work is that phonon transmission is suppressed at the interface between silicide and silicon without degrading electrical conductivity. The estimated thermal conductivity of the 3-layer laminated device is 126.2 +/- 3.7 W/m. K. Thus, by using the 3-layer laminated structure, thermal conductivity is reduced by around 16% compared to bulk silicon. However, the Seebeck coefficient of the thermoelectric device is degraded compared to that of bulk silicon. It is understood that electrical conductivity is improved by using silicide as a scattering center.

Key Processes of Silicon-On-Glass MEMS Fabrication Technology for Gyroscope Application.

PubMed

Ma, Zhibo; Wang, Yinan; Shen, Qiang; Zhang, Han; Guo, Xuetao

2018-04-17

MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.

Tungsten coating for improved wear resistance and reliability of microelectromechanical devices

DOEpatents

Fleming, James G.; Mani, Seethambal S.; Sniegowski, Jeffry J.; Blewer, Robert S.

2001-01-01

A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 .degree. C. in the presence of gaseous nitrogen trifluoride (NF.sub.3). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF.sub.6) at an elevated temperature, preferably about 450.degree. C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact. The present invention can be applied to many different types of MEM devices including microrelays, micromirrors and microengines. Additionally, the tungsten wear-resistant coating of the present invention can be used to enhance the hardness, wear resistance, electrical conductivity, optical reflectivity and chemical inertness of one or more semiconductor surfaces within a MEM device.

A MEMS Infrared Thermopile Fabricated from Silicon-On-Insulator with Phononic Crystal Structures and Carbon Nanotube Absorption Layer

NASA Astrophysics Data System (ADS)

Gray, Kory Forrest

The goal of this project was to examine the possibility of creating a novel thermal infrared detector based on silicon CMOS technology that has been enhanced by the latest nano-engineering discoveries. Silicon typically is not thought as an efficient thermoelectric material. However recent advancements in nanotechnology have improved the potential for a highly sensitive infrared detector based on nano-structured silicon. The thermal conductivity of silicon has been shown to be reduced from 150 W/mK down to 60 W/mK just by decreasing the scale of the silicon from bulk down to the sub-micron scale. Further reduction of the thermal conductivity has been shown by patterning silicon with a phonon crystal structure which has been reported to have thermal conductivities down to 10 W/mK. The phonon crystal structure consists of a 2D array of holes that are etched into the silicon. The size and pitch of the holes are on the order of the mean free path of the phonons in silicon which is approximately 200-500nm. This particular device had 200nm holes on a 400nm pitch. The Seebeck coefficient of silicon can also be enhanced by the reduction of the material from the bulk to sub-micron scale and with degenerate level doping. The combination of decreased thermal conductivity and increased Seebeck coefficient allow silicon to be a promising material for thermoelectric infrared detectors. The highly doped silicon is desired to reduce the electrical resistance of the device. The low electrical resistance is required to reduce the Johnson noise of the device which is the dominant noise source for most thermal detectors. This project designed a MEMS thermopile using a silicon-on-insulator substrate, and a CMOS compatible process. The basic thermopile consists of a silicon dioxide membrane with phononic crystal patterned silicon thermocouples around the edges of the membrane. Vertical aligned, multi-walled, carbon nanotubes were used as the infrared absorption layer. A MEMS thermoelectric detector with a D* of 3 * 107 cm Hz 0.5/W was demonstrated with a time response of 3-10 milliseconds. With this initial research, it is possible to improve the D* to the high 108 cm Hz 0.5/W range by slightly changing the design of the thermopile and patterning the absorption layer.

Simultaneous Purification and Perforation of Low-Grade Si Sources for Lithium-Ion Battery Anode.

PubMed

Jin, Yan; Zhang, Su; Zhu, Bin; Tan, Yingling; Hu, Xiaozhen; Zong, Linqi; Zhu, Jia

2015-11-11

Silicon is regarded as one of the most promising candidates for lithium-ion battery anodes because of its abundance and high theoretical capacity. Various silicon nanostructures have been heavily investigated to improve electrochemical performance by addressing issues related to structure fracture and unstable solid-electrolyte interphase (SEI). However, to further enable widespread applications, scalable and cost-effective processes need to be developed to produce these nanostructures at large quantity with finely controlled structures and morphologies. In this study, we develop a scalable and low cost process to produce porous silicon directly from low grade silicon through ball-milling and modified metal-assisted chemical etching. The morphology of porous silicon can be drastically changed from porous-network to nanowire-array by adjusting the component in reaction solutions. Meanwhile, this perforation process can also effectively remove the impurities and, therefore, increase Si purity (up to 99.4%) significantly from low-grade and low-cost ferrosilicon (purity of 83.4%) sources. The electrochemical examinations indicate that these porous silicon structures with carbon treatment can deliver a stable capacity of 1287 mAh g(-1) over 100 cycles at a current density of 2 A g(-1). This type of purified porous silicon with finely controlled morphology, produced by a scalable and cost-effective fabrication process, can also serve as promising candidates for many other energy applications, such as thermoelectrics and solar energy conversion devices.

All-optical control of light on a graphene-on-silicon nitride chip using thermo-optic effect.

PubMed

Qiu, Ciyuan; Yang, Yuxing; Li, Chao; Wang, Yifang; Wu, Kan; Chen, Jianping

2017-12-06

All-optical signal processing avoids the conversion between optical signals and electronic signals and thus has the potential to achieve a power efficient photonic system. Micro-scale all-optical devices for light manipulation are the key components in the all-optical signal processing and have been built on the semiconductor platforms (e.g., silicon and III-V semiconductors). However, the two-photon absorption (TPA) effect and the free-carrier absorption (FCA) effect in these platforms deteriorate the power handling and limit the capability to realize complex functions. Instead, silicon nitride (Si 3 N 4 ) provides a possibility to realize all-optical large-scale integrated circuits due to its insulator nature without TPA and FCA. In this work, we investigate the physical dynamics of all-optical control on a graphene-on-Si 3 N 4 chip based on thermo-optic effect. In the experimental demonstration, a switching response time constant of 253.0 ns at a switching energy of ~50 nJ is obtained with a device dimension of 60 μm × 60 μm, corresponding to a figure of merit (FOM) of 3.0 nJ mm. Detailed coupled-mode theory based analysis on the thermo-optic effect of the device has been performed.

DAPHNE silicon photonics technological platform for research and development on WDM applications

NASA Astrophysics Data System (ADS)

Baudot, Charles; Fincato, Antonio; Fowler, Daivid; Perez-Galacho, Diego; Souhaité, Aurélie; Messaoudène, Sonia; Blanc, Romuald; Richard, Claire; Planchot, Jonathan; De-Buttet, Come; Orlando, Bastien; Gays, Fabien; Mezzomo, Cécilia; Bernard, Emilie; Marris-Morini, Delphine; Vivien, Laurent; Kopp, Christophe; Boeuf, Frédéric

2016-05-01

A new technological platform aimed at making prototypes and feasibility studies has been setup at STMicroelectronics using 300mm wafer foundry facilities. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is devoted at developing and evaluating new devices and sub-systems in particular for wavelength division multiplexing (WDM) applications and ring resonator based applications. Developed in the course of PLAT4MFP7 European project, DAPHNE is a flexible platform that fits perfectly R&D needs. The fabrication flow enables the processing of photonic integrated circuits using a silicon-on-insulator (SOI) of 300nm, partial etches of 150nm and 50nm and a total silicon etching. Consequently, two varieties of rib waveguides and one strip waveguide can be fabricated simultaneously with auto-alignment properties. The process variability on the 150nm partially etched silicon and the thin 50nm slab region are both less than 6 nm. Using a variety of different implantation configurations and a back-end of line of 5 metal layers, active devices are fabricated both in germanium and silicon. An available far back-end of line process consists of making 20 μm diameter copper posts on top of the electrical pads so that an electronic integrated circuit can be bonded on top the photonic die by 3D integration. Besides having those fabrication process options, DAPHNE is equipped with a library of standard cells for optical routing and multiplexing. Moreover, typical Mach-Zehnder modulators based on silicon pn junctions are also available for optical signal modulation. To achieve signal detection, germanium photodetectors also exist as standard cells. The measured single-mode propagation losses are 3.5 dB/cm for strip, 3.7 dB/cm for deep-rib (50nm slab) and 1.4 dB/cm for standard rib (150nm slab) waveguides. Transition tapers between different waveguide structures are as low as 0.006 dB.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Silicon Nanowire Growth at Chosen Positions and Orientations

NASA Technical Reports Server (NTRS)

Getty, Stephanie A.

2009-01-01

It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.

Feasibility study for future implantable neural-silicon interface devices.

PubMed

Al-Armaghany, Allann; Yu, Bo; Mak, Terrence; Tong, Kin-Fai; Sun, Yihe

2011-01-01

The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

10 Gb/s operation of photonic crystal silicon optical modulators.

PubMed

Nguyen, Hong C; Sakai, Yuya; Shinkawa, Mizuki; Ishikura, Norihiro; Baba, Toshihiko

2011-07-04

We report the first experimental demonstration of 10 Gb/s modulation in a photonic crystal silicon optical modulator. The device consists of a 200 μm-long SiO2-clad photonic crystal waveguide, with an embedded p-n junction, incorporated into an asymmetric Mach-Zehnder interferometer. The device is integrated on a SOI chip and fabricated by CMOS-compatible processes. With the bias voltage set at 0 V, we measure a V(π)L < 0.056 V∙cm. Optical modulation is demonstrated by electrically driving the device with a 2(31) - 1 bit non-return-to-zero pseudo-random bit sequence signal. An open eye pattern is observed at bitrates of 10 Gb/s and 2 Gb/s, with and without pre-emphasis of the drive signal, respectively.

Microstructure factor and mechanical and electronic properties of hydrogenated amorphous and nanocrystalline silicon thin-films for microelectromechanical systems applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mouro, J.; Gualdino, A.; Chu, V.

2013-11-14

Thin-film silicon allows the fabrication of MEMS devices at low processing temperatures, compatible with monolithic integration in advanced electronic circuits, on large-area, low-cost, and flexible substrates. The most relevant thin-film properties for applications as MEMS structural layers are the deposition rate, electrical conductivity, and mechanical stress. In this work, n{sup +}-type doped hydrogenated amorphous and nanocrystalline silicon thin-films were deposited by RF-PECVD, and the influence of the hydrogen dilution in the reactive mixture, the RF-power coupled to the plasma, the substrate temperature, and the deposition pressure on the structural, electrical, and mechanical properties of the films was studied. Three differentmore » types of silicon films were identified, corresponding to three internal structures: (i) porous amorphous silicon, deposited at high rates and presenting tensile mechanical stress and low electrical conductivity, (ii) dense amorphous silicon, deposited at intermediate rates and presenting compressive mechanical stress and higher values of electrical conductivity, and (iii) nanocrystalline silicon, deposited at very low rates and presenting the highest compressive mechanical stress and electrical conductivity. These results show the combinations of electromechanical material properties available in silicon thin-films and thus allow the optimized selection of a thin silicon film for a given MEMS application. Four representative silicon thin-films were chosen to be used as structural material of electrostatically actuated MEMS microresonators fabricated by surface micromachining. The effect of the mechanical stress of the structural layer was observed to have a great impact on the device resonance frequency, quality factor, and actuation force.« less

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Raichoudhury, P.; Mollenkopf, H. C.

1981-01-01

The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly solar grade silicon. Cr is highly mobile in silicon even at temperatures as low as 600 C. Contrasting with earlier data for Mo, Ti, and V, Cr concentrations vary from place to place in polycrystalline silicon wafers and the electrically-active Cr concentration in the polysilicon is more than an order of magnitude smaller than would be projected from single crystal impurity data. We hypothesize that Cr diffuses during ingot cooldown after growth, preferentially segregates to grain and becomes electrically deactivated. Accelerated aging data from Ni-contaminated silicon imply that no significant impurity-induced cell performance reduction should be expected over a twenty year device lifetime.

Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation

NASA Astrophysics Data System (ADS)

Feng, Wei; Watanabe, Naoya; Shimamoto, Haruo; Aoyagi, Masahiro; Kikuchi, Katsuya

2018-07-01

The residual stresses induced around through-silicon vias (TSVs) by a fabrication process is one of the major concerns of reliability. We proposed a methodology to investigate the residual stress in a via-last TSV. Firstly, radial and axial thermal stresses were measured by polarized Raman spectroscopy. The agreement between the simulated stress level and measured results validated the detail simulation model. Furthermore, the validated simulation model was adopted to the study of residual stress by element death/birth methods. The residual stress at room temperature concentrates at passivation layers owing to the high fabrication process temperatures of 420 °C for SiN film and 350 °C for SiO2 films. For a Si substrate, a high-level stress was observed near potential device locations, which requires attention to address reliability concerns in stress-sensitive devices. This methodology of residual stress analysis can be adopted to investigate the residual stress in other devices.

Distinct photoresponse in graphene induced by laser irradiation and interfacial gating.

NASA Astrophysics Data System (ADS)

Wang, Wenhui; Guo, Xitao; Nan, Haiyan; Ni, Zhenhua; Spectroscopy; Optoelectronics Group Team

Graphene-based photodetectors have recently received much attention due to its unique optical and electronic properties. The photoresponse modulation plays a crucial role in the study of photocurrent generation mechanism and optoelectronic applications. Here, the tunable p-p +-p junctions of graphene were fabricated through simple laser irradiation process. Distinct photoresponse was observed at the graphene (G)-laser irradiation graphene (LIG) junction. Detailed investigation suggests that the photo-thermoelectric effect, instead of the photovoltaic effect, dominates the photocurrent generation at the G-LIG junction. On the other hand, the localized interface states, existing at the silicon dioxide/lightly doped Si interface, would induce an interfacial gating mechanism, which will enhance the photoresponsivity to 1000 A/W. More important, the photoresponse time of our device has been pushed to 400ns. The current device structure does not need a complicated fabrication process and is fully compatible with silicon technology. This work will open up a route to graphene-based high-performance optoelectronic devices. This work was supported by Southeast University.

Monitoring of Vital Signs with Flexible and Wearable Medical Devices.

PubMed

Khan, Yasser; Ostfeld, Aminy E; Lochner, Claire M; Pierre, Adrien; Arias, Ana C

2016-06-01

Advances in wireless technologies, low-power electronics, the internet of things, and in the domain of connected health are driving innovations in wearable medical devices at a tremendous pace. Wearable sensor systems composed of flexible and stretchable materials have the potential to better interface to the human skin, whereas silicon-based electronics are extremely efficient in sensor data processing and transmission. Therefore, flexible and stretchable sensors combined with low-power silicon-based electronics are a viable and efficient approach for medical monitoring. Flexible medical devices designed for monitoring human vital signs, such as body temperature, heart rate, respiration rate, blood pressure, pulse oxygenation, and blood glucose have applications in both fitness monitoring and medical diagnostics. As a review of the latest development in flexible and wearable human vitals sensors, the essential components required for vitals sensors are outlined and discussed here, including the reported sensor systems, sensing mechanisms, sensor fabrication, power, and data processing requirements. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Silicon-on ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Grung, B. L.; Heaps, J. D.; Schmit, F. M.; Schuldt, S. B.; Zook, J. D.

1981-01-01

The technical feasibility of producing solar-cell-quality sheet silicon to meet the Department of Energy (DOE) 1986 overall price goal of $0.70/watt was investigated. With the silicon-on-ceramic (SOC) approach, a low-cost ceramic substrate is coated with large-grain polycrystalline silicon by unidirectional solidification of molten silicon. This effort was divided into several areas of investigation in order to most efficiently meet the goals of the program. These areas include: (1) dip-coating; (2) continuous coating designated SCIM-coating, and acronym for Silicon Coating by an Inverted Meniscus (SCIM); (3) material characterization; (4) cell fabrication and evaluation; and (5) theoretical analysis. Both coating approaches were successful in producing thin layers of large grain, solar-cell-quality silicon. The dip-coating approach was initially investigated and considerable effort was given to this technique. The SCIM technique was adopted because of its scale-up potential and its capability to produce more conventiently large areas of SOC.

Organic electronics with polymer dielectrics on plastic substrates fabricated via transfer printing

NASA Astrophysics Data System (ADS)

Hines, Daniel R.

Printing methods are fast becoming important processing techniques for the fabrication of flexible electronics. Some goals for flexible electronics are to produce cheap, lightweight, disposable radio frequency identification (RFID) tags, very large flexible displays that can be produced in a roll-to-roll process and wearable electronics for both the clothing and medical industries. Such applications will require fabrication processes for the assembly of dissimilar materials onto a common substrate in ways that are compatible with organic and polymeric materials as well as traditional solid-state electronic materials. A transfer printing method has been developed with these goals and application in mind. This printing method relies primarily on differential adhesion where no chemical processing is performed on the device substrate. It is compatible with a wide variety of materials with each component printed in exactly the same way, thus avoiding any mixed processing steps on the device substrate. The adhesion requirements of one material printed onto a second are studied by measuring the surface energy of both materials and by surface treatments such as plasma exposure or the application of self-assembled monolayers (SAM). Transfer printing has been developed within the context of fabricating organic electronics onto plastic substrates because these materials introduce unique opportunities associated with processing conditions not typically required for traditional semiconducting materials. Compared to silicon, organic semiconductors are soft materials that require low temperature processing and are extremely sensitive to chemical processing and environmental contamination. The transfer printing process has been developed for the important and commonly used organic semiconducting materials, pentacene (Pn) and poly(3-hexylthiophene) (P3HT). A three-step printing process has been developed by which these materials are printed onto an electrode subassembly consisting of previously printed electrodes separated by a polymer dielectric layer all on a plastic substrate. These bottom contact, flexible organic thin-film transistors (OTFT) have been compared to unprinted (reference) devices consisting of top contact electrodes and a silicon dioxide dielectric layer on a silicon substrate. Printed Pn and P3HT TFTs have been shown to out-perform the reference devices. This enhancement has been attributed to an annealing under pressure of the organic semiconducting material.

Photovoltaic device using single wall carbon nanotubes and method of fabricating the same

DOEpatents

Biris, Alexandru S.; Li, Zhongrui

2012-11-06

A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.

Embracing the quantum limit in silicon computing.

PubMed

Morton, John J L; McCamey, Dane R; Eriksson, Mark A; Lyon, Stephen A

2011-11-16

Quantum computers hold the promise of massive performance enhancements across a range of applications, from cryptography and databases to revolutionary scientific simulation tools. Such computers would make use of the same quantum mechanical phenomena that pose limitations on the continued shrinking of conventional information processing devices. Many of the key requirements for quantum computing differ markedly from those of conventional computers. However, silicon, which plays a central part in conventional information processing, has many properties that make it a superb platform around which to build a quantum computer. © 2011 Macmillan Publishers Limited. All rights reserved

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Plasmonic engineering of spontaneous emission from silicon nanocrystals.

PubMed

Goffard, Julie; Gérard, Davy; Miska, Patrice; Baudrion, Anne-Laure; Deturche, Régis; Plain, Jérôme

2013-01-01

Silicon nanocrystals offer huge advantages compared to other semi-conductor quantum dots as they are made from an abundant, non-toxic material and are compatible with silicon devices. Besides, among a wealth of extraordinary properties ranging from catalysis to nanomedicine, metal nanoparticles are known to increase the radiative emission rate of semiconductor quantum dots. Here, we use gold nanoparticles to accelerate the emission of silicon nanocrystals. The resulting integrated hybrid emitter is 5-fold brighter than bare silicon nanocrystals. We also propose an in-depth analysis highlighting the role of the different physical parameters in the photoluminescence enhancement phenomenon. This result has important implications for the practical use of silicon nanocrystals in optoelectronic devices, for instance for the design of efficient down-shifting devices that could be integrated within future silicon solar cells.

Processing-Induced Electrically Active Defects in Black Silicon Nanowire Devices.

PubMed

Carapezzi, Stefania; Castaldini, Antonio; Mancarella, Fulvio; Poggi, Antonella; Cavallini, Anna

2016-04-27

Silicon nanowires (Si NWs) are widely investigated nowadays for implementation in advanced energy conversion and storage devices, as well as many other possible applications. Black silicon (BSi)-NWs are dry etched NWs that merge the advantages related to low-dimensionality with the special industrial appeal connected to deep reactive ion etching (RIE). In fact, RIE is a well established technique in microelectronics manufacturing. However, RIE processing could affect the electrical properties of BSi-NWs by introducing deep states into their forbidden gap. This work applies deep level transient spectroscopy (DLTS) to identify electrically active deep levels and the associated defects in dry etched Si NW arrays. Besides, the successful fitting of DLTS spectra of BSi-NWs-based Schottky barrier diodes is an experimental confirmation that the same theoretical framework of dynamic electronic behavior of deep levels applies in bulk as well as in low dimensional structures like NWs, when quantum confinement conditions do not occur. This has been validated for deep levels associated with simple pointlike defects as well as for deep levels associated with defects with richer structures, whose dynamic electronic behavior implies a more complex picture.

A wide bandgap silicon carbide (SiC) gate driver for high-temperature and high-voltage applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lamichhane, Ranjan; Ericson, Milton Nance; Frank, Steven Shane

2014-01-01

Limitations of silicon (Si) based power electronic devices can be overcome with Silicon Carbide (SiC) because of its remarkable material properties. SiC is a wide bandgap semiconductor material with larger bandgap, lower leakage currents, higher breakdown electric field, and higher thermal conductivity, which promotes higher switching frequencies for high power applications, higher temperature operation, and results in higher power density devices relative to Si [1]. The proposed work is focused on design of a SiC gate driver to drive a SiC power MOSFET, on a Cree SiC process, with rise/fall times (less than 100 ns) suitable for 500 kHz tomore » 1 MHz switching frequency applications. A process optimized gate driver topology design which is significantly different from generic Si circuit design is proposed. The ultimate goal of the project is to integrate this gate driver into a Toyota Prius plug-in hybrid electric vehicle (PHEV) charger module. The application of this high frequency charger will result in lighter, smaller, cheaper, and a more efficient power electronics system.« less

Benzocyclobutene-based electric micromachines supported on microball bearings: Design, fabrication, and characterization

NASA Astrophysics Data System (ADS)

Modafe, Alireza

This dissertation summarizes the research activities that led to the development of the first microball-bearing-supported linear electrostatic micromotor with benzocyclobutene (BCB) low-k polymer insulating layers. The primary application of this device is long-range, high-speed linear micropositioning. The future generations of this device include rotary electrostatic micromotors and microgenerators. The development of the first generation of microball-bearing-supported micromachines, including device theory, design, and modeling, material characterization, process development, device fabrication, and device test and characterization is presented. The first generation of these devices is based on a 6-phase, bottom-drive, linear, variable-capacitance micromotor (B-LVCM). The design of the electrical and mechanical components of the micromotor, lumped-circuit modeling of the device and electromechanical characteristics, including variable capacitance, force, power, and speed are presented. Electrical characterization of BCB polymers, characterization of BCB chemical mechanical planarization (CMP), development of embedded BCB in silicon (EBiS) process, and integration of device components using microfabrication techniques are also presented. The micromotor consists of a silicon stator, a silicon slider, and four stainless-steel microballs. The aligning force profile of the micromotor was extracted from simulated and measured capacitances of all phases. An average total aligning force of 0.27 mN with a maximum of 0.41 mN, assuming a 100 V peak-to-peak square-wave voltage, was measured. The operation of the micromotor was verified by applying square-wave voltages and characterizing the slider motion. An average slider speed of 7.32 mm/s when excited by a 40 Hz, 120 V square-wave voltage was reached without losing the synchronization. This research has a pivotal impact in the field of power microelectromechanical systems (MEMS). It establishes the foundation for the development of more reliable, efficient electrostatic micromachines with variety of applications such as micropropulsion, high-speed micropumping, microfluid delivery, and microsystem power generation.

Waveguide based compact silicon Schottky photodetector with enhanced responsivity in the telecom spectral band.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2012-12-17

We experimentally demonstrate an on-chip compact and simple to fabricate silicon Schottky photodetector for telecom wavelengths operating on the basis of internal photoemission process. The device is realized using CMOS compatible approach of local-oxidation of silicon, which enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. The photodetector demonstrates enhanced internal responsivity of 12.5mA/W for operation wavelength of 1.55µm corresponding to an internal quantum efficiency of 1%, about two orders of magnitude higher than our previously demonstrated results [22]. We attribute this improved detection efficiency to the presence of surface roughness at the boundary between the materials forming the Schottky contact. The combination of enhanced quantum efficiency together with a simple fabrication process provides a promising platform for the realization of all silicon photodetectors and their integration with other nanophotonic and nanoplasmonic structures towards the construction of monolithic silicon opto-electronic circuitry on-chip.

Magneto-optical non-reciprocal devices in silicon photonics

PubMed Central

Shoji, Yuya; Mizumoto, Tetsuya

2014-01-01

Silicon waveguide optical non-reciprocal devices based on the magneto-optical effect are reviewed. The non-reciprocal phase shift caused by the first-order magneto-optical effect is effective in realizing optical non-reciprocal devices in silicon waveguide platforms. In a silicon-on-insulator waveguide, the low refractive index of the buried oxide layer enhances the magneto-optical phase shift, which reduces the device footprints. A surface activated direct bonding technique was developed to integrate a magneto-optical garnet crystal on the silicon waveguides. A silicon waveguide optical isolator based on the magneto-optical phase shift was demonstrated with an optical isolation of 30 dB and insertion loss of 13 dB at a wavelength of 1548 nm. Furthermore, a four port optical circulator was demonstrated with maximum isolations of 15.3 and 9.3 dB in cross and bar ports, respectively, at a wavelength of 1531 nm. PMID:27877640

Hybrid Integration of Solid-State Quantum Emitters on a Silicon Photonic Chip.

PubMed

Kim, Je-Hyung; Aghaeimeibodi, Shahriar; Richardson, Christopher J K; Leavitt, Richard P; Englund, Dirk; Waks, Edo

2017-12-13

Scalable quantum photonic systems require efficient single photon sources coupled to integrated photonic devices. Solid-state quantum emitters can generate single photons with high efficiency, while silicon photonic circuits can manipulate them in an integrated device structure. Combining these two material platforms could, therefore, significantly increase the complexity of integrated quantum photonic devices. Here, we demonstrate hybrid integration of solid-state quantum emitters to a silicon photonic device. We develop a pick-and-place technique that can position epitaxially grown InAs/InP quantum dots emitting at telecom wavelengths on a silicon photonic chip deterministically with nanoscale precision. We employ an adiabatic tapering approach to transfer the emission from the quantum dots to the waveguide with high efficiency. We also incorporate an on-chip silicon-photonic beamsplitter to perform a Hanbury-Brown and Twiss measurement. Our approach could enable integration of precharacterized III-V quantum photonic devices into large-scale photonic structures to enable complex devices composed of many emitters and photons.

Dynamic observation on the growth behaviors in manganese silicide/silicon nanowire heterostructures.

PubMed

Hsieh, Yu-Hsun; Chiu, Chung-Hua; Huang, Chun-Wei; Chen, Jui-Yuan; Lin, Wan-Jhen; Wu, Wen-Wei

2015-02-07

Metal silicide nanowires (NWs) are very interesting materials with diverse physical properties. Among the silicides, manganese silicide nanostructures have attracted wide attention due to their several potential applications, including in microelectronics, optoelectronics, spintronics and thermoelectric devices. In this work, we exhibited the formation of pure manganese silicide and manganese silicide/silicon nanowire heterostructures through solid state reaction with line contacts between manganese pads and silicon NWs. Dynamical process and phase characterization were investigated by in situ transmission electron microscopy (in situ TEM) and spherical aberration corrected scanning transmission electron microscopy (Cs-corrected STEM), respectively. The growth dynamics of the manganese silicide phase under thermal effects were systematically studied. Additionally, Al2O3, serving as the surface oxide, altered the growth behavior of the MnSi nanowire, enhancing the silicide/Si epitaxial growth and effecting the diffusion process in the silicon nanowire as well. In addition to fundamental science, this significant study has great potential in advancing future processing techniques in nanotechnology and related applications.

Energy Storage Materials from Nature through Nanotechnology: A Sustainable Route from Reed Plants to a Silicon Anode for Lithium-Ion Batteries.

PubMed

Liu, Jun; Kopold, Peter; van Aken, Peter A; Maier, Joachim; Yu, Yan

2015-08-10

Silicon is an attractive anode material in energy storage devices, as it has a ten times higher theoretical capacity than its state-of-art carbonaceous counterpart. However, the common process to synthesize silicon nanostructured electrodes is complex, costly, and energy-intensive. Three-dimensional (3D) porous silicon-based anode materials have been fabricated from natural reed leaves by calcination and magnesiothermic reduction. This sustainable and highly abundant silica source allows for facile production of 3D porous silicon with very good electrochemical performance. The obtained silicon anode retains the 3D hierarchical architecture of the reed leaf. Impurity leaching and gas release during the fabrication process leads to an interconnected porosity and the reductive treatment to an inside carbon coating. Such anodes show a remarkable Li-ion storage performance: even after 4000 cycles and at a rate of 10 C, a specific capacity of 420 mA h g(-1) is achieved. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Plasma processes for producing silanes and derivatives thereof

DOEpatents

Laine, Richard M; Massey, Dean Richard; Peterson, Peter Young

2014-03-25

The invention is generally related to process for generating one or more molecules having the formula Si.sub.xH.sub.y, Si.sub.xD.sub.y, Si.sub.xH.sub.yD.sub.z, and mixtures thereof, where x,y and z are integers .gtoreq.1, H is hydrogen and D is deuterium, such as silane, comprising the steps of: providing a silicon containing material, wherein the silicon containing material includes at least 20 weight percent silicon atoms based on the total weight of the silicon containing material; generating a plasma capable of vaporizing a silicon atom, sputtering a silicon atom, or both using a plasma generating device; and contacting the plasma to the silicon containing material in a chamber having an atmosphere that includes at least about 0.5 mole percent hydrogen atoms and/or deuterium atoms based on the total moles of atoms in the atmosphere; so that a molecule having the formula Si.sub.xH.sub.y; (e.g., silane) is generated. The process preferably includes a step of removing one or more impurities from the Si.sub.xH.sub.y (e.g., the silane) to form a clean Si.sub.xH.sub.y, Si.sub.xD.sub.y, Si.sub.xH.sub.yD.sub.z (e.g., silane). The process may also include a step of reacting the Si.sub.xH.sub.y, Si.sub.xD.sub.y, Si.sub.xH.sub.yD.sub.z (e.g., the silane) to produce a high purity silicon containing material such as electronic grade metallic silicon, photovoltaic grade metallic silicon, or both.

Economic analysis of crystal growth in space

NASA Technical Reports Server (NTRS)

Ulrich, D. R.; Chung, A. M.; Yan, C. S.; Mccreight, L. R.

1972-01-01

Many advanced electronic technologies and devices for the 1980's are based on sophisticated compound single crystals, i.e. ceramic oxides and compound semiconductors. Space processing of these electronic crystals with maximum perfection, purity, and size is suggested. No ecomonic or technical justification was found for the growth of silicon single crystals for solid state electronic devices in space.

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

NASA Astrophysics Data System (ADS)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

Black silicon with self-cleaning surface prepared by wetting processes

PubMed Central

2013-01-01

This paper reports on a simple method to prepare a hydrophobic surface on black silicon, which is fabricated by metal-assisted wet etching. To increase the reaction rate, the reaction device was placed in a heat collection-constant temperature type magnetic stirrer and set at room temperature. It was demonstrated that the micro- and nanoscale spikes on the black silicon made the surface become hydrophobic. As the reaction rate increases, the surface hydrophobicity becomes more outstanding and presents self-cleaning until the very end. The reflectance of the black silicon is drastically suppressed over a broad spectral range due to the unique geometry, which is effective for the enhancement of absorption. PMID:23941184

Mn-silicide nanostructures aligned on massively parallel silicon nano-ribbons

NASA Astrophysics Data System (ADS)

De Padova, Paola; Ottaviani, Carlo; Ronci, Fabio; Colonna, Stefano; Olivieri, Bruno; Quaresima, Claudio; Cricenti, Antonio; Dávila, Maria E.; Hennies, Franz; Pietzsch, Annette; Shariati, Nina; Le Lay, Guy

2013-01-01

The growth of Mn nanostructures on a 1D grating of silicon nano-ribbons is investigated at atomic scale by means of scanning tunneling microscopy, low energy electron diffraction and core level photoelectron spectroscopy. The grating of silicon nano-ribbons represents an atomic scale template that can be used in a surface-driven route to control the combination of Si with Mn in the development of novel materials for spintronics devices. The Mn atoms show a preferential adsorption site on silicon atoms, forming one-dimensional nanostructures. They are parallel oriented with respect to the surface Si array, which probably predetermines the diffusion pathways of the Mn atoms during the process of nanostructure formation.

Mn-silicide nanostructures aligned on massively parallel silicon nano-ribbons.

PubMed

De Padova, Paola; Ottaviani, Carlo; Ronci, Fabio; Colonna, Stefano; Olivieri, Bruno; Quaresima, Claudio; Cricenti, Antonio; Dávila, Maria E; Hennies, Franz; Pietzsch, Annette; Shariati, Nina; Le Lay, Guy

2013-01-09

The growth of Mn nanostructures on a 1D grating of silicon nano-ribbons is investigated at atomic scale by means of scanning tunneling microscopy, low energy electron diffraction and core level photoelectron spectroscopy. The grating of silicon nano-ribbons represents an atomic scale template that can be used in a surface-driven route to control the combination of Si with Mn in the development of novel materials for spintronics devices. The Mn atoms show a preferential adsorption site on silicon atoms, forming one-dimensional nanostructures. They are parallel oriented with respect to the surface Si array, which probably predetermines the diffusion pathways of the Mn atoms during the process of nanostructure formation.

Electric measurements of PV heterojunction structures a-SiC/c-Si

NASA Astrophysics Data System (ADS)

Perný, Milan; Šály, Vladimír; Janíček, František; Mikolášek, Miroslav; Váry, Michal; Huran, Jozef

2018-01-01

Due to the particular advantages of amorphous silicon or its alloys with carbon in comparison to conventional crystalline materials makes such a material still interesting for study. The amorphous silicon carbide may be used in a number of micro-mechanical and micro-electronics applications and also for photovoltaic energy conversion devices. Boron doped thin layers of amorphous silicon carbide, presented in this paper, were prepared due to the optimization process for preparation of heterojunction solar cell structure. DC and AC measurement and subsequent evaluation were carried out in order to comprehensively assess the electrical transport processes in the prepared a-SiC/c-Si structures. We have investigated the influence of methane content in deposition gas mixture and different electrode configuration.

Programmable 2-D Addressable Cryogenic Aperture Masks

NASA Technical Reports Server (NTRS)

Kutyrev, A. S.; Moseley, S. H.; Jhabvala, M.; Li, M.; Schwinger, D. S.; Silverberg, R. F.; Wesenberg, R. P.

2004-01-01

We are developing a two-dimensional array of square microshutters (programmable aperture mask) for a multi-object spectrometer for the James Webb Space Telescope (JWST). This device will provide random access selection of the areas in the field to be studied. The device is in essence a close packed array of square slits, each of which can be opened independently to select areas of the sky for detailed study.The device is produced using a 100-micron thick silicon wafer as a substrate with 0.5-micron thick silicon nitride shutters on top of it. Silicon nitride has been selected as the blade and flexure material because its stiffness allows thinner and lighter structures than single crystal Si, the chief alternative, and because of its ease of manufacture. The 100 micron silicon wafer is backetched in a high aspect ratio Deep Reactive Ion Etching (Deep RIE) to leave only a support grid for the shutters and the address electronics. The shutter actuation is done magnetically whereas addressing is electrostatic. 128x128 format microshutter arrays have been produced. Their operation has been demostarted on 32x32 subarrays. Good reliability of the fabrication process and good quality of the microshutters has been achieved. The mechanical behavior and optical performance of the fabricated arrays at cryogenic temperature are being studied.

Characterization of Si (sub X)Ge (sub 1-x)/Si Heterostructures for Device Applications Using Spectroscopic Ellipsometry

NASA Technical Reports Server (NTRS)

Sieg, R. M.; Alterovitz, S. A.; Croke, E. T.; Harrell, M. J.; Tanner, M.; Wang, K. L.; Mena, R. A.; Young, P. G.

1993-01-01

Spectroscopic ellipsometry (SE) characterization of several complex Si (sub X)Ge (sub 1-x)/Si heterostructures prepared for device fabrication, including structures for heterojunction bipolar transistors (HBT), p-type and n-type heterostructure modulation doped field effect transistors, has been performed. We have shown that SE can simultaneously determine all active layer thicknesses, Si (sub X)Ge (sub 1-x) compositions, and the oxide overlayer thickness, with only a general knowledge of the structure topology needed a priori. The characterization of HBT material included the SE analysis of a Si (sub X)Ge (sub 1-x) layer deeply buried (600 nanometers) under the silicon emitter and cap layers. In the SE analysis of n-type heterostructures, we examined for the first time a silicon layer under tensile strain. We found that an excellent fit can be obtained using optical constants of unstrained silicon to represent the strained silicon conduction layer. We also used SE to measure lateral sample homogeneity, providing quantitative identification of the inhomogeneous layer. Surface overlayers resulting from prior sample processing were also detected and measured quantitatively. These results should allow SE to be used extensively as a non-destructive means of characterizing Si (sub X)Ge (sub 1-x)/Si heterostructures prior to device fabrication and testing.

Potentialities of silicon nanowire forests for thermoelectric generation

NASA Astrophysics Data System (ADS)

Dimaggio, Elisabetta; Pennelli, Giovanni

2018-04-01

Silicon is a material with very good thermoelectric properties, with regard to Seebeck coefficient and electrical conductivity. Low thermal conductivities, and hence high thermal to electrical conversion efficiencies, can be achieved in nanostructures, which are smaller than the phonon mean free path but large enough to preserve the electrical conductivity. We demonstrate that it is possible to fabricate a leg of a thermoelectric generator based on large collections of long nanowires, placed perpendicularly to the two faces of a silicon wafer. The process exploits the metal assisted etching technique which is simple, low cost, and can be easily applied to large surfaces. Copper can be deposited by electrodeposition on both faces, so that contacts can be provided, on top of the nanowires. Thermal conductivity of silicon nanowire forests with more than 107 nanowires mm-2 have been measured; the result is comparable with that achieved by several groups on devices based on few nanowires. On the basis of the measured parameters, numerical calculations of the efficiency of silicon-based thermoelectric generators are reported, and the potentialities of these devices for thermal to electrical energy conversion are shown. Criteria to improve the conversion efficiency are suggested and described.

Laser post-processing of halide perovskites for enhanced photoluminescence and absorbance

NASA Astrophysics Data System (ADS)

Tiguntseva, E. Y.; Saraeva, I. N.; Kudryashov, S. I.; Ushakova, E. V.; Komissarenko, F. E.; Ishteev, A. R.; Tsypkin, A. N.; Haroldson, R.; Milichko, V. A.; Zuev, D. A.; Makarov, S. V.; Zakhidov, A. A.

2017-11-01

Hybrid halide perovskites have emerged as one of the most promising type of materials for thin-film photovoltaic and light-emitting devices. Further boosting their performance is critically important for commercialization. Here we use femtosecond laser for post-processing of organo-metalic perovskite (MAPbI3) films. The high throughput laser approaches include both ablative silicon nanoparticles integration and laser-induced annealing. By using these techniques, we achieve strong enhancement of photoluminescence as well as useful light absorption. As a result, we observed experimentally 10-fold enhancement of absorbance in a perovskite layer with the silicon nanoparticles. Direct laser annealing allows for increasing of photoluminescence over 130%, and increase absorbance over 300% in near-IR range. We believe that the developed approaches pave the way to novel scalable and highly effective designs of perovskite based devices.

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Demaurex, Bénédicte, E-mail: benedicte.demaurex@epfl.ch; Bartlome, Richard; Seif, Johannes P.

2014-08-07

Low-temperature (≤200 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-enhanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems not only frommore » the growth conditions but also from unintentional contamination of the reactor. Based on our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.« less

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

DOE PAGES

Demaurex, Bénédicte; Bartlome, Richard; Seif, Johannes P.; ...

2014-08-05

Low-temperature (≤ 180 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-ehanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems notmore » only from the growth conditions but also from unintentional contamination of the reactor. As a result of our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.« less

Nanoscale doping of compound semiconductors by solid phase dopant diffusion

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ahn, Jaehyun, E-mail: jaehyun.ahn@utexas.edu; Koh, Donghyi; Roy, Anupam

2016-03-21

Achieving damage-free, uniform, abrupt, ultra-shallow junctions while simultaneously controlling the doping concentration on the nanoscale is an ongoing challenge to the scaling down of electronic device dimensions. Here, we demonstrate a simple method of effectively doping ΙΙΙ-V compound semiconductors, specifically InGaAs, by a solid phase doping source. This method is based on the in-diffusion of oxygen and/or silicon from a deposited non-stoichiometric silicon dioxide (SiO{sub x}) film on InGaAs, which then acts as donors upon activation by annealing. The dopant profile and concentration can be controlled by the deposited film thickness and thermal annealing parameters, giving active carrier concentration ofmore » 1.4 × 10{sup 18 }cm{sup −3}. Our results also indicate that conventional silicon based processes must be carefully reviewed for compound semiconductor device fabrication to prevent unintended doping.« less

Efficient Monolithic Perovskite/Silicon Tandem Solar Cell with Cell Area >1 cm(2).

PubMed

Werner, Jérémie; Weng, Ching-Hsun; Walter, Arnaud; Fesquet, Luc; Seif, Johannes Peter; De Wolf, Stefaan; Niesen, Bjoern; Ballif, Christophe

2016-01-07

Monolithic perovskite/crystalline silicon tandem solar cells hold great promise for further performance improvement of well-established silicon photovoltaics; however, monolithic tandem integration is challenging, evidenced by the modest performances and small-area devices reported so far. Here we present first a low-temperature process for semitransparent perovskite solar cells, yielding efficiencies of up to 14.5%. Then, we implement this process to fabricate monolithic perovskite/silicon heterojunction tandem solar cells yielding efficiencies of up to 21.2 and 19.2% for cell areas of 0.17 and 1.22 cm(2), respectively. Both efficiencies are well above those of the involved subcells. These single-junction perovskite and tandem solar cells are hysteresis-free and demonstrate steady performance under maximum power point tracking for several minutes. Finally, we present the effects of varying the intermediate recombination layer and hole transport layer thicknesses on tandem cell photocurrent generation, experimentally and by transfer matrix simulations.

Sputtered pin amorphous silicon semi-conductor device and method therefor

DOEpatents

Moustakas, Theodore D.; Friedman, Robert A.

1983-11-22

A high efficiency amorphous silicon PIN semi-conductor device is constructed by the sequential sputtering of N, I and P layers of amorphous silicon and at least one semi-transparent ohmic electrode. A method of construction produces a PIN device, exhibiting enhanced physical integrity and facilitates ease of construction in a singular vacuum system and vacuum pump down procedure.

Silicon Chemical Vapor Deposition Process Using a Half-Inch Silicon Wafer for Minimal Manufacturing System

NASA Astrophysics Data System (ADS)

Li, Ning; Habuka, Hitoshi; Ikeda, Shin-ichi; Hara, Shiro

A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed and verified by employing the technical issues, such as (i) vertical gas flow, (ii) thermal operation using a highly concentrated infrared flux, and (iii) reactor cleaning by chlorine trifluoride gas. The combination of (i) and (ii) could achieve a low heating power and a fast cooling designed by the heat balance of the small wafer placed at a position outside of the reflector. The cleaning process could be rapid by (iii). The heating step could be skipped because chlorine trifluoride gas was reactive at any temperature higher than room temperature.

Improved Method of Manufacturing SiC Devices

NASA Technical Reports Server (NTRS)

Okojie, Robert S.

2005-01-01

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Fabrication of sub-12 nm thick silicon nanowires by processing scanning probe lithography masks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kyoung Ryu, Yu; Garcia, Ricardo, E-mail: r.garcia@csic.es; Aitor Postigo, Pablo

2014-06-02

Silicon nanowires are key elements to fabricate very sensitive mechanical and electronic devices. We provide a method to fabricate sub-12 nm silicon nanowires in thickness by combining oxidation scanning probe lithography and anisotropic dry etching. Extremely thin oxide masks (0.3–1.1 nm) are transferred into nanowires of 2–12 nm in thickness. The width ratio between the mask and the silicon nanowire is close to one which implies that the nanowire width is controlled by the feature size of the nanolithography. This method enables the fabrication of very small single silicon nanowires with cross-sections below 100 nm{sup 2}. Those values are the smallest obtained withmore » a top-down lithography method.« less

Back contact to film silicon on metal for photovoltaic cells

DOEpatents

Branz, Howard M.; Teplin, Charles; Stradins, Pauls

2013-06-18

A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.

Low-loss silicon-on-insulator shallow-ridge TE and TM waveguides formed using thermal oxidation.

PubMed

Pafchek, R; Tummidi, R; Li, J; Webster, M A; Chen, E; Koch, T L

2009-02-10

A thermal oxidation fabrication technique is employed to form low-loss high-index-contrast silicon shallow-ridge waveguides in silicon-on-insulator (SOI) with maximally tight vertical confinement. Drop-port responses from weakly coupled ring resonators demonstrate propagation losses below 0.36 dB/cm for TE modes. This technique is also combined with "magic width" designs mitigating severe lateral radiation leakage for TM modes to achieve propagation loss values of 0.94 dB/cm. We discuss the fabrication process utilized to form these low-loss waveguides and implications for sensor devices in particular.

Ultralow power switching in a silicon-rich SiNy/SiNx double-layer resistive memory device.

PubMed

Kim, Sungjun; Chang, Yao-Feng; Kim, Min-Hwi; Bang, Suhyun; Kim, Tae-Hyeon; Chen, Ying-Chen; Lee, Jong-Ho; Park, Byung-Gook

2017-07-26

Here we demonstrate low-power resistive switching in a Ni/SiN y /SiN x /p ++ -Si device by proposing a double-layered structure (SiN y /SiN x ), where the two SiN layers have different trap densities. The LRS was measured to be as low as 1 nA at a voltage of 1 V, because the SiN x layer maintains insulating properties for the LRS. The single-layered device suffers from uncontrollability of the conducting path, accompanied by the inherent randomness of switching parameters, weak immunity to breakdown during the reset process, and a high operating current. On the other hand, for a double-layered device, the effective conducting path in each layer, which can determine the operating current, can be well controlled by the I CC during the initial forming and set processes. A one-step forming and progressive reset process is observed for a low-power mode, which differs from the high-power switching mode that shows a two-step forming and reset process. Moreover, nonlinear behavior in the LRS, whose origin can be attributed to the P-F conduction and F-N tunneling driven by abundant traps in the silicon-rich SiN x layer, would be beneficial for next-generation nonvolatile memory applications by using a conventional passive SiN x layer as an active dielectric.

Optimization of the bake-on siliconization of cartridges. Part I: Optimization of the spray-on parameters.

PubMed

Funke, Stefanie; Matilainen, Julia; Nalenz, Heiko; Bechtold-Peters, Karoline; Mahler, Hanns-Christian; Friess, Wolfgang

2016-07-01

Biopharmaceutical products are increasingly commercialized as drug/device combinations to enable self-administration. Siliconization of the inner syringe/cartridge glass barrel for adequate functionality is either performed at the supplier or drug product manufacturing site. Yet, siliconization processes are often insufficiently investigated. In this study, an optimized bake-on siliconization process for cartridges using a pilot-scale siliconization unit was developed. The following process parameters were investigated: spray quantity, nozzle position, spray pressure, time for pump dosing and the silicone emulsion concentration. A spray quantity of 4mg emulsion showed best, immediate atomization into a fine spray. 16 and 29mg of emulsion, hence 4-7-times the spray volume, first generated an emulsion jet before atomization was achieved. Poor atomization of higher quantities correlated with an increased spray loss and inhomogeneous silicone distribution, e.g., due to runlets forming build-ups at the cartridge lower edge and depositing on the star wheel. A prolonged time for pump dosing of 175ms led to a more intensive, long-lasting spray compared to 60ms as anticipated from a higher air-to-liquid ratio. A higher spray pressure of 2.5bar did not improve atomization but led to an increased spray loss. At a 20mm nozzle-to-flange distance the spray cone exactly reached the cartridge flange, which was optimal for thicker silicone layers at the flange to ease piston break-loose. Initially, 10μg silicone was sufficient for adequate extrusion in filled cartridges. However, both maximum break-loose and gliding forces in filled cartridges gradually increased from 5-8N to 21-22N upon 80weeks storage at room temperature. The increase for a 30μg silicone level from 3-6N to 10-12N was moderate. Overall, the study provides a comprehensive insight into critical process parameters during the initial spray-on process and the impact of these parameters on the characteristics of the silicone layer, also in context of long-term product storage. The presented experimental toolbox may be utilized for development or evaluation of siliconization processes. Copyright © 2016 Elsevier B.V. All rights reserved.

Silicon photonics for high-performance interconnection networks

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr

2011-12-01

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow.

Research Investigation Directed Toward Extending the Useful Range of the Electromagnetic Spectrum.

DTIC Science & Technology

1987-12-31

spectrometer ions photoionic emission threshold low temperature processing low energy ion beam silicon oxidation sputtering of silicon dioxide germanium...Osgood, "Optically-Induced, Room- Temperature Oxidation of Gallium Arsenide," Mat. Res. Soc. Symp. Proc. 75(1987):251-255. P. D. Brewer and R. M. Osgood... oxide films (40-70 A) at room temperature which are suitable for MOSFET devices, has been extensively studied experimentally and theoretically. The

Electrically conducting nanopatterns formed by chemical e-beam lithography via gold nanoparticle seeds.

PubMed

Schaal, Patrick A; Besmehn, Astrid; Maynicke, Eva; Noyong, Michael; Beschoten, Bernd; Simon, Ulrich

2012-02-07

We report the formation of thiol nanopatterns on SAM covered silicon wafers by converting sulfonic acid head groups via e-beam lithography. These thiol groups act as binding sites for gold nanoparticles, which can be enhanced to form electrically conducting nanostructures. This approach serves as a proof-of-concept for the combination of top-down and bottom-up processes for the generation of electrical devices on silicon.

New Energy-Dependent Soft X-Rav Damage In MOS Devices

NASA Astrophysics Data System (ADS)

Chan, Tung-Yi; Gaw, Henry; Seligson, Daniel; Pan, Lawrence; King, Paul L.; Pianetta, Piero

1988-06-01

An energy-dependent soft x-ray-induced device damage has been discovered in MOS devices fabricated using standard CMOS process. MOS devices were irradiated by monochromatic x-rays in energy range just above and below the silicon K-edge (1.84 keV). Photons below the K-edge is found to create more damage in the oxide and oxide/silicon interface than photons above the K-edge. This energy-dependent damage effect is believed to be due to charge traps generated during device fabrication. It is found that data for both n- and p-type devices lie along a universal curve if normalized threshold voltage shifts are plotted against absorbed dose in the oxide. The threshold voltage shift saturates when the absorbed dose in the oxide exceeds 1.4X105 mJ/cm3, corresponding to 6 Mrad in the oxide. Using isochronal anneals, the trapped charge damage is found to recover with an activation energy of 0.38 eV. A discrete radiation-induced damage state appears in the low frequency C-V curve in a temperature range from 1750C to 325°C.

Whatever happened to silicon carbide. [semiconductor devices

NASA Technical Reports Server (NTRS)

Campbell, R. B.

1981-01-01

The progress made in silicon carbide semiconductor devices in the 1955 to 1975 time frame is examined and reasons are given for the present lack of interest in the material. Its physical and chemical properties and methods of preparation are discussed. Fabrication techniques and the characteristics of silicon carbide devices are reviewed. It is concluded that a combination of economic factors and the lack of progress in fabrication techniques leaves no viable market for SiC devices in the near future.

Micromachined ultrasonic droplet generator based on a liquid horn structure

NASA Astrophysics Data System (ADS)

Meacham, J. M.; Ejimofor, C.; Kumar, S.; Degertekin, F. L.; Fedorov, A. G.

2004-05-01

A micromachined ultrasonic droplet generator is developed and demonstrated for drop-on-demand fluid atomization. The droplet generator comprises a bulk ceramic piezoelectric transducer for ultrasound generation, a reservoir for the ejection fluid, and a silicon micromachined liquid horn structure as the nozzle. The nozzles are formed using a simple batch microfabrication process that involves wet etching of (100) silicon in potassium hydroxide solution. Device operation is demonstrated by droplet ejection of water through 30 μm orifices at 1.49 and 2.30 MHz. The finite-element simulations of the acoustic fields in the cavity and electrical impedance of the device are in agreement with the measurements and indicate that the device utilizes cavity resonances in the 1-5 MHz range in conjunction with acoustic wave focusing by the pyramidally shaped nozzles to achieve low power operation.

RF performances of inductors integrated on localized p+-type porous silicon regions

PubMed Central

2012-01-01

To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate. PMID:23009746

Micromachined silicon cantilevers with integrated high-frequency magnetoimpedance sensors for simultaneous strain and magnetic field detection

NASA Astrophysics Data System (ADS)

Buettel, G.; Joppich, J.; Hartmann, U.

2017-12-01

Giant magnetoimpedance (GMI) measurements in the high-frequency regime utilizing a coplanar waveguide with an integrated Permalloy multilayer and micromachined on a silicon cantilever are reported. The fabrication process is described in detail. The aspect ratio of the magnetic multilayer in the magnetoresistive and magnetostrictive device was varied. Tensile strain and compressive strain were applied. Vector network analyzer measurements in the range from the skin effect to ferromagnetic resonance confirm the technological potential of GMI-based micro-electro-mechanical devices for strain and magnetic field sensing applications. The strain-impedance gauge factor was quantified by finite element strain calculations and reaches a maximum value of almost 200.

“Playing around” with Field-Effect Sensors on the Basis of EIS Structures, LAPS and ISFETs

PubMed Central

Schöning, Michael J.

2005-01-01

Microfabricated semiconductor devices are becoming increasingly relevant, also for the detection of biological and chemical quantities. Especially, the “marriage” of biomolecules and silicon technology often yields successful new sensor concepts. The fabrication techniques of such silicon-based chemical sensors and biosensors, respectively, will have a distinct impact in different fields of application such as medicine, food technology, environment, chemistry and biotechnology as well as information processing. Moreover, scientists and engineers are interested in the analytical benefits of miniaturised and microfabricated sensor devices. This paper gives a survey on different types of semiconductor-based field-effect structures that have been recently developed in our laboratory.

High-speed detection at two micrometres with monolithic silicon photodiodes

NASA Astrophysics Data System (ADS)

Ackert, Jason J.; Thomson, David J.; Shen, Li; Peacock, Anna C.; Jessop, Paul E.; Reed, Graham T.; Mashanovich, Goran Z.; Knights, Andrew P.

2015-06-01

With continued steep growth in the volume of data transmitted over optical networks there is a widely recognized need for more sophisticated photonics technologies to forestall a ‘capacity crunch’. A promising solution is to open new spectral regions at wavelengths near 2 μm and to exploit the long-wavelength transmission and amplification capabilities of hollow-core photonic-bandgap fibres and the recently available thulium-doped fibre amplifiers. To date, photodetector devices for this window have largely relied on III-V materials or, where the benefits of integration with silicon photonics are sought, GeSn alloys, which have been demonstrated thus far with only limited utility. Here, we describe a silicon photodiode operating at 20 Gbit s-1 in this wavelength region. The detector is compatible with standard silicon processing and is integrated directly with silicon-on-insulator waveguides, which suggests future utility in silicon-based mid-infrared integrated optics for applications in communications.

Heterogeneous silicon mesostructures for lipid-supported bioelectric interfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Yuanwen; Carvalho-de-Souza, João L.; Wong, Raymond C. S.

Silicon-based materials have widespread application as biophysical tools and biomedical devices. Here we introduce a biocompatible and degradable mesostructured form of silicon with multi-scale structural and chemical heterogeneities. The material was synthesized using mesoporous silica as a template through a chemical vapour deposition process. It has an amorphous atomic structure, an ordered nanowire-based framework and random submicrometre voids, and shows an average Young’s modulus that is 2–3 orders of magnitude smaller than that of single-crystalline silicon. In addition, we used the heterogeneous silicon mesostructures to design a lipid-bilayer-supported bioelectric interface that is remotely controlled and temporally transient, and that permitsmore » non-genetic and subcellular optical modulation of the electrophysiology dynamics in single dorsal root ganglia neurons. Our findings suggest that the biomimetic expansion of silicon into heterogeneous and deformable forms can open up opportunities in extracellular biomaterial or bioelectric systems.« less

Heterogeneous silicon mesostructures for lipid-supported bioelectric interfaces

PubMed Central

Jiang, Yuanwen; Carvalho-de-Souza, João L.; Wong, Raymond C. S.; Luo, Zhiqiang; Isheim, Dieter; Zuo, Xiaobing; Nicholls, Alan W.; Jung, Il Woong; Yue, Jiping; Liu, Di-Jia; Wang, Yucai; De Andrade, Vincent; Xiao, Xianghui; Navrazhnykh, Luizetta; Weiss, Dara E.; Wu, Xiaoyang; Seidman, David N.; Bezanilla, Francisco; Tian, Bozhi

2017-01-01

Silicon-based materials have widespread application as biophysical tools and biomedical devices. Here we introduce a biocompatible and degradable mesostructured form of silicon with multiscale structural and chemical heterogeneities. The material was synthesized using mesoporous silica as a template through a chemical-vapor-deposition process. It has an amorphous atomic structure, an ordered nanowire-based framework, and random submicrometre voids, and shows an average Young’s modulus that is 2–3 orders of magnitude smaller than that of single crystalline silicon. In addition, we used the heterogeneous silicon mesostructures to design a lipid-bilayer-supported bioelectric interface that is remotely controlled and temporally transient, and that permits non-genetic and subcellular optical modulation of the electrophysiology dynamics in single dorsal root ganglia neurons. Our findings suggest that the biomimetic expansion of silicon into heterogeneous and deformable forms can open up opportunities in extracellular biomaterial or bioelectric systems. PMID:27348576

Assessing the potential roles of silicon and germanium phthalocyanines in planar heterojunction organic photovoltaic devices and how pentafluoro phenoxylation can enhance π-π interactions and device performance.

PubMed

Lessard, Benoît H; White, Robin T; Al-Amar, Mohammad; Plint, Trevor; Castrucci, Jeffrey S; Josey, David S; Lu, Zheng-Hong; Bender, Timothy P

2015-03-11

In this study, we have assessed the potential application of dichloro silicon phthalocyanine (Cl2-SiPc) and dichloro germanium phthalocyanine (Cl2-GePc) in modern planar heterojunction organic photovoltaic (PHJ OPV) devices. We have determined that Cl2-SiPc can act as an electron donating material when paired with C60 and that Cl2-SiPc or Cl2-GePc can also act as an electron acceptor material when paired with pentacene. These two materials enabled the harvesting of triplet energy resulting from the singlet fission process in pentacene. However, contributions to the generation of photocurrent were observed for Cl2-SiPc with no evidence of photocurrent contribution from Cl2-GePc. The result of our initial assessment established the potential for the application of SiPc and GePc in PHJ OPV devices. Thereafter, bis(pentafluoro phenoxy) silicon phthalocyanine (F10-SiPc) and bis(pentafluoro phenoxy) germanium phthalocyanine (F10-GePc) were synthesized and characterized. During thermal processing, it was discovered that F10-SiPc and F10-GePc underwent a reaction forming small amounts of difluoro SiPc (F2-SiPc) and difluoro GePc (F2-GePc). This undesirable reaction could be circumvented for F10-SiPc but not for F10-GePc. Using single crystal X-ray diffraction, it was determined that F10-SiPc has significantly enhanced π-π interactions compared with that of Cl2-SiPc, which had little to none. Unoptimized PHJ OPV devices based on F10-SiPc were fabricated and directly compared to those constructed from Cl2-SiPc, and in all cases, PHJ OPV devices based on F10-SiPc had significantly improved device characteristics compared to Cl2-SiPc.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Comparison of Six Different Silicones In Vitro for Application as Glaucoma Drainage Device

PubMed Central

Windhövel, Claudia; Harder, Lisa; Bach, Jan-Peter; Teske, Michael; Grabow, Niels; Eickner, Thomas; Chichkov, Boris; Nolte, Ingo

2018-01-01

Silicones are widely used in medical applications. In ophthalmology, glaucoma drainage devices are utilized if conservative therapies are not applicable or have failed. Long-term success of these devices is limited by failure to control intraocular pressure due to fibrous encapsulation. Therefore, different medical approved silicones were tested in vitro for cell adhesion, cell proliferation and viability of human Sclera (hSF) and human Tenon fibroblasts (hTF). The silicones were analysed also depending on the sample preparation according to the manufacturer’s instructions. The surface quality was characterized with environmental scanning electron microscope (ESEM) and water contact angle measurements. All silicones showed homogeneous smooth and hydrophobic surfaces. Cell adhesion was significantly reduced on all silicones compared to the negative control. Proliferation index and cell viability were not influenced much. For development of a new glaucoma drainage device, the silicones Silbione LSR 4330 and Silbione LSR 4350, in this study, with low cell counts for hTF and low proliferation indices for hSF, and silicone Silastic MDX4-4210, with low cell counts for hSF and low proliferation indices for hTF, have shown the best results in vitro. Due to the high cell adhesion shown on Silicone LSR 40, 40,026, this material is unsuitable. PMID:29495462

Flexible single-crystal silicon nanomembrane photonic crystal cavity.

PubMed

Xu, Xiaochuan; Subbaraman, Harish; Chakravarty, Swapnajit; Hosseini, Amir; Covey, John; Yu, Yalin; Kwong, David; Zhang, Yang; Lai, Wei-Cheng; Zou, Yi; Lu, Nanshu; Chen, Ray T

2014-12-23

Flexible inorganic electronic devices promise numerous applications, especially in fields that could not be covered satisfactorily by conventional rigid devices. Benefits on a similar scale are also foreseeable for silicon photonic components. However, the difficulty in transferring intricate silicon photonic devices has deterred widespread development. In this paper, we demonstrate a flexible single-crystal silicon nanomembrane photonic crystal microcavity through a bonding and substrate removal approach. The transferred cavity shows a quality factor of 2.2×10(4) and could be bent to a curvature of 5 mm radius without deteriorating the performance compared to its counterparts on rigid substrates. A thorough characterization of the device reveals that the resonant wavelength is a linear function of the bending-induced strain. The device also shows a curvature-independent sensitivity to the ambient index variation.

Computer-aided engineering of semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Wavelength dependent vertical integration of nanoplasmonic circuits utilizing coupled ring resonators

NASA Astrophysics Data System (ADS)

Nielsen, M.; Elezzabi, A. Y.

2013-03-01

To become a competitor to replace CMOS-electronics for next-generation data processing, signal routing, and computing, nanoplasmonic circuits will require an analogue to electrical vias in order to enable vertical connections between device layers. Vertically stacked nanoplasmonic nanoring resonators formed of Ag/Si/Ag gap plasmon waveguides were studied as a novel 3-D coupling scheme that could be monolithically integrated on a silicon platform. The vertically coupled ring resonators were evanescently coupled to 100 nm x 100 nm Ag/Si/Ag input and output waveguides and the whole device was submerged in silicon dioxide. 3-D finite difference time domain simulations were used to examine the transmission spectra of the coupling device with varying device sizes and orientations. By having the signal coupling occur over multiple trips around the resonator, coupling efficiencies as high as 39% at telecommunication wavelengths between adjacent layers were present with planar device areas of only 1.00 μm2. As the vertical signal transfer was based on coupled ring resonators, the signal transfer was inherently wavelength dependent. Changing the device size by varying the radii of the nanorings allowed for tailoring the coupled frequency spectra. The plasmonic resonator based coupling scheme was found to have quality (Q) factors of upwards of 30 at telecommunication wavelengths. By allowing different device layers to operate on different wavelengths, this coupling scheme could to lead to parallel processing in stacked independent device layers.

Silicon superlattices: Theory and application to semiconductor devices

NASA Technical Reports Server (NTRS)

Moriarty, J. A.

1981-01-01

Silicon superlattices and their applicability to improved semiconductor devices were studied. The device application potential of the atomic like dimension of III-V semiconductor superlattices fabricated in the form of ultrathin periodically layered heterostructures was examined. Whether this leads to quantum size effects and creates the possibility to alter familiar transport and optical properties over broad physical ranges was studied. Applications to improved semiconductor lasers and electrondevices were achieved. Possible application of silicon sperlattices to faster high speed computing devices was examined. It was found that the silicon lattices show features of smaller fundamental energyband gaps and reduced effective masses. The effects correlate strongly with both the chemical and geometrical nature of the superlattice.

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Fabrication Of SNS Weak Links On SOS Substrates

NASA Technical Reports Server (NTRS)

Hunt, Brian D.

1995-01-01

High-quality superconductor/normal-conductor/superconductor (SNS) devices ("weak links") containing epitaxial films of YBa(2)Cu(3)O(7-x) and SrTiO(3) fabricated on silicon-on-sapphire (SOS) substrates with help of improved multilayer buffer system. Process for fabrication of edge-defined SNS weak links described in "Edge-Geometry SNS Devices Made of Y/Ba/Cu" (NPO-18552).

Materials and processing science: Limits for microelectronics

NASA Astrophysics Data System (ADS)

Rosenberg, R.

1988-09-01

The theme of this talk will be to illustrate examples of technologies that will drive materials and processing sciences to the limit and to describe some of the research being pursued to understand materials interactions which are pervasive to projected structure fabrication. It is to be expected that the future will see a progression to nanostructures where scaling laws will be tested and quantum transport will become more in evidence, to low temperature operation for tighter control and improved performance, to complex vertical profiles where 3D stacking and superlattices will produce denser packing and device flexibility, to faster communication links with optoelectronics, and to compatible packaging technologies. New low temperature processing techniques, such as epitaxy of silicon, PECVD of dielectrics, low temperature high pressure oxidation, silicon-germanium heterostructures, etc., must be combined with shallow metallurgies, new lithographic technologies, maskless patterning, rapid thermal processing (RTP) to produce needed profile control, reduce process incompatibilities and develop new device geometries. Materials interactions are of special consequence for chip substrates and illustrations of work in metal-ceramic and metal-polymer adhesion will be offered.

The parameter influence of ion irradiation on the distribution profile of the defect in silicon films

NASA Astrophysics Data System (ADS)

Shemukhin, A. A.; Balaskshin, Yu. V.; Evseev, A. P.; Chernysh, V. S.

2017-09-01

As silicon is an important element in semiconductor devices, the process of defect formation under ion irradiation in it is studied well enough. Modern electronic components are made on silicon lattices (films) that are 100-300 nm thick (Chernysh et al., 1980; Shemukhin et al., 2012; Ieshkin et al., 2015). However, there are still features to be observed in the process of defect formation in silicon. In our work we investigate the effect of fluence and target temperature on the defect formation in films and bulk silicon samples. To investigate defect formation in the silicon films and bulk silicon samples we present experimental data on Si+ implantation with an energy of 200 keV, fluences range from 5 * 1014 to 5 * 1015 ion/cm2 for a fixed flux 1 μA/cm2 and the substrate temperatures from 150 to 350 K The sample crystallinity was investigated by using the Rutherford backscattering technique (RBS) in channeling and random modes. It is shown that in contrast to bulk silicon for which amorphization is observed at 5 × 1016 ion/cm2, the silicon films on sapphire amorphize at lower critical fluences (1015 ion/cm2). So the amorphization critical fluences depend on the target temperature. In addition it is shown that under similar implantation parameters, the disordering of silicon films under the action of the ion beam is stronger than the bulk silicon.

Low temperature surface passivation of crystalline silicon and its application to interdigitated back contact silicon heterojunction (ibc-shj) solar cell

NASA Astrophysics Data System (ADS)

Shu, Zhan

With the absence of shading loss together with improved quality of surface passivation introduced by low temperature processed amorphous silicon crystalline silicon (a-Si:H/c-Si) heterojunction, the interdigitated back contact silicon heterojunction (IBC-SHJ) solar cell exhibits a potential for higher conversion efficiency and lower cost than a traditional front contact diffused junction solar cell. In such solar cells, the front surface passivation is of great importance to achieve both high open-circuit voltage (Voc) and short-circuit current (Jsc). Therefore, the motivation of this work is to develop a low temperature processed structure for the front surface passivation of IBC-SHJ solar cells, which must have an excellent and stable passivation quality as well as a good anti-reflection property. Four different thin film materials/structures were studied and evaluated for this purpose, namely: amorphous silicon nitride (a-SiNx:H), thick amorphous silicon film (a-Si:H), amorphous silicon/silicon nitride/silicon carbide (a-Si:H/a-SiN x:H/a-SiC:H) stack structure with an ultra-thin a-Si:H layer, and zinc sulfide (ZnS). It was demonstrated that the a-Si:H/a-SiNx:H/a-SiC:H stack surpasses other candidates due to both of its excellent surface passivation quality (SRV<5 cm/s) and lower absorption losses. The low recombination rate at the stack structure passivated c-Si surface is found to be resulted from (i) field effect passivation due to the positive fixed charge (Q fix~1x1011 cm-2 with 5 nm a-Si:H layer) in a-SiNx:H as measured from capacitance-voltage technique, and (ii) reduced defect state density (mid-gap Dit~4x1010 cm-2eV-1) at a-Si:H/c-Si interface provided by a 5 nm thick a-Si:H layer, as characterized by conductance-frequency measurements. Paralleled with the experimental studies, a computer program was developed in this work based on the extended Shockley-Read-Hall (SRH) model of surface recombination. With the help of this program, the experimental injection level dependent SRV curves of the stack passivated c-Si samples were successfully reproduced and the carrier capture cross sections of interface defect states were extracted. Additionally, anti-reflection properties of the stack structure were optimized and optical losses were analyzed. The Voc over 700 mV and Jsc over 38 mA/cm2 were achieved in IBC-SHJ solar cells using the stack structure for front surface passivation. Direct comparison shows that such low temperature deposited stack structure developed in this work achieves comparable device performance to the high temperature processed front surface passivation structure used in other high efficiency IBC solar cells. However, the lower fill factor (FF) of IBC-SHJ solar cell as compared with traditional front a-Si:H/c-Si heterojunction cell (HIT cell) greatly limits the overall performance of these devices. Two-dimensional (2D) simulations were used to comparatively model the HIT and IBC-SHJ solar cells to understand the underlying device physics which controls cell performance. The effects of a wide range of device parameters were investigated in the simulation, and pathways to improve the FF of IBC-SHJ solar cell were suggested.

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

Gettering in multicrystalline silicon: A design-of-experiments approach

NASA Astrophysics Data System (ADS)

Schubert, W. K.

1994-12-01

Design-of-experiment methods were used to study gettering due to phosphorus diffusion and aluminum alloying in four industrial multicrystalline silicon materials: Silicon-Film material from AstroPower, heat-exchanger method (HEM) material from Crystal Systems, edge-defined film-fed growth (EFG) material from Mobil Solar, and cast material from Solarex. Time and temperature for the diffusion and alloy processes were chosen for a four-factor quadratic interaction experiment. Simple diagnostic devices were used to evaluate the gettering. Only EFG and HEM materials exhibited statistically significant gettering effects within the ranges used for the various parameters. Diffusion and alloying temperature were significant for HEM material; also there was a second-order interaction between the diffusion time and temperature. There was no interaction between the diffusion and alloying processes in HEM material. EFG material showed a first-order dependence on diffusion temperature and a second-order interaction between the diffusion temperature and the alloying time. Gettering recommendations for the HEM material were used to produce the best-yet Sandia cells on this material, but correlation with the gettering experiment was not strong. Some of the discrepancy arises from necessary processing differences between the diagnostic devices and regular solar cells. This issue and other lessons learned concerning this type of experiment are discussed.

Fabrication and etching processes of silicon-based PZT thin films

NASA Astrophysics Data System (ADS)

Zhao, Hongjin; Liu, Yanxiang; Liu, Jianshe; Ren, Tian-Ling; Liu, Li-Tian; Li, Zhijian

2001-09-01

Lead-zirconate-titanate (PZT) thin films on silicon were prepared by a sol-gel method. Phase characterization and crystal orientation of the films were investigated by x-ray diffraction analysis (XRD). It was shown that the PZT thin films had a perfect perovskite structure after annealed at a low temperature of 600 degrees C. PZT thin films were chemically etched using HCl/HF solution through typical semiconductor lithographic process, and the etching condition was optimized. The scanning electron microscopy results indicated that the PZT thin film etching problem was well solved for the applications of PZT thin film devices.

Amorphous silicon photovoltaic devices

DOEpatents

Carlson, David E.; Lin, Guang H.; Ganguly, Gautam

2004-08-31

This invention is a photovoltaic device comprising an intrinsic or i-layer of amorphous silicon and where the photovoltaic device is more efficient at converting light energy to electric energy at high operating temperatures than at low operating temperatures. The photovoltaic devices of this invention are suitable for use in high temperature operating environments.

Demonstration of free space coherent optical communication using integrated silicon photonic orbital angular momentum devices.

PubMed

Su, Tiehui; Scott, Ryan P; Djordjevic, Stevan S; Fontaine, Nicolas K; Geisler, David J; Cai, Xinran; Yoo, S J B

2012-04-23

We propose and demonstrate silicon photonic integrated circuits (PICs) for free-space spatial-division-multiplexing (SDM) optical transmission with multiplexed orbital angular momentum (OAM) states over a topological charge range of -2 to +2. The silicon PIC fabricated using a CMOS-compatible process exploits tunable-phase arrayed waveguides with vertical grating couplers to achieve space division multiplexing and demultiplexing. The experimental results utilizing two silicon PICs achieve SDM mux/demux bit-error-rate performance for 1‑b/s/Hz, 10-Gb/s binary phase shifted keying (BPSK) data and 2-b/s/Hz, 20-Gb/s quadrature phase shifted keying (QPSK) data for individual and two simultaneous OAM states. © 2012 Optical Society of America

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Topics investigated include: measurements of transistor delay time; application of the infrared response technique to the study of radiation-damaged, lithium-drifted silicon detectors; and identification of a condition that minimizes wire flexure and reduces the failure rate of wire bonds in transistors and integrated circuits under slow thermal cycling conditions. Supplementary data concerning staff, standards committee activities, technical services, and publications are included as appendixes.

Tunable MOEMS Fabry-Perot interferometer for miniaturized spectral sensing in near-infrared

NASA Astrophysics Data System (ADS)

Rissanen, A.; Mannila, R.; Tuohiniemi, M.; Akujärvi, A.; Antila, J.

2014-03-01

This paper presents a novel MOEMS Fabry-Perot interferometer (FPI) process platform for the range of 800 - 1050 nm. Simulation results including design and optimization of device properties in terms of transmission peak width, tuning range and electrical properties are discussed. Process flow for the device fabrication is presented, with overall process integration and backend dicing steps resulting in successful fabrication yield. The mirrors of the FPI consist of LPCVD (low-pressure chemical vapor) deposited polySi-SiN λ/4-thin film Bragg reflectors, with the air gap formed by sacrificial SiO2 etching in HF vapor. Silicon substrate below the optical aperture is removed by inductively coupled plasma (ICP) etching to ensure transmission in the visible - near infra-red (NIR), which is below silicon transmission range. The characterized optical properties of the chips are compared to the simulated values. Achieved optical aperture diameter size enables utilization of the chips in both imaging as well as single-point spectral sensors.

Aluminum for bonding Si-Ge alloys to graphite

DOEpatents

Eggemann, Robert V.

1976-01-13

Improved thermoelectric device and process, comprising the high-temperature, vacuum bonding of a graphite contact and silicon-germanium thermoelectric element by the use of a low void, aluminum, metallurgical shim with low electrical resistance sandwiched therebetween.

Self-aligned process for forming microlenses at the tips of vertical silicon nanowires by atomic layer deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dan, Yaping, E-mail: yaping.dan@sjtu.edu.cn; Chen, Kaixiang; Crozier, Kenneth B.

The microlens is a key enabling technology in optoelectronics, permitting light to be efficiently coupled to and from devices such as image sensors and light-emitting diodes. Their ubiquitous nature motivates the development of new fabrication techniques, since existing methods face challenges as microlenses are scaled to smaller dimensions. Here, the authors demonstrate the formation of microlenses at the tips of vertically oriented silicon nanowires via a rapid atomic layer deposition process. The nature of the process is such that the microlenses are centered on the nanowires, and there is a self-limiting effect on the final sizes of the microlenses arisingmore » from the nanowire spacing. Finite difference time domain electromagnetic simulations are performed of microlens focusing properties, including showing their ability to enhance visible-wavelength absorption in silicon nanowires.« less

Investigation of high-speed Si photodetectors in standard CMOS technology

NASA Astrophysics Data System (ADS)

Wang, Huaqiang; Guo, Xia

2018-05-01

In this paper, the frequency response characteristics of the photodetector(PD) were studied considering intrinsic and extrinsic effects. Then we designed the interdigitated p-i-n PD on Silicon-on-Insulator (SOI) and epitaxial (EPI) substrates with photosensitive area of 30-μm diameter, fabricated by CMOS process. The 2-μm finger-spacing devices exhibited a 205 MHz bandwidth at a reverse bias of 3 V processed on 2-μm SOI substrates. EPI devices with 1 μm finger spacing exhibited a 131 MHz bandwidth under -3 V. Responsivity of 0.051 A/W and 0.21 A/W were measured at 850 nm on SOI and EPI substrates, respectively. Compared with the bulk silicon PD, the bandwidth is greatly improved. The PD gains the high cost performance ratio, which can be widely used in short distance communication such as visible light communication and free space optical communication.

Ultrasonic monitoring of the setting of silicone elastomeric impression materials.

PubMed

Kanazawa, Tomoe; Murayama, Ryosuke; Furuichi, Tetsuya; Imai, Arisa; Suda, Shunichi; Kurokawa, Hiroyasu; Takamizawa, Toshiki; Miyazaki, Masashi

2017-01-31

This study used an ultrasonic measurement device to monitor the setting behavior of silicone elastomeric impression materials, and the influence of temperature on setting behavior was determined. The ultrasonic device consisted of a pulser-receiver, transducers, and an oscilloscope. The two-way transit time through the mixing material was divided by two to account for the down-and-back travel path; then it was multiplied by the sonic velocity. Analysis of variance and the Tukey honest significant difference test were used. In the early stages of the setting process, most of the ultrasonic energy was absorbed by the elastomers and the second echoes were relatively weak. As the elastomers hardened, the sonic velocities increased until they plateaued. The changes in sonic velocities varied among the elastomers tested, and were affected by temperature conditions. The ultrasonic method used in this study has considerable potential for determining the setting processes of elastomeric impression materials.

Investigation of the influence of the proximity effect and randomness on a photolithographically fabricated photonic crystal nanobeam cavity

NASA Astrophysics Data System (ADS)

Tetsumoto, Tomohiro; Kumazaki, Hajime; Ishida, Rammaru; Tanabe, Takasumi

2018-01-01

Recent progress on the fabrication techniques used in silicon photonics foundries has enabled us to fabricate photonic crystal (PhC) nanocavities using a complementary metal-oxide-semiconductor (CMOS) compatible process. A high Q two-dimensional PhC nanocavity and a one-dimensional nanobeam PhC cavity with a Q exceeding 100 thousand have been fabricated using ArF excimer laser immersion lithography. These are important steps toward the fusion of silicon photonics devices and PhC devices. Although the fabrication must be reproducible for industrial applications, the properties of PhC nanocavities are sensitively affected by the proximity effect and randomness. In this study, we quantitatively investigated the influence of the proximity effect and randomness on a silicon nanobeam PhC cavity. First, we discussed the optical properties of cavities defined with one- and two-step exposure methods, which revealed the necessity of a multi-stage exposure process for our structure. Then, we investigated the impact of block structures placed next to the cavities. The presence of the blocks modified the resonant wavelength of the cavities by about 10 nm. The highest Q we obtained was over 100 thousand. We also discussed the influence of photomask misalignment, which is also a possible cause of disorders in the photolithographic fabrication process. This study will provide useful information for fabricating integrated photonic circuits with PhC nanocavities using a photolithographic process.

Epitaxial growth of silicon for layer transfer

DOEpatents

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Nondestructive imaging of atomically thin nanostructures buried in silicon

PubMed Central

Gramse, Georg; Kölker, Alexander; Lim, Tingbin; Stock, Taylor J. Z.; Solanki, Hari; Schofield, Steven R.; Brinciotti, Enrico; Aeppli, Gabriel; Kienberger, Ferry; Curson, Neil J.

2017-01-01

It is now possible to create atomically thin regions of dopant atoms in silicon patterned with lateral dimensions ranging from the atomic scale (angstroms) to micrometers. These structures are building blocks of quantum devices for physics research and they are likely also to serve as key components of devices for next-generation classical and quantum information processing. Until now, the characteristics of buried dopant nanostructures could only be inferred from destructive techniques and/or the performance of the final electronic device; this severely limits engineering and manufacture of real-world devices based on atomic-scale lithography. Here, we use scanning microwave microscopy (SMM) to image and electronically characterize three-dimensional phosphorus nanostructures fabricated via scanning tunneling microscope–based lithography. The SMM measurements, which are completely nondestructive and sensitive to as few as 1900 to 4200 densely packed P atoms 4 to 15 nm below a silicon surface, yield electrical and geometric properties in agreement with those obtained from electrical transport and secondary ion mass spectroscopy for unpatterned phosphorus δ layers containing ~1013 P atoms. The imaging resolution was 37 ± 1 nm in lateral and 4 ± 1 nm in vertical directions, both values depending on SMM tip size and depth of dopant layers. In addition, finite element modeling indicates that resolution can be substantially improved using further optimized tips and microwave gradient detection. Our results on three-dimensional dopant structures reveal reduced carrier mobility for shallow dopant layers and suggest that SMM could aid the development of fabrication processes for surface code quantum computers. PMID:28782006

Pre-strain effect on frequency-based impact energy dissipation through a silicone foam pad for shock mitigation [Pre-strain effect on the frequency response of shock mitigation through a silicone foam pad

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanborn, Brett; Song, Bo; Smith, Scott

Silicone foams have been used in a variety of applications from gaskets to cushioning pads over a wide range of environments. Particularly, silicone foams are used as a shock mitigation material for shock and vibration applications. Understanding the shock mitigation response, particularly in the frequency domain, is critical for optimal designs to protect internal devices and components more effectively and efficiently. The silicone foams may be subjected to pre-strains during the assembly process which may consequently influence the frequency response with respect to shock mitigation performance. A Kolsky compression bar was modified with pre-compression capabilities to characterize the shock mitigationmore » response of silicone foam in the frequency domain to determine the effect of pre-strain. Lastly, a silicone sample was also intentionally subjected to repeated pre-strain and dynamic loadings to explore the effect of repeated loading on the frequency response of shock mitigation.« less

Pre-strain effect on frequency-based impact energy dissipation through a silicone foam pad for shock mitigation [Pre-strain effect on the frequency response of shock mitigation through a silicone foam pad

DOE PAGES

Sanborn, Brett; Song, Bo; Smith, Scott

2015-12-29

Silicone foams have been used in a variety of applications from gaskets to cushioning pads over a wide range of environments. Particularly, silicone foams are used as a shock mitigation material for shock and vibration applications. Understanding the shock mitigation response, particularly in the frequency domain, is critical for optimal designs to protect internal devices and components more effectively and efficiently. The silicone foams may be subjected to pre-strains during the assembly process which may consequently influence the frequency response with respect to shock mitigation performance. A Kolsky compression bar was modified with pre-compression capabilities to characterize the shock mitigationmore » response of silicone foam in the frequency domain to determine the effect of pre-strain. Lastly, a silicone sample was also intentionally subjected to repeated pre-strain and dynamic loadings to explore the effect of repeated loading on the frequency response of shock mitigation.« less

Microsystem strategies for sample preparation in biological detection.

DOE Office of Scientific and Technical Information (OSTI.GOV)

James, Conrad D.; Galambos, Paul C.; Bennett, Dawn Jonita

2005-03-01

The objective of this LDRD was to develop microdevice strategies for dealing with samples to be examined in biological detection systems. This includes three sub-components: namely, microdevice fabrication, sample delivery to the microdevice, and sample processing within the microdevice. The first component of this work focused on utilizing Sandia's surface micromachining technology to fabricate small volume (nanoliter) fluidic systems for processing small quantities of biological samples. The next component was to develop interfaces for the surface-micromachined silicon devices. We partnered with Micronics, a commercial company, to produce fluidic manifolds for sample delivery to our silicon devices. Pressure testing was completedmore » to examine the strength of the bond between the pressure-sensitive adhesive layer and the silicon chip. We are also pursuing several other methods, both in house and external, to develop polymer-based fluidic manifolds for packaging silicon-based microfluidic devices. The second component, sample processing, is divided into two sub-tasks: cell collection and cell lysis. Cell collection was achieved using dielectrophoresis, which employs AC fields to collect cells at energized microelectrodes, while rejecting non-cellular particles. Both live and dead Staph. aureus bacteria have been collected using RF frequency dielectrophoresis. Bacteria have been separated from polystyrene microspheres using frequency-shifting dielectrophoresis. Computational modeling was performed to optimize device separation performance, and to predict particle response to the dielectrophoretic traps. Cell lysis is continuing to be pursued using microactuators to mechanically disrupt cell membranes. Novel thermal actuators, which can generate larger forces than previously tested electrostatic actuators, have been incorporated with and tested with cell lysis devices. Significant cell membrane distortion has been observed, but more experiments need to be conducted to determine the effects of the observed distortion on membrane integrity and cell viability. Finally, we are using a commercial PCR DNA amplification system to determine the limits of detectable sample size, and to examine the amplification of DNA bound to microspheres. Our objective is to use microspheres as capture-and-carry chaperones for small molecules such as DNA and proteins, enabling the capture and concentration of the small molecules using dielectrophoresis. Current tests demonstrated amplification of DNA bound to micron-sized polystyrene microspheres using 20-50 microliter volume size reactions.« less

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Metal organic chemical vapor deposition of 111-v compounds on silicon

DOEpatents

Vernon, Stanley M.

1986-01-01

Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.

Basic Mechanisms of Radiation Effects on Electronic Materials, Devices, and Integrated Circuits

DTIC Science & Technology

1982-08-01

recovery time versus reciprocal tempera- ture derived from data of the type shown in Figure 18. . . .31 20 Several ways to alter the charje state of...and long-term recovery processes that occUr in neutron-irradiated silicon ........ 40 29 Annealing factor versus time for 11 ohm-cm p-type bulk silicon...radioactive ele- ments (such as uranium and thorium) which, when incorporated in packaged integrated circuits, can cause occasional transient upsets

GaN-on-Silicon - Present capabilities and future directions

NASA Astrophysics Data System (ADS)

Boles, Timothy

2018-02-01

Gallium Nitride, in the form of epitaxial HEMT transistors on various substrate materials, is the newest and most promising semiconductor technology for high performance devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-Silicon based devices and MMIC's which enable both state-of-the-art high frequency functionality and the ability to scale production into large wafer diameter CMOS foundries. The design and development of GaN-on-Silicon structures and devices will be presented beginning with the basic material parameters, growth of the required epitaxial construction, and leading to the fundamental operational theory of high frequency, high power HEMTs. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including inherent frequency limiting transit time analysis, required impedance transformations, internal and external parasitic reactance, thermal impedance optimization, and challenges improved by full integration into monolithic MMICs. Lastly, future directions for implementing GaN-on-Silicon into mainstream CMOS silicon semiconductor technologies will be discussed.

Gas-phase synthesis of semiconductor nanocrystals and its applications

NASA Astrophysics Data System (ADS)

Mandal, Rajib

Luminescent nanomaterials is a newly emerging field that provides challenges not only to fundamental research but also to innovative technology in several areas such as electronics, photonics, nanotechnology, display, lighting, biomedical engineering and environmental control. These nanomaterials come in various forms, shapes and comprises of semiconductors, metals, oxides, and inorganic and organic polymers. Most importantly, these luminescent nanomaterials can have different properties owing to their size as compared to their bulk counterparts. Here we describe the use of plasmas in synthesis, modification, and deposition of semiconductor nanomaterials for luminescence applications. Nanocrystalline silicon is widely known as an efficient and tunable optical emitter and is attracting great interest for applications in several areas. To date, however, luminescent silicon nanocrystals (NCs) have been used exclusively in traditional rigid devices. For the field to advance towards new and versatile applications for nanocrystal-based devices, there is a need to investigate whether these NCs can be used in flexible and stretchable devices. We show how the optical and structural/morphological properties of plasma-synthesized silicon nanocrystals (Si NCs) change when they are deposited on stretchable substrates made of polydimethylsiloxane (PDMS). Synthesis of these NCs was performed in a nonthermal, low-pressure gas phase plasma reactor. To our knowledge, this is the first demonstration of direct deposition of NCs onto stretchable substrates. Additionally, in order to prevent oxidation and enhance the luminescence properties, a silicon nitride shell was grown around Si NCs. We have demonstrated surface nitridation of Si NCs in a single step process using non?thermal plasma in several schemes including a novel dual-plasma synthesis/shell growth process. These coated NCs exhibit SiNx shells with composition depending on process parameters. While measurements including photoluminescence (PL), surface analysis, and defect identification indicate the shell is protective against oxidation compared to Si NCs without any shell growth. Gallium Nitride (GaN) is one of the most well-known semiconductor material and the industry standard for fabricating LEDs. The problem is that epitaxial growth of high-quality GaN requires costly substrates (e.g. sapphire), high temperatures, and long processing times. Synthesizing freestanding NCs of GaN, on the other hand, could enable these novel device morphologies, as the NCs could be incorporated into devices without the requirements imposed by epitaxial GaN growth. Synthesis of GaN NCs was performed using a fully gas-phase process. Different sizes of crystalline GaN nanoparticles were produced indicating versatility of this gas-phase process. Elemental analysis using X-ray photoelectron spectroscopy (XPS) indicated a possible nitrogen deficiency in the NCs; addition of secondary plasma for surface treatment indicates improving stoichiometric ratio and points towards a unique method for creating high-quality GaN NCs with ultimate alloying and doping for full-spectrum luminescence.

Improved efficiency of hybrid organic photovoltaics by pulsed laser sintering of silver nanowire network transparent electrode.

PubMed

Spechler, Joshua A; Nagamatsu, Ken A; Sturm, James C; Arnold, Craig B

2015-05-20

In this Research Article, we demonstrate pulsed laser processing of a silver nanowire network transparent conductor on top of an otherwise complete solar cell. The macroscopic pulsed laser irradiation serves to sinter nanowire-nanowire junctions on the nanoscale, leading to a much more conductive electrode. We fabricate hybrid silicon/organic heterojunction photovoltaic devices, which have ITO-free, solution processed, and laser processed transparent electrodes. Furthermore, devices which have high resistive losses show up to a 35% increase in power conversion efficiency after laser processing. We perform this study over a range of laser fluences, and a range of nanowire area coverage to investigate the sintering mechanism of nanowires inside of a device stack. The increase in device performance is modeled using a simple photovoltaic diode approach and compares favorably to the experimental data.

Development of high temperature, high radiation resistant silicon semiconductors

NASA Technical Reports Server (NTRS)

Whorl, C. A.; Evans, A. W.

1972-01-01

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Modeling and fabrication of 4H-SiC Schottky junction

NASA Astrophysics Data System (ADS)

Martychowiec, A.; Pedryc, A.; Kociubiński, A.

2017-08-01

The rapidly growing demand for electronic devices requires using of alternative semiconductor materials, which could replace conventional silicon. Silicon carbide has been proposed for these harsh environment applications (high temperature, high voltage, high power conditions) because of its wide bandgap, its high temperature operation ability, its excellent thermal and chemical stability, and its high breakdown electric field strength. The Schottky barrier diode (SBD) is known as one of the best refined SiC devices. This paper presents prepared model, simulations and description of technology of 4H-SiC Schottky junction as well as characterization of fabricated structures. The future aim of the application of the structures is an optical detection of an ultraviolet radiation. The model section contains a comparison of two different solutions of SBD's construction. Simulations - as a crucial process of designing electronic devices - have been performed using the ATLAS device of Silvaco TCAD software. As a final result the paper shows I-V characteristics of fabricated diodes.

ESD robustness improving for the low-voltage triggering silicon-controlled rectifier by adding NWell at cathode

NASA Astrophysics Data System (ADS)

Jin, Xiangliang; Zheng, Yifei; Wang, Yang; Guan, Jian; Hao, Shanwan; Li, Kan; Luo, Jun

2018-01-01

The low-voltage triggering silicon-controlled rectifier (LVTSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its low trigger voltage and strong current-tolerating capability per area. In this paper, an improved LVTSCR by adding a narrow NWell (NW2) under the source region of NMOS is discussed, which is realized in a 0.5-μm CMOS process. A 2-dimension (2D) device simulation platform and a transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the preliminary LVTSCR, the improved LVTSCR elevates the second breakdown current (It2) from 2.39 A to 5.54 A and increases the holding voltage (Vh) from 3.04 V to 4.09 V without expanding device area or sacrificing any ESD performances. Furthermore, the influence of the size of the narrow NWell under the source region of NMOS on holding voltage is also discussed.

HgCdTe 256x256 NWIR FPA

NASA Technical Reports Server (NTRS)

Vural, Kadri; Blessinger, Michael; Chen, Jenkon; Kleinhans, William

1989-01-01

Researchers developed a HgCdTe 256x256 focal plane array (FPA) which operates in the 1 to 5 micron band. This is presently the largest demonstrated HgCdTe FPA. The detector material is HgCdTe on sapphire (PACE-1 technology) which has a low thermal expansion mismatch with silicon. The multiplexer is a CMOS FET-switch device processed through a commercial silicon foundry. The multiplexer input is direct injection and the charge capacity is about 2 times 10 to the 7th power electrons. The kTC limited read noise is 400 electrons. Researchers demonstrated high background imaging using the device. The broadband quantum efficiency is measured to be 59 percent. Dark currents less than 0.1 pA were measured at 77 K for detectors processed on PACE-1 material with 4.9 microns cutoff. The dark currents decrease as the temperature is lowered, and researchers are presently studying the T less than 77 K characteristics. The interconnect yield is greater than 95 percent. The devices are available for astronomical applications.

Neutron radiation tolerance of Au-activated silicon

NASA Technical Reports Server (NTRS)

Joyner, W. T.

1987-01-01

Double injection devices prepared by the introduction of deep traps, using the Au activation method have been found to tolerate gamma irradiation into the Gigarad (Si) region without significant degradation of operating characteristics. Silicon double injection devices, using deep levels creacted by Au diffusion, can tolerate fast neutron irradiation up to 10 to the 15th n/sq cm. Significant parameter degradation occurs at 10 to the 16th n/sq cm. However, since the actual doping of the basic material begins to change as a result of the transmutation of silicon into phosphorus for neutron fluences greater than 10 to the 17th/sq cm, the radiation tolerance of these devices is approaching the limit possible for any device based on initially doped silicon.

Structural Color Filters Enabled by a Dielectric Metasurface Incorporating Hydrogenated Amorphous Silicon Nanodisks.

PubMed

Park, Chul-Soon; Shrestha, Vivek Raj; Yue, Wenjing; Gao, Song; Lee, Sang-Shin; Kim, Eun-Soo; Choi, Duk-Yong

2017-05-31

It is advantageous to construct a dielectric metasurface in silicon due to its compatibility with cost-effective, mature processes for complementary metal-oxide-semiconductor devices. However, high-quality crystalline-silicon films are difficult to grow on foreign substrates. In this work, we propose and realize highly efficient structural color filters based on a dielectric metasurface exploiting hydrogenated amorphous silicon (a-Si:H), known to be lossy in the visible regime. The metasurface is comprised of an array of a-Si:H nanodisks embedded in a polymer, providing a homogeneously planarized surface that is crucial for practical applications. The a-Si:H nanodisk element is deemed to individually support an electric dipole (ED) and magnetic dipole (MD) resonance via Mie scattering, thereby leading to wavelength-dependent filtering characteristics. The ED and MD can be precisely identified by observing the resonant field profiles with the assistance of finite-difference time-domain simulations. The completed color filters provide a high transmission of around 90% in the off-resonance band longer than their resonant wavelengths, exhibiting vivid subtractive colors. A wide range of colors can be facilitated by tuning the resonance by adjusting the structural parameters like the period and diameter of the a-Si:H nanodisk. The proposed devices will be actively utilized to implement color displays, imaging devices, and photorealistic color printing.

Hybrid quantum and molecular mechanics embedded cluster models for chemistry on silicon and silicon carbide surfaces

NASA Astrophysics Data System (ADS)

Shoemaker, James Richard

Fabrication of silicon carbide (SiC) semiconductor devices are of interest for aerospace applications because of their high-temperature tolerance. Growth of an insulating SiO2 layer on SiC by oxidation is a poorly understood process, and sometimes produces interface defects that degrade device performance. Accurate theoretical models of surface chemistry, using quantum mechanics (QM), do not exist because of the huge computational cost of solving Schrodinger's equation for a molecular cluster large enough to represent a surface. Molecular mechanics (MM), which describes a molecule as a collection of atoms interacting through classical potentials, is a fast computational method, good at predicting molecular structure, but cannot accurately model chemical reactions. A new hybrid QM/MM computational method for surface chemistry was developed and applied to silicon and SiC surfaces. The addition of MM steric constraints was shown to have a large effect on the energetics of O atom adsorption on SiC. Adsorption of O atoms on Si-terminated SiC(111) favors above surface sites, in contrast to Si(111), but favors subsurface adsorption sites on C- terminated SiC(111). This difference, and the energetics of C atom etching via CO2 desorption, can explain the observed poor performance of SiC devices in which insulating layers were grown on C-terminated surfaces.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Sinusoidal nanotextures for light management in silicon thin-film solar cells.

PubMed

Köppel, G; Rech, B; Becker, C

2016-04-28

Recent progresses in liquid phase crystallization enabled the fabrication of thin wafer quality crystalline silicon layers on low-cost glass substrates enabling conversion efficiencies up to 12.1%. Because of its indirect band gap, a thin silicon absorber layer demands for efficient measures for light management. However, the combination of high quality crystalline silicon and light trapping structures is still a critical issue. Here, we implement hexagonal 750 nm pitched sinusoidal and pillar shaped nanostructures at the sun-facing glass-silicon interface into 10 μm thin liquid phase crystallized silicon thin-film solar cell devices on glass. Both structures are experimentally studied regarding their optical and optoelectronic properties. Reflection losses are reduced over the entire wavelength range outperforming state of the art anti-reflective planar layer systems. In case of the smooth sinusoidal nanostructures these optical achievements are accompanied by an excellent electronic material quality of the silicon absorber layer enabling open circuit voltages above 600 mV and solar cell device performances comparable to the planar reference device. For wavelengths smaller than 400 nm and higher than 700 nm optical achievements are translated into an enhanced quantum efficiency of the solar cell devices. Therefore, sinusoidal nanotextures are a well-balanced compromise between optical enhancement and maintained high electronic silicon material quality which opens a promising route for future optimizations in solar cell designs for silicon thin-film solar cells on glass.

Phase sensitive amplification in integrated waveguides (Conference Presentation)

NASA Astrophysics Data System (ADS)

Schroeder, Jochen B.; Zhang, Youngbin; Husko, Chad A.; LeFrancois, Simon; Eggleton, Benjamin J.

2017-02-01

Phase sensitive amplification (PSA) is an attractive technology for integrated all-optical signal processing, due to it's potential for noiseless amplification, phase regeneration and generation of squeezed light. In this talk I will review our results on implementing four-wave-mixing based PSA inside integrated photonic devices. In particular I will discuss PSA in chalcogenide ridge waveguides and silicon slow-light photonic crystals. We achieve PSA in both pump- and signal-degenerate schemes with maximum extinction ratios of 11 (silicon) and 18 (chalcogenide) dB. I will further discuss the influence of two-photon absorption and free carrier effects on the performance of silicon-based PSAs.

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

NASA Astrophysics Data System (ADS)

Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

2018-02-01

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

Temperature measuring device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lauf, R.J.; Bible, D.W.; Sohns, C.W.

1999-10-19

Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

Temperature measuring device

DOEpatents

Lauf, Robert J.; Bible, Don W.; Sohns, Carl W.

1999-01-01

Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

NASA Technical Reports Server (NTRS)

Speer, Kevin M.

2004-01-01

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Ion beam figuring of silicon aspheres

NASA Astrophysics Data System (ADS)

Demmler, Marcel; Zeuner, Michael; Luca, Alfonz; Dunger, Thoralf; Rost, Dirk; Kiontke, Sven; Krüger, Marcus

2011-03-01

Silicon lenses are widely used for infrared applications. Especially for portable devices the size and weight of the optical system are very important factors. The use of aspherical silicon lenses instead of spherical silicon lenses results in a significant reduction of weight and size. The manufacture of silicon lenses is more challenging than the manufacture of standard glass lenses. Typically conventional methods like diamond turning, grinding and polishing are used. However, due to the high hardness of silicon, diamond turning is very difficult and requires a lot of experience. To achieve surfaces of a high quality a polishing step is mandatory within the manufacturing process. Nevertheless, the required surface form accuracy cannot be achieved through the use of conventional polishing methods because of the unpredictable behavior of the polishing tools, which leads to an unstable removal rate. To overcome these disadvantages a method called Ion Beam Figuring can be used to manufacture silicon lenses with high surface form accuracies. The general advantage of the Ion Beam Figuring technology is a contactless polishing process without any aging effects of the tool. Due to this an excellent stability of the removal rate without any mechanical surface damage is achieved. The related physical process - called sputtering - can be applied to any material and is therefore also applicable to materials of high hardness like Silicon (SiC, WC). The process is realized through the commercially available ion beam figuring system IonScan 3D. During the process, the substrate is moved in front of a focused broad ion beam. The local milling rate is controlled via a modulated velocity profile, which is calculated specifically for each surface topology in order to mill the material at the associated positions to the target geometry. The authors will present aspherical silicon lenses with very high surface form accuracies compared to conventionally manufactured lenses.

Silicon detectors for combined MR-PET and MR-SPECT imaging

NASA Astrophysics Data System (ADS)

Studen, A.; Brzezinski, K.; Chesi, E.; Cindro, V.; Clinthorne, N. H.; Cochran, E.; Grošičar, B.; Grkovski, M.; Honscheid, K.; Kagan, H.; Lacasta, C.; Llosa, G.; Mikuž, M.; Stankova, V.; Weilhammer, P.; Žontar, D.

2013-02-01

Silicon based devices can extend PET-MR and SPECT-MR imaging to applications, where their advantages in performance outweigh benefits of high statistical counts. Silicon is in many ways an excellent detector material with numerous advantages, among others: excellent energy and spatial resolution, mature processing technology, large signal to noise ratio, relatively low price, availability, versatility and malleability. The signal in silicon is also immune to effects of magnetic field at the level normally used in MR devices. Tests in fields up to 7 T were performed in a study to determine effects of magnetic field on positron range in a silicon PET device. The curvature of positron tracks in direction perpendicular to the field's orientation shortens the distance between emission and annihilation point of the positron. The effect can be fully appreciated for a rotation of the sample for a fixed field direction, compressing range in all dimensions. A popular Ga-68 source was used showing a factor of 2 improvement in image noise compared to zero field operation. There was also a little increase in noise as the reconstructed resolution varied between 2.5 and 1.5 mm. A speculative applications can be recognized in both emission modalities, SPECT and PET. Compton camera is a subspecies of SPECT, where a silicon based scatter as a MR compatible part could inserted into the MR bore and the secondary detector could operate in less constrained environment away from the magnet. Introducing a Compton camera also relaxes requirements of the radiotracers used, extending the range of conceivable photon energies beyond 140.5 keV of the Tc-99m. In PET, one could exploit the compressed sub-millimeter range of positrons in the magnetic field. To exploit the advantage, detectors with spatial resolution commensurate to the effect must be used with silicon being an excellent candidate. Measurements performed outside of the MR achieving spatial resolution below 1 mm are reported.

Design and development of SiGe based near-infrared photodetectors

NASA Astrophysics Data System (ADS)

Zeller, John W.; Puri, Yash R.; Sood, Ashok K.; McMahon, Shane; Efsthadiatis, Harry; Haldar, Pradeep; Dhar, Nibir K.

2014-10-01

Near-infrared (NIR) sensors operating at room temperatures are critical for a variety of commercial and military applications including detecting mortar fire and muzzle flashes. SiGe technology offers a low-cost alternative to conventional IR sensor technologies such as InGaAs, InSb, and HgCdTe for developing NIR micro-sensors that will not require any cooling and can operate with high bandwidths and comparatively low dark currents. Since Ge has a larger thermal expansion coefficient than Si, tensile strain may be incorporated into detector devices during the growth process, enabling an extended operating wavelength range above 1600 nm. SiGe based pin photodetectors have advantages of high stability, low noise, and high responsivity compared to metal-semiconductor-metal (MSM) devices. We have developed a process flow and are fabricating SiGe detector devices on 12" (300 mm) silicon wafers in order to take advantage of high throughput, large-area leading-edge silicon based CMOS technology that provides small feature sizes with associated device cost/density scaling advantages. The fabrication of the detector devices is facilitated by a two-step growth process incorporating initial low temperature growth of Ge/SiGe to form a thin strain-relaxed layer, followed by high temperature growth to deposit a thicker absorbing film, and subsequent high temperature anneal. This growth process is designed to effectively reduce dark current and enhance detector performance by reducing the number of defects and threading dislocations which form recombination centers during the growth process. Various characterization techniques have been employed to determine the properties of the epitaxially deposited Ge/SiGe layers, and the corresponding results are discussed.

Laser processing for strengthening of the self-restoring metal-elastomer interface on a silicone sheet

NASA Astrophysics Data System (ADS)

Yasuda, Kiyokazu

2012-08-01

A self-restoring microsystem is a unique concept which realizes the sensing functionality and robust interface which mechanically and electrically connects a deformable object such as a human body with printed electronic devices. For this purpose, the formation of conductive wiring on an elastomer substrate was attempted using the nickel ink printing process. Before the wiring process, surface patterning of a silicone sheet by a galvano-scanned infrared laser was conducted for the enhancement of interface adhesion of the metal deposit and polymer. Characterization of the fabricated pattern was conducted by optical microscopy. The novel method was successfully demonstrated as a fabrication of selective patterns of metal particles on self-restoring MEMS.

Silicon Carbide Power Devices and Integrated Circuits

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan; Samsel, Isaak; LaBel, Ken; Chen, Yuan; Ikpe, Stanley; Wilcox, Ted; Phan, Anthony; Kim, Hak; Topper, Alyson

2017-01-01

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

Silicon nanowire device and method for its manufacture

DOEpatents

Okandan, Murat; Draper, Bruce L.; Resnick, Paul J.

2017-01-03

There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 .mu.m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation.

Analysis of thin baked-on silicone layers by FTIR and 3D-Laser Scanning Microscopy.

PubMed

Funke, Stefanie; Matilainen, Julia; Nalenz, Heiko; Bechtold-Peters, Karoline; Mahler, Hanns-Christian; Friess, Wolfgang

2015-10-01

Pre-filled syringes (PFS) and auto-injection devices with cartridges are increasingly used for parenteral administration. To assure functionality, silicone oil is applied to the inner surface of the glass barrel. Silicone oil migration into the product can be minimized by applying a thin but sufficient layer of silicone oil emulsion followed by thermal bake-on versus spraying-on silicone oil. Silicone layers thicker than 100nm resulting from regular spray-on siliconization can be characterized using interferometric profilometers. However, the analysis of thin silicone layers generated by bake-on siliconization is more challenging. In this paper, we have evaluated Fourier transform infrared (FTIR) spectroscopy after solvent extraction and a new 3D-Laser Scanning Microscopy (3D-LSM) to overcome this challenge. A multi-step solvent extraction and subsequent FTIR spectroscopy enabled to quantify baked-on silicone levels as low as 21-325μg per 5mL cartridge. 3D-LSM was successfully established to visualize and measure baked-on silicone layers as thin as 10nm. 3D-LSM was additionally used to analyze the silicone oil distribution within cartridges at such low levels. Both methods provided new, highly valuable insights to characterize the siliconization after processing, in order to achieve functionality. Copyright © 2015 Elsevier B.V. All rights reserved.

Micromachined modulator arrays for use in free-space optical communication systems

NASA Astrophysics Data System (ADS)

Lewis, Keith L.; Ridley, Kevin D.; McNie, Mark E.; Smith, Gilbert W.; Scott, Andrew M.

2004-12-01

A summary is presented of some of the design criteria relevant to the realisation of silicon micromachined modulator arrays for use in free-space optical communication systems. Theoretical performance levels achievable are compared with values measured on experimental devices produced using a modified Multi-User MEMS Process (MUMPS). Devices capable of realising modulation rates in excess of 300 kHz are described and their optical characteristics compared with published data on devices based on multiple quantum well technology.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crowder, M.A.; Sposili, R.S.; Cho, H.S.

Nonhydrogenated, n-channel, low-temperature-processed, single-crystal Si thin-film transistors (TFT`s) have been fabricated on Si thin films prepared via sequential lateral solidification (SLS). The device characteristics of the resulting SLS TFT`s exhibit properties and a level of performance that are superior to polycrystalline Si-based TFT`s and are comparable to similar devices fabricated on silicon-on-insulator (SOI) substrates or bulk-Si wafers. The authors attribute these high-performance device characteristics to the absence of high-angle grain-boundaries within the active channel portion of the TFT`s.

Low-voltage, high-extinction-ratio, Mach-Zehnder silicon optical modulator for CMOS-compatible integration.

PubMed

Ding, Jianfeng; Chen, Hongtao; Yang, Lin; Zhang, Lei; Ji, Ruiqiang; Tian, Yonghui; Zhu, Weiwei; Lu, Yangyang; Zhou, Ping; Min, Rui

2012-01-30

We demonstrate a carrier-depletion Mach-Zehnder silicon optical modulator, which is compatible with CMOS fabrication process and works well at a low driving voltage. This is achieved by the optimization of the coplanar waveguide electrode to reduce the electrical signal transmission loss. At the same time, the velocity and impedance matching are both considered. The 12.5 Gbit/s data transmission experiment of the fabricated device with a 2-mm-long phase shifter is performed. The driving voltages with the swing amplitudes of 1 V and 2 V and the reverse bias voltages of 0.5 V and 0.8 V are applied to the device, respectively. The corresponding extinction ratios are 7.67 and 12.79 dB.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

High-performance silicon nanowire bipolar phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Chen, Kaixiang; Crozier, Kenneth B.; Dan, Yaping

2016-07-01

Silicon nanowires (SiNWs) have emerged as sensitive absorbing materials for photodetection at wavelengths ranging from ultraviolet (UV) to the near infrared. Most of the reports on SiNW photodetectors are based on photoconductor, photodiode, or field-effect transistor device structures. These SiNW devices each have their own advantages and trade-offs in optical gain, response time, operating voltage, and dark current noise. Here, we report on the experimental realization of single SiNW bipolar phototransistors on silicon-on-insulator substrates. Our SiNW devices are based on bipolar transistor structures with an optically injected base region and are fabricated using CMOS-compatible processes. The experimentally measured optoelectronic characteristics of the SiNW phototransistors are in good agreement with simulation results. The SiNW phototransistors exhibit significantly enhanced response to UV and visible light, compared with typical Si p-i-n photodiodes. The near infrared responsivities of the SiNW phototransistors are comparable to those of Si avalanche photodiodes but are achieved at much lower operating voltages. Compared with other reported SiNW photodetectors as well as conventional bulk Si photodiodes and phototransistors, the SiNW phototransistors in this work demonstrate the combined advantages of high gain, high photoresponse, low dark current, and low operating voltage.

Method for implementation of back-illuminated CMOS or CCD imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2008-01-01

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Additives to silane for thin film silicon photovoltaic devices

DOEpatents

Hurley, Patrick Timothy; Ridgeway, Robert Gordon; Hutchison, Katherine Anne; Langan, John Giles

2013-09-17

Chemical additives are used to increase the rate of deposition for the amorphous silicon film (.alpha.Si:H) and/or the microcrystalline silicon film (.mu.CSi:H). The electrical current is improved to generate solar grade films as photoconductive films used in the manufacturing of Thin Film based Photovoltaic (TFPV) devices.

Ultra-Sensitive Magnetoresistive Displacement Sensing Device

NASA Technical Reports Server (NTRS)

Olivas, John D. (Inventor); Lairson, Bruce M. (Inventor); Ramesham, Rajeshuni (Inventor)

2003-01-01

An ultrasensitive displacement sensing device for use in accelerometers, pressure gauges, temperature transducers, and the like, comprises a sputter deposited, multilayer, magnetoresistive field sensor with a variable electrical resistance based on an imposed magnetic field. The device detects displacement by sensing changes in the local magnetic field about the magnetoresistive field sensor caused by the displacement of a hard magnetic film on a movable microstructure. The microstructure, which may be a cantilever, membrane, bridge, or other microelement, moves under the influence of an acceleration a known displacement predicted by the configuration and materials selected, and the resulting change in the electrical resistance of the MR sensor can be used to calculate the displacement. Using a micromachining approach, very thin silicon and silicon nitride membranes are fabricated in one preferred embodiment by means of anisotropic etching of silicon wafers. Other approaches include reactive ion etching of silicon on insulator (SOI), or Low Pressure Chemical Vapor Deposition of silicon nitride films over silicon substrates. The device is found to be improved with the use of giant magnetoresistive elements to detect changes in the local magnetic field.

Hybrid indium phosphide-on-silicon nanolaser diode

NASA Astrophysics Data System (ADS)

Crosnier, Guillaume; Sanchez, Dorian; Bouchoule, Sophie; Monnier, Paul; Beaudoin, Gregoire; Sagnes, Isabelle; Raj, Rama; Raineri, Fabrice

2017-04-01

The most-awaited convergence of microelectronics and photonics promises to bring about a revolution for on-chip data communications and processing. Among all the optoelectronic devices to be developed, power-efficient nanolaser diodes able to be integrated densely with silicon photonics and electronics are essential to convert electrical data into the optical domain. Here, we report a demonstration of ultracompact laser diodes based on one-dimensional (1D) photonic crystal (PhC) nanocavities made in InP nanoribs heterogeneously integrated on a silicon-waveguide circuitry. The specific nanorib design enables an efficient electrical injection of carriers in the nanocavity without spoiling its optical properties. Room-temperature continuous-wave (CW) single-mode operation is obtained with a low current threshold of 100 µA. Laser emission at 1.56 µm in the silicon waveguides is obtained with wall-plug efficiencies greater than 10%. This result opens up exciting avenues for constructing optical networks at the submillimetre scale for on-chip interconnects and signal processing.

The effect of dry shear aligning of nanotube thin films on the photovoltaic performance of carbon nanotube-silicon solar cells.

PubMed

Stolz, Benedikt W; Tune, Daniel D; Flavel, Benjamin S

2016-01-01

Recent results in the field of carbon nanotube-silicon solar cells have suggested that the best performance is obtained when the nanotube film provides good coverage of the silicon surface and when the nanotubes in the film are aligned parallel to the surface. The recently developed process of dry shear aligning - in which shear force is applied to the surface of carbon nanotube thin films in the dry state, has been shown to yield nanotube films that are very flat and in which the surface nanotubes are very well aligned in the direction of shear. It is thus reasonable to expect that nanotube films subjected to dry shear aligning should outperform otherwise identical films formed by other processes. In this work, the fabrication and characterisation of carbon nanotube-silicon solar cells using such films is reported, and the photovoltaic performance of devices produced with and without dry shear aligning is compared.

The effect of dry shear aligning of nanotube thin films on the photovoltaic performance of carbon nanotube–silicon solar cells

PubMed Central

Stolz, Benedikt W; Tune, Daniel D

2016-01-01

Summary Recent results in the field of carbon nanotube–silicon solar cells have suggested that the best performance is obtained when the nanotube film provides good coverage of the silicon surface and when the nanotubes in the film are aligned parallel to the surface. The recently developed process of dry shear aligning – in which shear force is applied to the surface of carbon nanotube thin films in the dry state, has been shown to yield nanotube films that are very flat and in which the surface nanotubes are very well aligned in the direction of shear. It is thus reasonable to expect that nanotube films subjected to dry shear aligning should outperform otherwise identical films formed by other processes. In this work, the fabrication and characterisation of carbon nanotube–silicon solar cells using such films is reported, and the photovoltaic performance of devices produced with and without dry shear aligning is compared. PMID:27826524

Transfer of micro and nano-photonic silicon nanomembrane waveguide devices on flexible substrates.

PubMed

Ghaffari, Afshin; Hosseini, Amir; Xu, Xiaochuan; Kwong, David; Subbaraman, Harish; Chen, Ray T

2010-09-13

This paper demonstrates transfer of optical devices without extra un-patterned silicon onto low-cost, flexible plastic substrates using single-crystal silicon nanomembranes. Employing this transfer technique, stacking two layers of silicon nanomembranes with photonic crystal waveguide in the first layer and multi mode interference couplers in the second layer is shown, respectively. This technique is promising to realize high density integration of multilayer hybrid structures on flexible substrates.

Effects of 22 MeV protons on single junction and silicon controlled rectifiers

NASA Technical Reports Server (NTRS)

Beatty, M. E., III

1972-01-01

The effects of 22-MeV protons on various types of silicon single junction and silicon controlled rectifiers were investigated. The results show that low-leakage devices and silicon controlled rectifiers are the most susceptable to radiation damage. There are also differences noted between single junction rectifiers of the same type made by different manufacturers, which emphasizes the need for better selection of devices used in spacecraft.

Periodically poled silicon

NASA Astrophysics Data System (ADS)

Hon, Nick K.; Tsia, Kevin K.; Solli, Daniel R.; Jalali, Bahram

2009-03-01

We propose a new class of photonic devices based on periodic stress fields in silicon that enable second-order nonlinearity as well as quasi-phase matching. Periodically poled silicon (PePSi) adds the periodic poling capability to silicon photonics and allows the excellent crystal quality and advanced manufacturing capabilities of silicon to be harnessed for devices based on second-order nonlinear effects. As an example of the utility of the PePSi technology, we present simulations showing that midwave infrared radiation can be efficiently generated through difference frequency generation from near-infrared with a conversion efficiency of 50%.

Vertical waveguides integrated with silicon photodetectors: Towards high efficiency and low cross-talk image sensors

NASA Astrophysics Data System (ADS)

Tut, Turgut; Dan, Yaping; Duane, Peter; Yu, Young; Wober, Munib; Crozier, Kenneth B.

2012-01-01

We describe the experimental realization of vertical silicon nitride waveguides integrated with silicon photodetectors. The waveguides are embedded in a silicon dioxide layer. Scanning photocurrent microscopy is performed on a device containing a waveguide, and on a device containing the silicon dioxide layer, but without the waveguide. The results confirm the waveguide's ability to guide light onto the photodetector with high efficiency. We anticipate that the use of these structures in image sensors, with one waveguide per pixel, would greatly improve efficiency and significantly reduce inter-pixel crosstalk.

Numerical Simulation and Experiments of Fatigue Crack Growth in Multi-Layer Structures of MEMS and Microelectronic Devices

DTIC Science & Technology

2006-12-01

ABAQUS by use of the UEL subroutine feature. The damage variable was defined on averaged variables per element (Roe and Siegmund, 2003). The location of... thermal expansion (CTE) which is similar to silicon. During the anodic bonding process, the stack of silicon and glass wafers is placed on a hot plate and...Brinckmann, T. Siegmund, "Modeling fatigue crack growth with ABAQUS ," 2005 ABAQUS Fracture Review Team Meeting, Providence, RI, (2005). 8. S

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

DOEpatents

Tour, James M.; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2015-09-08

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the gap region between the first electrical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

DOEpatents

Tour, James M; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2013-11-26

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the the gap region between the first electical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

Energy-Conversion Properties of Vapor-Liquid-Solid-Grown Silicon Wire-Array Photocathodes

NASA Astrophysics Data System (ADS)

Boettcher, Shannon W.; Spurgeon, Joshua M.; Putnam, Morgan C.; Warren, Emily L.; Turner-Evans, Daniel B.; Kelzenberg, Michael D.; Maiolo, James R.; Atwater, Harry A.; Lewis, Nathan S.

2010-01-01

Silicon wire arrays, though attractive materials for use in photovoltaics and as photocathodes for hydrogen generation, have to date exhibited poor performance. Using a copper-catalyzed, vapor-liquid-solid-growth process, SiCl4 and BCl3 were used to grow ordered arrays of crystalline p-type silicon (p-Si) microwires on p+-Si(111) substrates. When these wire arrays were used as photocathodes in contact with an aqueous methyl viologen2+/+ electrolyte, energy-conversion efficiencies of up to 3% were observed for monochromatic 808-nanometer light at fluxes comparable to solar illumination, despite an external quantum yield at short circuit of only 0.2. Internal quantum yields were at least 0.7, demonstrating that the measured photocurrents were limited by light absorption in the wire arrays, which filled only 4% of the incident optical plane in our test devices. The inherent performance of these wires thus conceptually allows the development of efficient photovoltaic and photoelectrochemical energy-conversion devices based on a radial junction platform.

Energy-conversion properties of vapor-liquid-solid-grown silicon wire-array photocathodes.

PubMed

Boettcher, Shannon W; Spurgeon, Joshua M; Putnam, Morgan C; Warren, Emily L; Turner-Evans, Daniel B; Kelzenberg, Michael D; Maiolo, James R; Atwater, Harry A; Lewis, Nathan S

2010-01-08

Silicon wire arrays, though attractive materials for use in photovoltaics and as photocathodes for hydrogen generation, have to date exhibited poor performance. Using a copper-catalyzed, vapor-liquid-solid-growth process, SiCl4 and BCl3 were used to grow ordered arrays of crystalline p-type silicon (p-Si) microwires on p+-Si(111) substrates. When these wire arrays were used as photocathodes in contact with an aqueous methyl viologen(2+/+) electrolyte, energy-conversion efficiencies of up to 3% were observed for monochromatic 808-nanometer light at fluxes comparable to solar illumination, despite an external quantum yield at short circuit of only 0.2. Internal quantum yields were at least 0.7, demonstrating that the measured photocurrents were limited by light absorption in the wire arrays, which filled only 4% of the incident optical plane in our test devices. The inherent performance of these wires thus conceptually allows the development of efficient photovoltaic and photoelectrochemical energy-conversion devices based on a radial junction platform.

A third-order silicon racetrack add-drop filter with a moderate feature size

NASA Astrophysics Data System (ADS)

Wang, Ying; Zhou, Xin; Chen, Qian; Shao, Yue; Chen, Xiangning; Huang, Qingzhong; Jiang, Wei

2018-01-01

In this work, we design and fabricate a highly compact third-order racetrack add-drop filter consisting of silicon waveguides with modified widths on a silicon-on-insulator (SOI) wafer. Compared to the previous approach that requires an exceedingly narrow coupling gap less than 100nm, we propose a new approach that enlarges the minimum feature size of the whole device to be 300 nm to reduce the process requirement. The three-dimensional finite-difference time-domain (3D-FDTD) method is used for simulation. Experiment results show good agreement with simulation results in property. In the experiment, the filter shows a nearly box-like channel dropping response, which has a large flat 3-dB bandwidth ({3 nm), relatively large FSR ({13.3 nm) and out-of-band rejection larger than 14 dB at the drop port with a footprint of 0.0006 mm2 . The device is small and simple enough to have a wide range of applications in large scale on-chip photonic integration circuits.

Silicon MOS inductor

DOEpatents

Balberg, Isaac

1981-01-01

A device made of amorphous silicon which exhibits inductive properties at certain voltage biases and in certain frequency ranges in described. Devices of the type described can be made in integrated circuit form.

Back-junction back-contact n-type silicon solar cell with diffused boron emitter locally blocked by implanted phosphorus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Müller, Ralph, E-mail: ralph.mueller@ise.fraunhofer.de; Schrof, Julian; Reichel, Christian

2014-09-08

The highest energy conversion efficiencies in the field of silicon-based photovoltaics have been achieved with back-junction back-contact (BJBC) silicon solar cells by several companies and research groups. One of the most complex parts of this cell structure is the fabrication of the locally doped p- and n-type regions, both on the back side of the solar cell. In this work, we introduce a process sequence based on a synergistic use of ion implantation and furnace diffusion. This sequence enables the formation of all doped regions for a BJBC silicon solar cell in only three processing steps. We observed that implantedmore » phosphorus can block the diffusion of boron atoms into the silicon substrate by nearly three orders of magnitude. Thus, locally implanted phosphorus can be used as an in-situ mask for a subsequent boron diffusion which simultaneously anneals the implanted phosphorus and forms the boron emitter. BJBC silicon solar cells produced with such an easy-to-fabricate process achieved conversion efficiencies of up to 21.7%. An open-circuit voltage of 674 mV and a fill factor of 80.6% prove that there is no significant recombination at the sharp transition between the highly doped emitter and the highly doped back surface field at the device level.« less

Silicon-based sleeve devices for chemical reactions

DOEpatents

Northrup, M. Allen; Mariella, Jr., Raymond P.; Carrano, Anthony V.; Balch, Joseph W.

1996-01-01

A silicon-based sleeve type chemical reaction chamber that combines heaters, such as doped polysilicon for heating, and bulk silicon for convection cooling. The reaction chamber combines a critical ratio of silicon and silicon nitride to the volume of material to be heated (e.g., a liquid) in order to provide uniform heating, yet low power requirements. The reaction chamber will also allow the introduction of a secondary tube (e.g., plastic) into the reaction sleeve that contains the reaction mixture thereby alleviating any potential materials incompatibility issues. The reaction chamber may be utilized in any chemical reaction system for synthesis or processing of organic, inorganic, or biochemical reactions, such as the polymerase chain reaction (PCR) and/or other DNA reactions, such as the ligase chain reaction, which are examples of a synthetic, thermal-cycling-based reaction. The reaction chamber may also be used in synthesis instruments, particularly those for DNA amplification and synthesis.

Silicon-based sleeve devices for chemical reactions

DOEpatents

Northrup, M.A.; Mariella, R.P. Jr.; Carrano, A.V.; Balch, J.W.

1996-12-31

A silicon-based sleeve type chemical reaction chamber is described that combines heaters, such as doped polysilicon for heating, and bulk silicon for convection cooling. The reaction chamber combines a critical ratio of silicon and silicon nitride to the volume of material to be heated (e.g., a liquid) in order to provide uniform heating, yet low power requirements. The reaction chamber will also allow the introduction of a secondary tube (e.g., plastic) into the reaction sleeve that contains the reaction mixture thereby alleviating any potential materials incompatibility issues. The reaction chamber may be utilized in any chemical reaction system for synthesis or processing of organic, inorganic, or biochemical reactions, such as the polymerase chain reaction (PCR) and/or other DNA reactions, such as the ligase chain reaction, which are examples of a synthetic, thermal-cycling-based reaction. The reaction chamber may also be used in synthesis instruments, particularly those for DNA amplification and synthesis. 32 figs.

Confined silicon nanospheres by biomass lignin for stable lithium ion battery.

PubMed

Niu, Xiaoying; Zhou, Jinqiu; Qian, Tao; Wang, Mengfan; Yan, Chenglin

2017-10-06

Biomass lignin, as a significant renewable resource, is one of the most abundant natural polymers in the world. Here, we report a novel silicon-based material, in which lignin-derived functional conformal network crosslinks the silicon nanoparticles via self-assembly. This newly-developed material could greatly solve the problems of large volume change during lithiation/delithiation process and the formation of unstable solid electrolyte interphase layers on the silicon surface. With this anode, the battery demonstrates a high capacity of ∼3000 mA h g -1 , a highly stable cycling retention (∼89% after 100 cycles at 300 mA g -1 ) and an excellent rate capability (∼800 mA h g -1 at 9 A g -1 ). Moreover, the feasibility of full lithium-ion batteries with the novel silicon-based material would provide wide range of applications in the field of flexible energy storage systems for wearable electronic devices.

Confined silicon nanospheres by biomass lignin for stable lithium ion battery

NASA Astrophysics Data System (ADS)

Niu, Xiaoying; Zhou, Jinqiu; Qian, Tao; Wang, Mengfan; Yan, Chenglin

2017-10-01

Biomass lignin, as a significant renewable resource, is one of the most abundant natural polymers in the world. Here, we report a novel silicon-based material, in which lignin-derived functional conformal network crosslinks the silicon nanoparticles via self-assembly. This newly-developed material could greatly solve the problems of large volume change during lithiation/delithiation process and the formation of unstable solid electrolyte interphase layers on the silicon surface. With this anode, the battery demonstrates a high capacity of ˜3000 mA h g-1, a highly stable cycling retention (˜89% after 100 cycles at 300 mA g-1) and an excellent rate capability (˜800 mA h g-1 at 9 A g-1). Moreover, the feasibility of full lithium-ion batteries with the novel silicon-based material would provide wide range of applications in the field of flexible energy storage systems for wearable electronic devices.

Pulsed energy synthesis and doping of silicon carbide

DOEpatents

Truher, J.B.; Kaschmitter, J.L.; Thompson, J.B.; Sigmon, T.W.

1995-06-20

A method for producing beta silicon carbide thin films by co-depositing thin films of amorphous silicon and carbon onto a substrate is disclosed, whereafter the films are irradiated by exposure to a pulsed energy source (e.g. excimer laser) to cause formation of the beta-SiC compound. Doped beta-SiC may be produced by introducing dopant gases during irradiation. Single layers up to a thickness of 0.5-1 micron have been produced, with thicker layers being produced by multiple processing steps. Since the electron transport properties of beta silicon carbide over a wide temperature range of 27--730 C is better than these properties of alpha silicon carbide, they have wide application, such as in high temperature semiconductors, including HETEROJUNCTION-junction bipolar transistors and power devices, as well as in high bandgap solar arrays, ultra-hard coatings, light emitting diodes, sensors, etc.

Pulsed energy synthesis and doping of silicon carbide

DOEpatents

Truher, Joel B.; Kaschmitter, James L.; Thompson, Jesse B.; Sigmon, Thomas W.

1995-01-01

A method for producing beta silicon carbide thin films by co-depositing thin films of amorphous silicon and carbon onto a substrate, whereafter the films are irradiated by exposure to a pulsed energy source (e.g. excimer laser) to cause formation of the beta-SiC compound. Doped beta-SiC may be produced by introducing dopant gases during irradiation. Single layers up to a thickness of 0.5-1 micron have been produced, with thicker layers being produced by multiple processing steps. Since the electron transport properties of beta silicon carbide over a wide temperature range of 27.degree.-730.degree. C. is better than these properties of alpha silicon carbide, they have wide application, such as in high temperature semiconductors, including hetero-junction bipolar transistors and power devices, as well as in high bandgap solar arrays, ultra-hard coatings, light emitting diodes, sensors, etc.

Development of low-cost silicon crystal growth techniques for terrestrial photovoltaic solar energy conversion

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1976-01-01

Because of the growing need for new sources of electrical energy, photovoltaic solar energy conversion is being developed. Photovoltaic devices are now being produced mainly from silicon wafers obtained from the slicing and polishing of cylindrically shaped single crystal ingots. Inherently high-cost processes now being used must either be eliminated or modified to provide low-cost crystalline silicon. Basic to this pursuit is the development of new or modified methods of crystal growth and, if necessary, crystal cutting. If silicon could be grown in a form requiring no cutting, a significant cost saving would potentially be realized. Therefore, several techniques for growth in the form of ribbons or sheets are being explored. In addition, novel techniques for low-cost ingot growth and cutting are under investigation.

Flexible manufacturing for photonics device assembly

NASA Technical Reports Server (NTRS)

Lu, Shin-Yee; Pocha, Michael D.; Strand, Oliver T.; Young, K. David

1994-01-01

The assembly of photonics devices such as laser diodes, optical modulators, and opto-electronics multi-chip modules (OEMCM), usually requires the placement of micron size devices such as laser diodes, and sub-micron precision attachment between optical fibers and diodes or waveguide modulators (usually referred to as pigtailing). This is a very labor intensive process. Studies done by the opto-electronics (OE) industry have shown that 95 percent of the cost of a pigtailed photonic device is due to the use of manual alignment and bonding techniques, which is the current practice in industry. At Lawrence Livermore National Laboratory, we are working to reduce the cost of packaging OE devices through the use of automation. Our efforts are concentrated on several areas that are directly related to an automated process. This paper will focus on our progress in two of those areas, in particular, an automated fiber pigtailing machine and silicon micro-technology compatible with an automated process.

Nonlinear silicon photonics

NASA Astrophysics Data System (ADS)

Borghi, M.; Castellan, C.; Signorini, S.; Trenti, A.; Pavesi, L.

2017-09-01

Silicon photonics is a technology based on fabricating integrated optical circuits by using the same paradigms as the dominant electronics industry. After twenty years of fervid development, silicon photonics is entering the market with low cost, high performance and mass-manufacturable optical devices. Until now, most silicon photonic devices have been based on linear optical effects, despite the many phenomenologies associated with nonlinear optics in both bulk materials and integrated waveguides. Silicon and silicon-based materials have strong optical nonlinearities which are enhanced in integrated devices by the small cross-section of the high-index contrast silicon waveguides or photonic crystals. Here the photons are made to strongly interact with the medium where they propagate. This is the central argument of nonlinear silicon photonics. It is the aim of this review to describe the state-of-the-art in the field. Starting from the basic nonlinearities in a silicon waveguide or in optical resonator geometries, many phenomena and applications are described—including frequency generation, frequency conversion, frequency-comb generation, supercontinuum generation, soliton formation, temporal imaging and time lensing, Raman lasing, and comb spectroscopy. Emerging quantum photonics applications, such as entangled photon sources, heralded single-photon sources and integrated quantum photonic circuits are also addressed at the end of this review.

Microdynamic Devices Fabricated on Silicon-On-Sapphire Substrates.

DTIC Science & Technology

Silicon-on-sapphire substrates are provided for the fabrication of micromechanical devices, such as micromotors . The high voltage stand-off...a consequence, the electrostatically driven devices, micromotors , can be incorporated in the integrated circuits and yet be powered at elevated voltages to increase their work potential.

Influence of polarized bias and porous silicon morphology on the electrical behavior of Au-porous silicon contacts*

PubMed Central

Zhao, Yue; Li, Dong-sheng; Xing, Shou-xiang; Yang, De-ren; Jiang, Min-hua

2005-01-01

This paper reports the surface morphology and I-V curves of porous silicon (PS) samples and related devices. The observed fabrics on the PS surface were found to affect the electrical property of PS devices. When the devices were operated under different external bias (10 V or 3 V) for 10 min, their observed obvious differences in electrical properties may be due to the different control mechanisms in the Al/PS interface and PS matrix morphology. PMID:16252350

Efficient Near-Infrared-Transparent Perovskite Solar Cells Enabling Direct Comparison of 4-Terminal and Monolithic Perovskite/Silicon Tandem Cells

DOE PAGES

Werner, Jeremie; Barraud, Loris; Walter, Arnaud; ...

2016-07-30

Combining market-proven silicon solar cell technology with an efficient wide band gap top cell into a tandem device is an attractive approach to reduce the cost of photovoltaic systems. For this, perovskite solar cells are promising high-efficiency top cell candidates, but their typical device size (<0.2 cm 2), is still far from standard industrial sizes. Here, we present a 1 cm 2 near-infrared transparent perovskite solar cell with 14.5% steadystate efficiency, as compared to 16.4% on 0.25 cm 2. By mechanically stacking these cells with silicon heterojunction cells, we experimentally demonstrate a 4-terminal tandem measurement with a steady-state efficiency ofmore » 25.2%, with a 0.25 cm 2 top cell. The developed top cell processing methods enable the fabrication of a 20.5% efficient and 1.43 cm 2 large monolithic perovskite/silicon heterojunction tandem solar cell, featuring a rear-side textured bottom cell to increase its near-infrared spectral response. Finally, we compare both tandem configurations to identify efficiency-limiting factors and discuss the potential for further performance improvement.« less

Efficient Near-Infrared-Transparent Perovskite Solar Cells Enabling Direct Comparison of 4-Terminal and Monolithic Perovskite/Silicon Tandem Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Werner, Jeremie; Barraud, Loris; Walter, Arnaud

Combining market-proven silicon solar cell technology with an efficient wide band gap top cell into a tandem device is an attractive approach to reduce the cost of photovoltaic systems. For this, perovskite solar cells are promising high-efficiency top cell candidates, but their typical device size (<0.2 cm 2), is still far from standard industrial sizes. Here, we present a 1 cm 2 near-infrared transparent perovskite solar cell with 14.5% steadystate efficiency, as compared to 16.4% on 0.25 cm 2. By mechanically stacking these cells with silicon heterojunction cells, we experimentally demonstrate a 4-terminal tandem measurement with a steady-state efficiency ofmore » 25.2%, with a 0.25 cm 2 top cell. The developed top cell processing methods enable the fabrication of a 20.5% efficient and 1.43 cm 2 large monolithic perovskite/silicon heterojunction tandem solar cell, featuring a rear-side textured bottom cell to increase its near-infrared spectral response. Finally, we compare both tandem configurations to identify efficiency-limiting factors and discuss the potential for further performance improvement.« less

Deuterated silicon nitride photonic devices for broadband optical frequency comb generation

NASA Astrophysics Data System (ADS)

Chiles, Jeff; Nader, Nima; Hickstein, Daniel D.; Yu, Su Peng; Briles, Travis Crain; Carlson, David; Jung, Hojoong; Shainline, Jeffrey M.; Diddams, Scott; Papp, Scott B.; Nam, Sae Woo; Mirin, Richard P.

2018-04-01

We report and characterize low-temperature, plasma-deposited deuterated silicon nitride thin films for nonlinear integrated photonics. With a peak processing temperature less than 300$^\\circ$C, it is back-end compatible with pre-processed CMOS substrates. We achieve microresonators with a quality factor of up to $1.6\\times 10^6 $ at 1552 nm, and $>1.2\\times 10^6$ throughout $\\lambda$ = 1510 -- 1600 nm, without annealing or stress management. We then demonstrate the immediate utility of this platform in nonlinear photonics by generating a 1 THz free spectral range, 900-nm-bandwidth modulation-instability microresonator Kerr comb and octave-spanning, supercontinuum-broadened spectra.

Review Application of Nanostructured Black Silicon

NASA Astrophysics Data System (ADS)

Lv, Jian; Zhang, Ting; Zhang, Peng; Zhao, Yingchun; Li, Shibin

2018-04-01

As a widely used semiconductor material, silicon has been extensively used in many areas, such as photodiode, photodetector, and photovoltaic devices. However, the high surface reflectance and large bandgap of traditional bulk silicon restrict the full use of the spectrum. To solve this problem, many methods have been developed. Among them, the surface nanostructured silicon, namely black silicon, is the most efficient and widely used. Due to its high absorption in the wide range from UV-visible to infrared, black silicon is very attractive for using as sensitive layer of photodiodes, photodetector, solar cells, field emission, luminescence, and other photoelectric devices. Intensive study has been performed to understand the enhanced absorption of black silicon as well as the response extended to infrared spectrum range. In this paper, the application of black silicon is systematically reviewed. The limitations and challenges of black silicon material are also discussed. This article will provide a meaningful introduction to black silicon and its unique properties.

Microfabricated sleeve devices for chemical reactions

DOEpatents

Northrup, M. Allen

2003-01-01

A silicon-based sleeve type chemical reaction chamber that combines heaters, such as doped polysilicon for heating, and bulk silicon for convection cooling. The reaction chamber combines a critical ratio of silicon and non-silicon based materials to provide the thermal properties desired. For example, the chamber may combine a critical ratio of silicon and silicon nitride to the volume of material to be heated (e.g., a liquid) in order to provide uniform heating, yet low power requirements. The reaction chamber will also allow the introduction of a secondary tube (e.g., plastic) into the reaction sleeve that contains the reaction mixture thereby alleviating any potential materials incompatibility issues. The reaction chamber may be utilized in any chemical reaction system for synthesis or processing of organic, inorganic, or biochemical reactions, such as the polymerase chain reaction (PCR) and/or other DNA reactions, such as the ligase chain reaction, which are examples of a synthetic, thermal-cycling-based reaction. The reaction chamber may also be used in synthesis instruments, particularly those for DNA amplification and synthesis.

Advanced Silicon-on-Insulator: Crystalline Silicon on Atomic Layer Deposited Beryllium Oxide.

PubMed

Min Lee, Seung; Hwan Yum, Jung; Larsen, Eric S; Chul Lee, Woo; Keun Kim, Seong; Bielawski, Christopher W; Oh, Jungwoo

2017-10-16

Silicon-on-insulator (SOI) technology improves the performance of devices by reducing parasitic capacitance. Devices based on SOI or silicon-on-sapphire technology are primarily used in high-performance radio frequency (RF) and radiation sensitive applications as well as for reducing the short channel effects in microelectronic devices. Despite their advantages, the high substrate cost and overheating problems associated with complexities in substrate fabrication as well as the low thermal conductivity of silicon oxide prevent broad applications of this technology. To overcome these challenges, we describe a new approach of using beryllium oxide (BeO). The use of atomic layer deposition (ALD) for producing this material results in lowering the SOI wafer production cost. Furthermore, the use of BeO exhibiting a high thermal conductivity might minimize the self-heating issues. We show that crystalline Si can be grown on ALD BeO and the resultant devices exhibit potential for use in advanced SOI technology applications.

The modeling of MMI structures for signal processing applications

NASA Astrophysics Data System (ADS)

Le, Thanh Trung; Cahill, Laurence W.

2008-02-01

Microring resonators are promising candidates for photonic signal processing applications. However, almost all resonators that have been reported so far use directional couplers or 2×2 multimode interference (MMI) couplers as the coupling element between the ring and the bus waveguides. In this paper, instead of using 2×2 couplers, novel structures for microring resonators based on 3×3 MMI couplers are proposed. The characteristics of the device are derived using the modal propagation method. The device parameters are optimized by using numerical methods. Optical switches and filters using Silicon on Insulator (SOI) then have been designed and analyzed. This device can become a new basic component for further applications in optical signal processing. The paper concludes with some further examples of photonic signal processing circuits based on MMI couplers.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology.

PubMed

Llobet, J; Rius, G; Chuquitarqui, A; Borrisé, X; Koops, R; van Veghel, M; Perez-Murano, F

2018-04-02

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

NASA Astrophysics Data System (ADS)

Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

2018-04-01

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Impurity gettering in semiconductors

DOEpatents

Sopori, B.L.

1995-06-20

A process for impurity gettering in a semiconductor substrate or device such as a silicon substrate or device is disclosed. The process comprises hydrogenating the substrate or device at the back side thereof with sufficient intensity and for a time period sufficient to produce a damaged back side. Thereafter, the substrate or device is illuminated with electromagnetic radiation at an intensity and for a time period sufficient to cause the impurities to diffuse to the back side and alloy with a metal there present to form a contact and capture the impurities. The impurity gettering process also can function to simultaneously passivate defects within the substrate or device, with the defects likewise diffusing to the back side for simultaneous passivation. Simultaneously, substantially all hydrogen-induced damage on the back side of the substrate or device is likewise annihilated. Also taught is an alternate process comprising thermal treatment after hydrogenation of the substrate or device at a temperature of from about 500 C to about 700 C for a time period sufficient to cause the impurities to diffuse to the damaged back side thereof for subsequent capture by an alloying metal. 1 fig.

Impurity gettering in semiconductors

DOEpatents

Sopori, Bhushan L.

1995-01-01

A process for impurity gettering in a semiconductor substrate or device such as a silicon substrate or device. The process comprises hydrogenating the substrate or device at the back side thereof with sufficient intensity and for a time period sufficient to produce a damaged back side. Thereafter, the substrate or device is illuminated with electromagnetic radiation at an intensity and for a time period sufficient to cause the impurities to diffuse to the back side and alloy with a metal there present to form a contact and capture the impurities. The impurity gettering process also can function to simultaneously passivate defects within the substrate or device, with the defects likewise diffusing to the back side for simultaneous passivation. Simultaneously, substantially all hydrogen-induced damage on the back side of the substrate or device is likewise annihilated. Also taught is an alternate process comprising thermal treatment after hydrogenation of the substrate or device at a temperature of from about 500.degree. C. to about 700.degree. C. for a time period sufficient to cause the impurities to diffuse to the damaged back side thereof for subsequent capture by an alloying metal.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, B.

The 11th Workshop will provide a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and non-photovoltaic fields. Discussions will include the various aspects of impurities and defects in silicon--their properties, the dynamics during device processing, and their application for developing low-cost processes for manufacturing high-efficiency silicon solar cells. Sessions and panel discussions will review impurities and defects in crystalline-silicon PV, advanced cell structures, new processes and process characterization techniques, and future manufacturing demands. The workshop will emphasize some of the promising new technologies in Si solar cell fabrication that can lower PVmore » energy costs and meet the throughput demands of the future. The three-day workshop will consist of presentations by invited speakers, followed by discussion sessions. Topics to be discussed are: Si Mechanical properties and Wafer Handling, Advanced Topics in PV Fundamentals, Gettering and Passivation, Impurities and Defects, Advanced Emitters, Crystalline Silicon Growth, and Solar Cell Processing. The workshop will also include presentations by NREL subcontractors who will review the highlights of their research during the current subcontract period. In addition, there will be two poster sessions presenting the latest research and development results. Some presentations will address recent technologies in the microelectronics field that may have a direct bearing on PV.« less

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, K.H.

1998-06-30

A method is disclosed for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates. 1 fig.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, Kurt H.

1998-01-01

A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates.

CMOS Imager Has Better Cross-Talk and Full-Well Performance

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas J.

2011-01-01

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Nanostructure iron-silicon thin film deposition using plasma focus device

NASA Astrophysics Data System (ADS)

Kotb, M.; Saudy, A. H.; Hassaballa, S.; Eloker, M. M.

2013-03-01

The presented study in this paper reports the deposition of nano-structure iron-silicon thin film on a glass substrate using 3.3 KJ Mather-type plasma focus device. The iron-silicon powder was put on the top of hollow copper anode electrode. The deposition was done under different experimental conditions such as numbers of electric discharge shots and angular position of substrate. The film samples were exposed to energetic argon ions generated by plasma focus device at different distances from the top of the central electrode. The exposed samples were then analyzed for their structure and optical properties using X-ray diffraction (XRD) and UV-visible spectroscopy. The structure of iron-silicon thin films deposited using plasma focus device depends on the distance from the anode, the number of focus deposition shots and the angular position of the sample

Silicon carbide, an emerging high temperature semiconductor

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony

1991-01-01

In recent years, the aerospace propulsion and space power communities have expressed a growing need for electronic devices that are capable of sustained high temperature operation. Applications for high temperature electronic devices include development instrumentation within engines, engine control, and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Other earth-based applications include deep-well drilling instrumentation, nuclear reactor instrumentation and control, and automotive sensors. To meet the needs of these applications, the High Temperature Electronics Program at the Lewis Research Center is developing silicon carbide (SiC) as a high temperature semiconductor material. Research is focussed on developing the crystal growth, characterization, and device fabrication technologies necessary to produce a family of silicon carbide electronic devices and integrated sensors. The progress made in developing silicon carbide is presented, and the challenges that lie ahead are discussed.

Silicone metalization

DOEpatents

Maghribi, Mariam N [Livermore, CA; Krulevitch, Peter [Pleasanton, CA; Hamilton, Julie [Tracy, CA

2006-12-05

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Silicone metalization

DOEpatents

Maghribi, Mariam N.; Krulevitch, Peter; Hamilton, Julie

2008-12-09

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

MEMS for vibration energy harvesting

NASA Astrophysics Data System (ADS)

Li, Lin; Zhang, Yangjian; San, Haisheng; Guo, Yinbiao; Chen, Xuyuan

2008-03-01

In this paper, a capacitive vibration-to-electrical energy harvester was designed. An integrated process flow for fabricating the designed capacitive harvester is presented. For overcoming the disadvantage of depending on external power source in capacitive energy harvester, two parallel electrodes with different work functions are used as the two electrodes of the capacitor to generate a build-in voltage for initially charging the capacitor. The device is a sandwich structure of silicon layer in two glass layers with area of about 1 cm2. The silicon structure is fabricated by using silicon-on-insulator (SOI) wafer. The glass wafers are anodic bonded on to both sides of the SOI wafer to create a vacuum sealed package.

Silicone and Fluorosilicone Based Materials for Biomedical Applications

NASA Astrophysics Data System (ADS)

Palsule, Aniruddha S.

The biocompatibility and the biodurability of silicones is a result of various material properties such as hydrophobicity, low surface tension, high elasticity and chemical and thermal stability. A variety of biomedical implants employ an inflatable silicone rubber balloon filled with a saline solution. Commercial examples of such a system are silicone breast implants, tissue expanders and gastric bands for obesity control. Despite the advantages, saline filled silicones systems still have a certain set of challenges that need to be addressed in order to improve the functionality of these devices and validate their use as biomaterials. The central goal of this research is to identify these concerns, design solutions and to provide a better understanding of the behavior of implantable silicones. The first problem this research focuses on is the quantification and identification of the low molecular weight silicones that are not crosslinked into the elastomeric matrix and therefore can be leached out by solvent extraction. We have developed an environmentally friendly pre-extraction technique using supercritical CO 2 and also determined the exact nature of the extractables using Gas Chromatography. We have also attempted to address the issue of an observed loss of pressure in the saline filled device during application by studying the relaxation behavior of silicone elastomer using Dynamic Mechanical Analysis and constructing long-term relaxation master curves. We have also developed a technique to develop highly hydrophobic fluorinated barrier layers for the silicone in order to prevent diffusion of water vapor across the walls of the implant. This involves a hybrid process consisting of surface modification by plasma technology followed by two different coating formulations. The first formulation employed UV curable fluorinated acrylate monomers for the coating process and the second was based on Atom Transfer Radical Polymerization (ATRP) to generate a fluorinated coating that is covalently grafted on the silicone surface in the form of dense polymer brushes. The research also attempts to validate the use of sterilization of the implant with gamma irradiation by comprehensively reviewing the existing literature and then summarizing the effects of gamma irradiation on linear, cyclic and crosslinked silicones. We have predicted a model describing the effects of irradiation and supplemented that with data in the laboratory. Finally we have investigated the use of biological enzymes as alternate catalyst systems for the synthesis of silicone copolymers. We have demonstrated the use of the enzyme Lipase (CALB), as a catalyst for the synthesis of fluorosilicone copolymers containing ester and amide linkages.

Method of high purity silane preparation

DOEpatents

Tsuo, Y. Simon; Belov, Eugene P.; Gerlivanov, Vadim G.; Zadde, Vitali V.; Kleschevnikova, Solomonida I.; Korneev, Nikolai N.; Lebedev, Eugene N.; Pinov, Akhsarbek B.; Ryabenko, Eugene A.; Strebkov, Dmitry S.; Chernyshev, Eugene A.

2000-01-01

A process for the preparation of high purity silane, suitable for forming thin layer silicon structures in various semiconductor devices and high purity poly- and single crystal silicon for a variety of applications, is provided. Synthesis of high-purity silane starts with a temperature assisted reaction of metallurgical silicon with alcohol in the presence of a catalyst. Alcoxysilanes formed in the silicon-alcohol reaction are separated from other products and purified. Simultaneous reduction and oxidation of alcoxysilanes produces gaseous silane and liquid secondary products, including, active part of a catalyst, tetra-alcoxysilanes, and impurity compounds having silicon-hydrogen bonds. Silane is purified by an impurity adsorption technique. Unreacted alcohol is extracted and returned to the reaction with silicon. Concentrated mixture of alcoxysilanes undergoes simultaneous oxidation and reduction in the presence of a catalyst at the temperature -20.degree. C. to +40.degree. C. during 1 to 50 hours. Tetra-alcoxysilane extracted from liquid products of simultaneous oxidation and reduction reaction is directed to a complete hydrolysis. Complete hydrolysis of tetra-alcoxysilane results in formation of industrial silica sol and alcohol. Alcohol is dehydrated by tetra-alcoxysilane and returned to the reaction with silicon.

Design, fabrication, and characterization of 4H-silicon carbide rectifiers for power switching applications

NASA Astrophysics Data System (ADS)

Sheridan, David Charles

Silicon Carbide has received a substantial increase in research interest over the past few years as a base material system for high-frequency and high-power semiconductor devices. Of the over 1200 polytypes, 4H-SiC is the most attractive polytype for power devices due to its wide band gap (3.2eV), excellent thermal conductivity (4.9 W/cm·K), and high critical field strength (˜2 x 106 V/cm). Important for power devices, the 10x increase in critical field strength of SiC allows high voltage blocking layers to be fabricated significantly thinner than for comparable Si devices. For power rectifiers, this reduces device on-resistance, while maintaining the same high voltage blocking capability. In this work, 4H-SiC Schottky, pn, and junction barrier Schottky (JBS) rectifiers for use in high voltage switching applications have been designed, fabricated, and extensively characterized. First, a detailed review of 4H-SiC material parameters was performed and SiC models were implemented into a standard Si drift-diffusion numerical simulator. Using these models, a SiC simulation methodology was developed in order to enable predictive SiC device design. A wide variety of rectifier and edge termination designs were investigated and optimized with respect to breakdown efficiency, area consumption, resistance to interface charge, and fabrication practicality. Simulated termination methods include: field plates, floating guard rings, and a variety of junction termination extensions (JTE). Using the device simulation results, both Schottky and JBS rectifiers were fabricated with a novel self-aligned edge termination design, and fabricated with process elements developed at the Alabama Microelectronics Science and Technology Center facility. These rectifiers exhibited near-ideal forward characteristics and had blocking voltages in excess of 2.5kV. The SiC diodes were subjected to inductive switching tests, and were found to have superior reverse recovery characteristics compared to a similar Si diode. Finally, the performance of these SiC rectifiers were tested in inductive switching circuits and in high dose gamma radiation environments. In both cases, these devices were shown to be superior to their silicon counterparts. The details of this work was presented and published in the proceedings of the 45th International Meeting of the American Vacuum Society [1], the 1999 International Conference on Silicon Carbide and Related Materials [2, 3] and the 2000 European Conference on Silicon Carbide and Related Materials [4]. The expanded conference papers were published in the international journal. Solid-State Electronics [5, 6].

A Silicon-Chip Source of Bright Photon-Pair Comb

DTIC Science & Technology

2012-10-16

A silicon -chip source of bright photon-pair comb Wei C. Jiang,1, ∗ Xiyuan Lu,2, ∗ Jidong Zhang,3 Oskar Painter,4 and Qiang Lin1, 3, † 1Institute of...efficient monolithic photon-pair source for on-chip application. Here we report a device on the silicon -on-insulator platform that utilizes dramatic cavity...enhanced four-wave mixing in a high-Q silicon microdisk resonator. The device is able to produce high-purity photon pairs in a comb fashion, with an

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

DTIC Science & Technology

2011-11-01

stack between the GaN and Substrate layers. The University of Bristol recently reported that this TBR in commercial devices on Silicon Carbide ( SiC ...Circuit RF Radio Frequency PA Power Amplifier SiC Silicon Carbide FEA Finite Element Analysis heff Effective Heat transfer Coefficient (W/m 2 K...substrate material switched from sapphire to silicon , and by another factor of two from silicon to SiC . TABLE 1: SAMPLE RESULTS FROM DOUGLAS ET AL. FOR

Thermally tunable silicon racetrack resonators with ultralow tuning power.

PubMed

Dong, Po; Qian, Wei; Liang, Hong; Shafiiha, Roshanak; Feng, Dazeng; Li, Guoliang; Cunningham, John E; Krishnamoorthy, Ashok V; Asghari, Mehdi

2010-09-13

We present thermally tunable silicon racetrack resonators with an ultralow tuning power of 2.4 mW per free spectral range. The use of free-standing silicon racetrack resonators with undercut structures significantly enhances the tuning efficiency, with one order of magnitude improvement of that for previously demonstrated thermo-optic devices without undercuts. The 10%-90% switching time is demonstrated to be ~170 µs. Such low-power tunable micro-resonators are particularly useful as multiplexing devices and wavelength-tunable silicon microcavity modulators.

Effect of post-implantation annealing on Al-N isoelectronic trap formation in silicon: Al-N pair formation and defect recovery mechanisms

NASA Astrophysics Data System (ADS)

Mori, Takahiro; Morita, Yukinori; Matsukawa, Takashi

2018-05-01

The effect of post-implantation annealing (PIA) on Al-N isoelectronic trap (IET) formation in silicon has been experimentally investigated to discuss the Al-N IET formation and implantation-induced defect recovery mechanisms. We performed a photoluminescence study, which indicated that self-interstitial clusters and accompanying vacancies are generated in the ion implantation process. It is supposed that Al and N atoms move to the vacancy sites and form stable Al-N pairs in the PIA process. Furthermore, the PIA process recovers self-interstitial clusters while transforming their atomic configuration. The critical temperature for the formation/dissociation of Al-N pairs was found to be 450 °C, with which we describe the process integration for devices utilizing Al-N IET technology.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Programmable DNA-Mediated Multitasking Processor.

PubMed

Shu, Jian-Jun; Wang, Qi-Wen; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

2015-04-30

Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boccard, Mathieu; Holman, Zachary C.

Amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphous silicon carbide beingmore » shown to surpass amorphous silicon for temperatures above 300 °C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boccard, Mathieu; Holman, Zachary C.

With this study, amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphousmore » silicon carbide being shown to surpass amorphous silicon for temperatures above 300°C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE PAGES

Boccard, Mathieu; Holman, Zachary C.

2015-08-14

With this study, amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphousmore » silicon carbide being shown to surpass amorphous silicon for temperatures above 300°C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

PubMed

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Efficiency enhancement of silicon nanowire solar cells by using UV/Ozone treatments and micro-grid electrodes

NASA Astrophysics Data System (ADS)

Chen, Junyi; Subramani, Thiyagu; Sun, Yonglie; Jevasuwan, Wipakorn; Fukata, Naoki

2018-05-01

Silicon nanowire solar cells were fabricated by metal catalyzed electroless etching (MCEE) followed by thermal chemical vapor deposition (CVD). In this study, we investigated two effects, a UV/ozone treatment and the use of a micro-grid electrodes, to enhance light absorption and reduce the optic losses in the solar cell device. The UV/ozone treatment successfully improved the conversion efficiency. The micro-grid electrodes were then applied in solar cell devices subjected to a back surface field (BSF) treatment and rapid thermal annealing (RTA). These effects improved the conversion efficiency from 9.4% to 10.9%. Moreover, to reduce surface recombination and improve the continuity of front electrodes, we optimized the etching time of the MCEE process, giving a high efficiency of 12.3%.

Role of the inversion layer on the charge injection in silicon nanocrystal multilayered light emitting devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tondini, S.; Dipartimento di Fisica, Informatica e Matematica, Università di Modena e Reggio Emilia, Via Campi 213/a, 41125 Modena; Pucker, G.

2016-09-07

The role of the inversion layer on injection and recombination phenomena in light emitting diodes (LEDs) is here studied on a multilayer (ML) structure of silicon nanocrystals (Si-NCs) embedded in SiO{sub 2}. Two Si-NC LEDs, which are similar for the active material but different in the fabrication process, elucidate the role of the non-radiative recombination rates at the ML/substrate interface. By studying current- and capacitance-voltage characteristics as well as electroluminescence spectra and time-resolved electroluminescence under pulsed and alternating bias pumping scheme in both the devices, we are able to ascribe the different experimental results to an efficient or inefficient minoritymore » carrier (electron) supply by the p-type substrate in the metal oxide semiconductor LEDs.« less