A deep etching mechanism for trench-bridging silicon nanowires

NASA Astrophysics Data System (ADS)

Tasdemir, Zuhal; Wollschläger, Nicole; Österle, Werner; Leblebici, Yusuf; Erdem Alaca, B.

2016-03-01

Introducing a single silicon nanowire with a known orientation and dimensions to a specific layout location constitutes a major challenge. The challenge becomes even more formidable, if one chooses to realize the task in a monolithic fashion with an extreme topography, a characteristic of microsystems. The need for such a monolithic integration is fueled by the recent surge in the use of silicon nanowires as functional building blocks in various electromechanical and optoelectronic applications. This challenge is addressed in this work by introducing a top-down, silicon-on-insulator technology. The technology provides a pathway for obtaining well-controlled silicon nanowires along with the surrounding microscale features up to a three-order-of-magnitude scale difference. A two-step etching process is developed, where the first shallow etch defines a nanoscale protrusion on the wafer surface. After applying a conformal protection on the protrusion, a deep etch step is carried out forming the surrounding microscale features. A minimum nanowire cross-section of 35 nm by 168 nm is demonstrated in the presence of an etch depth of 10 μm. Nanowire cross-sectional features are characterized via transmission electron microscopy and linked to specific process steps. The technology allows control on all dimensional aspects along with the exact location and orientation of the silicon nanowire. The adoption of the technology in the fabrication of micro and nanosystems can potentially lead to a significant reduction in process complexity by facilitating direct access to the nanowire during surface processes such as contact formation and doping.

A deep etching mechanism for trench-bridging silicon nanowires.

PubMed

Tasdemir, Zuhal; Wollschläger, Nicole; Österle, Werner; Leblebici, Yusuf; Alaca, B Erdem

2016-03-04

Introducing a single silicon nanowire with a known orientation and dimensions to a specific layout location constitutes a major challenge. The challenge becomes even more formidable, if one chooses to realize the task in a monolithic fashion with an extreme topography, a characteristic of microsystems. The need for such a monolithic integration is fueled by the recent surge in the use of silicon nanowires as functional building blocks in various electromechanical and optoelectronic applications. This challenge is addressed in this work by introducing a top-down, silicon-on-insulator technology. The technology provides a pathway for obtaining well-controlled silicon nanowires along with the surrounding microscale features up to a three-order-of-magnitude scale difference. A two-step etching process is developed, where the first shallow etch defines a nanoscale protrusion on the wafer surface. After applying a conformal protection on the protrusion, a deep etch step is carried out forming the surrounding microscale features. A minimum nanowire cross-section of 35 nm by 168 nm is demonstrated in the presence of an etch depth of 10 μm. Nanowire cross-sectional features are characterized via transmission electron microscopy and linked to specific process steps. The technology allows control on all dimensional aspects along with the exact location and orientation of the silicon nanowire. The adoption of the technology in the fabrication of micro and nanosystems can potentially lead to a significant reduction in process complexity by facilitating direct access to the nanowire during surface processes such as contact formation and doping.

High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Antoniadis, H.

Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink highmore » efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.« less

Silicon photonics and challenges for fabrication

NASA Astrophysics Data System (ADS)

Feilchenfeld, N. B.; Nummy, K.; Barwicz, T.; Gill, D.; Kiewra, E.; Leidy, R.; Orcutt, J. S.; Rosenberg, J.; Stricker, A. D.; Whiting, C.; Ayala, J.; Cucci, B.; Dang, D.; Doan, T.; Ghosal, M.; Khater, M.; McLean, K.; Porth, B.; Sowinski, Z.; Willets, C.; Xiong, C.; Yu, C.; Yum, S.; Giewont, K.; Green, W. M. J.

2017-03-01

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

Technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE)

NASA Astrophysics Data System (ADS)

Wegrzecka, Iwona; Panas, Andrzej; Bar, Jan; Budzyński, Tadeusz; Grabiec, Piotr; Kozłowski, Roman; Sarnecki, Jerzy; Słysz, Wojciech; Szmigiel, Dariusz; Wegrzecki, Maciej; Zaborowski, Michał

2013-07-01

The paper discusses the technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE). The developed technology enables the fabrication of both planar and epiplanar p+-ν-n+ detector structures with an active area of up to 50 cm2. The starting material for epiplanar structures are silicon wafers with a high-resistivity n-type epitaxial layer ( ν layer - ρ < 3 kΩcm) deposited on a highly doped n+-type substrate (ρ< 0,02Ωcm) developed and fabricated at the Institute of Electronic Materials Technology. Active layer thickness of the epiplanar detectors (νlayer) may range from 10 μm to 150 μm. Imported silicon with min. 5 kΩcm resistivity is used to fabricate planar detectors. Active layer thickness of the planar detectors (ν) layer) may range from 200 μm to 1 mm. This technology enables the fabrication of both discrete and multi-junction detectors (monolithic detector arrays), such as single-sided strip detectors (epiplanar and planar) and double-sided strip detectors (planar). Examples of process diagrams for fabrication of the epiplanar and planar detectors are presented in the paper, and selected technological processes are discussed.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the crucial development step between the original research effort in Lexington and the GW factory scheduled to be online before the end of the decade. At the conclusion of the project, it is clear that the Direct Wafer™ technology will have a dramatic impact on the entire silicon photovoltaic supply chain by effectively doubling existing silicon capacity (by reducing silicon usage by 50%) and reducing supply chain capital costs by 35%. The technology, when fully-scaled in the US, will also lead to significant job growth, with the eventual creation of 1,000 jobs in Western New York.« less

High Power Silicon Carbide (SiC) Power Processing Unit Development

NASA Technical Reports Server (NTRS)

Scheidegger, Robert J.; Santiago, Walter; Bozak, Karin E.; Pinero, Luis R.; Birchenough, Arthur G.

2015-01-01

NASA GRC successfully designed, built and tested a technology-push power processing unit for electric propulsion applications that utilizes high voltage silicon carbide (SiC) technology. The development specifically addresses the need for high power electronics to enable electric propulsion systems in the 100s of kilowatts. This unit demonstrated how high voltage combined with superior semiconductor components resulted in exceptional converter performance.

Mirror Technology

NASA Technical Reports Server (NTRS)

1992-01-01

Under a NASA contract, MI-CVD developed a process for producing bulk silicon carbide by means of a chemical vapor deposition process. The technology allows growth of a high purity material with superior mechanical/thermal properties and high polishability - ideal for mirror applications. The company employed the technology to develop three research mirrors for NASA Langley and is now marketing it as CVD SILICON CARBIDE. Its advantages include light weight, thermal stability and high reflectivity. The material has nuclear research facility applications and is of interest to industrial users of high power lasers.

New technologies for solar energy silicon - Cost analysis of dichlorosilane process

NASA Technical Reports Server (NTRS)

Yaws, C. L.; Li, K.-Y.; Chu, T. C. T.; Fang, C. S.; Lutwack, R.; Briglio, A., Jr.

1981-01-01

A reduction in the cost of silicon for solar cells is an important objective in a project concerned with the reduction of the cost of electricity produced with solar cells. The cost goal for the silicon material is about $14 per kg (1980 dollars). The process which is currently employed to produce semiconductor grade silicon from trichlorosilane is not suited for meeting this cost goal. Other processes for producing silicon are, therefore, being investigated. A description is presented of results obtained for the DCS process which involves the production of dichlorosilane as a silicon source material for solar energy silicon. Major benefits of dichlorosilane as a silicon source material include faster reaction rates for chemical vapor deposition of silicon. The DCS process involves the reaction 2SiHCl3 yields reversibly SiH2Cl2 + SiCl4. The results of a cost analysis indicate a total product cost without profit of $1.29/kg of SiH2Cl2.

Rapid Prototyping of Nanofluidic Slits in a Silicone Bilayer

PubMed Central

Kole, Thomas P.; Liao, Kuo-Tang; Schiffels, Daniel; Ilic, B. Robert; Strychalski, Elizabeth A.; Kralj, Jason G.; Liddle, J. Alexander; Dritschilo, Anatoly; Stavis, Samuel M.

2015-01-01

This article reports a process for rapidly prototyping nanofluidic devices, particularly those comprising slits with microscale widths and nanoscale depths, in silicone. This process consists of designing a nanofluidic device, fabricating a photomask, fabricating a device mold in epoxy photoresist, molding a device in silicone, cutting and punching a molded silicone device, bonding a silicone device to a glass substrate, and filling the device with aqueous solution. By using a bilayer of hard and soft silicone, we have formed and filled nanofluidic slits with depths of less than 400 nm and aspect ratios of width to depth exceeding 250 without collapse of the slits. An important attribute of this article is that the description of this rapid prototyping process is very comprehensive, presenting context and details which are highly relevant to the rational implementation and reliable repetition of the process. Moreover, this process makes use of equipment commonly found in nanofabrication facilities and research laboratories, facilitating the broad adaptation and application of the process. Therefore, while this article specifically informs users of the Center for Nanoscale Science and Technology (CNST) at the National Institute of Standards and Technology (NIST), we anticipate that this information will be generally useful for the nanofabrication and nanofluidics research communities at large, and particularly useful for neophyte nanofabricators and nanofluidicists. PMID:26958449

Silicon Carbide Technologies for Lightweighted Aerospace Mirrors

DTIC Science & Technology

2008-09-01

Silicon Carbide Technologies for Lightweighted Aerospace Mirrors Lawrence E. Matson (1) Ming Y. Chen (1) Brett deBlonk (2) Iwona A...glass and beryllium to produce lightweighted aerospace mirror systems has reached its limits due to the long lead times, high processing costs...for making mirror structural substrates, figuring and finishing technologies being investigated to reduce cost time and cost, and non-destructive

Lead sulfide - Silicon MOSFET infrared focal plane development

NASA Technical Reports Server (NTRS)

Barrett, J. R.; Jhabvala, M. D.

1983-01-01

A process for directly integrating photoconductive lead sulfide (PbS) infrared detector material with silicon MOS integrated circuits has been developed primarily for application in long (greater than 10,000 detector elements) linear arrays for pushbroom scanning applications. The processing technology is based on the conventional PMOS and CMOS technologies with a variation in the metallization. Results and measurements on a fully integrated eight-element multiplexer are shown.

Lithographic fabrication of nanoapertures

DOEpatents

Fleming, James G.

2003-01-01

A new class of silicon-based lithographically defined nanoapertures and processes for their fabrication using conventional silicon microprocessing technology have been invented. The new ability to create and control such structures should significantly extend our ability to design and implement chemically selective devices and processes.

Low cost solar array project: Experimental process system development unit for producing semiconductor-grade silicon using silane-to-silicon process

NASA Technical Reports Server (NTRS)

1980-01-01

The design, fabrication, and installation of an experimental process system development unit (EPSDU) were analyzed. Supporting research and development were performed to provide an information data base usable for the EPSDU and for technological design and economical analysis for potential scale-up of the process. Iterative economic analyses were conducted for the estimated product cost for the production of semiconductor grade silicon in a facility capable of producing 1000-MT/Yr.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Critical technology limits to silicon material and sheet production

NASA Technical Reports Server (NTRS)

Leipold, M. H.

1982-01-01

Earlier studies have indicated that expenditures related to the preparation of high-purity silicon and its conversion to silicon sheet represent from 40 to 52 percent of the cost of the entire panel. The present investigation is concerned with the elements which were selected for study in connection with the Flat-Plate Solar Array (FSA) Project. The first of two technologies which are being developed within the FSA Project involves the conversion of metallurgical-grade silicon through a silane purification process to silicon particles. The second is concerned with the conversion of trichlorosilane to dichlorosilane, and the subsequent production of silicon using modified rod reactors of the Siemens type. With respect to silicon sheet preparation, efforts have been focused both on the preparation of ingots, followed by wafering, and the direct crystallization of molten silicon into a ribbon or film.

Tailorable stimulated Brillouin scattering in nanoscale silicon waveguides.

PubMed

Shin, Heedeuk; Qiu, Wenjun; Jarecki, Robert; Cox, Jonathan A; Olsson, Roy H; Starbuck, Andrew; Wang, Zheng; Rakich, Peter T

2013-01-01

Nanoscale modal confinement is known to radically enhance the effect of intrinsic Kerr and Raman nonlinearities within nanophotonic silicon waveguides. By contrast, stimulated Brillouin-scattering nonlinearities, which involve coherent coupling between guided photon and phonon modes, are stifled in conventional nanophotonics, preventing the realization of a host of Brillouin-based signal-processing technologies in silicon. Here we demonstrate stimulated Brillouin scattering in silicon waveguides, for the first time, through a new class of hybrid photonic-phononic waveguides. Tailorable travelling-wave forward-stimulated Brillouin scattering is realized-with over 1,000 times larger nonlinearity than reported in previous systems-yielding strong Brillouin coupling to phonons from 1 to 18 GHz. Experiments show that radiation pressures, produced by subwavelength modal confinement, yield enhancement of Brillouin nonlinearity beyond those of material nonlinearity alone. In addition, such enhanced and wideband coherent phonon emission paves the way towards the hybridization of silicon photonics, microelectromechanical systems and CMOS signal-processing technologies on chip.

Solar breeder: Energy payback time for silicon photovoltaic systems

NASA Technical Reports Server (NTRS)

Lindmayer, J.

1977-01-01

The energy expenditures of the prevailing manufacturing technology of terrestrial photovoltaic cells and panels were evaluated, including silicon reduction, silicon refinement, crystal growth, cell processing and panel building. Energy expenditures include direct energy, indirect energy, and energy in the form of equipment and overhead expenses. Payback times were development using a conventional solar cell as a test vehicle which allows for the comparison of its energy generating capability with the energies expended during the production process. It was found that the energy payback time for a typical solar panel produced by the prevailing technology is 6.4 years. Furthermore, this value drops to 3.8 years under more favorable conditions. Moreover, since the major energy use reductions in terrestrial manufacturing have occurred in cell processing, this payback time directly illustrates the areas where major future energy reductions can be made -- silicon refinement, crystal growth, and panel building.

Review of silicon photonics: history and recent advances

NASA Astrophysics Data System (ADS)

Ye, Winnie N.; Xiong, Yule

2013-09-01

Silicon photonics has attracted tremendous attention and research effort as a promising technology in optoelectronic integration for computing, communications, sensing, and solar harvesting. Mainly due to the combination of its excellent material properties and the complementary metal-oxide semiconductor (CMOS) fabrication processing technology, silicon has becoming the material choice for photonic and optoelectronic circuits with low cost, ultra-compact device footprint, and high-density integration. This review paper provides an overview on silicon photonics, by highlighting the early work from the mid-1980s on the fundamental building blocks such as silicon platforms and waveguides, and the main milestones that have been achieved so far in the field. A summary of reported work on functional elements in both passive and active devices, as well as the applications of the technology in interconnect, sensing, and solar cells, is identified.

Thin Carbon Layers on Nanostructured Silicon-Properties and Applications

NASA Astrophysics Data System (ADS)

Angelescu, Anca; Kleps, Irina; Miu, Mihaela; Simion, Monica; Bragaru, Adina; Petrescu, Stefana; Paduraru, Crina; Raducanu, Aurelia

Thin carbon layers such as silicon carbide (SiC) and diamond like carbon (DLC) layers on silicon, or on nanostructured silicon substrats were obtained by different methods. This paper is a review of our results in the areas of carbon layer microfabrication technologies and their properties related to different microsystem apllications. So, silicon membranes using a-SiC or DLC layers as etching mask, as well as silicon carbide membranes using a combined porous silicon — DLC structure were fabricated for sensor applications. A detailed evaluation of the field emission (FE) properties of these films was done to demonstrate their capability to be used in field emission devices. Carbon thin layers on nanostructured silicon samples were also investigated with respect to the living cell adhesion on these structures. The experiments indicate that the cell attachment on the surface of carbon coatings can be controlled by deposition parameters during the technological process.

Optimization of the silicon subcell for III-V on silicon multijunction solar cells: Key differences with conventional silicon technology

NASA Astrophysics Data System (ADS)

García-Tabarés, Elisa; Martín, Diego; García, Iván; Lelièvre, Jean François; Rey-Stolle, Ignacio

2012-10-01

Dual-junction solar cells formed by a GaAsP or GaInP top cell and a silicon (Si) bottom cell seem to be attractive candidates to materialize the long sought-for integration of III-V materials on Si for photovoltaic (PV) applications. Such integration would offer a cost breakthrough for PV technology, unifying the low cost of Si and the efficiency potential of III-V multijunction solar cells. The optimization of the Si solar cells properties in flat-plate PV technology is well-known; nevertheless, it has been proven that the behavior of Si substrates is different when processed in an MOVPE reactor In this study, we analyze several factors influencing the bottom subcell performance, namely, 1) the emitter formation as a result of phosphorus diffusion; 2) the passivation quality provided by the GaP nucleation layer; and 3) the process impact on the bottom subcell PV properties.

Summary of flat-plate solar array project documentation. Abstracts of published documents, 1975 to June 1982

NASA Technical Reports Server (NTRS)

1982-01-01

Technologies that will enable the private sector to manufacture and widely use photovoltaic systems for the generation of electricity in residential, commercial, industrial, and government applications at a cost per watt that is competitive with other means is investigated. Silicon refinement processes, advanced silicon sheet growth techniques, solar cell development, encapsulation, automated fabrication process technology, advanced module/array design, and module/array test and evaluation techniques are developed.

Development and Characterization of the Bonding and Integration Technologies Needed for Fabricating Silicon Carbide Based Injector Components

NASA Technical Reports Server (NTRS)

Halbig,Michael C.; Singh, Mrityunjay

2008-01-01

Advanced ceramic bonding and integration technologies play a critical role in the fabrication and application of silicon carbide based components for a number of aerospace and ground based applications. One such application is a lean direct injector for a turbine engine to achieve low NOx emissions. Ceramic to ceramic diffusion bonding and ceramic to metal brazing technologies are being developed for this injector application. For the diffusion bonding technology, titanium interlayers (coatings and foils) were used to aid in the joining of silicon carbide (SiC) substrates. The influence of such variables as surface finish, interlayer thickness, and processing time were investigated. Electron microprobe analysis was used to identify the reaction formed phases. In the diffusion bonds, an intermediate phase, Ti5Si3Cx, formed that is thermally incompatible in its thermal expansion and caused thermal stresses and cracking during the processing cool-down. Thinner interlayers of pure titanium and/or longer processing times resulted in an optimized microstructure. Tensile tests on the joined materials resulted in strengths of 13-28 MPa depending on the SiC substrate material. Nondestructive evaluation using ultrasonic immersion showed well formed bonds. For the joining technology of brazing Kovar fuel tubes to silicon carbide, preliminary development of the joining approach has begun. Various technical issues and requirements for the injector application are addressed.

A cochlear implant fabricated using a bulk silicon-surface micromachining process

NASA Astrophysics Data System (ADS)

Bell, Tracy Elizabeth

1999-11-01

This dissertation presents the design and fabrication of two generations of a silicon microelectrode array for use in a cochlear implant. A cochlear implant is a device that is inserted into the inner ear and uses electrical stimulation to provide sound sensations to the profoundly deaf. The first-generation silicon cochlear implant is a passive device fabricated using silicon microprobe technology developed at the University of Michigan. It contains twenty-two iridium oxide (IrO) stimulating sites that are 250 mum in diameter and spaced at 750 mum intervals. In-vivo recordings were made in guinea pig auditory cortex in response to electrical stimulation with this device, verifying its ability to electrically evoke an auditory response. Auditory thresholds as low as 78 muA were recorded. The second-generation implant is a thirty-two site, four-channel device with on-chip CMOS site-selection circuitry and integrated position sensing. It was fabricated using a novel bulk silicon surface micromachining process which was developed as a part of this dissertation work. While the use of semiconductor technology offers many advantages in fabricating cochlear implants over the methods currently used, it was felt that even further advantages could be gained by developing a new micromachining process which would allow circuitry to be distributed along the full length of the cochlear implant substrate. The new process uses electropolishing of an n+ bulk silicon sacrificial layer to undercut and release n- epitaxial silicon structures from the wafer. An extremely abrupt etch-stop between the n+ and n- silicon is obtained, with no electropolishing taking place in the n-type silicon that is doped lower than 1 x 1017 cm-3 in concentration. Lateral electropolishing rates of up to 50 mum/min were measured using this technique, allowing one millimeter-wide structures to be fully undercut in as little as 10 minutes. The new micromachining process was integrated with a standard p-well CMOS integrated circuit process to fabricate the second-generation active silicon cochlear implants.

Porous silicon technology for integrated microsystems

NASA Astrophysics Data System (ADS)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially rough surface on the porous silicon sample without introducing significant thermal stress. (Abstract shortened by UMI.)

Flat-plate solar array project. Volume 2: Silicon material

NASA Technical Reports Server (NTRS)

Lutwack, R.

1986-01-01

The goal of the Silicon Material Task, a part of the Flat Plate Solar Array (FSA) Project, was to develop and demonstate the technology for the low cost production of silicon of suitable purity to be used as the basic material for the manufacture of terrestrial photovoltaic solar cells. Summarized are 11 different processes for the production of silicon that were investigated and developed to varying extent by industrial, university, and Government researchers. The silane production section of the Union Carbide Corp. (UCC) silane process was developed completely in this program. Coupled with Siemens-type chemical vapor deposition reactors, the process was carried through the pilot stage. The overall UCC process involves the conversion of metallurgical-grade silicon to silane followed by decomposition of the silane to purified silicon. The other process developments are described to varying extents. Studies are reported on the effects of impurities in silicon on both silicon-material properties and on solar cell performance. These studies on the effects of impurities yielded extensive information and models for relating specific elemental concentrations to levels of deleterious effects.

Flat-plate solar array project. Volume 2: Silicon material

NASA Astrophysics Data System (ADS)

Lutwack, R.

1986-10-01

The goal of the Silicon Material Task, a part of the Flat Plate Solar Array (FSA) Project, was to develop and demonstate the technology for the low cost production of silicon of suitable purity to be used as the basic material for the manufacture of terrestrial photovoltaic solar cells. Summarized are 11 different processes for the production of silicon that were investigated and developed to varying extent by industrial, university, and Government researchers. The silane production section of the Union Carbide Corp. (UCC) silane process was developed completely in this program. Coupled with Siemens-type chemical vapor deposition reactors, the process was carried through the pilot stage. The overall UCC process involves the conversion of metallurgical-grade silicon to silane followed by decomposition of the silane to purified silicon. The other process developments are described to varying extents. Studies are reported on the effects of impurities in silicon on both silicon-material properties and on solar cell performance. These studies on the effects of impurities yielded extensive information and models for relating specific elemental concentrations to levels of deleterious effects.

Development of a Process for a High Capacity Arc Heater Production of Silicon for Solar Arrays

NASA Technical Reports Server (NTRS)

Reed, W. H.

1979-01-01

A program was established to develop a high temperature silicon production process using existing electric arc heater technology. Silicon tetrachloride and a reductant (sodium) are injected into an arc heated mixture of hydrogen and argon. Under these high temperature conditions, a very rapid reaction is expected to occur and proceed essentially to completion, yielding silicon and gaseous sodium chloride. Techniques for high temperature separation and collection were developed. Included in this report are: test system preparation; testing; injection techniques; kinetics; reaction demonstration; conclusions; and the project status.

Novel Bonding Technology for Hermetically Sealed Silicon Micropackage

NASA Astrophysics Data System (ADS)

Lee, Duck-Jung; Ju, Byeong-Kwon; Choi, Woo-Beom; Jeong, Jee-Won; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1999-01-01

We performed glass-to-silicon bonding and fabricated a hermetically sealed silicon wafer using silicon direct bonding followed by anodic bonding (SDAB). The hydrophilized glass and silicon wafers in solution were dried and initially bonded in atmosphere as in the silicon direct bonding (SDB) process, but annealing at high temperature was not performed. Anodic bonding was subsequently carried out for the initially bonded specimens. Then the wafer pairs bonded by the SDAB method were different from those bonded by the anodic bonding process only. The effects of the bonding process on the bonded area and tensile strength were investigated as functions of bonding temperature and voltage. Using scanning electron microscopy (SEM), the cross-sectional view of the bonded interface region was observed. In order to investigate the migration of the sodium ions in the bonding process, the concentration of the bonded glass was compared with that of standard glass. The specimen bonded using the SDAB process had higher efficiency than that using the anodic bonding process only.

Research and preparation of ultra purity silicon tetrachloride

NASA Astrophysics Data System (ADS)

Wan, Ye; Zhao, Xiong; Yan, Dazhou; Yang, Dian; Li, Yunhao; Guo, Shuhu

2017-10-01

This article demonstrated a technology for producing ultra-purity silicon tetrachloride, which using the high purity SiCl4 as raw material through the method of combination ray reaction with purification. This technology could remove metal impurities and compounds impurities contained hydrogen effectively. The purity of product prepared by this technology can reach at 99.9999%, content of metal impurities can be low at 0.3PPb, meeting the requirement of industry easily. This technology has the advantages of simple process, continuous operation, and stable performance.

Tailorable stimulated Brillouin scattering in nanoscale silicon waveguides

PubMed Central

Shin, Heedeuk; Qiu, Wenjun; Jarecki, Robert; Cox, Jonathan A.; Olsson, Roy H.; Starbuck, Andrew; Wang, Zheng; Rakich, Peter T.

2013-01-01

Nanoscale modal confinement is known to radically enhance the effect of intrinsic Kerr and Raman nonlinearities within nanophotonic silicon waveguides. By contrast, stimulated Brillouin-scattering nonlinearities, which involve coherent coupling between guided photon and phonon modes, are stifled in conventional nanophotonics, preventing the realization of a host of Brillouin-based signal-processing technologies in silicon. Here we demonstrate stimulated Brillouin scattering in silicon waveguides, for the first time, through a new class of hybrid photonic–phononic waveguides. Tailorable travelling-wave forward-stimulated Brillouin scattering is realized—with over 1,000 times larger nonlinearity than reported in previous systems—yielding strong Brillouin coupling to phonons from 1 to 18 GHz. Experiments show that radiation pressures, produced by subwavelength modal confinement, yield enhancement of Brillouin nonlinearity beyond those of material nonlinearity alone. In addition, such enhanced and wideband coherent phonon emission paves the way towards the hybridization of silicon photonics, microelectromechanical systems and CMOS signal-processing technologies on chip. PMID:23739586

IEEE Photovoltaic Specialists Conference, 20th, Las Vegas, NV, Sept. 26-30, 1988, Conference Record. Volumes 1 & 2

NASA Astrophysics Data System (ADS)

Various papers on photovoltaics are presented. The general topics considered include: amorphous materials and cells; amorphous silicon-based solar cells and modules; amorphous silicon-based materials and processes; amorphous materials characterization; amorphous silicon; high-efficiency single crystal solar cells; multijunction and heterojunction cells; high-efficiency III-V cells; modeling and characterization of high-efficiency cells; LIPS flight experience; space mission requirements and technology; advanced space solar cell technology; space environmental effects and modeling; space solar cell and array technology; terrestrial systems and array technology; terrestrial utility and stand-alone applications and testing; terrestrial concentrator and storage technology; terrestrial stand-alone systems applications; terrestrial systems test and evaluation; terrestrial flatplate and concentrator technology; use of polycrystalline materials; polycrystalline II-VI compound solar cells; analysis of and fabrication procedures for compound solar cells.

Low cost silicon solar array project silicon materials task

NASA Technical Reports Server (NTRS)

1977-01-01

A program was established to develop a high temperature silicon production process using existing electric arc heater technology. Silicon tetrachloride and a reductant will be injected into an arc heated mixture of hydrogen and argon. Under these high temperature conditions, a very rapid reaction is expected to occur and proceed essentially to completion, yielding silicon and gaseous sodium chloride. Techniques for high temperature separation and collection of the molten silicon will be developed using standard engineering approaches, and the salt vapor will later be electrolytically separated into its elemental constituents for recycle. Preliminary technical evaluations and economic projections indicate not only that this process appears to be feasible, but that it also has the advantages of rapid, high capacity production of good quality molten silicon at a nominal cost.

Automated aray assembly, phase 2

NASA Technical Reports Server (NTRS)

Daiello, R. V.

1979-01-01

A manufacturing process suitable for the large-scale production of silicon solar array modules at a cost of less than $500/peak kW is described. Factors which control the efficiency of ion implanted silicon solar cells, screen-printed thick film metallization, spray-on antireflection coating process, and panel assembly are discussed. Conclusions regarding technological readiness or cost effectiveness of individual process steps are presented.

Low Cost Solar Array Project. Feasibility of the silane process for producing semiconductor-grade silicon. Final report, October 1975-March 1979

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

1979-06-01

The commercial production of low-cost semiconductor-grade silicon is an essential requirement of the JPL/DOE (Department of Energy) Low-Cost Solar Array (LSA) Project. A 1000-metric-ton-per-year commercial facility using the Union Carbide Silane Process will produce molten silicon for an estimated price of $7.56/kg (1975 dollars, private financing), meeting the DOE goal of less than $10/kg. Conclusions and technology status are reported for both contract phases, which had the following objectives: (1) establish the feasibility of Union Carbide's Silane Process for commercial application, and (2) develop an integrated process design for an Experimental Process System Development Unit (EPSDU) and a commercial facility,more » and estimate the corresponding commercial plant economic performance. To assemble the facility design, the following work was performed: (a) collection of Union Carbide's applicable background technology; (b) design, assembly, and operation of a small integrated silane-producing Process Development Unit (PDU); (c) analysis, testing, and comparison of two high-temperature methods for converting pure silane to silicon metal; and (d) determination of chemical reaction equilibria and kinetics, and vapor-liquid equilibria for chlorosilanes.« less

18th Workshop on Crystalline Silicon Solar Cells and Modules: Materials and Processes; Workshop Proceedings, 3-6 August 2008, Vail, Colorado

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, B. L.

2008-09-01

The National Center for Photovoltaics sponsored the 18th Workshop on Crystalline Silicon Solar Cells & Modules: Materials and Processes, held in Vail, CO, August 3-6, 2008. This meeting provided a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and relevant non-photovoltaic fields. The theme of this year's meeting was 'New Directions for Rapidly Growing Silicon Technologies.'

Energy requirement for the production of silicon solar arrays

NASA Technical Reports Server (NTRS)

Lindmayer, J.; Wihl, M.; Scheinine, A.; Morrison, A.

1977-01-01

An assessment of potential changes and alternative technologies which could impact the photovoltaic manufacturing process is presented. Topics discussed include: a multiple wire saw, ribbon growth techniques, silicon casting, and a computer model for a large-scale solar power plant. Emphasis is placed on reducing the energy demands of the manufacturing process.

Recent progress in high-output-voltage silicon solar cells

NASA Technical Reports Server (NTRS)

Muelenberg, A.; Arndt, R. A.; Allison, J. F.; Weizer, V.

1980-01-01

The status of the technology associated with the development of high output voltage silicon solar cells is reported. The energy conversion efficiency of a double diffusion process is compared to that of a single diffusion process. The efficiency of a 0.1 ohm/cm solar cell is characterized both before and after covering.

Evolutionary process development towards next generation crystalline silicon solar cells : a semiconductor process toolbox application

NASA Astrophysics Data System (ADS)

John, J.; Prajapati, V.; Vermang, B.; Lorenz, A.; Allebe, C.; Rothschild, A.; Tous, L.; Uruena, A.; Baert, K.; Poortmans, J.

2012-08-01

Bulk crystalline Silicon solar cells are covering more than 85% of the world's roof top module installation in 2010. With a growth rate of over 30% in the last 10 years this technology remains the working horse of solar cell industry. The full Aluminum back-side field (Al BSF) technology has been developed in the 90's and provides a production learning curve on module price of constant 20% in average. The main reason for the decrease of module prices with increasing production capacity is due to the effect of up scaling industrial production. For further decreasing of the price per wattpeak silicon consumption has to be reduced and efficiency has to be improved. In this paper we describe a successive efficiency improving process development starting from the existing full Al BSF cell concept. We propose an evolutionary development includes all parts of the solar cell process: optical enhancement (texturing, polishing, anti-reflection coating), junction formation and contacting. Novel processes are benchmarked on industrial like baseline flows using high-efficiency cell concepts like i-PERC (Passivated Emitter and Rear Cell). While the full Al BSF crystalline silicon solar cell technology provides efficiencies of up to 18% (on cz-Si) in production, we are achieving up to 19.4% conversion efficiency for industrial fabricated, large area solar cells with copper based front side metallization and local Al BSF applying the semiconductor toolbox.

Laser Integration on Silicon Photonic Circuits Through Transfer Printing

DTIC Science & Technology

2017-03-10

AFRL-AFOSR-UK-TR-2017-0019 Laser integration on silicon photonic circuits through transfer printing Gunther Roelkens UNIVERSITEIT GENT VZW Final...TYPE Final 3. DATES COVERED (From - To) 15 Sep 2015 to 14 Sep 2016 4. TITLE AND SUBTITLE Laser integration on silicon photonic circuits through...parallel integration of III-V lasers on silicon photonic integrated circuits. The report discusses the technological process that has been developed as

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

PubMed

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

Development of Si(1-x)Ge(x) technology for microwave sensing applications

NASA Technical Reports Server (NTRS)

Mena, Rafael A.; Taub, Susan R.; Alterovitz, Samuel A.; Young, Paul E.; Simons, Rainee N.; Rosenfeld, David

1993-01-01

The progress for the first year of the work done under the Director's Discretionary Fund (DDF) research project entitled, 'Development of Si(1-x)Ge(x) Technology for Microwave Sensing Applications.' This project includes basic material characterization studies of silicon-germanium (SiGe), device processing on both silicon (Si) and SiGe substrates, and microwave characterization of transmission lines on silicon substrates. The material characterization studies consisted of ellipsometric and magneto-transport measurements and theoretical calculations of the SiGe band-structure. The device fabrication efforts consisted of establishing SiGe device processing capabilities in the Lewis cleanroom. The characterization of microwave transmission lines included studying the losses of various coplanar transmission lines and the development of transitions on silicon. Each part of the project is discussed individually and the findings for each part are presented. Future directions are also discussed.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications - SiC, GaN, Ga2O3, and Diamond.

PubMed

Wellmann, Peter J

2017-11-17

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications – SiC, GaN, Ga2O3, and Diamond

PubMed Central

2017-01-01

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies. PMID:29200530

Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process

DOEpatents

McKee, Rodney A.; Walker, Frederick J.

1993-01-01

A process and structure involving a silicon substrate utilizes an ultra high vacuum and molecular beam epitaxy (MBE) methods to grow an epitaxial oxide film upon a surface of the substrate. As the film is grown, the lattice of the compound formed at the silicon interface becomes stabilized, and a base layer comprised of an oxide having a sodium chloride-type lattice structure grows epitaxially upon the compound so as to cover the substrate surface. A perovskite may then be grown epitaxially upon the base layer to render a product which incorporates silicon, with its electronic capabilities, with a perovskite having technologically-significant properties of its own.

Silicon pore optics for the international x-ray observatory

NASA Astrophysics Data System (ADS)

Wille, E.; Wallace, K.; Bavdaz, M.; Collon, M. J.; Günther, R.; Ackermann, M.; Beijersbergen, M. W.; Riekerink, M. O.; Blom, M.; Lansdorp, B.; de Vreede, L.

2017-11-01

Lightweight X-ray Wolter optics with a high angular resolution will enable the next generation of X-ray telescopes in space. The International X-ray Observatory (IXO) requires a mirror assembly of 3 m2 effective area (at 1.5 keV) and an angular resolution of 5 arcsec. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor industry. We present the manufacturing process ranging from single mirror plates towards complete focusing mirror modules mounted in flight configuration. The performance of the mirror modules is tested using X-ray pencil beams or full X-ray illumination. In 2009, an angular resolution of 9 arcsec was achieved, demonstrating the improvement of the technology compared to 17 arcsec in 2007. Further development activities of Silicon Pore Optics concentrate on ruggedizing the mounting system and performing environmental tests, integrating baffles into the mirror modules and assessing the mass production.

A novel multi-level IC-compatible surface microfabrication technology for MEMS with independently controlled lateral and vertical submicron transduction gaps

NASA Astrophysics Data System (ADS)

Cicek, Paul-Vahe; Elsayed, Mohannad; Nabki, Frederic; El-Gamal, Mourad

2017-11-01

An above-IC compatible multi-level MEMS surface microfabrication technology based on a silicon carbide structural layer is presented. The fabrication process flow provides optimal electrostatic transduction by allowing the creation of independently controlled submicron vertical and lateral gaps without the need for high resolution lithography. Adopting silicon carbide as the structural material, the technology ensures material, chemical and thermal compatibility with modern semiconductor nodes, reporting the lowest peak processing temperature (i.e. 200 °C) of all comparable works. This makes this process ideally suited for integrating capacitive-based MEMS directly above standard CMOS substrates. Process flow design and optimization are presented in the context of bulk-mode disk resonators, devices that are shown to exhibit improved performance with respect to previous generation flexural beam resonators, and that represent relatively complex MEMS structures. The impact of impending improvements to the fabrication technology is discussed.

Fabrication of porous silicon nitride ceramics using binder jetting technology

NASA Astrophysics Data System (ADS)

Rabinskiy, L.; Ripetsky, A.; Sitnikov, S.; Solyaev, Y.; Kahramanov, R.

2016-07-01

This paper presents the results of the binder jetting technology application for the processing of the Si3N4-based ceramics. The difference of the developed technology from analogues used for additive manufacturing of silicon nitride ceramics is a method of the separate deposition of the mineral powder and binder without direct injection of suspensions/slurries. It is assumed that such approach allows reducing the technology complexity and simplifying the process of the feedstock preparation, including the simplification of the composite materials production. The binders based on methyl ester of acrylic acid with polyurethane and modified starch were studied. At this stage of the investigations, the technology of green body's fabrication is implemented using a standard HP cartridge mounted on the robotic arm. For the coordinated operation of the cartridge and robot the specially developed software was used. Obtained green bodies of silicon powder were used to produce the ceramic samples via reaction sintering. The results of study of ceramics samples microstructure and composition are presented. Sintered ceramics are characterized by fibrous α-Si3N4 structure and porosity up to 70%.

Automated array assembly task, phase 1

NASA Technical Reports Server (NTRS)

Carbajal, B. G.

1977-01-01

An assessment of state-of-the-art technologies that are applicable to silicon solar cell and solar cell module fabrication is provided. The assessment consists of a technical feasibility evaluation and a cost projection for high-volume production of silicon solar cell modules. The cost projection was approached from two directions; a design-to-cost analysis assigned cost goals to each major process element in the fabrication scheme, and a cost analysis built up projected costs for alternate technologies for each process element. A technical evaluation was used in combination with the cost analysis to identify a baseline low cost process. A novel approach to metal pattern design based on minimum power loss was developed. These design equations were used as a tool in the evaluation of metallization technologies.

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1983-01-01

The feasibility of making non-volatile digital memory devices of barium titanate, BaTiO3, that are integrated onto a silicon substrate with the required ferroelectric film produced by processing, compatible with silicon technology was examined.

Advanced detectors and signal processing for bubble memories

NASA Technical Reports Server (NTRS)

Kryder, M. H.; Rasky, P. H. L.; Greve, D. W.

1985-01-01

The feasibility of combining silicon and magnetic bubble technologies is demonstrated. Results of bubble film annealing indicate that a low temperature silicon on garnet technology is the most likely one to succeed commercially. Annealing ambients are also shown to have a major effect on the magnetic properties of bubble films. Functional MOSFETs were fabricated on bubble films coated with thick (approximately 1 micron) SiO2 layers. The two main problems with these silicon on garnet MOSFETs are low electron mobilities and large gate leakage currents. Results indicate that the laser recrystallized silicon and gate oxide (SiO2) layers are contaminated. The data suggest that part of the contaminating ions originate in the sputtered oxide spacer layer and part originates in the bubble film itself. A diffusion barrier, such as silicon nitride, placed between the bubble film and the silicon layer should eliminate the contamination induced problem.

Highly Manufacturable Deep (Sub-Millimeter) Etching Enabled High Aspect Ratio Complex Geometry Lego-Like Silicon Electronics.

PubMed

Ghoneim, Mohamed Tarek; Hussain, Muhammad Mustafa

2017-04-01

A highly manufacturable deep reactive ion etching based process involving a hybrid soft/hard mask process technology shows high aspect ratio complex geometry Lego-like silicon electronics formation enabling free-form (physically flexible, stretchable, and reconfigurable) electronic systems. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Development of a process for high capacity arc heater production of silicon for solar arrays

NASA Technical Reports Server (NTRS)

Meyer, T. N.

1980-01-01

A high temperature silicon production process using existing electric arc heater technology is discussed. Silicon tetrachloride and a reductant, liquid sodium, were injected into an arc heated mixture of hydrogen and argon. Under these high temperature conditions, a very rapid reaction occurred, yielding silicon and gaseous sodium chloride. Techniques for high temperature separation and collection of the molten silicon were developed. The desired degree of separation was not achieved. The electrical, control and instrumentation, cooling water, gas, SiCl4, and sodium systems are discussed. The plasma reactor, silicon collection, effluent disposal, the gas burnoff stack, and decontamination and safety are also discussed. Procedure manuals, shakedown testing, data acquisition and analysis, product characterization, disassembly and decontamination, and component evaluation are reviewed.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

2013-05-01

Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

Silicon production process evaluations

NASA Technical Reports Server (NTRS)

1982-01-01

Chemical engineering analyses involving the preliminary process design of a plant (1,000 metric tons/year capacity) to produce silicon via the technology under consideration were accomplished. Major activities in the chemical engineering analyses included base case conditions, reaction chemistry, process flowsheet, material balance, energy balance, property data, equipment design, major equipment list, production labor and forward for economic analysis. The process design package provided detailed data for raw materials, utilities, major process equipment and production labor requirements necessary for polysilicon production in each process.

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Optofluidic encapsulation and manipulation of silicon microchips using image processing based optofluidic maskless lithography and railed microfluidics.

PubMed

Chung, Su Eun; Lee, Seung Ah; Kim, Jiyun; Kwon, Sunghoon

2009-10-07

We demonstrate optofluidic encapsulation of silicon microchips using image processing based optofluidic maskless lithography and manipulation using railed microfluidics. Optofluidic maskless lithography is a dynamic photopolymerization technique of free-floating microstructures within a fluidic channel using spatial light modulator. Using optofluidic maskless lithography via computer-vision aided image processing, polymer encapsulants are fabricated for chip protection and guiding-fins for efficient chip conveying within a fluidic channel. Encapsulated silicon chips with guiding-fins are assembled using railed microfluidics, which is an efficient guiding and heterogeneous self-assembly system of microcomponents. With our technology, externally fabricated silicon microchips are encapsulated, fluidically guided and self-assembled potentially enabling low cost fluidic manipulation and assembly of integrated circuits.

From Bell Labs to Silicon Valley: A Saga of Technology Transfer, 1954-1961

NASA Astrophysics Data System (ADS)

Riordan, Michael

2009-03-01

Although Bell Telephone Laboratories invented the transistor and developed most of the associated semiconductor technology, the integrated circuit or microchip emerged elsewhere--at Texas Instruments and Fairchild Semiconductor Company. I recount how the silicon technology required to make microchips possible was first developed at Bell Labs in the mid-1950s. Much of it reached the San Francisco Bay Area when transistor pioneer William Shockley left Bell Labs in 1955 to establish the Shockley Semiconductor Laboratory in Mountain View, hiring a team of engineers and scientists to develop and manufacture transistors and related semiconductor devices. But eight of them--including Gordon Moore and Robert Noyce, eventually the co-founders of Intel--resigned en masse in September 1957 to start Fairchild, bringing with them the scientific and technological expertise they had acquired and further developed at Shockley's firm. This event marked the birth of Silicon Valley, both technologically and culturally. By March 1961 the company was marketing its Micrologic integrated circuits, the first commercial silicon microchips, based on the planar processing technique developed at Fairchild by Jean Hoerni.

Monolithically interconnected silicon-film™ module technology

NASA Astrophysics Data System (ADS)

DelleDonne, E. J.; Ford, D. H.; Hall, R. B.; Ingram, A. E.; Rand, J. A.; Barnett, A. M.

1999-03-01

AstroPower is developing an advanced thin-silicon-based, photovoltaic module product. A low-cost monolithic interconnected device is being integrated into a module that combines the design and process features of advanced light trapped, thin-silicon solar cells. This advanced product incorporates a low-cost substrate, a nominally 50-μm thick grown silicon layer with minority carrier diffusion lengths exceeding the active layer thickness, light trapping due to back-surface reflection, and back-surface passivation. The thin silicon layer enables high solar cell performance and can lead to a module conversion efficiency as high as 19%. These performance design features, combined with low-cost manufacturing using relatively low-cost capital equipment, continuous processing and a low-cost substrate, will lead to high-performance, low-cost photovoltaic panels.

Direct Growth of Graphene on Silicon by Metal-Free Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Tai, Lixuan; Zhu, Daming; Liu, Xing; Yang, Tieying; Wang, Lei; Wang, Rui; Jiang, Sheng; Chen, Zhenhua; Xu, Zhongmin; Li, Xiaolong

2018-06-01

The metal-free synthesis of graphene on single-crystal silicon substrates, the most common commercial semiconductor, is of paramount significance for many technological applications. In this work, we report the growth of graphene directly on an upside-down placed, single-crystal silicon substrate using metal-free, ambient-pressure chemical vapor deposition. By controlling the growth temperature, in-plane propagation, edge-propagation, and core-propagation, the process of graphene growth on silicon can be identified. This process produces atomically flat monolayer or bilayer graphene domains, concave bilayer graphene domains, and bulging few-layer graphene domains. This work would be a significant step toward the synthesis of large-area and layer-controlled, high-quality graphene on single-crystal silicon substrates. [Figure not available: see fulltext.

Sensitivity analysis of add-on price estimate for select silicon wafering technologies

NASA Technical Reports Server (NTRS)

Mokashi, A. R.

1982-01-01

The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

Recent progress in terrestrial photovoltaic collector technology

NASA Technical Reports Server (NTRS)

Ferber, R. R.

1982-01-01

The U.S. Photovoltaic Research and Development Program has the objective to develop the technology necessary to foster widespread grid-competitive electric power generation by the late 1980s. The flat-plate and the concentrator collector activities form the nucleus of the program. The project is concerned with the refining of silicon, silicon sheet production, solar cell processing and fabrication, encapsulation materials development, and collector design and production. The Large-Area Silicon Sheet Task has the objective to develop and demonstrate the feasibility of several methods for producing large area silicon sheet material suitable for fabricating low-cost, high-efficiency solar cells. It is expected that a variety of economic flat-plate and concentrator collectors will become commercially available for grid-connected applications.

Open Air Silicon Deposition by Atmospheric Pressure Plasma under Local Ambient Gas Control

NASA Astrophysics Data System (ADS)

Naito, Teruki; Konno, Nobuaki; Yoshida, Yukihisa

2015-09-01

In this paper, we report open air silicon (Si) deposition by combining a silane free Si deposition technology and a newly developed local ambient gas control technology. Recently, material processing in open air has been investigated intensively. While a variety of materials have been deposited, there were only few reports on Si deposition due to the susceptibility to contamination and the hazardous nature of source materials. Since Si deposition is one of the most important processes in device fabrication, we have developed open air silicon deposition technologies in BEANS project. For a clean and safe process, a local ambient gas control head was designed. Process gas leakage was prevented by local evacuation, and air contamination was shut out by inert curtain gas. By numerical and experimental investigations, a safe and clean process condition with air contamination less than 10 ppm was achieved. Si film was deposited in open air by atmospheric pressure plasma enhanced chemical transport under the local ambient gas control. The film was microcrystalline Si with the crystallite size of 17 nm, and the Hall mobility was 2.3 cm2/V .s. These properties were comparable to those of Si films deposited in a vacuum chamber. This research has been conducted as one of the research items of New Energy and Industrial Technology Development Organization ``BEANS'' project.

Development of silicon growth techniques from melt with surface heating

NASA Astrophysics Data System (ADS)

Kravtsov, Anatoly

2018-05-01

The paper contains literary and personal data on the development history of silicon-growing technology with volumetric and surface melt heating. It discusses the advantages and disadvantages of surface-heating technology. Examples are given of the implementation of such processes in the 60s-70s of the last century, and the reasons for the discontinuation of the relevant work. It describes the main solutions for the implementation of crystal growth process with the electron-beam heating of the melt surface, implemented by KEPP EU (Latvia). It discusses differences in the management of the growth process for the crystals with constant diameters compared to the Czochralski method. It lists geometrical and electro-physical properties of the obtained crystals. It describes the possible use of such crystals and the immediate challenges of technology development.

Bonding and Integration Technologies for Silicon Carbide Based Injector Components

NASA Technical Reports Server (NTRS)

Halbig, Michael C.; Singh, Mrityunjay

2008-01-01

Advanced ceramic bonding and integration technologies play a critical role in the fabrication and application of silicon carbide based components for a number of aerospace and ground based applications. One such application is a lean direct injector for a turbine engine to achieve low NOx emissions. Ceramic to ceramic diffusion bonding and ceramic to metal brazing technologies are being developed for this injector application. For the diffusion bonding, titanium interlayers (PVD and foils) were used to aid in the joining of silicon carbide (SiC) substrates. The influence of such variables as surface finish, interlayer thickness (10, 20, and 50 microns), processing time and temperature, and cooling rates were investigated. Microprobe analysis was used to identify the phases in the bonded region. For bonds that were not fully reacted an intermediate phase, Ti5Si3Cx, formed that is thermally incompatible in its thermal expansion and caused thermal stresses and cracking during the processing cool-down. Thinner titanium interlayers and/or longer processing times resulted in stable and compatible phases that did not contribute to microcracking and resulted in an optimized microstructure. Tensile tests on the joined materials resulted in strengths of 13-28 MPa depending on the SiC substrate material. Non-destructive evaluation using ultrasonic immersion showed well formed bonds. For the joining technology of brazing Kovar fuel tubes to silicon carbide, preliminary development of the joining approach has begun. Various technical issues and requirements for the injector application are addressed.

Silicon production in a fluidized bed reactor

NASA Technical Reports Server (NTRS)

Rohatgi, N. K.

1986-01-01

Part of the development effort of the JPL in-house technology involved in the Flat-Plate Solar Array (FSA) Project was the investigation of a low-cost process to produce semiconductor-grade silicon for terrestrial photovoltaic cell applications. The process selected was based on pyrolysis of silane in a fluidized-bed reactor (FBR). Following initial investigations involving 1- and 2-in. diameter reactors, a 6-in. diameter, engineering-scale FBR was constructed to establish reactor performance, mechanism of silicon deposition, product morphology, and product purity. The overall mass balance for all experiments indicates that more than 90% of the total silicon fed into the reactor is deposited on silicon seed particles and the remaining 10% becomes elutriated fines. Silicon production rates were demonstrated of 1.5 kg/h at 30% silane concentration and 3.5 kg/h at 80% silane concentration. The mechanism of silicon deposition is described by a six-path process: heterogeneous deposition, homogeneous decomposition, coalescence, coagulation, scavenging, and heterogeneous growth on fines. The bulk of the growth silicon layer appears to be made up of small diameter particles. This product morphology lends support to the concept of the scavenging of homogeneously nucleated silicon.

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Water Splitting Using Porous Silicon Photo-electrodes for Hydrogen Production

NASA Astrophysics Data System (ADS)

Ali, M.; Starkov, V. V.; Gosteva, E. A.; Druzhinin, A. V.; Sattar, S.

2017-11-01

This paper presents the efficiency study results of using gradient-porous silicon structures with different morphology, as photo-anodes for photo-electrochemical dissociation of water. The results of a study of the physicochemical properties of gradient-porous silicon structures show the relatively low cost and simplicity of the technological process, as well as the possibility of forming structures with predefined properties, allow the creation of effective devices for artificial photosynthesis based on porous silicon for subsequent use in hydrogen energy.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip

PubMed Central

Schuck, C.; Guo, X.; Fan, L.; Ma, X.; Poot, M.; Tang, H. X.

2016-01-01

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips. PMID:26792424

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, B.

The 11th Workshop will provide a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and non-photovoltaic fields. Discussions will include the various aspects of impurities and defects in silicon--their properties, the dynamics during device processing, and their application for developing low-cost processes for manufacturing high-efficiency silicon solar cells. Sessions and panel discussions will review impurities and defects in crystalline-silicon PV, advanced cell structures, new processes and process characterization techniques, and future manufacturing demands. The workshop will emphasize some of the promising new technologies in Si solar cell fabrication that can lower PVmore » energy costs and meet the throughput demands of the future. The three-day workshop will consist of presentations by invited speakers, followed by discussion sessions. Topics to be discussed are: Si Mechanical properties and Wafer Handling, Advanced Topics in PV Fundamentals, Gettering and Passivation, Impurities and Defects, Advanced Emitters, Crystalline Silicon Growth, and Solar Cell Processing. The workshop will also include presentations by NREL subcontractors who will review the highlights of their research during the current subcontract period. In addition, there will be two poster sessions presenting the latest research and development results. Some presentations will address recent technologies in the microelectronics field that may have a direct bearing on PV.« less

Solar silicon via improved and expanded metallurgical silicon technology

NASA Technical Reports Server (NTRS)

Hunt, L. P.; Dosaj, V. D.; Mccormick, J. R.

1977-01-01

A completed preliminary survey of silica sources indicates that sufficient quantities of high-purity quartz are available in the U.S. and Canada to meet goals. Supply can easily meet demand for this little-sought commodity. Charcoal, as a reductant for silica, can be purified to a sufficient level by high-temperature fluorocarbon treatment and vacuum processing. High-temperature treatment causes partial graphitization which can lead to difficulty in smelting. Smelting of Arkansas quartz and purified charcoal produced kilogram quantities of silicon having impurity levels generally much lower than in MG-Si. Half of the goal was met of increasing the boron resistivity from 0.03 ohm-cm in metallurgical silicon to 0.3 ohm-cm in solar silicon. A cost analysis of the solidification process indicate $3.50-7.25/kg Si for the Czochralski-type process and $1.50-4.25/kg Si for the Bridgman-type technique.

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

PubMed

Shen, Wen-Wei; Chen, Kuan-Neng

2017-12-01

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Rapid Prototyping Technology for Manufacturing GTE Turbine Blades

NASA Astrophysics Data System (ADS)

Balyakin, A. V.; Dobryshkina, E. M.; Vdovin, R. A.; Alekseev, V. P.

2018-03-01

The conventional approach to manufacturing turbine blades by investment casting is expensive and time-consuming, as it takes a lot of time to make geometrically precise and complex wax patterns. Turbine blade manufacturing in pilot production can be sped up by accelerating the casting process while keeping the geometric precision of the final product. This paper compares the rapid prototyping method (casting the wax pattern composition into elastic silicone molds) to the conventional technology. Analysis of the size precision of blade casts shows that silicon-mold casting features sufficient geometric precision. Thus, this method for making wax patterns can be a cost-efficient solution for small-batch or pilot production of turbine blades for gas-turbine units (GTU) and gas-turbine engines (GTE). The paper demonstrates how additive technology and thermographic analysis can speed up the cooling of wax patterns in silicone molds. This is possible at an optimal temperature and solidification time, which make the process more cost-efficient while keeping the geometric quality of the final product.

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology.

PubMed

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-12-03

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm(2), and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p(+-)n homojunction through the formation of re-grown crystalline silicon layer (~5-10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method.

Sensitivity analysis of the add-on price estimate for the silicon web growth process

NASA Technical Reports Server (NTRS)

Mokashi, A. R.

1981-01-01

The web growth process, a silicon-sheet technology option, developed for the flat plate solar array (FSA) project, was examined. Base case data for the technical and cost parameters for the technical and commercial readiness phase of the FSA project are projected. The process add on price, using the base case data for cost parameters such as equipment, space, direct labor, materials and utilities, and the production parameters such as growth rate and run length, using a computer program developed specifically to do the sensitivity analysis with improved price estimation are analyzed. Silicon price, sheet thickness and cell efficiency are also discussed.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

NASA Technical Reports Server (NTRS)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

Processes and process development in Taiwan

NASA Technical Reports Server (NTRS)

Hwang, H. L.

1986-01-01

Silicon material research in the Republic of China (ROC) parallels its development in the electronic industry. A brief outline of the historical development in ROC silicon material research is given. Emphasis is placed on the recent Silane Project managed by the National Science Council, ROC, including project objectives, task forces, and recent accomplishments. An introduction is also given to industrialization of the key technologies developed in this project.

DAPHNE silicon photonics technological platform for research and development on WDM applications

NASA Astrophysics Data System (ADS)

Baudot, Charles; Fincato, Antonio; Fowler, Daivid; Perez-Galacho, Diego; Souhaité, Aurélie; Messaoudène, Sonia; Blanc, Romuald; Richard, Claire; Planchot, Jonathan; De-Buttet, Come; Orlando, Bastien; Gays, Fabien; Mezzomo, Cécilia; Bernard, Emilie; Marris-Morini, Delphine; Vivien, Laurent; Kopp, Christophe; Boeuf, Frédéric

2016-05-01

A new technological platform aimed at making prototypes and feasibility studies has been setup at STMicroelectronics using 300mm wafer foundry facilities. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is devoted at developing and evaluating new devices and sub-systems in particular for wavelength division multiplexing (WDM) applications and ring resonator based applications. Developed in the course of PLAT4MFP7 European project, DAPHNE is a flexible platform that fits perfectly R&D needs. The fabrication flow enables the processing of photonic integrated circuits using a silicon-on-insulator (SOI) of 300nm, partial etches of 150nm and 50nm and a total silicon etching. Consequently, two varieties of rib waveguides and one strip waveguide can be fabricated simultaneously with auto-alignment properties. The process variability on the 150nm partially etched silicon and the thin 50nm slab region are both less than 6 nm. Using a variety of different implantation configurations and a back-end of line of 5 metal layers, active devices are fabricated both in germanium and silicon. An available far back-end of line process consists of making 20 μm diameter copper posts on top of the electrical pads so that an electronic integrated circuit can be bonded on top the photonic die by 3D integration. Besides having those fabrication process options, DAPHNE is equipped with a library of standard cells for optical routing and multiplexing. Moreover, typical Mach-Zehnder modulators based on silicon pn junctions are also available for optical signal modulation. To achieve signal detection, germanium photodetectors also exist as standard cells. The measured single-mode propagation losses are 3.5 dB/cm for strip, 3.7 dB/cm for deep-rib (50nm slab) and 1.4 dB/cm for standard rib (150nm slab) waveguides. Transition tapers between different waveguide structures are as low as 0.006 dB.

Develop Silicone Encapsulation Systems for Terrestrial Silicon Solar Arrays

NASA Technical Reports Server (NTRS)

1979-01-01

The results for Task 3 of the Low Cost Solar Array Project are presented. Task 3 is directed toward the development of a cost effective encapsulating system for photovoltaic modules using silicon based materials. The technical approach of the contract effort is divided into four special tasks: (1) technology review; (2) generation of concepts for screening and processing silicon encapsulation systems; (3) assessment of encapsulation concepts; and (4) evaluation of encapsulation concepts. The candidate silicon materials are reviewed. The silicon and modified silicon resins were chosen on the basis of similarity to materials with known weatherability, cost, initial tangential modulus, accelerated dirt pick-up test results and the ratio of the content of organic phenyl substitution of methyl substitution on the backbone of the silicon resin.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ji, Xiaoyu; Lei, Shiming; Yu, Shih -Ying

Semiconductor core optical fibers with a silica cladding are of great interest in nonlinear photonics and optoelectronics applications. Laser crystallization has been recently demonstrated for crystallizing amorphous silicon fibers into crystalline form. Here we explore the underlying mechanism by which long single-crystal silicon fibers, which are novel platforms for silicon photonics, can be achieved by this process. Using finite element modeling, we construct a laser processing diagram that reveals a parameter space within which single crystals can be grown. Utilizing this diagram, we illustrate the creation of single-crystal silicon core fibers by laser crystallizing amorphous silicon deposited inside silica capillarymore » fibers by high-pressure chemical vapor deposition. The single-crystal fibers, up to 5.1 mm long, have a very welldefined core/cladding interface and a chemically pure silicon core that leads to very low optical losses down to ~0.47-1dB/cm at the standard telecommunication wavelength (1550 nm). Furthermore, tt also exhibits a photosensitivity that is comparable to bulk silicon. Creating such laser processing diagrams can provide a general framework for developing single-crystal fibers in other materials of technological importance.« less

Emission measurement and safety assessment for the production process of silicon nanoparticles in a pilot-scale facility

NASA Astrophysics Data System (ADS)

Wang, Jing; Asbach, Christof; Fissan, Heinz; Hülser, Tim; Kaminski, Heinz; Kuhlbusch, Thomas A. J.; Pui, David Y. H.

2012-03-01

Emission into the workplace was measured for the production process of silicon nanoparticles in a pilot-scale facility at the Institute of Energy and Environmental Technology e.V. (IUTA). The silicon nanoparticles were produced in a hot-wall reactor and consisted of primary particles around 60 nm in diameter. We employed real-time aerosol instruments to measure particle number and lung-deposited surface area concentrations and size distribution; airborne particles were also collected for off-line electron microscopic analysis. Emission of silicon nanoparticles was not detected during the processes of synthesis, collection, and bagging. This was attributed to the completely closed production system and other safety measures against particle release which will be discussed briefly. Emission of silicon nanoparticles significantly above the detection limit was only observed during the cleaning process when the production system was open and manually cleaned. The majority of the detected particles was in the size range of 100-400 nm and were silicon nanoparticle agglomerates first deposited in the tubing then re-suspended during the cleaning process. Appropriate personal protection equipment is recommended for safety protection of the workers during cleaning.

Single-crystal silicon optical fiber by direct laser crystallization

DOE PAGES

Ji, Xiaoyu; Lei, Shiming; Yu, Shih -Ying; ...

2016-12-05

Semiconductor core optical fibers with a silica cladding are of great interest in nonlinear photonics and optoelectronics applications. Laser crystallization has been recently demonstrated for crystallizing amorphous silicon fibers into crystalline form. Here we explore the underlying mechanism by which long single-crystal silicon fibers, which are novel platforms for silicon photonics, can be achieved by this process. Using finite element modeling, we construct a laser processing diagram that reveals a parameter space within which single crystals can be grown. Utilizing this diagram, we illustrate the creation of single-crystal silicon core fibers by laser crystallizing amorphous silicon deposited inside silica capillarymore » fibers by high-pressure chemical vapor deposition. The single-crystal fibers, up to 5.1 mm long, have a very welldefined core/cladding interface and a chemically pure silicon core that leads to very low optical losses down to ~0.47-1dB/cm at the standard telecommunication wavelength (1550 nm). Furthermore, tt also exhibits a photosensitivity that is comparable to bulk silicon. Creating such laser processing diagrams can provide a general framework for developing single-crystal fibers in other materials of technological importance.« less

Challenges and Opportunities in Reactive Processing and Applications of Advanced Ceramic Materials

NASA Technical Reports Server (NTRS)

Singh, Mrityunjay

2003-01-01

Recently, there has been a great deal of interest in the research, development, and commercialization of innovative synthesis and processing technologies for advanced ceramics and composite materials. Reactive processing approaches have been actively considered due to their robustness, flexibility, and affordability. A wide variety of silicon carbide-based advanced ceramics and composites are currently being fabricated using the processing approaches involving reactive infiltration of liquid and gaseous species into engineered fibrous or microporous carbon performs. The microporous carbon performs have been fabricated using the temperature induced phase separation and pyrolysis of two phase organic (resin-pore former) mixtures and fiber reinforcement of carbon and ceramic particulate bodies. In addition, pyrolyzed native plant cellulose tissues also provide unique carbon templates for manufacturing of non-oxide and oxide ceramics. In spite of great interest in this technology due to their affordability and robustness, there is a lack of scientific basis for process understanding and many technical challenges still remain. The influence of perform properties and other parameters on the resulting microstructure and properties of final material is not well understood. In this presentation, mechanism of silicon-carbon reaction in various systems and the effect of perform microstructure on the mechanical properties of advanced silicon carbide based materials will be discussed. Various examples of applications of reactively processed advanced silicon carbide ceramics and composite materials will be presented.

Cost Benefit Analysis of Integrated COTS Energy- Related Technologies for Army’s Force Provider Module

DTIC Science & Technology

2009-09-01

Year Defense Plan (FYDP), on which the Department of Defense operates, subsequently needs 26 Richard G. Lugar, U.S. Senator for Indiana , “U.S...mature thin-film technologies exist such as Amorphous Silicon (a-Si), Cadmium Telluride (CdTe), and Copper Indium Gallium (di) Selenide (CIGS), all...cheaper processing, lower material costs, and is free of the environmental and health hazard issues of cadmium . Amorphous silicon coupled with

Semi-transparent solar cells

NASA Astrophysics Data System (ADS)

Sun, J.; Jasieniak, J. J.

2017-03-01

Semi-transparent solar cells are a type of technology that combines the benefits of visible light transparency and light-to-electricity conversion. One of the biggest opportunities for such technologies is in their integration as windows and skylights within energy-sustainable buildings. Currently, such building integrated photovoltaics (BIPV) are dominated by crystalline silicon based modules; however, the opaque nature of silicon creates a unique opportunity for the adoption of emerging photovoltaic candidates that can be made truly semi-transparent. These include: amorphous silicon-, kesterite-, chalcopyrite-, CdTe-, dye-sensitized-, organic- and perovskite- based systems. For the most part, amorphous silicon has been the workhorse in the semi-transparent solar cell field owing to its established, low-temperature fabrication processes. Excitement around alternative classes, particularly perovskites and the inorganic candidates, has recently arisen because of the major efficiency gains exhibited by these technologies. Importantly, each of these presents unique opportunities and challenges within the context of BIPV. This topic review provides an overview into the broader benefits of semi-transparent solar cells as building-integrated features, as well as providing the current development status into all of the major types of semi-transparent solar cells technologies.

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

A silicon carbide array for electrocorticography and peripheral nerve recording.

PubMed

Diaz-Botia, C A; Luna, L E; Neely, R M; Chamanzar, M; Carraro, C; Carmena, J M; Sabes, P N; Maboudian, R; Maharbiz, M M

2017-10-01

Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

A silicon carbide array for electrocorticography and peripheral nerve recording

NASA Astrophysics Data System (ADS)

Diaz-Botia, C. A.; Luna, L. E.; Neely, R. M.; Chamanzar, M.; Carraro, C.; Carmena, J. M.; Sabes, P. N.; Maboudian, R.; Maharbiz, M. M.

2017-10-01

Objective. Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. Approach. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. Main results. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Significance. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

Low-cost solar array project and Proceedings of the 15th Project Integration Meeting

NASA Technical Reports Server (NTRS)

1980-01-01

Progress made by the Low-Cost Solar Array Project during the period December 1979 to April 1980 is described. Project analysis and integration, technology development in silicon material, large area silicon sheet and encapsulation, production process and equipment development, engineering, and operation are included.

NASA 2009 Body of Knowledge (BoK) Through-Slicon Via Technology

NASA Technical Reports Server (NTRS)

Gerke, David

2009-01-01

Through-silicon via (TSV) is the latest in a progression of technologies for stacking silicon devices in three dimensions (3D). Driven by the need for improved performance, methods to use short vertical interconnects to replace the long interconnects found in 2D structures have been developed. The industry is moving past the feasibility (research and development [R and D]) phase for TSV technology into the commercialization phase where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Even though design, thermal, and test issues remain, much progress has been made.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

A review of the silicon material task

NASA Technical Reports Server (NTRS)

Lutwack, R.

1984-01-01

The Silicon Material Task of the Flat-Plate Solar Array Project was assigned the objective of developing the technology for low-cost processes for producing polysilicon suitable for terrestrial solar-cell applications. The Task program comprised sections for process developments for semiconductor-grade and solar-cell-grade products. To provide information for deciding upon process designs, extensive investigations of the effects of impurities on material properties and the performance of cells were conducted. The silane process of the Union Carbide Corporation was carried through several stages of technical and engineering development; a pilot plant was the culmination of this effort. The work to establish silane fluidized-bed technology for a low-cost process is continuing. The advantages of the use of dichlorosilane is a siemens-type were shown by Hemlock Semiconductor Corporation. The development of other processes is described.

A review of the silicon material task

NASA Astrophysics Data System (ADS)

Lutwack, R.

1984-02-01

The Silicon Material Task of the Flat-Plate Solar Array Project was assigned the objective of developing the technology for low-cost processes for producing polysilicon suitable for terrestrial solar-cell applications. The Task program comprised sections for process developments for semiconductor-grade and solar-cell-grade products. To provide information for deciding upon process designs, extensive investigations of the effects of impurities on material properties and the performance of cells were conducted. The silane process of the Union Carbide Corporation was carried through several stages of technical and engineering development; a pilot plant was the culmination of this effort. The work to establish silane fluidized-bed technology for a low-cost process is continuing. The advantages of the use of dichlorosilane is a siemens-type were shown by Hemlock Semiconductor Corporation. The development of other processes is described.

Lasers in energy device manufacturing

NASA Astrophysics Data System (ADS)

Ostendorf, A.; Schoonderbeek, A.

2008-02-01

Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

Alternative process for thin layer etching: Application to nitride spacer etching stopping on silicon germanium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Posseme, N., E-mail: nicolas.posseme@cea.fr; Pollet, O.; Barnola, S.

2014-08-04

Silicon nitride spacer etching realization is considered today as one of the most challenging of the etch process for the new devices realization. For this step, the atomic etch precision to stop on silicon or silicon germanium with a perfect anisotropy (no foot formation) is required. The situation is that none of the current plasma technologies can meet all these requirements. To overcome these issues and meet the highly complex requirements imposed by device fabrication processes, we recently proposed an alternative etching process to the current plasma etch chemistries. This process is based on thin film modification by light ionsmore » implantation followed by a selective removal of the modified layer with respect to the non-modified material. In this Letter, we demonstrate the benefit of this alternative etch method in term of film damage control (silicon germanium recess obtained is less than 6 A), anisotropy (no foot formation), and its compatibility with other integration steps like epitaxial. The etch mechanisms of this approach are also addressed.« less

Yield enhancement with DFM

NASA Astrophysics Data System (ADS)

Paek, Seung Weon; Kang, Jae Hyun; Ha, Naya; Kim, Byung-Moo; Jang, Dae-Hyun; Jeon, Junsu; Kim, DaeWook; Chung, Kun Young; Yu, Sung-eun; Park, Joo Hyun; Bae, SangMin; Song, DongSup; Noh, WooYoung; Kim, YoungDuck; Song, HyunSeok; Choi, HungBok; Kim, Kee Sup; Choi, Kyu-Myung; Choi, Woonhyuk; Jeon, JoongWon; Lee, JinWoo; Kim, Ki-Su; Park, SeongHo; Chung, No-Young; Lee, KangDuck; Hong, YoungKi; Kim, BongSeok

2012-03-01

A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.

Room temperature multiplexed gas sensing using chemical-sensitive 3.5-nm-thin silicon transistors.

PubMed

Fahad, Hossain Mohammad; Shiraki, Hiroshi; Amani, Matin; Zhang, Chuchu; Hebbar, Vivek Srinivas; Gao, Wei; Ota, Hiroki; Hettick, Mark; Kiriya, Daisuke; Chen, Yu-Ze; Chueh, Yu-Lun; Javey, Ali

2017-03-01

There is great interest in developing a low-power gas sensing technology that can sensitively and selectively quantify the chemical composition of a target atmosphere. Nanomaterials have emerged as extremely promising candidates for this technology due to their inherent low-dimensional nature and high surface-to-volume ratio. Among these, nanoscale silicon is of great interest because pristine silicon is largely inert on its own in the context of gas sensing, unless functionalized with an appropriate gas-sensitive material. We report a chemical-sensitive field-effect transistor (CS-FET) platform based on 3.5-nm-thin silicon channel transistors. Using industry-compatible processing techniques, the conventional electrically active gate stack is replaced by an ultrathin chemical-sensitive layer that is electrically nonconducting and coupled to the 3.5-nm-thin silicon channel. We demonstrate a low-power, sensitive, and selective multiplexed gas sensing technology using this platform by detecting H 2 S, H 2 , and NO 2 at room temperature for environment, health, and safety in the oil and gas industry, offering significant advantages over existing technology. Moreover, the system described here can be readily integrated with mobile electronics for distributed sensor networks in environmental pollution mapping and personal air-quality monitors.

Room temperature multiplexed gas sensing using chemical-sensitive 3.5-nm-thin silicon transistors

PubMed Central

Fahad, Hossain Mohammad; Shiraki, Hiroshi; Amani, Matin; Zhang, Chuchu; Hebbar, Vivek Srinivas; Gao, Wei; Ota, Hiroki; Hettick, Mark; Kiriya, Daisuke; Chen, Yu-Ze; Chueh, Yu-Lun; Javey, Ali

2017-01-01

There is great interest in developing a low-power gas sensing technology that can sensitively and selectively quantify the chemical composition of a target atmosphere. Nanomaterials have emerged as extremely promising candidates for this technology due to their inherent low-dimensional nature and high surface-to-volume ratio. Among these, nanoscale silicon is of great interest because pristine silicon is largely inert on its own in the context of gas sensing, unless functionalized with an appropriate gas-sensitive material. We report a chemical-sensitive field-effect transistor (CS-FET) platform based on 3.5-nm-thin silicon channel transistors. Using industry-compatible processing techniques, the conventional electrically active gate stack is replaced by an ultrathin chemical-sensitive layer that is electrically nonconducting and coupled to the 3.5-nm-thin silicon channel. We demonstrate a low-power, sensitive, and selective multiplexed gas sensing technology using this platform by detecting H2S, H2, and NO2 at room temperature for environment, health, and safety in the oil and gas industry, offering significant advantages over existing technology. Moreover, the system described here can be readily integrated with mobile electronics for distributed sensor networks in environmental pollution mapping and personal air-quality monitors. PMID:28378017

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Laser-zone Growth in a Ribbon-to-ribbon (RTR) Process Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Baghdadi, A.; Gurtler, R. W.; Legge, R.; Sopori, B.; Rice, M. J.; Ellis, R. J.

1979-01-01

A technique for growing limited-length ribbons continually was demonstrated. This Rigid Edge technique can be used to recrystallize about 95% of the polyribbon feedstock. A major advantage of this method is that only a single, constant length silicon ribbon is handled throughout the entire process sequence; this may be accomplished using cassettes similar to those presently in use for processing Czochralski waters. Thus a transition from Cz to ribbon technology can be smoothly affected. The maximum size being considered, 3 inches x 24 inches, is half a square foot, and will generate 6 watts for 12% efficiency at 1 sun. Silicon dioxide has been demonstrated as an effective, practical diffusion barrier for use during the polyribbon formation.

Millimeter-Wave Wireless Power Transfer Technology for Space Applications

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Manohara, Harish; Mojarradi, Mohammad M.; Vo, Tuan A.; Mojarradi, Hadi; Bae, Sam Y.; Marzwell, Neville

2008-01-01

In this paper we present a new compact, scalable, and low cost technology for efficient receiving of power using RF waves at 94 GHz. This technology employs a highly innovative array of slot antennas that is integrated on substrate composed of gold (Au), silicon (Si), and silicon dioxide (SiO2) layers. The length of the slots and spacing between them are optimized for a highly efficient beam through a 3-D electromagnetic simulation process. Antenna simulation results shows a good beam profile with very low side lobe levels and better than 93% antenna efficiency.

Imaging of the native inversion layer in Silicon-On-Insulator wafers via Scanning Surface Photovoltage: Implications for RF device performance

NASA Astrophysics Data System (ADS)

Dahanayaka, Daminda; Wong, Andrew; Kaszuba, Philip; Moszkowicz, Leon; Slinkman, James; IBM SPV Lab Team

2014-03-01

Silicon-On-Insulator (SOI) technology has proved beneficial for RF cell phone technologies, which have equivalent performance to GaAs technologies. However, there is evident parasitic inversion layer under the Buried Oxide (BOX) at the interface with the high resistivity Si substrate. The latter is inferred from capacitance-voltage measurements on MOSCAPs. The inversion layer has adverse effects on RF device performance. We present data which, for the first time, show the extent of the inversion layer in the underlying substrate. This knowledge has driven processing techniques to suppress the inversion.

Silicon photonic IC embedded optical-PCB for high-speed interconnect application

NASA Astrophysics Data System (ADS)

Kallega, Rakshitha; Nambiar, Siddharth; Kumar, Abhai; Ranganath, Praveen; Selvaraja, Shankar Kumar

2018-02-01

Optical-Printed Circuit Board (PCB) is an emerging optical interconnect technology to bridge the gap between the board edge and the processing module. The technology so far has been used as a broadband transmitter using polymer waveguides in the PCB. In this paper, we report a Silicon Nitride based photonic IC embedded in the PCB along with the polymers as waveguides in the PCB. The motivation for such integration is to bring routing capability and to reduce the power loss due to broadcasting mode.

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology

PubMed Central

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-01-01

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm2, and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p+−n homojunction through the formation of re-grown crystalline silicon layer (~5–10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method. PMID:26632759

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

The silicon-glass microreactor with embedded sensors—technology and results of preliminary qualitative tests, toward intelligent microreaction plant

NASA Astrophysics Data System (ADS)

Knapkiewicz, P.

2013-03-01

The technology and preliminary qualitative tests of silicon-glass microreactors with embedded pressure and temperature sensors are presented. The concept of microreactors for leading highly exothermic reactions, e.g. nitration of hydrocarbons, and design process-included computer-aided simulations are described in detail. The silicon-glass microreactor chip consisting of two micromixers (multistream micromixer), reaction channels, cooling/heating chambers has been proposed. The microreactor chip was equipped with a set of pressure and temperature sensors and packaged. Tests of mixing quality, pressure drops in channels, heat exchange efficiency and dynamic behavior of pressure and temperature sensors were documented. Finally, two applications were described.

Silica-on-silicon waveguide quantum circuits.

PubMed

Politi, Alberto; Cryan, Martin J; Rarity, John G; Yu, Siyuan; O'Brien, Jeremy L

2008-05-02

Quantum technologies based on photons will likely require an integrated optics architecture for improved performance, miniaturization, and scalability. We demonstrate high-fidelity silica-on-silicon integrated optical realizations of key quantum photonic circuits, including two-photon quantum interference with a visibility of 94.8 +/- 0.5%; a controlled-NOT gate with an average logical basis fidelity of 94.3 +/- 0.2%; and a path-entangled state of two photons with fidelity of >92%. These results show that it is possible to directly "write" sophisticated photonic quantum circuits onto a silicon chip, which will be of benefit to future quantum technologies based on photons, including information processing, communication, metrology, and lithography, as well as the fundamental science of quantum optics.

Technological processes of grating light valve as diffractive spatial light modulator in laser phototypesetting system

NASA Astrophysics Data System (ADS)

Zhang, Wei; Geng, Yu; Hou, Changlun; Yang, Guoguang; Bai, Jian

2008-11-01

Grating Light Valve (GLV) is a kind of optics device based on Micro-Opto-Electro-Mechanical System (MOEMS) technology, utilizing diffraction principle to switch, attenuate and modulate light. In this paper, traditional GLV device's structure and its working principle are illuminated, and a kind of modified GLV structure is presented, with details introduction of the fabrication technology. The GLV structure includes single crystal silicon substrate, silicon dioxide isolating layer, aluminum layer of fixed ribbons and silicon nitride of movable ribbons. In the fabrication, lots of techniques are adopted, such as low-pressure chemical vapor deposition (LPCVD), photolithography, etching and evaporation. During the fabrication processes, Photolithography is a fundamental and fatal technology, which determines etching result and GLV quality. Some methods are proposed through repeated experiments, to improve etching result greatly and guide the practical application. This kind of GLV device can be made both small and inexpensively, and has been tested to show proper range of actuation under DC bias, with good performance. The GLV device also has merits such as low cost, simple technology, high fill ratio and low driving voltage. It can properly be well used and match the demands of high light power needed in laser phototypesetting system, as a high-speed, high-resolution light modulator.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Progress Report 18 for the Period February to July 1981 and Proceeidngs of the 18th Project Integration Meeting

NASA Technical Reports Server (NTRS)

1981-01-01

Progress in the low cost solar array project during the period February to July 1981 is reported. Included are: (1) project analysis and integration; (2) technology development in silicon material, large area silicon sheer and encapsulation; (3) process development; (4) engineering, and operations.

Low-cost solar array project and Proceedings of the 14th Project Integration Meeting

NASA Technical Reports Server (NTRS)

Mcdonald, R. R.

1980-01-01

Activities are reported on the following areas: project analysis and integration; technology development in silicon material, large area sheet silicon, and encapsulation; production process and equipment development; and engineering and operations, and the steps taken to integrate these efforts. Visual materials presented at the project Integration Meeting are included.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids.

PubMed

Strobel, Sebastian; Hernández, Rocío Murcia; Hansen, Allan G; Tornow, Marc

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10(-18) farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

Micro-spectroscopy on silicon wafers and solar cells

PubMed Central

2011-01-01

Micro-Raman (μRS) and micro-photoluminescence spectroscopy (μPLS) are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance) of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes. PMID:21711723

A high voltage dielectrically isolated smart power technology based on silicon direct bonding

NASA Astrophysics Data System (ADS)

Macary, Veronique

1992-09-01

The feasibility of a dielectrically isolated technology based on the silicon direct bonding technique, for high voltage smart power applications in the 1000 to 1550 V/1 to 20 A range, where a vertical power switch is necessary, is investigated and demonstrated. Static and dynamic isolation of the low voltage circuitry integrated beside the vertical power transistor is the main concern of this family of circuits. The dielectric isolation offers better protection to the low voltage part than does the junction isolation, because of the elimination of the parasitic bipolar transistor inherent to the latter isolation technique. Silicon direct bonding provides a cost effective way to obtain a buried oxide isolation layer. In addition, the application requires a Si/Si bonded area in the active region of the vertical power switch. Strong influence of the prebonding cleaning in the electrical characteristics of the Si/Si interface is pointed out, and presence of crystalline defects is assumed to be at the origin of electrical failures. The main problems of silicon direct bonding process compatibility with standard processes were overcome, and a complete process flow, including the simultaneous integration of a vertical power bipolar transistor together with a bipolar control circuitry, was validated. Using a peripheral biased ring is shown to provide an easy way to optimize high voltage termination for the smart power circuit, while adding a non-additional technological step. This technique was studied by dimensional electrical simulations (BIDIM2 software), as well as analytically computed.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Smart integration of silicon nanowire arrays in all-silicon thermoelectric micro-nanogenerators

NASA Astrophysics Data System (ADS)

Fonseca, Luis; Santos, Jose-Domingo; Roncaglia, Alberto; Narducci, Dario; Calaza, Carlos; Salleras, Marc; Donmez, Inci; Tarancon, Albert; Morata, Alex; Gadea, Gerard; Belsito, Luca; Zulian, Laura

2016-08-01

Micro and nanotechnologies are called to play a key role in the fabrication of small and low cost sensors with excellent performance enabling new continuous monitoring scenarios and distributed intelligence paradigms (Internet of Things, Trillion Sensors). Harvesting devices providing energy autonomy to those large numbers of microsensors will be essential. In those scenarios where waste heat sources are present, thermoelectricity will be the obvious choice. However, miniaturization of state of the art thermoelectric modules is not easy with the current technologies used for their fabrication. Micro and nanotechnologies offer an interesting alternative considering that silicon in nanowire form is a material with a promising thermoelectric figure of merit. This paper presents two approaches for the integration of large numbers of silicon nanowires in a cost-effective and practical way using only micromachining and thin-film processes compatible with silicon technologies. Both approaches lead to automated physical and electrical integration of medium-high density stacked arrays of crystalline or polycrystalline silicon nanowires with arbitrary length (tens to hundreds microns) and diameters below 100 nm.

Efficient 'Optical Furnace': A Cheaper Way to Make Solar Cells is Reaching the Marketplace

DOE Office of Scientific and Technical Information (OSTI.GOV)

von Kuegelgen, T.

In Bhushan Sopori's laboratory, you'll find a series of optical furnaces he has developed for fabricating solar cells. When not in use, they sit there discreetly among the lab equipment. But when a solar silicon wafer is placed inside one for processing, Sopori walks over to a computer and types in a temperature profile. Almost immediately this fires up the furnace, which glows inside and selectively heats up the silicon wafer to 800 degrees centigrade by the intense light it produces. Sopori, a principal engineer at the National Renewable Energy Laboratory, has been researching and developing optical furnace technology formore » around 20 years. He says it's a challenging technology to develop because there are many issues to consider when you process a solar cell, especially in optics. Despite the challenges, Sopori and his research team have advanced the technology to the point where it will benefit all solar cell manufacturers. They are now developing a commercial version of the furnace in partnership with a manufacturer. 'This advanced optical furnace is highly energy efficient, and it can be used to manufacture any type of solar cell,' he says. Each type of solar cell or manufacturing process typically requires a different furnace configuration and temperature profile. With NREL's new optical furnace system, a solar cell manufacturer can ask the computer for any temperature profile needed for processing a solar cell, and the same type of furnace is suitable for several solar cell fabrication process steps. 'In the future, solar cell manufacturers will only need this one optical furnace because it can be used for any process, including diffusion, metallization and oxidation,' Sopori says. 'This helps reduce manufacturing costs.' One startup company, Applied Optical Systems, has recognized the furnace's potential for manufacturing thin-film silicon cells. 'We'd like to develop thin-film silicon cells with higher efficiencies, up to 15 to 18 percent, and we believe this furnace will enable us to do so,' says A. Rangappan, founder and CEO of Applied Optical Systems. Rangappan also says it will take only a few minutes for the optical furnace to process a thin-film solar cell, which reduces manufacturing costs. Overall, he estimates the company's solar cell will cost around 80 cents per watt. For manufacturing these thin-film silicon cells, Applied Optical Systems and NREL have developed a partnership through a cooperative research and development agreement (CRADA) to construct an optical furnace system prototype. DOE is providing $500,000 from its Technology Commercialization Development Fund to help offset the prototype's development costs because of the technology's significant market potential. The program has provided the NREL technology transfer office with a total of $4 million to expand such collaborative efforts between NREL researchers and companies. Applied Optical will construct a small version of the optical furnace based on the prototype design in NREL's process development and integration laboratory through a separate CRADA. This small furnace will only develop one solar cell wafer at a time. Then, the company will construct a large, commercial-scale optical furnace at its own facilities, which will turn out around 1,000 solar cell wafers per hour. 'We hope to start using the optical furnace for manufacturing within four to five years,' Rangappan says. Meanwhile, another partnership using the optical furnace has evolved between NREL and SiXtron Advanced Materials, another startup. Together they'll use the optical furnace to optimize the metallization process for novel antireflective solar cell coatings. The process is not only expected to yield higher efficiencies for silicon-based solar cells, but also lowers processing costs and eliminates safety concerns for manufacturers. Most solar cell manufacturers currently use a plasma-enhanced chemical vapor deposition (PECVD) system with compressed and extremely pyrophoric silane gas (SiH4) for applying passivation antireflective coatings (ARC). If silane is exposed to air, the SiH4 will explode - a serious safety issue for high-volume manufacturers. SiXtron's process uses a solid, silicon-based polymer that's converted into noncompressed, nonexplosive gas, which then flows to a standard PECVD system. 'The solid source is so safe to handle that it can be shipped by FedEx,' says Zbigniew Barwicz, president and CEO of SiXtron. Barwicz says manufacturers can use the same PECVD processing equipment for the SiXtron process that they already use for SiH4, a plug-and-play solution. For this novel passivation ARC process, NREL is helping to optimize the metallization parameters. NREL has developed a new technology called optical processing. One of the applications of this process is fire-through contact formation of silicon solar cells.« less

Silicon carbide-free graphene growth on silicon for lithium-ion battery with high volumetric energy density

PubMed Central

Son, In Hyuk; Hwan Park, Jong; Kwon, Soonchul; Park, Seongyong; Rümmeli, Mark H.; Bachmatiuk, Alicja; Song, Hyun Jae; Ku, Junhwan; Choi, Jang Wook; Choi, Jae-man; Doo, Seok-Gwang; Chang, Hyuk

2015-01-01

Silicon is receiving discernable attention as an active material for next generation lithium-ion battery anodes because of its unparalleled gravimetric capacity. However, the large volume change of silicon over charge–discharge cycles weakens its competitiveness in the volumetric energy density and cycle life. Here we report direct graphene growth over silicon nanoparticles without silicon carbide formation. The graphene layers anchored onto the silicon surface accommodate the volume expansion of silicon via a sliding process between adjacent graphene layers. When paired with a commercial lithium cobalt oxide cathode, the silicon carbide-free graphene coating allows the full cell to reach volumetric energy densities of 972 and 700 Wh l−1 at first and 200th cycle, respectively, 1.8 and 1.5 times higher than those of current commercial lithium-ion batteries. This observation suggests that two-dimensional layered structure of graphene and its silicon carbide-free integration with silicon can serve as a prototype in advancing silicon anodes to commercially viable technology. PMID:26109057

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

NASA Astrophysics Data System (ADS)

Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

2018-04-01

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

Electrostatic separation for recycling silver, silicon and polyethylene terephthalate from waste photovoltaic cells

NASA Astrophysics Data System (ADS)

Zhang, Zisheng; Sun, Bo; Yang, Jie; Wei, Yusheng; He, Shoujie

2017-04-01

Electrostatic separation technology has been proven to be an effective and environmentally friendly way of recycling electronic waste. In this study, this technology was applied to recycle waste solar panels. Mixed particles of silver and polyethylene terephthalate, silicon and polyethylene terephthalate, and silver and silicon were separated with a single-roll-type electrostatic separator. The influence of high voltage level, roll speed, radial position corona electrode and angular position of the corona electrode on the separation efficiency was studied. The experimental data showed that separation of silver/polyethylene terephthalate and silicon/polyethylene terephthalate needed a higher voltage level, while separation of silver and silicon needed a smaller angular position for the corona electrode and a higher roll speed. The change of the high voltage level, roll speed, radial position of the corona electrode, and angular position of the corona electrode has more influence on silicon separation efficiency than silver separation efficiency. An integrated process is proposed using a two-roll-type corona separator for multistage separation of a mixture of these three materials. The separation efficiency for silver and silicon were found to reach 96% and 98%, respectively.

Ion assisted deposition of SiO2 film from silicon

NASA Astrophysics Data System (ADS)

Pham, Tuan. H.; Dang, Cu. X.

2005-09-01

Silicon dioxide, SiO2, is one of the preferred low index materials for optical thin film technology. It is often deposited by electron beam evaporation source with less porosity and scattering, relatively durable and can have a good laser damage threshold. Beside these advantages the deposition of critical optical thin film stacks with silicon dioxide from an E-gun was severely limited by the stability of the evaporation pattern or angular distribution of the material. The even surface of SiO2 granules in crucible will tend to develop into groove and become deeper with the evaporation process. As the results, angular distribution of the evaporation vapor changes in non-predicted manner. This report presents our experiments to apply Ion Assisted Deposition process to evaporate silicon in a molten liquid form. By choosing appropriate process parameters we can get SiO2 film with good and stable property.

Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited].

PubMed

Stojanović, Vladimir; Ram, Rajeev J; Popović, Milos; Lin, Sen; Moazeni, Sajjad; Wade, Mark; Sun, Chen; Alloatti, Luca; Atabaki, Amir; Pavanello, Fabio; Mehta, Nandish; Bhargava, Pavan

2018-05-14

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-01-01

Mobil Solar Energy Corporation currently practices a unique crystal growth technology for producing crystalline silicon sheet, which is then cut with lasers into wafers. The wafers are processed into solar cells and incorporated into modules for photovoltaic applications. The silicon sheet is produced using a method known as Edge-defined Film-fed growth (EFG), in the form of hollow eight-sided polygons (octagons) with 10 cm faces. These are grown to lengths of 5 meters and thickness of 300 microns, with continuous melt replenishment, in compact furnaces designed to operate at a high sheet area production area of 135 sq cm/min. The present Photovoltaic Manufacturing Technology (PVMaT) three-year program seeks to advance the manufacturing line capabilities of the Mobil Solar crystal growth and cutting technologies. If successful, these advancements will provide significant reductions in already low silicon raw material usage, improve process productivity, laser cutting throughput and yield, and so lower both individual wafer cost and the cost of module production. This report summarizes the significant technical improvements in EFG technology achieved in Phase 1 of this program. Technical results are reported for each of the three main program areas: (1) thin octagon growth (crystal growth) -- to reduce the thickness of the octagon to an interim goal of 250 microns during Phase 1, with an ultimate goal of achieving 200 micron thicknesses; (2) laser cutting -- to improve the laser cutting process, so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and (3) process control and product specification -- to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Pinpoint and bulk electrochemical reduction of insulating silicon dioxide to silicon.

PubMed

Nohira, Toshiyuki; Yasuda, Kouji; Ito, Yasuhiko

2003-06-01

Silicon dioxide (SiO(2)) is conventionally reduced to silicon by carbothermal reduction, in which the oxygen is removed by a heterogeneous-homogeneous reaction sequence at approximately 1,700 degrees C. Here we report pinpoint and bulk electrochemical methods for removing oxygen from solid SiO(2) in a molten CaCl(2) electrolyte at 850 degrees C. This approach involves a 'contacting electrode', in which a metal wire supplies electrons to a selected region of the insulating SiO(2). Bulk reduction of SiO(2) is possible by increasing the number of contacting points. The same method was also demonstrated with molten LiCl-KCl-CaCl(2) at 500 degrees C. The novelty and relative simplicity of this method might lead to new processes in silicon semiconductor technology, as well as in high-purity silicon production. The methodology may be applicable to electrochemical processing of a wide variety of insulating materials, provided that the electrolyte dissolves the appropriate constituent ion(s) of the material.

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

NASA Astrophysics Data System (ADS)

Rotta, Davide; Sebastiano, Fabio; Charbon, Edoardo; Prati, Enrico

2017-06-01

Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal-oxide-semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal-oxide-semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal-oxide-semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal-oxide-semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm2 for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.

Advanced refractory-metal and process technology for the fabrication of x-ray masks

NASA Astrophysics Data System (ADS)

Brooks, Cameron J.; Racette, Kenneth C.; Lercel, Michael J.; Powers, Lynn A.; Benoit, Douglas E.

1999-06-01

This paper provides an in-depth report of the advanced materials and process technology being developed for x-ray mask manufacturing at IBM. Masks using diamond membranes as replacement for silicon carbide are currently being fabricated. Alternate tantalum-based absorbers, such as tantalum boron, which offer improved etch resolution and critical dimension control, as well as higher x-ray absorption, are also being investigated. In addition to the absorber studies, the development of conductive chromium- based hard-mask films to replace the current silicon oxynitride layer is being explored. The progress of this advanced-materials work, which includes significant enhancements to x-ray mask image-placement performance, will be outlined.

Advanced Turbine Technology Applications Project (ATTAP)

NASA Technical Reports Server (NTRS)

1991-01-01

This report summarizes work performed in support of the development and demonstration of a structural ceramic technology for automotive gas turbine engines. The AGT101 regenerated gas turbine engine developed under the previous DOE/NASA Advanced Gas Turbine (AGT) program is being utilized for verification testing of the durability of next-generation ceramic components and their suitability for service at reference powertrain design conditions. Topics covered in this report include ceramic processing definition and refinement, design improvements to the test bed engine and test rigs, and design methodologies related to ceramic impact and fracture mechanisms. Appendices include reports by ATTAP subcontractors addressing the development of silicon nitride and silicon carbide families of materials and processes.

Flexible amorphous silicon PIN diode x-ray detectors

NASA Astrophysics Data System (ADS)

Marrs, Michael; Bawolek, Edward; Smith, Joseph T.; Raupp, Gregory B.; Morton, David

2013-05-01

A low temperature amorphous silicon (a-Si) thin film transistor (TFT) and amorphous silicon PIN photodiode technology for flexible passive pixel detector arrays has been developed using active matrix display technology. The flexible detector arrays can be conformed to non-planar surfaces with the potential to detect x-rays or other radiation with an appropriate conversion layer. The thin, lightweight, and robust backplanes may enable the use of highly portable x-ray detectors for use in the battlefield or in remote locations. We have fabricated detector arrays up to 200 millimeters along the diagonal on a Gen II (370 mm x 470 mm rectangular substrate) using plasma enhanced chemical vapor deposition (PECVD) a-Si as the active layer and PECVD silicon nitride (SiN) as the gate dielectric and passivation. The a-Si based TFTs exhibited an effective saturation mobility of 0.7 cm2/V-s, which is adequate for most sensing applications. The PIN diode material was fabricated using a low stress amorphous silicon (a-Si) PECVD process. The PIN diode dark current was 1.7 pA/mm2, the diode ideality factor was 1.36, and the diode fill factor was 0.73. We report on the critical steps in the evolution of the backplane process from qualification of the low temperature (180°C) TFT and PIN diode process on the 150 mm pilot line, the transfer of the process to flexible plastic substrates, and finally a discussion and demonstration of the scale-up to the Gen II (370 x 470 mm) panel scale pilot line.

The electrophotonic silicon biosensor

NASA Astrophysics Data System (ADS)

Juan-Colás, José; Parkin, Alison; Dunn, Katherine E.; Scullion, Mark G.; Krauss, Thomas F.; Johnson, Steven D.

2016-09-01

The emergence of personalized and stratified medicine requires label-free, low-cost diagnostic technology capable of monitoring multiple disease biomarkers in parallel. Silicon photonic biosensors combine high-sensitivity analysis with scalable, low-cost manufacturing, but they tend to measure only a single biomarker and provide no information about their (bio)chemical activity. Here we introduce an electrochemical silicon photonic sensor capable of highly sensitive and multiparameter profiling of biomarkers. Our electrophotonic technology consists of microring resonators optimally n-doped to support high Q resonances alongside electrochemical processes in situ. The inclusion of electrochemical control enables site-selective immobilization of different biomolecules on individual microrings within a sensor array. The combination of photonic and electrochemical characterization also provides additional quantitative information and unique insight into chemical reactivity that is unavailable with photonic detection alone. By exploiting both the photonic and the electrical properties of silicon, the sensor opens new modalities for sensing on the microscale.

Preparation of a silicon surface for subsequent growth of dilute nitride alloys by molecular-beam epitaxy

NASA Astrophysics Data System (ADS)

Lazarenko, A. A.; Berezovskaya, T. N.; Denisov, D. V.; Sobolev, M. S.; Pirogov, E. V.; Nikitina, E. V.

2017-11-01

This article discusses the process of preparation of a silicon surface for subsequent growth of dilute nitride alloys by molecular-beam epitaxy. The method of preparation of Si (100) and Si (111) substrates was developed. This method provides reproducible high-quality silicon surface for molecular-beam epitaxy of Si-GaP heterostructures. As a result, it managed to reduce the eviction oxide temperature below 800 °C, which is an important parameter for the MBE technology.

Advancements in silicon web technology

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Easoz, J.; Mchugh, J. P.; Piotrowski, P.; Hundal, R.

1987-01-01

Low defect density silicon web crystals up to 7 cm wide are produced from systems whose thermal environments are designed for low stress conditions using computer techniques. During growth, the average silicon melt temperature, the lateral melt temperature distribution, and the melt level are each controlled by digital closed loop systems to maintain thermal steady state and to minimize the labor content of the process. Web solar cell efficiencies of 17.2 pct AM1 have been obtained in the laboratory while 15 pct efficiencies are common in pilot production.

Multiple EFG silicon ribbon technology as the basis for manufacturing low-cost terrestrial solar cells. [Epitaxial Film Growth

NASA Technical Reports Server (NTRS)

Mackintosh, B.; Kalejs, J. P.; Ho, C. T.; Wald, F. V.

1981-01-01

Mackintosh et al. (1978) have reported on the development of a multiple ribbon furnace based on the 'edge defined film fed growth' (EFG) process for the fabrication of silicon ribbon. It has been demonstrated that this technology can meet the requirements for a silicon substrate material to be used in the manufacture of solar panels which can meet requirements regarding a selling price of $0.70/Wp when certain goals in terms of throughput and quality are achieved. These goals for the multiple ribbon technology using 10 cm wide ribbon require simultaneous growth of 12 ribbons by one operator at average speeds of 4 to 4.5 cm/min, and 13% efficient solar cells. A description is presented of the progress made toward achieving these goals. It is concluded that the required performance levels have now been achieved. The separate aspects of technology must now be integrated into a single prototype furnace.

3D Integration for Wireless Multimedia

NASA Astrophysics Data System (ADS)

Kimmich, Georg

The convergence of mobile phone, internet, mapping, gaming and office automation tools with high quality video and still imaging capture capability is becoming a strong market trend for portable devices. High-density video encode and decode, 3D graphics for gaming, increased application-software complexity and ultra-high-bandwidth 4G modem technologies are driving the CPU performance and memory bandwidth requirements close to the PC segment. These portable multimedia devices are battery operated, which requires the deployment of new low-power-optimized silicon process technologies and ultra-low-power design techniques at system, architecture and device level. Mobile devices also need to comply with stringent silicon-area and package-volume constraints. As for all consumer devices, low production cost and fast time-to-volume production is key for success. This chapter shows how 3D architectures can bring a possible breakthrough to meet the conflicting power, performance and area constraints. Multiple 3D die-stacking partitioning strategies are described and analyzed on their potential to improve the overall system power, performance and cost for specific application scenarios. Requirements and maturity of the basic process-technology bricks including through-silicon via (TSV) and die-to-die attachment techniques are reviewed. Finally, we highlight new challenges which will arise with 3D stacking and an outlook on how they may be addressed: Higher power density will require thermal design considerations, new EDA tools will need to be developed to cope with the integration of heterogeneous technologies and to guarantee signal and power integrity across the die stack. The silicon/wafer test strategies have to be adapted to handle high-density IO arrays, ultra-thin wafers and provide built-in self-test of attached memories. New standards and business models have to be developed to allow cost-efficient assembly and testing of devices from different silicon and technology providers.

Technology and design of an active-matrix OLED on crystalline silicon direct-view display for a wristwatch computer

NASA Astrophysics Data System (ADS)

Sanford, James L.; Schlig, Eugene S.; Prache, Olivier; Dove, Derek B.; Ali, Tariq A.; Howard, Webster E.

2002-02-01

The IBM Research Division and eMagin Corp. jointly have developed a low-power VGA direct view active matrix OLED display, fabricated on a crystalline silicon CMOS chip. The display is incorporated in IBM prototype wristwatch computers running the Linus operating system. IBM designed the silicon chip and eMagin developed the organic stack and performed the back-end-of line processing and packaging. Each pixel is driven by a constant current source controlled by a CMOS RAM cell, and the display receives its data from the processor memory bus. This paper describes the OLED technology and packaging, and outlines the design of the pixel and display electronics and the processor interface. Experimental results are presented.

Key Processes of Silicon-On-Glass MEMS Fabrication Technology for Gyroscope Application.

PubMed

Ma, Zhibo; Wang, Yinan; Shen, Qiang; Zhang, Han; Guo, Xuetao

2018-04-17

MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Materials and processing science: Limits for microelectronics

NASA Astrophysics Data System (ADS)

Rosenberg, R.

1988-09-01

The theme of this talk will be to illustrate examples of technologies that will drive materials and processing sciences to the limit and to describe some of the research being pursued to understand materials interactions which are pervasive to projected structure fabrication. It is to be expected that the future will see a progression to nanostructures where scaling laws will be tested and quantum transport will become more in evidence, to low temperature operation for tighter control and improved performance, to complex vertical profiles where 3D stacking and superlattices will produce denser packing and device flexibility, to faster communication links with optoelectronics, and to compatible packaging technologies. New low temperature processing techniques, such as epitaxy of silicon, PECVD of dielectrics, low temperature high pressure oxidation, silicon-germanium heterostructures, etc., must be combined with shallow metallurgies, new lithographic technologies, maskless patterning, rapid thermal processing (RTP) to produce needed profile control, reduce process incompatibilities and develop new device geometries. Materials interactions are of special consequence for chip substrates and illustrations of work in metal-ceramic and metal-polymer adhesion will be offered.

The establishment of a production-ready manufacturing process utilizing thin silicon substrates for solar cells

NASA Technical Reports Server (NTRS)

Pryor, R. A.

1980-01-01

Three inch diameter Czochralski silicon substrates sliced directly to 5 mil, 8 mil, and 27 mil thicknesses with wire saw techniques were procured. Processing sequences incorporating either diffusion or ion implantation technologies were employed to produce n+p or n+pp+ solar cell structures. These cells were evaluated for performance, ease of fabrication, and cost effectiveness. It was determined that the use of 7 mil or even 4 mil wafers would provide near term cost reductions for solar cell manufacturers.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Proton exchange membrane micro fuel cells on 3D porous silicon gas diffusion layers

NASA Astrophysics Data System (ADS)

Kouassi, S.; Gautier, G.; Thery, J.; Desplobain, S.; Borella, M.; Ventura, L.; Laurent, J.-Y.

2012-10-01

Since the 90's, porous silicon has been studied and implemented in many devices, especially in MEMS technology. In this article, we present a new approach to build miniaturized proton exchange membrane micro-fuel cells using porous silicon as a hydrogen diffusion layer. In particular, we propose an innovative process to build micro fuel cells from a “corrugated iron like” 3D structured porous silicon substrates. This structure is able to increase up to 40% the cell area keeping a constant footprint on the silicon wafer. We propose here a process route to perform electrochemically 3D porous gas diffusion layers and to deposit fuel cell active layers on such substrates. The prototype peak power performance was measured to be 90 mW cm-2 in a “breathing configuration” at room temperature. These performances are less than expected if we compare with a reference 2D micro fuel cell. Actually, the active layer deposition processes are not fully optimized but this prototype demonstrates the feasibility of these 3D devices.

Silicon pore optics for future x-ray telescopes

NASA Astrophysics Data System (ADS)

Wille, Eric; Bavdaz, Marcos; Wallace, Kotska; Shortt, Brian; Collon, Maximilien; Ackermann, Marcelo; Günther, Ramses; Olde Riekerink, Mark; Koelewijn, Arenda; Haneveld, Jeroen; van Baren, Coen; Erhard, Markus; Kampf, Dirk; Christensen, Finn; Krumrey, Michael; Freyberg, Michael; Burwitz, Vadim

2017-11-01

Lightweight X-ray Wolter optics with a high angular resolution will enable the next generation of X-ray telescopes in space. The candidate mission ATHENA (Advanced Telescope for High Energy Astrophysics) required a mirror assembly of 1 m2 effective area (at 1 keV) and an angular resolution of 10 arcsec or better. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is being developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor industry. We present the recent upgrades made to the manufacturing processes and equipment, ranging from the manufacture of single mirror plates towards complete focusing mirror modules mounted in flight configuration, and results from first vibration tests. The performance of the mirror modules is tested at X-ray facilities that were recently extended to measure optics at a focal distance up to 20 m.

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

Solid oxide membrane (SOM) process for ytterbium and silicon production from their oxides

NASA Astrophysics Data System (ADS)

Jiang, Yihong

The Solid oxide membrane (SOM) electrolysis is an innovative green technology that produces technologically important metals directly from their respective oxides. A yttria-stabilized zirconia (YSZ) tube, closed at one end is employed to separate the molten salt containing dissolved metal oxides from the anode inside the YSZ tube. When the applied electric potential between the cathode in the molten salt and the anode exceeds the dissociation potential of the desired metal oxides, oxygen ions in the molten salt migrate through the YSZ membrane and are oxidized at the anode while the dissolved metal cations in the flux are reduced to the desired metal at the cathode. Compared with existing metal production processes, the SOM process has many advantages such as one unit operation, less energy consumption, lower capital costs and zero carbon emission. Successful implementation of the SOM electrolysis process would provide a way to mitigate the negative environmental impact of the metal industry. Successful demonstration of producing ytterbium (Yb) and silicon (Si) directly from their respective oxides utilizing the SOM electrolysis process is presented in this dissertation. During the SOM electrolysis process, Yb2O3 was reduced to Yb metal on an inert cathode. The melting point of the supporting electrolyte (LiF-YbF3-Yb2O3) was determined by differential thermal analysis (DTA). Static stability testing confirmed that the YSZ tube was stable with the flux at operating temperature. Yb metal deposit on the cathode was confirmed by scanning electron microscopy (SEM) and energy dispersive x-ray spectroscopy (EDS). During the SOM electrolysis process for silicon production, a fluoride based flux based on BaF2, MgF2, and YF3 was engineered to serve as the liquid electrolyte for dissolving silicon dioxide. YSZ tube was used to separate the molten salt from an anode current collector in the liquid silver. Liquid tin was chosen as cathode to dissolve the reduced silicon during SOM electrolysis. After electrolysis, upon cooling, silicon crystals precipitated out from the Si-Sn liquid alloy. The presence of high-purity silicon crystals in the liquid tin cathode was confirmed by SEM/EDS. The fluoride based flux was also optimized to improve YSZ membrane stability for long-term use.

EDITORIAL: Special issue on silicon photonics

NASA Astrophysics Data System (ADS)

Reed, Graham; Paniccia, Mario; Wada, Kazumi; Mashanovich, Goran

2008-06-01

The technology now known as silicon photonics can be traced back to the pioneering work of Soref in the mid-1980s (see, for example, Soref R A and Lorenzo J P 1985 Electron. Lett. 21 953). However, the nature of the research conducted today, whilst it builds upon that early work, is unrecognizable in terms of technology metrics such as device efficiency, device data rate and device dimensions, and even in targeted applications areas. Today silicon photonics is still evolving, and is enjoying a period of unprecedented attention in terms of research focus. This has resulted in orders-of-magnitude improvement in device performance over the last few years to levels many thought were impossible. However, despite the existence of the research field for more than two decades, silicon is still regarded as a 'new' optical material, one that is being manipulated and modified to satisfy the requirements of a range of applications. This is somewhat ironic since silicon is one of the best known and most thoroughly studied materials, thanks to the electronics industry that has made silicon its material of choice. The principal reasons for the lack of study of this 'late developer' are that (i) silicon is an indirect bandgap material and (ii) it does not exhibit a linear electro-optic (Pockels) effect. The former condition means that it is difficult to make a laser in silicon based on the intrinsic performance of the material, and consequently, in recent years, researchers have attempted to modify the material to artificially engineer the conditions for lasing to be viable (see, for example, the review text, Jalali B et al 2008 Silicon Lasers in Silicon Photonics: The State of the Art ed G T Reed (New York: Wiley)). The latter condition means that optical modulators are intrinsically less efficient in silicon than in some other materials, particularly when targeting the popular telecommunications wavelengths around 1.55 μm. Therefore researchers have sought alternative mechanisms for modulation in silicon that have yielded increasingly impressive results (see, for example, Liao L et al 2007 Electron. Lett. 43 issue 22). The convergence of computing and communications and the resultant demand for increased bandwidth has been one of the factors influencing the upsurge of interest in silicon, together with the requirement for photonic and electronic integration, all to be realized at low cost. Thus emerging applications such as short-reach communications links for optical interconnect and fibre to the home (FTTH) (as well as a multitude of other applications) are frequently offered as examples of where silicon photonics will have a significant, perhaps a revolutionary, impact. One of the major conclusions of the joint MIT-industry Communication Technology Roadmap (http://mph-roadmap.mit.edu/index.php), was that 'Photonics technology will be driven by electronic-photonic synergy and short (<1 km) reach interconnection. This direction will ignite a major shift in leadership of the optical component industry from information transmission (telecom) to information processing (computing imaging).' Thus the case is made for low-cost implementation, making silicon a prime candidate, particularly if true electronic/photonic integration is to be realized. Despite the limitations of silicon as an optical material, the intrinsic advantages of the most popular silicon optical platform, silicon-on-insulator (SOI), should not be overlooked. The very high confinement nature of this technology platform brings a host of advantages, including the possibility to miniaturize devices and circuits, to reduce power consumption, optical loss and cost, to increase yield, and to be compatible with CMOS-based intelligence. Thus the limitations of silicon as an optical material can be offset against the very significant advantages, to both commercial as well as technological success. Of course, there is still much to do, hence the increasing global investment in silicon technology and the massive increase in research activity in silicon photonics since the early work in the 1980s. Only time will tell if silicon can realize its potential to satisfy the ever-increasing array of applications. However, the indications are positive, and the contributors to this cause employ increasingly impressive levels of intellectual and technological capability to realize the desired goals. It is an interesting time to be involved in slicon photonics, and it will be equally fascinating to watch the evolution of the technology in the future. Whatever happens, silicon will make the transition from being regarded as purely an electronic material to recognition as an optoelectronic material. The evidence for this is represented in the collection of papers that form this special issue of Semiconductor Science and Technology. This special issue is, in turn, representative of the rapidly increasing body of literature that represents the field of silicon photonics. In a field of such rapid transition as silicon photonics, the hope is that this special issue takes a snapshot of the technology at the time of publication, to document the progress of the field for future reference, and in turn to stimulate further work. The Guest Editors are grateful for the tireless support of Clare Bedrock at IOP Publishing.

Results from a first production of enhanced Silicon Sensor Test Structures produced by ITE Warsaw

NASA Astrophysics Data System (ADS)

Bergauer, T.; Dragicevic, M.; Frey, M.; Grabiec, P.; Grodner, M.; Hänsel, S.; Hartmann, F.; Hoffmann, K.-H.; Hrubec, J.; Krammer, M.; Kucharski, K.; Macchiolo, A.; Marczewski, J.

2009-01-01

Monitoring the manufacturing process of silicon sensors is essential to ensure stable quality of the produced detectors. During the CMS silicon sensor production we were utilising small Test Structures (TS) incorporated on the cut-away of the wafers to measure certain process-relevant parameters. Experience from the CMS production and quality assurance led to enhancements of these TS. Another important application of TS is the commissioning of new vendors. The measurements provide us with a good understanding of the capabilities of a vendor's process. A first batch of the new TS was produced at the Institute of Electron Technology in Warsaw Poland. We will first review the improvements to the original CMS test structures and then discuss a selection of important measurements performed on this first batch.

Silicon microelectronic field-emissive devices for advanced display technology

NASA Astrophysics Data System (ADS)

Morse, J. D.

1993-03-01

Field-emission displays (FED's) offer the potential advantages of high luminous efficiency, low power consumption, and low cost compared to AMLCD or CRT technologies. An LLNL team has developed silicon-point field emitters for vacuum triode structures and has also used thin-film processing techniques to demonstrate planar edge-emitter configurations. LLNL is interested in contributing its experience in this and other FED-related technologies to collaborations for commercial FED development. At LLNL, FED development is supported by computational capabilities in charge transport and surface/interface modeling in order to develop smaller, low-work-function field emitters using a variety of materials and coatings. Thin-film processing, microfabrication, and diagnostic/test labs permit experimental exploration of emitter and resistor structures. High field standoff technology is an area of long-standing expertise that guides development of low-cost spacers for FEDS. Vacuum sealing facilities are available to complete the FED production engineering process. Drivers constitute a significant fraction of the cost of any flat-panel display. LLNL has an advanced packaging group that can provide chip-on-glass technologies and three-dimensional interconnect generation permitting driver placement on either the front or the back of the display substrate.

Silicon ribbon growth by a capillary action shaping technique

NASA Technical Reports Server (NTRS)

Schwuttke, G. H.; Schwuttke, G. H.; Ciszek, T. F.; Kran, A.

1977-01-01

Substantial improvements in ribbon surface quality are achieved with a higher melt meniscus than that attainable with the film-fed (EFG) growth technique. A capillary action shaping method is described in which meniscus shaping for the desired ribbon geometry occurs at the vertex of a wettable die. As ribbon growth depletes the melt meniscus, capillary action supplies replacement material. Topics discussed cover experimental apparatus and growth procedures; die materials investigations, fabrication and evaluation; process development for 25 mm, 38 mm, 50 mm and 100 mm silicon ribbons; and long grain direct solidification of silicon. Methods for the structural and electrical characterization of cast silicon ribbons are assessed as well as silicon ribbon technology for the 1978 to 1986 period.

Silicon Micro- and Nanofabrication for Medicine

PubMed Central

Fine, Daniel; Goodall, Randy; Bansal, Shyam S.; Chiappini, Ciro; Hosali, Sharath; van de Ven, Anne L.; Srinivasan, Srimeenkashi; Liu, Xuewu; Godin, Biana; Brousseau, Louis; Yazdi, Iman K.; Fernandez-Moure, Joseph; Tasciotti, Ennio; Wu, Hung-Jen; Hu, Ye; Klemm, Steve; Ferrari, Mauro

2013-01-01

This manuscript constitutes a review of several innovative biomedical technologies fabricated using the precision and accuracy of silicon micro- and nanofabrication. The technologies to be reviewed are subcutaneous nanochannel drug delivery implants for the continuous tunable zero-order release of therapeutics, multi-stage logic embedded vectors for the targeted systemic distribution of both therapeutic and imaging contrast agents, silicon and porous silicon nanowires for investigating cellular interactions and processes as well as for molecular and drug delivery applications, porous silicon (pSi) as inclusions into biocomposites for tissue engineering, especially as it applies to bone repair and regrowth, and porous silica chips for proteomic profiling. In the case of the biocomposites, the specifically designed pSi inclusions not only add to the structural robustness, but can also promote tissue and bone regrowth, fight infection, and reduce pain by releasing stimulating factors and other therapeutic agents stored within their porous network. The common material thread throughout all of these constructs, silicon and its associated dielectrics (silicon dioxide, silicon nitride, etc.), can be precisely and accurately machined using the same scalable micro- and nanofabrication protocols that are ubiquitous within the semiconductor industry. These techniques lend themselves to the high throughput production of exquisitely defined and monodispersed nanoscale features that should eliminate architectural randomness as a source of experimental variation thereby potentially leading to more rapid clinical translation. PMID:23584841

Processing experiments on non-Czochralski silicon sheet

NASA Technical Reports Server (NTRS)

Pryor, R. A.; Grenon, L. A.; Sakiotis, N. G.; Pastirik, E. M.; Sparks, T. O.; Legge, R. N.

1981-01-01

A program is described which supports and promotes the development of processing techniques which may be successfully and cost-effectively applied to low-cost sheets for solar cell fabrication. Results are reported in the areas of process technology, cell design, cell metallization, and production cost simulation.

IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

2015-08-01

SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2011-06-08

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Atomic Scale Understanding of Poly-Si/SiO2/c-Si Passivated Contacts: Passivation Degradation Due to Metallization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aguiar, Jeffery A.; Young, David; Lee, Benjamin

2016-11-21

The key attributes for achieving high efficiency crystalline silicon solar cells include class leading developments in the ability to approach the theoretical limits of silicon solar technology (29.4% efficiency). The push for high efficiency devices is further compounded with the clear need for passivation to reduce recombination at the metal contacts. At the same time there is stringent requirement to retain the same material device quality, surface passivation, and performance characteristics following subsequent processing. The development of passivated silicon cell structures that retain active front and rear surface passivation and overall material cell quality is therefore a relevant and activemore » area of development. To address the potential outcomes of metallization on passivated silicon stack, we report on some common microstructural features of degradation due to metallization for a series of silicon device stacks. A fundamental materials understanding of the metallization process on retaining high-efficiency passivated Si devices is therefore gained over these series of results.« less

A MoTe2 based light emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Heuck, M.; Grosso, G.; Furchi, M.; Cao, Y.; Zheng, J.; Navarro-Moratalla, E.; Zhou, L.; Taniguchi, T.; Watanabe, K.; Kong, J.; Englund, D.; Jarillo-Herrero, P.

A key challenge in photonics today is to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, partly because many components such as waveguides, interferometers and modulators, could be integrated on silicon-based processors. However, light sources and photodetectors present continued challenges. Common approaches for light source include off-chip or wafer-bonded lasers based on III-V materials, but studies show advantages for directly modulated light sources. The most advanced photodetectors in silicon photonics are based on germanium growth which increases system cost. The emerging two dimensional transition metal dichalcogenides (TMDs) offer a path for optical interconnects components that can be integrated with the CMOS processing by back-end-of-the-line processing steps. Here we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with infrared band gap. The state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Micromachined needles and lancets with design adjustable bevel angles

NASA Astrophysics Data System (ADS)

Sparks, Douglas; Hubbard, Timothy

2004-08-01

A new method of micromachining hollow needles and two-dimensional needle arrays from single crystal silicon is described. The process involves a combination of fusion bonding, photolithography and anisotropic plasma etching. The cannula produced with this process can have design adjustable bevel angles, wall thickness and channel dimensions. A subset of processing steps can be employed to produce silicon blades and lancets with design adjustable bevel angles and shaft dimensions. Applications for this technology include painless drug infusion, blood diagnosis, glucose monitoring, cellular injection and the manufacture of microkeratomes for ocular, vascular and neural microsurgery.

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

2018-05-01

Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

In situ observation of shear-driven amorphization in silicon crystals

DOE Office of Scientific and Technical Information (OSTI.GOV)

He, Yang; Zhong, Li; Fan, Feifei

Amorphous materials have attracted great interest in the scientific and technological fields. An amorphous solid usually forms under the externally driven conditions of melt-quenching, irradiation and severe mechanical deformation. However, its dynamic formation process remains elusive. Here we report the in situ atomic-scale observation of dynamic amorphization processes during mechanical straining of nanoscale silicon crystals by high resolution transmission electron microscopy (HRTEM). We observe the shear-driven amorphization (SDA) occurring in a dominant shear band. The SDA involves a sequence of processes starting with the shear-induced diamond-cubic to diamond-hexagonal phase transition that is followed by dislocation nucleation and accumulation in themore » newly formed phase, leading to the formation of amorphous silicon. The SDA formation through diamond-hexagonal phase is rationalized by its structural conformity with the order in the paracrystalline amorphous silicon, which maybe widely applied to diamond-cubic materials. Besides, the activation of SDA is orientation-dependent through the competition between full dislocation nucleation and partial gliding.« less

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pope, C.S.

The future of the photovoltaic industry is discussed. The success of a small New Jersey high technology solar firm, Chronar, is described. The company started a modern, efficient commercial facility for the manufacture of 1 megawatt capacity amorphous silicon solar cells. The hatch manufacturing process consists of the deposition of the amorphous silicon layers in a machine called a 6 pack named for the six identical glow discharge chambers operated simultaneously by a mini-computer.

Reconfigurable Cellular Photonic Crystal Arrays (RCPA)

DTIC Science & Technology

2013-03-01

signal processing based on reconfigurable integrated optics devices. This technology has the potential to revolutionize the design circle of optical...Accomplishments III.A. Design and fabrication of an accumulation-mode modulator Figure 1(a) shows the schematic of a compact resonator on the double-Si... integration of silicon nitride on silicon-on-insulator platform to enhance the arsenal of photonic circuit designers . The coherent integration of

Harsh Environment Silicon Carbide Sensor Technology for Geothermal Instrumentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pisano, Albert P.

2013-04-26

This project utilizes Silicon Carbide (SiC) materials platform to fabricate advanced sensors to be used as high-temperature downhole instrumentation for the DOE’s Geothermal Technologies Program on Enhanced Geothermal Systems. The scope of the proposed research is to 1) develop a SiC pressure sensor that can operate in harsh supercritical conditions, 2) develop a SiC temperature sensor that can operate in harsh supercritical conditions, 3) develop a bonding process for adhering SiC sensor die to well casing couplers, and 4) perform experimental exposure testing of sensor materials and the sensor devices.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Six Sigma-based approach to optimise the diffusion process of crystalline silicon solar cell manufacturing

NASA Astrophysics Data System (ADS)

Prasad, A. Guru; Saravanan, S.; Gijo, E. V.; Dasari, Sreenivasa Murty; Tatachar, Raghu; Suratkar, Prakash

2016-02-01

Silicon-based photovoltaics (PV) plays the dominant role in the history of PV due to the continuous process and technology improvement in silicon solar cells and its manufacturing flow. In general, silicon solar cell process uses either p-type- or n-type-doped silicon as the starting material. Currently, most of the PV industries use p-type, boron-doped silicon wafer as the starting material. In this work too, the boron-doped wafers were considered as the starting material to create pn junction and phosphorus was used as n-type doping material. Industries use either phosphorous oxy chloride (POCl3) or ortho phosphoric acid (H3PO4) as the precursor for doping phosphorous. While the industries use POCl3 as the precursor, the throughput is lesser than that of the industries' use of H3PO4 due to the manufacturing limitations of the POCl3-based equipments. Hence, in order to achieve the operational excellence in POCl3-based equipments, business strategies such as the Six Sigma methodology have to be adapted. This paper describes the application of Six Sigma Define-Measure-Analyze-Improve-Control methodology for throughput improvement of the phosphorus doping process. The optimised recipe has been implemented in the production and it is running successfully. As a result of this project, an effective gain of 0.9 MW was reported per annum.

Photovoltaic research and development in Japan

NASA Technical Reports Server (NTRS)

Shimada, K.

1983-01-01

The status of the Japanese photovoltaic (PV) R&D activities was surveyed through literature searches, private communications, and site visits in 1982. The results show that the Japanese photovoltaic technology is maturing rapidly, consistent with the steady government funding under the Sunshine Project. Two main thrusts of the Project are: (1) completion of the solar panel production pilot plants using cast ingot and sheet silicon materials, and (2) development of large area amorphous silicon solar cells with acceptable efficiency (10 to 12%). An experimental automated solar panel production plant rated at 500 kW/yr is currently under construction for the Sunshine Project for completion in March 1983. Efficiencies demonstrated by experimental large are amorphous silicon solar cells are approaching 8%. Small area amorphous silicon solar cells are, however, currently being mass produced and marketed by several companies at an equivalent annual rate of 2 MW/yr for consumer electronic applications. There is no evidence of an immediate move by the Japanese PV industry to enter extensively into the photovoltaic power market, domestic or otherwise. However, the photovoltaic technology itself could become ready for such an entry in the very near future, especially by making use of advanced process automation technologies.

Low temperature spalling of silicon: A crack propagation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, themore » crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.« less

Thick-film materials for silicon photovoltaic cell manufacture

NASA Technical Reports Server (NTRS)

Field, M. B.

1977-01-01

Thick film technology is applicable to three areas of silicon solar cell fabrication; metallization, junction formation, and coating for protection of screened ohmic contacts, particularly wrap around contacts, interconnection and environmental protection. Both material and process parameters were investigated. Printed ohmic contacts on n- and p-type silicon are very sensitive to the processing parameters of firing time, temperature, and atmosphere. Wrap around contacts are easily achieved by first printing and firing a dielectric over the edge and subsequently applying a low firing temperature conductor. Interconnection of cells into arrays can be achieved by printing and cofiring thick film metal pastes, soldering, or with heat curing conductive epoxies on low cost substrates. Printed (thick) film vitreous protection coatings do not yet offer sufficient optical uniformity and transparency for use on silicon. A sprayed, heat curable SiO2 based resin shows promise of providing both optical matching and environmental protection.

A Microsystem Based on Porous Silicon-Glass Anodic Bonding for Gas and Liquid Optical Sensing

PubMed Central

De Stefano, Luca; Malecki, Krzysztof; Della Corte, Francesco G.; Moretti, Luigi; Rea, Ilaria; Rotiroti, Lucia; Rendina, Ivo

2006-01-01

We have recently presented an integrated silicon-glass opto-chemical sensor for lab-on-chip applications, based on porous silicon and anodic bonding technologies. In this work, we have optically characterized the sensor response on exposure to vapors of several organic compounds by means of reflectivity measurements. The interaction between the porous silicon, which acts as transducer layer, and the organic vapors fluxed into the glass sealed microchamber, is preserved by the fabrication process, resulting in optical path increase, due to the capillary condensation of the vapors into the pores. Using the Bruggemann theory, we have calculated the filled pores volume for each substance. The sensor dynamic has been described by time-resolved measurements: due to the analysis chamber miniaturization, the response time is only of 2 s. All these results have been compared with data acquired on the same PSi structure before the anodic bonding process.

Inexpensive method for producing macroporous silicon particulates (MPSPs) with pyrolyzed polyacrylonitrile for lithium ion batteries

PubMed Central

Thakur, Madhuri; Sinsabaugh, Steven L.; Isaacson, Mark J.; Wong, Michael S.; Biswal, Sibani Lisa

2012-01-01

One of the most exciting areas in lithium ion batteries is engineering structured silicon anodes. These new materials promise to lead the next generation of batteries with significantly higher reversible charge capacity than current technologies. One drawback of these materials is that their production involves costly processing steps, limiting their application in commercial lithium ion batteries. In this report we present an inexpensive method for synthesizing macroporous silicon particulates (MPSPs). After being mixed with polyacrylonitrile (PAN) and pyrolyzed, MPSPs can alloy with lithium, resulting in capacities of 1000 mAhg−1 for over 600+ cycles. These sponge-like MPSPs with pyrolyzed PAN (PPAN) can accommodate the large volume expansion associated with silicon lithiation. This performance combined with low cost processing yields a competitive anode material that will have an immediate and direct application in lithium ion batteries. PMID:23139860

Very low temperature materials and self-alignment technology for amorphous hydrated silicon thin film transistors fabricated on transparent large area plastic substrates

NASA Astrophysics Data System (ADS)

Yang, Chien-Sheng

The purpose of this research has been to (1) explore materials prepared using plasma enhanced chemical vapor deposition (PECVD) at 110sp°C for amorphous silicon thin film transistors (TFT's) fabricated on low temperature compatible, large area flexible polyethylene terephthalate (PET) substrates, and (2) develop full self-alignment technology using selective area n+ PECVD for source/drain contacts of amorphous silicon TFT's. For item (1), silicon nitride films, as gate dielectrics of TFT's, were deposited using SiHsb4+NHsb3, SiHsb4+NHsb3+Nsb2, SiHsb4+NHsb3+He, or SiHsb4+NHsb3+Hsb2 gases. Good quality silicon nitride films can be deposited using a SiHsb4+NHsb3 gas with high NHsb3/SiHsb4 ratios, or using a SiHsb4+NHsb3+Nsb2 gas with moderate NHsb3/SiHsb4 ratios. A chemical model was proposed to explain the Nsb2 dilution effect. This model includes calculations of (a) the electron energy distribution function in a plasma, (b) rate constants of electron impact dissociation, and (3) the (NHsbx) / (SiHsby) ratio in a plasma. The Nsb2 dilution was shown to have a effect of shifting the electron energy distribution into high energy, thus enhancing the (NHsbx) / (SiHsbyrbrack ratio in a plasma and promoting the deposition of N-rich silicon nitride films, which leads to decreased trap state density and a shift in trap state density to deeper in the gap. Amorphous silicon were formed successfully at 110sp°C on large area glass and plastic(PET) substrates. Linear mobilities are 0.33 and 0.12 cmsp2/Vs for TFT's on glass and plastic substrates, respectively. ON/OFF current ratios exceed 10sp7 for TFT's on glass and 10sp6 for TFT's on PET. For item (2), a novel full self-alignment process was developed for amorphous silicon TFT's. This process includes (1) back-exposure using the bottom gate metal as the mask, and (2) selective area n+ micro-crystalline silicon PECVD for source/drain contacts of amorphous silicon TFT's. TFT's fabricated using the full self-alignment process showed linear mobilities ranging from 0.5 to 1.0 cmsp2/Vs.

Optimization of pH sensing using silicon nanowire field effect transistors with HfO2 as the sensing surface.

PubMed

Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak

2011-10-07

Silicon nanowire field effect transistor sensors with SiO(2)/HfO(2) as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO(2) as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

Review of the Potential of the Ni/Cu Plating Technique for Crystalline Silicon Solar Cells

PubMed Central

Rehman, Atteq ur; Lee, Soo Hong

2014-01-01

Developing a better method for the metallization of silicon solar cells is integral part of realizing superior efficiency. Currently, contact realization using screen printing is the leading technology in the silicon based photovoltaic industry, as it is simple and fast. However, the problem with metallization of this kind is that it has a lower aspect ratio and higher contact resistance, which limits solar cell efficiency. The mounting cost of silver pastes and decreasing silicon wafer thicknesses encourages silicon solar cell manufacturers to develop fresh metallization techniques involving a lower quantity of silver usage and not relying pressing process of screen printing. In recent times nickel/copper (Ni/Cu) based metal plating has emerged as a metallization method that may solve these issues. This paper offers a detailed review and understanding of a Ni/Cu based plating technique for silicon solar cells. The formation of a Ni seed layer by adopting various deposition techniques and a Cu conducting layer using a light induced plating (LIP) process are appraised. Unlike screen-printed metallization, a step involving patterning is crucial for opening the masking layer. Consequently, experimental procedures involving patterning methods are also explicated. Lastly, the issues of adhesion, back ground plating, process complexity and reliability for industrial applications are also addressed. PMID:28788516

Review of the Potential of the Ni/Cu Plating Technique for Crystalline Silicon Solar Cells.

PubMed

Rehman, Atteq Ur; Lee, Soo Hong

2014-02-18

Developing a better method for the metallization of silicon solar cells is integral part of realizing superior efficiency. Currently, contact realization using screen printing is the leading technology in the silicon based photovoltaic industry, as it is simple and fast. However, the problem with metallization of this kind is that it has a lower aspect ratio and higher contact resistance, which limits solar cell efficiency. The mounting cost of silver pastes and decreasing silicon wafer thicknesses encourages silicon solar cell manufacturers to develop fresh metallization techniques involving a lower quantity of silver usage and not relying pressing process of screen printing. In recent times nickel/copper (Ni/Cu) based metal plating has emerged as a metallization method that may solve these issues. This paper offers a detailed review and understanding of a Ni/Cu based plating technique for silicon solar cells. The formation of a Ni seed layer by adopting various deposition techniques and a Cu conducting layer using a light induced plating (LIP) process are appraised. Unlike screen-printed metallization, a step involving patterning is crucial for opening the masking layer. Consequently, experimental procedures involving patterning methods are also explicated. Lastly, the issues of adhesion, back ground plating, process complexity and reliability for industrial applications are also addressed.

Silicon carbide semiconductor technology for high temperature and radiation environments

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.

1993-01-01

Viewgraphs on silicon carbide semiconductor technology and its potential for enabling electronic devices to function in high temperature and high radiation environments are presented. Topics covered include silicon carbide; sublimation growth of 6H-SiC boules; SiC chemical vapor deposition reaction system; 6H silicon carbide p-n junction diode; silicon carbide MOSFET; and silicon carbide JFET radiation response.

Silicon Micromachining for Terahertz Component Development

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Reck, Theodore J.; Jung-Kubiak, Cecile; Siles, Jose V.; Lee, Choonsup; Lin, Robert; Mehdi, Imran

2013-01-01

Waveguide component technology at terahertz frequencies has come of age in recent years. Essential components such as ortho-mode transducers (OMT), quadrature hybrids, filters, and others for high performance system development were either impossible to build or too difficult to fabricate with traditional machining techniques. With micromachining of silicon wafers coated with sputtered gold it is now possible to fabricate and test these waveguide components. Using a highly optimized Deep Reactive Ion Etching (DRIE) process, we are now able to fabricate silicon micromachined waveguide structures working beyond 1 THz. In this paper, we describe in detail our approach of design, fabrication, and measurement of silicon micromachined waveguide components and report the results of a 1 THz canonical E-plane filter.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Low-cost solar array project progress and plans

NASA Technical Reports Server (NTRS)

Callaghan, W. T.

1981-01-01

The considered project is part of the DOE Photovoltaic Technology and Market Development Program. This program is concerned with the development and the utilization of cost-competitive photovoltaic systems. The project has the objective to develop, by 1986, the national capability to manufacture low-cost, long-life photovoltaic arrays at production rates that will realize economies of scale, and at a price of less than $0.70/watt. The array performance objectives include an efficiency greater than 10% and an operating lifetime longer than 20 years. The objective of the silicon material task is to establish the practicality of processes for producing silicon suitable for terrestrial photovoltaic applications at a price of $14/kg. The large-area sheet task is concerned with the development of process technology for sheet formation. Low-cost encapsulation material systems are being developed in connection with the encapsulation task. Another project goal is related to the development of economical process sequences.

Nanofluidic interfaces in microfluidic networks

DOE PAGES

Millet, Larry J.; Doktycz, Mitchel John; Retterer, Scott T.

2015-09-24

The integration of nano- and microfluidic technologies enables the construction of tunable interfaces to physical and biological systems across relevant length scales. The ability to perform chemical manipulations of miniscule sample volumes is greatly enhanced through these technologies and extends the ability to manipulate and sample the local fluidic environments at subcellular, cellular and community or tissue scales. Here we describe the development of a flexible surface micromachining process for the creation of nanofluidic channel arrays integrated within SU-8 microfluidic networks. The use of a semi-porous, silicon rich, silicon nitride structural layer allows rapid release of the sacrificial silicon dioxidemore » during the nanochannel fabrication. Nanochannel openings that form the interface to biological samples are customized using focused ion beam milling. The compatibility of these interfaces with on-chip microbial culture is demonstrated.« less

High-productivity DRIE solutions for 3D-SiP and MEMS volume manufacturing

NASA Astrophysics Data System (ADS)

Puech, M.; Thevenoud, J. M.; Launay, N.; Arnal, N.; Godinat, P.; Andrieu, B.; Gruffat, J. M.

2006-12-01

Emerging 3D-SiP technologies and high volume MEMS applications require high productivity mass production DRIE systems. The Alcatel DRIE product range has recently been optimized to reach the highest process and hardware production performances. A study based on sub-micron high aspect ratio structures encountered in the most stringent 3D-SiP has been carried out. The optimization of the Bosch process parameters have shown ultra high silicon etch rate, with unrivaled uniformity and repeatability leading to excellent process yields. In parallel, most recent hardware and proprietary design optimization including vacuum pumping lines, process chamber, wafer chucks, pressure control system, gas delivery are discussed. A key factor for achieving the highest performances was the recognized expertise of Alcatel vacuum and plasma science technologies. These improvements have been monitored in a mass production environment for a mobile phone application. Field data analysis shows a significant reduction of cost of ownership thanks to increased throughput and much lower running costs. These benefits are now available for all 3D-SiP and high volume MEMS applications. The typical etched patterns include tapered trenches for CMOS imagers, through silicon via holes for die stacking, well controlled profile angle for 3D high precision inertial sensors, and large exposed area features for inkjet printer head and Silicon microphones.

Production and use of metals and oxygen for lunar propulsion

NASA Technical Reports Server (NTRS)

Hepp, Aloysius F.; Linne, Diane L.; Landis, Geoffrey A.; Groth, Mary F.; Colvin, James E.

1991-01-01

Production, power, and propulsion technologies for using oxygen and metals derived from lunar resources are discussed. The production process is described, and several of the more developed processes are discussed. Power requirements for chemical, thermal, and electrical production methods are compared. The discussion includes potential impact of ongoing power technology programs on lunar production requirements. The performance potential of several possible metal fuels including aluminum, silicon, iron, and titanium are compared. Space propulsion technology in the area of metal/oxygen rocket engines is discussed.

The 17th Project Integration Meeting

NASA Technical Reports Server (NTRS)

Mcdonald, R. R.

1981-01-01

Progress made by the Low-Cost Solar Array Project during the period September 1980 to February 1981 is described. Included are reports on project analysis and integration; technology development in silicon material, large-area silicon sheet and encapsulation; production process and equipment development; engineering, and operations. A report on and copies of visual presentations made at the Project Integration Meeting held at Pasadena, California on February 4 and 5, 1981 are also included.

Defects and device performance

NASA Technical Reports Server (NTRS)

Storti, G.; Armstrong, R.; Johnson, S.; Lin, H. C.; Regnault, W.; Yoo, K. C.

1985-01-01

The necessity for a low-cost crystalline silicon sheet material for photovoltaics has generated a number of alternative crystal growth techniques that would replace Czochralski (Cz) and float-zone (FZ) technologies. Efficiencies of devices fabricated from low resistivity FZ silicon are approaching 20%, and it is highly likely that this value will be superseded in the near future. However, FZ silicon is expensive, and is unlikely ever to be used for photovoltaics. Cz silicon has many of the desirable qualities of FZ except that minority-carrier lifetimes at lower resistivities are significantly less than those of FZ silicon. Even with Cz silicon, it is unlikely that cost goals can be met because of the poor-material yield that results from sawing and other aspects of the crystal rowth. Although other silicon sheet technologies have been investigated, almost all have characteristics that limit efficiency to approx. 16%. In summary, 20% efficient solar cells can likely be fabricated from both FZ and Cz silicon, but costs are likely to be ultimately unacceptable. Alternate silicon technologies are not likely to achieve this goal, but cost per watt figures may be eventually better than either of the single crystal technologies and may rival any thin-film technology.

High-speed detection at two micrometres with monolithic silicon photodiodes

NASA Astrophysics Data System (ADS)

Ackert, Jason J.; Thomson, David J.; Shen, Li; Peacock, Anna C.; Jessop, Paul E.; Reed, Graham T.; Mashanovich, Goran Z.; Knights, Andrew P.

2015-06-01

With continued steep growth in the volume of data transmitted over optical networks there is a widely recognized need for more sophisticated photonics technologies to forestall a ‘capacity crunch’. A promising solution is to open new spectral regions at wavelengths near 2 μm and to exploit the long-wavelength transmission and amplification capabilities of hollow-core photonic-bandgap fibres and the recently available thulium-doped fibre amplifiers. To date, photodetector devices for this window have largely relied on III-V materials or, where the benefits of integration with silicon photonics are sought, GeSn alloys, which have been demonstrated thus far with only limited utility. Here, we describe a silicon photodiode operating at 20 Gbit s-1 in this wavelength region. The detector is compatible with standard silicon processing and is integrated directly with silicon-on-insulator waveguides, which suggests future utility in silicon-based mid-infrared integrated optics for applications in communications.

Ion beam figuring of silicon aspheres

NASA Astrophysics Data System (ADS)

Demmler, Marcel; Zeuner, Michael; Luca, Alfonz; Dunger, Thoralf; Rost, Dirk; Kiontke, Sven; Krüger, Marcus

2011-03-01

Silicon lenses are widely used for infrared applications. Especially for portable devices the size and weight of the optical system are very important factors. The use of aspherical silicon lenses instead of spherical silicon lenses results in a significant reduction of weight and size. The manufacture of silicon lenses is more challenging than the manufacture of standard glass lenses. Typically conventional methods like diamond turning, grinding and polishing are used. However, due to the high hardness of silicon, diamond turning is very difficult and requires a lot of experience. To achieve surfaces of a high quality a polishing step is mandatory within the manufacturing process. Nevertheless, the required surface form accuracy cannot be achieved through the use of conventional polishing methods because of the unpredictable behavior of the polishing tools, which leads to an unstable removal rate. To overcome these disadvantages a method called Ion Beam Figuring can be used to manufacture silicon lenses with high surface form accuracies. The general advantage of the Ion Beam Figuring technology is a contactless polishing process without any aging effects of the tool. Due to this an excellent stability of the removal rate without any mechanical surface damage is achieved. The related physical process - called sputtering - can be applied to any material and is therefore also applicable to materials of high hardness like Silicon (SiC, WC). The process is realized through the commercially available ion beam figuring system IonScan 3D. During the process, the substrate is moved in front of a focused broad ion beam. The local milling rate is controlled via a modulated velocity profile, which is calculated specifically for each surface topology in order to mill the material at the associated positions to the target geometry. The authors will present aspherical silicon lenses with very high surface form accuracies compared to conventionally manufactured lenses.

Phase 1 of the automated array assembly task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Coleman, M. G.; Pryor, R. A.; Grenon, L. A.; Lesk, I. A.

1977-01-01

The state of technology readiness for the automated production of solar cells and modules is reviewed. Individual process steps and process sequences for making solar cells and modules were evaluated both technically and economically. High efficiency with a suggested cell goal of 15% was stressed. It is concluded that the technology exists to manufacture solar cells which will meet program goals.

Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Hsieh, I.-Wei

In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic devices are quite different from those of electronic devices. Minimizing propagation losses by reducing sidewall roughness to nanometer scale over a device length of several millimeters or even centimeters has prompted researchers in academia and industry to refine the fabrication process. Chapter 3 of this thesis summarizes our efforts in fabricating silicon photonic devices using standard CMOS technology. Chapter 4 describes the characterization of nonlinear effects, including self-phase modulation (SPM), cross-phase modulation (XPM), and supercontinuum generation in silicon-wire waveguides. Silicon-wire waveguides are strip waveguides with submicron transverse dimensions, which allow strong light confinement inside the silicon core. This strong optical confinement, in addition to the large third-order nonlinear optical susceptibility of crystalline silicon, leads to a net nonlinearity which is several orders of magnitude higher than the nonlinearity of silica fiber. Significant nonlinear effects can be observed and characterized over a device length of only several millimeters in silicon wires with very small input power. These effects provide opportunities for engineers to design active silicon photonic devices which are compact and energy-efficient. Chapter 5 presents a realization of an integrated SOI optical isolator, which is a critical yet often overlooked component in photonic integrated circuits. This study shows the feasibility to make a hybrid garnet/SOI active device with very promising results. Finally, Chapter 6 summarizes our demonstration of transmitting terabit-scale data streams in silicon-wire waveguides, which is an important first-step towards enabling intra-chip interconnection networks with ultra-high bandwidths. Although the scope of this thesis is limited to providing only fractional views of the whole silicon photonics area, it provides enough references for interested readers to conduct further literature research in other aspects of silicon photonics. It is the author's hope that the thesis would convey to its readers the significance and potential of this exciting emerging technology.

Packaging of ferroelectric liquid crystal-on-silicon spatial light modulators

NASA Astrophysics Data System (ADS)

Lin, W.; Morozova, Nina D.; Ju, TehHua; Zhang, Weidong; Lee, Yung-Cheng; McKnight, Douglas J.; Johnson, Kristina M.

1996-11-01

A self-pulling soldering technology has been demonstrated for assembling liquid crystal on silicon (LCOS) spatial light modulators (SLMs). One of the major challenges in manufacturing the LCOS modules is to reproducibly control the thickness of the gap between the very large scale integrated circuit (VLSI) chip and the cover glass. The liquid crystal material is sandwiched between the VLSI chop and the cover glass which is coated with a transparent conductor. Solder joints with different profiles and sizes have been designed to provide surface tension forces to control the gap accommodating the ferroelectric liquid crystal layer in the range of a micron level with sub- micron uniformity. The optimum solder joint design is defined as a joint that results in the maximum pulling force. This technology provides an automatic, batch assembly process for a LCOS SLM through one reflow process. Fluxless soldering technology is used to assemble the module. This approach avoids residues from chemical of flux and oxides, and eliminates potential contamination to the device. Two different LCOS SLM designs and the process optimization are described.

Qualification of silicon pore optics

NASA Astrophysics Data System (ADS)

Wille, Eric; Bavdaz, Marcos; Fransen, Sebastiaan; Collon, Maximilien; Ackermann, Marcelo; Guenther, Ramses; Chatbi, Abdelhakim; Vacanti, Giuseppe; Vervest, Mark; van Baren, Coen; Haneveld, Jeroen; Riekerink, Mark Olde; Koelewijn, Arenda; Kampf, Dirk; Zuknik, Karl-Heinz; Reutlinger, Arnd

2014-07-01

Silicon Pore Optics (SPO) are the enabling technology for ESA's second large class mission in the Cosmic Vision programme. As for every space hardware, a critical qualification process is required to verify the suitability of the SPO mirror modules surviving the launch loads and maintaining their performance in the space environment. We present recent design modifications to further strengthen the mounting system (brackets and dowel pins) against mechanical loads. The progress of a formal qualification test campaign with the new mirror module design is shown. We discuss mechanical and thermal limitations of the SPO technology and provide recommendations for the mission design of the next X-ray Space Observatory.

Self-aligned process for forming microlenses at the tips of vertical silicon nanowires by atomic layer deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dan, Yaping, E-mail: yaping.dan@sjtu.edu.cn; Chen, Kaixiang; Crozier, Kenneth B.

The microlens is a key enabling technology in optoelectronics, permitting light to be efficiently coupled to and from devices such as image sensors and light-emitting diodes. Their ubiquitous nature motivates the development of new fabrication techniques, since existing methods face challenges as microlenses are scaled to smaller dimensions. Here, the authors demonstrate the formation of microlenses at the tips of vertically oriented silicon nanowires via a rapid atomic layer deposition process. The nature of the process is such that the microlenses are centered on the nanowires, and there is a self-limiting effect on the final sizes of the microlenses arisingmore » from the nanowire spacing. Finite difference time domain electromagnetic simulations are performed of microlens focusing properties, including showing their ability to enhance visible-wavelength absorption in silicon nanowires.« less

Low-cost solar array progress and plans

NASA Astrophysics Data System (ADS)

Callaghan, W. T.

It is pointed out that significant redirection has occurred in the U.S. Department of Energy (DOE) Photovoltaics Program, and thus in the Flat-Plate Solar Array Project (FSA), since the 3rd European Communities Conference. The Silicon Materials Task has now the objective to sponsor theoretical and experimental research on silicon material refinement technology suitable for photovoltaic flat-plate solar arrays. With respect to the hydrochlorination reaction, a process proof of concept was completed through definition of reaction kinetics, catalyst, and reaction characteristics. In connection with the dichlorosilane chemical vapor desposition process, a preliminary design was completed of an experimental process system development unit with a capacity of 100 to 200 MT/yr of Si.Attention is also given to the silicon-sheet formation research area, environmental isolation research, the cell and module formation task, the engineering sciences area, and the module performance and failure analysis area.

Low cost Czochralski crystal growing technology. Near implementation of the flat plate photovoltaic cost reduction of the low cost solar array project

NASA Technical Reports Server (NTRS)

Roberts, E. G.

1980-01-01

Equipment developed for the manufacture of over 100 kg of silicon ingot from one crucible by rechanging from another crucible is described. Attempts were made to eliminate the cost of raising the furnace temperature to 250 C above the melting point of silicon by using an RF coil to melt polycrystalline silicon rod as a means of rechanging the crucible. Microprocessor control of the straight growth process was developed and domonstrated for both 4 inch and 6 inch diameter. Both meltdown and melt stabilization processes were achieved using operator prompting through the microprocessor. The use of the RF work coil in poly rod melting as a heat sink in the accelerated growth process was unsuccessful. The total design concept for fabrication and interfacing of the total cold crucible system was completed.

LCoS-SLM technology based on Digital Electro-optics Platform and using in dynamic optics for application development

NASA Astrophysics Data System (ADS)

Tsai, Chun-Wei; Wang, Chen; Lyu, Bo-Han; Chu, Chen-Hsien

2017-08-01

Digital Electro-optics Platform is the main concept of Jasper Display Corp. (JDC) to develop various applications. These applications are based on our X-on-Silicon technologies, for example, X-on-Silicon technologies could be used on Liquid Crystal on Silicon (LCoS), Micro Light-Emitting Diode on Silicon (μLEDoS), Organic Light-Emitting Diode on Silicon (OLEDoS), and Cell on Silicon (CELLoS), etc. LCoS technology is applied to Spatial Light Modulator (SLM), Dynamic Optics, Wavelength Selective Switch (WSS), Holographic Display, Microscopy, Bio-tech, 3D Printing and Adaptive Optics, etc. In addition, μLEDoS technology is applied to Augmented Reality (AR), Head Up Display (HUD), Head-mounted Display (HMD), and Wearable Devices. Liquid Crystal on Silicon - Spatial Light Modulator (LCoSSLM) based on JDC's On-Silicon technology for both amplitude and phase modulation, have an expanding role in several optical areas where light control on a pixel-by-pixel basis is critical for optimum system performance. Combination of the advantage of hardware and software, we can establish a "dynamic optics" for the above applications or more. Moreover, through the software operation, we can control the light more flexible and easily as programmable light processor.

High surface area silicon materials: fundamentals and new technology.

PubMed

Buriak, Jillian M

2006-01-15

Crystalline silicon forms the basis of just about all computing technologies on the planet, in the form of microelectronics. An enormous amount of research infrastructure and knowledge has been developed over the past half-century to construct complex functional microelectronic structures in silicon. As a result, it is highly probable that silicon will remain central to computing and related technologies as a platform for integration of, for instance, molecular electronics, sensing elements and micro- and nanoelectromechanical systems. Porous nanocrystalline silicon is a fascinating variant of the same single crystal silicon wafers used to make computer chips. Its synthesis, a straightforward electrochemical, chemical or photochemical etch, is compatible with existing silicon-based fabrication techniques. Porous silicon literally adds an entirely new dimension to the realm of silicon-based technologies as it has a complex, three-dimensional architecture made up of silicon nanoparticles, nanowires, and channel structures. The intrinsic material is photoluminescent at room temperature in the visible region due to quantum confinement effects, and thus provides an optical element to electronic applications. Our group has been developing new organic surface reactions on porous and nanocrystalline silicon to tailor it for a myriad of applications, including molecular electronics and sensing. Integration of organic and biological molecules with porous silicon is critical to harness the properties of this material. The construction and use of complex, hierarchical molecular synthetic strategies on porous silicon will be described.

Investigating reliability attributes of silicon photovoltaic cells - An overview

NASA Technical Reports Server (NTRS)

Royal, E. L.

1982-01-01

Reliability attributes are being developed on a wide variety of advanced single-crystal silicon solar cells. Two separate investigations: cell-contact integrity (metal-to-silicon adherence), and cracked cells identified with fracture-strength-reducing flaws are discussed. In the cell-contact-integrity investigation, analysis of contact pull-strength data shows that cell types made with different metallization technologies, i.e., vacuum, plated, screen-printed and soldered, have appreciably different reliability attributes. In the second investigation, fracture strength was measured using Czochralski wafers and cells taken at various stages of processing and differences were noted. Fracture strength, which is believed to be governed by flaws introduced during wafer sawing, was observed to improve (increase) after chemical polishing and other process steps that tend to remove surface and edge flaws.

Erosion mechanisms of monocrystalline silicon under a microparticle laden air jet

NASA Astrophysics Data System (ADS)

Li, Q. L.; Wang, J.; Huang, C. Z.

2008-08-01

Microabrasive air-jet machining is considered as a promising precision processing technology for silicon substrates. In this paper, the impressions produced on a monocrystalline silicon by the impacts of microsolid particles entrained by an air jet and the associated microscopic erosion mechanisms are presented and discussed. It is shown that the impressions can be classified into three categories, namely, craters, scratches, and microdents, of which two types of craters and two types of scratches can lead to large-scale fractures. Craters with cleavage fracture surfaces have been found to play an important role in the material removal process. In addition, it is shown that most particles bounced away from the target surface without sliding or rolling during an impact so that most impressions formed are crater-type erosions.

Amorphous silicon as high index photonic material

NASA Astrophysics Data System (ADS)

Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

2009-05-01

Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

Light trapping in a-Si/c-Si heterojunction solar cells by embedded ITO nanoparticles at rear surface

NASA Astrophysics Data System (ADS)

Dhar, Sukanta; Mandal, Sourav; Mitra, Suchismita; Ghosh, Hemanta; Mukherjee, Sampad; Banerjee, Chandan; Saha, Hiranmoy; Barua, A. K.

2017-12-01

The advantages of the amorphous silicon (a-Si)/crystalline silicon (c-Si) hetero junction technology are low temperature (<200 °C) processing and fewer process steps to fabricate the device. In this work, we used indium tin oxide (ITO) nanoparticles embedded in amorphous silicon material at the rear side of the crystalline wafer. The nanoparticles were embedded in silicon to have higher scattering efficiency, as has been established by simulation studies. It has been shown that significant photocurrent enhancements (32.8 mA cm-2 to 35.1 mA cm-2) are achieved because of high scattering and coupling efficiency of the embedded nanoparticles into the silicon device, leading to an increase in efficiency from 13.74% to 15.22%. In addition, we have observed a small increase in open circuit voltage. This may be due to the surface passivation during the ITO nanoparticle formation with hydrogen plasma treatment. We also support our experimental results by simulation, with the help of a commercial finite-difference time-domain (FDTD) software solution.

An innovative large scale integration of silicon nanowire-based field effect transistors

NASA Astrophysics Data System (ADS)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Novel silicon crystals and method for their preparation

NASA Technical Reports Server (NTRS)

Authier, B.

1977-01-01

Plate shaped silicon crystals and their preparation by pouring a silicon melt into a suitable mold and then allowing it to solidify in a temperature gradient were investigated. The production of energy by direct conversion of solar energy into electrical energy by means of solar cells takes on increasing importance. While this type of energy production is already the prevailing form today in the realm of satellite technology, its terrestrial application has thus far encountered strict limitations owing to the high price of such solar cells. Of the greatest interest in this connection are silicon cells. A substantial reduction in the semiconductor material costs and the costs involved in the further processing to make solar cells are prerequisites for a rational market growth for solar energy.

The role of printing techniques for large-area dye sensitized solar cells

NASA Astrophysics Data System (ADS)

Mariani, Paolo; Vesce, Luigi; Di Carlo, Aldo

2015-10-01

The versatility of printing technologies and their intrinsic ability to outperform other techniques in large-area deposition gives scope to revolutionize the photovoltaic (PV) manufacturing field. Printing methods are commonly used in conventional silicon-based PVs to cover part of the production process. Screen printing techniques, for example, are applied to deposit electrical contacts on the silicon wafer. However, it is with the advent of third generation PVs that printing/coating techniques have been extensively used in almost all of the manufacturing processes. Among all the third generation PVs, dye sensitized solar cell (DSSC) technology has been developed up to commercialization levels. DSSCs and modules can be fabricated by adopting all of the main printing techniques on both rigid and flexible substrates. This allows an easy tuning of cell/module characteristics to the desired application. Transparency, colour, shape, layout and other DSSC’s features can be easily varied by changing the printing parameters and paste/ink formulations used in the printing process. This review focuses on large-area printing/coating technologies for the fabrication of DSSCs devices. The most used and promising techniques are presented underlining the process parameters and applications.

Silicon Carbide Technologies for Lightweighted Aerospace Mirrors

NASA Astrophysics Data System (ADS)

Matson, L.; Chen, M.; Deblonk, B.; Palusinski, I.

The use of monolithic glass and beryllium to produce lightweighted aerospace mirror systems has reached its limits due to the long lead times, high processing costs, environmental effects and launch load/weight requirements. New material solutions and manufacturing processes are required to meet DoD's directed energy weapons, reconnaissance/surveillance, and secured communications needs. Over the past several years the Air Force, MDA, and NASA has focused their efforts on the fabrication, lightweighting, and scale-up of numerous silicon carbide (SiC) based materials. It is anticipated that SiC can be utilized for most applications from cryogenic to high temperatures. This talk will focus on describing the SOA for these (near term) SiC technology solutions for making mirror structural substrates, figuring and finishing technologies being investigated to reduce cost time and cost, and non-destructive evaluation methods being investigated to help eliminate risk. Mirror structural substrates made out of advanced engineered materials (far term solutions) such as composites, foams, and microsphere arrays for ultra lightweighting will also be briefly discussed.

Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

PubMed

Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

2013-05-06

Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

Technology for Solar Array Production on the Moon

NASA Technical Reports Server (NTRS)

Landis, Geoffrey A.

2002-01-01

Silicon, aluminum, and glass are the primary raw materials that will be required for production of solar arrays on the moon. A process sequence is proposed for producing these materials from lunar regolith is proposed, consisting of separating the required materials from lunar rock with fluorine. Fluorosilane produced by this process is reduced to silicon; the fluorine salts are reduced to metals by reaction with metallic potassium. Fluorine is recovered from residual MgF and CaF2 by reaction with K2O. Aluminum, calcium oxide, and magnesium oxide are recovered to manufacture structural materials and glass.

Advanced detectors and signal processing

NASA Technical Reports Server (NTRS)

Greve, D. W.; Rasky, P. H. L.; Kryder, M. H.

1986-01-01

Continued progress is reported toward development of a silicon on garnet technology which would allow fabrication of advanced detection and signal processing circuits on bubble memories. The first integrated detectors and propagation patterns have been designed and incorporated on a new mask set. In addition, annealing studies on spacer layers are performed. Based on those studies, a new double layer spacer is proposed which should reduce contamination of the silicon originating in the substrate. Finally, the magnetic sensitivity of uncontaminated detectors from the last lot of wafers is measured. The measured sensitivity is lower than anticipated but still higher than present magnetoresistive detectors.

On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

NASA Astrophysics Data System (ADS)

Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

2018-04-01

The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

Optical MEMS platform for low-cost on-chip integration of planar light circuits and optical switching

NASA Astrophysics Data System (ADS)

German, Kristine A.; Kubby, Joel; Chen, Jingkuang; Diehl, James; Feinberg, Kathleen; Gulvin, Peter; Herko, Larry; Jia, Nancy; Lin, Pinyen; Liu, Xueyuan; Ma, Jun; Meyers, John; Nystrom, Peter; Wang, Yao Rong

2004-07-01

Xerox Corporation has developed a technology platform for on-chip integration of latching MEMS optical waveguide switches and Planar Light Circuit (PLC) components using a Silicon On Insulator (SOI) based process. To illustrate the current state of this new technology platform, working prototypes of a Reconfigurable Optical Add/Drop Multiplexer (ROADM) and a l-router will be presented along with details of the integrated latching MEMS optical switches. On-chip integration of optical switches and PLCs can greatly reduce the size, manufacturing cost and operating cost of multi-component optical equipment. It is anticipated that low-cost, low-overhead optical network products will accelerate the migration of functions and services from high-cost long-haul markets to price sensitive markets, including networks for metropolitan areas and fiber to the home. Compared to the more common silica-on-silicon PLC technology, the high index of refraction of silicon waveguides created in the SOI device layer enables miniaturization of optical components, thereby increasing yield and decreasing cost projections. The latching SOI MEMS switches feature moving waveguides, and are advantaged across multiple attributes relative to alternative switching technologies, such as thermal optical switches and polymer switches. The SOI process employed was jointly developed under the auspice of the NIST APT program in partnership with Coventor, Corning IntelliSense Corp., and MicroScan Systems to enable fabrication of a broad range of free space and guided wave MicroOptoElectroMechanical Systems (MOEMS).

Effect of ultraviolet illumination and ambient gases on the photoluminescence and electrical properties of nanoporous silicon layer for organic vapor sensor.

PubMed

Atiwongsangthong, Narin

2012-08-01

The purpose of this research, the nanoporous silicon layer were fabricated and investigated the physical properties such as photoluminescence and the electrical properties in order to develop organic vapor sensor by using nanoporous silicon. The Changes in the photoluminescence intensity of nanoporous silicon samples are studied during ultraviolet illumination in various ambient gases such as nitrogen, oxigen and vacuum. In this paper, the nanoporous silicon layer was used as organic vapor adsorption and sensing element. The advantage of this device are simple process compatible in silicon technology and usable in room temperature. The structure of this device consists of nanoporous silicon layer which is formed by anodization of silicon wafer in hydrofluoric acid solution and aluminum electrode which deposited on the top of nanoporous silicon layer by evaporator. The nanoporous silicon sensors were placed in a gas chamber with various organic vapor such as ethanol, methanol and isopropyl alcohol. From studying on electrical characteristics of this device, it is found that the nanoporous silicon layer can detect the different organic vapor. Therefore, the nanoporous silicon is important material for organic vapor sensor and it can develop to other applications about gas sensors in the future.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Analysis of area-time efficiency for an integrated focal plane architecture

NASA Astrophysics Data System (ADS)

Robinson, William H.; Wills, D. Scott

2003-05-01

Monolithic integration of photodetectors, analog-to-digital converters, digital processing, and data storage can improve the performance and efficiency of next-generation portable image products. Our approach combines these components into a single processing element, which is tiled to form a SIMD focal plane processor array with the capability to execute early image applications such as median filtering (noise removal), convolution (smoothing), and inside edge detection (segmentation). Digitizing and processing a pixel at the detection site presents new design challenges, including the allocation of silicon resources. This research investigates the area-time (A"T2) efficiency by adjusting the number of Pixels-per-Processing Element (PPE). Area calculations are based upon hardware implementations of components scaled for 250nm or 120nm technology. The total execution time is calculated from the sequential execution of each application on a generic focal plane architectural simulator. For a Quad-CIF system resolution (176×144), results show that 1 PPE provides the optimal area-time efficiency (5.7 μs2 x mm2 for 250nm, 1.7 μs2 x mm2 for 120nm) but requires a large silicon chip (2072mm2 for 250nm, 614mm2 for 120nm). Increasing the PPE to 4 or 16 can reduce silicon area by 48% and 60% respectively (120nm technology) while maintaining performance within real-time constraints.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology.

PubMed

Llobet, J; Rius, G; Chuquitarqui, A; Borrisé, X; Koops, R; van Veghel, M; Perez-Murano, F

2018-04-02

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

NASA Astrophysics Data System (ADS)

Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

2018-04-01

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Silicon Technologies Adjust to RF Applications

NASA Technical Reports Server (NTRS)

Reinecke Taub, Susan; Alterovitz, Samuel A.

1994-01-01

Silicon (Si), although not traditionally the material of choice for RF and microwave applications, has become a serious challenger to other semiconductor technologies for high-frequency applications. Fine-line electron- beam and photolithographic techniques are now capable of fabricating silicon gate sizes as small as 0.1 micron while commonly-available high-resistivity silicon wafers support low-loss microwave transmission lines. These advances, coupled with the recent development of silicon-germanium (SiGe), arm silicon integrated circuits (ICs) with the speed required for increasingly higher-frequency applications.

Phase sensitive amplification in integrated waveguides (Conference Presentation)

NASA Astrophysics Data System (ADS)

Schroeder, Jochen B.; Zhang, Youngbin; Husko, Chad A.; LeFrancois, Simon; Eggleton, Benjamin J.

2017-02-01

Phase sensitive amplification (PSA) is an attractive technology for integrated all-optical signal processing, due to it's potential for noiseless amplification, phase regeneration and generation of squeezed light. In this talk I will review our results on implementing four-wave-mixing based PSA inside integrated photonic devices. In particular I will discuss PSA in chalcogenide ridge waveguides and silicon slow-light photonic crystals. We achieve PSA in both pump- and signal-degenerate schemes with maximum extinction ratios of 11 (silicon) and 18 (chalcogenide) dB. I will further discuss the influence of two-photon absorption and free carrier effects on the performance of silicon-based PSAs.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Proceedings of the 13th Project integration meeting

NASA Technical Reports Server (NTRS)

Mcdonald, R. R.

1979-01-01

Progress made by the Low Cost Solar Array Project during the period April through August 1979 is presented. Reports are given on project analysis and integration; technology development in silicon material, large area sheet silicon, and encapsulation; production process and equipment development; engineering and operations, and a discussion of the steps taken to integrate these efforts. A report on, and copies of viewgraphs presented at the Project Integration Meeting held August 22-23, 1979 are presented.

Affordable, Robust Ceramic Joining Technology (ARCJoint) Developed

NASA Technical Reports Server (NTRS)

Steele, Gynelle C.

2001-01-01

Affordable, Robust Ceramic Joining Technology (ARCJoint) is a method for joining high temperature- resistant ceramic pieces together, establishing joints that are strong, and allowing joining to be done in the field. This new way of joining allows complex shapes to be formed by joining together geometrically simple shapes. The joining technology at NASA is one of the enabling technologies for the application of silicon-carbide-based ceramic and composite components in demanding and high-temperature applications. The technology is being developed and tested for high-temperature propulsion parts for aerospace use. Commercially, it can be used for joining ceramic pieces used for high temperature applications in the power-generating and chemical industries, as well as in the microelectronics industry. This innovation could yield big payoffs for not only the power-generating industry but also the Silicon Valley chipmakers. This technology, which was developed at the NASA Glenn Research Center by Dr. Mrityunjay Singh, is a two-step process involving first using a paste to join together ceramic pieces and bonding them by heating the joint to 110 to 120 C for between 10 and 20 min. This makes the joint strong enough to be handled for the final joining. Then, a silicon-based substance is applied to the joint and heated to 1400 C for 10 to 15 min. The resulting joint is as strong as the original ceramic material and can withstand the same high temperatures.

Using the surface charge profiler for in-line monitoring of doping concentration in silicon epitaxial wafer manufacturing

NASA Astrophysics Data System (ADS)

Tower, Joshua P.; Kamieniecki, Emil; Nguyen, M. C.; Danel, Adrien

1999-08-01

The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

Silicon Valley's Processing Needs versus San Jose State University's Manufacturing Systems Processing Component: Implications for Industrial Technology

ERIC Educational Resources Information Center

Obi, Samuel C.

2004-01-01

Manufacturing professionals within universities tend to view manufacturing systems from a global perspective. This perspective tends to assume that manufacturing processes are employed equally in every manufacturing enterprise, irrespective of the geography and the needs of the people in those diverse regions. But in reality local and societal…

Dynamic hybrid life cycle assessment of energy and carbon of multicrystalline silicon photovoltaic systems.

PubMed

Zhai, Pei; Williams, Eric D

2010-10-15

This paper advances the life cycle assessment (LCA) of photovoltaic systems by expanding the boundary of the included processes using hybrid LCA and accounting for the technology-driven dynamics of embodied energy and carbon emissions. Hybrid LCA is an extended method that combines bottom-up process-sum and top-down economic input-output (EIO) methods. In 2007, the embodied energy was 4354 MJ/m(2) and the energy payback time (EPBT) was 2.2 years for a multicrystalline silicon PV system under 1700 kWh/m(2)/yr of solar radiation. These results are higher than those of process-sum LCA by approximately 60%, indicating that processes excluded in process-sum LCA, such as transportation, are significant. Even though PV is a low-carbon technology, the difference between hybrid and process-sum results for 10% penetration of PV in the U.S. electrical grid is 0.13% of total current grid emissions. Extending LCA from the process-sum to hybrid analysis makes a significant difference. Dynamics are characterized through a retrospective analysis and future outlook for PV manufacturing from 2001 to 2011. During this decade, the embodied carbon fell substantially, from 60 g CO(2)/kWh in 2001 to 21 g/kWh in 2011, indicating that technological progress is realizing reductions in embodied environmental impacts as well as lower module price.

Physical Properties of Polyester Fabrics Treated with Nano, Micro and Macro Emulsion Silicones

NASA Astrophysics Data System (ADS)

Parvinzadeh, M.; Hajiraissi, R.

2007-08-01

The processing of textile to achieve a particular handle is one of the most important aspects of finishing technology. Fabrics softeners are liquid composition added to washing machines during the rinse cycle to make clothes feel better to the touch. The first fabric softeners were developed by the textile industry during the early twentieth century. In this research polyester fabrics were treated with nano, micro and macro emulsion silicone softeners. Some of the physical properties of the treated fabric samples are discussed. The drapeability of treated samples was improved after treatment with nano silicone softeners. The colorimetric measurement of softener-treated fabrics is evaluated with a reflectance spectrophotometer. Moisture regain of treated samples is increased due to coating of silicone softeners. There is some increase in the weight of softener-treated samples. Samples treated with nano emulsion silicones gave better results compared to micro- and macro-emulsion treated ones.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

NASA Astrophysics Data System (ADS)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Polymer dispensing and embossing technology for the lens type LED packaging

NASA Astrophysics Data System (ADS)

Chien, Chien-Lin Chang; Huang, Yu-Che; Hu, Syue-Fong; Chang, Chung-Min; Yip, Ming-Chuen; Fang, Weileun

2013-06-01

This study presents a ring-type micro-structure design on the substrate and its corresponding micro fabrication processes for a lens-type light-emitting diode (LED) package. The dome-type or crater-type silicone lenses are achieved by a dispensing and embossing process rather than a molding process. Silicone with a high viscosity and thixotropy index is used as the encapsulant material. The ring-type micro structure is adopted to confine the dispensed silicone encapsulant so as to form the packaged lens. With the architecture and process described, this LED package technology herein has three merits: (1) the flexibility of lens-type LED package designs is enhanced; (2) a dome-type package design is used to enhance the intensity; (3) a crater-type package design is used to enhance the view angle. Measurement results show the ratio between the lens height and lens radius can vary from 0.4 to 1 by changing the volume of dispensed silicone. The view angles of dome-type and crater-type packages can reach 155° ± 5° and 175° ± 5°, respectively. As compared with the commercial plastic leaded chip carrier-type package, the luminous flux of a monochromatic blue light LED is improved by 15% by the dome-type package (improved by 7% by the crater-type package) and the luminous flux of a white light LED is improved by 25% by the dome-type package (improved by 13% by the crater-type package). The luminous flux of monochromatic blue light LED and white light LED are respectively improved by 8% and 12% by the dome-type package as compare with the crater-type package.

Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits

NASA Astrophysics Data System (ADS)

Sutton, Akil K.

Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

Economics of polysilicon processes

NASA Technical Reports Server (NTRS)

Yaws, C. L.; Li, K. Y.; Chou, S. M.

1986-01-01

Techniques are being developed to provide lower cost polysilicon material for solar cells. Existing technology which normally provides semiconductor industry polysilicon material is undergoing changes and also being used to provide polysilicon material for solar cells. Economics of new and existing technologies are presented for producing polysilicon. The economics are primarily based on the preliminary process design of a plant producing 1,000 metric tons/year of silicon. The polysilicon processes include: Siemen's process (hydrogen reduction of trichlorosilane); Union Carbide process (silane decomposition); and Hemlock Semiconductor process (hydrogen reduction of dichlorosilane). The economics include cost estimates of capital investment and product cost to produce polysilicon via the technology. Sensitivity analysis results are also presented to disclose the effect of major paramentes such as utilities, labor, raw materials and capital investment.

“Playing around” with Field-Effect Sensors on the Basis of EIS Structures, LAPS and ISFETs

PubMed Central

Schöning, Michael J.

2005-01-01

Microfabricated semiconductor devices are becoming increasingly relevant, also for the detection of biological and chemical quantities. Especially, the “marriage” of biomolecules and silicon technology often yields successful new sensor concepts. The fabrication techniques of such silicon-based chemical sensors and biosensors, respectively, will have a distinct impact in different fields of application such as medicine, food technology, environment, chemistry and biotechnology as well as information processing. Moreover, scientists and engineers are interested in the analytical benefits of miniaturised and microfabricated sensor devices. This paper gives a survey on different types of semiconductor-based field-effect structures that have been recently developed in our laboratory.

Automated array assembly task, phase 1

NASA Technical Reports Server (NTRS)

Carbajal, B. G.

1977-01-01

State-of-the-art technologies applicable to silicon solar cell and solar cell module fabrication were assessed. The assessment consisted of a technical feasibility evaluation and a cost projection for high volume production of solar cell modules. Design equations based on minimum power loss were used as a tool in the evaluation of metallization technologies. A solar cell process sensitivity study using models, computer calculations, and experimental data was used to identify process step variation and cell output variation correlations.

Small area silicon diffused junction X-ray detectors

NASA Technical Reports Server (NTRS)

Walton, J. T.; Pehl, R. H.; Larsh, A. E.

1982-01-01

The low-temperature performance of silicon diffused junction detectors in the measurement of low energy X-rays is reported. The detectors have an area of 0.04 sq cm and a thickness of 100 microns. The spectral resolutions of these detectors were found to be in close agreement with expected values, indicating that the defects introduced by the high-temperature processing required in the device fabrication were not deleteriously affecting the detection of low-energy X-rays. Device performance over a temperature range of 77 K to 150 K is given. These detectors were designed to detect low-energy X-rays in the presence of minimum ionizing electrons. The successful application of silicon-diffused junction technology to X-ray detector fabrication may facilitate the development of other novel silicon X-ray detector designs.

Experimental identification of nitrogen-vacancy complexes in nitrogen implanted silicon

NASA Astrophysics Data System (ADS)

Adam, Lahir Shaik; Law, Mark E.; Szpala, Stanislaw; Simpson, P. J.; Lawther, Derek; Dokumaci, Omer; Hegde, Suri

2001-07-01

Nitrogen implantation is commonly used in multigate oxide thickness processing for mixed signal complementary metal-oxide-semiconductor and System on a Chip technologies. Current experiments and diffusion models indicate that upon annealing, implanted nitrogen diffuses towards the surface. The mechanism proposed for nitrogen diffusion is the formation of nitrogen-vacancy complexes in silicon, as indicated by ab initio studies by J. S. Nelson, P. A. Schultz, and A. F. Wright [Appl. Phys. Lett. 73, 247 (1998)]. However, to date, there does not exist any experimental evidence of nitrogen-vacancy formation in silicon. This letter provides experimental evidence through positron annihilation spectroscopy that nitrogen-vacancy complexes indeed form in nitrogen implanted silicon, and compares the experimental results to the ab initio studies, providing qualitative support for the same.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

NASA Astrophysics Data System (ADS)

Bisadi, Zahra; Acerbi, Fabio; Fontana, Giorgio; Zorzi, Nicola; Piemonte, Claudio; Pucker, Georg; Pavesi, Lorenzo

2018-02-01

A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED) coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST) suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Electrochemistry of Silicon: Instrumentation, Science, Materials and Applications

NASA Astrophysics Data System (ADS)

Lehmann, Volker

2002-04-01

Silicon has been and will most probably continue to be the dominant material in semiconductor technology. Although the defect-free silicon single crystal is one of the best understood systems in materails science, its electrochemistry to many people is still a kind of "alchemy". This view is partly due to the interdisciplinary aspects of the topic: Physics meets chemistry at the silicon-electrolyte interface. This book gives a comprehensive overview of this important aspect of silicon technology as well as examples of applications ranging from photonic crystals to biochips. It will serve materials scientists as well as engineers involved in silicon technology as a quick reference with its more than 150 technical tables and diagrams and ca. 1000 references cited for easy access of the original literature.

3D-FBK Pixel Sensors: Recent Beam Tests Results with Irradiated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Micelli, A.; /INFN, Trieste /Udine U.; Helle, K.

2012-04-30

The Pixel Detector is the innermost part of the ATLAS experiment tracking device at the Large Hadron Collider, and plays a key role in the reconstruction of the primary vertices from the collisions and secondary vertices produced by short-lived particles. To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology ismore » an innovative combination of very-large-scale integration and Micro-Electro-Mechanical-Systems where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. This paper reports on the 2010 June beam test results for irradiated 3D devices produced at FBK (Trento, Italy). The performance of these devices, all bump-bonded with the ATLAS pixel FE-I3 read-out chip, is compared to that observed before irradiation in a previous beam test.« less

Thermal ink-jet device using single-chip silicon microchannels

NASA Astrophysics Data System (ADS)

Wuu, DongSing; Cheng, Chen-Yue; Horng, RayHua; Chan, G. C.; Chiu, Sao-Ling; Wu, Yi-Yung

1998-06-01

We present a new method to fabricate silicon microfluidic channels by through-hole etching with subsequent planarization. The method is based on etching out the deep grooves through a perforated silicon carbide membrane, followed by sealing the membrane with plasma-enhanced chemical vapor deposition (PECVD). Low-pressure-chemical-vapor- deposited (LPCVD) polysilicon was used as a sacrificial layer to define the channel structure and only one etching step is required. This permits the realization of planarization after a very deep etching step in silicon and offers the possibility for film deposition, resist spinning and film patterning across deep grooves. The process technology was demonstrated on the fabrication of a monolithic silicon microchannel structure for thermal inkjet printing. The Ta-Al heater arrays are integrated on the top of each microchannel, which connect to a common on-chip front-end ink reservoir. The fabrication of this device requires six masks and no active nozzle-to-chip alignment. Moreover, the present micromachining process is compatible with the addition of on-chip circuitry for multiplexing the heater control signals. Heat transfer efficiency to the ink is enhanced by the high thermal conductivity of the silicon carbide in the channel ceiling, while the bulk silicon maintains high interchannel isolation. The fabricated inkjet devices show the droplet sizes of 20 - 50 micrometer in diameter with various channel dimensions and stable ejection of ink droplets more than 1 million.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

PubMed

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Development of the silane process for the production of low-cost polysilicon

NASA Technical Reports Server (NTRS)

Iya, S. K.

1986-01-01

It was recognized that the traditional hot rod type deposition process for decomposing silane is energy intensive, and a different approach for converting silane to silicon was chosen. A 1200 metric tons/year capacity commercial plant was constructed in Moses Lake, Washington. A fluidized bed processor was chosen as the most promising technology and several encouraging test runs were conducted. This technology continues to be very promising in producing low cost polysilicon. The Union Carbide silane process and the research development on the fluidized bed silane decomposition are discussed.

Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

NASA Astrophysics Data System (ADS)

Doris, B.; DeSalvo, B.; Cheng, K.; Morin, P.; Vinet, M.

2016-03-01

This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint development program between IBM, ST Microelectronics and CEA-LETI. In particular, we review the technological developments ranging from substrate engineering to process modules that enable functionality and improve FDSOI performance over several generations. Various multi Vt integration schemes to maximize the benefits of the thin BOX FDSOI platform are discussed. Manufacturability as well as scalability concerns are highlighted and addressed. In addition, this work provides understanding of the performance/power trade-offs for FDSOI circuits and device variability. Finally, clear directions for future application-specific products are given, demonstrating that FDSOI is an attractive CMOS option for next generation high performance and low-power applications.

Selecting mirror materials for high-performance optical systems

NASA Astrophysics Data System (ADS)

Parsonage, Thomas B.

1990-11-01

The properties of four candidate mirror materials--beryllium, silicon carbide, a silicon carbide/aluminum iretal-matrix carposite and aluminum--are corrpared. Because of its high specific stiffness and dirrensional stability under changing mschanical and thermal loads , beryllium is the best choice . Berjllium mirrors have been made irore cost-conpetitive by new processing technologies in which mirror blanks are isostatically pressed to near-net shape directly fran beiyllium pc1ers. Isostatic pressing also improves material properties and mskes it possible to develop mirror rraterials with superior properties.

Proceedings of the 22nd Project Integration Meeting

NASA Technical Reports Server (NTRS)

1983-01-01

This report describes progress made by the Flat-Plate Solar Array Project during the period January to September 1983. It includes reports on silicon sheet growth and characterization, module technology, silicon material, cell processing and high-efficiency cells, environmental isolation, engineering sciences, module performance and failure analysis and project analysis and integration. It includes a report on, and copies of visual presentations made at the 22nd Project Integration Meeting held at Pasadena, California, on September 28 and 29, 1983.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Drake, G.; Garcia-Scivres, M.; Paramonov, A.

We propose to use silicon photonics technology to build radiation-hard fiber-optic links for high-bandwidth readout of tracking detectors. The CMOS integrated silicon photonics was developed by Luxtera and commercialized by Molex. The commercial off-the-shelf (COTS) fiber-optic links feature moderate radiation tolerance insufficient for trackers. A transceiver contains four RX and four TX channels operating at 10 Gbps each. The next generation will likely operate at 25 Gbps per channel. The approach uses a standard CMOS process and single-mode fibers, providing low power consumption and good scalability and reliability.

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

NASA Astrophysics Data System (ADS)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Development of processing procedures for advanced silicon solar cells. [antireflection coatings and short circuit currents

NASA Technical Reports Server (NTRS)

Scott-Monck, J. A.; Stella, P. M.; Avery, J. E.

1975-01-01

Ten ohm-cm silicon solar cells, 0.2 mm thick, were produced with short circuit current efficiencies up to thirteen percent and using a combination of recent technical advances. The cells were fabricated in conventional and wraparound contact configurations. Improvement in cell collection efficiency from both the short and long wavelengths region of the solar spectrum was obtained by coupling a shallow junction and an optically transparent antireflection coating with back surface field technology. Both boron diffusion and aluminum alloying techniques were evaluated for forming back surface field cells. The latter method is less complicated and is compatible with wraparound cell processing.

Far-Infrared Blocked Impurity Band Detector Development

NASA Technical Reports Server (NTRS)

Hogue, H. H.; Guptill, M. T.; Monson, J. C.; Stewart, J. W.; Huffman, J. E.; Mlynczak, M. G.; Abedin, M. N.

2007-01-01

DRS Sensors & Targeting Systems, supported by detector materials supplier Lawrence Semiconductor Research Laboratory, is developing far-infrared detectors jointly with NASA Langley under the Far-IR Detector Technology Advancement Partnership (FIDTAP). The detectors are intended for spectral characterization of the Earth's energy budget from space. During the first year of this effort we have designed, fabricated, and evaluated pilot Blocked Impurity Band (BIB) detectors in both silicon and germanium, utilizing pre-existing customized detector materials and photolithographic masks. A second-year effort has prepared improved silicon materials, fabricated custom photolithographic masks for detector process, and begun detector processing. We report the characterization results from the pilot detectors and other progress.

Production technology for high efficiency ion implanted solar cells

NASA Technical Reports Server (NTRS)

Kirkpatrick, A. R.; Minnucci, J. A.; Greenwald, A. C.; Josephs, R. H.

1978-01-01

Ion implantation is being developed for high volume automated production of silicon solar cells. An implanter designed for solar cell processing and able to properly implant up to 300 4-inch wafers per hour is now operational. A machine to implant 180 sq m/hr of solar cell material has been designed. Implanted silicon solar cells with efficiencies exceeding 16% AM1 are now being produced and higher efficiencies are expected. Ion implantation and transient processing by pulsed electron beams are being integrated with electrostatic bonding to accomplish a simple method for large scale, low cost production of high efficiency solar cell arrays.

Molecular transport through nanoporous silicon nitride membranes produced from self-assembling block copolymers.

PubMed

Montagne, Franck; Blondiaux, Nicolas; Bojko, Alexandre; Pugin, Raphaël

2012-09-28

To achieve fast and selective molecular filtration, membrane materials must ideally exhibit a thin porous skin and a high density of pores with a narrow size distribution. Here, we report the fabrication of nanoporous silicon nitride membranes (NSiMs) at the full wafer scale using a versatile process combining block copolymer (BCP) self-assembly and conventional photolithography/etching techniques. In our method, self-assembled BCP micelles are used as templates for creating sub-100 nm nanopores in a thin low-stress silicon nitride layer, which is then released from the underlying silicon wafer by etching. The process yields 100 nm thick free-standing NSiMs of various lateral dimensions (up to a few mm(2)). We show that the membranes exhibit a high pore density, while still retaining excellent mechanical strength. Permeation experiments reveal that the molecular transport rate across NSiMs is up to 16-fold faster than that of commercial polymeric membranes. Moreover, using dextran molecules of various molecular weights, we also demonstrate that size-based separation can be achieved with a very good selectivity. These new silicon nanosieves offer a relevant technological alternative to commercially available ultra- and microfiltration membranes for conducting high resolution biomolecular separations at small scales.

Mass production of silicon pore optics for ATHENA

NASA Astrophysics Data System (ADS)

Wille, Eric; Bavdaz, Marcos; Collon, Maximilien

2016-07-01

Silicon Pore Optics (SPO) provide high angular resolution with low effective area density as required for the Advanced Telescope for High Energy Astrophysics (Athena). The x-ray telescope consists of several hundreds of SPO mirror modules. During the development of the process steps of the SPO technology, specific requirements of a future mass production have been considered right from the beginning. The manufacturing methods heavily utilise off-the-shelf equipment from the semiconductor industry, robotic automation and parallel processing. This allows to upscale the present production flow in a cost effective way, to produce hundreds of mirror modules per year. Considering manufacturing predictions based on the current technology status, we present an analysis of the time and resources required for the Athena flight programme. This includes the full production process starting with Si wafers up to the integration of the mirror modules. We present the times required for the individual process steps and identify the equipment required to produce two mirror modules per day. A preliminary timeline for building and commissioning the required infrastructure, and for flight model production of about 1000 mirror modules, is presented.

New dynamic silicon photonic components enabled by MEMS technology

NASA Astrophysics Data System (ADS)

Errando-Herranz, Carlos; Edinger, Pierre; Colangelo, Marco; Björk, Joel; Ahmed, Samy; Stemme, Göran; Niklaus, Frank; Gylfason, Kristinn B.

2018-02-01

Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

High temperature and frequency pressure sensor based on silicon-on-insulator layers

NASA Astrophysics Data System (ADS)

Zhao, Y. L.; Zhao, L. B.; Jiang, Z. D.

2006-03-01

Based on silicon on insulator (SOI) technology, a novel high temperature pressure sensor with high frequency response is designed and fabricated, in which a buried silicon dioxide layer in the silicon material is developed by the separation by implantation of oxygen (SIMOX) technology. This layer can isolate leak currents between the top silicon layer for the detecting circuit and body silicon at a temperature of about 200 °C. In addition, the technology of silicon and glass bonding is used to create a package of the sensor without internal strain. A structural model and test data from the sensor are presented. The experimental results showed that this kind of sensor possesses good static performance in a high temperature environment and high frequency dynamic characteristics, which may satisfy the pressure measurement demands of the oil industry, aviation and space, and so on.

Photovoltaic Materials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Duty, C.; Angelini, J.; Armstrong, B.

The goal of the current project was to help make the US solar industry a world leader in the manufacture of thin film photovoltaics. The overall approach was to leverage ORNL’s unique characterization and processing technologies to gain a better understanding of the fundamental challenges for solar cell processing and apply that knowledge to targeted projects with industry members. ORNL has the capabilities in place and the expertise required to understand how basic material properties including defects, impurities, and grain boundaries affect the solar cell performance. ORNL also has unique processing capabilities to optimize the manufacturing process for fabrication ofmore » high efficiency and low cost solar cells. ORNL recently established the Center for Advanced Thin-film Systems (CATS), which contains a suite of optical and electrical characterization equipment specifically focused on solar cell research. Under this project, ORNL made these facilities available to industrial partners who were interested in pursuing collaborative research toward the improvement of their product or manufacturing process. Four specific projects were pursued with industrial partners: Global Solar Energy is a solar industry leader in full scale production manufacturing highly-efficient Copper Indium Gallium diSelenide (CIGS) thin film solar material, cells and products. ORNL worked with GSE to develop a scalable, non-vacuum, solution technique to deposit amorphous or nanocrystalline conducting barrier layers on untextured stainless steel substrates for fabricating high efficiency flexible CIGS PV. Ferro Corporation’s Electronic, Color and Glass Materials (“ECGM”) business unit is currently the world’s largest supplier of metallic contact materials in the crystalline solar cell marketplace. Ferro’s ECGM business unit has been the world's leading supplier of thick film metal pastes to the crystalline silicon PV industry for more than 30 years, and has had operational cells and modules in the field for 25 years. Under this project, Ferro leveraged world leading analytical capabilities at ORNL to characterize the paste-to-silicon interface microstructure and develop high efficiency next generation contact pastes. Ampulse Corporation is developing a revolutionary crystalline-silicon (c-Si) thin-film solar photovoltaic (PV) technology. Utilizing uniquely-textured substrates and buffer materials from the Oak Ridge National Laboratory (ORNL), and breakthroughs in Hot-Wire Chemical Vapor Deposition (HW-CVD) techniques in epitaxial silicon developed at the National Renewable Energy Laboratory (NREL), Ampulse is creating a solar technology that is tunable in silicon thickness, and hence in efficiency and economics, to meet the specific requirements of multiple solar PV applications. This project focused on the development of a high rate deposition process to deposit Si, Ge, and Si1-xGex films as an alternate to hot-wire CVD. Mossey Creek Solar is a start-up company with great expertise in the solar field. The primary interest is to create and preserve jobs in the solar sector by developing high-yield, low-cost, high-efficiency solar cells using MSC-patented and -proprietary technologies. The specific goal of this project was to produce large grain formation in thin, net-shape-thickness mc-Si wafers processed with high-purity silicon powder and ORNL's plasma arc lamp melting without introducing impurities that compromise absorption coefficient and carrier lifetime. As part of this project, ORNL also added specific pieces of equipment to enhance our ability to provide unique insight for the solar industry. These capabilities include a moisture barrier measurement system, a combined physical vapor deposition and sputtering system dedicated to cadmium-containing deposits, adeep level transient spectroscopy system useful for identifying defects, an integrating sphere photoluminescence system, and a high-speed ink jet printing system. These tools were combined with others to study the effect of defects on the performance of crystalline silicon and thin film solar cells, to explore non-vacuum ink-based approaches to solar cell production, as well as large-scale and low-cost deposition and processing of thin film CdTe material.« less

Large area, low cost space solar cells with optional wraparound contacts

NASA Technical Reports Server (NTRS)

Michaels, D.; Mendoza, N.; Williams, R.

1981-01-01

Design parameters for two large area, low cost solar cells are presented, and electron irradiation testing, thermal alpha testing, and cell processing are discussed. The devices are a 2 ohm-cm base resistivity silicon cell with an evaporated aluminum reflector produced in a dielectric wraparound cell, and a 10 ohm-cm silicon cell with the BSF/BSR combination and a conventional contact system. Both cells are 5.9 x 5.9 cm and require 200 micron thick silicon material due to mission weight constraints. Normalized values for open circuit voltage, short circuit current, and maximum power calculations derived from electron radiation testing are given. In addition, thermal alpha testing values of absorptivity and emittance are included. A pilot cell processing run produced cells averaging 14.4% efficiencies at AMO 28 C. Manufacturing for such cells will be on a mechanized process line, and the area of coverslide application technology must be considered in order to achieve cost effective production.

Stability and rheology of dispersions of silicon nitride and silicon carbide

NASA Technical Reports Server (NTRS)

Feke, Donald L.

1987-01-01

The relationship between the surface and colloid chemistry of commercial ultra-fine silicon carbide and silicon nitride powders was examined by a variety of standard characterization techniques and by methodologies especially developed for ceramic dispersions. These include electrokinetic measurement, surface titration, and surface spectroscopies. The effects of powder pretreatment and modification strategies, which can be utilized to augment control of processing characteristics, were monitored with these technologies. Both silicon carbide and nitride were found to exhibit silica-like surface chemistries, but silicon nitride powders possess an additional amine surface functionality. Colloidal characteristics of the various nitride powders in aqueous suspension is believed to be highly dependent on the relative amounts of the two types of surface groups, which in turn is determined by the powder synthesis route. The differences in the apparent colloidal characteristics for silicon nitride powders cannot be attributed to the specific absorption of ammonium ions. Development of a model for the prediction of double-layer characteristics of materials with a hybrid site interface facilitated understanding and prediction of the behavior of both surface charge and surface potential for these materials. The utility of the model in application to silicon nitride powders was demonstrated.

Effect of post-implantation annealing on Al-N isoelectronic trap formation in silicon: Al-N pair formation and defect recovery mechanisms

NASA Astrophysics Data System (ADS)

Mori, Takahiro; Morita, Yukinori; Matsukawa, Takashi

2018-05-01

The effect of post-implantation annealing (PIA) on Al-N isoelectronic trap (IET) formation in silicon has been experimentally investigated to discuss the Al-N IET formation and implantation-induced defect recovery mechanisms. We performed a photoluminescence study, which indicated that self-interstitial clusters and accompanying vacancies are generated in the ion implantation process. It is supposed that Al and N atoms move to the vacancy sites and form stable Al-N pairs in the PIA process. Furthermore, the PIA process recovers self-interstitial clusters while transforming their atomic configuration. The critical temperature for the formation/dissociation of Al-N pairs was found to be 450 °C, with which we describe the process integration for devices utilizing Al-N IET technology.

New 3D structuring process for non-integrated circuit related technologies (Conference Presentation)

NASA Astrophysics Data System (ADS)

Nouri, Lamia; Possémé, Nicolas; Landis, Stéfan; Milesi, Frédéric; Gaillard, Frédéric-Xavier

2017-04-01

Fabrication processes that microelectronic developed for Integrated circuit (IC) technologies for decades, do not meet the new emerging structuration's requirements, in particular non-IC related technologies one, such as MEMS/NEMS, Micro-Fluidics, photovoltaics, lenses. Actually complex 3D structuration requires complex lithography patterning approaches such as gray-scale electron beam lithography, laser ablation, focused ion beam lithography, two photon polymerization. It is now challenging to find cheaper and easiest technique to achieve 3D structures. In this work, we propose a straightforward process to realize 3D structuration, intended for silicon based materials (Si, SiN, SiOCH). This structuration technique is based on nano-imprint lithography (NIL), ion implantation and selective wet etching. In a first step a pattern is performed by lithography on a substrate, then ion implantation is realized through a resist mask in order to create localized modifications in the material, thus the pattern is transferred into the subjacent layer. Finally, after the resist stripping, a selective wet etching is carried out to remove selectively the modified material regarding the non-modified one. In this paper, we will first present results achieved with simple 2D line array pattern processed either on Silicon or SiOCH samples. This step have been carried out to demonstrate the feasibility of this new structuration process. SEM pictures reveals that "infinite" selectivity between the implanted areas versus the non-implanted one could be achieved. We will show that a key combination between the type of implanted ion species and wet etching chemistries is required to obtain such results. The mechanisms understanding involved during both implantation and wet etching processes will also be presented through fine characterizations with Photoluminescence, Raman and Secondary Ion Mass Spectrometry (SIMS) for silicon samples, and ellipso-porosimetry and Fourier Transform InfraRed spectroscopy (FTIR) for SiOCH samples. Finally the benefit of this new patterning approach will be presented on 3D patterns structures.

Nanofabrication on unconventional substrates using transferred hard masks

DOE PAGES

Li, Luozhou; Bayn, Igal; Lu, Ming; ...

2015-01-15

Here, a major challenge in nanofabrication is to pattern unconventional substrates that cannot be processed for a variety of reasons, such as incompatibility with spin coating, electron beam lithography, optical lithography, or wet chemical steps. Here, we present a versatile nanofabrication method based on re-usable silicon membrane hard masks, patterned using standard lithography and mature silicon processing technology. These masks, transferred precisely onto targeted regions, can be in the millimetre scale. They allow for fabrication on a wide range of substrates, including rough, soft, and non-conductive materials, enabling feature linewidths down to 10 nm. Plasma etching, lift-off, and ion implantationmore » are realized without the need for scanning electron/ion beam processing, UV exposure, or wet etching on target substrates.« less

Development of advanced Czochralski Growth Process to produce low cost 150 KG silicon ingots from a single crucible for technology readiness

NASA Technical Reports Server (NTRS)

1981-01-01

The goals in this program for advanced czochralski growth process to produce low cost 150 kg silicon ingots from a single crucible for technology readiness are outlined. To provide a modified CG2000 crystal power capable of pulling a minimum of five crystals, each of approximately 30 kg in weight, 150 mm diameter from a single crucible with periodic melt replenishment. Crystals to have: resistivity of 1 to 3 ohm cm, p-type; dislocation density below 1- to the 6th power per cm; orientation (100); after growth yield of greater than 90%. Growth throughput of greater than 2.5 kg per hour of machine operation using a radiation shield. Prototype equipment suitable for use as a production facility. The overall cost goal is $.70 per peak watt by 1986. To accomplish these goals, the modified CG2000 grower and development program includes: (1) increased automation with a microprocessor based control system; (2) sensors development which will increase the capability of the automatic controls system, and provide technology transfer of the developed systems.

Joining and Integration of Silicon Carbide-Based Materials for High Temperature Applications

NASA Technical Reports Server (NTRS)

Halbig, Michael C.; Singh, Mrityunjay

2016-01-01

Advanced joining and integration technologies of silicon carbide-based ceramics and ceramic matrix composites are enabling for their implementation into wide scale aerospace and ground-based applications. The robust joining and integration technologies allow for large and complex shapes to be fabricated and integrated with the larger system. Potential aerospace applications include lean-direct fuel injectors, thermal actuators, turbine vanes, blades, shrouds, combustor liners and other hot section components. Ground based applications include components for energy and environmental systems. Performance requirements and processing challenges are identified for the successful implementation different joining technologies. An overview will be provided of several joining approaches which have been developed for high temperature applications. In addition, various characterization approaches were pursued to provide an understanding of the processing-microstructure-property relationships. Microstructural analysis of the joint interfaces was conducted using optical, scanning electron, and transmission electron microscopy to identify phases and evaluate the bond quality. Mechanical testing results will be presented along with the need for new standardized test methods. The critical need for tailoring interlayer compositions for optimum joint properties will also be highlighted.

Impact of VLSI/VHSIC on satellite on-board signal processing

NASA Astrophysics Data System (ADS)

Aanstoos, J. V.; Ruedger, W. H.; Snyder, W. E.; Kelly, W. L.

Forecasted improvements in IC fabrication techniques, such as the use of X-ray lithography, are expected to yield submicron circuit feature sizes within the decade of the 1980s. As dimensions decrease, reliability, cost, speed, power consumption and density improvements will be realized which have a significant impact on the capabilities of onboard spacecraft signal processing functions. This will in turn result in increases of the intelligence that may be deployed on spaceborne remote sensing platforms. Among programs oriented toward such goals are the silicon-based Very High Speed Integrated Circuit (VHSIC) researches sponsored by the U.S. Department of Defense, and efforts toward the development of GaAs devices which will compete with silicon VLSI technology for future applications. GaAs has an electron mobility which is five to six times that of silicon, and promises commensurate computation speed increases under low field conditions.

Proceedings of the Flat-Plate Solar Array Project Workshop on Crystal Gowth for High-Efficiency Silicon Solar Cells

NASA Technical Reports Server (NTRS)

Dumas, K. A. (Editor)

1985-01-01

A Workshop on Crystal Growth for High-Efficiency Silicon Solar Cells was held December 3 and 4, 1984, in San Diego, California. The Workshop offered a day and a half of technical presentations and discussions and an afternoon session that involved a panel discussion and general discussion of areas of research that are necessary to the development of materials for high-efficiency solar cells. Topics included the theoretical and experimental aspects of growing high-quality silicon crystals, the effects of growth-process-related defects on photovoltaic devices, and the suitability of various growth technologies as cost-effective processes. Fifteen invited papers were presented, with a discussion period following each presentation. The meeting was organized by the Flat-Plate Solar Array Project of the Jet Propulsion Laboratory. These Proceedings are a record of the presentations and discussions, edited for clarity and continuity.

Argon–germane in situ plasma clean for reduced temperature Ge on Si epitaxy by high density plasma chemical vapor deposition

DOE PAGES

Douglas, Erica A.; Sheng, Josephine J.; Verley, Jason C.; ...

2015-06-04

We found that the demand for integration of near infrared optoelectronic functionality with silicon complementary metal oxide semiconductor (CMOS) technology has for many years motivated the investigation of low temperature germanium on silicon deposition processes. Our work describes the development of a high density plasma chemical vapor deposition process that uses a low temperature (<460 °C) in situ germane/argon plasma surface preparation step for epitaxial growth of germanium on silicon. It is shown that the germane/argon plasma treatment sufficiently removes SiO x and carbon at the surface to enable germanium epitaxy. Finally, the use of this surface preparation step demonstratesmore » an alternative way to produce germanium epitaxy at reduced temperatures, a key enabler for increased flexibility of integration with CMOS back-end-of-line fabrication.« less

SEMICONDUCTOR TECHNOLOGY Texturization of mono-crystalline silicon solar cells in TMAH without the addition of surfactant

NASA Astrophysics Data System (ADS)

Weiying, Ou; Yao, Zhang; Hailing, Li; Lei, Zhao; Chunlan, Zhou; Hongwei, Diao; Min, Liu; Weiming, Lu; Jun, Zhang; Wenjing, Wang

2010-10-01

Etching was performed on (100) silicon wafers using silicon-dissolved tetramethylammonium hydroxide (TMAH) solutions without the addition of surfactant. Experiments were carried out in different TMAH concentrations at different temperatures for different etching times. The surface phenomena, etching rates, surface morphology and surface reflectance were analyzed. Experimental results show that the resulting surface covered with uniform pyramids can be realized with a small change in etching rates during the etching process. The etching mechanism is explained based on the experimental results and the theoretical considerations. It is suggested that all the components in the TMAH solutions play important roles in the etching process. Moreover, TMA+ ions may increase the wettability of the textured surface. A good textured surface can be obtained in conditions where the absorption of OH-/H2O is in equilibrium with that of TMA+/SiO2 (OH)22-.

Crystalline silicon solar cells with high resistivity emitter

NASA Astrophysics Data System (ADS)

Panek, P.; Drabczyk, K.; Zięba, P.

2009-06-01

The paper presents a part of research targeted at the modification of crystalline silicon solar cell production using screen-printing technology. The proposed process is based on diffusion from POCl3 resulting in emitter with a sheet resistance on the level of 70 Ω/□ and then, shaped by high temperature passivation treatment. The study was focused on a shallow emitter of high resistivity and on its influence on output electrical parameters of a solar cell. Secondary ion mass spectrometry (SIMS) has been employed for appropriate distinguishing the total donor doped profile. The solar cell parameters were characterized by current-voltage characteristics and spectral response (SR) methods. Some aspects playing a role in suitable manufacturing process were discussed. The situation in a photovoltaic industry with emphasis on silicon supply and current prices of solar cells, modules and photovoltaic (PV) systems are described. The economic and quantitative estimation of the PV world market is shortly discussed.

Inter-Wire Antiferromagnetic Exchange Interaction in Ni/Si-Ferromagnetic/Semiconductor Nanocomposites

NASA Astrophysics Data System (ADS)

Granitzer, P.; Rumpf, K.; Hofmayer, M.; Krenn, H.; Pölt, P.; Reichmann, A.; Hofer, F.

2007-04-01

A matrix of mesoporous silicon offering an array of quasi 1-dimensional oriented pores of high aspect ratio perpendicular to the sample surface has been produced. This porous silicon (PS) skeleton is filled with Ni in a further process-step to achieve ferromagnetic metallic nanostructures within the channels. This produced silicon based nanocomposite is compatible with state-of-the-art silicon technology. Beside the vertical magnetic surface anisotropy of this Ni-filled composite the nearly monodisperse distribution of pore diameters and its regular arrangement in a quasi 2-dimensional lattice provides novel magnetic phenomena like a depression of the magnetization curve at magnetic fields beyond 2T, which can be interpreted as a field induced antiferromagnetic exchange interaction between Ni-wires which is strongly influenced by magnetostrictive stresses at the Ni/Si-interface. 2007 American Institute of Physics

Cryo-Etched Black Silicon for Use as Optical Black

NASA Technical Reports Server (NTRS)

Yee, Karl Y.; White, Victor E.; Mouroulis, Pantazis; Eastwood, Michael L.

2011-01-01

Stray light reflected from the surface of imaging spectrometer components in particular, the spectrometer slit degrade the image quality. A technique has been developed for rapid, uniform, and cost-effective black silicon formation based on inductively coupled plasma (ICP) etching at cryogenic temperatures. Recent measurements show less than 1-percent total reflectance from 350 2,500 nm of doped black silicon formed in this way, making it an excellent option for texturing of component surfaces for reduction of stray light. Oxygen combines with SF6 + Si etch byproducts to form a passivation layer atop the Si when the etch is performed at cryogenic temperatures. Excess flow of oxygen results in micromasking and the formation of black silicon. The process is repeatable and reliable, and provides control over etch depth and sidewall profile. Density of the needles can be controlled to some extent. Regions to be textured can be patterned lithographically. Adhesion is not an issue as the nanotips are part of the underlying substrate. This is in contrast to surface growth/deposition techniques such as carbon nanotubes (CNTs). The black Si surface is compatible with wet processing, including processing with solvents, the textured surface is completely inorganic, and it does not outgas. In radiometry applications, optical absorbers are often constructed using gold black or CNTs. This black silicon technology is an improvement for these types of applications.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Research on silicon microchannel array oxidation insulation technology and stress issues

NASA Astrophysics Data System (ADS)

Chai, Jin; Li, Mo; Liang, Yong-zhao; Yang, Ji-kai; Wang, Guo-zheng; Duanmu, Qing-duo

2013-08-01

Microchannel plate is widely used in the field of low light level night vision, photomultiplier, tubes, X-ray enhancer and so on. In order to meet the requirement of microchannel plate electron multiplier, we used the method of thermal oxidation to produce a thin film of silicon dioxide which could play a role in electric insulation. Silicon dioxide film has a high breakdown voltage, it can satisfy the high breakdown voltage requirements of electron multiplier. We should find the reasonable parameter values and preparation process in the oxidation so that the thickness and uniformity of the silicon dioxide layer would meet requirement. This article has been focused on researching and analyzing of the problem of oxide insulation and thermal stress in the process of production of silicon dioxide film. In this experiment, dry oxygen and wet oxygen were carried out respectively for 8 hours. The thickness of dry oxygen silicon dioxide films was 458 nm and wet oxygen silicon dioxide films was 1.4 μm. Under these conditions, the silicon microchannel is uniformity and neat, meanwhile the insulating layer's breakdown voltage was measured at 450 V after the wet oxygen oxidation. By using ANSYS finite element software, we analyze the thermal stress, which came from the microchannel oxygen processes, under the conditions of which ambient temperature was 27 ℃ and porosity was 64%, we simulated the thermal stress in the temperature of 1200 ℃ and 1000 ℃, finally we got the maximum equivalent thermal stress of 472 MPa and 403 MPa respectively. The higher thermal stress area was spread over Si-SiO2 interface, by simulate conditions 50% porosity silicon microchannel sample was selected for simulation analysis at 1100 ℃, we got the maximum equivalent thermal stress of 472 MPa, Thermal stress is the minimum value of 410 MPa.

4 channels x 10-Gbps optoelectronic transceiver based on silicon optical bench technology

NASA Astrophysics Data System (ADS)

Chen, Chin T.; Hsiao, Hsu L.; Chang, Chia. C.; Shen, Po K.; Lu, Guan F.; Lee, Yun C.; Chang, Shou F.; Lin, Yo S.; Wu, Mount L.

2012-01-01

In this paper, a bi-directional 4-channel x 10-Gbps optoelectronic transceiver based on this silicon optical bench (SiOB) technology is developed. A bi-directional optical sub-assembly (BOSA), fiber ribbon assembly, PCB with high frequency trace design, transmitter driver, and receiver TIA IC are included in this transceiver. The BOSA and PCB also have some specific design for conventional chip-on-board (COB) process. In eye diagram measurement, the transmitter can pass 10-G Ethernet eye mask with 25% margin at room temperature; Bit-error-rate (BER) performance from the transmitter to receiver via 10-meter fiber can achieve 10-12 order, which confirm the transceiver's ability of 10-Gbps data transmission per a channel.

On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

PubMed

Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

2014-07-10

Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

Phosphorus Diffusion Gettering Efficacy in Upgraded Metallurgical-Grade Solar Silicon

NASA Astrophysics Data System (ADS)

Jiménez, A.; del Cañizo, C.; Cid, C.; Peral, A.

2018-05-01

In the context of the continuous price reduction in photovoltaics (PV) in recent years, Si feedstock continues to be a relevant component in the cost breakdown of a PV module, highlighting the need for low-cost, low-capital expenditure (CAPEX) silicon technologies to further reduce this cost component. Upgraded metallurgical-grade silicon (UMG Si) has recently received much attention, improving its quality and even attaining, in some cases, solar cell efficiencies similar to those of conventional material. However, some technical challenges still have to be addressed when processing this material to compensate efficiently for the high content of impurities and contaminants. Adaptation of a conventional solar cell process to monocrystalline UMG Si wafers has been studied in this work. In particular, a tailored phosphorus diffusion gettering step followed by a low-temperature anneal at 700°C was implemented, resulting in enhanced bulk lifetime and emitter recombination properties. In spite of the need for further research and material optimization, UMG Si wafers were successfully processed, achieving efficiencies in the range of 15% for a standard laboratory solar cell process with aluminum back surface field.

Progress and challenges for cost effective kerfless Silicon crystal growth for PV application

NASA Astrophysics Data System (ADS)

Serra, J. M.; Alves, J. Maia; Vallera, A. M.

2017-06-01

The major barrier for PV penetration is cost. And the single most important cost factor in silicon technology is the wafer (≈35% of the module cost). Although tremendous progress on cell processing has been reported in recent years, a much smaller evolution is seen on what should be the key point to address - the wafer. The ingot-slicing process is reaching its limits as the wafer thickness is reduced in an effort to lower material costs. Kerf losses of ≈50% and an increase in breakage of a high value added material are putting a lower bound to this approach. New ideas are therefore needed for producing wafers in a way to overcome these limitations. In this paper we present three new concepts being developed in our laboratory that have one thing in common: they all are zero kerf loss processes, aiming at significant reductions in material loss. One explores the concept of exfoliation, the other two aim at the growth of silicon directly into ribbons. These were conceived as continuous processes, based on a floating molten zone concept, to avoid impurity contamination during crystallization.

75 FR 20812 - Silicon Metal from Brazil: Amended Final Results of Administrative Review Pursuant to Court Decision

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-21

... regarding the 94/95 period of review. See American Silicon Technologies v. United States, 28 C.I.T. 698.../95 period of review. See American Silicon Technologies v. United States, 27 C.I.T. 1677; 2003 Ct...

Fabrication of high aspect ratio structure and its releasing for silicon on insulator MEMS/MOEMS device application

NASA Astrophysics Data System (ADS)

Fan, Ji; Zhang, Wen Ting; Liu, Jin Quan; Wu, Wen Jie; Zhu, Tao; Tu, Liang Cheng

2015-04-01

We systematically investigate the fabrication and dry-release technology for a high aspect ratio (HAR) structure with vertical and smooth silicon etching sidewalls. One-hundred-micrometer silicon on insulator (SOI) wafers are used in this work. By optimizing the process parameters of inductively coupled plasma deep reactive-ion etching, a HAR (˜25∶1) structure with a microtrench width of 4 μm has been demonstrated. A perfect etching profile has been obtained in which the structures present an almost perfect verticality of 0.10 μm and no sidewall scallops. The root-mean square roughness of silicon sidewalls is 20 to 29 nm. An in situ dry-release method using notching effect is employed after etching. By analysis, we found that the final notch length is typically an aspect-ratio-dependent process. The structure designed in this work has been successfully released by this in situ dry-release method, and the released bottom roughness effectively prohibits the stiction mechanism. The results demonstrate potential applications for design and fabrication of HAR SOI MEMS/MOEMS.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Nanobonding: A key technology for emerging applications in health and environmental sciences

NASA Astrophysics Data System (ADS)

Howlader, Matiar M. R.; Deen, M. Jamal; Suga, Tadatomo

2015-03-01

In this paper, surface-activation-based nanobonding technology and its applications are described. This bonding technology allows for the integration of electronic, photonic, fluidic and mechanical components into small form-factor systems for emerging sensing and imaging applications in health and environmental sciences. Here, we describe four different nanobonding techniques that have been used for the integration of various substrates — silicon, gallium arsenide, glass, and gold. We use these substrates to create electronic (silicon), photonic (silicon and gallium arsenide), microelectromechanical (glass and silicon), and fluidic (silicon and glass) components for biosensing and bioimaging systems being developed. Our nanobonding technologies provide void-free, strong, and nanometer scale bonding at room temperature or at low temperatures (<200 °C), and do not require chemicals, adhesives, or high external pressure. The interfaces of the nanobonded materials in ultra-high vacuum and in air correspond to covalent bonds, and hydrogen or hydroxyl bonds, respectively.

An overview of crystalline silicon solar cell technology: Past, present, and future

NASA Astrophysics Data System (ADS)

Sopian, K.; Cheow, S. L.; Zaidi, S. H.

2017-09-01

Crystalline silicon (c-Si) solar cell, ever since its inception, has been identified as the only economically and environmentally sustainable renewable resource to replace fossil fuels. Performance c-Si based photovoltaic (PV) technology has been equal to the task. Its price has been reduced by a factor of 250 over last twenty years (from ˜ 76 USD to ˜ 0.3 USD); its market growth is expected to reach 100 GWP by 2020. Unfortunately, it is still 3-4 times higher than carbon-based fuels. With the matured PV manufacturing technology as it exists today, continuing price reduction poses stiff challenges. Alternate manufacturing approaches in combination with thin wafers, low (< 10 x) optical enhancement with Fresnel lenses, band-gap engineering for enhanced optical absorption, and newer, advanced solar cell configurations including partially transparent bifacial and back contact solar cells will be required. This paper will present a detailed, cost-based analysis of advanced solar cell manufacturing technologies aimed at higher (˜ 22 %) efficiency with existing equipment and processes.

Deep silicon etching: current capabilities and future directions

NASA Astrophysics Data System (ADS)

Westerman, Russ; Martinez, Linnell; Pays-Volard, David; Mackenzie, Ken; Lazerand, Thierry

2014-03-01

Deep Reactive Ion Etching (DRIE) has revolutionized a wide variety of MEMS applications since its inception nearly two decades ago. The DRIE technology has been largely responsible for allowing lab scale technology demonstrations to become manufacturable and profitable consumer products. As applications which utilize DRIE technologies continue to expand and evolve, they continue to spawn a range of new requirements and open up exciting opportunities for advancement of DRIE. This paper will examine a number of current and emerging DRIE applications including nanotechnology, and DRIE related packaging technologies such as Through Silicon Via (TSV) and plasma dicing. The paper will discuss a number of technical challenges and solutions associated with these applications including: feature profile control at high aspect ratios, causes and elimination of feature tilt/skew, process options for fragile device structures, and problems associated with through substrate etching. The paper will close with a short discussion around the challenges of implementing DRIE in production environments as well as looking at potentially disruptive enhancements / substitutions for DRIE.

Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

NASA Astrophysics Data System (ADS)

Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

2008-09-01

In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Proceedings of the 21st Project Integration Meeting

NASA Technical Reports Server (NTRS)

1983-01-01

Progress made by the Flat Plate Solar Array Project during the period April 1982 to January 1983 is described. Reports on polysilicon refining, thin film solar cell and module technology development, central station electric utility activities, silicon sheet growth and characteristics, advanced photovoltaic materials, cell and processes research, module technology, environmental isolation, engineering sciences, module performance and failure analysis and project analysis and integration are included.

Way Forward for High Performance Payload Processing Development

NASA Astrophysics Data System (ADS)

Notebaert, Olivier; Franklin, John; Lefftz, Vincent; Moreno, Jose; Patte, Mathieu; Syed, Mohsin; Wagner, Arnaud

2012-08-01

Payload processing is facing technological challenges due to the large increase of performance requirements of future scientific, observation and telecom missions as well as the future instruments technologies capturing much larger amount of data. For several years, with the perspective of higher performance together with the planned obsolescence of solutions covering the current needs, ESA and the European space industry has been developing several technology solutions. Silicon technologies, radiation mitigation techniques and innovative functional architectures are developed with the goal of designing future space qualified processing devices with a much higher level of performance than today. The fast growing commercial market application have developed very attractive technologies but which are not fully suitable with respect to their tolerance to space environment. Without the financial capacity to explore and develop all possible technology paths, a specific and global approach is required to cover the future mission needs and their necessary performance targets with effectiveness.The next sections describe main issues and priorities and provides further detailed relevant for this approach covering the high performance processing technology.

Fabrication of p-type porous silicon nanowire with oxidized silicon substrate through one-step MACE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Shaoyuan; Faculty of Metallurgical and Energy Engineering, Kunming University of Science and Technology, Kunming 650093; Ma, Wenhui, E-mail: mwhsilicon@163.com

2014-05-01

In this paper, the simple pre-oxidization process is firstly used to treat the starting silicon wafer, and then MPSiNWs are successfully fabricated from the moderately doped wafer by one-step MACE technology in HF/AgNO{sub 3} system. The PL spectrum of MPSiNWs obtained from the oxidized silicon wafers show a large blue-shift, which can be attributed to the deep Q. C. effect induced by numerous mesoporous structures. The effects of HF and AgNO{sub 3} concentration on formation of SiNWs were carefully investigated. The results indicate that the higher HF concentration is favorable to the growth of SiNWs, and the density of SiNWsmore » is significantly reduced when Ag{sup +} ions concentrations are too high. The deposition behaviors of Ag{sup +} ions on oxidized and unoxidized silicon surface were studied. According to the experimental results, a model was proposed to explain the formation mechanism of porous SiNWs by etching the oxidized starting silicon. - Graphical abstract: Schematic cross-sectional views of PSiNWs array formation by etching oxidized silicon wafer in HF/AgNO{sub 3} solution. (A) At the starting point; (B) during the etching process; and (C) after Ag dendrites remove. - Highlights: • Prior to etching, a simple pre-oxidation is firstly used to treat silicon substrate. • The medially doped p-type MPSiNWs are prepared by one-step MACE. • Deposition behaviors of Ag{sup +} ions on oxidized and unoxidized silicon are studied. • A model is finally proposed to explain the formation mechanism of PSiNWs.« less

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

NASA Technical Reports Server (NTRS)

Jhabvala, Murzy; Jhabvala, Christine A.; Ewin, Audrey J.; Hess, Larry A.; Hartmann, Thomas M.; La, Anh T.

2012-01-01

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

NASA Astrophysics Data System (ADS)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Solar Grade Silicon from Agricultural By-products

DOE Office of Scientific and Technical Information (OSTI.GOV)

Laine, Richard M

2012-08-20

In this project, Mayaterials developed a low cost, low energy and low temperature method of purifying rice hull ash to high purity (5-6Ns) and converting it by carbothermal reduction to solar grade quality silicon (Sipv) using a self-designed and built electric arc furnace (EAF). Outside evaluation of our process by an independent engineering firm confirms that our technology greatly lowers estimated operating expenses (OPEX) to $5/kg and capital expenses (CAPEX) to $24/kg for Sipv production, which is well below best-in-class plants using a Siemens process approach (OPEX of 14/kg and CAPEX of $87/kg, respectively). The primary limiting factor in themore » widespread use of photovoltaic (PV) cells is the high cost of manufacturing, compared to more traditional sources to reach 6 g Sipv/watt (with averages closer to 8+g/watt). In 2008, the spot price of Sipv rose to $450/kg. While prices have since dropped to a more reasonable $25/kg; this low price level is not sustainable, meaning the longer-term price will likely return to $35/kg. The 6-8 g Si/watt implies that the Sipv used in a module will cost $0.21-0.28/watt for the best producers (45% of the cost of a traditional solar panel), a major improvement from the cost/wafer driven by the $50/kg Si costs of early 2011, but still a major hindrance in fulfilling DOE goal of lowering the cost of solar energy below $1/watt. The solar cell industry has grown by 40% yearly for the past eight years, increasing the demand for Sipv. As such, future solar silicon price spikes are expected in the next few years. Although industry has invested billions of dollars to meet this ever-increasing demand, the technology to produce Sipv remains largely unchanged requiring the energy intensive, and chlorine dependent Siemens process or variations thereof. While huge improvements have been made, current state-of-the-art industrial plant still use 65 kWh/kg of silicon purified. Our technology offers a key distinction to other technologies as it starts one step upstream from all other Sipv production efforts. Our process starts by producing high purity SiO2/C feedstocks from which Sipv can be produced in a single, chlorine free, final EAF step. Specifically, our unique technology, and the resultant SiO2/C product can serve as high purity feedstocks to existing metallurgical silicon (Simet) producers, allowing them to generate Sipv with existing US manufacturing infrastructure, reducing the overall capital and commissioning schedule. Our low energy, low CAPEX and OPEX process purifies the silica and carbon present in rice hull ash (RHA) at low temperatures (< 200C) to produce high purity (5-6 Ns) feedstock for production of Sipv using furnaces similar to those used to produce Simet. During the course of this project we partnered with Wadham Energy LP (Wadham), who burns 220k ton of rice hulls (RH)/yr generating 200 GWh of electricity/yr and >30k ton/yr RHA. The power generation step produces much more energy (42 kWh/kg of final silicon produced) than required to purify the RHA (5 kWh/kg of Sipv, compared to 65 kWh/kg noted above. Biogenic silica offers three very important foundations for producing high purity silicon. First, wastes from silica accumulating plants, such as rice, corn, many grasses, algae and grains, contain very reactive, amorphous silica from which impurities are easily removed. Second, plants take up only a limited set of, and minimal quantities of the heavy metals present in nature, meaning fewer minerals must be removed. Third, biomass combustion generates a product with intrinsic residual carbon, mixed at nanometer length scales with the SiO2. RHA is 80-90 wt% high surface area (20 m2/g), amorphous SiO2 with some simple mineral content mixed intimately with 5-15 wt% carbon. The mineral content is easily removed by low cost, acid washes using Mayaterials IP, leading to purified rice hull ash (RHAclean) at up to 6N purity. This highly reactive silica is partially extracted from RHAclean at 200 C in an environmentally benign process to adjust SiO2:C ratios to those needed in EAF processing to Sipv. EAF processing with silica depleted rice hull ash (RHASD), with nanometer scale carbon/silica mixing, reacts up to 10x faster than in traditional EAF processing because the physical distances over which the reactions occur are measured in nm vs cm. We have focused on demonstrating the efficiency in existing furnace technologies, meaning our success offers the potential to convert some portion of existing US furnace infrastructure (for Simet) to high purity silicon production. The linkage of our process to the existing infrastructure of the U.S. silicon manufacturing industry, already a world leader, is unique compared to all other initiatives trying to produce Sipv. Purifying the silica/carbon mixture before EAF conversion to Sipv greatly reduces CAPEX and OPEX costs, reducing the final solar energy cost by $0.18-0.24/watt.« less

Macro, mini, micro and nano (M(sup 3)N) technologies for the future

NASA Technical Reports Server (NTRS)

Friedrich, Craig R.; Warrington, Robert O.; Gao, Robert X.; Lin, Gang

1993-01-01

Microelectromechanical systems (MEMS), micro systems technologies (MST), and micromanufacturing are relatively recent phrases or acronyms that have become synonymous with the design, development, and manufacture of 'micro' devices and systems. Micromanufacturing encompasses MEMS or MST and, in addition, includes all of the processes involved in the production of micro things. Integration of mechanical and electrical components, including built-in computers, can be formed into systems which must be connected to the macroworld. Macro, mini, micro, and nano technologies are all a part of MEMS or micromanufacturing. At this point in the development of the technology, it is becoming apparent that mini systems, with micro components, could very well be the economic drivers of the technology for the foreseeable future. Initial research in the fabrication of microdevices using IC processing technology took place over thirty years ago. Anisotropic etching of silicon was used to produce piezoresistive diaphragms. Since the early 60's, there has been gradual progress in MEMS until the early 1980's when worldwide interest in the technology really started to develop. During this time high aspect ratio micromachining using x rays was started in Germany. In 1987 the concept of a 'silicon micromechanics foundry' was proposed. Since then the interest in the U.S., Germany, and Japan has increased to the point where hundreds of millions of dollars of research monies are being funneled into the technology (at least in Germany and Japan) and the technology has been classified as critical or as a technology or national importance by the U.S. government.

A Heat and Mass Transfer Model of a Silicon Pilot Furnace

NASA Astrophysics Data System (ADS)

Sloman, Benjamin M.; Please, Colin P.; Van Gorder, Robert A.; Valderhaug, Aasgeir M.; Birkeland, Rolf G.; Wegge, Harald

2017-10-01

The most common technological route for metallurgical silicon production is to feed quartz and a carbon source ( e.g., coal, coke, or charcoal) into submerged-arc furnaces, which use electrodes as electrical conductors. We develop a mathematical model of a silicon furnace. A continuum approach is taken, and we derive from first principles the equations governing the time evolution of chemical concentrations, gas partial pressures, velocity, and temperature within a one-dimensional vertical section of a furnace. Numerical simulations are obtained for this model and are shown to compare favorably with experimental results obtained using silicon pilot furnaces. A rising interface is shown to exist at the base of the charge, with motion caused by the heating of the pilot furnace. We find that more reactive carbon reduces the silicon monoxide losses, while reducing the carbon content in the raw material mixture causes greater solid and liquid material to build-up in the charge region, indicative of crust formation (which can be detrimental to the silicon production process). We also comment on how the various findings could be relevant for industrial operations.

Bio-inspired Fabrication of Complex Hierarchical Structure in Silicon.

PubMed

Gao, Yang; Peng, Zhengchun; Shi, Tielin; Tan, Xianhua; Zhang, Deqin; Huang, Qiang; Zou, Chuanping; Liao, Guanglan

2015-08-01

In this paper, we developed a top-down method to fabricate complex three dimensional silicon structure, which was inspired by the hierarchical micro/nanostructure of the Morpho butterfly scales. The fabrication procedure includes photolithography, metal masking, and both dry and wet etching techniques. First, microscale photoresist grating pattern was formed on the silicon (111) wafer. Trenches with controllable rippled structures on the sidewalls were etched by inductively coupled plasma reactive ion etching Bosch process. Then, Cr film was angled deposited on the bottom of the ripples by electron beam evaporation, followed by anisotropic wet etching of the silicon. The simple fabrication method results in large scale hierarchical structure on a silicon wafer. The fabricated Si structure has multiple layers with uniform thickness of hundreds nanometers. We conducted both light reflection and heat transfer experiments on this structure. They exhibited excellent antireflection performance for polarized ultraviolet, visible and near infrared wavelengths. And the heat flux of the structure was significantly enhanced. As such, we believe that these bio-inspired hierarchical silicon structure will have promising applications in photovoltaics, sensor technology and photonic crystal devices.

An all-silicon optical PC-to-PC link utilizing USB

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Alberts, Antonie C.; Venter, Petrus J.; du Plessis, Monuko; Rademeyer, Pieter

2013-02-01

An integrated silicon light source still remains the Holy Grail for integrated optical communication systems. Hot carrier luminescent light sources provide a way to create light in a standard CMOS process, potentially enabling cost effective optical communication between CMOS integrated circuits. In this paper we present a 1 Mb/s integrated silicon optical link for information transfer, targeting a real-world integrated solution by connecting two PCs via a USB port while transferring data optically between the devices. This realization represents the first optical communication product prototype utilizing a CMOS light emitter. The silicon light sources which are implemented in a standard 0.35 μm CMOS technology are electrically modulated and detected using a commercial silicon avalanche photodiode. Data rates exceeding 10 Mb/s using silicon light sources have previously been demonstrated using raw bit streams. In this work data is sent in two half duplex streams accompanied with the separate transmission of a clock. Such an optical communication system could find application in high noise environments where data fidelity, range and cost are a determining factor.

Optimization of silicon oxynitrides by plasma-enhanced chemical vapor deposition for an interferometric biosensor

NASA Astrophysics Data System (ADS)

Choo, Sung Joong; Lee, Byung-Chul; Lee, Sang-Myung; Park, Jung Ho; Shin, Hyun-Joon

2009-09-01

In this paper, silicon oxynitride layers deposited with different plasma-enhanced chemical vapor deposition (PECVD) conditions were fabricated and optimized, in order to make an interferometric sensor for detecting biochemical reactions. For the optimization of PECVD silicon oxynitride layers, the influence of the N2O/SiH4 gas flow ratio was investigated. RF power in the PEVCD process was also adjusted under the optimized N2O/SiH4 gas flow ratio. The optimized silicon oxynitride layer was deposited with 15 W in chamber under 25/150 sccm of N2O/SiH4 gas flow rates. The clad layer was deposited with 20 W in chamber under 400/150 sccm of N2O/SiH4 gas flow condition. An integrated Mach-Zehnder interferometric biosensor based on optical waveguide technology was fabricated under the optimized PECVD conditions. The adsorption reaction between bovine serum albumin (BSA) and the silicon oxynitride surface was performed and verified with this device.

The NASA Lewis Research Center program in space solar cell research and technology. [efficient silicon solar cell development program

NASA Technical Reports Server (NTRS)

Brandhorst, H. W., Jr.

1979-01-01

Progress in space solar cell research and technology is reported. An 18 percent-AMO-efficient silicon solar cell, reduction in the radiation damage suffered by silicon solar cells in space, and high efficiency wrap-around contact and thin (50 micrometer) coplanar back contact silicon cells are among the topics discussed. Reduction in the cost of silicon cells for space use, cost effective GaAs solar cells, the feasibility of 30 percent AMO solar energy conversion, and reliable encapsulants for space blankets are also considered.

Process and device integration for silicon tunnel FETs utilizing isoelectronic trap technology to enhance the ON current

NASA Astrophysics Data System (ADS)

Mori, Takahiro; Asai, Hidehiro; Fukuda, Koichi; Matsukawa, Takashi

2018-04-01

A tunnel FET (TFET) is a candidate replacement for conventional MOSFETs to realize low-power LSI. The most significant issue with the practical application of TFETs concerns their low tunneling current. Si is an indirect-gap material with a low band-to-band tunneling probability and is not favored for the channel. However, a new technology has recently been proposed to enhance the tunneling current in Si-TFETs by utilizing isoelectronic trap (IET) technology. IET technology provides an innovative approach to realizing low-power LSI with TFETs. In this paper, state-of-the-art research on Si-TFETs with IET technology from the viewpoint of process and device integration is reviewed.

Silicon carbide, a semiconductor for space power electronics

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Matus, Lawrence G.

1991-01-01

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

A review of materials engineering in silicon-based optical fibres

NASA Astrophysics Data System (ADS)

Healy, Noel; Gibson, Ursula; Peacock, Anna C.

2018-02-01

Semiconductor optical fibre technologies have grown rapidly in the last decade and there are now a range of production and post-processing techniques that allow for a vast degree of control over the core material's optoelectronic properties. These methodologies and the unique optical fibre geometry provide an exciting platform for materials engineering and fibres can now be produced with single crystal cores, low optical losses, tunable strain, and inscribable phase composition. This review discusses the state-of-the-art regarding the production of silicon optical fibres in amorphous and crystalline form and then looks at the post-processing techniques and the improved material quality and new functionality that they afford.

Silicon deposition in nanopores using a liquid precursor.

PubMed

Masuda, Takashi; Tatsuda, Narihito; Yano, Kazuhisa; Shimoda, Tatsuya

2016-11-22

Techniques for depositing silicon into nanosized spaces are vital for the further scaling down of next-generation devices in the semiconductor industry. In this study, we filled silicon into 3.5-nm-diameter nanopores with an aspect ratio of 70 by exploiting thermodynamic behaviour based on the van der Waals energy of vaporized cyclopentasilane (CPS). We originally synthesized CPS as a liquid precursor for semiconducting silicon. Here we used CPS as a gas source in thermal chemical vapour deposition under atmospheric pressure because vaporized CPS can fill nanopores spontaneously. Our estimation of the free energy of CPS based on Lifshitz van der Waals theory clarified the filling mechanism, where CPS vapour in the nanopores readily undergoes capillary condensation because of its large molar volume compared to those of other vapours such as water, toluene, silane, and disilane. Consequently, a liquid-specific feature was observed during the deposition process; specifically, condensed CPS penetrated into the nanopores spontaneously via capillary force. The CPS that filled the nanopores was then transformed into solid silicon by thermal decomposition at 400 °C. The developed method is expected to be used as a nanoscale silicon filling technology, which is critical for the fabrication of future quantum scale silicon devices.

Silicon deposition in nanopores using a liquid precursor

NASA Astrophysics Data System (ADS)

Masuda, Takashi; Tatsuda, Narihito; Yano, Kazuhisa; Shimoda, Tatsuya

2016-11-01

Techniques for depositing silicon into nanosized spaces are vital for the further scaling down of next-generation devices in the semiconductor industry. In this study, we filled silicon into 3.5-nm-diameter nanopores with an aspect ratio of 70 by exploiting thermodynamic behaviour based on the van der Waals energy of vaporized cyclopentasilane (CPS). We originally synthesized CPS as a liquid precursor for semiconducting silicon. Here we used CPS as a gas source in thermal chemical vapour deposition under atmospheric pressure because vaporized CPS can fill nanopores spontaneously. Our estimation of the free energy of CPS based on Lifshitz van der Waals theory clarified the filling mechanism, where CPS vapour in the nanopores readily undergoes capillary condensation because of its large molar volume compared to those of other vapours such as water, toluene, silane, and disilane. Consequently, a liquid-specific feature was observed during the deposition process; specifically, condensed CPS penetrated into the nanopores spontaneously via capillary force. The CPS that filled the nanopores was then transformed into solid silicon by thermal decomposition at 400 °C. The developed method is expected to be used as a nanoscale silicon filling technology, which is critical for the fabrication of future quantum scale silicon devices.

Development of betavoltaic cell technology production based on microchannel silicon and its electrical parameters evaluation.

PubMed

Krasnov, A A; Starkov, V V; Legotin, S A; Rabinovich, O I; Didenko, S I; Murashev, V N; Cheverikin, V V; Yakimov, E B; Fedulova, N A; Rogozev, B I; Laryushkin, A S

2017-03-01

In the paper a manufacturing process of three-dimensional (3D) microchannel structure by silicon (Si) anodic etching was discussed. The possibility of microchannels formation allows to increase the active area more than 100 times. In this structure the p-n junction on the whole Si surface was formed. The obtained data allowed to evaluate the characteristics of the betavoltaic converter with a 3D structure by using isotope 63Ni with a specific activity of 10Ci/g. Copyright © 2016 Elsevier Ltd. All rights reserved.

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

PubMed

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

Microwave components for cellular portable radiotelephone

NASA Astrophysics Data System (ADS)

Muraguchi, Masahiro; Aikawa, Masayoshi

1995-09-01

Mobile and personal communication systems are expected to represent a huge market for microwave components in the coming years. A number of components in silicon bipolar, silicon Bi-CMOS, GaAs MESFET, HBT and HEMT are now becoming available for system application. There are tradeoffs among the competing technologies with regard to performance, cost, reliability and time-to-market. This paper describes process selection and requirements of cost and r.f. performances to microwave semiconductor components for digital cellular and cordless telephones. Furthermore, new circuit techniques which were developed by NTT are presented.

Photovoltaic energy technologies: Health and environmental effects document

NASA Astrophysics Data System (ADS)

Moskowitz, P. D.; Hamilton, L. D.; Morris, S. C.; Rowe, M. D.

1980-09-01

The potential health and environmental consequences of producing electricity by photovoltaic energy systems was analyzed. Potential health and environmental risks are identified in representative fuel and material supply cycles including extraction, processing, refining, fabrication, installation, operation, and isposal for four photovoltaic energy systems (silicon N/P single crystal, silicon metal/insulator/semiconductor (MIS) cell, cadmium sulfide/copper sulfide backwall cell, and gallium arsenide heterojunction cell) delivering equal amounts of useful energy. Each step of the fuel and material supply cycles, materials demands, byproducts, public health, occupational health, and environmental hazards is identified.

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

NASA Astrophysics Data System (ADS)

Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

2009-10-01

We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Molecular dynamics study on splitting of hydrogen-implanted silicon in Smart-Cut® technology

NASA Astrophysics Data System (ADS)

Bing, Wang; Bin, Gu; Rongying, Pan; Sijia, Zhang; Jianhua, Shen

2015-03-01

Defect evolution in a single crystal silicon which is implanted with hydrogen atoms and then annealed is investigated in the present paper by means of molecular dynamics simulation. By introducing defect density based on statistical average, this work aims to quantitatively examine defect nucleation and growth at nanoscale during annealing in Smart-Cut® technology. Research focus is put on the effects of the implantation energy, hydrogen implantation dose and annealing temperature on defect density in the statistical region. It is found that most defects nucleate and grow at the annealing stage, and that defect density increases with the increase of the annealing temperature and the decrease of the hydrogen implantation dose. In addition, the enhancement and the impediment effects of stress field on defect density in the annealing process are discussed. Project supported by the National Natural Science Foundation of China (No. 11372261), the Excellent Young Scientists Supporting Project of Science and Technology Department of Sichuan Province (No. 2013JQ0030), the Supporting Project of Department of Education of Sichuan Province (No. 2014zd3132), the Opening Project of Key Laboratory of Testing Technology for Manufacturing Process, Southwest University of Science and Technology-Ministry of Education (No. 12zxzk02), the Fund of Doctoral Research of Southwest University of Science and Technology (No. 12zx7106), and the Postgraduate Innovation Fund Project of Southwest University of Science and Technology (No. 14ycxjj0121).

A comparative study on the direct deposition of μc-Si:H and plasma-induced recrystallization of a-Si:H: Insight into Si crystallization in a high-density plasma

NASA Astrophysics Data System (ADS)

Zhou, H. P.; Xu, M.; Xu, S.; Feng, Y. Y.; Xu, L. X.; Wei, D. Y.; Xiao, S. Q.

2018-03-01

Deep insight into the crystallization mechanism of amorphous silicon is of theoretical and technological significance for the preparation of high-quality microcrystalline/polycrystalline silicon. In this work, we intensively compare the present two plasma-involved routes, i.e., the direct deposition and recrystallization of precursor amorphous silicon (a-Si) films, to fabricate microcrystalline silicon. Both the directly deposited and recrystallized samples show multi-layered structures as revealed by electronic microscopy. High-density hydrogen plasma involved recrystallization process, which is mediated by the hydrogen diffusion into the deep region of the precursor a-Si film, displays significantly different nucleation configuration, interface properties, and crystallite shape. The underlying mechanisms are analyzed in combination with the interplay of high-density plasma and growing or treated surface.

Radiation Hard Silicon Particle Detectors for Phase-II LHC Trackers

NASA Astrophysics Data System (ADS)

Oblakowska-Mucha, A.

2017-02-01

The major LHC upgrade is planned after ten years of accelerator operation. It is foreseen to significantly increase the luminosity of the current machine up to 1035 cm-2s-1 and operate as the upcoming High Luminosity LHC (HL-LHC) . The major detectors upgrade, called the Phase-II Upgrade, is also planned, a main reason being the aging processes caused by severe particle radiation. Within the RD50 Collaboration, a large Research and Development program has been underway to develop silicon sensors with sufficient radiation tolerance for HL-LHC trackers. In this summary, several results obtained during the testing of the devices after irradiation to HL-LHC levels are presented. Among the studied structures, one can find advanced sensors types like 3D silicon detectors, High-Voltage CMOS technologies, or sensors with intrinsic gain (LGAD). Based on these results, the RD50 Collaboration gives recommendation for the silicon detectors to be used in the detector upgrade.

Advanced Non-Destructive Assessment Technology to Determine the Aging of Silicon Containing Materials for Generation IV Nuclear Reactors

NASA Astrophysics Data System (ADS)

Koenig, T. W.; Olson, D. L.; Mishra, B.; King, J. C.; Fletcher, J.; Gerstenberger, L.; Lawrence, S.; Martin, A.; Mejia, C.; Meyer, M. K.; Kennedy, R.; Hu, L.; Kohse, G.; Terry, J.

2011-06-01

To create an in-situ, real-time method of monitoring neutron damage within a nuclear reactor core, irradiated silicon carbide samples are examined to correlate measurable variations in the material properties with neutron fluence levels experienced by the silicon carbide (SiC) during the irradiation process. The reaction by which phosphorus doping via thermal neutrons occurs in the silicon carbide samples is known to increase electron carrier density. A number of techniques are used to probe the properties of the SiC, including ultrasonic and Hall coefficient measurements, as well as high frequency impedance analysis. Gamma spectroscopy is also used to examine residual radioactivity resulting from irradiation activation of elements in the samples. Hall coefficient measurements produce the expected trend of increasing carrier concentration with higher fluence levels, while high frequency impedance analysis shows an increase in sample impedance with increasing fluence.

Correlation between surface carbon concentration and adhesive strength at the Si cell/EVA interface in a PV module

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dhere, N.G.; Wollam, M.E.; Gadre, K.S.

1997-12-31

Silicon solar cell/EVA composite is being studied with an objective to further improve the manufacturing technology of PV modules. Sample extraction and adhesion strength measurement process has been modified. Silicon and EVA samples were extracted from solar cells of new and field-deployed modules. Optical microscopy, SEM, and AES of samples from new modules revealed EVA islands covering most of the silicon cell surface indicating a cohesive failure. A good correlation was observed between the adhesive strength and surface concentration of carbon. A low carbon concentration which indicated less EVA clinging to cell surface always resulted in low adhesive strengths. Themore » correlation provides a simple technique for inferring properties of EVA.« less

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

Development for 2D pattern quantification method on mask and wafer

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Toyoda, Yasutaka; Wang, Zhigang

2010-03-01

We have developed the effective method of mask and silicon 2-dimensional metrology. The aim of this method is evaluating the performance of the silicon corresponding to Hotspot on a mask. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. 2-dimensional Shape quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. On the other hand, there is roughness in the silicon shape made from a mass-production line. Moreover, there is variation in the silicon shape. For this reason, quantification of silicon shape is important, in order to estimate the performance of a pattern. In order to quantify, the same shape is equalized in two dimensions. And the method of evaluating based on the shape is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. It is possible to analyze variability of the edge of the same position with high precision. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is adaptable to following fields of mask quality management. - Estimate of the correlativity of shape variability and a process margin. - Determination of two-dimensional variability of pattern. - Verification of the performance of the pattern of various kinds of Hotspots. In this report, we introduce the experimental results and the application. We expect that the mask measurement and the shape control on mask production will make a huge contribution to mask yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the shape of the same location of Design, Mask, and Silicon in such a viewpoint.

Improved silicon nitride for advanced heat engines

NASA Technical Reports Server (NTRS)

Yeh, H. C.; Wimmer, J. M.

1986-01-01

Silicon nitride is a high temperature material currently under consideration for heat engine and other applications. The objective is to improve the net shape fabrication technology of Si3N4 by injection molding. This is to be accomplished by optimizing the process through a series of statistically designed matrix experiments. To provide input to the matrix experiments, a wide range of alternate materials and processing parameters was investigated throughout the whole program. The improvement in the processing is to be demonstrated by a 20 percent increase in strength and a 100 percent increase in the Weibull modulus over that of the baseline material. A full characterization of the baseline process was completed. Material properties were found to be highly dependent on each step of the process. Several important parameters identified thus far are the starting raw materials, sinter/hot isostatic pressing cycle, powder bed, mixing methods, and sintering aid levels.

Semiconductor technology program. Progress briefs

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1979-01-01

The current status of NBS work on measurement technology for semiconductor materials, process control, and devices is reported. Results of both in-house and contract research are covered. Highlighted activities include modeling of diffusion processes, analysis of model spreading resistance data, and studies of resonance ionization spectroscopy, resistivity-dopant density relationships in p-type silicon, deep level measurements, photoresist sensitometry, random fault measurements, power MOSFET thermal characteristics, power transistor switching characteristics, and gross leak testing. New and selected on-going projects are described. Compilations of recent publications and publications in press are included.

Non-Contact Technique for Determining the Mechanical Stress in thin Films on Wafers by Profiler

NASA Astrophysics Data System (ADS)

Djuzhev, N. A.; Dedkova, A. A.; E Gusev, E.; Makhiboroda, M. A.; Glagolev, P. Y.

2017-04-01

This paper presents an algorithm for analysis of relief for the purpose of calculating mechanical stresses in a selected direction on the plate in the form of software package Matlab. The method allows for the measurement sample in the local area. It provides a visual representation of the data and allows to get stress distribution on wafer surface. Automated analysis process reduces the likelihood of errors researcher. Achieved time saving during processing results. In carrying out several measurements possible drawing card plate to predict yield crystals. According to this technique done in measurement of mechanical stresses of thermal silicon oxide film on a silicon substrate. Analysis of the results showed objectivity and reliability calculations. This method can be used for selecting the optimal parameters of the material deposition conditions. In software of device-technological simulation TCAD defined process time, temperature and oxidation of the operation of the sample environment for receiving the set value of the dielectric film thickness. Calculated thermal stresses are in the system silicon-silicon oxide. There is a good correlation between numerical simulations and analytical calculation. It is shown that the nature of occurrence of mechanical stress is not limited to the difference of thermal expansion coefficients of materials.

Energy requirement for the production of silicon solar arrays

NASA Technical Reports Server (NTRS)

Lindmayer, J.; Wihl, M.; Scheinne, A.; Morrison, A. D.

1977-01-01

Photovoltaics is subject of an extensive technology assessment in terms of its net energy potential as an alternate energy source. Reduction of quartzite pebbles, refinement, crystal growth, cell processing and panel building are evaluated for energy expenditure compared to direct, indirect, and overhead energies.

Single-silicon CCD-CMOS platform for multi-spectral detection from terahertz to x-rays.

PubMed

Shalaby, Mostafa; Vicario, Carlo; Hauri, Christoph P

2017-11-15

Charge-coupled devices (CCDs) are a well-established imaging technology in the visible and x-ray frequency ranges. However, the small quantum photon energies of terahertz radiation have hindered the use of this mature semiconductor technological platform in this frequency range, leaving terahertz imaging totally dependent on low-resolution bolometer technologies. Recently, it has been shown that silicon CCDs can detect terahertz photons at a high field, but the detection sensitivity is limited. Here we show that silicon, complementary metal-oxide-semiconductor (CMOS) technology offers enhanced detection sensitivity of almost two orders of magnitude, compared to CCDs. Our findings allow us to extend the low-frequency terahertz cutoff to less than 2 THz, nearly closing the technological gap with electronic imagers operating up to 1 THz. Furthermore, with the silicon CCD/CMOS technology being sensitive to mid-infrared (mid-IR) and the x-ray ranges, we introduce silicon as a single detector platform from 1 EHz to 2 THz. This overcomes the present challenge in spatially overlapping a terahertz/mid-IR pump and x-ray probe radiation at facilities such as free electron lasers, synchrotron, and laser-based x-ray sources.

Review: Semiconductor Piezoresistance for Microsystems.

PubMed

Barlian, A Alvin; Park, Woo-Tae; Mallon, Joseph R; Rastegar, Ali J; Pruitt, Beth L

2009-01-01

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

Ferroelectrics for semiconductor devices

NASA Astrophysics Data System (ADS)

Sayer, M.; Wu, Z.; Vasant Kumar, C. V. R.; Amm, D. T.; Griswold, E. M.

1992-11-01

The technology for the implementation of the integration of thin film ferroelectrics with silicon processing for various devices is described, and factors affecting the integration of ferroelectric films with semiconductor processing are discussed. Consideration is also given to film properties, the properties of electrode materials and structures, and the phenomena of ferroelectric fatigue and aging. Particular attention is given to the nonmemory device application of ferroelectrics.

The U.S. and Japanese amorphous silicon technology programs A comparison

NASA Technical Reports Server (NTRS)

Shimada, K.

1984-01-01

The U.S. Department of Energy/Solar Energy Research Institute Amorphous Silicon (a-Si) Solar Cell Program performs R&D on thin-film hydrogenated amorphous silicon for eventual development of stable amorphous silicon cells with 12 percent efficiency by 1988. The Amorphous Silicon Solar Cell Program in Japan is sponsored by the Sunshine Project to develop an alternate energy technology. While the objectives of both programs are to eventually develop a-Si photovoltaic modules and arrays that would produce electricity to compete with utility electricity cost, the U.S. program approach is research oriented and the Japanese is development oriented.

Feasibility of Actively Cooled Silicon Nitride Airfoil for Turbine Applications Demonstrated

NASA Technical Reports Server (NTRS)

Bhatt, Ramakrishna T.

2001-01-01

Nickel-base superalloys currently limit gas turbine engine performance. Active cooling has extended the temperature range of service of nickel-base superalloys in current gas turbine engines, but the margin for further improvement appears modest. Therefore, significant advancements in materials technology are needed to raise turbine inlet temperatures above 2400 F to increase engine specific thrust and operating efficiency. Because of their low density and high-temperature strength and thermal conductivity, in situ toughened silicon nitride ceramics have received a great deal of attention for cooled structures. However, the high processing costs and low impact resistance of silicon nitride ceramics have proven to be major obstacles for widespread applications. Advanced rapid prototyping technology in combination with conventional gel casting and sintering can reduce high processing costs and may offer an affordable manufacturing approach. Researchers at the NASA Glenn Research Center, in cooperation with a local university and an aerospace company, are developing actively cooled and functionally graded ceramic structures. The objective of this program is to develop cost-effective manufacturing technology and experimental and analytical capabilities for environmentally stable, aerodynamically efficient, foreign-object-damage-resistant, in situ toughened silicon nitride turbine nozzle vanes, and to test these vanes under simulated engine conditions. Starting with computer aided design (CAD) files of an airfoil and a flat plate with internal cooling passages, the permanent and removable mold components for gel casting ceramic slips were made by stereolithography and Sanders machines, respectively. The gel-cast part was dried and sintered to final shape. Several in situ toughened silicon nitride generic airfoils with internal cooling passages have been fabricated. The uncoated and thermal barrier coated airfoils and flat plates were burner rig tested for 30 min without and with air cooling. Without cooling, the surface temperature of the flat plate reached approximately 2350 F. Starting with computer aided design (CAD) files of an airfoil and a flat plate with internal cooling passages, the permanent and removable mold components for gel casting ceramic slips were made by stereolithography and Sanders machines, respectively. The gel-cast part was dried and sintered to final shape. Several in situ toughened silicon nitride generic airfoils with internal cooling passages have been fabricated. The uncoated and thermal barrier coated airfoils and flat plates were burner rig tested for 30 min without and with air cooling. Without cooling, the surface temperature of the flat plate reached approximately 2350 F. With cooling, the surface temperature decreased to approximately 1910 F--a drop of approximately 440 F. This preliminary study demonstrates that a near-net-shape silicon nitride airfoil can be fabricated and that silicon nitride can sustain severe thermal shock and the thermal gradients induced by cooling and, thus, is a viable candidate for cooled components.

Advanced Turbine Technology Applications Project (ATTAP)

NASA Technical Reports Server (NTRS)

1992-01-01

This report is the fourth in a series of Annual Technical Summary Reports for the Advanced Turbine Technology Applications Project (ATTAP). This report covers plans and progress on ceramics development for commercial automotive applications over the period 1 Jan. - 31 Dec. 1991. Project effort conducted under this contract is part of the DOE Gas Turbine Highway Vehicle System program. This program is directed to provide the U.S. automotive industry the high-risk, long-range technology necessary to produce gas turbine engines for automobiles with reduced fuel consumption, reduced environmental impact, and a decreased reliance on scarce materials and resources. The program is oriented toward developing the high-risk technology of ceramic structural component design and fabrication, such that industry can carry this technology forward to production in the 1990s. The ATTAP test bed engine, carried over from the previous AGT101 project, is being used for verification testing of the durability of next-generation ceramic components, and their suitability for service at Reference Powertrain Design conditions. This document reports the technical effort conducted by GAPD and the ATTAP subcontractors during the fourth year of the project. Topics covered include ceramic processing definition and refinement, design improvements to the ATTAP test bed engine and test rigs and the methodology development of ceramic impact and fracture mechanisms. Appendices include reports by ATTAP subcontractors in the development of silicon nitride and silicon carbide families of materials and processes.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes.

PubMed

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

Overview of processing activities aimed at higher efficiencies and economical production

NASA Technical Reports Server (NTRS)

Bickler, D. B.

1985-01-01

An overview of processing activities aimed at higher efficiencies and economical production were presented. Present focus is on low-cost process technology for higher-efficiency cells of up to 18% or higher. Process development concerns center on the use of less than optimum silicon sheet, the control of production yields, and making uniformly efficient large-area cells. High-efficiency cell factors that require process development are bulk material perfection, very shallow junction formation, front-surface passivation, and finely detailed metallization. Better bulk properties of the silicon sheet and the keeping of those qualities throughout large areas during cell processing are required so that minority carrier lifetimes are maintained and cell performance is not degraded by high doping levels. When very shallow junctions are formed, the process must be sensitive to metallizatin punch-through, series resisitance in the cell, and control of dopant leaching during surface passivation. There is a need to determine the sensitivity to processing by mathematical modeling and experimental activities.

3D active edge silicon sensors: Device processing, yield and QA for the ATLAS-IBL production

DOE Office of Scientific and Technical Information (OSTI.GOV)

Da Vià, Cinzia; Boscardil, Maurizio; Dalla Betta, GianFranco

2013-01-01

3D silicon sensors, where plasma micromachining is used to etch deep narrow apertures in the silicon substrate to form electrodes of PIN junctions, were successfully manufactured in facilities in Europe and USA. In 2011 the technology underwent a qualification process to establish its maturity for a medium scale production for the construction of a pixel layer for vertex detection, the Insertable B-Layer (IBL) at the CERN-LHC ATLAS experiment. The IBL collaboration, following that recommendation from the review panel, decided to complete the production of planar and 3D sensors and endorsed the proposal to build enough modules for a mixed IBLmore » sensor scenario where 25% of 3D modules populate the forward and backward part of each stave. The production of planar sensors will also allow coverage of 100% of the IBL, in case that option was required. This paper will describe the processing strategy which allowed successful 3D sensor production, some of the Quality Assurance (QA) tests performed during the pre-production phase and the production yield to date.« less

InGaAlAsPN: A Materials System for Silicon Based Optoelectronics and Heterostructure Device Technologies

NASA Technical Reports Server (NTRS)

Broekaert, T. P. E.; Tang, S.; Wallace, R. M.; Beam, E. A., III; Duncan, W. M.; Kao, Y. -C.; Liu, H. -Y.

1995-01-01

A new material system is proposed for silicon based opto-electronic and heterostructure devices; the silicon lattice matched compositions of the (In,Ga,Al)-(As,P)N 3-5 compounds. In this nitride alloy material system, the bandgap is expected to be direct at the silicon lattice matched compositions with a bandgap range most likely to be in the infrared to visible. At lattice constants ranging between those of silicon carbide and silicon, a wider bandgap range is expected to be available and the high quality material obtained through lattice matching could enable applications such as monolithic color displays, high efficiency multi-junction solar cells, opto-electronic integrated circuits for fiber communications, and the transfer of existing 3-5 technology to silicon.

Advanced Silicon-on-Insulator: Crystalline Silicon on Atomic Layer Deposited Beryllium Oxide.

PubMed

Min Lee, Seung; Hwan Yum, Jung; Larsen, Eric S; Chul Lee, Woo; Keun Kim, Seong; Bielawski, Christopher W; Oh, Jungwoo

2017-10-16

Silicon-on-insulator (SOI) technology improves the performance of devices by reducing parasitic capacitance. Devices based on SOI or silicon-on-sapphire technology are primarily used in high-performance radio frequency (RF) and radiation sensitive applications as well as for reducing the short channel effects in microelectronic devices. Despite their advantages, the high substrate cost and overheating problems associated with complexities in substrate fabrication as well as the low thermal conductivity of silicon oxide prevent broad applications of this technology. To overcome these challenges, we describe a new approach of using beryllium oxide (BeO). The use of atomic layer deposition (ALD) for producing this material results in lowering the SOI wafer production cost. Furthermore, the use of BeO exhibiting a high thermal conductivity might minimize the self-heating issues. We show that crystalline Si can be grown on ALD BeO and the resultant devices exhibit potential for use in advanced SOI technology applications.

Analysis of energy production with different photovoltaic technologies in the Colombian geography

NASA Astrophysics Data System (ADS)

Muñoz, Y.; Zafra, D.; Acevedo, V.; Ospino, A.

2014-06-01

This research has analyzed the photovoltaic technologies, Polycrystalline silicon, Monocrystalline Silicon, GIS, Cadmium Tellurium and Amorphous Silicon; in eight cities of the Colombian territory, in order to obtain a clear idea of what is the most appropriate for each city or region studied. PVsyst simulation software has been used to study in detail each photovoltaic technology, for an installed capacity of 100kW knowing the specific data of losses by temperature, mismatch, efficiency, wiring, angle inclination of the arrangement, among others

Experimental and theoretical rationalization of the growth mechanism of silicon quantum dots in non-stoichiometric SiN x : role of chlorine in plasma enhanced chemical vapour deposition

NASA Astrophysics Data System (ADS)

Mon-Pérez, E.; Salazar, J.; Ramos, E.; Santoyo Salazar, J.; López Suárez, A.; Dutt, A.; Santana, G.; Marel Monroy, B.

2016-11-01

Silicon quantum dots (Si-QDs) embedded in an insulator matrix are important from a technological and application point of view. Thus, being able to synthesize them in situ during the matrix growth process is technologically advantageous. The use of SiH2Cl2 as the silicon precursor in the plasma enhanced chemical vapour deposition (PECVD) process allows us to obtain Si-QDs without post-thermal annealing. Foremost in this work, is a theoretical rationalization of the mechanism responsible for Si-QD generation in a film including an analysis of the energy released by the extraction of HCl and the insertion of silylene species into the terminal surface bonds. From the results obtained using density functional theory (DFT), we propose an explanation of the mechanism responsible for the formation of Si-QDs in non-stoichiometric SiN x starting from chlorinated precursors in a PECVD system. Micrograph images obtained through transmission electron microscopy confirmed the presence of Si-QDs, even in nitrogen-rich (N-rich) samples. The film stoichiometry was controlled by varying the growth parameters, in particular the NH3/SiH2Cl2 ratio and hydrogen dilution. Experimental and theoretical results together show that using a PECVD system, along with chlorinated precursors it is possible to obtain Si-QDs at a low substrate temperature without annealing treatment. The optical property studies carried out in the present work highlight the prospects of these thin films for down shifting and as an antireflection coating in silicon solar cells.

Initial results for the silicon monolithically interconnected solar cell product

NASA Technical Reports Server (NTRS)

Dinetta, L. C.; Shreve, K. P.; Cotter, J. E.; Barnett, A. M.

1995-01-01

This proprietary technology is based on AstroPower's electrostatic bonding and innovative silicon solar cell processing techniques. Electrostatic bonding allows silicon wafers to be permanently attached to a thermally matched glass superstrate and then thinned to final thicknesses less than 25 micron. These devices are based on the features of a thin, light-trapping silicon solar cell: high voltage, high current, light weight (high specific power) and high radiation resistance. Monolithic interconnection allows the fabrication costs on a per watt basis to be roughly independent of the array size, power or voltage, therefore, the cost effectiveness to manufacture solar cell arrays with output powers ranging from milliwatts up to four watts and output voltages ranging from 5 to 500 volts will be similar. This compares favorably to conventionally manufactured, commercial solar cell arrays, where handling of small parts is very labor intensive and costly. In this way, a wide variety of product specifications can be met using the same fabrication techniques. Prototype solar cells have demonstrated efficiencies greater than 11%. An open-circuit voltage of 5.4 volts, fill factor of 65%, and short-circuit current density of 28 mA/sq cm at AM1.5 illumination are typical. Future efforts are being directed to optimization of the solar cell operating characteristics as well as production processing. The monolithic approach has a number of inherent advantages, including reduced cost per interconnect and increased reliability of array connections. These features make this proprietary technology an excellent candidate for a large number of consumer products.

Solid state laser applications in photovoltaics manufacturing

NASA Astrophysics Data System (ADS)

Dunsky, Corey; Colville, Finlay

2008-02-01

Photovoltaic energy conversion devices are on a rapidly accelerating growth path driven by increasing government and societal pressure to use renewable energy as part of an overall strategy to address global warming attributed to greenhouse gas emissions. Initially supported in several countries by generous tax subsidies, solar cell manufacturers are relentlessly pushing the performance/cost ratio of these devices in a quest to reach true cost parity with grid electricity. Clearly this eventual goal will result in further acceleration in the overall market growth. Silicon wafer based solar cells are currently the mainstay of solar end-user installations with a cost up to three times grid electricity. But next-generation technology in the form of thin-film devices promises streamlined, high-volume manufacturing and greatly reduced silicon consumption, resulting in dramatically lower per unit fabrication costs. Notwithstanding the modest conversion efficiency of thin-film devices compared to wafered silicon products (around 6-10% versus 15-20%), this cost reduction is driving existing and start-up solar manufacturers to switch to thin-film production. A key aspect of these devices is patterning large panels to create a monolithic array of series-interconnected cells to form a low current, high voltage module. This patterning is accomplished in three critical scribing processes called P1, P2, and P3. Lasers are the technology of choice for these processes, delivering the desired combination of high throughput and narrow, clean scribes. This paper examines these processes and discusses the optimization of industrial lasers to meet their specific needs.

Reduced Moment-Based Models for Oxygen Precipitates and Dislocation Loops in Silicon

NASA Astrophysics Data System (ADS)

Trzynadlowski, Bart

The demand for ever smaller, higher-performance integrated circuits and more efficient, cost-effective solar cells continues to push the frontiers of process technology. Fabrication of silicon devices requires extremely precise control of impurities and crystallographic defects. Failure to do so not only reduces performance, efficiency, and yield, it threatens the very survival of commercial enterprises in today's fiercely competitive and price-sensitive global market. The presence of oxygen in silicon is an unavoidable consequence of the Czochralski process, which remains the most popular method for large-scale production of single-crystal silicon. Oxygen precipitates that form during thermal processing cause distortion of the surrounding silicon lattice and can lead to the formation of dislocation loops. Localized deformation caused by both of these defects introduces potential wells that trap diffusing impurities such as metal atoms, which is highly desirable if done far away from sensitive device regions. Unfortunately, dislocations also reduce the mechanical strength of silicon, which can cause wafer warpage and breakage. Engineers must negotiate this and other complex tradeoffs when designing fabrication processes. Accomplishing this in a complex, modern process involving a large number of thermal steps is impossible without the aid of computational models. In this dissertation, new models for oxygen precipitation and dislocation loop evolution are described. An oxygen model using kinetic rate equations to evolve the complete precipitate size distribution was developed first. This was then used to create a reduced model tracking only the moments of the size distribution. The moment-based model was found to run significantly faster than its full counterpart while accurately capturing the evolution of oxygen precipitates. The reduced model was fitted to experimental data and a sensitivity analysis was performed to assess the robustness of the results. Source code for both models is included. A moment-based model for dislocation loop formation from {311} defects in ion-implanted silicon was also developed and validated against experimental data. Ab initio density functional theory calculations of stacking faults and edge dislocations were performed to extract energies and elastic properties. This allowed the effect of applied stress on the evolution of {311} defects and dislocation loops to be investigated.

High Productivity DRIE solutions for 3D-SiP and MEMS Volume Manufacturing

NASA Astrophysics Data System (ADS)

Puech, M.; Thevenoud, JM; Launay, N.; Arnal, N.; Godinat, P.; Andrieu, B.; Gruffat, JM

2006-04-01

Emerging 3D-SiP technologies and high volume MEMS applications require high productivity mass production DRIE systems. The Alcatel DRIE product range has recently been optimised to reach the highest process and hardware production performances. A study based on sub-micron high aspect ratio structures encountered in the most stringent 3D-SiP has been carried out. The optimization of the Bosch process parameters has resulted in ultra high silicon etch rates, with unrivalled uniformity and repeatability leading to excellent process. In parallel, most recent hardware and proprietary design optimization including vacuum pumping lines, process chamber, wafer chucks, pressure control system, gas delivery are discussed. These improvements have been monitored in a mass production environment for a mobile phone application. Field data analysis shows a significant reduction of cost of ownership thanks to increased throughput and much lower running costs. These benefits are now available for all 3D-SiP and high volume MEMS applications. The typical etched patterns include tapered trenches for CMOS imagers, through silicon via holes for die stacking, well controlled profile angle for 3D high precision inertial sensors, and large exposed area features for inkjet printer heads and Silicon microphones.

Composite Transparent Electrode of Graphene Nanowalls and Silver Nanowires on Micropyramidal Si for High-Efficiency Schottky Junction Solar Cells.

PubMed

Jiao, Tianpeng; Liu, Jian; Wei, Dapeng; Feng, Yanhui; Song, Xuefen; Shi, Haofei; Jia, Shuming; Sun, Wentao; Du, Chunlei

2015-09-16

The conventional graphene-silicon Schottky junction solar cell inevitably involves the graphene growth and transfer process, which results in complicated technology, loss of quality of the graphene, extra cost, and environmental unfriendliness. Moreover, the conventional transfer method is not well suited to conformationally coat graphene on a three-dimensional (3D) silicon surface. Thus, worse interfacial conditions are inevitable. In this work, we directly grow graphene nanowalls (GNWs) onto the micropyramidal silicon (MP) by the plasma-enhanced chemical vapor deposition method. By controlling growth time, the cell exhibits optimal pristine photovoltaic performance of 3.8%. Furthermore, we improve the conductivity of the GNW electrode by introducing the silver nanowire (AgNW) network, which could achieve lower sheet resistance. An efficiency of 6.6% has been obtained for the AgNWs-GNWs-MP solar cell without any chemical doping. Meanwhile, the cell exhibits excellent stability exposed to air. Our studies show a promising way to develop simple-technology, low-cost, high-efficiency, and stable Schottky junction solar cells.

[Effect of silicon coating on bonding strength of ceramics and titanium].

PubMed

Zhou, Shu; Wang, Yu; Zhang, Fei-Min; Guang, Han-Bing

2009-06-01

This study investigated the effect of silicon coating (SiO2) by solution-gelatin (Sol-Gel) technology on bonding strength of titanium and ceramics. Sixteen pure titanium specimens with the size of 25 mm x 3 mm x 0.5 mm were divided into two groups (n=8), test group was silicon coated by Sol-Gel technology, the other one was control group. The middle area of the samples were veneered with Vita Titankeramik system, the phase composition of two specimens were characterized by X-ray diffraction (XRD). The bonding strength of titanium/porcelain was evaluated using three-point bending test. The interface of titanium and porcelain and fractured titanium surface were investigated by scanning electron microscope (SEM) with energy depressive spectrum (EDS). Contents of surface silicon increased after modification with silicon coated by Sol-Gel technology. The mean bonding strength of test group and control group were (37.768 +/- 0.777) MPa and (29.483 +/- 1.007) MPa. There was a statistically significant difference (P=0.000) between them. The bonded ceramic boundary of test group was wider than control group. Silicon coating by Sol-Gel technology was significant in improving bonding strength of titanium/Vita Titankeramik system.

Microstamped opto-mechanical actuator for tactile displays

NASA Astrophysics Data System (ADS)

Camargo, Carlos J.; Torras, Núria; Campanella, Humberto; Marshall, Jean E.; Zinoviev, Kirill; Campo, Eva M.; Terentjev, Eugene M.; Esteve, Jaume

2011-10-01

Over the last few years, several technologies have been adapted for use in tactile displays, such as thermo-pneumatic actuators, piezoelectric polymers and dielectric elastomers. None of these approaches offers high-performance for refreshable Braille display system (RBDS), due to considerations of weight, power efficiency and response speed. Optical actuation offers an attractive alternative to solve limitations of current-art technologies, allowing electromechanical decoupling, elimination of actuation circuits and remote controllability. Creating these opticallydriven devices requires liquid crystal - carbon nanotube (LC-CNT) composites that show a reversible shape change in response to an applied light. This work thus reports on novel opto-actuated Braille dots based on LC-CNT composite and silicon mold microstamping. The manufacturing approach succeeds on producing blisters according to the Braille standard for the visually impaired, by taking shear-aligned LC-CNT films and silicon stamps. For this application, we need to define specifically-shaped structures. Some technologies have succeeded on elastomer microstructuring. Nevertheless, they are not applicable for LC-CNT molding because they do not consider the stretching of the polymer which is required for LC-CNT fabrication. Our process demonstrates that composites micro-molding and their 3-D structuring is feasible by silicon-based stamping. Its work principle involves the mechanical stretching, allowing the LC mesogens alignment.

Conformal coating of amorphous silicon and germanium by high pressure chemical vapor deposition for photovoltaic fabrics

NASA Astrophysics Data System (ADS)

Ji, Xiaoyu; Cheng, Hiu Yan; Grede, Alex J.; Molina, Alex; Talreja, Disha; Mohney, Suzanne E.; Giebink, Noel C.; Badding, John V.; Gopalan, Venkatraman

2018-04-01

Conformally coating textured, high surface area substrates with high quality semiconductors is challenging. Here, we show that a high pressure chemical vapor deposition process can be employed to conformally coat the individual fibers of several types of flexible fabrics (cotton, carbon, steel) with electronically or optoelectronically active materials. The high pressure (˜30 MPa) significantly increases the deposition rate at low temperatures. As a result, it becomes possible to deposit technologically important hydrogenated amorphous silicon (a-Si:H) from silane by a simple and very practical pyrolysis process without the use of plasma, photochemical, hot-wire, or other forms of activation. By confining gas phase reactions in microscale reactors, we show that the formation of undesired particles is inhibited within the microscale spaces between the individual wires in the fabric structures. Such a conformal coating approach enables the direct fabrication of hydrogenated amorphous silicon-based Schottky junction devices on a stainless steel fabric functioning as a solar fabric.

Ultrafast all-optical arithmetic logic based on hydrogenated amorphous silicon microring resonators

NASA Astrophysics Data System (ADS)

Gostimirovic, Dusan; Ye, Winnie N.

2016-03-01

For decades, the semiconductor industry has been steadily shrinking transistor sizes to fit more performance into a single silicon-based integrated chip. This technology has become the driving force for advances in education, transportation, and health, among others. However, transistor sizes are quickly approaching their physical limits (channel lengths are now only a few silicon atoms in length), and Moore's law will likely soon be brought to a stand-still despite many unique attempts to keep it going (FinFETs, high-k dielectrics, etc.). This technology must then be pushed further by exploring (almost) entirely new methodologies. Given the explosive growth of optical-based long-haul telecommunications, we look to apply the use of high-speed optics as a substitute to the digital model; where slow, lossy, and noisy metal interconnections act as a major bottleneck to performance. We combine the (nonlinear) optical Kerr effect with a single add-drop microring resonator to perform the fundamental AND-XOR logical operations of a half adder, by all-optical means. This process is also applied to subtraction, higher-order addition, and the realization of an all-optical arithmetic logic unit (ALU). The rings use hydrogenated amorphous silicon as a material with superior nonlinear properties to crystalline silicon, while still maintaining CMOS-compatibility and the many benefits that come with it (low cost, ease of fabrication, etc.). Our method allows for multi-gigabit-per-second data rates while maintaining simplicity and spatial minimalism in design for high-capacity manufacturing potential.

Sol-gel derived antireflective structures for applications in silicon solar cells

NASA Astrophysics Data System (ADS)

Karasiński, Paweł; Skolik, Marcin

2016-12-01

This work presents theoretical and experimental results of antireflective coatings (ARCs) obtained for applications in silicon solar cells. ARCs were derived from sol-gel process and dip-coated using silica (SiO2) and titania (TiO2). Theoretical results were obtained using 2×2 transfer matrix calculation method. Technological process of SiO2 and TiO2 thin film fabrication as well as measurement techniques are described in this paper. Strong correlation between theoretical and experimental data is demonstrated. It is shown, that weighted average reflection from a substrate can be reduced ten times with the use of SiO2/TiO2/Si double layer ARCs, when compared to a bare silica substrate.

Enhancing the brightness of electrically driven single-photon sources using color centers in silicon carbide

NASA Astrophysics Data System (ADS)

Khramtsov, Igor A.; Vyshnevyy, Andrey A.; Fedyanin, Dmitry Yu.

2018-03-01

Practical applications of quantum information technologies exploiting the quantum nature of light require efficient and bright true single-photon sources which operate under ambient conditions. Currently, point defects in the crystal lattice of diamond known as color centers have taken the lead in the race for the most promising quantum system for practical non-classical light sources. This work is focused on a different quantum optoelectronic material, namely a color center in silicon carbide, and reveals the physics behind the process of single-photon emission from color centers in SiC under electrical pumping. We show that color centers in silicon carbide can be far superior to any other quantum light emitter under electrical control at room temperature. Using a comprehensive theoretical approach and rigorous numerical simulations, we demonstrate that at room temperature, the photon emission rate from a p-i-n silicon carbide single-photon emitting diode can exceed 5 Gcounts/s, which is higher than what can be achieved with electrically driven color centers in diamond or epitaxial quantum dots. These findings lay the foundation for the development of practical photonic quantum devices which can be produced in a well-developed CMOS compatible process flow.

Uncooled Terahertz real-time imaging 2D arrays developed at LETI: present status and perspectives

NASA Astrophysics Data System (ADS)

Simoens, François; Meilhan, Jérôme; Dussopt, Laurent; Nicolas, Jean-Alain; Monnier, Nicolas; Sicard, Gilles; Siligaris, Alexandre; Hiberty, Bruno

2017-05-01

As for other imaging sensor markets, whatever is the technology, the commercial spread of terahertz (THz) cameras has to fulfil simultaneously the criteria of high sensitivity and low cost and SWAP (size, weight and power). Monolithic silicon-based 2D sensors integrated in uncooled THz real-time cameras are good candidates to meet these requirements. Over the past decade, LETI has been studying and developing such arrays with two complimentary technological approaches, i.e. antenna-coupled silicon bolometers and CMOS Field Effect Transistors (FET), both being compatible to standard silicon microelectronics processes. LETI has leveraged its know-how in thermal infrared bolometer sensors in developing a proprietary architecture for THz sensing. High technological maturity has been achieved as illustrated by the demonstration of fast scanning of large field of view and the recent birth of a commercial camera. In the FET-based THz field, recent works have been focused on innovative CMOS read-out-integrated circuit designs. The studied architectures take advantage of the large pixel pitch to enhance the flexibility and the sensitivity: an embedded in-pixel configurable signal processing chain dramatically reduces the noise. Video sequences at 100 frames per second using our 31x31 pixels 2D Focal Plane Arrays (FPA) have been achieved. The authors describe the present status of these developments and perspectives of performance evolutions are discussed. Several experimental imaging tests are also presented in order to illustrate the capabilities of these arrays to address industrial applications such as non-destructive testing (NDT), security or quality control of food.

SPS Energy Conversion Power Management Workshop

NASA Technical Reports Server (NTRS)

1980-01-01

Energy technology concerning photovoltaic conversion, solar thermal conversion systems, and electrical power distribution processing is discussed. The manufacturing processes involving solar cells and solar array production are summarized. Resource issues concerning gallium arsenides and silicon alternatives are reported. Collector structures for solar construction are described and estimates in their service life, failure rates, and capabilities are presented. Theories of advanced thermal power cycles are summarized. Power distribution system configurations and processing components are presented.

Manufacturability study of masks created by inverse lithography technology (ILT)

NASA Astrophysics Data System (ADS)

Martin, Patrick M.; Progler, C. J.; Xiao, G.; Gray, R.; Pang, L.; Liu, Y.

2005-11-01

As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes unpredictable; and, high MEEF imposes much more stringent demands on mask quality. Therefore, in order for any new lithography technology to be adopted into production, mask manufacturability must be studied thoroughly and carefully. In this paper we will present the mask manufacturability study on mask patterns created using Inverse Lithography Technology (ILT). Unlike conventional OPC methodologies, ILT uses a unique outcome-based technology to mathematically determine the mask features that produce the desired on-wafer results. ILT solves the most critical litho challenges of the deep sub-wavelength era. Potential benefits include: higher yield; expanded litho process windows; superb pattern fidelity at 90, 65 & 45-nm nodes; and reduced time-to-silicon - all without changing the existing lithography infrastructure and design-to-silicon flow. In this study a number of cell structures were selected and used as test patterns. "Luminized patterns" were generated for binary mask and attenuated phase-shift mask. Both conventional OPC patterns and "luminized patterns" were put on a test reticle side by side, and they all have a number of variations in term of correction aggressivity level and mask complexity. Mask manufacturability, including data fracturing, writing time, mask inspection, and metrology were studied. The results demonstrate that, by optimizing the inspection recipe, masks created using ILT technology can be made and qualified using current processes with a reasonable turn-around time.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

Highly organised and dense vertical silicon nanowire arrays grown in porous alumina template on <100> silicon wafers

PubMed Central

2013-01-01

In this work, nanoimprint lithography combined with standard anodization etching is used to make perfectly organised triangular arrays of vertical cylindrical alumina nanopores onto standard <100>−oriented silicon wafers. Both the pore diameter and the period of alumina porous array are well controlled and can be tuned: the periods vary from 80 to 460 nm, and the diameters vary from 15 nm to any required diameter. These porous thin layers are then successfully used as templates for the guided epitaxial growth of organised mono-crystalline silicon nanowire arrays in a chemical vapour deposition chamber. We report the densities of silicon nanowires up to 9 × 109 cm−2 organised in highly regular arrays with excellent diameter distribution. All process steps are demonstrated on surfaces up to 2 × 2 cm2. Specific emphasis was made to select techniques compatible with microelectronic fabrication standards, adaptable to large surface samples and with a reasonable cost. Achievements made in the quality of the porous alumina array, therefore on the silicon nanowire array, widen the number of potential applications for this technology, such as optical detectors or biological sensors. PMID:23773702

Particulate-free porous silicon networks for efficient capacitive deionization water desalination

PubMed Central

Metke, Thomas; Westover, Andrew S.; Carter, Rachel; Oakes, Landon; Douglas, Anna; Pint, Cary L.

2016-01-01

Energy efficient water desalination processes employing low-cost and earth-abundant materials is a critical step to sustainably manage future human needs for clean water resources. Here we demonstrate that porous silicon – a material harnessing earth abundance, cost, and environmental/biological compatibility is a candidate material for water desalination. With appropriate surface passivation of the porous silicon material to prevent surface corrosion in aqueous environments, we show that porous silicon templates can enable salt removal in capacitive deionization (CDI) ranging from 0.36% by mass at the onset from fresh to brackish water (10 mM, or 0.06% salinity) to 0.52% in ocean water salt concentrations (500 mM, or ~0.3% salinity). This is on par with reports of most carbon nanomaterial based CDI systems based on particulate electrodes and covers the full salinity range required of a CDI system with a total ocean-to-fresh water required energy input of ~1.45 Wh/L. The use of porous silicon for CDI enables new routes to directly couple water desalination technology with microfluidic systems and photovoltaics that natively use silicon materials, while mitigating adverse effects of water contamination occurring from nanoparticulate-based CDI electrodes. PMID:27101809

Particulate-free porous silicon networks for efficient capacitive deionization water desalination.

PubMed

Metke, Thomas; Westover, Andrew S; Carter, Rachel; Oakes, Landon; Douglas, Anna; Pint, Cary L

2016-04-22

Energy efficient water desalination processes employing low-cost and earth-abundant materials is a critical step to sustainably manage future human needs for clean water resources. Here we demonstrate that porous silicon - a material harnessing earth abundance, cost, and environmental/biological compatibility is a candidate material for water desalination. With appropriate surface passivation of the porous silicon material to prevent surface corrosion in aqueous environments, we show that porous silicon templates can enable salt removal in capacitive deionization (CDI) ranging from 0.36% by mass at the onset from fresh to brackish water (10 mM, or 0.06% salinity) to 0.52% in ocean water salt concentrations (500 mM, or ~0.3% salinity). This is on par with reports of most carbon nanomaterial based CDI systems based on particulate electrodes and covers the full salinity range required of a CDI system with a total ocean-to-fresh water required energy input of ~1.45 Wh/L. The use of porous silicon for CDI enables new routes to directly couple water desalination technology with microfluidic systems and photovoltaics that natively use silicon materials, while mitigating adverse effects of water contamination occurring from nanoparticulate-based CDI electrodes.

Fabricating micro-instruments in surface-micromachined polycrystalline silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comtois, J.H.; Michalicek, M.A.; Barron, C.C.

1997-04-01

Smaller, lighter instruments can be fabricated as Micro-Electro-Mechanical Systems (MEMS), having micron scale moving parts packaged together with associated control and measurement electronics. Batch fabrication of these devices will make economical applications such as condition-based machine maintenance and remote sensing. The choice of instrumentation is limited only by the designer`s imagination. This paper presents one genre of MEMS fabrication, surface-micromachined polycrystalline silicon (polysilicon). Two currently available but slightly different polysilicon processes are presented. One is the ARPA-sponsored ``Multi-User MEMS ProcesS`` (MUMPS), available commercially through MCNC; the other is the Sandia National Laboratories ``Sandia Ultra-planar Multilevel MEMS Technology`` (SUMMiT). Example componentsmore » created in both processes will be presented, with an emphasis on actuators, actuator force testing instruments, and incorporating actuators into larger instruments.« less

Thickness optimization of auricular silicone scaffold based on finite element analysis.

PubMed

Jiang, Tao; Shang, Jianzhong; Tang, Li; Wang, Zhuo

2016-01-01

An optimized thickness of a transplantable auricular silicone scaffold was researched. The original image data were acquired from CT scans, and reverse modeling technology was used to build a digital 3D model of an auricle. The transplant process was simulated in ANSYS Workbench by finite element analysis (FEA), solid scaffolds were manufactured based on the FEA results, and the transplantable artificial auricle was finally obtained with an optimized thickness, as well as sufficient intensity and hardness. This paper provides a reference for clinical transplant surgery. Copyright © 2015 Elsevier Ltd. All rights reserved.

Integration of mask and silicon metrology in DFM

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Sugiyama, Akiyuki; Toyoda, Yasutaka

2009-03-01

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

SiC Design Guide: Manufacture of Silicon Carbide Products (Briefing charts)

DTIC Science & Technology

2010-06-08

DISTRIBUTION STATEMENT A: Approved for public release; distribution is unlimited. 13. SUPPLEMENTARY NOTES Presented at Mirror Technology Days, Boulder...coatings. 15. SUBJECT TERMS Mirrors , structures, silicon carbide, design, inserts, coatings, pockets, ribs, bonding, threads 16. SECURITY...Prescribed by ANSI Std. 239.18 purify protect transport SiC Design Guide Manufacture of Silicon Carbide Products Mirror Technology Days June 7 to 9, 2010

Review: Semiconductor Piezoresistance for Microsystems

PubMed Central

Barlian, A. Alvin; Park, Woo-Tae; Mallon, Joseph R.; Rastegar, Ali J.; Pruitt, Beth L.

2010-01-01

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers. PMID:20198118

Operando plasmon-enhanced Raman spectroscopy in silicon anodes for Li-ion battery

NASA Astrophysics Data System (ADS)

Miroshnikov, Yana; Zitoun, David

2017-11-01

Silicon, an attractive candidate for high-energy lithium-ion batteries (LIBs), displays an alloying mechanism with lithium and presents several unique characteristics which make it an interesting scientific topic and also a technological challenge. In situ local probe measurements have been recently developed to understand the lithiation process and propose an effective remedy to the failure mechanisms. One of the most specific techniques, which is able to follow the phase changes in poorly crystallized electrode materials, makes use of Raman spectroscopy within the battery, i.e., in operando mode. Such an approach has been successful but is still limited by the rather signal-to-noise ratio of the spectroscopy. Herein, the operando Raman signal from the silicon anodes is enhanced by plasmonic nanoparticles following the known surface-enhanced Raman spectroscopy (SERS). Coinage metals (Ag and Au) display a surface plasmon resonance in the visible and allow the SERS effect to take place. We have found that the as-prepared materials reach high specific capacities over 1000 mAh/g with stability over more than 1000 cycles at 1C rate and can be suitable to perform as anodes in LIB. Moreover, the incorporation of coinage metals enables SERS to take place specifically on the surface of silicon. Consequently, by using a specially designed Raman cell, it is possible to follow the processes in a silicon-coinage metal-based battery trough operando SERS measurements.

A bipolar analog front-end integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

A low noise, low power, high bandwidth, radiation hard, silicon bipolar transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using CBIC-U2, 4 GHz f(sub T) complementary bipolar technology. Each channel contains the following functions: low noise preamplification, pulse shaping, and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 micron pitch double-sided silicon strip detector. The chip measures 6.8 mm by 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to four times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Phi = 10(exp 14) protons/sq cm have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

The Selective Epitaxy of Silicon at Low Temperatures.

NASA Astrophysics Data System (ADS)

Lou, Jen-Chung

1991-01-01

This dissertation has developed a process for the selective epitaxial growth (SEG) of silicon at low temperatures using a dichlorosilane-hydrogen mixture in a hot-wall low pressure chemical vapor deposition (LPCVD) reactor. Some basic issues concerning the quality of epilayers --substrate preparation, ex-situ and in-situ cleaning, and deposition cycle, have been studied. We find it necessary to use a plasma etch to open epitaxial windows for the SEG of Si. A cycled plasma etch, a thin sacrificial oxide growth, and an oxide etching step can completely remove plasma-etch-induced surface damage and contaminants, which result in high quality epilayers. A practical wafer cleaning step is developed for low temperature Si epitaxial growth. An ex-situ HF vapor treatment can completely remove chemical oxide from the silicon surface and retard the reoxidation of the silicon surface. An in-situ low-concentration DCS cycle can aid in decomposition of surface oxide during a 900 ^circC H_2 prebake step. An HF vapor treatment combined with a low-concentration of DCS cycle consistently achieves defect-free epilayers at 850^circC and lower temperatures. We also show that a BF_sp{2}{+ } or F^+ ion implantation is a potential ex-situ wafer cleaning process for SEG of Si at low temperatures. The mechanism for the formation of surface features on Si epilayers is also discussed. Based on O ^+ ion implantation, we showed that the oxygen incorporation in silicon epilayers suppresses the Si growth rate. Therefore, we attribute the formation of surface features to the local reduction of the Si growth rate due to the dissolution of oxide islands at the epi/substrate interface. Finally, with this developed process for the SEG of silicon, defect-free overgrown epilayers are also obtained. This achievement demonstrates the feasibility for the future silicon-on-oxide (SOI) manufacturing technology.

Novel fabrication of silicon carbide based ceramics for nuclear applications

NASA Astrophysics Data System (ADS)

Singh, Abhishek Kumar

Advances in nuclear reactor technology and the use of gas-cooled fast reactors require the development of new materials that can operate at the higher temperatures expected in these systems. These materials include refractory alloys based on Nb, Zr, Ta, Mo, W, and Re; ceramics and composites such as SiC--SiCf; carbon--carbon composites; and advanced coatings. Besides the ability to handle higher expected temperatures, effective heat transfer between reactor components is necessary for improved efficiency. Improving thermal conductivity of the fuel can lower the center-line temperature and, thereby, enhance power production capabilities and reduce the risk of premature fuel pellet failure. Crystalline silicon carbide has superior characteristics as a structural material from the viewpoint of its thermal and mechanical properties, thermal shock resistance, chemical stability, and low radioactivation. Therefore, there have been many efforts to develop SiC based composites in various forms for use in advanced energy systems. In recent years, with the development of high yield preceramic precursors, the polymer infiltration and pyrolysis (PIP) method has aroused interest for the fabrication of ceramic based materials, for various applications ranging from disc brakes to nuclear reactor fuels. The pyrolysis of preceramic polymers allow new types of ceramic materials to be processed at relatively low temperatures. The raw materials are element-organic polymers whose composition and architecture can be tailored and varied. The primary focus of this study is to use a pyrolysis based process to fabricate a host of novel silicon carbide-metal carbide or oxide composites, and to synthesize new materials based on mixed-metal silicocarbides that cannot be processed using conventional techniques. Allylhydridopolycarbosilane (AHPCS), which is an organometal polymer, was used as the precursor for silicon carbide. Inert gas pyrolysis of AHPCS produces near-stoichiometric amorphous silicon carbide (a-SiC) at 900--1150 °C. Results indicated that this processing technique can be effectively used to fabricate various silicon carbide composites with UC or UO2 as the nuclear component.

Solar energy for electricity and fuels.

PubMed

Inganäs, Olle; Sundström, Villy

2016-01-01

Solar energy conversion into electricity by photovoltaic modules is now a mature technology. We discuss the need for materials and device developments using conventional silicon and other materials, pointing to the need to use scalable materials and to reduce the energy payback time. Storage of solar energy can be achieved using the energy of light to produce a fuel. We discuss how this can be achieved in a direct process mimicking the photosynthetic processes, using synthetic organic, inorganic, or hybrid materials for light collection and catalysis. We also briefly discuss challenges and needs for large-scale implementation of direct solar fuel technologies.

Process Demonstration For Lunar In Situ Resource Utilization-Molten Oxide Electrolysis (MSFC Independent Research and Development Project No. 5-81)

NASA Technical Reports Server (NTRS)

Curreri, P. A.; Ethridge, E. C.; Hudson, S. B.; Miller, T. Y.; Grugel, R. N.; Sen, S.; Sadoway, D. R.

2006-01-01

The purpose of this Focus Area Independent Research and Development project was to conduct, at Marshall Space Flight Center, an experimental demonstration of the processing of simulated lunar resources by the molten oxide electrolysis process to produce oxygen and metal. In essence, the vision was to develop two key technologies, the first to produce materials (oxygen, metals, and silicon) from lunar resources and the second to produce energy by photocell production on the Moon using these materials. Together, these two technologies have the potential to greatly reduce the costs and risks of NASA s human exploration program. Further, it is believed that these technologies are the key first step toward harvesting abundant materials and energy independent of Earth s resources.

Building a Successful Technology Cluster

EPA Science Inventory

Silicon Valley is the iconic cluster—a dense regional network of companies, universities, research institutions, and other stakeholders involved in a single industry. Many regions have sought to replicate the success of Silicon Valley, which has produced technological innov...

Specific energy yield comparison between crystalline silicon and amorphous silicon based PV modules

NASA Astrophysics Data System (ADS)

Ferenczi, Toby; Stern, Omar; Hartung, Marianne; Mueggenburg, Eike; Lynass, Mark; Bernal, Eva; Mayer, Oliver; Zettl, Marcus

2009-08-01

As emerging thin-film PV technologies continue to penetrate the market and the number of utility scale installations substantially increase, detailed understanding of the performance of the various PV technologies becomes more important. An accurate database for each technology is essential for precise project planning, energy yield prediction and project financing. However recent publications showed that it is very difficult to get accurate and reliable performance data of theses technologies. This paper evaluates previously reported claims the amorphous silicon based PV modules have a higher annual energy yield compared to crystalline silicon modules relative to their rated performance. In order to acquire a detailed understanding of this effect, outdoor module tests were performed at GE Global Research Center in Munich. In this study we examine closely two of the five reported factors that contribute to enhanced energy yield of amorphous silicon modules. We find evidence to support each of these factors and evaluate their relative significance. We discuss aspects for improvement in how PV modules are sold and identify areas for further study further study.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Nanophotonic applications for silicon-on-insulator (SOI)

NASA Astrophysics Data System (ADS)

de la Houssaye, Paul R.; Russell, Stephen D.; Shimabukuro, Randy L.

2004-07-01

Silicon-on-insulator is a proven technology for very large scale integration of microelectronic devices. The technology also offers the potential for development of nanophotonic devices and the ability to interface such devices to the macroscopic world. This paper will report on fabrication techniques used to form nano-structured silicon wires on an insulating structure that is amenable to interfacing nanostructured sensors with high-performance microelectronic circuitry for practical implementation. Nanostructures formed on silicon-on-sapphire can also exploit the transparent substrate for novel device geometries. This research harnesses the unique properties of a high-quality single crystal film of silicon on sapphire and uses the film thickness as one of the confinement dimensions. Lateral arrays of silicon nanowires were fabricated in the thin (5 to 20 nm) silicon layer and studied. This technique offers simplified contact to individual wires and provides wire surfaces that are more readily accessible for controlled alteration and device designs.

Modeling chemical vapor deposition of silicon dioxide in microreactors at atmospheric pressure

NASA Astrophysics Data System (ADS)

Konakov, S. A.; Krzhizhanovskaya, V. V.

2015-01-01

We developed a multiphysics mathematical model for simulation of silicon dioxide Chemical Vapor Deposition (CVD) from tetraethyl orthosilicate (TEOS) and oxygen mixture in a microreactor at atmospheric pressure. Microfluidics is a promising technology with numerous applications in chemical synthesis due to its high heat and mass transfer efficiency and well-controlled flow parameters. Experimental studies of CVD microreactor technology are slow and expensive. Analytical solution of the governing equations is impossible due to the complexity of intertwined non-linear physical and chemical processes. Computer simulation is the most effective tool for design and optimization of microreactors. Our computational fluid dynamics model employs mass, momentum and energy balance equations for a laminar transient flow of a chemically reacting gas mixture at low Reynolds number. Simulation results show the influence of microreactor configuration and process parameters on SiO2 deposition rate and uniformity. We simulated three microreactors with the central channel diameter of 5, 10, 20 micrometers, varying gas flow rate in the range of 5-100 microliters per hour and temperature in the range of 300-800 °C. For each microchannel diameter we found an optimal set of process parameters providing the best quality of deposited material. The model will be used for optimization of the microreactor configuration and technological parameters to facilitate the experimental stage of this research.

Analyzing Noise for the Muon Silicon Scanner

DOE Office of Scientific and Technical Information (OSTI.GOV)

Marchan, Miguelangel; Utes, Michael

2017-01-01

The development of a silicon muon tomography detector is a joint project between Fermilab and National Security Technologies, LLC. The goal of this detector is to detect nuclear materials better than technology in the past. Using silicon strip detectors and readout chips used by experiments at CERN we have been developing the detector. This summer we have been testing components of the detector and have been analyzing noise characteristics.

Price estimates for the production of wafers from silicon ingots

NASA Technical Reports Server (NTRS)

Mokashi, A. R.

1982-01-01

The status of the inside-diameter sawing, (ID), multiblade sawing (MBS), and fixed-abrasive slicing technique (FAST) processes are discussed with respect to the estimated price each process adds on to the price of the final photovoltaic module. The expected improvements in each process, based on the knowledge of the current level of technology, are projected for the next two to five years and the expected add-on prices in 1983 and 1986 are estimated.

Silicon web process development. [for low cost solar cells

NASA Technical Reports Server (NTRS)

Duncan, C. S.; Hopkins, R. H.; Seidensticker, R. G.; Mchugh, J. P.; Hill, F. E.; Heimlich, M. E.; Driggers, J. M.

1979-01-01

Silicon dendritic web, a single crystal ribbon shaped during growth by crystallographic forces and surface tension (rather than dies), is a highly promising base material for efficient low cost solar cells. The form of the product smooth, flexible strips 100 to 200 microns thick, conserves expensive silicon and facilitates automation of crystal growth and the subsequent manufacturing of solar cells. These characteristics, coupled with the highest demonstrated ribbon solar cell efficiency-15.5%-make silicon web a leading candidate to achieve, or better, the 1986 Low Cost Solar Array (LSA) Project cost objective of 50 cents per peak watt of photovoltaic output power. The main objective of the Web Program, technology development to significantly increase web output rate, and to show the feasibility for simultaneous melt replenishment and growth, have largely been accomplished. Recently, web output rates of 23.6 sq cm/min, nearly three times the 8 sq cm/min maximum rate of a year ago, were achieved. Webs 4 cm wide or greater were grown on a number of occassions.

High-efficiency crystalline silicon technology development

NASA Technical Reports Server (NTRS)

Prince, M. B.

1984-01-01

The rationale for pursuing high efficiency crystalline silicon technology research is discussed. Photovoltaic energy systems are reviewed as to their cost effectiveness and their competitiveness with other energy systems. The parameters of energy system life are listed and briefly reviewed.

Department of Defense Advisory Group on Electron Devices. Special Technology Area Review on Microwave Packaging Technology. Appendix

DTIC Science & Technology

1993-02-01

sintered in hydrogen furnace at very high temperatures . Multiple furnace firing occurs until the binders are removed and part density is achieved "* Process...and base Low temperature co-fired ceramic - Metallized for shielding and grounding - Low resistance thick-film metallization - High thermal resistance...ESPECIALLY LOW TEMPERATURE COFIRED CERAMIC CERAMICS HIGH THERMAL CONDUCTIVITY,MATCHED GaAS AND SILICON SUBSTRATE MATERIALS I I,1Z#A,17Mr1 J, TI

Experimental and theoretical rationalization of the growth mechanism of silicon quantum dots in non-stoichiometric SiN x : role of chlorine in plasma enhanced chemical vapour deposition.

PubMed

Mon-Pérez, E; Salazar, J; Ramos, E; Salazar, J Santoyo; Suárez, A López; Dutt, A; Santana, G; Monroy, B Marel

2016-11-11

Silicon quantum dots (Si-QDs) embedded in an insulator matrix are important from a technological and application point of view. Thus, being able to synthesize them in situ during the matrix growth process is technologically advantageous. The use of SiH 2 Cl 2 as the silicon precursor in the plasma enhanced chemical vapour deposition (PECVD) process allows us to obtain Si-QDs without post-thermal annealing. Foremost in this work, is a theoretical rationalization of the mechanism responsible for Si-QD generation in a film including an analysis of the energy released by the extraction of HCl and the insertion of silylene species into the terminal surface bonds. From the results obtained using density functional theory (DFT), we propose an explanation of the mechanism responsible for the formation of Si-QDs in non-stoichiometric SiN x starting from chlorinated precursors in a PECVD system. Micrograph images obtained through transmission electron microscopy confirmed the presence of Si-QDs, even in nitrogen-rich (N-rich) samples. The film stoichiometry was controlled by varying the growth parameters, in particular the NH 3 /SiH 2 Cl 2 ratio and hydrogen dilution. Experimental and theoretical results together show that using a PECVD system, along with chlorinated precursors it is possible to obtain Si-QDs at a low substrate temperature without annealing treatment. The optical property studies carried out in the present work highlight the prospects of these thin films for down shifting and as an antireflection coating in silicon solar cells.

Development of advanced Czochralski growth process to produce low cost 150 kg silicon ingots from a single crucible for technology readiness

NASA Technical Reports Server (NTRS)

1980-01-01

The design and development of an advanced Czochralski crystal grower are described. Several exhaust gas analysis system equipment specifications studied are discussed. Process control requirements were defined and design work began on the melt temperature, melt level, and continuous diameter control. Sensor development included assembly and testing of a bench prototype of a diameter scanner system.

Industrial Applications of Graphite Fluoride Fibers

NASA Technical Reports Server (NTRS)

Hung, Ching-Cheh; Kucera, Donald

1991-01-01

Based on fluorination technology developed during 1934 to 1959, and the fiber technology developed during the 1970s, a new process was developed to produce graphite fluoride fibers. In the process, pitch based graphitized carbon fibers are at first intercalated and deintercalated several times by bromine and iodine, followed by several cycles of nitrogen heating and fluorination at 350 to 370 C. Electrical, mechanical, and thermal properties of this fiber depend on the fluorination process and the fluorine content of the graphite fluoride product. However, these properties are between those of graphite and those of PTFE (Teflon). Therefore, it is considered to be a semiplastic. The physical properties suggest that this new material may have many new and unexplored applications. For example, it can be a thermally conductive electrical insulator. Its coefficient of thermal expansion (CTE) can be adjusted to match that of silicon, and therefore, it can be a heat sinking printed circuit board which is CTE compatible with silicon. Using these fibers in printed circuit boards may provide improved electrical performance and reliability of the electronics on the board over existing designs. Also, since it releases fluorine at 300 C or higher, it can be used as a material to store fluorine and to conduct fluorination. This application may simplify the fluorination process and reduce the risk of handling fluorine.

Extracting Silicon From Sodium-Process Products

NASA Technical Reports Server (NTRS)

Kapur, V.; Sanjurjo, A.; Sancier, K. M.; Nanis, L.

1982-01-01

New acid leaching process purifies silicon produced in reaction between silicon fluoride and sodium. Concentration of sodium fluoride and other impurities and byproducts remaining in silicon are within acceptable ranges for semi-conductor devices. Leaching process makes sodium reduction process more attractive for making large quantities of silicon for solar cells.

Nonclassical light sources for silicon photonics

NASA Astrophysics Data System (ADS)

Bajoni, Daniele; Galli, Matteo

2017-09-01

Quantum photonics has recently attracted a lot of attention for its disruptive potential in emerging technologies like quantum cryptography, quantum communication and quantum computing. Driven by the impressive development in nanofabrication technologies and nanoscale engineering, silicon photonics has rapidly become the platform of choice for on-chip integration of high performing photonic devices, now extending their functionalities towards quantum-based applications. Focusing on quantum Information Technology (qIT) as a key application area, we review recent progress in integrated silicon-based sources of nonclassical states of light. We assess the state of the art in this growing field and highlight the challenges that need to be overcome to make quantum photonics a reliable and widespread technology.

Experimental verification of layout physical verification of silicon photonics

NASA Astrophysics Data System (ADS)

El Shamy, Raghi S.; Swillam, Mohamed A.

2018-02-01

Silicon photonics have been approved as one of the best platforms for dense integration of photonic integrated circuits (PICs) due to the high refractive index contrast among its materials. Silicon on insulator (SOI) is a widespread photonics technology, which support a variety of devices for lots of applications. As the photonics market is growing, the number of components in the PICs increases which increase the need for an automated physical verification (PV) process. This PV process will assure reliable fabrication of the PICs as it will check both the manufacturability and the reliability of the circuit. However, PV process is challenging in the case of PICs as it requires running an exhaustive electromagnetic (EM) simulations. Our group have recently proposed an empirical closed form models for the directional coupler and the waveguide bends based on the SOI technology. The models have shown a very good agreement with both finite element method (FEM) and finite difference time domain (FDTD) solvers. These models save the huge time of the 3D EM simulations and can be easily included in any electronic design automation (EDA) flow as the equations parameters can be easily extracted from the layout. In this paper we present experimental verification for our previously proposed models. SOI directional couplers with different dimensions have been fabricated using electron beam lithography and measured. The results from the measurements of the fabricate devices have been compared to the derived models and show a very good agreement. Also the matching can reach 100% by calibrating certain parameter in the model.

Integrating silicon photonic interconnects with CMOS: Fabrication to architecture

NASA Astrophysics Data System (ADS)

Sherwood, Nicholas Ramsey

While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

Roadmap on silicon photonics

NASA Astrophysics Data System (ADS)

Thomson, David; Zilkie, Aaron; Bowers, John E.; Komljenovic, Tin; Reed, Graham T.; Vivien, Laurent; Marris-Morini, Delphine; Cassan, Eric; Virot, Léopold; Fédéli, Jean-Marc; Hartmann, Jean-Michel; Schmid, Jens H.; Xu, Dan-Xia; Boeuf, Frédéric; O'Brien, Peter; Mashanovich, Goran Z.; Nedeljkovic, M.

2016-07-01

Silicon photonics research can be dated back to the 1980s. However, the previous decade has witnessed an explosive growth in the field. Silicon photonics is a disruptive technology that is poised to revolutionize a number of application areas, for example, data centers, high-performance computing and sensing. The key driving force behind silicon photonics is the ability to use CMOS-like fabrication resulting in high-volume production at low cost. This is a key enabling factor for bringing photonics to a range of technology areas where the costs of implementation using traditional photonic elements such as those used for the telecommunications industry would be prohibitive. Silicon does however have a number of shortcomings as a photonic material. In its basic form it is not an ideal material in which to produce light sources, optical modulators or photodetectors for example. A wealth of research effort from both academia and industry in recent years has fueled the demonstration of multiple solutions to these and other problems, and as time progresses new approaches are increasingly being conceived. It is clear that silicon photonics has a bright future. However, with a growing number of approaches available, what will the silicon photonic integrated circuit of the future look like? This roadmap on silicon photonics delves into the different technology and application areas of the field giving an insight into the state-of-the-art as well as current and future challenges faced by researchers worldwide. Contributions authored by experts from both industry and academia provide an overview and outlook for the silicon waveguide platform, optical sources, optical modulators, photodetectors, integration approaches, packaging, applications of silicon photonics and approaches required to satisfy applications at mid-infrared wavelengths. Advances in science and technology required to meet challenges faced by the field in each of these areas are also addressed together with predictions of where the field is destined to reach.

Nanoparticles and nanorods of silicon carbide from the residues of corn

NASA Astrophysics Data System (ADS)

Qadri, S. B.; Gorzkowski, E.; Rath, B. B.; Feng, J.; Qadri, S. N.; Kim, H.; Caldwell, J. D.; Imam, M. A.

2015-01-01

We have investigated the thermally induced transformation of various residues of the corn plant into nanoparticles and nanorods of different silicon carbide (SiC) polytypes. This has been accomplished by both microwave-induced and conventional furnace pyrolysis in excess of 1450 °C in an inert atmosphere. This simple process of producing nanoparticles of different polytypes of SiC from the corn plant opens a new method of utilizing agricultural waste to produce viable industrial products that are technologically important for nanoelectronics, molecular sensors, nanophotonics, biotechnology, and other mechanical applications. Using x-ray and Raman scattering characterization, we have demonstrated that the processed samples of corn husk, leaves, stalks, and cob consist of SiC nanostructures of the 2H, 3C, 4H, and 6H polytypes.

Advanced dendritic web growth development

NASA Technical Reports Server (NTRS)

Hopkins, R. H.

1985-01-01

A program to develop the technology of the silicon dendritic web ribbon growth process is examined. The effort is being concentrated on the area rate and quality requirements necessary to meet the JPL/DOE goals for terrestrial PV applications. Closed loop web growth system development and stress reduction for high area rate growth is considered.

Markets Hidden on Thoroughfares: The Social Construction of Economic Informality/Illegality in Beijing's Zhongguancun, China

ERIC Educational Resources Information Center

Chang, Ho-Jun

2009-01-01

This dissertation deals with the tense relation between the visibility of unauthorized economic practices and the invisibility of law in Zhongguancun (ZGC) Beijing, a Chinese information technology (IT) industry center dubbed "China's Silicon Valley." This dissertation ethnographically examines the double process of extra-legal/illegal…

High-efficiency UV/optical/NIR detectors for large aperture telescopes and UV explorer missions: development of and field observations with delta-doped arrays

NASA Astrophysics Data System (ADS)

Nikzad, Shouleh; Jewell, April D.; Hoenk, Michael E.; Jones, Todd J.; Hennessy, John; Goodsall, Tim; Carver, Alexander G.; Shapiro, Charles; Cheng, Samuel R.; Hamden, Erika T.; Kyne, Gillian; Martin, D. Christopher; Schiminovich, David; Scowen, Paul; France, Kevin; McCandliss, Stephan; Lupu, Roxana E.

2017-07-01

Exciting concepts are under development for flagship, probe class, explorer class, and suborbital class NASA missions in the ultraviolet/optical spectral range. These missions will depend on high-performance silicon detector arrays being delivered affordably and in high numbers. To that end, we have advanced delta-doping technology to high-throughput and high-yield wafer-scale processing, encompassing a multitude of state-of-the-art silicon-based detector formats and designs. We have embarked on a number of field observations, instrument integrations, and independent evaluations of delta-doped arrays. We present recent data and innovations from JPL's Advanced Detectors and Systems Program, including two-dimensional doping technology, JPL's end-to-end postfabrication processing of high-performance UV/optical/NIR arrays and advanced coatings for detectors. While this paper is primarily intended to provide an overview of past work, developments are identified and discussed throughout. Additionally, we present examples of past, in-progress, and planned observations and deployments of delta-doped arrays.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

NASA Technical Reports Server (NTRS)

Stahl, R. H.

1977-01-01

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

Fabrication of a 20.5-inch-diameter segmented silicon annular optic prototype for the ROMA program

NASA Astrophysics Data System (ADS)

Hassell, Frank R.; Groark, Frank M.

1995-10-01

Recent advancements in single crystal silicon material science and fabrication capabilities and very low absorption (VLA) multi-layer dielectric coating technology have led to the development of uncooled, large aperture, high power mirrors for high energy laser (HEL) systems. Based on this success, a segmented single-crystal silicon substrate concept has been selected as the baseline fabrication approach for uncooled 1.2 meter diameter resonator annular optics for the Alpha space based high energy laser. The objective of this Resonator Optics Materials Assessment (ROMA) task was to demonstrate all of the key fabrication processes required to fabricate the full sized annular optics for the Alpha space based high energy laser. This paper documents the fabrication of a half-scale annular optic prototype (AOP) of the Alpha laser rear cone.

Quantum Theory and the Silicon Revolution. Resources in Technology.

ERIC Educational Resources Information Center

Deal, Walter F., III

1995-01-01

This learning activity describes silicon as one of the most plentiful materials on earth, demonstrating how it supplies the building blocks for electronic devices such as transistors, integrated circuits, and microprocessors. It includes a design brief on control technology. (JOW)

Innovative and water based stripping approach for thick and bulk photoresists

NASA Astrophysics Data System (ADS)

Rudolph, Matthias; Schumann, Dirk; Thrun, Xaver; Esche, Silvio; Hohle, Christoph

2014-10-01

The usage of phase fluid based stripping agents to remove photoresists from silicon substrates was studied. Photoresists are required for many silicon based technologies such as MEMS patterning, 3D-Integration or frontend and backend of line semiconductor applications [1]. Although the use of resists is very common, their successful integration often depends on the ability to remove the resist after certain processing steps. On the one hand the resist is changing during subsequent process steps that can cause a thermally activated cross-linking which increases the stripping complexity. Resist removal is also challenging after the formation of a hard polymer surface layer during plasma or implant processes which is called skin or crust [2]. On the other hand the choice of stripping chemistry is often limited due to the presence of functional materials such as metals which can be damaged by aggressive stripping chemistries [3].

Crystalline-silicon reliability lessons for thin-film modules

NASA Technical Reports Server (NTRS)

Ross, R. G., Jr.

1985-01-01

The reliability of crystalline silicon modules has been brought to a high level with lifetimes approaching 20 years, and excellent industry credibility and user satisfaction. The transition from crystalline modules to thin film modules is comparable to the transition from discrete transistors to integrated circuits. New cell materials and monolithic structures will require new device processing techniques, but the package function and design will evolve to a lesser extent. Although there will be new encapsulants optimized to take advantage of the mechanical flexibility and low temperature processing features of thin films, the reliability and life degradation stresses and mechanisms will remain mostly unchanged. Key reliability technologies in common between crystalline and thin film modules include hot spot heating, galvanic and electrochemical corrosion, hail impact stresses, glass breakage, mechanical fatigue, photothermal degradation of encapsulants, operating temperature, moisture sorption, circuit design strategies, product safety issues, and the process required to achieve a reliable product from a laboratory prototype.

Surface-micromachined and high-aspect ratio electrostatic actuators for aeronautic and space applications: design and lifetime considerations

NASA Astrophysics Data System (ADS)

Vescovo, P.; Joseph, E.; Bourbon, G.; Le Moal, P.; Minotti, P.; Hibert, C.; Pont, G.

2003-09-01

This paper focuses on recent advances in the field of MEMS-based actuators and distributed microelectromechanical systems (MEMS). IC-processed actuators (e.g. actuators that are machined using integrated circuit batch processes) are expected to open a wide range of industrial applications on the near term. The most promising investigations deal with high-aspect ratio electric field driven microactuators suitable for use in numerous technical fields such as aeronautics and space industry. Because the silicon micromachining technology have the potential to integrate both mechanical components and control circuits within a single process, MEMS-based active control of microscopic and macroscopic structures appears to be one of the most promising challenges for the next decade. As a first step towards new generations of MEMS-based smart structures, recent investigations dealing with silicon mechanisms involving MEMS-based actuators are briefly discussed in this paper.

Silicon-sheet and thin-film cell and module technology potential: Issue study

NASA Technical Reports Server (NTRS)

Shimada, K.; Costogue, E. N.; Ferber, R. R.

1984-01-01

The development of high-efficiency low-cost crystalline silicon ribbon and thih-film solar cells for the energy national photovoltaics program was examined. The findings of an issue study conducted are presented. The collected data identified the status of the technology, future research needs, and problems experienced. The potentials of present research activities to meet the Federal/industry long-term technical goal of achieving 15 cents per kilowatt-hour levelized PV energy cost are assessed. Recommendations for future research needs related to crystalline silicon ribbon and thin-film technologies for flat-plate collectors are also included.

Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tiriolo, Raffaele; Rangnekar, Neel; Zhang, Han

A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservationmore » of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.« less

Adaptive optics high-resolution IR spectroscopy with silicon grisms and immersion gratings

NASA Astrophysics Data System (ADS)

Ge, Jian; McDavitt, Daniel L.; Chakraborty, Abhijit; Bernecker, John L.; Miller, Shane

2003-02-01

The breakthrough of silicon immersion grating technology at Penn State has the ability to revolutionize high-resolution infrared spectroscopy when it is coupled with adaptive optics at large ground-based telescopes. Fabrication of high quality silicon grism and immersion gratings up to 2 inches in dimension, less than 1% integrated scattered light, and diffraction-limited performance becomes a routine process thanks to newly developed techniques. Silicon immersion gratings with etched dimensions of ~ 4 inches are being developed at Penn State. These immersion gratings will be able to provide a diffraction-limited spectral resolution of R = 300,000 at 2.2 micron, or 130,000 at 4.6 micron. Prototype silicon grisms have been successfully used in initial scientific observations at the Lick 3m telescope with adaptive optics. Complete K band spectra of a total of 6 T Tauri and Ae/Be stars and their close companions at a spectral resolution of R ~ 3000 were obtained. This resolving power was achieved by using a silicon echelle grism with a 5 mm pupil diameter in an IR camera. These results represent the first scientific observations conducted by the high-resolution silicon grisms, and demonstrate the extremely high dispersing power of silicon-based gratings. New discoveries from this high spatial and spectral resolution IR spectroscopy will be reported. The future of silicon-based grating applications in ground-based AO IR instruments is promising. Silicon immersion gratings will make very high-resolution spectroscopy (R > 100,000) feasible with compact instruments for implementation on large telescopes. Silicon grisms will offer an efficient way to implement low-cost medium to high resolution IR spectroscopy (R ~ 1000-50000) through the conversion of existing cameras into spectrometers by locating a grism in the instrument's pupil location.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

PubMed

Hussain, Aftab M; Hussain, Muhammad M

2016-06-01

Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The development of silicon carbide-based power electronics devices

NASA Astrophysics Data System (ADS)

Hopkins, Richard H.; Perkins, John F.

1995-01-01

In 1989 Westinghouse created an internally funded initiative to develop silicon carbide materials and device technology for a variety of potential commercial and military applications. Westinghouse saw silicon carbide as having the potential for dual use. For space applications, size and weight reductions could be achieved, together with increased reliability. Terrestrially, uses in harsh-temperature environments would be enabled. Theoretically, the physical and electrical properties of silicon carbide were highly promising for high-power, high-temperature, radiation-hardened electronics. However, bulk material with the requisite electronic qualities was not available, and the methods needed to produce a silicon carbide wafer—to fabricate high-quality devices—and to transition these technologies into a commercial product were considered to be a high-risk investment. It was recognized that through a collaborative effort, the CCDS could provide scientific expertise in several areas, thus reducing this risk. These included modeling of structures, electrical contacts, dielectrics, and epitaxial growth. This collaboration has been very successful, with developed technologies being transferred to Westinghouse.

First fabrication of a silicon vertical JFET for power distribution in high energy physics applications

NASA Astrophysics Data System (ADS)

Fernández-Martínez, Pablo; Flores, D.; Hidalgo, S.; Quirion, D.; Durà, R.; Ullán, M.

2018-01-01

A new vertical JFET transistor has been recently developed at the IMB-CNM, taking advantage of a deep-trenched 3D technology to achieve vertical conduction and low switch-off voltage. The silicon V-JFET transistors were mainly conceived to work as rad-hard protection switches for the renewed HV powering scheme (HV-MUX) of the ATLAS upgraded tracker. This work presents the features of the first batch of V-JFETs produced at the IMB-CNM clean room, together with the results of a full pre-irradiation characterization of the fabricated prototypes. Details of the technological process are provided and the outcome quality is also evaluated with the aid of reverse engineering techniques. Concerning the electrical performance of the prototypes, promising results were obtained, already meeting most of the HV-MUX specifications, both at room and below-zerotemperatures.

Black silicon significantly enhances phosphorus diffusion gettering.

PubMed

Pasanen, Toni P; Laine, Hannu S; Vähänissi, Ville; Schön, Jonas; Savin, Hele

2018-01-31

Black silicon (b-Si) is currently being adopted by several fields of technology, and its potential has already been demonstrated in various applications. We show here that the increased surface area of b-Si, which has generally been considered as a drawback e.g. in applications that require efficient surface passivation, can be used as an advantage: it enhances gettering of deleterious metal impurities. We demonstrate experimentally that interstitial iron concentration in intentionally contaminated silicon wafers reduces from 1.7 × 10 13  cm -3 to less than 10 10  cm -3 via b-Si gettering coupled with phosphorus diffusion from a POCl 3 source. Simultaneously, the minority carrier lifetime increases from less than 2 μs of a contaminated wafer to more than 1.5 ms. A series of different low temperature anneals suggests segregation into the phosphorus-doped layer to be the main gettering mechanism, a notion which paves the way of adopting these results into predictive process simulators. This conclusion is supported by simulations which show that the b-Si needles are entirely heavily-doped with phosphorus after a typical POCl 3 diffusion process, promoting iron segregation. Potential benefits of enhanced gettering by b-Si include the possibility to use lower quality silicon in high-efficiency photovoltaic devices.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Microelectromechanical-System-Based Variable-Focus Liquid Lens for Capsule Endoscopes

NASA Astrophysics Data System (ADS)

Seo, Sang Won; Han, Seungoh; Seo, Jun Ho; Kim, Young Mok; Kang, Moon Sik; Min, Nam Ki; Choi, Woo Beom; Sung, Man Young

2009-05-01

A liquid lens based on the electrowetting phenomenon was designed to be cylindrical to minimize dead area. The lens was fabricated with microelectromechanical-system (MEMS) technology using silicon thin film and wafer bonding processes. A multiple dielectric layer comprising Teflon, silicon nitride, and thermal oxide was formed on the cylinder wall. With a change of 11 Vrms in the applied bias, the lens module, including the fabricated liquid lens, showed a focal length change of approximately 166 mm. A capsule endoscope was assembled, including the lens module, and was successfully used to take images of a pig colon at various focal lengths.

Novel method for measurement of transistor gate length using energy-filtered transmission electron microscopy

NASA Astrophysics Data System (ADS)

Lee, Sungho; Kim, Tae-Hoon; Kang, Jonghyuk; Yang, Cheol-Woong

2016-12-01

As the feature size of devices continues to decrease, transmission electron microscopy (TEM) is becoming indispensable for measuring the critical dimension (CD) of structures. Semiconductors consist primarily of silicon-based materials such as silicon, silicon dioxide, and silicon nitride, and the electrons transmitted through a plan-view TEM sample provide diverse information about various overlapped silicon-based materials. This information is exceedingly complex, which makes it difficult to clarify the boundary to be measured. Therefore, we propose a simple measurement method using energy-filtered TEM (EF-TEM). A precise and effective measurement condition was obtained by determining the maximum value of the integrated area ratio of the electron energy loss spectrum at the boundary to be measured. This method employs an adjustable slit allowing only electrons with a certain energy range to pass. EF-TEM imaging showed a sharp transition at the boundary when the energy-filter’s passband centre was set at 90 eV, with a slit width of 40 eV. This was the optimum condition for the CD measurement of silicon-based materials involving silicon nitride. Electron energy loss spectroscopy (EELS) and EF-TEM images were used to verify this method, which makes it possible to measure the transistor gate length in a dynamic random access memory manufactured using 35 nm process technology. This method can be adapted to measure the CD of other non-silicon-based materials using the EELS area ratio of the boundary materials.

Achieving thermography with a thermal security camera using uncooled amorphous silicon microbolometer image sensors

NASA Astrophysics Data System (ADS)

Wang, Yu-Wei; Tesdahl, Curtis; Owens, Jim; Dorn, David

2012-06-01

Advancements in uncooled microbolometer technology over the last several years have opened up many commercial applications which had been previously cost prohibitive. Thermal technology is no longer limited to the military and government market segments. One type of thermal sensor with low NETD which is available in the commercial market segment is the uncooled amorphous silicon (α-Si) microbolometer image sensor. Typical thermal security cameras focus on providing the best image quality by auto tonemaping (contrast enhancing) the image, which provides the best contrast depending on the temperature range of the scene. While this may provide enough information to detect objects and activities, there are further benefits of being able to estimate the actual object temperatures in a scene. This thermographic ability can provide functionality beyond typical security cameras by being able to monitor processes. Example applications of thermography[2] with thermal camera include: monitoring electrical circuits, industrial machinery, building thermal leaks, oil/gas pipelines, power substations, etc...[3][5] This paper discusses the methodology of estimating object temperatures by characterizing/calibrating different components inside a thermal camera utilizing an uncooled amorphous silicon microbolometer image sensor. Plots of system performance across camera operating temperatures will be shown.

Thin film GaP for solar cell application

NASA Astrophysics Data System (ADS)

Morozov, I. A.; Gudovskikh, A. S.; Kudryashov, D. A.; Nikitina, E. V.; Kleider, J.-P.; Myasoedov, A. V.; Levitskiy, V.

2016-08-01

A new approach to the silicon based heterostructures technology consisting of the growth of III-V compounds (GaP) on a silicon substrate by low-temperature plasma enhanced atomic layer deposition (PE-ALD) is proposed. The basic idea of the method is to use a time modulation of the growth process, i.e. time separated stages of atoms or precursors transport to the growing surface, migration over the surface, and crystal lattice relaxation for each monolayer. The GaP layers were grown on Si substrates by PE-ALD at 350°C with phosphine (PH3) and trimethylgallium (TMG) as sources of III and V atoms. Scanning and transmission electron microscopy demonstrate that the grown GaP films have homogeneous amorphous structure, smooth surface and a sharp GaP/Si interface. The GaP/Si heterostructures obtained by PE-ALD compare favourably to that conventionally grown by molecular beam epitaxy (MBE). Indeed, spectroscopic ellipsometry measurements indicate similar interband optical absorption while photoluminescence measurements indicate higher charge carrier effective lifetime. The better passivation properties of GaP layers grown by PE-ALD demonstrate a potential of this technology for new silicon based photovoltaic heterostructure

Affordable, Robust Ceramic Joining Technology (ARCJoinT) for High Temperature Applications

NASA Technical Reports Server (NTRS)

Singh, M.

1998-01-01

Ceramic joining is recognized as one of the enabling technologies for the successful utilization of silicon carbide-based monolithic ceramic and fiber reinforced composite components in a number of demanding and high temperature applications in aerospace and ground-based systems. An affordable, robust ceramic joining technology (ARCJoinT) for joining of silicon carbide-based ceramics and fiber reinforced composites has been developed. This technique is capable of producing joints with tailorable thickness and composition. A wide variety of silicon carbide-based ceramics and composites, in different shapes and sizes, have been joined using this technique. The room and high temperature mechanical properties and fractography of ceramic joints have been reported. In monolithic silicon carbide ceramics, these joints maintain their mechanical strength up to 1350 C in air. There is no change in the mechanical strength of joints in silicon carbide matrix composites up to 1200 C in air. In composites, simple butt joints yield only about 20% of the ultimate strength of the parent materials. This technology is suitable for the joining of large and complex shaped ceramic and composite components, and with certain modifications, can be applied to repair of ceramic components damaged in service.

Preparing the optics technology to observe the hot universe

NASA Astrophysics Data System (ADS)

Bavdaz, Marcos; Wille, Eric; Wallace, Kotska; Shortt, Brian; Fransen, Sebastiaan; Collon, Maximilien; Ackermann, Marcelo; Vacanti, Giuseppe; Guenther, Ramses; Haneveld, Jeroen; Riekerink, Mark Olde; van Baren, Coen; Kampf, Dirk; Zuknik, Karl-Heinz; Christensen, Finn; Della Monica Ferreira, Desiree; Jakobsen, Anders Clemen; Krumrey, Michael; Müller, Peter; Burwitz, Vadim; Pareschi, Giovanni; Ghigo, Mauro

2014-07-01

With the selection of "The hot and energetic Universe" as science theme for ESA's second large class mission (L2) in the Cosmic Vision programme, work is focusing on the technology preparation for an advanced X-ray observatory. The core enabling technology for the high performance mirror is the Silicon Pore Optics (SPO) [1 to 23], a modular X-ray optics technology, which utilises processes and equipment developed for the semiconductor industry. The paper provides an overview of the programmatic background, the status of SPO technology and gives an outline of the development roadmap and activities undertaken and planned by ESA on optics, coatings [24 to 30] and test facilities [31, 33].

Advancing MEMS Technology Usage through the MUMPS (Multi-User MEMS Processes) Program

NASA Technical Reports Server (NTRS)

Koester, D. A.; Markus, K. W.; Dhuler, V.; Mahadevan, R.; Cowen, A.

1995-01-01

In order to help provide access to advanced micro-electro-mechanical systems (MEMS) technologies and lower the barriers for both industry and academia, the Microelectronic Center of North Carolina (MCNC) and ARPA have developed a program which provides users with access to both MEMS processes and advanced electronic integration techniques. The four distinct aspects of this program, the multi-user MEMS processes (MUMP's), the consolidated micro-mechanical element library, smart MEMS, and the MEMS technology network are described in this paper. MUMP's is an ARPA-supported program created to provide inexpensive access to MEMS technology in a multi-user environment. It is both a proof-of-concept and educational tool that aids in the development of MEMS in the domestic community. MUMP's technologies currently include a 3-layer poly-silicon surface micromachining process and LIGA (lithography, electroforming, and injection molding) processes that provide reasonable design flexibility within set guidelines. The consolidated micromechanical element library (CaMEL) is a library of active and passive MEMS structures that can be downloaded by the MEMS community via the internet. Smart MEMS is the development of advanced electronics integration techniques for MEMS through the application of flip chip technology. The MEMS technology network (TechNet) is a menu of standard substrates and MEMS fabrication processes that can be purchased and combined to create unique process flows. TechNet provides the MEMS community greater flexibility and enhanced technology accessibility.

A silicon technology for millimeter-wave monolithic circuits

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-12-01

A silicon millimeter-wave integrated-circuit (SIMMWIC) technology that includes high-energy ion implantation and pulsed-laser annealing, secondary ion mass spectrometry (SIMS) profile diagnostics, and novel wafer thinning has been developed. This technology has been applied to a SIMMWIC single-pole single-throw (SPST) switch and to IMPATT and p-i-n diode fabrication schemes. Thus, the SIMMWIC technology is a proven base for monolithic millimeter-wave sources and control circuit applications.

Theoretical-Experimental Analysis of the Effects of Grain Boundaries on the Electrical Properties of SOI (Silicon-on-Insulator) MOSFETS.

DTIC Science & Technology

1983-11-01

work on recrystallization of polycrystalline silicon ( polysilicon ) films deposited on silicon-dioxide has demonstrated remarkable improvement in film...quality, and thus has identified another possibly viable 1SO technology for ICs. The polysilicon -on-S10 2 technology not only has the advantages alluded...and consequently higher areal device densities. Virtually all the research to date on polysilicon -on-SiO 2 has concentrated on the

Chemical vapor deposition and characterization of polysilanes polymer based thin films and their applications in compound semiconductors and silicon devices

NASA Astrophysics Data System (ADS)

Oulachgar, El Hassane

As the semiconductors industry is moving toward nanodevices, there is growing need to develop new materials and thin films deposition processes which could enable strict control of the atomic composition and structure of thin film materials in order to achieve precise control on their electrical and optical properties. The accurate control of thin film characteristics will become increasingly important as the miniaturization of semiconductor devices continue. There is no doubt that chemical synthesis of new materials and their self assembly will play a major role in the design and fabrication of next generation semiconductor devices. The objective of this work is to investigate the chemical vapor deposition (CVD) process of thin film using a polymeric precursor as a source material. This process offers many advantages including low deposition cost, hazard free working environment, and most importantly the ability to customize the polymer source material through polymer synthesis and polymer functionalization. The combination between polymer synthesis and CVD process will enable the design of new generation of complex thin film materials with a wide range of improved chemical, mechanical, electrical and optical properties which cannot be easily achieved through conventional CVD processes based on gases and small molecule precursors. In this thesis we mainly focused on polysilanes polymers and more specifically poly(dimethylsilanes). The interest in these polymers is motivated by their distinctive electronic and photonic properties which are attributed to the delocalization of the sigma-electron along the Si-Si backbone chain. These characteristics make polysilane polymers very promising in a broad range of applications as a dielectric, a semiconductor and a conductor. The polymer-based CVD process could be eventually extended to other polymer source materials such as polygermanes, as well as and a variety of other inorganic and hybrid organic-inorganic polymers. This work has demonstrated that a polysilane polymeric source can be used to deposit a wide range of thin film materials exhibiting similar properties with conventional ceramic materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC) silicon dioxide (SiO2) and silicon nitride (Si3N4). The strict control of the deposition process allows precise control of the electrical, optical and chemical properties of polymer-based thin films within a broad range. This work has also demonstrated for the first time that poly(dimethylsilmaes) polymers deposited by CVD can be used to effectively passivate both silicon and gallium arsenide MOS devices. This finding makes polymer-based thin films obtained by CVD very promising for the development of high-kappa dielectric materials for next generation high-mobility CMOS technology. Keywords. Thin films, Polymers, Vapor Phase Deposition, CVD, Nanodielectrics, Organosilanes, Polysilanes, GaAs Passivation, MOSFET, Silicon Oxynitride, Integrated Waveguide, Silicon Carbide, Compound Semiconductors.

The design, fabrication and characterization of fluidic membranes for micro-engines with the aim of frequency lowering

NASA Astrophysics Data System (ADS)

Chutani, R.; Formosa, F.; de Labachelerie, M.; Badel, A.; Lanzetta, F.

2016-12-01

This paper describes the design, microfabrication and linear dynamic characterization of low frequency thick membranes as a potential technological solution for resonant micro-engines, for which classical pistons cannot be used. The proposed structure is called a hybrid fluid-membrane and consists of two thin flexible membranes that encapsulate an incompressible fluid. Lower frequency structures, compared to geometrically equivalent single layer membranes, are thus obtained. Each flexible membrane is based on a composite structure which comprises a silicon planar logarithmic spiral spring embedded in a room temperature vulcanization silicone polymer. Thus, the stiffness and sealing features are dissociated for a better design control. The developed realization and assembly process is demonstrated at the wafer level. The process involves the anodic bonding of multiple stacks of silicon/glass structures, fluid filling and sealing. Various dimensions of hybrid fluid-membranes are successfully fabricated. Their dynamic characterization underlines the agreement between experimental and theoretical results. The results provide the opportunity for the design and fabrication of low frequency membranes to match the dynamics requirements of micro-engines.

Nanostructured silicon for thermoelectric

NASA Astrophysics Data System (ADS)

Stranz, A.; Kähler, J.; Waag, A.; Peiner, E.

2011-06-01

Thermoelectric modules convert thermal energy into electrical energy and vice versa. At present bismuth telluride is the most widely commercial used material for thermoelectric energy conversion. There are many applications where bismuth telluride modules are installed, mainly for refrigeration. However, bismuth telluride as material for energy generation in large scale has some disadvantages. Its availability is limited, it is hot stable at higher temperatures (>250°C) and manufacturing cost is relatively high. An alternative material for energy conversion in the future could be silicon. The technological processing of silicon is well advanced due to the rapid development of microelectronics in recent years. Silicon is largely available and environmentally friendly. The operating temperature of silicon thermoelectric generators can be much higher than of bismuth telluride. Today silicon is rarely used as a thermoelectric material because of its high thermal conductivity. In order to use silicon as an efficient thermoelectric material, it is necessary to reduce its thermal conductivity, while maintaining high electrical conductivity and high Seebeck coefficient. This can be done by nanostructuring into arrays of pillars. Fabrication of silicon pillars using ICP-cryogenic dry etching (Inductive Coupled Plasma) will be described. Their uniform height of the pillars allows simultaneous connecting of all pillars of an array. The pillars have diameters down to 180 nm and their height was selected between 1 micron and 10 microns. Measurement of electrical resistance of single silicon pillars will be presented which is done in a scanning electron microscope (SEM) equipped with nanomanipulators. Furthermore, measurement of thermal conductivity of single pillars with different diameters using the 3ω method will be shown.

[A micro-silicon multi-slit spectrophotometer based on MEMS technology].

PubMed

Hao, Peng; Wu, Yi-Hui; Zhang, Ping; Liu, Yong-Shun; Zhang, Ke; Li, Hai-Wen

2009-06-01

A new mini-spectrophotometer was developed by adopting micro-silicon slit and pixel segmentation technology, and this spectrophotometer used photoelectron diode array as the detector by the back-dividing-light way. At first, the effect of the spectral bandwidth on the tested absorbance linear correlation was analyzed. A theory for the design of spectrophotometer's slit was brought forward after discussing the relationships between spectrophotometer spectrum band width and pre-and post-slits width. Then, the integrative micro-silicon-slit, which features small volume, high precision, and thin thickness, was manufactured based on the MEMS technology. Finally, a test was carried on linear absorbance solution by this spectrophotometer. The final result showed that the correlation coefficients were larger than 0.999, which means that the new mini-spectrophotometer with micro-silicon slit pixel segmentation has an obvious linear correlation.

Polishing of silicon based advanced ceramics

NASA Astrophysics Data System (ADS)

Klocke, Fritz; Dambon, Olaf; Zunke, Richard; Waechter, D.

2009-05-01

Silicon based advanced ceramics show advantages in comparison to other materials due to their extreme hardness, wear and creep resistance, low density and low coefficient of thermal expansion. As a matter of course, machining requires high efforts. In order to reach demanded low roughness for optical or tribological applications a defect free surface is indispensable. In this paper, polishing of silicon nitride and silicon carbide is investigated. The objective is to elaborate scientific understanding of the process interactions. Based on this knowledge, the optimization of removal rate, surface quality and form accuracy can be realized. For this purpose, fundamental investigations of polishing silicon based ceramics are undertaken and evaluated. Former scientific publications discuss removal mechanisms and wear behavior, but the scientific insight is mainly based on investigations in grinding and lapping. The removal mechanisms in polishing are not fully understood due to complexity of interactions. The role of, e.g., process parameters, slurry and abrasives, and their influence on the output parameters is still uncertain. Extensive technological investigations demonstrate the influence of the polishing system and the machining parameters on the stability and the reproducibility. It is shown that the interactions between the advanced ceramics and the polishing systems is of great relevance. Depending on the kind of slurry and polishing agent the material removal mechanisms differ. The observed effects can be explained by dominating mechanical or chemo-mechanical removal mechanisms. Therefore, hypotheses to state adequate explanations are presented and validated by advanced metrology devices, such as SEM, AFM and TEM.

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-08-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

Current-voltage characteristics and increase in the quantum efficiency of three-terminal gate and avalanche-based silicon LEDs.

PubMed

Xu, Kaikai

2013-09-20

In this paper, the emission of visible light by a monolithically integrated silicon p-n junction under reverse-bias is discussed. The modulation of light intensity is achieved using an insulated-gate terminal on the surface of the p-n junction. By varying the gate voltage, the breakdown voltage of the p-n junction will be adjustable so that the reverse current I(sub) flowing through the p-n junction at a fixed reverse-bias voltage is changed. It is observed that the light, which is emitted from the defects located at the p-n junction, depends closely on the reverse current I(sub). In regard to the phenomenon of electroluminescence, the relationship between the optical emission power and the reverse current I(sub) is linear. On the other hand, it is observed that both the quantum efficiency and the power conversion efficiency are able to have obvious enhancement, although the reverse-bias of the p-n junction is reduced and the corresponding reverse-current is much lower. Moreover, the successful fabrication on monolithic silicon light source on the bulk silicon by means of standard silicon complementary metal-oxide-semiconductor process technology is presented.

CMOS-compatible photonic devices for single-photon generation

NASA Astrophysics Data System (ADS)

Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

2016-09-01

Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pradeepkumar, Aiswarya; Mishra, Neeraj; Kermany, Atieh Ranjbar

Epitaxial cubic silicon carbide on silicon is of high potential technological relevance for the integration of a wide range of applications and materials with silicon technologies, such as micro electro mechanical systems, wide-bandgap electronics, and graphene. The hetero-epitaxial system engenders mechanical stresses at least up to a GPa, pressures making it extremely challenging to maintain the integrity of the silicon carbide/silicon interface. In this work, we investigate the stability of said interface and we find that high temperature annealing leads to a loss of integrity. High–resolution transmission electron microscopy analysis shows a morphologically degraded SiC/Si interface, while mechanical stress measurementsmore » indicate considerable relaxation of the interfacial stress. From an electrical point of view, the diode behaviour of the initial p-Si/n-SiC junction is catastrophically lost due to considerable inter-diffusion of atoms and charges across the interface upon annealing. Temperature dependent transport measurements confirm a severe electrical shorting of the epitaxial silicon carbide to the underlying substrate, indicating vast predominance of the silicon carriers in lateral transport above 25 K. This finding has crucial consequences on the integration of epitaxial silicon carbide on silicon and its potential applications.« less

The MOS silicon gate technology and the first microprocessors

NASA Astrophysics Data System (ADS)

Faggin, F.

2015-12-01

Today we are so used to the enormous capabilities of microelectronics that it is hard to imagine what it might have been like in the early Sixties and Seventies when much of the technology we use today was being developed. This paper will first present a brief history of microelectronics and computers, taking us to the threshold of the inventions of the MOS silicon gate technology and the microprocessor. These two creations provided the basic technology that would allow only a few years later to merge microelectronics and computers into the first commercial monolithic computer. By the late Seventies, the first monolithic computer weighting less than one gram, occupying a volume of less than one cubic centimeter, dissipating less than one Watt, and selling for less than ten dollars, could perform more information processing than the UNIVAC I, the first commercial electronic computer introduced in 1951, made with 5200 vacuum tubes, dissipating 125kW, weighting 13 metric tons, occupying a room larger than 35m2, and selling for more than one million dollars per unit. The first-person story of the SGT and the early microprocessors will be told by the Italian-born physicist who led both projects.

Technological Innovation of Thin-Film Transistors: Technology Development, History, and Future

NASA Astrophysics Data System (ADS)

Yamamoto, Yoshitaka

2012-06-01

The scale of the liquid crystal display industry has expanded rapidly, driven by technological innovations for thin-film transistors (TFTs). The TFT technology, which started from amorphous silicon (a-Si), has produced large TVs, and low-temperature polycrystalline silicon (poly-Si) has become a core technology for small displays, such as mobile phones. Recently, various TFT technological seeds have been realized, indicating that new information appliances that match new lifestyles and information infrastructures will be available in the near future. In this article, I review the history of TFT technology and discuss the future of TFT technological development from the technological innovation viewpoint.

Microsystems Research in Japan

DTIC Science & Technology

2003-09-01

microsystems applications, like microfluidic systems, will require more than planar lithography -based fabrication processes. The committee was impressed by the...United States focused on exploiting silicon planar lithography as the core technology for microstructure fabrication, whereas Japan explored a wide...including LIGA and its extensions, micro-stereolithography, and e-beam lithography . The range of materials seen in Japan was broader than in the

Economic analysis of crystal growth in space

NASA Technical Reports Server (NTRS)

Ulrich, D. R.; Chung, A. M.; Yan, C. S.; Mccreight, L. R.

1972-01-01

Many advanced electronic technologies and devices for the 1980's are based on sophisticated compound single crystals, i.e. ceramic oxides and compound semiconductors. Space processing of these electronic crystals with maximum perfection, purity, and size is suggested. No ecomonic or technical justification was found for the growth of silicon single crystals for solid state electronic devices in space.

Effects of Impurities and Processing on Silicon Solar Cells, Phase 3

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Davis, J. R.; Blais, P. D.; Rohatgi, A.; Campbell, R. B.; Rai-Choudhury, P.; Stapleton, R. E.; Mollenkopf, H. C.; Mccormick, J. R.

1979-01-01

Results of the 14th quarterly report are presented for a program designed to assess the effects of impurities, thermochemical processes and any impurity process interactions on the performance of terrestrial silicon solar cells. The Phase 3 effort encompasses: (1) potential interactions between impurities and thermochemical processing of silicon; (2) impurity-cell performance relationships in n-base silicon; (3) effect of contaminants introduced during silicon production, refining or crystal growth on cell performance; (4) effects of nonuniform impurity distributions in large area silicon wafers; and (5) a preliminary study of the permanence of impurity effects in silicon solar cells.

A preliminary 'test case' manufacturing sequence for 50 cents/watt solar photovoltaic modules in 1986

NASA Technical Reports Server (NTRS)

Bickler, D. B.

1979-01-01

The paper describes a 'test case' manufacturing process sequence for solar photovoltaic modules which will cost 50 cents/watt in 1986. The process, which starts with the purification of silicon grown into 75-mm-wide thin ribbons, is discussed, and the plant layout is depicted; each department is sized to produce 250 MW of modules/per year. The cost of this process sequence is compared to present technology at various companies showing considerable spread for each process; data are tabulated in a composite state-of-the-art cell processing cost summary for these processes.

Low cost solar array project. Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

NASA Technical Reports Server (NTRS)

1980-01-01

Technical activities are reported in the design of process, facilities, and equipment for producing silicon at a rate and price comensurate with production goals for low cost solar cell modules. The silane-silicone process has potential for providing high purity poly-silicon on a commercial scale at a price of fourteen dollars per kilogram by 1986, (1980 dollars). Commercial process, economic analysis, process support research and development, and quality control are discussed.

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

PubMed Central

Jeong, Gyu-Seob

2017-01-01

The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies. PMID:28841154

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

PubMed

Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

2017-08-25

The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

REVIEW ARTICLE: How will physics be involved in silicon microelectronics

NASA Astrophysics Data System (ADS)

Kamarinos, Georges; Felix, Pierre

1996-03-01

By the year 2000 electronics will probably be the basis of the largest industry in the world. Silicon microelectronics will continue to keep a dominant place covering 99% of the `semiconductor market'. The aim of this review article is to indicate for the next decade the domains in which research work in `physics' is needed for a technological advance towards increasing speed, complexity and density of silicon ultra large scale integration (ULSI) integrated circuits (ICs). By `physics' we mean here not only condensed matter physics but also the basic physical chemistry and thermodynamics. The review begins with a brief and general introduction in which we elucidate the current state of the art and the trends in silicon microelectronics. Afterwards we examine the involvement of physics in silicon microelectronics in the two main sections. The first section concerns the processes of fabrication of ICs: lithography, oxidation, diffusion, chemical and physical vapour deposition, rapid thermal processing, etching, interconnections, ultra-clean processing and microcontamination. The second section concerns the electrical operation of the ULSI devices. It defines the integration scales and points out the importance of the intermediate scale of integration which is the scale of the next generation of ICs. The emergence of cryomicroelectronics is also reviewed and an extended paragraph is dedicated to the problem of reliability and ageing of devices and ICs: hot carrier degradation, interdevice coupling and noise are considered. It is shown, during our analysis, that the next generation of silicon ICs needs mainly: (i) `scientific' fabrication and (ii) microscopic modelling and simulation of the electrical characteristics of the scaled down devices. To attain the above objectives a return to the `first principles' of physics as well as a recourse to nonlinear and non-equilibrium thermodynamics are mandatory. In the references we list numerous review papers and references of specialized colloquia proceedings so that a more detailed survey of the subject is possible for the reader.

Silicon nanoparticles: applications in cell biology and medicine

PubMed Central

O’Farrell, Norah; Houlton, Andrew; Horrocks, Benjamin R

2006-01-01

In this review, we describe the synthesis, physical properties, surface functionalization, and biological applications of silicon nanoparticles (also known as quantum dots). We compare them against current technologies, such as fluorescent organic dyes and heavy metal chalcogenide-based quantum dots. In particular, we examine the many different methods that can be used to both create and modify these nanoparticles and the advantages they may have over current technologies that have stimulated research into designing silicon nanoparticles for in vitro and in vivo applications. PMID:17722279

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Rapid Surface Functionalization of Hydrogen-Terminated Silicon by Alkyl Silanols.

PubMed

Escorihuela, Jorge; Zuilhof, Han

2017-04-26

Surface functionalization of inorganic semiconductor substrates, particularly silicon, has focused attention toward many technologically important applications, involving photovoltaic energy, biosensing and catalysis. For such modification processes, oxide-free (H-terminated) silicon surfaces are highly required, and different chemical approaches have been described in the past decades. However, their reactivity is often poor, requiring long reaction times (2-18 h) or the use of UV light (10-30 min). Here, we report a simple and rapid surface functionalization for H-terminated Si(111) surfaces using alkyl silanols. This catalyst-free surface reaction is fast (15 min at room temperature) and can be accelerated with UV light irradiation, reducing the reaction time to 1-2 min. This grafting procedure leads to densely packed organic monolayers that are hydrolytically stable (even up to 30 days at pH 3 or 11) and can display excellent antifouling behavior against a range of organic polymers.

Rapid Surface Functionalization of Hydrogen-Terminated Silicon by Alkyl Silanols

PubMed Central

2017-01-01

Surface functionalization of inorganic semiconductor substrates, particularly silicon, has focused attention toward many technologically important applications, involving photovoltaic energy, biosensing and catalysis. For such modification processes, oxide-free (H-terminated) silicon surfaces are highly required, and different chemical approaches have been described in the past decades. However, their reactivity is often poor, requiring long reaction times (2–18 h) or the use of UV light (10–30 min). Here, we report a simple and rapid surface functionalization for H-terminated Si(111) surfaces using alkyl silanols. This catalyst-free surface reaction is fast (15 min at room temperature) and can be accelerated with UV light irradiation, reducing the reaction time to 1–2 min. This grafting procedure leads to densely packed organic monolayers that are hydrolytically stable (even up to 30 days at pH 3 or 11) and can display excellent antifouling behavior against a range of organic polymers. PMID:28409624

Micromachined pressure sensors: Review and recent developments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Eaton, W.P.; Smith, J.H.

1997-03-01

Since the discovery of piezoresistivity in silicon in the mid 1950s, silicon-based pressure sensors have been widely produced. Micromachining technology has greatly benefited from the success of the integrated circuits industry, burrowing materials, processes, and toolsets. Because of this, microelectromechanical systems (MEMS) are now poised to capture large segments of existing sensor markets and to catalyze the development of new markets. Given the emerging importance of MEMS, it is instructive to review the history of micromachined pressure sensors, and to examine new developments in the field. Pressure sensors will be the focus of this paper, starting from metal diaphragm sensorsmore » with bonded silicon strain gauges, and moving to present developments of surface-micromachined, optical, resonant, and smart pressure sensors. Considerations for diaphragm design will be discussed in detail, as well as additional considerations for capacitive and piezoresistive devices.« less

Short-pulse laser interactions with disordered materials and liquids

DOE Office of Scientific and Technical Information (OSTI.GOV)

Phinney, L.M.; Goldman, C.H.; Longtin, J.P.

High-power, short-pulse lasers in the picosecond and subpicosecond range are utilized in an increasing number of technologies, including materials processing and diagnostics, micro-electronics and devices, and medicine. In these applications, the short-pulse radiation interacts with a wide range of media encompassing disordered materials and liquids. Examples of disordered materials include porous media, polymers, organic tissues, and amorphous forms of silicon, silicon nitride, and silicon dioxide. In order to accurately model, efficiently control, and optimize short-pulse, laser-material interactions, a thorough understanding of the energy transport mechanisms is necessary. Thus, fractals and percolation theory are used to analyze the anomalous diffusion regimemore » in random media. In liquids, the thermal aspects of saturable and multiphoton absorption are examined. Finally, a novel application of short-pulse laser radiation to reduce surface adhesion forces in microstructures through short-pulse laser-induced water desorption is presented.« less

Electrical leakage phenomenon in heteroepitaxial cubic silicon carbide on silicon

NASA Astrophysics Data System (ADS)

Pradeepkumar, Aiswarya; Zielinski, Marcin; Bosi, Matteo; Verzellesi, Giovanni; Gaskill, D. Kurt; Iacopi, Francesca

2018-06-01

Heteroepitaxial 3C-SiC films on silicon substrates are of technological interest as enablers to integrate the excellent electrical, electronic, mechanical, thermal, and epitaxial properties of bulk silicon carbide into well-established silicon technologies. One critical bottleneck of this integration is the establishment of a stable and reliable electronic junction at the heteroepitaxial interface of the n-type SiC with the silicon substrate. We have thus investigated in detail the electrical and transport properties of heteroepitaxial cubic silicon carbide films grown via different methods on low-doped and high-resistivity silicon substrates by using van der Pauw Hall and transfer length measurements as test vehicles. We have found that Si and C intermixing upon or after growth, particularly by the diffusion of carbon into the silicon matrix, creates extensive interstitial carbon traps and hampers the formation of a stable rectifying or insulating junction at the SiC/Si interface. Although a reliable p-n junction may not be realistic in the SiC/Si system, we can achieve, from a point of view of the electrical isolation of in-plane SiC structures, leakage suppression through the substrate by using a high-resistivity silicon substrate coupled with deep recess etching in between the SiC structures.

Advanced electrolyte/additive for lithium-ion batteries with silicon anode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Shuo; He, Meinan; Su, Chi-Cheung

State-of-the-art lithium-ion batteries (LIBs) are based on a lithium transition metal oxide cathode, a graphite anode and a nonaqueous carbonate electrolyte. To further increase the energy and power density of LIBs, silicon anodes have been intensively explored due to their high theoretical capacity, low operation potential, and low cost. However, the main challenges for Si anode are the large volume change during lithiation/delithiation process and the instability of the solid-electrolyte-interphase associated with this process. Recently, significant progress has been achieved via advanced material fabrication technologies and rational electrolyte design in terms of improving the Coulombic efficiency and capacity retention. Inmore » this paper, new developments in advanced electrolyte and additive for LIBs with Si anode were systematically reviewed, and perspectives over future research were suggested.« less

Summary of flat-plate solar array project documentation: Abstracts of published documents, 1975-1986, revision 1

NASA Technical Reports Server (NTRS)

Phillips, M. J.

1986-01-01

Abstracts of final reports, or the latest quarterly or annual, of the Flat-Plate Solar Array (FSA) Project Contractor of Jet Propulsion Laboratory (JPL) in-house activities are presented. Also presented is a list of proceedings and publications, by author, of work connected with the project. The aim of the program has been to stimulate the development of technology that will enable the private sector to manufacture and widely use photovoltaic systems for the generation of electricity in residential, commercial, industrial, and Government applications at a cost per watt that is competitive with utility generated power. FSA Project activities have included the sponsoring of research and development efforts in silicon refinement processes, advanced silicon sheet growth techniques, higher efficiency solar cells, solar cell/module fabrication processes, encapsulation, module/array engineering and reliability, and economic analyses.

Some practical considerations for economical back contact formation on high efficiency solar cells

NASA Technical Reports Server (NTRS)

Lesk, I. A.

1985-01-01

The back contact can detract from solar cell performance in a number of ways: high recombination, barrier, photovoltaic, minority carrier collection, resistance. These effects may act in a nonuniform fashion over the cell area, and complicate the analysis of photovoltaic performance aimed at a better understanding of the effects of device geometry and material and/or processing parameters. The back contact is tested by reproducing it on both sides of a substrate. The objective is to find a back contact which performs well as a back contact, can be applied cheaply to large area solar cells, fits well into a practical process sequence, does not introduce structural damage or undesirable impurities into the silicon substrate, is compatible with an effective front contact technology, permits low temperature solder contacting, adheres well to silicon, and is reliable.

Broadband enhancement of single photon emission and polarization dependent coupling in silicon nitride waveguides.

PubMed

Bisschop, Suzanne; Guille, Antoine; Van Thourhout, Dries; Hens, Zeger; Brainis, Edouard

2015-06-01

Single-photon (SP) sources are important for a number of optical quantum information processing applications. We study the possibility to integrate triggered solid-state SP emitters directly on a photonic chip. A major challenge consists in efficiently extracting their emission into a single guided mode. Using 3D finite-difference time-domain simulations, we investigate the SP emission from dipole-like nanometer-sized inclusions embedded into different silicon nitride (SiNx) photonic nanowire waveguide designs. We elucidate the effect of the geometry on the emission lifetime and the polarization of the emitted SP. The results show that highly efficient and polarized SP sources can be realized using suspended SiNx slot-waveguides. Combining this with the well-established CMOS-compatible processing technology, fully integrated and complex optical circuits for quantum optics experiments can be developed.

Advanced Flip Chips in Extreme Temperature Environments

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni

2010-01-01

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Study on the mechanism of color coordinate shift of LED package

NASA Astrophysics Data System (ADS)

Zhuang, Yunyi; Wang, Yong; Yang, Bobo; Li, Zhanguo; Yang, Lei; Zou, Jun

2017-07-01

In the paper, the influences of the chip, silicone and phosphors on the color coordinate shift of LED were studied. In the process of LED baking, it was found that the effect of the chip and silicone on the color coordinate drift is less than 3% through the analysis of each influencing factor. But the influence of the phosphors is large and accounted for 11.11% of the overall impact factors. Therefore, it is important to select the better green phosphors in thermal stability for the LED package and it has a guiding significance to the color coordinate of LED distribution. Project supported by the National Natural Science Foundation of China (No. 11474036), the Natural Science Foundation of Shanghai (No. 12ZR1430900), the Shanghai Institute of Technology Talents Scheme (No. YJ2014-04), the Shanghai Municipal Alliance Program (Nos. Lm201514, Lm201505, Lm201455), the Science and Technology Commission of Shanghai Municipality (CN) (No. 14500503300), the Shanghai Cooperative Project (No. ShanghaiCXY-2013-61), and the Jiashan County Technology Program (No. 20141316).

Study of shape evaluation for mask and silicon using large field of view

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Shinoda, Shinichi; Toyoda, Yasutaka

2010-09-01

We have developed a highly integrated method of mask and silicon metrology. The aim of this integration is evaluating the performance of the silicon corresponding to Hotspot on a mask. It can use the mask shape of a large field, besides. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. As an optimal solution to these issues, we provide a DFM solution that extracts 2-dimensional data for a more realistic and error-free simulation by reproducing accurately the contour of the actual mask, in addition to the simulation results from the mask data. On the other hand, there is roughness in the silicon form made from a mass-production line. Moreover, there is variation in the silicon form. For this reason, quantification of silicon form is important, in order to estimate the performance of a pattern. In order to quantify, the same form is equalized in two dimensions. And the method of evaluating based on the form is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is adaptable to following fields of mask quality management. •Discrimination of nuisance defects for fine pattern. •Determination of two-dimensional variability of pattern. •Verification of the performance of the pattern of various kinds of Hotspots. In this report, we introduce the experimental results and the application. We expect that the mask measurement and the shape control on mask production will make a huge contribution to mask yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the form of the same location of Design, Mask, and Silicon in such a viewpoint. And we report it about algorithm of the image composition in Large Field.

Progress in silicon carbide semiconductor technology

NASA Technical Reports Server (NTRS)

Powell, J. A.; Neudeck, P. G.; Matus, L. G.; Petit, J. B.

1992-01-01

Silicon carbide semiconductor technology has been advancing rapidly over the last several years. Advances have been made in boule growth, thin film growth, and device fabrication. This paper wi11 review reasons for the renewed interest in SiC, and will review recent developments in both crystal growth and device fabrication.

Silicon Integrated Optics: Fabrication and Characterization

NASA Astrophysics Data System (ADS)

Shearn, Michael Joseph, II

For decades, the microelectronics industry has sought integration and miniaturization as canonized in Moore's Law, and has continued doubling transistor density about every two years. However, further miniaturization of circuit elements is creating a bandwidth problem as chip interconnect wires shrink as well. A potential solution is the creation of an on-chip optical network with low delays that would be impossible to achieve using metal buses. However, this technology requires integrating optics with silicon microelectronics. The lack of efficient silicon optical sources has stymied efforts of an all-Si optical platform. Instead, the integration of efficient emitter materials, such as III-V semiconductors, with Si photonic structures is a low-cost, CMOS-compatible alternative platform. This thesis focuses on making and measuring on-chip photonic structures suitable for on-chip optical networking. The first part of the thesis assesses processing techniques of silicon and other semiconductor materials. Plasmas for etching and surface modification are described and used to make bonded, hybrid Si/III-V structures. Additionally, a novel masking method using gallium implantation into silicon for pattern definition is characterized. The second part of the thesis focuses on demonstrations of fabricated optical structures. A dense array of silicon devices is measured, consisting of fully-etched grating couplers, low-loss waveguides and ring resonators. Finally, recent progress in the Si/III-V hybrid system is discussed. Supermode control of devices is described, which uses changing Si waveguide width to control modal overlap with the gain material. Hybrid Si/III-V, Fabry-Perot evanescent lasers are demonstrated, utilizing a CMOS-compatible process suitable for integration on in electronics platforms. Future prospects and ultimate limits of Si devices and the hybrid Si/III-V system are also considered.

Design and development of SiGe based near-infrared photodetectors

NASA Astrophysics Data System (ADS)

Zeller, John W.; Puri, Yash R.; Sood, Ashok K.; McMahon, Shane; Efsthadiatis, Harry; Haldar, Pradeep; Dhar, Nibir K.

2014-10-01

Near-infrared (NIR) sensors operating at room temperatures are critical for a variety of commercial and military applications including detecting mortar fire and muzzle flashes. SiGe technology offers a low-cost alternative to conventional IR sensor technologies such as InGaAs, InSb, and HgCdTe for developing NIR micro-sensors that will not require any cooling and can operate with high bandwidths and comparatively low dark currents. Since Ge has a larger thermal expansion coefficient than Si, tensile strain may be incorporated into detector devices during the growth process, enabling an extended operating wavelength range above 1600 nm. SiGe based pin photodetectors have advantages of high stability, low noise, and high responsivity compared to metal-semiconductor-metal (MSM) devices. We have developed a process flow and are fabricating SiGe detector devices on 12" (300 mm) silicon wafers in order to take advantage of high throughput, large-area leading-edge silicon based CMOS technology that provides small feature sizes with associated device cost/density scaling advantages. The fabrication of the detector devices is facilitated by a two-step growth process incorporating initial low temperature growth of Ge/SiGe to form a thin strain-relaxed layer, followed by high temperature growth to deposit a thicker absorbing film, and subsequent high temperature anneal. This growth process is designed to effectively reduce dark current and enhance detector performance by reducing the number of defects and threading dislocations which form recombination centers during the growth process. Various characterization techniques have been employed to determine the properties of the epitaxially deposited Ge/SiGe layers, and the corresponding results are discussed.

High temperature latent heat thermal energy storage to augment solar thermal propulsion for microsatellites

NASA Astrophysics Data System (ADS)

Gilpin, Matthew R.

Solar thermal propulsion (STP) offers an unique combination of thrust and efficiency, providing greater total DeltaV capability than chemical propulsion systems without the order of magnitude increase in total mission duration associated with electric propulsion. Despite an over 50 year development history, no STP spacecraft has flown to-date as both perceived and actual complexity have overshadowed the potential performance benefit in relation to conventional technologies. The trend in solar thermal research over the past two decades has been towards simplification and miniaturization to overcome this complexity barrier in an effort finally mount an in-flight test. A review of micro-propulsion technologies recently conducted by the Air Force Research Laboratory (AFRL) has identified solar thermal propulsion as a promising configuration for microsatellite missions requiring a substantial Delta V and recommended further study. A STP system provides performance which cannot be matched by conventional propulsion technologies in the context of the proposed microsatellite ''inspector" requiring rapid delivery of greater than 1500 m/s DeltaV. With this mission profile as the target, the development of an effective STP architecture goes beyond incremental improvements and enables a new class of microsatellite missions. Here, it is proposed that a bi-modal solar thermal propulsion system on a microsatellite platform can provide a greater than 50% increase in Delta V vs. chemical systems while maintaining delivery times measured in days. The realization of a microsatellite scale bi-modal STP system requires the integration of multiple new technologies, and with the exception of high performance thermal energy storage, the long history of STP development has provided "ready" solutions. For the target bi-modal STP microsatellite, sensible heat thermal energy storage is insufficient and the development of high temperature latent heat thermal energy storage is an enabling technology for the platform. The use of silicon and boron as high temperature latent heat thermal energy storage materials has been in the background of solar thermal research for decades without a substantial investigation. This is despite a broad agreement in the literature about the performance benefits obtainable from a latent heat mechanisms which provides a high energy storage density and quasi-isothermal heat release at high temperature. In this work, an experimental approach was taken to uncover the practical concerns associated specifically with applying silicon as an energy storage material. A new solar furnace was built and characterized enabling the creation of molten silicon in the laboratory. These tests have demonstrated the basic feasibility of a molten silicon based thermal energy storage system and have highlighted asymmetric heat transfer as well as silicon expansion damage to be the primary engineering concerns for the technology. For cylindrical geometries, it has been shown that reduced fill factors can prevent damage to graphite walled silicon containers at the expense of decreased energy storage density. Concurrent with experimental testing, a cooling model was written using the "enthalpy method" to calculate the phase change process and predict test section performance. Despite a simplistic phase change model, and experimentally demonstrated complexities of the freezing process, results coincided with experimental data. It is thus possible to capture essential system behaviors of a latent heat thermal energy storage system even with low fidelity freezing kinetics modeling allowing the use of standard tools to obtain reasonable results. Finally, a technological road map is provided listing extant technological concerns and potential solutions. Improvements in container design and an increased understanding of convective coupling efficiency will ultimately enable both high temperature latent heat thermal energy storage and a new class of high performance bi-modal solar thermal spacecraft.

Potential of thin-film solar cell module technology

NASA Technical Reports Server (NTRS)

Shimada, K.; Ferber, R. R.; Costogue, E. N.

1985-01-01

During the past five years, thin-film cell technology has made remarkable progress as a potential alternative to crystalline silicon cell technology. The efficiency of a single-junction thin-film cell, which is the most promising for use in flat-plate modules, is now in the range of 11 percent with 1-sq cm cells consisting of amorphous silicon, CuInSe2 or CdTe materials. Cell efficiencies higher than 18 percent, suitable for 15 percent-efficient flat plate modules, would require a multijunction configuration such as the CdTe/CuInSe2 and tandem amorphous-silicon (a-Si) alloy cells. Assessments are presented of the technology status of thin-film-cell module research and the potential of achieving the higher efficiencies required for large-scale penetration into the photovoltaic (PV) energy market.

Process for forming retrograde profiles in silicon

DOEpatents

Weiner, K.H.; Sigmon, T.W.

1996-10-15

A process is disclosed for forming retrograde and oscillatory profiles in crystalline and polycrystalline silicon. The process consisting of introducing an n- or p-type dopant into the silicon, or using prior doped silicon, then exposing the silicon to multiple pulses of a high-intensity laser or other appropriate energy source that melts the silicon for short time duration. Depending on the number of laser pulses directed at the silicon, retrograde profiles with peak/surface dopant concentrations which vary are produced. The laser treatment can be performed in air or in vacuum, with the silicon at room temperature or heated to a selected temperature.

Characterization of nanometer-thick polycrystalline silicon with phonon-boundary scattering enhanced thermoelectric properties and its application in infrared sensors.

PubMed

Zhou, Huchuan; Kropelnicki, Piotr; Lee, Chengkuo

2015-01-14

Although significantly reducing the thermal conductivity of silicon nanowires has been reported, it remains a challenge to integrate silicon nanowires with structure materials and electrodes in the complementary metal-oxide-semiconductor (CMOS) process. In this paper, we investigated the thermal conductivity of nanometer-thick polycrystalline silicon (poly-Si) theoretically and experimentally. By leveraging the phonon-boundary scattering, the thermal conductivity of 52 nm thick poly-Si was measured as low as around 12 W mK(-1) which is only about 10% of the value of bulk single crystalline silicon. The ZT of n-doped and p-doped 52 nm thick poly-Si was measured as 0.067 and 0.024, respectively, while most previously reported data had values of about 0.02 and 0.01 for a poly-Si layer with a thickness of 0.5 μm and above. Thermopile infrared sensors comprising 128 pairs of thermocouples made of either n-doped or p-doped nanometer-thick poly-Si strips in a series connected by an aluminium (Al) metal interconnect layer are fabricated using microelectromechanical system (MEMS) technology. The measured vacuum specific detectivity (D*) of the n-doped and p-doped thermopile infrared (IR) sensors are 3.00 × 10(8) and 1.83 × 10(8) cm Hz(1/2) W(-1) for sensors of 52 nm thick poly-Si, and 5.75 × 10(7) and 3.95 × 10(7) cm Hz(1/2) W(-1) for sensors of 300 nm thick poly-Si, respectively. The outstanding thermoelectric properties indicate our approach is promising for diverse applications using ultrathin poly-Si technology.

Metalorganic chemical vapor deposition of gallium nitride on sacrificial substrates

NASA Astrophysics Data System (ADS)

Fenwick, William Edward

GaN-based light emitting diodes (LEDs) face several challenges if the technology is to continue to make a significant impact in general illumination, and on technology that has become known as solid state lighting (SSL). Two of the most pressing challenges for the continued penetration of SSL into traditional lighting applications are efficacy and total lumens from the device, and their related cost. The development of alternative substrate technologies is a promising avenue toward addressing both of these challenges, as both GaN-based device technology and the associated metalorganic chemical vapor deposition (MOCVD) technology are already relatively mature technologies with a well-understood cost base. Zinc oxide (ZnO) and silicon (Si) are among the most promising alternative substrates for GaN epitaxy. These substrates offer the ability to access both higher efficacy and lumen devices (ZnO) at a much reduced cost. This work focuses on the development of MOCVD growth processes to yield high quality GaN-based materials and devices on both ZnO and Si. ZnO is a promising substrate for growth of low defect-density GaN because of its similar lattice constant and thermal expansion coefficient. The major hurdles for GaN growth on ZnO are the instability of the substrate in a hydrogen atmosphere, which is typical of nitride growth conditions, and the inter-diffusion of zinc and oxygen from the substrate into the GaN-based epitaxial layer. A process was developed for the MOCVD growth of GaN and InxGa 1-xN on ZnO that attempted to address these issues. The structural and optical properties of these films were studied using various techniques. X-ray diffraction (XRD) showed the growth of wurtzite GaN on ZnO, and room-temperature photoluminescence (RT-PL) showed near band-edge luminescence from the GaN and InxGa1-xN layers. However, high zinc and oxygen concentrations due to interdiffusion near the ZnO substrate remained an issue; therefore, the diffusion of zinc and oxygen into the subsequent GaN layer was studied in more detail. Several approaches were investigated---for example, transition layers such as Al2O3 and Al xGa1-xN/GaN---to minimize diffusion of these impurities into the GaN layer. Silicon, due to its prevalence, is the most promising material for the development of an inexpensive, large-area substrate technology. The challenge in MOCVD growth of GaN on Si is the tensile strain induced by the lattice and thermal mismatch between GaN and Si and the formation of anti-phase boundaries. Typical approaches to solve these problems involve complicated and multiple buffer layer structures, which lead to relatively slow growth rates. In this work, a thin atomic layer deposition (ALD)-grown Al2O3 interlayer was employed to relieve strain and increase material quality while also simplifying the growth process. While some residual strain was still observed in the GaN material by XRD and PL, the use of this oxide interlayer leads to an improvement in thin film quality as seen by a reduction in both crack density (<1 mm-2) on ALD-Al2O3/Si) and screw dislocation density (from 3x109cm-2 on bare Si to 2x108cm-2 on ALD-Al 2O3/Si) in the GaN films. A side-by-side comparison of GaN-based multiple quantum well LEDs grown on sapphire and on Al2O3/Si shows similar performance characteristic for both device structures. A redshift in peak emission wavelength was also observed on silicon compared to sapphire, and this is attributed to higher indium content due to the slight tensile strain in the layers on silicon. IQE of the devices on silicon is ˜32% as measured by LT-PL, compared to ˜37% on sapphire, but this difference can be assigned to the difference in indium compositions. These results show a great promise toward an inexpensive, large-area, silicon-based substrate technology for MOCVD growth of the next generation of GaN-based optoelectronic devices for SSL and other applications.

Polysilicon planarization and plug recess etching in a decoupled plasma source chamber using two endpoint techniques

NASA Astrophysics Data System (ADS)

Kaplita, George A.; Schmitz, Stefan; Ranade, Rajiv; Mathad, Gangadhara S.

1999-09-01

The planarization and recessing of polysilicon to form a plug are processes of increasing importance in silicon IC fabrication. While this technology has been developed and applied to DRAM technology using Trench Storage Capacitors, the need for such processes in other IC applications (i.e. polysilicon studs) has increased. Both planarization and recess processes usually have stringent requirements on etch rate, recess uniformity, and selectivity to underlying films. Additionally, both processes generally must be isotropic, yet must not expand any seams that might be present in the polysilicon fill. These processes should also be insensitive to changes in exposed silicon area (pattern factor) on the wafer. A SF6 plasma process in a polysilicon DPS (Decoupled Plasma Source) reactor has demonstrated the capability of achieving the above process requirements for both planarization and recess etch. The SF6 process in the decoupled plasma source reactor exhibited less sensitivity to pattern factor than in other types of reactors. Control of these planarization and recess processes requires two endpoint systems to work sequentially in the same recipe: one for monitoring the endpoint when blanket polysilicon (100% Si loading) is being planarized and one for monitoring the recess depth while the plug is being recessed (less than 10% Si loading). The planarization process employs an optical emission endpoint system (OES). An interferometric endpoint system (IEP), capable of monitoring lateral interference, is used for determining the recess depth. The ability of using either or both systems is required to make these plug processes manufacturable. Measuring the recess depth resulting from the recess process can be difficult, costly and time- consuming. An Atomic Force Microscope (AFM) can greatly alleviate these problems and can serve as a critical tool in the development of recess processes.

Two different ways for waveguides and optoelectronics components on top of C-MOS

NASA Astrophysics Data System (ADS)

Fedeli, J. M.; Jeannot, S.; Kostrzewa, M.; Di Cioccio, L.; Jousseaume, V.; Orobtchouk, R.; Maury, P.; Zussy, M.

2006-02-01

While fabrication of photonic components at the wafer level is a long standing goal of integrated optics, new applications such as optical interconnects are introducing new challenges for waveguides and optoelectronic component fabrication. Indeed, global interconnects are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits could be an alternative. The critical points to perform an optical link on a chip are firstly the realization of compact passive optical distribution and secondly the report of optoelectronic components for the sources and detectors. This paper presents two different approaches for the integration of both waveguides and optoelectronic components. In a first "total bonding" approach, waveguides have been elaborated using classical "Silicon On Insulators" technology and then reported using molecular bonding on top off Si wafers. The S0I substrate was then chemically etched, after what InP dies were moleculary bonded on top of the waveguides. With this approach, optical components with low loses and a good equilibrium are demonsrated. Using molecular bonding, InP dies were reported with no degradation of the optoelectronic properties of the films. In a second approach, using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, basic optical components are demonstrated. This low temperature technology is compatible with a microelectronic Back End process, allowing an integration of the waveguides directly on top of CMOS circuits. InP dies can then be bonded on top of the waveguides.

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Mobil Solar Energy Corporation thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

Mobil Solar Energy Corporation manufactures photovoltaic modules based on its unique Edge-defined Film-fed Growth (EFG) process for producing octagon-shaped hollow polycrystalline silicon tubes. The octagons are cut by lasers into 100 mm x 100 mm wafers which are suitable for solar cell processing. This process avoids slicing, grinding and polishing operations which are wasteful of material and are typical of most other wafer production methods. EFG wafers are fabricated into solar cells and modules using processes that have been specially developed to allow scaling up to high throughput rates. The goals of the Photovoltaic Manufacturing Technology Initiative (PVMaT) program at Mobil Solar were to improve the EFG manufacturing line through technology advances that accelerate cost reduction in production and stimulate market growth for its product. The program was structured into three main tasks: to decrease silicon utilization by lowering wafer thickness from 400 to 200 (mu)m; to enhance laser cutting yields and throughput while improving the wafer strength; and to raise crystal growth productivity and yield. The technical problems faced and the advances made in the Mobil Solar PVMaT program are described. The author concludes with a presentation of the results of a detailed cost model for EFT module production. This model describes the accelerated reductions in manufacturing costs which are already in place and the future benefits anticipated to result from the technical achievements of the PVMaT program.

Fabrication of TiO2 nanostructures on porous silicon for thermoelectric application

NASA Astrophysics Data System (ADS)

Fahrizal, F. N.; Ahmad, M. K.; Ramli, N. M.; Ahmad, N.; Fakhriah, R.; Mohamad, F.; Nafarizal, N.; Soon, C. F.; Ameruddin, A. S.; Faridah, A. B.; Shimomura, M.; Murakami, K.

2017-09-01

Nowadays, technology is moving by leaps and bounds over the last several decades. This has created new opportunities and challenge in the research fields. In this study, the experiment is about to investigate the potential of Titanium Dioxide (TiO2) nanostructures that have been growth onto a layer of porous silicon (pSi) for their thermoelectric application. Basically, it is divided into two parts, which is the preparation of the porous silicon (pSi) substrate by electrochemical-etching process and the growth of the Titanium Dioxide (TiO2) nanostructures by hydrothermal method. This sample have been characterize by Field Emission Scanning Electron Microscopy (FESEM) to visualize the morphology of the TiO2 nanostructures area that formed onto the porous silicon (pSi) substrate. Besides, the sample is also used to visualize their cross-section images under the FESEM microscopy. Next, the sample is characterized by the X-Ray Diffraction (XRD) machine. The XRD machine is used to get the information about the chemical composition, crystallographic structure and physical properties of materials.

Fabrication of close-packed TES microcalorimeter arrays using superconducting molybdenum/gold transition-edge sensors

NASA Astrophysics Data System (ADS)

Finkbeiner, F. M.; Brekosky, R. P.; Chervenak, J. A.; Figueroa-Feliciano, E.; Li, M. J.; Lindeman, M. A.; Stahle, C. K.; Stahle, C. M.; Tralshawala, N.

2002-02-01

We present an overview of our efforts in fabricating Transition-Edge Sensor (TES) microcalorimeter arrays for use in astronomical x-ray spectroscopy. Two distinct types of array schemes are currently pursued: 5×5 single pixel TES array where each pixel is a TES microcalorimeter, and Position-Sensing TES (PoST) array. In the latter, a row of 7 or 15 thermally-linked absorber pixels is read out by two TES at its ends. Both schemes employ superconducting Mo/Au bilayers as the TES. The TES are placed on silicon nitride membranes for thermal isolation from the structural frame. The silicon nitride membranes are prepared by a Deep Reactive Ion Etch (DRIE) process into a silicon wafer. In order to achieve the concept of closely packed arrays without decreasing its structural and functional integrity, we have already developed the technology to fabricate arrays of cantilevered pixel-sized absorbers and slit membranes in silicon nitride films. Furthermore, we have started to investigate ultra-low resistance through-wafer micro-vias to bring the electrical contact out to the back of a wafer. .

Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

DTIC Science & Technology

2016-08-01

APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...mechanism on which to base on-chip nonlinear optical devices compatible with a rapidly growing silicon photonics toolbox.3–9 While silicon on insulator

Chemical Bonding Technology: Direct Investigation of Interfacial Bonds

NASA Technical Reports Server (NTRS)

Koenig, J. L.; Boerio, F. J.; Plueddemann, E. P.; Miller, J.; Willis, P. B.; Cuddihy, E. F.

1986-01-01

This is the third Flat-Plate Solar Array (FSA) Project document reporting on chemical bonding technology for terrestrial photovoltaic (PV) modules. The impetus for this work originated in the late 1970s when PV modules employing silicone encapsulation materials were undergoing delamination during outdoor exposure. At that time, manufacturers were not employing adhesion promoters and, hence, module interfaces in common with the silicone materials were only in physical contact and therefore easily prone to separation if, for example, water were to penetrate to the interfaces. Delamination with silicone materials virtually vanished when adhesion promoters, recommended by silicone manufacturers, were used. The activities related to the direct investigation of chemically bonded interfaces are described.

The challenge of screen printed Ag metallization on nano-scale poly-silicon passivated contacts for silicon solar cells

NASA Astrophysics Data System (ADS)

Jiang, Lin; Song, Lixin; Yan, Li; Becht, Gregory; Zhang, Yi; Hoerteis, Matthias

2017-08-01

Passivated contacts can be used to reduce metal-induced recombination for higher energy conversion efficiency for silicon solar cells, and are obtained increasing attentions by PV industries in recent years. The reported thicknesses of passivated contact layers are mostly within tens of nanometer range, and the corresponding metallization methods are realized mainly by plating/evaporation technology. This high cost metallization cannot compete with the screen printing technology, and may affect its market potential comparing with the presently dominant solar cell technology. Very few works have been reported on screen printing metallization on passivated contact solar cells. Hence, there is a rising demand to realize screen printing metallization technology on this topic. In this work, we investigate applying screen printing metallization pastes on poly-silicon passivated contacts. The critical challenge for us is to build low contact resistance that can be competitive to standard technology while restricting the paste penetrations within the thin nano-scale passivated contact layers. The contact resistivity of 1.1mohm-cm2 and the open circuit voltages > 660mV are achieved, and the most appropriate thickness range is estimated to be around 80 150nm.

Crystal structure of laser-induced subsurface modifications in Si

NASA Astrophysics Data System (ADS)

Verburg, P. C.; Smillie, L. A.; Römer, G. R. B. E.; Haberl, B.; Bradby, J. E.; Williams, J. S.; Huis in't Veld, A. J.

2015-08-01

Laser-induced subsurface modification of dielectric materials is a well-known technology. Applications include the production of optical components and selective etching. In addition to dielectric materials, the subsurface modification technology can be applied to silicon, by employing near to mid-infrared radiation. An application of subsurface modifications in silicon is laser-induced subsurface separation, which is a method to separate wafers into individual dies. Other applications for which proofs of concept exist are the formation of waveguides and resistivity tuning. However, limited knowledge is available about the crystal structure of subsurface modifications in silicon. In this work, we investigate the geometry and crystal structure of laser-induced subsurface modifications in monocrystalline silicon wafers. In addition to the generation of lattice defects, we found that transformations to amorphous silicon and Si -iii/Si -xii occur as a result of the laser irradiation.

The Athena optics

NASA Astrophysics Data System (ADS)

Bavdaz, Marcos; Wille, Eric; Shortt, Brian; Fransen, Sebastiaan; Collon, Maximilien; Vacanti, Giuseppe; Günther, Ramses; Yanson, Alexei; Vervest, Mark; Haneveld, Jeroen; van Baren, Coen; Zuknik, Karl-Heinz; Christensen, Finn; Krumrey, Michael; Burwitz, Vadim; Pareschi, Giovanni; Valsecchi, Giuseppe

2015-09-01

The Advanced Telescope for High ENergy Astrophysics (Athena) was selected in 2014 as the second large class mission (L2) of the ESA Cosmic Vision Science Programme within the Directorate of Science and Robotic Exploration. The mission development is proceeding via the implementation of the system studies and in parallel a comprehensive series of technology preparation activities. [1-3]. The core enabling technology for the high performance mirror is the Silicon Pore Optics (SPO), a modular X-ray optics technology, which utilises processes and equipment developed for the semiconductor industry [4-31]. This paper provides an overview of the programmatic background, the status of SPO technology and give an outline of the development roadmap and activities undertaken and planned by ESA.

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Black silicon solar cell: analysis optimization and evolution towards a thinner and flexible future.

PubMed

Roy, Arijit Bardhan; Dhar, Arup; Choudhuri, Mrinmoyee; Das, Sonali; Hossain, S Minhaz; Kundu, Avra

2016-07-29

Analysis and optimization of silicon nano-structured geometry (black silicon) for photovoltaic applications has been reported. It is seen that a unique class of geometry: micro-nanostructure has the potential to find a balance between the conflicting interests of reduced reflection for wide angles of incidence, reduced surface area enhancement due to the nano-structuring of the substrate and reduced material wastage due to the etching of the silicon substrate to realize the geometry itself. It is established that even optimally designed micro-nanostructures would not be useful for conventional wafer based approaches. The work presents computational studies on how such micro-nanostructures are more potent for future ultra-thin monocrystalline silicon absorbers. For such ultra-thin absorbers, the optimally designed micro-nanostructures provide additional advantages of advanced light management capabilities as it behaves as a lossy 2D photonic crystal making the physically thin absorber optically thick along with the ability to collect photo-generated carriers orthogonal to the direction of light (radial junction) for unified photon-electron harvesting. Most significantly, the work answers the key question on how thin the monocrystalline solar absorber should be so that optimum micro-nanostructure would be able to harness the incident photons ensuring proper collection so as to reach the well-known Shockley-Queisser limit of solar cells. Flexible ultra-thin monocrystalline silicon solar cells have been fabricated using nanosphere lithography and MacEtch technique along with a synergistic association of crystalline and amorphous silicon technologies to demonstrate its physical and technological flexibilities. The outcomes are relevant so that nanotechnology may be seamlessly integrated into the technology roadmap of monocrystalline silicon solar cells as the silicon thickness should be significantly reduced without compromising the efficiency within the next decade.

Process development for single-crystal silicon solar cells

NASA Astrophysics Data System (ADS)

Bohra, Mihir H.

Solar energy is a viable, rapidly growing and an important renewable alternative to other sources of energy generation because of its abundant supply and low manufacturing cost. Silicon still remains the major contributor for manufacturing solar cells accounting for 80% of the market share. Of this, single-crystal solar cells account for half of the share. Laboratory cells have demonstrated 25% efficiency; however, commercial cells have efficiencies of 16% - 20% resulting from a focus on implementation processes geared to rapid throughput and low cost, thereby reducing the energy pay-back time. An example would be the use of metal pastes which dissolve the dielectric during the firing process as opposed to lithographically defined contacts. With current trends of single-crystal silicon photovoltaic (PV) module prices down to 0.60/W, almost all other PV technologies are challenged to remain cost competitive. This presents a unique opportunity in revisiting the PV cell fabrication process and incorporating moderately more expensive IC process practices into PV manufacturing. While they may drive the cost toward a 1/W benchmark, there is substantial room to "experiment", leading to higher efficiencies which will help maintain the overall system cost. This work entails a turn-key process designed to provide a platform for rapid evaluation of novel materials and processes. A two-step lithographic process yielding a baseline 11% - 13% efficient cell is described. Results of three studies have shown improvements in solar cell output parameters due to the inclusion of a back-surface field implant, a higher emitter doping and also an additional RCA Clean.

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon

PubMed Central

Girel, Kseniya V.; Panarin, Andrei; Terekhov, Sergei N.

2018-01-01

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy. PMID:29883382

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon.

PubMed

Bandarenka, Hanna V; Girel, Kseniya V; Zavatski, Sergey A; Panarin, Andrei; Terekhov, Sergei N

2018-05-21

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy.

Thin film CdTe based neutron detectors with high thermal neutron efficiency and gamma rejection for security applications

NASA Astrophysics Data System (ADS)

Smith, L.; Murphy, J. W.; Kim, J.; Rozhdestvenskyy, S.; Mejia, I.; Park, H.; Allee, D. R.; Quevedo-Lopez, M.; Gnade, B.

2016-12-01

Solid-state neutron detectors offer an alternative to 3He based detectors, but suffer from limited neutron efficiencies that make their use in security applications impractical. Solid-state neutron detectors based on single crystal silicon also have relatively high gamma-ray efficiencies that lead to false positives. Thin film polycrystalline CdTe based detectors require less complex processing with significantly lower gamma-ray efficiencies. Advanced geometries can also be implemented to achieve high thermal neutron efficiencies competitive with silicon based technology. This study evaluates these strategies by simulation and experimentation and demonstrates an approach to achieve >10% intrinsic efficiency with <10-6 gamma-ray efficiency.

Dense arrays of millimeter-sized glass lenses fabricated at wafer-level.

PubMed

Albero, Jorge; Perrin, Stéphane; Bargiel, Sylwester; Passilly, Nicolas; Baranski, Maciej; Gauthier-Manuel, Ludovic; Bernard, Florent; Lullin, Justine; Froehly, Luc; Krauter, Johann; Osten, Wolfgang; Gorecki, Christophe

2015-05-04

This paper presents the study of a fabrication technique of lenses arrays based on the reflow of glass inside cylindrical silicon cavities. Lenses whose sizes are out of the microfabrication standards are considered. In particular, the case of high fill factor arrays is discussed in detail since the proximity between lenses generates undesired effects. These effects, not experienced when lenses are sufficiently separated so that they can be considered as single items, are corrected by properly designing the silicon cavities. Complete topographic as well as optical characterizations are reported. The compatibility of materials with Micro-Opto-Electromechanical Systems (MOEMS) integration processes makes this technology attractive for the miniaturization of inspection systems, especially those devoted to imaging.

Development of silicon carbide semiconductor devices for high temperature applications

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony; Petit, Jeremy B.

1991-01-01

The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

Ceramic technology for solar thermal receivers

NASA Technical Reports Server (NTRS)

Kudirka, A. A.; Smoak, R. H.

1981-01-01

The high-temperature capability, resistance to corrosive environments and non-strategic nature of ceramics have prompted applications in the solar thermal field whose advantages over metallic devices of comparable performance may begin to be assessed. It is shown by a survey of point-focusing receiver designs employing a variety of ceramic compositions and fabrication methods that the state-of-the-art in structural ceramics is not sufficiently advanced to fully realize the promised benefits of higher temperature capabilities at lower cost than metallic alternatives. The ceramics considered include alumina, berylia, magnesia, stabilized zirconia, fused silica, silicon nitride, silicon carbide, mullite and cordierite, processed by such methods as isostatic pressing, dry pressing, slip casting, extrusion, calendaring and injection molding.

Micromachined silicon cantilevers with integrated high-frequency magnetoimpedance sensors for simultaneous strain and magnetic field detection

NASA Astrophysics Data System (ADS)

Buettel, G.; Joppich, J.; Hartmann, U.

2017-12-01

Giant magnetoimpedance (GMI) measurements in the high-frequency regime utilizing a coplanar waveguide with an integrated Permalloy multilayer and micromachined on a silicon cantilever are reported. The fabrication process is described in detail. The aspect ratio of the magnetic multilayer in the magnetoresistive and magnetostrictive device was varied. Tensile strain and compressive strain were applied. Vector network analyzer measurements in the range from the skin effect to ferromagnetic resonance confirm the technological potential of GMI-based micro-electro-mechanical devices for strain and magnetic field sensing applications. The strain-impedance gauge factor was quantified by finite element strain calculations and reaches a maximum value of almost 200.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Novel ultra-lightweight and high-resolution MEMS x-ray optics

NASA Astrophysics Data System (ADS)

Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Takagi, Utako; Mita, Makoto; Riveros, Raul; Yamaguchi, Hitomi; Kato, Fumiki; Sugiyama, Susumu; Fujiwara, Kouzou; Morishita, Kohei; Nakajima, Kazuo; Fujihira, Shinya; Kanamori, Yoshiaki; Yamasaki, Noriko Y.; Mitsuda, Kazuhisa; Maeda, Ryutaro

2009-05-01

We have been developing ultra light-weight X-ray optics using MEMS (Micro Electro Mechanical Systems) technologies.We utilized crystal planes after anisotropic wet etching of silicon (110) wafers as X-ray mirrors and succeeded in X-ray reflection and imaging. Since we can etch tiny pores in thin wafers, this type of optics can be the lightest X-ray telescope. However, because the crystal planes are alinged in certain directions, we must approximate ideal optical surfaces with flat planes, which limits angular resolution of the optics on the order of arcmin. In order to overcome this issue, we propose novel X-ray optics based on a combination of five recently developed MEMS technologies, namely silicon dry etching, X-ray LIGA, silicon hydrogen anneal, magnetic fluid assisted polishing and hot plastic deformation of silicon. In this paper, we describe this new method and report on our development of X-ray mirrors fabricated by these technologies and X-ray reflection experiments of two types of MEMS X-ray mirrors made of silicon and nickel. For the first time, X-ray reflections on these mirrors were detected in the angular response measurements. Compared to model calculations, surface roughness of the silicon and nickel mirrors were estimated to be 5 nm and 3 nm, respectively.

Technology Finds Its Place in Silicon Valley Schools

ERIC Educational Resources Information Center

Hundley, Paula; Scigliano, Marie

2012-01-01

Technology today is poised to usher in the best of times. Exploring what other districts do highlights the common themes as well as the unique challenges. Three very different districts in Silicon Valley--Portola Valley School District, Campbell Union School District and San Jose Unified School District--explain the strategies they use to enhance…

Overview of Silicon Carbide Technology: Device, Converter, System, and Application

DOE PAGES

Wang, Fei; Zhang, Zheyu

2016-12-28

This article overviews the silicon carbide (SiC) technology. The focus is on the benefits of SiC based power electronics for converters and systems, as well as their ability in enabling new applications. The challenges and research trends on the design and application of SiC power electronics are also discussed.

Silicon Startup Schools: Technocracy, Algorithmic Imaginaries and Venture Philanthropy in Corporate Education Reform

ERIC Educational Resources Information Center

Williamson, Ben

2018-01-01

Technology companies are investing billions of dollars in educational technology, but also creating their own alternative schools. This article traces the emergence of four prototypical 'silicon startup schools' as exemplars of a technocratic mode of corporatized education reform: IBM's P-TECH, part of its Smarter Cities program; AltSchool, a…

Monolithic optical link in silicon-on-insulator CMOS technology.

PubMed

Dutta, Satadal; Agarwal, Vishal; Hueting, Raymond J E; Schmitz, Jurriaan; Annema, Anne-Johan

2017-03-06

This work presents a monolithic laterally-coupled wide-spectrum (350 nm < λ < 1270 nm) optical link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical abrupt n⁺p junctions, separated by a shallow trench isolation composed of silicon dioxide. Medium trench isolation around the devices along with the buried oxide layer provides galvanic isolation. Optical coupling in both avalanche-mode and forward-mode operation of the LED are analyzed for various designs and bias conditions. From both DC and pulsed transient measurements, it is further shown that heating in the avalanche-mode LED leads to a slow thermal coupling to the PD with time constants in the ms range. An integrated heat sink in the same technology leads to a ∼ 6 times reduction in the change in PD junction temperature per unit electrical power dissipated in the avalanche-mode LED. The analysis paves way for wide-spectrum optical links integrated in smart power technologies.