DOE Office of Scientific and Technical Information (OSTI.GOV)

Pradeepkumar, Aiswarya; Mishra, Neeraj; Kermany, Atieh Ranjbar

Epitaxial cubic silicon carbide on silicon is of high potential technological relevance for the integration of a wide range of applications and materials with silicon technologies, such as micro electro mechanical systems, wide-bandgap electronics, and graphene. The hetero-epitaxial system engenders mechanical stresses at least up to a GPa, pressures making it extremely challenging to maintain the integrity of the silicon carbide/silicon interface. In this work, we investigate the stability of said interface and we find that high temperature annealing leads to a loss of integrity. High–resolution transmission electron microscopy analysis shows a morphologically degraded SiC/Si interface, while mechanical stress measurementsmore » indicate considerable relaxation of the interfacial stress. From an electrical point of view, the diode behaviour of the initial p-Si/n-SiC junction is catastrophically lost due to considerable inter-diffusion of atoms and charges across the interface upon annealing. Temperature dependent transport measurements confirm a severe electrical shorting of the epitaxial silicon carbide to the underlying substrate, indicating vast predominance of the silicon carriers in lateral transport above 25 K. This finding has crucial consequences on the integration of epitaxial silicon carbide on silicon and its potential applications.« less

Polycrystalline silicon on tungsten substrates

NASA Technical Reports Server (NTRS)

Bevolo, A. J.; Schmidt, F. A.; Shanks, H. R.; Campisi, G. J.

1979-01-01

Thin films of electron-beam-vaporized silicon were deposited on fine-grained tungsten substrates under a pressure of about 1 x 10 to the -10th torr. Mass spectra from a quadrupole residual-gas analyzer were used to determine the partial pressure of 13 residual gases during each processing step. During separate silicon depositions, the atomically clean substrates were maintained at various temperatures between 400 and 780 C, and deposition rates were between 20 and 630 A min. Surface contamination and interdiffusion were monitored by in situ Auger electron spectrometry before and after cleaning, deposition, and annealing. Auger depth profiling, X-ray analysis, and SEM in the topographic and channeling modes were utilized to characterize the samples with respect to silicon-metal interface, interdiffusion, silicide formation, and grain size of silicon. The onset of silicide formation was found to occur at approximately 625 C. Above this temperature tungsten silicides were formed at a rate faster than the silicon deposition. Fine-grain silicon films were obtained at lower temperatures.

Silicon nitride protective coatings for silvered glass mirrors

DOEpatents

Tracy, C. Edwin; Benson, David K.

1988-01-01

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate before metal deposition to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors.

Silicon nitride protective coatings for silvered glass mirrors

DOEpatents

Tracy, C.E.; Benson, D.K.

1984-07-20

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate prior to metal deposition thereon to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors.

Molecular tailoring of interfaces for thin film on substrate systems

NASA Astrophysics Data System (ADS)

Grady, Martha Elizabeth

Thin film on substrate systems appear most prevalently within the microelectronics industry, which demands that devices operate in smaller and smaller packages with greater reliability. The reliability of these multilayer film systems is strongly influenced by the adhesion of each of the bimaterial interfaces. During use, microelectronic components undergo thermo-mechanical cycling, which induces interfacial delaminations leading to failure of the overall device. The ability to tailor interfacial properties at the molecular level provides a mechanism to improve thin film adhesion, reliability and performance. This dissertation presents the investigation of molecular level control of interface properties in three thin film-substrate systems: photodefinable polyimide films on passivated silicon substrates, self-assembled monolayers at the interface of Au films and dielectric substrates, and mechanochemically active materials on rigid substrates. For all three materials systems, the effect of interfacial modifications on adhesion is assessed using a laser-spallation technique. Laser-induced stress waves are chosen because they dynamically load the thin film interface in a precise, noncontacting manner at high strain rates and are suitable for both weak and strong interfaces. Photodefinable polyimide films are used as dielectrics in flip chip integrated circuit packages to reduce the stress between silicon passivation layers and mold compound. The influence of processing parameters on adhesion is examined for photodefinable polyimide films on silicon (Si) substrates with three different passivation layers: silicon nitride (SiNx), silicon oxynitride (SiOxNy), and the native silicon oxide (SiO2). Interfacial strength increases when films are processed with an exposure step as well as a longer cure cycle. Additionally, the interfacial fracture energy is assessed using a dynamic delamination protocol. The high toughness of this interface (ca. 100 J/m2) makes it difficult to use more conventional interfacial fracture testing techniques. Self-assembled monolayers (SAMs) provide an enabling platform for molecular tailoring of the chemical and physical properties of an interface in an on-demand fashion. The SAM end-group functionality is systematically varied and the corresponding effect on interfacial adhesion between a transfer printed gold (Au) film and a fused silica substrate is measured. SAMs with four different end groups are investigated: methyl, amine, bromine and thiol. In addition to these four end groups, mixed monolayers of increasing molar ratio of thiol to methyl SAMs in solution are investigated. There is a strong dependence of interfacial chemistry on the adhesion strength of Au films. In addition to the chemical functionality of the SAM, surface roughness of the underlying substrate also has a significant impact on the interfacial strength. Thin films of mechanochemically active polymer are subjected to laser-generated, high amplitude acoustic pulses. Stress wave propagation through the film produces large amplitude stresses (>100 MPa) in short time frames (10-20 ns), leading to very high strain-rates (ca. 107-108 s -1). The polymer system, spiropyran (SP)- linked polystyrene (PS), undergoes a force-induced chemical reaction causing fluorescence and color change. Activation of SP is evident via a fluorescence signal in thin films subject to high strain-rates. In contrast, quasi-static loading of bulk SP-linked PS samples failed to result in SP activation. Mechanoresponsive coatings have potential to indicate deformation under shockwave loading conditions. In addition to SP-linked polymer films, the activation of spiropyran interfacial molecules with different side groups is characterized as they adsorb onto a SAM platform with preferential amine terminating chemistry. The reactivity of SP monolayers due to UV irradiation is evaluated by water contact angle goniometry and fluorescence spectroscopy. Side groups on the interfacial spiropyran molecule affect the reactivity and the proximity of neighboring spiropyrans can prevent efficient mobility.

Hybrid stretchable circuits on silicone substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk; Liu, Q.

When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substrate—a silicone matrix carrying concentric rigid disks—ensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

Folded Coplanar Waveguide Slot Antenna on Silicon Substrates With a Polyimide Interface Layer

NASA Technical Reports Server (NTRS)

Bacon, Andrew; Ponchak, George E.; Papapolymerou, John; Bushyager, Nathan; Tentzeris, Manos; Williams, W. D. (Technical Monitor)

2002-01-01

A novel mm-wave Coplanar Waveguide (CPW) folded slot antenna is characterized on low-resistivity Si substrate (1 omega-cm) and a high resistivity Si substrate with a polyimide interface layer for the first time. The antenna resonates around 30 GHz with a return loss greater than 14.6 dB. Measured radiation patterns indicate the existence of a main lobe, but the radiation pattern is affected by a strong surface wave mode, which is greater in the high resistivity Si wafer.

Comparison of silicon, nickel, and nickel silicide (Ni 3Si) as substrates for epitaxial diamond growth

NASA Astrophysics Data System (ADS)

Tucker, D. A.; Seo, D.-K.; Whangbo, M.-H.; Sivazlian, F. R.; Stoner, B. R.; Bozeman, S. P.; Sowers, A. T.; Nemanich, R. J.; Glass, J. T.

1995-07-01

We carried out experimental and theoretical studies aimed at probing interface interactions of diamond with Si, Ni, and Ni 3Si substrates. Oriented diamond films deposited on (100) silicon were characterized by polar Raman, polar XRD, and cross-sectional HRTEM. These studies show that the diamond-(100)/Si(100) interface does not adopt the 45°-rotation but the 3 : 2-match arrangement. Our extended Hückel tight-binding (EHTB) electronic structure calculations for a model system show that the interface interaction favors the 3 : 2-match arrangement. Growth on polycrystalline Ni 3Si resulted in oriented diamond particles while, under the same growth conditions, largely graphite was formed on the nickel substrate. Our EHTB electronic structure calculations for model systems show that the (111) and (100) surfaces of Ni 3Si have a strong preference for diamond-nucleation over graphite-nucleation, but this is not the case for the (111) and (100) surfaces of Ni.

Space-charge behavior of 'Thin-MOS' diodes with MBE-grown silicon films

NASA Technical Reports Server (NTRS)

Lieneweg, U.; Bean, J. C.

1984-01-01

Basic theoretical and experimental characteristics of a novel 'Thin-MOS' technology, which has promising aspects for integrated high-frequency devices up to several hundred gigahertz are presented. The operation of such devices depends on charge injection into undoped silicon layers of about 1000-A thickness, grown by molecular beam epitaxy on heavily doped substrates, and isolation by thermally grown oxides of about 100-A thickness. Capacitance-voltage characteristics measured at high and low frequencies agree well with theoretical ones derived from uni and ambipolar space-charge models. It is concluded that after oxidation the residual doping in the epilayer is less than approximately 10 to the 16th/cu cm and rises by 3 orders of magnitude at the substrate interface within less than 100 A and that interface states at the oxide interface can be kept low.

Self-assembly of microscopic chiplets at a liquid–liquid–solid interface forming a flexible segmented monocrystalline solar cell

PubMed Central

Knuesel, Robert J.; Jacobs, Heiko O.

2010-01-01

This paper introduces a method for self-assembling and electrically connecting small (20–60 micrometer) semiconductor chiplets at predetermined locations on flexible substrates with high speed (62500 chips/45 s), accuracy (0.9 micrometer, 0.14°), and yield (> 98%). The process takes place at the triple interface between silicone oil, water, and a penetrating solder-patterned substrate. The assembly is driven by a stepwise reduction of interfacial free energy where chips are first collected and preoriented at an oil-water interface before they assemble on a solder-patterned substrate that is pulled through the interface. Patterned transfer occurs in a progressing linear front as the liquid layers recede. The process eliminates the dependency on gravity and sedimentation of prior methods, thereby extending the minimal chip size to the sub-100 micrometer scale. It provides a new route for the field of printable electronics to enable the integration of microscopic high performance inorganic semiconductors on foreign substrates with the freedom to choose target location, pitch, and integration density. As an example we demonstrate a fault-tolerant segmented flexible monocrystalline silicon solar cell, reducing the amount of Si that is used when compared to conventional rigid cells. PMID:20080682

Spectroellipsometric detection of silicon substrate damage caused by radiofrequency sputtering of niobium oxide

NASA Astrophysics Data System (ADS)

Lohner, Tivadar; Serényi, Miklós; Szilágyi, Edit; Zolnai, Zsolt; Czigány, Zsolt; Khánh, Nguyen Quoc; Petrik, Péter; Fried, Miklós

2017-11-01

Substrate surface damage induced by deposition of metal atoms by radiofrequency (rf) sputtering or ion beam sputtering onto single-crystalline silicon (c-Si) surface has been characterized earlier by electrical measurements. The question arises whether it is possible to characterize surface damage using spectroscopic ellipsometry (SE). In our experiments niobium oxide layers were deposited by rf sputtering on c-Si substrates in gas mixture of oxygen and argon. Multiple angle of incidence spectroscopic ellipsometry measurements were performed, a four-layer optical model (surface roughness layer, niobium oxide layer, native silicon oxide layer and ion implantation-amorphized silicon [i-a-Si] layer on a c-Si substrate) was created in order to evaluate the spectra. The evaluations yielded thicknesses of several nm for the i-a-Si layer. Better agreement could be achieved between the measured and the generated spectra by inserting a mixed layer (with components of c-Si and i-a-Si applying the effective medium approximation) between the silicon oxide layer and the c-Si substrate. High depth resolution Rutherford backscattering (RBS) measurements were performed to investigate the interface disorder between the deposited niobium oxide layer and the c-Si substrate. Atomic resolution cross-sectional transmission electron microscopy investigation was applied to visualize the details of the damaged subsurface region of the substrate.

Wet-chemical passivation of atomically flat and structured silicon substrates for solar cell application

NASA Astrophysics Data System (ADS)

Angermann, H.; Rappich, J.; Korte, L.; Sieber, I.; Conrad, E.; Schmidt, M.; Hübener, K.; Polte, J.; Hauschild, J.

2008-04-01

Special sequences of wet-chemical oxidation and etching steps were optimised with respect to the etching behaviour of differently oriented silicon to prepare very smooth silicon interfaces with excellent electronic properties on mono- and poly-crystalline substrates. Surface photovoltage (SPV) and photoluminescence (PL) measurements, atomic force microscopy (AFM) and scanning electron microscopy (SEM) investigations were utilised to develop wet-chemical smoothing procedures for atomically flat and structured surfaces, respectively. Hydrogen-termination as well as passivation by wet-chemical oxides were used to inhibit surface contamination and native oxidation during the technological processing. Compared to conventional pre-treatments, significantly lower micro-roughness and densities of surface states were achieved on mono-crystalline Si(100), on evenly distributed atomic steps, such as on vicinal Si(111), on silicon wafers with randomly distributed upside pyramids, and on poly-crystalline EFG ( Edge-defined Film-fed- Growth) silicon substrates. The recombination loss at a-Si:H/c-Si interfaces prepared on c-Si substrates with randomly distributed upside pyramids was markedly reduced by an optimised wet-chemical smoothing procedure, as determined by PL measurements. For amorphous-crystalline hetero-junction solar cells (ZnO/a-Si:H(n)/c-Si(p)/Al) with textured c-Si substrates the smoothening procedure results in a significant increase of short circuit current Isc, fill factor and efficiency η. The scatter in the cell parameters for measurements on different cells is much narrower, as compared to conventional pre-treatments, indicating more well-defined and reproducible surface conditions prior to a-Si:H emitter deposition and/or a higher stability of the c-Si surface against variations in the a-Si:H deposition conditions.

Nanophotonic applications for silicon-on-insulator (SOI)

NASA Astrophysics Data System (ADS)

de la Houssaye, Paul R.; Russell, Stephen D.; Shimabukuro, Randy L.

2004-07-01

Silicon-on-insulator is a proven technology for very large scale integration of microelectronic devices. The technology also offers the potential for development of nanophotonic devices and the ability to interface such devices to the macroscopic world. This paper will report on fabrication techniques used to form nano-structured silicon wires on an insulating structure that is amenable to interfacing nanostructured sensors with high-performance microelectronic circuitry for practical implementation. Nanostructures formed on silicon-on-sapphire can also exploit the transparent substrate for novel device geometries. This research harnesses the unique properties of a high-quality single crystal film of silicon on sapphire and uses the film thickness as one of the confinement dimensions. Lateral arrays of silicon nanowires were fabricated in the thin (5 to 20 nm) silicon layer and studied. This technique offers simplified contact to individual wires and provides wire surfaces that are more readily accessible for controlled alteration and device designs.

Pressure cell for investigations of solid-liquid interfaces by neutron reflectivity.

PubMed

Kreuzer, Martin; Kaltofen, Thomas; Steitz, Roland; Zehnder, Beat H; Dahint, Reiner

2011-02-01

We describe an apparatus for measuring scattering length density and structure of molecular layers at planar solid-liquid interfaces under high hydrostatic pressure conditions. The device is designed for in situ characterizations utilizing neutron reflectometry in the pressure range 0.1-100 MPa at temperatures between 5 and 60 °C. The pressure cell is constructed such that stratified molecular layers on crystalline substrates of silicon, quartz, or sapphire with a surface area of 28 cm(2) can be investigated against noncorrosive liquid phases. The large substrate surface area enables reflectivity to be measured down to 10(-5) (without background correction) and thus facilitates determination of the scattering length density profile across the interface as a function of applied load. Our current interest is on the stability of oligolamellar lipid coatings on silicon surfaces against aqueous phases as a function of applied hydrostatic pressure and temperature but the device can also be employed to probe the structure of any other solid-liquid interface.

Model for interface formation and the resulting electrical properties for barium-strontium-titanate films on silicon

NASA Astrophysics Data System (ADS)

Mueller, A. H.; Suvorova, N. A.; Irene, E. A.; Auciello, O.; Schultz, J. A.

2003-04-01

The interface formation between sputtered barium strontium titanate (BST) films and both Si and SiO2 substrate surfaces has been followed using real-time spectroscopic ellipsometry and the mass spectrometry of recoiled ions. In both substrates an intermixed interface layer was observed and subcutaneous Si oxidation occurred. A model for the interface formation is proposed in which the interface includes an SiO2 film on Si, and an intermixed film on which is pure BST. During the deposition of BST the interfaces films were observed to change in time. Electrical characterization of the resulting metal-BST interface capacitors indicates that those samples with SiO2 on the Si surface had the best electrical characteristics.

Chemical Interaction-Guided, Metal-Free Growth of Large-Area Hexagonal Boron Nitride on Silicon-Based Substrates.

PubMed

Behura, Sanjay; Nguyen, Phong; Debbarma, Rousan; Che, Songwei; Seacrist, Michael R; Berry, Vikas

2017-05-23

Hexagonal boron nitride (h-BN) is an ideal platform for interfacing with two-dimensional (2D) nanomaterials to reduce carrier scattering for high-quality 2D electronics. However, scalable, transfer-free growth of hexagonal boron nitride (h-BN) remains a challenge. Currently, h-BN-based 2D heterostructures require exfoliation or chemical transfer of h-BN grown on metals resulting in small areas or significant interfacial impurities. Here, we demonstrate a surface-chemistry-influenced transfer-free growth of large-area, uniform, and smooth h-BN directly on silicon (Si)-based substrates, including Si, silicon nitride (Si 3 N 4 ), and silicon dioxide (SiO 2 ), via low-pressure chemical vapor deposition. The growth rates increase with substrate electronegativity, Si < Si 3 N 4 < SiO 2 , consistent with the adsorption rates calculated for the precursor molecules via atomistic molecular dynamics simulations. Under graphene with high grain density, this h-BN film acts as a polymer-free, planar-dielectric interface increasing carrier mobility by 3.5-fold attributed to reduced surface roughness and charged impurities. This single-step, chemical interaction guided, metal-free growth mechanism of h-BN for graphene heterostructures establishes a potential pathway for the design of complex and integrated 2D-heterostructured circuitry.

Heat- and electron-beam-induced transport of gold particles into silicon oxide and silicon studied by in situ high-resolution transmission electron microscopy.

PubMed

Biskupek, Johannes; Kaiser, Ute; Falk, Fritz

2008-06-01

In this study, we describe the transport of gold (Au) nanoparticles from the surface into crystalline silicon (Si) covered by silicon oxide (SiO(2)) as revealed by in situ high-resolution transmission electron microscopy. Complete crystalline Au nanoparticles sink through the SiO(2) layer into the Si substrate when high-dose electron irradiation is applied and temperature is raised above 150 degrees C. Above temperatures of 250 degrees C, the Au nanoparticles finally dissolve into fragments accompanied by crystallization of the amorphized Si substrate around these fragments. The transport process is explained by a wetting process followed by Stokes motion. Modelling this process yields boundaries for the interface energies involved.

The microstructure of laterally seeded silicon-on-oxide

NASA Astrophysics Data System (ADS)

Pinizzotto, R. F.; Lam, H. W.; Vaandrager, B. L.

1982-03-01

The production of large scale integrated circuits in thin silicon films on insulating substrates is currently of much interest in the electronics industry. One of the most promising techniques of forming this composite structure is by lateral seeding. We have used optical microscopy and transmission electron microscopy to characterize the microstructure of silicon-on-oxide formed by scanning CW laser induced lateral epitaxy. The primary defects are dislocations. Dislocation rearrangement leads to the formation of both small angle boundaries (stable, regular dislocation arrays) and grain boundaries. The grains were found to be misoriented to the <100> direction perpendicular to the film plane by ≤ 4° and to the <100> directions in the plane of the film by ≤ 2°. Internal reflection twins are a common defect. Microtwinning was found to occur at the vertical step caused by the substrate-oxide interface if the substrate to oxide step height was > 120 nm. The microstructure is continuous across successive scan lines. Microstructural defects are found to initiate at the same topographical location in different oxide pads. We propose that this is due to the meeting of two crystallization growth fronts. The liquid silicon between the fronts causes large stresses in this area because of the 9% volume increase during solidification. The defects observed in the bulk may form by a similar mechanism or by dislocation generation at substrate-oxide interface irregularities. The models predict that slower growth leads to improved material quality. This has been observed experimentally.

Optical and Interface-Based Methods of Defect Engineering in Silicon

ERIC Educational Resources Information Center

Kondratenko, Yevgeniy Vladimirovich

2009-01-01

Ion implantation is widely used in the microelectronics industry for fabrication of source and drain transistor regions. Unfortunately, implantation causes considerable damage to the substrate lattice rendering most of the implanted dopant electrically inactive. Rapid thermal annealing (RTA) heals the damage by rapidly heating the substrate with a…

Optically-initiated silicon carbide high voltage switch with contoured-profile electrode interfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sullivan, James S.; Hawkins, Steven A.

An improved photoconductive switch having a SiC or other wide band gap substrate material with opposing contoured profile cavities which have a contoured profile selected from one of Rogowski, Bruce, Chang, Harrison, and Ernst profiles, and two electrodes with matching contoured-profile convex interface surfaces.

The effect of surface topography on the micellisation of hexadecyltrimethylammonium chloride at the silicon-aqueous interface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Darkins, Robert; Sushko, Maria L.; Liu, Jun

2015-02-11

Amphiphilic aggregation at solid-liquid interfaces can generate mesostructured micelles that can serve as soft templates. In this study we have simulated the self-assembly of hexadecyltrimethylammonium chloride (C16TAC) surfactants at the Si(100)- and Si(111)-aqueous interfaces. The surfactants are found to form semicylindrical micelles on Si(100) but hemispherical micelles on Si(111). This difference in micelle structure is shown to be a consequence of the starkly different surface topographies that result from the reconstruction of the two silicon surfaces. This reveals that micelle structure can be governed by epitaxial matching even with non-polar substrates.

Indium-bump-free antimonide superlattice membrane detectors on silicon substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zamiri, M., E-mail: mzamiri@chtm.unm.edu, E-mail: skrishna@chtm.unm.edu; Klein, B.; Schuler-Sandy, T.

2016-02-29

We present an approach to realize antimonide superlattices on silicon substrates without using conventional Indium-bump hybridization. In this approach, PIN superlattices are grown on top of a 60 nm Al{sub 0.6}Ga{sub 0.4}Sb sacrificial layer on a GaSb host substrate. Following the growth, the individual pixels are transferred using our epitaxial-lift off technique, which consists of a wet-etch to undercut the pixels followed by a dry-stamp process to transfer the pixels to a silicon substrate prepared with a gold layer. Structural and optical characterization of the transferred pixels was done using an optical microscope, scanning electron microscopy, and photoluminescence. The interface betweenmore » the transferred pixels and the new substrate was abrupt, and no significant degradation in the optical quality was observed. An Indium-bump-free membrane detector was then fabricated using this approach. Spectral response measurements provided a 100% cut-off wavelength of 4.3 μm at 77 K. The performance of the membrane detector was compared to a control detector on the as-grown substrate. The membrane detector was limited by surface leakage current. The proposed approach could pave the way for wafer-level integration of photonic detectors on silicon substrates, which could dramatically reduce the cost of these detectors.« less

180 Degree Hybrid (Rat-Race) Junction on CMOS Grade Silicon with a Polyimide Interface Layer

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Papapolymerou, John

2003-01-01

180-degree hybrid junctions can be used to equally divide power between two output ports with either a 0 or 180-degree phase difference. Alternatively, they can be used to combine signals from two sources and output a sum and difference signal. The main limitation of implementing; these on CMOS grade silicon is the high loss associated with the substrate. In this paper, we present a low loss 180-degree hybrid junction on CMOS grade (15 omega-cm) silicon with a polyimide interface layer for the first time. The divider utilizes Finite Ground Coplanar (FGC) line technology, and operates at a center frequency of 15 GIIz.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Structure and method for controlling band offset and alignment at a crystalline oxide-on-semiconductor interface

DOEpatents

McKee, Rodney A.; Walker, Frederick J.

2003-11-25

A crystalline oxide-on-semiconductor structure and a process for constructing the structure involves a substrate of silicon, germanium or a silicon-germanium alloy and an epitaxial thin film overlying the surface of the substrate wherein the thin film consists of a first epitaxial stratum of single atomic plane layers of an alkaline earth oxide designated generally as (AO).sub.n and a second stratum of single unit cell layers of an oxide material designated as (A'BO.sub.3).sub.m so that the multilayer film arranged upon the substrate surface is designated (AO).sub.n (A'BO.sub.3).sub.m wherein n is an integer repeat of single atomic plane layers of the alkaline earth oxide AO and m is an integer repeat of single unit cell layers of the A'BO.sub.3 oxide material. Within the multilayer film, the values of n and m have been selected to provide the structure with a desired electrical structure at the substrate/thin film interface that can be optimized to control band offset and alignment.

Nanobonding: A key technology for emerging applications in health and environmental sciences

NASA Astrophysics Data System (ADS)

Howlader, Matiar M. R.; Deen, M. Jamal; Suga, Tadatomo

2015-03-01

In this paper, surface-activation-based nanobonding technology and its applications are described. This bonding technology allows for the integration of electronic, photonic, fluidic and mechanical components into small form-factor systems for emerging sensing and imaging applications in health and environmental sciences. Here, we describe four different nanobonding techniques that have been used for the integration of various substrates — silicon, gallium arsenide, glass, and gold. We use these substrates to create electronic (silicon), photonic (silicon and gallium arsenide), microelectromechanical (glass and silicon), and fluidic (silicon and glass) components for biosensing and bioimaging systems being developed. Our nanobonding technologies provide void-free, strong, and nanometer scale bonding at room temperature or at low temperatures (<200 °C), and do not require chemicals, adhesives, or high external pressure. The interfaces of the nanobonded materials in ultra-high vacuum and in air correspond to covalent bonds, and hydrogen or hydroxyl bonds, respectively.

Effects of varying oxygen partial pressure on molten silicon-ceramic substrate interactions

NASA Technical Reports Server (NTRS)

Ownby, D. P.; Barsoum, M. W.

1980-01-01

The silicon sessile drop contact angle was measured on hot pressed silicon nitride, silicon nitride coated on hot pressed silicon nitride, silicon carbon coated on graphite, and on Sialon to determine the degree to which silicon wets these substances. The post-sessile drop experiment samples were sectioned and photomicrographs were taken of the silicon-substrate interface to observe the degree of surface dissolution and degradation. Of these materials, silicon did not form a true sessile drop on the SiC on graphite due to infiltration of the silicon through the SiC coating, nor on the Sialon due to the formation of a more-or-less rigid coating on the liquid silicon. The most wetting was obtained on the coated Si3N4 with a value of 42 deg. The oxygen concentrations in a silicon ribbon furnace and in a sessile drop furnace were measured using the protable thoria-yttria solid solution electrolyte oxygen sensor. Oxygen partial pressures of 10 to the minus 7 power atm and 10 to the minus 8 power atm were obtained at the two facilities. These measurements are believed to represent nonequilibrium conditions.

Laser processing for strengthening of the self-restoring metal-elastomer interface on a silicone sheet

NASA Astrophysics Data System (ADS)

Yasuda, Kiyokazu

2012-08-01

A self-restoring microsystem is a unique concept which realizes the sensing functionality and robust interface which mechanically and electrically connects a deformable object such as a human body with printed electronic devices. For this purpose, the formation of conductive wiring on an elastomer substrate was attempted using the nickel ink printing process. Before the wiring process, surface patterning of a silicone sheet by a galvano-scanned infrared laser was conducted for the enhancement of interface adhesion of the metal deposit and polymer. Characterization of the fabricated pattern was conducted by optical microscopy. The novel method was successfully demonstrated as a fabrication of selective patterns of metal particles on self-restoring MEMS.

Atomic insight into tribochemical wear mechanism of silicon at the Si/SiO2 interface in aqueous environment: Molecular dynamics simulations using ReaxFF reactive force field

NASA Astrophysics Data System (ADS)

Wen, Jialin; Ma, Tianbao; Zhang, Weiwei; Psofogiannakis, George; van Duin, Adri C. T.; Chen, Lei; Qian, Linmao; Hu, Yuanzhong; Lu, Xinchun

2016-12-01

In this work, the atomic mechanism of tribochemical wear of silicon at the Si/SiO2 interface in aqueous environment was investigated using ReaxFF molecular dynamics (MD) simulations. Two types of Si atom removal pathways were detected in the wear process. The first is caused by the destruction of stretched Si-O-Si bonds on the Si substrate surface and is assisted by the attachment of H atoms on the bridging oxygen atoms of the bonds. The other is caused by the rupture of Si-Si bonds in the stretched Si-Si-O-Si bond chains at the interface. Both pathways effectively remove Si atoms from the silicon surface via interfacial Si-O-Si bridge bonds. Our simulations also demonstrate that higher pressures applied to the silica phase can cause more Si atoms to be removed due to the formation of increased numbers of interfacial Si-O-Si bridge bonds. Besides, water plays a dual role in the wear mechanism, by oxidizing the Si substrate surface as well as by preventing the close contact of the surfaces. This work shows that the removal of Si atoms from the substrate is a result of both chemical reaction and mechanical effects and contributes to the understanding of tribochemical wear behavior in the microelectromechanical systems (MEMS) and Si chemical mechanical polishing (CMP) process.

Self-organized, effective medium black silicon antireflection structures for silicon optics in the mid-infrared

NASA Astrophysics Data System (ADS)

Steglich, Martin; Käsebier, Thomas; Kley, Ernst-Bernhard; Tünnermann, Andreas

2016-09-01

Thanks to its high quality and low cost, silicon is the material of choice for optical devices operating in the mid-infrared (MIR; 2 μm to 6 μm wavelength). Unfortunately in this spectral region, the refractive index is comparably high (about 3.5) and leads to severe reflection losses of about 30% per interface. In this work, we demonstrate that self-organized, statistical Black Silicon structures, fabricated by Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE), can be used to effectively suppress interface reflection. More importantly, it is shown that antireflection can be achieved in an image-preserving, non-scattering way. This enables Black Silicon antireflection structures (ARS) for imaging applications in the MIR. It is demonstrated that specular transmittances of 97% can be easily achieved on both flat and curved substrates, e.g. lenses. Moreover, by a combined optical and morphological analysis of a multitude of different Black Silicon ARS, an effective medium criterion for the examined structures is derived that can also be used as a design rule for maximizing sample transmittance in a desired wavelength range. In addition, we show that the mechanical durability of the structures can be greatly enhanced by coating with hard dielectric materials like diamond-like carbon (DLC), hence enabling practical applications. Finally, the distinct advantages of statistical Black Silicon ARS over conventional AR layer stacks are discussed: simple applicability to topological substrates, absence of thermal stress and cost-effectiveness.

Propagation Characteristics of Finite Ground Coplanar Waveguide on Si Substrates With Porous Si and Polyimide Interface Layers

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Itotia, Isaac K.; Drayton, Rhonda Franklin

2003-01-01

Measured and modeled propagation characteristics of Finite Ground Coplanar (FGC) waveguide fabricated on a 15 ohm-cm Si substrate with a 23 micron thick, 68% porous Si layer and a 20 micron thick polyimide interface layer are presented for the first time. Attenuation and effective permittivity as function of the FGC geometry and the bias between the center conductor and the ground planes are presented. It is shown that the porous Si reduces the attenuation by 1 dB/cm compared to FGC lines with only polyimide interface layers, and the polyimide on porous silicon demonstrates negligible bias dependence.

Characterization of Silicon Moth-Eye Antireflection Coatings for Astronomical Applications in the Infrared

NASA Astrophysics Data System (ADS)

Jeram, Sarik; Ge, Jian; Jiang, Peng; Phillips, Blayne

2016-01-01

Silicon moth-eye antireflective structures have emerged to be an excellent approachfor reducing the amount of light that is lost upon incidence on a given surface of optics made of silicon. This property has been exploited for a wide variety of products ranging from eyeglasses and flat-panel displays to solar panels. These materials typically come in the form of coatings that are applied to an optical substrate such as glass. Moth-eye coatings, made of a periodic array of subwavelength pillars on silicon substrates or other substrates, can produce the desired antireflection (AR) performance for a broad wavelength range and over a wide range of incident angles. In the field of astronomy, every photon striking a detector is significant - and thus, losses from reflectivity at the various optical interfaces before a detector can have significant implications to the science at hand. Moth-eye AR coatings on these optical interfaces may minimize their reflection losses while maximizing light throughput for a multitude of different astronomical instruments. In addition, moth-eye AR coatings, which are patterned directly on silicon surfaces, can significantly enhance the coating durability. At the University of Florida, we tested two moth-eye filters designed for use in the near-infrared regime at 1-8 microns by examining their optical properties, such as transmission, the scattered light, and wavefront quality, and testing the coatings at cryogenic temperatures to characterize their viability for use in both ground- and space-based infrared instruments. This presentation will report our lab evaluation results.

Continuous coating of silicon-on-ceramic

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Schuldt, S. B.; Grung, B. L.; Zook, J. D.; Butter, C. D.

1980-01-01

Growth of sheet silicon on low-cost substrates has been demonstrated by the silicon coating with inverted meniscus (SCIM) technique. A mullite-based ceramic substrate is coated with carbon and then passed over a trough of molten silicon with a raised meniscus. Solidification occurs at the trailing edge of the downstream meniscus, producing a silicon-on-ceramic (SOC) layer. Meniscus shape and stability are controlled by varying the level of molten silicon in a reservoir connected to the trough. The thermal conditions for growth and the crystallographic texture of the SOC layers are similar to those produced by dip-coating, the original technique of meniscus-controlled growth. The thermal conditions for growth have been analyzed in some detail. The analysis correctly predicts the velocity-thickness relationship and the liquid-solid interface shape for dip-coating, and appears to be equally applicable to SCIM-coating. Solar cells made from dip-coated SOC material have demonstrated efficiencies of 10% on 4-sq cm cells and 9.9% on 10-sq cm cells.

First-principles investigation of band offsets and dielectric properties of Silicon-Silicon Nitride interfaces

NASA Astrophysics Data System (ADS)

Pham, Tuan Anh; Li, Tianshu; Gygi, Francois; Galli, Giulia

2011-03-01

Silicon Nitride (Si3N4) is a possible candidate material to replace or be alloyed with SiO2 to form high-K dielectric films on Si substrates, so as to help prevent leakage currents in modern CMOS transistors. Building on our previous work on dielectric properties of crystalline and amorphous Si3N4 slabs, we present an analysis of the band offsets and dielectric properties of crystalline-Si/amorphous Si3N4 interfaces based on first principles calculations. We discuss shortcomings of the conventional bulk-plus line up approach in band offset calculations for systems with an amorphous component, and we present the results of band offsets obtained from calculations of local density of states. Finally, we describe the role of bonding configurations in determining band edges and dielectric constants at the interface. We acknowledge financial support from Intel Corporation.

Imaging of the native inversion layer in Silicon-On-Insulator wafers via Scanning Surface Photovoltage: Implications for RF device performance

NASA Astrophysics Data System (ADS)

Dahanayaka, Daminda; Wong, Andrew; Kaszuba, Philip; Moszkowicz, Leon; Slinkman, James; IBM SPV Lab Team

2014-03-01

Silicon-On-Insulator (SOI) technology has proved beneficial for RF cell phone technologies, which have equivalent performance to GaAs technologies. However, there is evident parasitic inversion layer under the Buried Oxide (BOX) at the interface with the high resistivity Si substrate. The latter is inferred from capacitance-voltage measurements on MOSCAPs. The inversion layer has adverse effects on RF device performance. We present data which, for the first time, show the extent of the inversion layer in the underlying substrate. This knowledge has driven processing techniques to suppress the inversion.

Interface effects in the dissolution of silicon into thin gold films

NASA Technical Reports Server (NTRS)

Sankur, H.; Mccaldin, J. O.

1975-01-01

The dissolution of crystalline Si and amorphous Si substrates into thin films of evaporated Au was studied with an electron microprobe and scanning electron microscopy. The dissolution pattern was found to be nonuniform along the plane of the surface and dependent on the crystalline orientation of the Si substrate. The dissolution is greatly facilitated when a very thin layer of Pd is evaporated between the Si substrate and the Au film.

Thin film silicon by a microwave plasma deposition technique: Growth and devices, and, interface effects in amorphous silicon/crystalline silicon solar cells

NASA Astrophysics Data System (ADS)

Jagannathan, Basanth

Thin film silicon (Si) was deposited by a microwave plasma CVD technique, employing double dilution of silane, for the growth of low hydrogen content Si films with a controllable microstructure on amorphous substrates at low temperatures (<400sp°C). The double dilution was achieved by using a Ar (He) carrier for silane and its subsequent dilution by Hsb2. Structural and electrical properties of the films have been investigated over a wide growth space (temperature, power, pressure and dilution). Amorphous Si films deposited by silane diluted in He showed a compact nature and a hydrogen content of ˜8 at.% with a photo/dark conductivity ratio of 10sp4. Thin film transistors (W/L = 500/25) fabricated on these films, showed an on/off ratio of ˜10sp6 and a low threshold voltage of 2.92 volts. Microcrystalline Si films with a high crystalline content (˜80%) were also prepared by this technique. Such films showed a dark conductivity ˜10sp{-6} S/cm, with a conduction activation energy of 0.49 eV. Film growth and properties have been compared for deposition in Ar and He carrier systems and growth models have been proposed. Low temperature junction formation by undoped thin film silicon was examined through a thin film silicon/p-type crystalline silicon heterojunctions. The thin film silicon layers were deposited by rf glow discharge, dc magnetron sputtering and microwave plasma CVD. The hetero-interface was identified by current transport analysis and high frequency capacitance methods as the key parameter controlling the photovoltaic (PV) response. The effect of the interface on the device properties (PV, junction, and carrier transport) was examined with respect to modifications created by chemical treatment, type of plasma species, their energy and film microstructure interacting with the substrate. Thermally stimulated capacitance was used to determine the interfacial trap parameters. Plasma deposition of thin film silicon on chemically clean c-Si created electron trapping sites while hole traps were seen when a thin oxide was present at the interface. Under optimized conditions, a 10.6% efficient cell (11.5% with SiOsb2 A/R) with an open circuit voltage of 0.55 volts and a short circuit current density of 30 mA/cmsp2 was fabricated.

Band offset engineering of 2DEG oxide systems on Si

NASA Astrophysics Data System (ADS)

Jin, Eric; Kornblum, Lior; Kumah, Divine; Zou, Ke; Broadbridge, Christine; Ngai, Joseph; Ahn, Charles; Walker, Fred

2015-03-01

The discovery of 2-dimensional electron gases (2DEGs) at perovskite oxide interfaces has sparked much interest in recent years due to their large carrier densities when compared with semiconductor heterostructures. For device applications, these oxide systems are plagued by low room temperature electrical mobilities. We present an approach to combine the high carrier density of 2DEG oxides with a higher mobility medium in order to realize the combined benefits of higher mobility and carrier density. We grow epitaxial films of the interfacial oxide system LaTiO3/SrTiO3 (LTO/STO) on silicon by molecular beam epitaxy. Magnetotransport measurements show that the sheet carrier densities of the heterostructures scale with the number of LTO/STO interfaces, consistent with the presence of a 2DEG at each interface. Sheet carrier densities of 8.9 x 1014 cm-2 per interface are measured. Band offsets between the STO and Si are obtained, showing that the conduction band edge of the STO is close in energy to that of silicon, but in a direction that hinders carrier transfer to the silicon substrate. Through modification of the STO/Si interface, we suggest an approach to raise the band offset in order to move the 2DEG from the oxide into the silicon.

Interface and interaction of graphene layers on SiC(0001[combining macron]) covered with TiC(111) intercalation.

PubMed

Wang, Lu; Wang, Qiang; Huang, Jianmei; Li, Wei-Qi; Chen, Guang-Hui; Yang, Yanhui

2017-10-11

It is important to understand the interface and interaction between the graphene layer, titanium carbide [TiC(111)] interlayer, and silicon carbide [SiC(0001[combining macron])] substrates in epitaxial growth of graphene on silicon carbide (SiC) substrates. In this study, the fully relaxed interfaces which consist of up to three layers of TiC(111) coatings on the SiC(0001[combining macron]) as well as the graphene layers interactions with these TiC(111)/SiC(0001[combining macron]) were systematically studied using the density functional theory-D2 (DFT-D2) method. The results showed that the two layers of TiC(111) coating with the C/C-terminated interfaces were thermodynamically more favorable than one or three layers of TiC(111) on the SiC(0001[combining macron]). Furthermore, the bonding of the Ti-hollow-site stacked interfaces would be a stronger link than that of the Ti-Fcc-site stacked interfaces. However, the formation of the C/Ti/C and Ti/C interfaces implied that the first upper carbon layer can be formed on TiC(111)/SiC(0001[combining macron]) using the decomposition of the weaker Ti-C and C-Si interfacial bonds. When growing graphene layers on these TiC(111)/SiC(0001[combining macron]) substrates, the results showed that the interaction energy depended not only on the thickness of the TiC(111) interlayer, but also on the number of graphene layers. Bilayer graphene on the two layer thick TiC(111)/SiC(0001[combining macron]) was thermodynamically more favorable than a monolayer or trilayer graphene on these TiC(111)/SiC(0001[combining macron]) substrates. The adsorption energies of the bottom graphene layers with the TiC(111)/SiC(0001[combining macron]) substrates increased with the decrease of the interface vertical distance. The interaction energies between the bottom, second and third layers of graphene on the TiC(111)/SiC(0001[combining macron]) were significantly higher than that of the freestanding graphene layers. All of these findings provided insight into the growth of epitaxial graphene on TiC(111)/SiC(0001[combining macron]) substrates and the design of graphene/TiC/SiC-based electronic devices.

Processing of n+/p-/p+ strip detectors with atomic layer deposition (ALD) grown Al2O3 field insulator on magnetic Czochralski silicon (MCz-si) substrates

NASA Astrophysics Data System (ADS)

Härkönen, J.; Tuovinen, E.; Luukka, P.; Gädda, A.; Mäenpää, T.; Tuominen, E.; Arsenovich, T.; Junkes, A.; Wu, X.; Li, Z.

2016-08-01

Detectors manufactured on p-type silicon material are known to have significant advantages in very harsh radiation environment over n-type detectors, traditionally used in High Energy Physics experiments for particle tracking. In p-type (n+ segmentation on p substrate) position-sensitive strip detectors, however, the fixed oxide charge in the silicon dioxide is positive and, thus, causes electron accumulation at the Si/SiO2 interface. As a result, unless appropriate interstrip isolation is applied, the n-type strips are short-circuited. Widely adopted methods to terminate surface electron accumulation are segmented p-stop or p-spray field implantations. A different approach to overcome the near-surface electron accumulation at the interface of silicon dioxide and p-type silicon is to deposit a thin film field insulator with negative oxide charge. We have processed silicon strip detectors on p-type Magnetic Czochralski silicon (MCz-Si) substrates with aluminum oxide (Al2O3) thin film insulator, grown with Atomic Layer Deposition (ALD) method. The electrical characterization by current-voltage and capacitance-voltage measurement shows reliable performance of the aluminum oxide. The final proof of concept was obtained at the test beam with 200 GeV/c muons. For the non-irradiated detector the charge collection efficiency (CCE) was nearly 100% with a signal-to-noise ratio (S/N) of about 40, whereas for the 2×1015 neq/cm2 proton irradiated detector the CCE was 35%, when the sensor was biased at 500 V. These results are comparable with the results from p-type detectors with the p-spray and p-stop interstrip isolation techniques. In addition, interestingly, when the aluminum oxide was irradiated with Co-60 gamma-rays, an accumulation of negative fixed oxide charge in the oxide was observed.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Characterization of spiral ganglion neurons cultured on silicon micro-pillar substrates for new auditory neuro-electronic interfaces.

PubMed

Mattotti, M; Micholt, L; Braeken, D; Kovačić, D

2015-04-01

One of the strategies to improve cochlear implant technology is to increase the number of electrodes in the neuro-electronic interface. The objective was to characterize in vitro cultures of spiral ganglion neurons (SGN) cultured on surfaces of novel silicon micro-pillar substrates (MPS). SGN from P5 rat pups were cultured on MPS with different micro-pillar widths (1-5.6 μm) and spacings (0.6-15 μm) and were compared with control SGN cultures on glass coverslips by immunocytochemistry and scanning electron microscopy (SEM). Overall, MPS support SGN growth equally well as the control glass surfaces. Micro-pillars of a particular size-range (1.2-2.4 μm) were optimal in promoting SGN presence, neurite growth and alignment. On this specific micro-pillar size, more SGN were present, and neurites were longer and more aligned. SEM pictures highlight how cells on micro-pillars with smaller spacings grow directly on top of pillars, while at wider spacings (from 3.2 to 15 μm) they grow on the bottom of the surface, losing contact guidance. Further, we found that MPS encourage more monopolar and bipolar SGN morphologies compared to the control condition. Finally, MPS induce longest neurite growth with minimal interaction of S100+ glial cells. These results indicate that silicon micro-pillar substrates create a permissive environment for the growth of primary auditory neurons promoting neurite sprouting and are a promising technology for future high-density three-dimensional CMOS-based auditory neuro-electronic interfaces.

A deep-level transient spectroscopy study of gamma-ray irradiation on the passivation properties of silicon nitride layer on silicon

NASA Astrophysics Data System (ADS)

Dong, Peng; Yu, Xuegong; Ma, Yao; Xie, Meng; Li, Yun; Huang, Chunlai; Li, Mo; Dai, Gang; Zhang, Jian

2017-08-01

Plasma-enhanced chemical vapor deposited silicon nitride (SiNx) films are extensively used as passivation material in the solar cell industry. Such SiNx passivation layers are the most sensitive part to gamma-ray irradiation in solar cells. In this work, deep-level transient spectroscopy has been applied to analyse the influence of gamma-ray irradiation on the passivation properties of SiNx layer on silicon. It is shown that the effective carrier lifetime decreases with the irradiation dose. At the same time, the interface state density is significantly increased after irradiation, and its energy distribution is broadened and shifts deeper with respect to the conduction band edge, which makes the interface states becoming more efficient recombination centers for carriers. Besides, C-V characteristics show a progressive negative shift with increasing dose, indicating the generation of effective positive charges in SiNx films. Such positive charges are beneficial for shielding holes from the n-type silicon substrates, i. e. the field-effect passivation. However, based on the reduced carrier lifetime after irradiation, it can be inferred that the irradiation induced interface defects play a dominant role over the trapped positive charges, and therefore lead to the degradation of passivation properties of SiNx on silicon.

Metal oxide nanorod arrays on monolithic substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Pu-Xian; Guo, Yanbing; Ren, Zheng

A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can includemore » a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod. Structures can be bonded to the surface of a substrate and resist erosion if exposed to high velocity flow rates.« less

Delamination analysis of metal-ceramic multilayer coatings subject to nanoindentation

DOE PAGES

Jamison, Ryan Dale; Shen, Yu -Lin

2016-01-22

Internal damage has been experimentally observed in aluminum (Al)/silicon carbide (SiC) multilayer coatings subject to nanoindentation loading. Post-indentation characterization has identified that delamination at the coating/substrate interface is the most prominent form of damage. In this study the finite element method is employed to study the effect of delamination on indentation-derived hardness and Young's modulus. The model features alternating Al/SiC nanolayers above a silicon (Si) substrate, in consistence with the actual material system used in earlier experiments. Cohesive elements with a traction–separation relationship are used to facilitate delamination along the coating/substrate interface. Delamination is observed numerically to be sensitive tomore » the critical normal and shear stresses that define the cohesive traction–separation behavior. Axial tensile stress below the edge of indentation contact is found to be the largest contributor to damage initiation and evolution. Delamination results in a decrease in both indentation-derived hardness and Young's modulus. As a result, a unique finding is that delamination can occur during the unloading process of indentation, depending on the loading condition and critical tractions.« less

Oxide mediated liquid-solid growth of high aspect ratio aligned gold silicide nanowires on Si(110) substrates.

PubMed

Bhatta, Umananda M; Rath, Ashutosh; Dash, Jatis K; Ghatak, Jay; Yi-Feng, Lai; Liu, Chuan-Pu; Satyam, P V

2009-11-18

Silicon nanowires grown using the vapor-liquid-solid method are promising candidates for nanoelectronics applications. The nanowires grow from an Au-Si catalyst during silicon chemical vapor deposition. In this paper, the effect of temperature, oxide at the interface and substrate orientation on the nucleation and growth kinetics during formation of nanogold silicide structures is explained using an oxide mediated liquid-solid growth mechanism. Using real time in situ high temperature transmission electron microscopy (with 40 ms time resolution), we show the formation of high aspect ratio ( approximately 15.0) aligned gold silicide nanorods in the presence of native oxide at the interface during in situ annealing of gold thin films on Si(110) substrates. Steps observed in the growth rate and real time electron diffraction show the existence of liquid Au-Si nano-alloy structures on the surface besides the un-reacted gold nanostructures. These results might enable us to engineer the growth of nanowires and similar structures with an Au-Si alloy as a catalyst.

Developments toward an 18% efficient silicon solar cell

NASA Technical Reports Server (NTRS)

Meulenberg, A., Jr.

1983-01-01

Limitations to increased open-circuit voltage were identified and experimentally verified for 0.1 ohm-cm solar cells with heavily doped emitters. After major reduction in the dark current contribution from the metal-silicon interface of the grid contacts, the surface recombination velocity of the oxide-silicon interface of shallow junction solar cells is the limiting factor. In deep junction solar cells, where the junction field does not aid surface collection, the emitter bulk is the limiting factor. Singly-diffused, shallow junction cells have been fabricated with open circuit voltages in excess of 645 mV. Double-diffusion shallow and deep junctions cells have displayed voltages above 650 mV. MIS solar cells formed on 0.1 ohm-cm substrates have exibited the lowest dark currents produced in the course of the contract work.

Kapitza thermal resistance studied by high-frequency photothermal radiometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horny, Nicolas; Chirtoc, Mihai; Hamaoui, Georges

2016-07-18

Kapitza thermal resistance is determined using high-frequency photothermal radiometry (PTR) extended for modulation up to 10 MHz. Interfaces between 50 nm thick titanium coatings and silicon or stainless steel substrates are studied. In the used configuration, the PTR signal is not sensitive to the thermal conductivity of the film nor to its optical absorption coefficient, thus the Kapitza resistance is directly determined from single thermal parameter fits. Results of thermal resistances show the significant influence of the nature of the substrate, as well as of the presence of free electrons at the interface.

The XPS depth profiling and tribological characterization of ion-plated gold on various metals

NASA Technical Reports Server (NTRS)

Miyoshi, K.; Spalvins, T.; Buckley, D. H.

1983-01-01

Friction properties were measured with a gold film; the graded interface between gold and nickel substrate; and the nickel substrate. All sliding was conducted against hard silicon carbide pins in two processes. In the adhesive process, friction arises primarily from adhesion between sliding surfaces. In the abrasion process, friction occurs as a result of the hard pin sliding against the film, indenting into it, and plowing a series of grooves. Copper and 440 C stainless steel substrates were also used. Results indicate that the friction related to both adhesion and abrasion is influenced by coating depth. The trends in friction behavior as a function of film depth are, however, just the opposite. The graded interface exhibited the highest adhesion and friction, while the graded interface resulted in the lowest abrasion and friction. The coefficient of friction due to abrasion is inversely related to the hardness. The greater the hardness of the surface, the lower is the abrasion and friction. The microhardness in the graded interface exhibited the highest hardness due to an alloy hardening effect. Almost no graded interface between the vapor-deposited gold film and the substrates was detected.

Key Durability Issues with Mullite-Based Environmental Barrier Coatings for Si-Based Ceramics

NASA Technical Reports Server (NTRS)

Lee, Kang N.

1999-01-01

Plasma-sprayed mullite (3Al2O3 central dot 2SiO2) and mullite/yttria-stabilized-zirconia (YSZ) dual layer coatings have been developed to protect silicon-based ceramics from environmental attack. Mullite-based coating systems show excellent durability in air. However, in combustion environments, corrosive species such as molten salt or water vapor penetrate through cracks in the coating and attack the Si-based ceramics along the interface, Thus modification of the coating system for enhanced crack-resistance is necessary for long-term durability in combustion environments. Other key durability issues include interfacial contamination and coating/substrate bonding. Interfacial contamination leads to enhanced oxidation and interfacial pore formation, while weak coating/substrate bonding leads to rapid attack of the interface by corrosive species, both of which can cause premature failure of the coating. Interfacial contamination can be minimized by limiting impurities in coating and substrate materials. The interface may be modified to improve the coating/substrate bond.

Key Durability Issues with Mullite-Based Environmental Barrier Coatings for Si-Based Ceramics

NASA Technical Reports Server (NTRS)

Lee, Kang N.

2000-01-01

Plasma-sprayed mullite (3Al2O3.2SiO2) and mullite/yttria-stabilized-zirconia (YSZ) dual layer coatings have been developed to protect silicon -based ceramics from environmental attack. Mullite-based coating systems show excellent durability in air. However, in combustion environments, corrosive species such as molten salt or water vapor penetrate through cracks in the coating and attack the Si-based ceramics along the interface. Thus the modification of the coating system for enhanced crack-resistance is necessary for long-term durability in combustion environments. Other key durability issues include interfacial contamination and coating/substrate bonding. Interfacial contamination leads to enhanced oxidation and interfacial pore formation, while a weak coating/substrate bonding leads to rapid attack of the interface by corrosive species, both of which can cause a premature failure of the coating. Interfacial contamination can be minimized by limiting impurities in coating and substrate materials. The interface may be modified to improve the coating/substrate bond.

Friction and hardness of gold films deposited by ion plating and evaporation

NASA Technical Reports Server (NTRS)

Miyoshi, K.; Spalvins, T.; Buckley, D. H.

1983-01-01

Sliding friction experiments were conducted with ion-plated and vapor-deposited gold films on various substrates in contact with a 0.025-mm-radius spherical silicon carbide rider in mineral oil. Hardness measurements were also made to examine the hardness depth profile of the coated gold on the substrate. The results indicate that the hardness is influenced by the depth of the gold coating from the surface. The hardness increases with an increase in the depth. The hardness is also related to the composition gradient in the graded interface between the gold coating and the substrate. The graded interface exhibited the highest hardness resulting from an alloy hardening effect. The coefficient of friction is inversely related to the hardness, namely, the load carrying capacity of the surface. The greater the hardness that the metal surface possesses, the lower is the coefficient of friction. The graded interface exhibited the lowest coefficient of friction.

Soft X-ray multilayers produced by sputtering and molecular beam epitaxy (MBE) - Substrate and interfacial roughness

NASA Astrophysics Data System (ADS)

Kearney, Patrick A.; Slaughter, J. M.; Powers, K. D.; Falco, Charles M.

1988-01-01

Roughness measurements were made on uncoated silicon wafers and float glass using a WYKO TOPO-3D phase shifting interferometry, and the results are reported. The wafers are found to be slightly smoother than the flat glass. The effects of different cleaning methods and of the deposition of silicon 'buffer layers' on substrate roughness are examined. An acid cleaning method is described which gives more consistent results than detergent cleaning. Healing of the roughness due to sputtered silicon buffer layers was not observed on the length scale probed by the WYKO. Sputtered multilayers are characterized using both the WYKO interferometer and low-angle X-ray diffraction in order to yield information about the roughness of the top surface and of the multilayer interfaces. Preliminary results on film growth using molecular beam epitaxy are also presented.

Radiation Hardened Silicon-on-Insulator Structures with N+ Ion Modified Buried SiO2 Layer

NASA Astrophysics Data System (ADS)

Tyschenko, I. E.; Popov, V. P.

2009-12-01

Radiation-resistant silicon-on-insulator structures were produced by N+ ion implantation into thermally grown SiO2 film and subsequent hydrogen transfer of the Si layer to the nitrogen-implanted substrate under conditions of vacuum wafer bonding. Accumulation of the carriers in the buried SiO2 was investigated as a function of fluence of nitrogen ions in the range (1-6)×1015 cm2 and as a function of total radiation dose ranging from 104 to 107 rad (Si). It was found that the charge generated near the nitrided bonding interface was reduced by a factor of four compared to the thermal SiO2/Si interface.

Whiskerless Schottky diode

NASA Technical Reports Server (NTRS)

Bishop, William L. (Inventor); Mcleod, Kathleen A. (Inventor); Mattauch, Robert J. (Inventor)

1991-01-01

A Schottky diode for millimeter and submillimeter wave applications is comprised of a multi-layered structure including active layers of gallium arsenide on a semi-insulating gallium arsenide substrate with first and second insulating layers of silicon dioxide on the active layers of gallium arsenide. An ohmic contact pad lays on the silicon dioxide layers. An anode is formed in a window which is in and through the silicon dioxide layers. An elongated contact finger extends from the pad to the anode and a trench, preferably a transverse channel or trench of predetermined width, is formed in the active layers of the diode structure under the contact finger. The channel extends through the active layers to or substantially to the interface of the semi-insulating gallium arsenide substrate and the adjacent gallium arsenide layer which constitutes a buffer layer. Such a structure minimizes the effect of the major source of shunt capacitance by interrupting the current path between the conductive layers beneath the anode contact pad and the ohmic contact. Other embodiments of the diode may substitute various insulating or semi-insulating materials for the silicon dioxide, various semi-conductors for the active layers of gallium arsenide, and other materials for the substrate, which may be insulating or semi-insulating.

Graded Index Silicon Geranium on Lattice Matched Silicon Geranium Semiconductor Alloy

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor); Elliott, James R., Jr. (Inventor); Stoakley, Diane M. (Inventor)

2009-01-01

A lattice matched silicon germanium (SiGe) semiconductive alloy is formed when a {111} crystal plane of a cubic diamond structure SiGe is grown on the {0001} C-plane of a single crystalline Al2O3 substrate such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,-1,0> orientation of the {0001} C-plane. A lattice match between the substrate and the SiGe is achieved by using a SiGe composition that is 0.7223 atomic percent silicon and 0.2777 atomic percent germanium. A layer of Si(1-x), ,Ge(x) is formed on the cubic diamond structure SiGe. The value of X (i) defines an atomic percent of germanium satisfying 0.2277

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.

PubMed

Zhang, Liangliang; Guo, Yuzheng; Hassan, Vinayak Vishwanath; Tang, Kechao; Foad, Majeed A; Woicik, Joseph C; Pianetta, Piero; Robertson, John; McIntyre, Paul C

2016-07-27

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.

Effects of argon addition on a-CNx film deposition by hot carbon filament chemical vapor deposition

NASA Astrophysics Data System (ADS)

Watanabe, Yoshihisa; Aono, Masami; Yamazaki, Ayumi; Kitazawa, Nobuaki; Nakamura, Yoshikazu

2002-07-01

Using a carbon filament which supplies carbon and heat, amorphous carbon nitride (a-CNx) films were prepared on Si (100) substrates by hot filament chemical vapor deposition. Deposition was performed in a low-pressure atmosphere of pure nitrogen and a gas mixture of nitrogen and argon. Effects of argon additions to the nitrogen atmosphere on the film microstructure and interface composition between the film and substrate were studied by field-emission scanning electron microscopy (FESEM) and x-ray photoelectron spectroscopy (XPS). FESEM observations reveal that the film prepared in a pure nitrogen atmosphere has uniform nucleation and a densely packed columnar pieces structure. The film prepared in the nitrogen and argon gas mixture exhibits preferential nucleation and a tapered structure with macroscopic voids. Depth analyses using XPS reveal that the film prepared in pure nitrogen possesses a broad interface, which includes silicon carbide as well as a-CNx, whereas a sharp interface is discerned in the film prepared in the mixed nitrogen and argon gas. We observed that silicon carbide formation is suppressed by an argon addition to the nitrogen atmosphere during deposition. copyright 2002 American Vacuum Society.

Chemical structure of interfaces

NASA Technical Reports Server (NTRS)

Grunthaner, F. J.

1985-01-01

The interfacial structure of silicon/dielectric and silicon/metal systems is particularly amenable to analysis using a combination of surface spectroscopies together with a variety of chemical structures of Si/SiO2, Si/SiO2Si3N4, Si/Si2N2O, Si/SiO2/Al, and Si/Native Oxide interfaces using high resolution (0.350 eV FWHM) X ray photoelectron spectroscopy. The general structure of these dielectric interfaces entails a monolayer chemical transition layer at the Si/dielectric boundary. Amorphous Si substrates show a wide variety of hydrogenated Si and Si(OH) sub x states that are not observed in thermal oxidation of single crystal material. Extended SiO2 layers greater than 8 A in thickness are shown to be stoichiometric SiO2, but to exhibit a wide variety of local network structures. In the nitrogen containing systems, an approach to stoichiometric oxynitride compounds with interesting impurity and electron trapping properties are seen. In native oxides, substantial topographical nonuniformity in oxide thickness and composition are found. Analysis of metal/oxide interfacial layers is accomplished by analytical removal of the Si substrate by UHV XeF2 dry etching methods.

Enhancement of phonon backscattering due to confinement of ballistic phonon pathways in silicon as studied with a microfabricated phonon spectrometer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Otelaja, O. O.; Robinson, R. D., E-mail: rdr82@cornell.edu

2015-10-26

In this work, the mechanism for enhanced phonon backscattering in silicon is investigated. An understanding of phonon propagation through substrates has implications for engineering heat flow at the nanoscale, for understanding sources of decoherence in quantum systems, and for realizing efficient phonon-mediated particle detectors. In these systems, phonons that backscatter from the bottom of substrates, within the crystal or from interfaces, often contribute to the overall detector signal. We utilize a microscale phonon spectrometer, comprising superconducting tunnel junction emitters and detectors, to specifically probe phonon backscattering in silicon substrates (∼500 μm thick). By etching phonon “enhancers” or deep trenches (∼90 μm) aroundmore » the detectors, we show that the backscattered signal level increases by a factor of ∼2 for two enhancers versus one enhancer. Using a geometric analysis of the phonon pathways, we show that the mechanism of the backscattered phonon enhancement is due to confinement of the ballistic phonon pathways and increased scattering off the enhancer walls. Our result is applicable to the geometric design and patterning of substrates that are employed in phonon-mediated detection devices.« less

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Demaurex, Bénédicte, E-mail: benedicte.demaurex@epfl.ch; Bartlome, Richard; Seif, Johannes P.

2014-08-07

Low-temperature (≤200 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-enhanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems not only frommore » the growth conditions but also from unintentional contamination of the reactor. Based on our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.« less

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

DOE PAGES

Demaurex, Bénédicte; Bartlome, Richard; Seif, Johannes P.; ...

2014-08-05

Low-temperature (≤ 180 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-ehanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems notmore » only from the growth conditions but also from unintentional contamination of the reactor. As a result of our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.« less

Characterization of mechanical properties of hydroxyapatite-silicon-multi walled carbon nano tubes composite coatings synthesized by EPD on NiTi alloys for biomedical application.

PubMed

Khalili, Vida; Khalil-Allafi, Jafar; Sengstock, Christina; Motemani, Yahya; Paulsen, Alexander; Frenzel, Jan; Eggeler, Gunther; Köller, Manfred

2016-06-01

Release of Ni(1+) ions from NiTi alloy into tissue environment, biological response on the surface of NiTi and the allergic reaction of atopic people towards Ni are challengeable issues for biomedical application. In this study, composite coatings of hydroxyapatite-silicon multi walled carbon nano-tubes with 20wt% Silicon and 1wt% multi walled carbon nano-tubes of HA were deposited on a NiTi substrate using electrophoretic methods. The SEM images of coated samples exhibit a continuous and compact morphology for hydroxyapatite-silicon and hydroxyapatite-silicon-multi walled carbon nano-tubes coatings. Nano-indentation analysis on different locations of coatings represents the highest elastic modulus (45.8GPa) for HA-Si-MWCNTs which is between the elastic modulus of NiTi substrate (66.5GPa) and bone tissue (≈30GPa). This results in decrease of stress gradient on coating-substrate-bone interfaces during performance. The results of nano-scratch analysis show the highest critical distance of delamination (2.5mm) and normal load before failure (837mN) as well as highest critical contact pressure for hydroxyapatite-silicon-multi walled carbon nano-tubes coating. The cell culture results show that human mesenchymal stem cells are able to adhere and proliferate on the pure hydroxyapatite and composite coatings. The presence of both silicon and multi walled carbon nano-tubes (CS3) in the hydroxyapatite coating induce more adherence of viable human mesenchymal stem cells in contrast to the HA coated samples with only silicon (CS2). These results make hydroxyapatite-silicon-multi walled carbon nano-tubes a promising composite coating for future bone implant application. Copyright © 2016 Elsevier Ltd. All rights reserved.

Epitaxial Reactor Development for Growth of Silicon-on-Insulator Devices.

DTIC Science & Technology

1987-04-01

emision from substrate reflected from interface 40 Constructive interference condition 2tc= n X / 1 * Destrictive interference condition 2tD= (2n+1) X...combinations of growth conditions resulted in no oxide growth on the original silicon wafer. Growths occurred for Si:O molecular ratios higher than 1:1...growth rates occurred at 1050 0 C with water vapor at 1250 cc/min and silane at 50 cc/min. These results are shown in Table 6. The molecular ratio was 2:1

Improved growth of GaN layers on ultra thin silicon nitride/Si (1 1 1) by RF-MBE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, Mahesh; Roul, Basanta; Central Research Laboratory, Bharat Electronics, Bangalore 560013

High-quality GaN epilayers were grown on Si (1 1 1) substrates by molecular beam epitaxy using a new growth process sequence which involved a substrate nitridation at low temperatures, annealing at high temperatures, followed by nitridation at high temperatures, deposition of a low-temperature buffer layer, and a high-temperature overgrowth. The material quality of the GaN films was also investigated as a function of nitridation time and temperature. Crystallinity and surface roughness of GaN was found to improve when the Si substrate was treated under the new growth process sequence. Micro-Raman and photoluminescence (PL) measurement results indicate that the GaN filmmore » grown by the new process sequence has less tensile stress and optically good. The surface and interface structures of an ultra thin silicon nitride film grown on the Si surface are investigated by core-level photoelectron spectroscopy and it clearly indicates that the quality of silicon nitride notably affects the properties of GaN growth.« less

Rapid Grafting of Azido-labeled Oligo(ethylene glycol)s onto an Alkynyl-terminated Monolayer on Non-oxidized Silicon via Microwave-assisted “Click” Reaction

PubMed Central

Li, Yan; Wang, Jun; Cai, Chengzhi

2011-01-01

Microwave (MW) irradiation was used for the grafting of azido-labeled oligo(ethylene oxide) (OEG) on alkynyl-terminated non-oxidized silicon substrates via copper-catalyzed “click” reaction. The “clickable” monolayers were prepared by photografting of an α,ω-alkynene, where the alkynyl terminus was protected by a trimethylgermanyl (TMG) group, onto hydrogen-terminated Si(111) surfaces. X-ray photoelectron spectroscopy (XPS) was primarily employed to characterize the monolayers, and the data obtained were utilized to calculate the surface density of the TMG-alkynyl-functionalized substrate. MW-assisted one-pot deprotection/click reaction was optimized on the surfaces using azido-tagged OEG derivatives. Using MW instead of conventional heating led to a substantial improvement on the rate of the reaction while suppressing the oxidation of the silicon interface and OEG degradation. The antifouling property of the resulting substrates was evaluated using fibrinogen as a model protein. Results show that the OEG-modification reduced the protein adsorption by >90%. PMID:21306165

Ion-beam mixed ultra-thin cobalt suicide (CoSi2) films by cobalt sputtering and rapid thermal annealing

NASA Astrophysics Data System (ADS)

Kal, S.; Kasko, I.; Ryssel, H.

1995-10-01

The influence of ion-beam mixing on ultra-thin cobalt silicide (CoSi2) formation was investigated by characterizing the ion-beam mixed and unmixed CoSi2 films. A Ge+ ion-implantation through the Co film prior to silicidation causes an interface mixing of the cobalt film with the silicon substrate and results in improved silicide-to-silicon interface roughness. Rapid thermal annealing was used to form Ge+ ion mixed and unmixed thin CoSi2 layer from 10 nm sputter deposited Co film. The silicide films were characterized by secondary neutral mass spectroscopy, x-ray diffraction, tunneling electron microscopy (TEM), Rutherford backscattering, and sheet resistance measurements. The experi-mental results indicate that the final rapid thermal annealing temperature should not exceed 800°C for thin (<50 nm) CoSi2 preparation. A comparison of the plan-view and cross-section TEM micrographs of the ion-beam mixed and unmixed CoSi2 films reveals that Ge+ ion mixing (45 keV, 1 × 1015 cm-2) produces homogeneous silicide with smooth silicide-to-silicon interface.

Study program to develop and evaluate die and container materials for the growth of silicon ribbons. [for development of low cost solar cells

NASA Technical Reports Server (NTRS)

Addington, L. A.; Ownby, P. D.; Yu, B. B.; Barsoum, M. W.; Romero, H. V.; Zealer, B. G.

1979-01-01

The development and evaluation of proprietary coatings of pure silicon carbide, silicon nitride, and aluminum nitride on less pure hot pressed substrates of the respective ceramic materials, is described. Silicon sessile drop experiments were performed on coated test specimens under controlled oxygen partial pressure. Prior to testing, X-ray diffraction and SEM characterization was performed. The reaction interfaces were characterized after testing with optical and scanning electron microscopy and Auger electron spectroscopy. Increasing the oxygen partial pressure was found to increase the molten silicon contact angle, apparently because adsorbed oxygen lowers the solid-vapor interfacial free energy. It was also found that adsorbed oxygen increased the degree of attack of molten silicon upon the chemical vapor deposited coatings. Cost projections show that reasonably priced, coated, molten silicon resistant refractory material shapes are obtainable.

Electrical response of electron selective atomic layer deposited TiO2‑x heterocontacts on crystalline silicon substrates

NASA Astrophysics Data System (ADS)

Ahiboz, Doğuşcan; Nasser, Hisham; Aygün, Ezgi; Bek, Alpan; Turan, Raşit

2018-04-01

Integration of oxygen deficient sub-stoichiometric titanium dioxide (TiO2‑x) thin films as the electron transporting-hole blocking layer in solar cell designs are expected to reduce fabrication costs by eliminating high temperature processes while maintaining high conversion efficiencies. In this paper, we conducted a study to reveal the electrical properties of TiO2‑x thin films grown on crystalline silicon (c-Si) substrates by atomic layer deposition (ALD) technique. Effect of ALD substrate temperature, post deposition annealing, and doping type of the c-Si substrate on the interface states and TiO2‑x bulk properties were extracted by performing admittance (C-V, G-V) and current-voltage (J-V) measurements. Moreover, the asymmetry in C-V and J-V measurements between the p-n type and n-n TiO2‑x-c-Si heterojunction types were examined and the electron transport selectivity of TiO2‑x was revealed.

Self-organized nickel nanoparticles on nanostructured silicon substrate intermediated by a titanium oxynitride (TiNxOy) interface

NASA Astrophysics Data System (ADS)

Morales, M.; Droppa, R., Jr.; de Mello, S. R. S.; Figueroa, C. A.; Zanatta, A. R.; Alvarez, F.

2018-01-01

In this work we report an experimental approach by combining in situ sequential top-down and bottom-up processes to induce the organization of nanosized nickel particles. The top-down process consists in xenon ion bombardment of a crystalline silicon substrate to generate a pattern, followed by depositing a ˜15 nm titanium oxynitride thin film to act as a metallic diffusion barrier. Then, metallic nanoparticles are deposited by argon ion sputtering a pure nickel target, and the sample is annealed to promote the organization of the nickel nanoparticles (a bottom-up process). According to the experimental results, the surface pattern and the substrate biaxial surface strain are the driving forces behind the alignment and organization of the nickel nanoparticles. Moreover, the ratio between the F of metallic atoms arriving at the substrate relative to its surface diffusion mobility determines the nucleation regime of the nickel nanoparticles. These features are presented and discussed considering the existing technical literature on the subject.

A novel route to prepare a multilayer system via the combination of interface-mediated catalytic chain transfer polymerization and thiol-ene click chemistry.

PubMed

Zengin, Adem; Caykara, Tuncer

2017-05-01

Herein, we have designed a novel multilayer system composed of poly(methyl methacrylate) [poly(MMA)] brush, biotin, streptavidin and protein-A on a silicon substrate to attach onanti-immunoglobulin G (anti-IgG). poly(MMA) brush with vinyl end-group was first synthesized by the interface-mediated catalytic chain transfer polymerization. The brush was then modified with cysteamine molecules to generate the polymer chains with amine end-group via a thiol-ene click chemistry. The amine end-groups of poly(MMA) chains were also modified with biotin units to ensure selective connection points for streptavidin molecules. Finally, a multilayer system on the silicon substrate was formed by using streptavidin and protein-A molecules, respectively. This multilayer system was employed to attach anti-IgG molecules in a highly oriented manner and provide anti-IgG molecular functional configuration on the multilayer. High reproducibility of the amount of anti-IgG adsorption and homogeneous anti-IgG adsorption layer on the silicon surface could be provided by this multilayer system. The multilayer system with protein A may be opened the door for designing an efficient immunoassay protein chip. Copyright © 2017. Published by Elsevier B.V.

Broadband omnidirectional antireflection coating based on subwavelength surface Mie resonators

PubMed Central

Spinelli, P.; Verschuuren, M.A.; Polman, A.

2012-01-01

Reflection is a natural phenomenon that occurs when light passes the interface between materials with different refractive index. In many applications, such as solar cells or photodetectors, reflection is an unwanted loss process. Many ways to reduce reflection from a substrate have been investigated so far, including dielectric interference coatings, surface texturing, adiabatic index matching and scattering from plasmonic nanoparticles. Here we present an entirely new concept that suppresses the reflection of light from a silicon surface over a broad spectral range. A two-dimensional periodic array of subwavelength silicon nanocylinders designed to possess strongly substrate-coupled Mie resonances yields almost zero total reflectance over the entire spectral range from the ultraviolet to the near-infrared. This new antireflection concept relies on the strong forward scattering that occurs when a scattering structure is placed in close proximity to a high-index substrate with a high optical density of states. PMID:22353722

Fabrication of (NH4)2S passivated GaAs metal-insulator-semiconductor devices using low-frequency plasma-enhanced chemical vapor deposition

NASA Astrophysics Data System (ADS)

Jaouad, A.; Aimez, V.; Aktik, Ç.; Bellatreche, K.; Souifi, A.

2004-05-01

Metal-insulator-semiconductor (MIS) capacitors were fabricated on n-GaAs(100) substrate using (NH4)2S surface passivation and low-frequency plasma-enhanced chemical vapor deposited silicon nitride as gate insulators. The electrical properties of the fabricated MIS capacitors were analyzed using high-frequency capacitance-voltage and conductance-voltage measurements. The high concentration of hydrogen present during low-frequency plasma deposition of silicon nitride enhances the passivation of GaAs surface, leading to the unpinning of the Fermi level and to a good modulation of the surface potential by gate voltage. The electrical properties of the insulator-semiconductor interface are improved after annealing at 450 °C for 60 s, as a significant reduction of the interface fixed charges and of the interface states density is put into evidence. The minimum interface states density was found to be about 3×1011 cm-2 eV-1, as estimated by the Terman method. .

Feasibility study for future implantable neural-silicon interface devices.

PubMed

Al-Armaghany, Allann; Yu, Bo; Mak, Terrence; Tong, Kin-Fai; Sun, Yihe

2011-01-01

The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures.

Feasibility of Electrochemical Deposition of Nickel/Silicon Carbide Fibers Composites over Nickel Superalloys

NASA Astrophysics Data System (ADS)

Ambrosio, E. P.; Abdul Karim, M. R.; Pavese, M.; Biamino, S.; Badini, C.; Fino, P.

2017-05-01

Nickel superalloys are typical materials used for the hot parts of engines in aircraft and space vehicles. They are very important in this field as they offer high-temperature mechanical strength together with a good resistance to oxidation and corrosion. Due to high-temperature buckling phenomena, reinforcement of the nickel superalloy might be needed to increase stiffness. For this reason, it was thought to investigate the possibility of producing composite materials that might improve properties of the metal at high temperature. The composite material was produced by using electrochemical deposition method in which a composite with nickel matrix and long silicon carbide fibers was deposited over the nickel superalloy. The substrate was Inconel 718, and monofilament continuous silicon carbide fibers were chosen as reinforcement. Chemical compatibility was studied between Inconel 718 and the reinforcing fibers, with fibers both in an uncoated condition, and coated with carbon or carbon/titanium diboride. Both theoretical calculations and experiments were conducted, which suggested the use of a carbon coating over the fibers and a buffer layer of nickel to avoid unwanted reactions between the substrate and silicon carbide. Deposition was then performed, and this demonstrated the practical feasibility of the process. Yield strength was measured to detect the onset of interface debonding between the substrate and the composite layer.

Directional Etching of Silicon by Silver Nanostructures

NASA Astrophysics Data System (ADS)

Sharma, Pradeep; Wang, Yuh-Lin

2011-02-01

We report directional etching of nanostructures (nanochannels and nanotrenches) into the Si(100) substrates in aqueous HF and H2O2 solution by lithographically defined Ag patterns (nanoparticles, nanorods, and nanorings). The Effect of Ag/Si interface oxide on the directional etching has been studied by etching Ag/SiOx/Si samples of known interface oxide thickness. Based on high resolution transmission electron microscopy (HRTEM) imaging and TEM-energy dispersive X-ray (EDX) spectra of the Ag/Si interfaces, we propose that maintenance of the sub-nanometer oxide at the Ag/Si interfaces and Ag-Si interaction are the key factors which regulate the directional etching of Si.

Epitaxial Growth of beta-Silicon Carbide (SiC) on a Compliant Substrate via Chemical Vapor Deposition (CVD)

NASA Technical Reports Server (NTRS)

Mitchell, Sharanda L.

1996-01-01

Many lattice defects have been attributed to the lattice mismatch and the difference in the thermal coefficient of expansion between SiC and silicon (Si). Stacking faults, twins and antiphase boundaries are some of the lattice defects found in these SiC films. These defects may be a partial cause of the disappointing performance reported for the prototype devices fabricated from beta-SiC films. The objective of this research is to relieve some of the thermal stress due to lattice mismatch when SiC is epitaxially grown on Si. The compliant substrate is a silicon membrane 2-4 microns thick. The CVD process includes the buffer layer which is grown at 1360 C followed by a very thin epitaxial growth of SiC. Then the temperature is raised to 1500 C for the subsequent growth of SiC. Since silicon melts at 1415 C, the SiC will be grown on molten Silicon which is absorbed by a porous graphite susceptor eliminating the SiC/Si interface. We suspect that this buffer layer will yield less stressed material to help in the epitaxial growth of SiC.

Thermal transport across metal silicide-silicon interfaces: An experimental comparison between epitaxial and nonepitaxial interfaces

NASA Astrophysics Data System (ADS)

Ye, Ning; Feser, Joseph P.; Sadasivam, Sridhar; Fisher, Timothy S.; Wang, Tianshi; Ni, Chaoying; Janotti, Anderson

2017-02-01

Silicides are used extensively in nano- and microdevices due to their low electrical resistivity, low contact resistance to silicon, and their process compatibility. In this work, the thermal interface conductance of TiSi2, CoSi2, NiSi, and PtSi are studied using time-domain thermoreflectance. Exploiting the fact that most silicides formed on Si(111) substrates grow epitaxially, while most silicides on Si(100) do not, we study the effect of epitaxy, and show that for a wide variety of interfaces there is no dependence of interface conductance on the detailed structure of the interface. In particular, there is no difference in the thermal interface conductance between epitaxial and nonepitaxial silicide/silicon interfaces, nor between epitaxial interfaces with different interface orientations. While these silicide-based interfaces yield the highest reported interface conductances of any known interface with silicon, none of the interfaces studied are found to operate close to the phonon radiation limit, indicating that phonon transmission coefficients are nonunity in all cases and yet remain insensitive to interfacial structure. In the case of CoSi2, a comparison is made with detailed computational models using (1) full-dispersion diffuse mismatch modeling (DMM) including the effect of near-interfacial strain, and (2) an atomistic Green' function (AGF) approach that integrates near-interface changes in the interatomic force constants obtained through density functional perturbation theory. Above 100 K, the AGF approach significantly underpredicts interface conductance suggesting that energy transport does not occur purely by coherent transmission of phonons, even for epitaxial interfaces. The full-dispersion DMM closely predicts the experimentally observed interface conductances for CoSi2, NiSi, and TiSi2 interfaces, while it remains an open question whether inelastic scattering, cross-interfacial electron-phonon coupling, or other mechanisms could also account for the high-temperature behavior. The effect of degenerate semiconductor dopant concentration on metal-semiconductor thermal interface conductance was also investigated with the result that we have found no dependencies of the thermal interface conductances up to (n or p type) ≈1 ×1019 cm-3, indicating that there is no significant direct electronic transport and no transport effects that depend on long-range metal-semiconductor band alignment.

Detailed study of SiOxNy:H/Si interface properties for high quality surface passivation of crystalline silicon

NASA Astrophysics Data System (ADS)

Dong, Peng; Lei, Dong; Yu, Xuegong; Huang, Chunlai; Li, Mo; Dai, Gang; Zhang, Jian; Yang, Deren

2018-01-01

In this work, we present a detailed study on the interface and passivation properties of the hydrogenated silicon oxynitride (SiOxNy:H) on the crystalline silicon (c-Si) and their correlations with the film composition. The SiOxNy:H films were synthesized by plasma enhanced chemical vapor deposition (PECVD) at various N2O flow rates, which results in different film composition, in particular the different H-related bonds, such as Sisbnd H and Nsbnd H bonds. Fourier transform infrared spectroscopy measurements show that the concentration of Nsbnd H bonds increases with the N2O flows from 0 to 30 sccm, while drops below the detection limit at N2O flows above 30 sccm. This changing trend of Nsbnd H bonds correlates well with the evolution of carrier lifetime of silicon substrate passivated by SiOxNy:H film, indicating the crucial role of Nsbnd H bonds in surface passivation. It is inferred that during the film deposition and forming gas anneal (FGA) a considerable amount of hydrogen atoms are liberated from the weak type of Nsbnd H bonds rather than Sisbnd H bonds, and then passivate the dangling bonds at the interface, thus resulting in the significant reduction of interface state density and the improved passivation quality. In detail, the interface state density is reduced from ∼5 × 1012 to ∼2 × 1012 cm-2 eV-1 after the FGA, as derived from the high frequency capacitance-voltage (Csbnd V) measurements.

Polytype Stability and Microstructural Characterization of Silicon Carbide Epitaxial Films Grown on [ {11}overline{{2}} {0} ]- and [0001]-Oriented Silicon Carbide Substrates

NASA Astrophysics Data System (ADS)

Bishop, S. M.; Reynolds, C. L.; Liliental-Weber, Z.; Uprety, Y.; Zhu, J.; Wang, D.; Park, M.; Molstad, J. C.; Barnhardt, D. E.; Shrivastava, A.; Sudarshan, T. S.; Davis, R. F.

2007-04-01

The polytype and surface and defect microstructure of epitaxial layers grown on 4H( {11}overline{{2}} {0} ), 4H(0001) on-axis, 4H(0001) 8° off-axis, and 6H(0001) on-axis substrates have been investigated. High-resolution x-ray diffraction (XRD) revealed the epitaxial layers on 4H( {11}overline{{2}} {0} ) and 4H(0001) 8° off-axis to have the 4H-SiC (silicon carbide) polytype, while the 3C-SiC polytype was identified for epitaxial layers on 4H(0001) and 6H(0001) on-axis substrates. Cathodoluminescence (CL), Raman spectroscopy, and transmission electron microscopy (TEM) confirmed these results. The epitaxial surface of 4H( {11}overline{{2}} {0} ) films was specular with a roughness of 0.16-nm root-mean-square (RMS), in contrast to the surfaces of the other epitaxial layer-substrate orientations, which contained curvilinear boundaries, growth pits (˜3 × 104 cm-2), triangular defects >100 μm, and significant step bunching. Molten KOH etching revealed large defect densities within 4H( {11}overline{{2}} {0} ) films that decreased with film thickness to ˜106 cm-2 at 2.5 μm, while cross-sectional TEM studies showed areas free of defects and an indistinguishable film-substrate interface for 4H( {11}overline{{2}} {0} ) epitaxial layers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dong, Rui; Moore, Logan; Ocola, Leonidas E.

The mask-free patterning technique is employed to fabricate arrays of MoS2 and WS2 structures on silicon and graphene substrates with quality interfaces. By depositing precursor inks with the AFM cantilevers and subsequent heat treatment in the CVD furnace, it is demonstrated that MoS2 and WS2 structures can be formed on graphene surfaces at predefined device architectures.

Unidirectional endotaxial cobalt di-silicide nanowires on Si(110) substrates

NASA Astrophysics Data System (ADS)

Mahato, J. C.; Das, Debolina; Banu, Nasrin; Satpati, Biswarup; Dev, B. N.

2017-10-01

Self-organized growth of well-ordered endotaxial silicide nanowires (NWs) on clean Si(110) surfaces has been investigated by in situ scanning tunneling microscopy (STM) and transmission electron microscopy (TEM). Co deposition on clean Si(110) reconstructed surfaces at ∼600 °C produces unidirectional CoSi2 NWs by reaction of cobalt with the hot silicon substrate. STM investigations reveal four major types of distinct NWs, all growing along the [-110] in-plane direction except one type growing along the in-plane [-113] direction. There are also some nanodots. The cross-sectional TEM measurements show that the unidirectional NWs are of two types—flat-top and ridged. The NWs grow not only on the substrate but also into the substrate. CoSi2 in flat top NWs are in the same crystallographic orientation as the substrate Si and the buried interfaces between CoSi2 and Si are A-type. In the ridged NWs CoSi2 and Si are in different crystallographic orientations and the interfaces are B-type. The ridged NWs are in general wider and grow deeper into the substrate.

Unidirectional endotaxial cobalt di-silicide nanowires on Si(110) substrates.

PubMed

Mahato, J C; Das, Debolina; Banu, Nasrin; Satpati, Biswarup; Dev, B N

2017-10-20

Self-organized growth of well-ordered endotaxial silicide nanowires (NWs) on clean Si(110) surfaces has been investigated by in situ scanning tunneling microscopy (STM) and transmission electron microscopy (TEM). Co deposition on clean Si(110) reconstructed surfaces at ∼600 °C produces unidirectional CoSi 2 NWs by reaction of cobalt with the hot silicon substrate. STM investigations reveal four major types of distinct NWs, all growing along the [-110] in-plane direction except one type growing along the in-plane [-113] direction. There are also some nanodots. The cross-sectional TEM measurements show that the unidirectional NWs are of two types-flat-top and ridged. The NWs grow not only on the substrate but also into the substrate. CoSi 2 in flat top NWs are in the same crystallographic orientation as the substrate Si and the buried interfaces between CoSi 2 and Si are A-type. In the ridged NWs CoSi 2 and Si are in different crystallographic orientations and the interfaces are B-type. The ridged NWs are in general wider and grow deeper into the substrate.

Silica substrate or portion formed from oxidation of monocrystalline silicon

DOEpatents

Matzke, Carolyn M.; Rieger, Dennis J.; Ellis, Robert V.

2003-07-15

A method is disclosed for forming an inclusion-free silica substrate using a monocrystalline silicon substrate as the starting material and oxidizing the silicon substrate to convert it entirely to silica. The oxidation process is performed from both major surfaces of the silicon substrate using a conventional high-pressure oxidation system. The resulting product is an amorphous silica substrate which is expected to have superior etching characteristics for microfabrication than conventional fused silica substrates. The present invention can also be used to convert only a portion of a monocrystalline silicon substrate to silica by masking the silicon substrate and locally thinning a portion the silicon substrate prior to converting the silicon portion entirely to silica. In this case, the silica formed by oxidizing the thinned portion of the silicon substrate can be used, for example, as a window to provide optical access through the silicon substrate.

Temperature Dependence of Diffusion and Reaction at a Pd/SiC Contact

NASA Technical Reports Server (NTRS)

Shi, D.T.; Lu, W. J.; Bryant, E.; Elshot, K.; Lafate, K.; Chen, H.; Burger, A.; Collins, W. E.

1998-01-01

Schottky diodes of Palladium/SiC are good candidates for hydrogen and hydrocarbon gas sensors at elevated temperature. The detection sensibility of the diodes has been found heavily temperature dependent. In this work, emphasis has been put on the understanding of changes of physical and chemical properties of the Schottky diodes with variation of temperature. Schottky diodes were made by depositing ultra-thin palladium films onto silicon carbide substrates. The electrical and chemical properties of Pd/SiC Schottky contacts were studied by XPS and AES at different annealing temperatures. No significant change in the Schottky barrier height of the Pd/SiC contact was found in the temperature range of RT-400 C. However, both palladium diffused into SiC and silicon migrated into palladium thin film as well as onto surface were observed at room temperature. The formation of palladium compounds at the Pd/SiC interface was also observed. Both diffusion and reaction at the Pd/SiC interface became significant at 300 C and higher temperature. In addition, silicon oxide was found also at the interface of the Pd/SiC contact at high temperature. In this report, the mechanism of diffusion and reaction at the Pd/SiC interface will be discussed along with experimental approaches.

Determination of band alignment at two-dimensional MoS2/Si van der Waals heterojunction

NASA Astrophysics Data System (ADS)

Goel, Neeraj; Kumar, Rahul; Mishra, Monu; Gupta, Govind; Kumar, Mahesh

2018-06-01

To understand the different mechanism occurring at the MoS2-silicon interface, we have fabricated a MoS2/Si heterojunction by exfoliating MoS2 on top of the silicon substrate. Raman spectroscopy and atomic force microscopy (AFM) measurement expose the signature of few-layers in the deposited MoS2 flake. Herein, the temperature dependence of the energy barrier and carrier density at the MoS2/Si heterojunction has been extensively investigated. Furthermore, to study band alignment at the MoS2/Si interface, we have calculated a valence band offset of 0.66 ± 0.17 eV and a conduction band offset of 0.42 ± 0.17 eV using X-ray and Ultraviolet photoelectron spectroscopy. We determined a type-II band alignment at the interface which is very conducive for the transport of photoexcited carriers. As a proof-of-concept application, we extend our analysis of the photovoltaic behavior of the MoS2/Si heterojunction. This work provides not only a comparative study between MoS2/p-Si and MoS2/n-Si heterojunctions but also paves the way to engineer the properties of the interface for the future integration of MoS2 with silicon.

Thermal load leveling during silicon crystal growth from a melt using anisotropic materials

DOEpatents

Carlson, Frederick M.; Helenbrook, Brian T.

2016-10-11

An apparatus for growing a silicon crystal substrate comprising a heat source, an anisotropic thermal load leveling component, a crucible, and a cold plate component is disclosed. The anisotropic thermal load leveling component possesses a high thermal conductivity and may be positioned atop the heat source to be operative to even-out temperature and heat flux variations emanating from the heat source. The crucible may be operative to contain molten silicon in which the top surface of the molten silicon may be defined as a growth interface. The crucible may be substantially surrounded by the anisotropic thermal load leveling component. The cold plate component may be positioned above the crucible to be operative with the anisotropic thermal load leveling component and heat source to maintain a uniform heat flux at the growth surface of the molten silicon.

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

NASA Astrophysics Data System (ADS)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

A study of trends and techniques for space base electronics

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Wade, T. E.; Gassaway, J. D.

1979-01-01

The use of dry processing and alternate dielectrics for processing wafers is reported. A two dimensional modeling program was written for the simulation of short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide-silicon interface. In solving current continuity equation, the program does not converge. However, solving the two dimensional Poisson equation for the potential distribution was achieved. The status of other 2D MOSFET simulation programs are summarized.

Real-time monitoring of surface-initiated atom transfer radical polymerization using silicon photonic microring resonators: implications for combinatorial screening of polymer brush growth conditions.

PubMed

Limpoco, F Ted; Bailey, Ryan C

2011-09-28

We directly monitor in parallel and in real time the temporal profiles of polymer brushes simultaneously grown via multiple ATRP reaction conditions on a single substrate using arrays of silicon photonic microring resonators. In addition to probing relative polymerization rates, we show the ability to evaluate the dynamic properties of the in situ grown polymers. This presents a powerful new platform for studying modified interfaces that may allow for the combinatorial optimization of surface-initiated polymerization conditions.

Role of the inversion layer on the charge injection in silicon nanocrystal multilayered light emitting devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tondini, S.; Dipartimento di Fisica, Informatica e Matematica, Università di Modena e Reggio Emilia, Via Campi 213/a, 41125 Modena; Pucker, G.

2016-09-07

The role of the inversion layer on injection and recombination phenomena in light emitting diodes (LEDs) is here studied on a multilayer (ML) structure of silicon nanocrystals (Si-NCs) embedded in SiO{sub 2}. Two Si-NC LEDs, which are similar for the active material but different in the fabrication process, elucidate the role of the non-radiative recombination rates at the ML/substrate interface. By studying current- and capacitance-voltage characteristics as well as electroluminescence spectra and time-resolved electroluminescence under pulsed and alternating bias pumping scheme in both the devices, we are able to ascribe the different experimental results to an efficient or inefficient minoritymore » carrier (electron) supply by the p-type substrate in the metal oxide semiconductor LEDs.« less

Observation of interface defects in thermally oxidized SiC using positron annihilation

NASA Astrophysics Data System (ADS)

Dekker, James; Saarinen, Kimmo; Ólafsson, Halldór; Sveinbjörnsson, Einar Ö.

2003-03-01

Positron annihilation has been applied to study thermally oxidized 4H- and 6H-SiC. The SiC/SiO2 interface is found to contain a high density of open-volume defects. The positron trapping at the interface defects correlates with the charge of the interface determined by capacitance-voltage experiments. For oxides grown on n-SiC substrates, the positron annihilation characteristics at these defects are nearly indistinguishable from those of a silicon/oxide interface, with no discernable contribution from C-related bonds or carbon clusters. These results indicate that those defects at the SiC/oxide interface, which are visible to positrons, are similar to those at the Si/oxide interface. The positron annihilation characteristics suggest that these defects are vacancies surrounded by oxygen atoms.

Grafting of functionalized polymer on porous silicon surface using Grignard reagent

NASA Astrophysics Data System (ADS)

Tighilt, F.-Z.; Belhousse, S.; Sam, S.; Hamdani, K.; Lasmi, K.; Chazalviel, J. N.; Gabouze, N.

2017-11-01

Recently, considerable attention has been paid to the manipulation and the control of the physicochemical properties of porous silicon surfaces because of their crucial importance to the modern microelectronics industry. Hybrid structures consisting of deposited polymer on porous silicon surfaces are important to applications in microelectronics, photovoltaics and sensors (Ensafi et al., 2016; Kashyout et al., 2015; Osorio et al.; 2015; Hejjo et al., 2002) [1-4]. In many cases, the polymer can provide excellent mechanical and chemical protection of the substrate, changes the electrochemical interface characteristics of the substrate, and provides new ways to the functionalization of porous silicon surfaces for molecular recognition and sensing. In this work, porous silicon surface was modified by anodic treatment in ethynylmagnesium bromide electrolyte leading to the formation of a polymeric layer bearing some bromine substituents. Subsequently, the formed polymer is functionalized with amine molecules containing functional groups (carboxylic acid or pyridine) by a substitution reaction between bromine sites and amine groups (Hofmann reaction). The chemical composition of the modified porous silicon surfaces was investigated and the grafting of polymeric chains and functional groups on the porous silicon surface was confirmed by Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS) which displayed the principal characteristic peaks attributed to the different functional groups. Furthermore, the surface of the material was examined by scanning electron microscopy (SEM).

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Single crystal functional oxides on silicon

PubMed Central

Bakaul, Saidur Rahman; Serrao, Claudy Rayan; Lee, Michelle; Yeung, Chun Wing; Sarker, Asis; Hsu, Shang-Lin; Yadav, Ajay Kumar; Dedon, Liv; You, Long; Khan, Asif Islam; Clarkson, James David; Hu, Chenming; Ramesh, Ramamoorthy; Salahuddin, Sayeef

2016-01-01

Single-crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism and so on that have the potential for completely new electronic applications. Direct synthesis of such oxides on silicon remains challenging because of the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces. Here we report integration of thin (down to one unit cell) single crystalline, complex oxide films onto silicon substrates, by epitaxial transfer at room temperature. In a field-effect transistor using a transferred lead zirconate titanate layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single-crystal functional oxides on-demand on silicon. PMID:26853112

Research and development of plasma sprayed tungsten coating on graphite and copper substrates

NASA Astrophysics Data System (ADS)

Liu, Xiang; Zhang, Fu; Tao, Shunyan; Cao, Yunzhen; Xu, Zengyu; Liu, Yong; Noda, N.

2007-06-01

Vacuum plasma sprayed tungsten coating on graphite and copper substrates has been prepared. VPS-W coated graphite has multilayered silicon and tungsten interface pre-deposited by physical vapor deposition (PVD) and VPS-W coated copper has graded transition interlayer. VPS-W coating was characterized, and then the high heat flux properties of the coating were examined. Experimental results indicated that both VPS-W coated graphite and VPS-W coated copper could endure 1000 cycles without visible failure under a heat flux of approximately 5 MW/m2 absorbed power density and 5 s pulse duration. A comparison between the present VPS-W coated graphite and VPS-W coated carbon fiber composite (CX-2002U) with Re interface made by Plansee Aktiengesllshaft was carried out. Results show that both Re and Si are suitable as intermediate layer for tungsten coating on carbon substrates.

Stability of the tungsten diselenide and silicon carbide heterostructure against high energy proton exposure

NASA Astrophysics Data System (ADS)

Walker, Roger C.; Shi, Tan; Jariwala, Bhakti; Jovanovic, Igor; Robinson, Joshua A.

2017-10-01

Single layers of tungsten diselenide (WSe2) can be used to construct ultra-thin, high-performance electronics. Additionally, there has been considerable progress in controlled and direct growth of single layers on various substrates. Based on these results, high-quality WSe2-based devices that approach the limit of physical thickness are now possible. Such devices could be useful for space applications, but understanding how high-energy radiation impacts the properties of WSe2 and the WSe2/substrate interface has been lacking. In this work, we compare the stability against high energy proton radiation of WSe2 and silicon carbide (SiC) heterostructures generated by mechanical exfoliation of WSe2 flakes and by direct growth of WSe2 via metal-organic chemical vapor deposition (MOCVD). These two techniques produce WSe2/SiC heterostructures with distinct differences due to interface states generated during the MOCVD growth process. This difference carries over to differences in band alignment from interface states and the ultra-thin nature of the MOCVD-grown material. Both heterostructures are not susceptible to proton-induced charging up to a dose of 1016 protons/cm2, as measured via shifts in the binding energy of core shell electrons and a decrease in the valence band offset. Furthermore, the MOCVD-grown material is less affected by the proton exposure due to its ultra-thin nature and a greater interaction with the substrate. These combined effects show that the directly grown material is suitable for multi-year use in space, provided that high quality devices can be fabricated from it.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Ultra-thin distributed Bragg reflectors via stacked single-crystal silicon nanomembranes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Minkyu; Seo, Jung-Hun; Lee, Jaeseong

2015-05-04

In this paper, we report ultra-thin distributed Bragg reflectors (DBRs) via stacked single-crystal silicon (Si) nanomembranes (NMs). Mesh hole-free single-crystal Si NMs were released from a Si-on-insulator substrate and transferred to quartz and Si substrates. Thermal oxidation was applied to the transferred Si NM to form high-quality SiO{sub 2} and thus a Si/SiO{sub 2} pair with uniform and precisely controlled thicknesses. The Si/SiO{sub 2} layers, as smooth as epitaxial grown layers, minimize scattering loss at the interface and in between the layers. As a result, a reflection of 99.8% at the wavelength range from 1350 nm to 1650 nm can be measuredmore » from a 2.5-pair DBR on a quartz substrate and 3-pair DBR on a Si substrate with thickness of 0.87 μm and 1.14 μm, respectively. The high reflection, ultra-thin DBRs developed here, which can be applied to almost any devices and materials, holds potential for application in high performance optoelectronic devices and photonics applications.« less

Transfer of InP epilayers by wafer bonding

NASA Astrophysics Data System (ADS)

Hjort, Klas

2004-08-01

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

Sub-10 nm Silicon Nanopillar Fabrication Using Fast and Brushless Thermal Assembly of PS-b-PDMS Diblock Copolymer.

PubMed

Garnier, Jérôme; Arias-Zapata, Javier; Marconot, Olivier; Arnaud, Sandrine; Böhme, Sophie; Girardot, Cécile; Buttard, Denis; Zelsmann, Marc

2016-04-20

A new approach to obtaining spherical nanodomains using polystyrene-block-polydimethylsiloxane (PS-b-PDMS) is proposed. To reduce drastically the process time, we blended a copolymer with cylindrical morphology with a PS homopolymer. Adding PS homopolymer into a low-molar-mass cylindrical morphology PS-b-PDMS system drives it toward a spherical morphology. Besides, by controlling the as-spun state, spherical PDMS nanodomains could be kept and thermally arranged. This PS-homopolymer addition allows not only an efficient, purely thermal arrangement process of spheres but also the ability to work directly on nontreated silicon substrates. Indeed, as shown by STEM measurements, no PS brush surface treatment was necessary in our study to avoid a PDMS wetting layer at the interface with the Si substrate. Our approach was compared to a sphere-forming diblock copolymer, which needs a longer thermal annealing. Furthermore, GISAXS measurements provided complete information on PDMS sphere features. Excellent long-range order spherical microdomains were therefore produced on flat surfaces and inside graphoepitaxy trenches with a period of 21 nm, as were in-plane spheres with a diameter of 8 nm with a 15 min thermal annealing. Finally, direct plasma-etching transfer into the silicon substrate was demonstrated, and 20 nm high silicon nanopillars were obtained, which are very promising results for various nanopatterning applications.

Transmission electron microscopy characterization of the interfacial structure of a galvanized dual-phase steel

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aslam, I., E-mail: ia31@msstate.edu

2016-10-15

Site-specific studies were carried out to characterize the interface of a galvanized dual-phase (DP) steel. Focused ion beam (FIB) was used to prepare specimens in the interface region (~ 100 nm thick) between the coating and the substrate. Transmission electron microscopy (TEM), scanning TEM (STEM), and high resolution TEM (HRTEM) were performed to resolve the phases and the structures at the interface between the zinc (Zn) coating and the steel substrate. The STEM and TEM results showed that a continuous manganese oxide (MnO) film with a thickness of ~ 20 nm was present on the surface of the substrate whilemore » no silicon (Si) oxides were resolved. Internal oxide particles were observed as well in the sub-surface region. Despite the presence of the continuous oxide film, a well-developed inhibition layer was observed right on top of the oxide film. The inhibition layer has a thickness of ~ 100 nm. Possible mechanisms for the growth of the inhibition layer were discussed. - Highlights: •Site-specific examinations were performed on the Zn/steel interface. •Continuous external MnO oxides (20 nm) were observed at the interface. •No Si oxides were observed at the interface. •Internal oxide particles were distributed in the subsurface. •A continuous inhibition layer grew on top of the external oxides.« less

In-depth porosity control of mesoporous silicon layers by an anodization current adjustment

NASA Astrophysics Data System (ADS)

Lascaud, J.; Defforge, T.; Certon, D.; Valente, D.; Gautier, G.

2017-12-01

The formation of thick mesoporous silicon layers in P+-type substrates leads to an increase in the porosity from the surface to the interface with silicon. The adjustment of the current density during the electrochemical etching of porous silicon is an intuitive way to control the layer in-depth porosity. The duration and the current density during the anodization were varied to empirically model porosity variations with layer thickness and build a database. Current density profiles were extracted from the model in order to etch layer with in-depth control porosity. As a proof of principle, an 80 μm-thick porous silicon multilayer was synthetized with decreasing porosities from 55% to 35%. The results show that the assessment of the in-depth porosity could be significantly enhanced by taking into account the pure chemical etching of the layer in the hydrofluoric acid-based electrolyte.

Theory of Covalent Adsorbate Frontier Orbital Energies on Functionalized Light-Absorbing Semiconductor Surfaces.

PubMed

Yu, Min; Doak, Peter; Tamblyn, Isaac; Neaton, Jeffrey B

2013-05-16

Functional hybrid interfaces between organic molecules and semiconductors are central to many emerging information and solar energy conversion technologies. Here we demonstrate a general, empirical parameter-free approach for computing and understanding frontier orbital energies - or redox levels - of a broad class of covalently bonded organic-semiconductor surfaces. We develop this framework in the context of specific density functional theory (DFT) and many-body perturbation theory calculations, within the GW approximation, of an exemplar interface, thiophene-functionalized silicon (111). Through detailed calculations taking into account structural and binding energetics of mixed-monolayers consisting of both covalently attached thiophene and hydrogen, chlorine, methyl, and other passivating groups, we quantify the impact of coverage, nonlocal polarization, and interface dipole effects on the alignment of the thiophene frontier orbital energies with the silicon band edges. For thiophene adsorbate frontier orbital energies, we observe significant corrections to standard DFT (∼1 eV), including large nonlocal electrostatic polarization effects (∼1.6 eV). Importantly, both results can be rationalized from knowledge of the electronic structure of the isolated thiophene molecule and silicon substrate systems. Silicon band edge energies are predicted to vary by more than 2.5 eV, while molecular orbital energies stay similar, with the different functional groups studied, suggesting the prospect of tuning energy alignment over a wide range for photoelectrochemistry and other applications.

High fluence swift heavy ion structure modification of the SiO2/Si interface and gate insulator in 65 nm MOSFETs

NASA Astrophysics Data System (ADS)

Ma, Yao; Gao, Bo; Gong, Min; Willis, Maureen; Yang, Zhimei; Guan, Mingyue; Li, Yun

2017-04-01

In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO2/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO2 and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.

Growth and characterization of molecular beam epitaxial GaAs layers on porous silicon

NASA Technical Reports Server (NTRS)

Lin, T. L.; Liu, J. K.; Sadwick, L.; Wang, K. L.; Kao, Y. C.

1987-01-01

GaAs layers have been grown on porous silicon (PS) substrates with good crystallinity by molecular beam epitaxy. In spite of the surface irregularity of PS substrates, no surface morphology deterioration was observed on epitaxial GaAs overlayers. A 10-percent Rutherford backscattering spectroscopy minimum channeling yield for GaAs-on-PS layers as compared to 16 percent for GaAs-on-Si layers grown under the same condition indicates a possible improvement of crystallinity when GaAs is grown on PS. Transmission electron microscopy reveals that the dominant defects in the GaAs-on-PS layers are microtwins and stacking faults, which originate from the GaAs/PS interface. GaAs is found to penetrate into the PS layers. n-type GaAs/p-type PS heterojunction diodes were fabricated with good rectifying characteristics.

Buffer-eliminated, charge-neutral epitaxial graphene on oxidized 4H-SiC (0001) surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sirikumara, Hansika I., E-mail: hansi.sirikumara@siu.edu; Jayasekera, Thushari, E-mail: thushari@siu.edu

Buffer-eliminated, charge-neutral epitaxial graphene (EG) is important to enhance its potential in device applications. Using the first principles Density Functional Theory calculations, we investigated the effect of oxidation on the electronic and structural properties of EG on 4H-SiC (0001) surface. Our investigation reveals that the buffer layer decouples from the substrate in the presence of both silicate and silicon oxy-nitride at the interface, and the resultant monolayer EG is charge-neutral in both cases. The interface at 4H-SiC/silicate/EG is characterized by surface dangling electrons, which opens up another route for further engineering EG on 4H-SiC. Dangling electron-free 4H-SiC/silicon oxy-nitride/EG is idealmore » for achieving charge-neutral EG.« less

Process for the deposition of high temperature stress and oxidation resistant coatings on silicon-based substrates

DOEpatents

Sarin, V.K.

1991-07-30

A process is disclosed for depositing a high temperature stress and oxidation resistant coating on a silicon nitride- or silicon carbide-based substrate body. A gas mixture is passed over the substrate at about 900--1500 C and about 1 torr to about ambient pressure. The gas mixture includes one or more halide vapors with other suitable reactant gases. The partial pressure ratios, flow rates, and process times are sufficient to deposit a continuous, fully dense, adherent coating. The halide and other reactant gases are gradually varied during deposition so that the coating is a graded coating of at least two layers. Each layer is a graded layer changing in composition from the material over which it is deposited to the material of the layer and further to the material, if any, deposited thereon, so that no clearly defined compositional interfaces exist. The gases and their partial pressures are varied according to a predetermined time schedule and the halide and other reactant gases are selected so that the layers include (a) an adherent, continuous intermediate layer about 0.5-20 microns thick of an aluminum nitride or an aluminum oxynitride material, over and chemically bonded to the substrate body, and (b) an adherent, continuous first outer layer about 0.5-900 microns thick including an oxide of aluminum or zirconium over and chemically bonded to the intermediate layer.

Process for the deposition of high temperature stress and oxidation resistant coatings on silicon-based substrates

DOEpatents

Sarin, Vinod K.

1991-01-01

A process for depositing a high temperature stress and oxidation resistant coating on a silicon nitride- or silicon carbide-based substrate body. A gas mixture is passed over the substrate at about 900.degree.-1500.degree. C. and about 1 torr to about ambient pressure. The gas mixture includes one or more halide vapors with other suitable reactant gases. The partial pressure ratios, flow rates, and process times are sufficient to deposit a continuous, fully dense, adherent coating. The halide and other reactant gases are gradually varied during deposition so that the coating is a graded coating of at least two layers. Each layer is a graded layer changing in composition from the material over which it is deposited to the material of the layer and further to the material, if any, deposited thereon, so that no clearly defined compositional interfaces exist. The gases and their partial pressures are varied according to a predetermined time schedule and the halide and other reactant gases are selected so that the layers include (a) an adherent, continuous intermediate layer about 0.5-20 microns thick of an aluminum nitride or an aluminum oxynitride material, over and chemically bonded to the substrate body, and (b) an adherent, continuous first outer layer about 0.5-900 microns thick including an oxide of aluminum or zirconium over and chemically bonded to the intermediate layer.

Optimization of amino group density on surfaces of titanium dioxide nanoparticles covalently bonded to a silicone substrate for antibacterial and cell adhesion activities.

PubMed

Okada, Masahiro; Yasuda, Shoji; Kimura, Tsuyoshi; Iwasaki, Mitsunobu; Ito, Seishiro; Kishida, Akio; Furuzono, Tsutomu

2006-01-01

A composite consisting of titanium dioxide (TiO2) particle, the surface of which was modified with amino groups, and a silicone substrate through covalent bonding at their interface was developed, and antibacterial and cell adhesion activities of the composite were evaluated. The density of the amino groups on the TiO2 particle surface was controlled by the reaction time of the modification reaction. The degradation rate of CH3CHO in the presence of the TiO2 particles under UV irradiation decreased with an increase in the amino group density on the TiO2 surface. On the other hand, the number of L929 cells adhering on the TiO2/silicone composite increased with an increase in the amino group density. From the above two results, the optimum density of amino groups for both photoreactivity and cell adhesiveness was estimated to be 2.0-4.0 molecules/nm2. The optimum amino group-modified TiO2/silicone composite sheet (amino group density, 3.0 molecules/nm2) showed an effective antibacterial activity for Escherichia coli bacteria under UV irradiation. (c) 2005 Wiley Periodicals, Inc

Interface effects on calculated defect levels for oxide defects

NASA Astrophysics Data System (ADS)

Edwards, Arthur; Barnaby, Hugh; Schultz, Peter; Pineda, Andrew

2014-03-01

Density functional theory (DFT) has had impressive recent success predicting defect levels in insulators and semiconductors [Schultz and von Lillienfeld, 2009]. Such success requires care in accounting for long-range electrostatic effects. Recently, Komsa and Pasquarello have started to address this problem in systems with interfaces. We report a multiscale technique for calculating electrostatic energies for charged defects in oxide of the metal-oxide-silicon (MOS) system, but where account is taken of substrate doping density, oxide thickness, and gate bias. We use device modeling to calculate electric fields for a point charge a fixed distance from the interface, and used the field to numerically calculate the long-range electrostatic interactions. We find, for example, that defect levels in the oxide do depend on both the magnitude and the polarity the substrate doping density. Furthermore, below 20 Å, oxide thickness also has significant effects. So, transferring results directly from bulk calculations leads to inaccuracies up to 0.5 eV- half of the silicon band gap. We will present trends in defect levels as a function of device parameters. We show that these results explain previous experimental results, and we comment on their potential impact on models for NBTI. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the United States Department of Energy's National Nuclear Security Administration under co.

Selective electrical interfaces with the nervous system.

PubMed

Rutten, Wim L C

2002-01-01

To achieve selective electrical interfacing to the neural system it is necessary to approach neuronal elements on a scale of micrometers. This necessitates microtechnology fabrication and introduces the interdisciplinary field of neurotechnology, lying at the juncture of neuroscience with microtechnology. The neuroelectronic interface occurs where the membrane of a cell soma or axon meets a metal microelectrode surface. The seal between these may be narrow or may be leaky. In the latter case the surrounding volume conductor becomes part of the interface. Electrode design for successful interfacing, either for stimulation or recording, requires good understanding of membrane phenomena, natural and evoked action potential generation, volume conduction, and electrode behavior. Penetrating multimicroelectrodes have been produced as one-, two-, and three-dimensional arrays, mainly in silicon, glass, and metal microtechnology. Cuff electrodes circumvent a nerve; their selectivity aims at fascicles more than at nerve fibers. Other types of electrodes are regenerating sieves and cone-ingrowth electrodes. The latter may play a role in brain-computer interfaces. Planar substrate-embedded electrode arrays with cultured neural cells on top are used to study the activity and plasticity of developing neural networks. They also serve as substrates for future so-called cultured probes.

Enhanced red photoluminescence of quartz by silicon nanocrystals thin film deposition

NASA Astrophysics Data System (ADS)

Momeni, A.; Pourgolestani, M.; Taheri, M.; Mansour, N.

2018-03-01

The room-temperature photoluminescence properties of silicon nanocrystals (SiNCs) thin film on a quartz substrate were investigated, which presents the red emission enhancement of quartz. We show that the photoluminescence intensity of quartz, in the wavelength range of 640-700 nm, can be enhanced as much as 15-fold in the presence of the SiNCs thin film. Our results reveal that the defect states at the SiNCs/SiO2 interface can be excited more efficiently by indirect excitation via the SiNCs, leading to the prominent red photoluminescence enhancement under the photo-excitation in the range of 440-470 nm. This work suggests a simple pathway to improve silicon-based light emitting devices for photonic applications.

Electrical Characterization of Amorphous Silicon MIS-Based Structures for HIT Solar Cell Applications.

PubMed

García, Héctor; Castán, Helena; Dueñas, Salvador; Bailón, Luis; García-Hernansanz, Rodrigo; Olea, Javier; Del Prado, Álvaro; Mártil, Ignacio

2016-12-01

A complete electrical characterization of hydrogenated amorphous silicon layers (a-Si:H) deposited on crystalline silicon (c-Si) substrates by electron cyclotron resonance chemical vapor deposition (ECR-CVD) was carried out. These structures are of interest for photovoltaic applications. Different growth temperatures between 30 and 200 °C were used. A rapid thermal annealing in forming gas atmosphere at 200 °C during 10 min was applied after the metallization process. The evolution of interfacial state density with the deposition temperature indicates a better interface passivation at higher growth temperatures. However, in these cases, an important contribution of slow states is detected as well. Thus, using intermediate growth temperatures (100-150 °C) might be the best choice.

Electrical Characterization of Amorphous Silicon MIS-Based Structures for HIT Solar Cell Applications

NASA Astrophysics Data System (ADS)

García, Héctor; Castán, Helena; Dueñas, Salvador; Bailón, Luis; García-Hernansanz, Rodrigo; Olea, Javier; del Prado, Álvaro; Mártil, Ignacio

2016-07-01

A complete electrical characterization of hydrogenated amorphous silicon layers (a-Si:H) deposited on crystalline silicon (c-Si) substrates by electron cyclotron resonance chemical vapor deposition (ECR-CVD) was carried out. These structures are of interest for photovoltaic applications. Different growth temperatures between 30 and 200 °C were used. A rapid thermal annealing in forming gas atmosphere at 200 °C during 10 min was applied after the metallization process. The evolution of interfacial state density with the deposition temperature indicates a better interface passivation at higher growth temperatures. However, in these cases, an important contribution of slow states is detected as well. Thus, using intermediate growth temperatures (100-150 °C) might be the best choice.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics.

III/V nano ridge structures for optical applications on patterned 300 mm silicon substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kunert, B.; Guo, W.; Mols, Y.

We report on an integration approach of III/V nano ridges on patterned silicon (Si) wafers by metal organic vapor phase epitaxy (MOVPE). Trenches of different widths (≤500 nm) were processed in a silicon oxide (SiO{sub 2}) layer on top of a 300 mm (001) Si substrate. The MOVPE growth conditions were chosen in a way to guarantee an efficient defect trapping within narrow trenches and to form a box shaped ridge with increased III/V volume when growing out of the trench. Compressively strained InGaAs/GaAs multi-quantum wells with 19% indium were deposited on top of the fully relaxed GaAs ridges as an activemore » material for optical applications. Transmission electron microcopy investigation shows that very flat quantum well (QW) interfaces were realized. A clear defect trapping inside the trenches is observed whereas the ridge material is free of threading dislocations with only a very low density of planar defects. Pronounced QW photoluminescence (PL) is detected from different ridge sizes at room temperature. The potential of these III/V nano ridges for laser integration on Si substrates is emphasized by the achieved ridge volume which could enable wave guidance and by the high crystal quality in line with the distinct PL.« less

On the Control of the Fixed Charge Densities in Al2O3-Based Silicon Surface Passivation Schemes.

PubMed

Simon, Daniel K; Jordan, Paul M; Mikolajick, Thomas; Dirnstorfer, Ingo

2015-12-30

A controlled field-effect passivation by a well-defined density of fixed charges is crucial for modern solar cell surface passivation schemes. Al2O3 nanolayers grown by atomic layer deposition contain negative fixed charges. Electrical measurements on slant-etched layers reveal that these charges are located within a 1 nm distance to the interface with the Si substrate. When inserting additional interface layers, the fixed charge density can be continuously adjusted from 3.5 × 10(12) cm(-2) (negative polarity) to 0.0 and up to 4.0 × 10(12) cm(-2) (positive polarity). A HfO2 interface layer of one or more monolayers reduces the negative fixed charges in Al2O3 to zero. The role of HfO2 is described as an inert spacer controlling the distance between Al2O3 and the Si substrate. It is suggested that this spacer alters the nonstoichiometric initial Al2O3 growth regime, which is responsible for the charge formation. On the basis of this charge-free HfO2/Al2O3 stack, negative or positive fixed charges can be formed by introducing additional thin Al2O3 or SiO2 layers between the Si substrate and this HfO2/Al2O3 capping layer. All stacks provide very good passivation of the silicon surface. The measured effective carrier lifetimes are between 1 and 30 ms. This charge control in Al2O3 nanolayers allows the construction of zero-fixed-charge passivation layers as well as layers with tailored fixed charge densities for future solar cell concepts and other field-effect based devices.

Spectroscopic Ellipsometry Studies of n-i-p Hydrogenated Amorphous Silicon Based Photovoltaic Devices

PubMed Central

Karki Gautam, Laxmi; Junda, Maxwell M.; Haneef, Hamna F.; Collins, Robert W.; Podraza, Nikolas J.

2016-01-01

Optimization of thin film photovoltaics (PV) relies on characterizing the optoelectronic and structural properties of each layer and correlating these properties with device performance. Growth evolution diagrams have been used to guide production of materials with good optoelectronic properties in the full hydrogenated amorphous silicon (a-Si:H) PV device configuration. The nucleation and evolution of crystallites forming from the amorphous phase were studied using in situ near-infrared to ultraviolet spectroscopic ellipsometry during growth of films prepared as a function of hydrogen to reactive gas flow ratio R = [H2]/[SiH4]. In conjunction with higher photon energy measurements, the presence and relative absorption strength of silicon-hydrogen infrared modes were measured by infrared extended ellipsometry measurements to gain insight into chemical bonding. Structural and optical models have been developed for the back reflector (BR) structure consisting of sputtered undoped zinc oxide (ZnO) on top of silver (Ag) coated glass substrates. Characterization of the free-carrier absorption properties in Ag and the ZnO + Ag interface as well as phonon modes in ZnO were also studied by spectroscopic ellipsometry. Measurements ranging from 0.04 to 5 eV were used to extract layer thicknesses, composition, and optical response in the form of complex dielectric function spectra (ε = ε1 + iε2) for Ag, ZnO, the ZnO + Ag interface, and undoped a-Si:H layer in a substrate n-i-p a-Si:H based PV device structure. PMID:28773255

Transmission electron microscopy characterization of the erbium silicide formation process using a Pt/Er stack on a silicon-on-insulator substrate.

PubMed

Łaszcz, A; Katcki, J; Ratajczak, J; Tang, Xiaohui; Dubois, E

2006-10-01

Very thin erbium silicide layers have been used as source and drain contacts to n-type Si in low Schottky barrier MOSFETs on silicon-on-insulator substrates. Erbium silicide is formed by a solid-state reaction between the metal and silicon during annealing. The influence of annealing temperature (450 degrees C, 525 degrees C and 600 degrees C) on the formation of an erbium silicide layer in the Pt/Er/Si/SiO(2)/Si structure was analysed by means of cross-sectional transmission electron microscopy. The Si grains/interlayer formed at the interface and the presence of Si grains within the Er-related layer constitute proof that Si reacts with Er in the presence of a Pt top layer in the temperature range 450-600 degrees C. The process of silicide formation in the Pt/Er/Si structure differs from that in the Er/Si structure. At 600 degrees C, the Pt top layer vanishes and a (Pt-Er)Si(x) system is formed.

Surface-plasmon mediated total absorption of light into silicon.

PubMed

Yoon, Jae Woong; Park, Woo Jae; Lee, Kyu Jin; Song, Seok Ho; Magnusson, Robert

2011-10-10

We report surface-plasmon mediated total absorption of light into a silicon substrate. For an Au grating on Si, we experimentally show that a surface-plasmon polariton (SPP) excited on the air/Au interface leads to total absorption with a rate nearly 10 times larger than the ohmic damping rate of collectively oscillating free electrons in the Au film. Rigorous numerical simulations show that the SPP resonantly enhances forward diffraction of light to multiple orders of lossy waves in the Si substrate with reflection and ohmic absorption in the Au film being negligible. The measured reflection and phase spectra reveal a quantitative relation between the peak absorbance and the associated reflection phase change, implying a resonant interference contribution to this effect. An analytic model of a dissipative quasi-bound resonator provides a general formula for the resonant absorbance-phase relation in excellent agreement with the experimental results.

Partially Ionized Beam Deposition of Silicon-Dioxide and Aluminum Thin Films - Defects Generation.

NASA Astrophysics Data System (ADS)

Wong, Justin Wai-Chow

1987-09-01

Detect formation in SiO_2 and Al thin films and interfaces were studied using a partially ionized beam (PIB) deposition technique. The evaporated species (the deposition material) were partially ionized to give an ion/atom ratio of <=q0.1% and the substrate was biased at 0-5kV during the deposition. The results suggest that due to the ion bombardment, stoichiometric SiO_2 films can be deposited at a low substrate temperature (~300 ^circC) and low oxygen pressure (<=q10^{-4} Torr). Such deposition cannot be achieved using conventional evaporation-deposition techniques. However, traps and mobile ions were observed in the oxide and local melt-down was observed when a sufficiently high electric field was applied to the film. For the PIB Al deposition on the Si substrate, stable Al/Si Schottky contact was formed when the substrate bias was <=q1kV. For a substrate bias of 2.5kV, the capacitance of the Al/Si interface increased dramatically. A model of self-ion implantation with a p-n junction created by the Al^+ ion implantation was proposed and tested to explain the increase of the interface capacitance. Several deep level states at the Al/Si interface were observed using Deep Level Transient Spectroscopy (DLTS) technique when the film was deposited at a bias of 3kV. The PIB Al films deposited on the Si substrate showed unusually strong electromigration resistance under high current density operation. This phenomenon was explained by the highly oriented microstructure of the Al films created by the self-ion bombardment during deposition. These findings show that PIB has potential applications in a number of areas, including low temperature thin film deposition, and epitaxial growth of thin films in the microelectronics thin film industry.

Boundary layers of aqueous surfactant and block copolymer solutions against hydrophobic and hydrophilic solid surfaces

NASA Astrophysics Data System (ADS)

Steitz, Roland; Schemmel, Sebastian; Shi, Hongwei; Findenegg, Gerhard H.

2005-03-01

The boundary layer of aqueous surfactants and amphiphilic triblock copolymers against flat solid surfaces of different degrees of hydrophobicity was investigated by neutron reflectometry (NR), grazing incidence small angle neutron scattering (GISANS) and atomic force microscopy (AFM). Solid substrates of different hydrophobicities were prepared by appropriate surface treatment or by coating silicon wafers with polymer films of different chemical natures. For substrates coated with thin films (20-30 nm) of deuterated poly(styrene) (water contact angle \\theta_{\\mathrm {w}} \\approx 90^\\circ ), neutron reflectivity measurements on the polymer/water interface revealed a water depleted liquid boundary layer of 2-3 nm thickness and a density about 90% of the bulk water density. No pronounced depletion layer was found at the interface of water against a less hydrophobic polyelectrolyte coating (\\theta_{\\mathrm {w}} \\approx 63^\\circ ). It is believed that the observed depletion layer at the hydrophobic polymer/water interface is a precursor of the nanobubbles which have been observed by AFM at this interface. Decoration of the polymer coatings by adsorbed layers of nonionic CmEn surfactants improves their wettability by the aqueous phase at surfactant concentrations well below the critical micellar concentration (CMC) of the surfactant. Here, GISANS experiments conducted on the system SiO2/C8E4/D2O reveal that there is no preferred lateral organization of the C8E4 adsorption layers. For amphiphilic triblock copolymers (PEO-PPO-PEO) it is found that under equilibrium conditions they form solvent-swollen brushes both at the air/water and the solid/water interface. In the latter case, the brushes transform to uniform, dense layers after extensive rinsing with water and subsequent solvent evaporation. The primary adsorption layers maintain properties of the precursor brushes. In particular, their thickness scales with the number of ethylene oxide units (EO) of the block copolymer. In the case of dip-coating without subsequent rinsing, surface patterns of the presumably crystalline polymer on top of the primary adsorption layer develop upon drying under controlled conditions. The morphology depends mainly on the nominal surface coverage with the triblock copolymer. Similar morphologies are found on bare and polystyrene-coated silicon substrates, indicating that the surface patterning is mainly driven by segregation forces within the polymer layers and not by interactions with the substrate.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-03-21

A method is disclosed for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics. 7 figures.

Metallic coatings on silicon substrates, and methods of forming metallic coatings on silicon substrates

DOEpatents

Branagan, Daniel J [Idaho Falls, ID; Hyde, Timothy A [Idaho Falls, ID; Fincke, James R [Los Alamos, NM

2008-03-11

The invention includes methods of forming a metallic coating on a substrate which contains silicon. A metallic glass layer is formed over a silicon surface of the substrate. The invention includes methods of protecting a silicon substrate. The substrate is provided within a deposition chamber along with a deposition target. Material from the deposition target is deposited over at least a portion of the silicon substrate to form a protective layer or structure which contains metallic glass. The metallic glass comprises iron and one or more of B, Si, P and C. The invention includes structures which have a substrate containing silicon and a metallic layer over the substrate. The metallic layer contains less than or equal to about 2 weight % carbon and has a hardness of at least 9.2 GPa. The metallic layer can have an amorphous microstructure or can be devitrified to have a nanocrystalline microstructure.

Semiconductor to Metal Transition Characteristics of VO2/NiO Epitaxial Heterostructures Integrated with Si(100)

NASA Astrophysics Data System (ADS)

Molaei, Roya

The novel functionalities of Vanadium dioxide (VO2), such as, several orders of magnitude transition in resistivity and IR transmittance, provide the exciting opportunity for the development of next generation memory, sensor, and field-effect based devices. A critical issue in the development of practical devices based on metal oxides is the integration of high quality epitaxial oxide thin films with the existing silicon technology which is based on silicon (100) substrates. However, silicon is not suitable for epitaxial growth of oxides owing to its tendency to readily form an amorphous oxide layer or silicide at the film-substrate interface. The oxide films deposited directly on silicon exhibit poor crystallinity and are not suitable for device applications. To overcome this challenge, appropriate substrate templates must be developed for the growth of oxide thin films on silicon substrates. The primary objective of this dissertation was to develop an integration methodology of VO2 with Si (100) substrates so they could be used in "smart" sensor type of devices along with other multifunctional devices on the same silicon chip. This was achieved by using a NiO/c- YSZ template layer deposited in situ. It will be shown that if the deposition conditions are controlled properly. This approach was used to integrate VO 2 thin films with Si (100) substrates using pulsed laser deposition (PLD) technique. The deposition methodology of integrating VO2 thin films on silicon using various other template layers will also be discussed. Detailed epitaxial relationship of NiO/c-YSZ/Si(100) heterostructures as a template to growth of VO2 as well as were studied. We also were able to create a p-n junction within a single NiO epilayer through subsequent nanosecond laser annealing, as well as established a structure-property correlation in NiO/c-YSZ/Si(100) thin film epitaxial heterostructures with especial emphasis on the stoichiometry and crystallographic characteristics. NiO/c-YSZ/Si(100) heterostructures were used as template to grow fully relaxed VO2 thin films. The detailed x-ray diffraction, transmission electron microscopy (TEM), electrical characterization results for the deposited films will be presented. In the framework on domain matching epitaxy, epitaxial growth of VO2 (tetragonal crystal structure at growth temperature) on NiO has been explained. Our detailed phi-scan X-ray diffraction measurements corroborate our understanding of the epitaxial growth and in-plane atomic arrangements at the interface. It was observed that the transition characteristics (sharpness, over which electrical property changes are completed, amplitude, transition temperature, and hysteresis) are a strong function of microstructure, strain, and stoichiometry. We have shown that by the choosing the right template layer, strain in the VO2 thin films can be fully relaxed and near-bulk VO2 transition temperatures can be achieved. Finally, I will present my research work on modification of semiconductor-to-metal transition characteristics and effect on room temperature magnetic properties of VO2 thin films upon laser annealing. While the microstructure (epitaxy, crystalline quality etc.) and phase were preserved, we envisage these changes to occur as a result of introduction of oxygen vacancies upon laser treatment.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Structural Studies of the Initial Stages of Fluoride Epitaxy on Silicon and GERMANIUM(111)

NASA Astrophysics Data System (ADS)

Denlinger, Jonathan David

The epitaxial growth of ionic insulators on semiconductor substrates is of interest due to fundamental issues of interface bonding and structure as well as to potential technological applications. The initial stages of Group IIa fluoride insulator growth on (111) Si and Ge substrates by molecular beam epitaxy are studied with the in situ combination of X-ray Photoelectron Spectroscopy (XPS) and Diffraction (XPD). While XPS probes the electronic structure, XPD reveals atomic structure. In addition, low energy electron diffraction (LEED) is used to probe surface order and a separate study using X-ray standing wave (XSW) fluorescence reveals interface cation bonding sites. Following the formation of a chemically-reacted interface layer in CaF_2 epitaxy on Si(111), the morphology of the subsequent bulk layers is found to be dependent on substrate temperature and incident flux rate. At temperatures >=600 ^circC a transition from three -dimensional island formation at low flux to laminar growth at higher flux is observed with bulk- and interface-resolved XPD. At lower substrate temperatures, laminar growth is observed at all fluxes, but with different bulk nucleation behavior due to changes in the stoichiometry of the interface layer. This new observation of kinetic effects on the initial nucleation in CaF_2 epitaxy has important ramifications for the formation of thicker heterostructures for scientific or device applications. XPS and XPD are also used to identify for the first time, surface core-level species of Ca and F, and a secondary interface-shifted F Auger component arising from a second-layer site directly above interface-layer Ca atoms. The effects of lattice mismatch (from -3% to 8%) are investigated with various growths of Ca_{rm x}Sr _{rm 1-x}F_2 on Si and Ge (111) substrates. Triangulation of (111) and (220) XSW indicates a predominance of 3-fold hollow Sr bonding sites coexisting with 4-fold top sites for monolayers of SrF_2 on Si. XSW and LEED reveal a lateral discommensuration of the overlayer for lattice mismatches of >5% relative to the substrate. XPD also reveals a transition from single - to mixed-domains of overlayer crystallographic orientation for mismatches >=3.5%.

Effect of same-temperature GaN cap layer on the InGaN/GaN multiquantum well of green light-emitting diode on silicon substrate.

PubMed

Zheng, Changda; Wang, Li; Mo, Chunlan; Fang, Wenqing; Jiang, Fengyi

2013-01-01

GaN green LED was grown on Si (111) substrate by MOCVD. To enhance the quality of InGaN/GaN MQWs, same-temperature (ST) GaN protection layers with different thickness of 8 Å, 15 Å, and 30 Å were induced after the InGaN quantum wells (QWs) layer. Results show that a relative thicker cap layer is benefit to get InGaN QWs with higher In percent at fixed well temperature and obtain better QW/QB interface. As the cap thickness increases, the indium distribution becomes homogeneous as verified by fluorescence microscope (FLM). The interface of MQWs turns to be abrupt from XRD analysis. The intensity of photoluminescence (PL) spectrum is increased and the FWHM becomes narrow.

Manufacturing, assembling and packaging of miniaturized implants for neural prostheses and brain-machine interfaces

NASA Astrophysics Data System (ADS)

Stieglitz, Thomas

2009-05-01

Implantable medical devices to interface with muscles, peripheral nerves, and the brain have been developed for many applications over the last decades. They have been applied in fundamental neuroscientific studies as well as in diagnosis, therapy and rehabilitation in clinical practice. Success stories of these implants have been written with help of precision mechanics manufacturing techniques. Latest cutting edge research approaches to restore vision in blind persons and to develop an interface with the human brain as motor control interface, however, need more complex systems and larger scales of integration and higher degrees of miniaturization. Microsystems engineering offers adequate tools, methods, and materials but so far, no MEMS based active medical device has been transferred into clinical practice. Silicone rubber, polyimide, parylene as flexible materials and silicon and alumina (aluminum dioxide ceramics) as substrates and insulation or packaging materials, respectively, and precious metals as electrodes have to be combined to systems that do not harm the biological target structure and have to work reliably in a wet environment with ions and proteins. Here, different design, manufacturing and packaging paradigms will be presented and strengths and drawbacks will be discussed in close relation to the envisioned biological and medical applications.

On the cause of the flat-spot phenomenon observed in silicon solar cells at low temperatures and low intensities

NASA Technical Reports Server (NTRS)

Weizer, V. G.; Broder, J. D.; Brandhorst, H. W., Jr.; Forestieri, A. F.

1982-01-01

A model is presented that explains the "flat-spot" (FS) power loss phenomenon observed in silicon solar cells operating deep space (low temperature, low intensity) conditions. Evidence is presented suggesting that the effect is due to localized metallurgical interactions between the silicon substrate and the contact metallization. These reactions are shown to result in localized regions in which the PN junction is destroyed and replaced with a metal-semiconductor-like interface. The effects of thermal treatment, crystallographic orientation, junction depth, and metallurization are presented along with a method of preventing the effect through the suppression of vacancy formation at the free surface of the contact metallization. Preliminary data indicating the effectiveness of a TiN diffusion barrier in preventing the effect are also given.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Investigations of Si Thin Films as Anode of Lithium-Ion Batteries

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Qingliu; Shi, Bing; Bareño, Javier

Amorphous silicon thin films having various thicknesses were investigated as a negative electrode material for lithium-ion batteries. Electrochemical characterization of the 20 nm thick thin silicon film revealed a very low first cycle Coulombic efficiency, which can be attributed to the silicon oxide layer formed on both the surface of the as-deposited Si thin film and the interface between the Si and the substrate. Among the investigated films, the 100 nm Si thin film demonstrated the best performance in terms of first cycle efficiency and cycle life. Observations from scanning electron microscopy demonstrated that the generation of cracks was inevitablemore » in the cycled Si thin films, even as the thickness of the film was as little as 20 nm, which was not predicted by previous modeling work. However, the cycling performance of the 20 and 100 nm silicon thin films was not detrimentally affected by these cracks. The poor capacity retention of the 1 mu m silicon thin film was attributed to the delamination.« less

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

DOE PAGES

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio; ...

2017-11-14

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 10 4 cm -2), localized areas with a defect density > 10 5 cm -2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stackingmore » faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. In conclusion, the impact of the defects on material performance and substrate re-use is also discussed.« less

Micromachined silicon parallel acoustic delay lines as time-delayed ultrasound detector array for real-time photoacoustic tomography

NASA Astrophysics Data System (ADS)

Cho, Y.; Chang, C.-C.; Wang, L. V.; Zou, J.

2016-02-01

This paper reports the development of a new 16-channel parallel acoustic delay line (PADL) array for real-time photoacoustic tomography (PAT). The PADLs were directly fabricated from single-crystalline silicon substrates using deep reactive ion etching. Compared with other acoustic delay lines (e.g., optical fibers), the micromachined silicon PADLs offer higher acoustic transmission efficiency, smaller form factor, easier assembly, and mass production capability. To demonstrate its real-time photoacoustic imaging capability, the silicon PADL array was interfaced with one single-element ultrasonic transducer followed by one channel of data acquisition electronics to receive 16 channels of photoacoustic signals simultaneously. A PAT image of an optically-absorbing target embedded in an optically-scattering phantom was reconstructed, which matched well with the actual size of the imaged target. Because the silicon PADL array allows a signal-to-channel reduction ratio of 16:1, it could significantly simplify the design and construction of ultrasonic receivers for real-time PAT.

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 10 4 cm -2), localized areas with a defect density > 10 5 cm -2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stackingmore » faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. In conclusion, the impact of the defects on material performance and substrate re-use is also discussed.« less

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

NASA Astrophysics Data System (ADS)

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio; Jensen, Mallory Ann; Morishige, Ashley E.; Lai, Barry; Hao, Ruiying; Ravi, T. S.; Buonassisi, Tonio

2018-02-01

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 104 cm-2), localized areas with a defect density > 105 cm-2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stacking faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. The impact of the defects on material performance and substrate re-use is also discussed.

Characterization of Thermal Oxides on 4H-SiC Epitaxial Substrates Using Fourier-Transform Infrared Spectroscopy.

PubMed

Seki, Hirofumi; Yoshikawa, Masanobu; Kobayashi, Takuma; Kimoto, Tsunenobu; Ozaki, Yukihiro

2017-05-01

Fourier transform infrared (FT-IR) spectra were measured for thermal oxides with different electrical properties grown on 4H-SiC substrates. The peak frequency of the transverse optical (TO) phonon mode was blue-shifted by 5 cm -1 as the oxide-layer thickness decreased to 3 nm. The blue shift of the TO mode indicates interfacial compressive stress in the oxide. Comparison of data for the oxide on a SiC substrate with that for similar oxides on a Si substrate implies that the peak shift of the TO mode at the SiO 2 /SiC interface is larger than that of SiO 2 /Si, which suggests that the interfacial stress for the oxide on the SiC substrate is larger than that on the Si substrate. For the SiO 2 /SiC interfacial region (<3 nm oxide thickness), despite the fact that the blue shift of the TO modes becomes larger while approaching the oxide/SiC interface, the peak frequency of the TO modes red-shifts at the oxide/SiC interface. The peak-frequency shift of the TO mode for the sample without post-oxidation annealing was larger than that for the samples post-annealed in a nitric oxide atmosphere. The channel mobilities are correlated with the degree of shift of the TO mode when the oxide thickness is <3 nm. It appears that the compressive stress at the SiO 2 /SiC interface generates silicon suboxide components and weakens the Si-O bonds. As the result, the TO mode was red-shifted and the oxygen deficiency increased to relax the compressive stress in the oxide with <3 nm thickness. Fourier transform infrared spectroscopy measurements provide unique and useful information about stress and inhomogeneity at the oxide/SiC interface.

Ion-implanted Si-nanostructures buried in a SiO{sub 2} substrate studied with soft-x-ray spectroscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Williams, R.; Rubensson, J.E.; Eisebitt, S.

1997-04-01

In recent years silicon nanostructures have gained great interest because of their optical luminescence, which immediately suggests several applications, e.g., in optoelectronic devices. Nanostructures are also investigated because of the fundamental physics involved in the underlying luminescence mechanism, especially attention has been drawn to the influence of the reduced dimensions on the electronic structure. The forming of stable and well-defined nanostructured materials is one goal of cluster physics. For silicon nanostructures this goal has so far not been reached, but various indirect methods have been established, all having the problem of producing less well defined and/or unstable nanostructures. Ion implantationmore » and subsequent annealing is a promising new technique to overcome some of these difficulties. In this experiment the authors investigate the electronic structure of ion-implanted silicon nanoparticles buried in a stabilizing SiO{sub 2} substrate. Soft X-ray emission (SXE) spectroscopy features the appropriate information depth to investigate such buried structures. SXE spectra to a good approximation map the local partial density of occupied states (LPDOS) in broad band materials like Si. The use of monochromatized synchrotron radiation (MSR) allows for selective excitation of silicon atoms in different chemical environments. Thus, the emission from Si atom sites in the buried structure can be separated from contributions from the SiO{sub 2} substrate. In this preliminary study strong size dependent effects are found, and the electronic structure of the ion-implanted nanoparticles is shown to be qualitatively different from porous silicon. The results can be interpreted in terms of quantum confinement and chemical shifts due to neighboring oxygen atoms at the interface to SiO{sub 2}.« less

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Vacancy-type defects in TiO2/SiO2/SiC dielectric stacks

NASA Astrophysics Data System (ADS)

Coleman, P. G.; Burrows, C. P.; Mahapatra, R.; Wright, N. G.

2007-07-01

Open-volume (vacancy-type) point defects have been observed in ˜80-nm-thick titanium dioxide films grown on silicon dioxide/4H silicon carbide substrates as stacks with high dielectric constant for power device applications, using variable-energy positron annihilation spectroscopy. The concentration of vacancies decreases as the titanium dioxide growth temperature is increased in the range from 700to1000°C, whereas grain boundaries form in the polycrystalline material at the highest growth temperatures. It is proposed that the optimal electrical performance for films grown at 800°C reflects a balance between decreasing vacancy concentration and increasing grain boundary formation. The concentration of vacancies at the silicon dioxide/silicon carbide interface appears to saturate after 2.5h oxidation at 1150°C. A supplementary result suggests that the quality of the 10-μm-thick deposited silicon carbide epilayer is compromised at depths of about 2μm and beyond, possibly by the migration of impurities and/or other defects from the standard-grade highly doped 4H silicon carbide wafer beneath the epilayer during oxidation.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

PubMed

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Oh, Jin Hyuk; Kim, Sun Ae; Park, Jaegyu; Kim, Sanggi

2015-06-10

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

RF performances of inductors integrated on localized p+-type porous silicon regions

PubMed Central

2012-01-01

To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate. PMID:23009746

Adsorption of the Three-phase Emulsion on Various Solid Surfaces.

PubMed

Enomoto, Yasutaka; Imai, Yoko; Tajima, Kazuo

2017-07-01

The present study investigates the adsorption of the three-phase emulsion on various solid/water interfaces. Vesicles can be used as emulsifiers in the three-phase emulsions and act as an independent phase unlike the surfactant used in conventional emulsions; therefore, it is expected that the three-phase emulsion formed by the adhesion of vesicles to the oil/water interface will adsorb on various solid/water interfaces. The cationic three-phase emulsion was prepared to encourage emulsion adsorption on negatively charged solid substrates in water. The emulsifier polyoxyethylene-(10) hydrogenated castor oil was rendered cationic by mixing with the surfactant cetyltrimethylammonium bromide and then used to prepare the cationic three-phase emulsion of hexadecane-in-water. Three solid substrates (silicon, glass, and copper) were dipped in the cationic emulsion and the emulsion was found to adsorb on the solid substrates while maintaining its structure. The amount of hexadecane adsorbed on the various surfaces was investigated by gas chromatography and found to increase with increasing hexadecane concentration in the emulsion and eventually plateaued just like molecular adsorption. The maximum surface coverage of the emulsion on the substrates was approximately 80%. However, even the equivalent nonionic three-phase emulsion was found to adsorb on the three solid surfaces. This was attributed to a novel mechanism of irreversible adhesion via the van der Waals attractive force.

Metal/silicon Interfaces and Their Oxidation Behavior - Photoemission Spectroscopy Analysis.

NASA Astrophysics Data System (ADS)

Yeh, Jyh-Jye

Synchrotron radiation photoemission spectroscopy was used to study Ni/Si and Au/Si interface properties on the atomic scale at room temperature, after high temperature annealing and after oxygen exposures. Room temperature studies of metal/Si interfaces provide background for an understanding of the interface structure after elevated temperature annealing. Oxidation studies of Si surfaces covered with metal overlayers yield insight about the effect of metal atoms in the Si oxidation mechanisms and are useful in the identification of subtle differences in bonding relations between atoms at the metal/Si interfaces. Core level and valence band spectra with variable surface sensitivities were used to study the interactions between metal, Si, and oxygen for metal coverages and oxide thickness in the monolayer region. Interface morphology at the initial stage of metal/Si interface formation and after oxidation was modeled on the basis of the evolutions of metal and Si signals at different probing depths in the photoemission experiment. Both Ni/Si and Au/Si interfaces formed at room temperature have a diffusive region at the interface. This is composed of a layer of metal-Si alloy, formed by Si outdiffusion into the metal overlayer, above a layer of interstitial metal atoms in the Si substrate. Different atomic structures of these two regions at Ni/Si interface can account for the two different growth orientations of epitaxial Ni disilicides on the Si(111) surface after thermal annealing. Annealing the Au/Si interface at high temperature depletes all the Au atoms except for one monolayer of Au on the Si(111) surface. These phenomena are attributed to differences in the metal-Si chemical bonding relations associated with specific atomic structures. After oxygen exposures, both the Ni disilicide surface and Au covered Si surfaces (with different coverages and surface orderings) show silicon in higher oxidation states, in comparison to oxidized silicon on a clean surface. Preferential Si dioxide growth on the Au/Si surface is related to the strong distortion of the Si lattice when Au-Si bonds are formed. In comparison, a monolayer of Ni on a Si surface, with its weaker Ni-Si bond, does not enhance oxide formation.

Thin Film Stability of Polystyrene with a Functional End Group

NASA Astrophysics Data System (ADS)

Tanaka, Keiji; Shimomura, Shinichiro; Inutsuka, Manabu; Tajima, Koichiro; Nabika, Masaaki; Moritomi, Satoru; Matsuno, Hisao; Kyushu Univ. Team; Sumitomo Chemical Co., Ltd. Collaboration

The thin film stability of omega- N-(3-(dimethylamino)propyl)propylamide-terminated polystyrene (PS-N) and its mixture with conventional polystyrene (PS-H) spin-coated on silicon wafers with a native oxide layer was studied. While a 20 nm-thick film of PS-H with a number-average molecular weight of approximately 50k was broken at 423 K, a comparable PS-N film and blend films with a PS-N fraction higher than 40 wt% were stable. Although the local conformation of chains at the substrate interface was not the same for PS with/without the functionalized terminal group, the glass transition temperature at the interface was identical for PS-H and PS-N. The residual adsorbed layer on the substrate after washing the films with toluene was thicker for PS-N than for PS-H. This implies that the end functionalization impacts chain movement on a large scale rather than via segmental dynamics.

Effect of Same-Temperature GaN Cap Layer on the InGaN/GaN Multiquantum Well of Green Light-Emitting Diode on Silicon Substrate

PubMed Central

Zheng, Changda; Wang, Li; Mo, Chunlan; Fang, Wenqing; Jiang, Fengyi

2013-01-01

GaN green LED was grown on Si (111) substrate by MOCVD. To enhance the quality of InGaN/GaN MQWs, same-temperature (ST) GaN protection layers with different thickness of 8 Å, 15 Å, and 30 Å were induced after the InGaN quantum wells (QWs) layer. Results show that a relative thicker cap layer is benefit to get InGaN QWs with higher In percent at fixed well temperature and obtain better QW/QB interface. As the cap thickness increases, the indium distribution becomes homogeneous as verified by fluorescence microscope (FLM). The interface of MQWs turns to be abrupt from XRD analysis. The intensity of photoluminescence (PL) spectrum is increased and the FWHM becomes narrow. PMID:24369453

Biwavelength transceiver module for parallel simultaneous bidirectional optical interconnections

NASA Astrophysics Data System (ADS)

Nguyen, Nga T. H.; Ukaegbu, Ikechi A.; Sangirov, Jamshid; Cho, Mu-Hee; Lee, Tae-Woo; Park, Hyo-Hoon

2013-12-01

The design of a biwavelength transceiver (TRx) module for parallel simultaneous bidirectional optical interconnects is described. The TRx module has been implemented using two different wavelengths, 850 and 1060 nm, to send and receive signals simultaneously through a common optical interface while optimizing cost and performance. Filtering mirrors are formed in the optical fibers which are embedded on a V-grooved silicon substrate for reflecting and filtering optical signals from/to vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD). The VCSEL and PD are flip-chip bonded on individual silicon optical benches, which are attached on the silicon substrate for optical signal coupling from the VCSEL to fiber and from fiber to the PD. A high-speed and low-loss ceramic printed circuit board, which has a compact size of 0.033 cc, has been designed to carry transmitter and receiver chips for easy packaging of the TRx module. Applied for quad small form-factor pluggable applications at 40-Gbps operation, the four-channel biwavelength TRx module showed clear eye diagrams with a bit error rate (BER) of 10-12 at input powers of -5 and -5.8 dBm for 1060 and 850 nm operation modes, respectively.

Thin film GaP for solar cell application

NASA Astrophysics Data System (ADS)

Morozov, I. A.; Gudovskikh, A. S.; Kudryashov, D. A.; Nikitina, E. V.; Kleider, J.-P.; Myasoedov, A. V.; Levitskiy, V.

2016-08-01

A new approach to the silicon based heterostructures technology consisting of the growth of III-V compounds (GaP) on a silicon substrate by low-temperature plasma enhanced atomic layer deposition (PE-ALD) is proposed. The basic idea of the method is to use a time modulation of the growth process, i.e. time separated stages of atoms or precursors transport to the growing surface, migration over the surface, and crystal lattice relaxation for each monolayer. The GaP layers were grown on Si substrates by PE-ALD at 350°C with phosphine (PH3) and trimethylgallium (TMG) as sources of III and V atoms. Scanning and transmission electron microscopy demonstrate that the grown GaP films have homogeneous amorphous structure, smooth surface and a sharp GaP/Si interface. The GaP/Si heterostructures obtained by PE-ALD compare favourably to that conventionally grown by molecular beam epitaxy (MBE). Indeed, spectroscopic ellipsometry measurements indicate similar interband optical absorption while photoluminescence measurements indicate higher charge carrier effective lifetime. The better passivation properties of GaP layers grown by PE-ALD demonstrate a potential of this technology for new silicon based photovoltaic heterostructure

Synthesis and properties of SiN coatings as stable fluorescent markers on vertically aligned carbon nanofibers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pearce, Ryan; Klein, Kate L; Ivanov, Ilia N

2014-01-01

The growth of vertically aligned carbon nanofibers (VACNFs) in a catalytic dc ammonia/acetylene plasma process on silicon substrates is often accompanied by sidewall deposition of material that contains mostly Si and N. In fluorescent microscopy experiments, imaging VACNF interfacing to live cell cultures it turned out that this material is broadly fluorescent, which made VACNFs useful as spatial markers, or created nuisance when DNA-labeling got masked. In this paper we provide insight into nature of this silicon/nitrogen in situ coatings. Here we have proposed a potential mechanism for deposition of SiNx coating on the sidewalls of VACNFs during PECVD synthesismore » in addition to exploring the origin of the coatings fluorescence. It seems most likely that the substrate reacts with the process gases through both processes similar to reactive sputtering and CVD to form silane and other silicon bearing compounds before being deposited isotropically as a SiNx coating onto the VACNFs. The case for the presence of Si-NCs is made strong through a combination of the strong fluorescence and elemental analysis of the samples. These broadly luminescent fibers can prove useful as registry markers in fluorescent cellular studies.« less

High sensitivity Schottky junction diode based on monolithically grown aligned polypyrrole nanofibers: Broad range detection of m-dihydroxybenzene.

PubMed

Ameen, Sadia; Akhtar, M Shaheer; Seo, Hyung-Kee; Shin, Hyung Shik

2015-07-30

Aligned p-type polypyrrole (PPy) nanofibers (NFs) thin film was grown on n-type silicon (100) substrate by an electrochemical technique to fabricate Schottky junction diode for the efficient detection of m-dihydroxybenzene chemical. The highly dense and well aligned PPy NFs with the average diameter (∼150-200 nm) were grown on n-type Si substrate. The formation of aligned PPy NFs was confirmed by elucidating the structural, compositional and the optical properties. The electrochemical behavior of the fabricated Pt/p-aligned PPy NFs/n-silicon Schottky junction diode was evaluated by cyclovoltametry (CV) and current (I)-voltage (V) measurements with the variation of m-dihydroxybenzene concentration in the phosphate buffer solution (PBS). The fabricated Pt/p-aligned PPy NFs/n-silicon Schottky junction diode exhibited the rectifying behavior of I-V curve with the addition of m-dihydroxybenzene chemical, while a weak rectifying I-V behavior was observed without m-dihydroxybenzene chemical. This non-linear I-V behavior suggested the formation of Schottky barrier at the interface of Pt layer and p-aligned PPy NFs/n-silicon thin film layer. By analyzing the I-V characteristics, the fabricated Pt/p-aligned PPy NFs/n-silicon Schottky junction diode displayed reasonably high sensitivity ∼23.67 μAmM(-1)cm(-2), good detection limit of ∼1.51 mM with correlation coefficient (R) of ∼0.9966 and short response time (10 s). Copyright © 2015 Elsevier B.V. All rights reserved.

Study of surface reaction during selective epitaxy growth of silicon by thermodynamic analysis and density functional theory calculation

NASA Astrophysics Data System (ADS)

Mayangsari, Tirta R.; Yusup, Luchana L.; Park, Jae-Min; Blanquet, Elisabeth; Pons, Michel; Jung, Jongwan; Lee, Won-Jun

2017-06-01

We modeled and simulated the surface reaction of silicon precursor on different surfaces by thermodynamic analysis and density functional theory calculation. We considered SiH2Cl2 and argon as the silicon precursor and the carrier gas without etchant gas. First, the equilibrium composition of both gaseous and solid species was analyzed as a function of process temperature. SiCl4 is the dominant gaseous species at below 750 °C, and SiCl2 and HCl are dominant at higher temperatures, and the yield of silicon decreases with increasing temperature over 700 °C due to the etching of silicon by HCl. The yield of silicon for SiO2 substrate is lower than that for silicon substrate, especially at 1000 °C or higher. Zero deposition yield and the etching of SiO2 substrate at higher temperatures leads to selective growth on silicon substrate. Next, the adsorption and the reaction of silicon precursor was simulated on H-terminated silicon (100) substrate and on OH-terminated β-cristobalite substrate. The adsorption and reaction of a SiH2Cl2 molecule are spontaneous for both Si and SiO2 substrates. However, the energy barrier for reaction is very small (6×10-4 eV) for Si substrate, whereas the energy barrier is high (0.33 eV) for SiO2 substrate. This makes the differences in growth rate, which also supports the experimental results in literature.

Self-assembly of silica nanoparticles by tuning substrate-adsorbate interaction

NASA Astrophysics Data System (ADS)

Utsav, Khanna, Sakshum; Mukhopadhayay, Indrajit; Banerjee, Rupak

2018-05-01

We report on self-assembled nanodisc formations of silica nanoparticles on a surface modified silicon substrate using modified Langmuir-Schafer deposition technique (stamping). The size, inter-particle separation as well as the packing of the silica nanoparticles within the nanodiscs formed spontaneously can be tuned by the surface pressure applied on the water surface. We obtain self-assembled nanodiscs of silica nanoparticle arranged in a hexagonal symmetry. We also observe that by varying the surface pressure of deposition at the water-molecule-air interface we obtain such 2D disc-shaped structure with varying sizes and a packing ratio of the silica nanoparticle.

Electronic states and band lineups in c-Si(100)/a-Si1-xCx:H heterojunctions

NASA Astrophysics Data System (ADS)

Brown, T. M.; Bittencourt, C.; Sebastiani, M.; Evangelisti, F.

1997-04-01

Heterostructures formed by depositing in situ amorphous hydrogenated silicon-carbon alloys on Si(100) substrates were characterized by photoelectric-yield spectroscopy, UPS, and XPS. It is shown that both substrate and overlayer valence-band tops can be identified on the photoelectric-yield spectrum, thus allowing a direct and precise determination of the band lineup. We find a valence-band discontinuity varying from 0.44 eV to 1.00 eV for carbon content ranging from 0 to 50%. The present data can be used as a test for the lineup theories and strongly support the interface dipole models.

Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsam (Inventor); Manohara, Harish (Inventor); Mobasser, Sohrab (Inventor); Lee, Choonsup (Inventor)

2011-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Anti- reflective device having an anti-reflection surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsman (Inventor); Mooasser, Sohrab (Inventor); Manohara, Harish (Inventor); Lee, Choonsup (Inventor); Bae, Kungsam (Inventor)

2009-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Enhanced adhesion by high energy bombardment

NASA Technical Reports Server (NTRS)

Griffith, Joseph E. (Inventor); Qiu, Yuanxun (Inventor); Tombrello, Thomas A. (Inventor)

1984-01-01

Films (12) of gold, copper, silicon nitride, or other materials are firmly bonded to insulator substrates (12) such as silica, a ferrite, or Teflon (polytetrafluorethylene) by irradiating the interface with high energy ions. Apparently, track forming processes in the electronic stopping region cause intermixing in a thin surface layer resulting in improved adhesion without excessive doping. Thick layers can be bonded by depositing or doping the interfacial surfaces with fissionable elements or alpha emitters.

Thermal Stability of Silver Paste Sintering on Coated Copper and Aluminum Substrates

NASA Astrophysics Data System (ADS)

Pei, Chun; Chen, Chuantong; Suganuma, Katsuaki; Fu, Guicui

2018-01-01

The thermal stability of silver (Ag) paste sintering on coated copper (Cu) and aluminum (Al) substrates has been investigated. Instead of conventional zincating or nickel plating, magnetron sputtering was used to achieve coating with titanium (Ti) and Ag. Silicon (Si) chips were bonded to coated Cu and Al substrates using a mixture of submicron Ag flakes and particles under 250°C and 0.4 MPa for 30 min. The joints were then subject to aging testing at 250°C for duration of 200 h, 500 h, and 1000 h. Two types of joints exhibited satisfactory initial shear strength above 45 MPa. However, the shear strength of the joints on Al substrate decreased to 28 MPa after 1000 h of aging, while no shear strength decline was detected for the joints on Cu substrate. Fracture surface analysis revealed that the vulnerable points of the two types of joints were (1) the Ag layer and (2) the interface between the Ti layer and Cu substrate. Based on the results of scanning electron microscopy (SEM), energy-dispersive x-ray spectroscopy (EDS), and simulations, cracks in the Ag layer were identified as the cause of the shear strength degradation in the joints on Al substrate. The interface evolution of the joints on Cu substrate was ascribed to Cu migration and discontinuity points that initialized in the Ti layer. This study reveals that Al exhibited superior thermal stability with sintered Ag paste.

Ceramic with preferential oxygen reactive layer

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Luthra, Krishan Lal (Inventor)

2001-01-01

An article comprises a silicon-containing substrate and an external environmental/thermal barrier coating. The external environmental/thermal barrier coating is permeable to diffusion of an environmental oxidant and the silicon-containing substrate is oxidizable by reaction with oxidant to form at least one gaseous product. The article comprises an intermediate layer/coating between the silicon-containing substrate and the environmental/thermal barrier coating that is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant. A method of forming an article, comprises forming a silicon-based substrate that is oxidizable by reaction with oxidant to at least one gaseous product and applying an intermediate layer/coating onto the substrate, wherein the intermediate layer/coating is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant.

Choosing a Silicone Encapsulant for Photovoltaic Applications

NASA Astrophysics Data System (ADS)

Velderrain, Michelle

2011-12-01

Growth in the solar industry has resulted in newer technologies, specifically concentrator photovoltaic (CPV) modules, to explore using new types of materials such as silicone encapsulants. CPV and LCPV module designs are to achieve the most efficient energy conversion possible however it is equally important to demonstrate long term reliability. Silicone is a material of interest due to its thermal stability and ability to absorb stresses incurred during thermal cycling. The refractive index of clear silicone adhesives is advantageous because it can be optimized using phenyl groups to match BK7 glass and other substrates to minimize light loss at the interfaces but it is relatively unknown how the optical properties change over time possibly yellowing in such a harsh environment. A 1.41 silicone encapsulant is compared to a 1.52 refractive index silicone. Optical Absorption (300 nm-1300 nm), Water Vapor Permeability, Moisture Absorption and effects of oxidation at elevated temperatures will be compared of these materials to aid the engineer in choosing a silicone for their CPV application. Non-phenyl containing 1.41 RI silicones have been used for several years for bonding solar arrays in the satellite industry. Phenyl groups on the siloxane polymer can change various properties of the silicone. Understanding how phenyl affects these properties allows the engineer to understand the benefits and risks when using a RI matching silicone to minimize light loss versus a non-phenyl containing silicone.

Fabrication of planarised conductively patterned diamond for bio-applications.

PubMed

Tong, Wei; Fox, Kate; Ganesan, Kumaravelu; Turnley, Ann M; Shimoni, Olga; Tran, Phong A; Lohrmann, Alexander; McFarlane, Thomas; Ahnood, Arman; Garrett, David J; Meffin, Hamish; O'Brien-Simpson, Neil M; Reynolds, Eric C; Prawer, Steven

2014-10-01

The development of smooth, featureless surfaces for biomedical microelectronics is a challenging feat. Other than the traditional electronic materials like silicon, few microelectronic circuits can be produced with conductive features without compromising the surface topography and/or biocompatibility. Diamond is fast becoming a highly sought after biomaterial for electrical stimulation, however, its inherent surface roughness introduced by the growth process limits its applications in electronic circuitry. In this study, we introduce a fabrication method for developing conductive features in an insulating diamond substrate whilst maintaining a planar topography. Using a combination of microwave plasma enhanced chemical vapour deposition, inductively coupled plasma reactive ion etching, secondary diamond growth and silicon wet-etching, we have produced a patterned substrate in which the surface roughness at the interface between the conducting and insulating diamond is approximately 3 nm. We also show that the patterned smooth topography is capable of neuronal cell adhesion and growth whilst restricting bacterial adhesion. Copyright © 2014 Elsevier B.V. All rights reserved.

Adhesion enhancement of titanium nitride coating on aluminum casting alloy by intrinsic microstructures

NASA Astrophysics Data System (ADS)

Nguyen, Chuong L.; Preston, Andrew; Tran, Anh T. T.; Dickinson, Michelle; Metson, James B.

2016-07-01

Aluminum casting alloys have excellent castability, high strength and good corrosion resistance. However, the presence of silicon in these alloys prevents surface finishing with conventional methods such as anodizing. Hard coating with titanium nitride can provide wear and corrosion resistances, as well as the aesthetic finish. A critical factor for a durable hard coating is its bonding with the underlying substrate. In this study, a titanium nitride layer was coated on LM25 casting alloy and a reference high purity aluminum substrate using Ion Assisted Deposition. Characterization of the coating and the critical interface was carried out by a range of complementing techniques, including SIMS, XPS, TEM, SEM/EDS and nano-indentation. It was observed that the coating on the aluminum alloy is stronger compared to that on the pure aluminum counterpart. Silicon particles in the alloy offers the reinforcement though mechanical interlocking at microscopic level, even with nano-scale height difference. This reinforcement overcomes the adverse effect caused by surface segregation of magnesium in aluminum casting alloys.

Oxygen impurity effects at metal/silicide interfaces - Formation of silicon oxide and suboxides in the Ni/Si system

NASA Technical Reports Server (NTRS)

Grunthaner, P. J.; Grunthaner, F. J.; Scott, D. M.; Nicolet, M.-A.; Mayer, J. W.

1981-01-01

The effect of implanted oxygen impurities on the Ni/Ni2Si interface is investigated using X-ray photoelectron spectroscopy, He-4(+) backscattering and O(d, alpha)-16 N-14 nuclear reactions. Oxygen dosages corresponding to concentrations of 1, 2, and 3 atomic percent were implanted into Ni films evaporated on Si substrates. The oxygen, nickel, and silicon core lines were monitored as a function of time during in situ growth of the Ni silicide to determine the chemical nature of the diffusion barrier which forms in the presence of oxygen impurities. Analysis of the Ni, Si, and O core levels demonstrates that the formation of SiO2 is responsible for the Ni diffusion barrier rather than Ni oxide or mixed oxides, such as Ni2SiO4. It is determined that 2.2 x 10 to the 16th O/qu cm is sufficient to prevent Ni diffusion under UHV annealing conditions.

Structural and electrical properties of AlN layers grown on silicon by reactive RF magnetron sputtering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bazlov, N., E-mail: n.bazlov@spbu.ru; Pilipenko, N., E-mail: nelly.pilipenko@gmail.com; Vyvenko, O.

2016-06-17

AlN films of different thicknesses were deposited on n-Si (100) substrates by reactive radio frequency (rf) magnetron sputtering. Dependences of structure and electrical properties on thickness of deposited films were researched. The structures of the films were analyzed with scanning electron microscopy (SEM) and with transmitting electron microscopy (TEM). Electrical properties of the films were investigated on Au-AlN-(n-Si) structures by means of current-voltage (I-V), capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) techniques. Electron microscopy investigations had shown that structure and chemical composition of the films were thickness stratified. Near silicon surface layer was amorphous aluminum oxide one contained trapsmore » of positive charges with concentration of about 4 × 10{sup 18} cm{sup −3}. Upper layers were nanocrystalline ones consisted of both wurzite AlN and cubic AlON nanocrystals. They contained traps both positive and negative charges which were situated within 30 nm distance from silicon surface. Surface densities of these traps were about 10{sup 12} cm{sup −2}. Electron traps with activation energies of (0.2 ÷ 0.4) eV and densities of about 10{sup 10} cm{sup −2} were revealed on interface between aluminum oxide layer and silicon substrate. Their densities varied weakly with the film thickness.« less

Back contact to film silicon on metal for photovoltaic cells

DOEpatents

Branz, Howard M.; Teplin, Charles; Stradins, Pauls

2013-06-18

A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.

Surface treatment effect on Si (111) substrate for carbon deposition using DC unbalanced magnetron sputtering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aji, A. S., E-mail: aji.ravazes70@gmail.com; Sahdan, M. F.; Hendra, I. B.

In this work, we studied the effect of HF treatment in silicon (111) substrate surface for depositing thin layer carbon. We performed the deposition of carbon by using DC Unbalanced Magnetron Sputtering with carbon pallet (5% Fe) as target. From SEM characterization results it can be concluded that the carbon layer on HF treated substrate is more uniform than on substrate without treated. Carbon deposition rate is higher as confirmed by AFM results if the silicon substrate is treated by HF solution. EDAX characterization results tell that silicon (111) substrate with HF treatment have more carbon fraction than substrate withoutmore » treatment. These results confirmed that HF treatment on silicon Si (111) substrates could enhance the carbon deposition by using DC sputtering. Afterward, the carbon atomic arrangement on silicon (111) surface is studied by performing thermal annealing process to 900 °C. From Raman spectroscopy results, thin film carbon is not changing until 600 °C thermal budged. But, when temperature increase to 900 °C, thin film carbon is starting to diffuse to silicon (111) substrates.« less

The role of the substrate in Graphene/Silicon photodiodes

NASA Astrophysics Data System (ADS)

Luongo, G.; Giubileo, F.; Iemmo, L.; Di Bartolomeo, A.

2018-01-01

The Graphene/Silicon (Gr/Si) junction can function as a Schottky diode with performances strictly related to the quality of the interface. Here, we focus on the substrate geometry and on its effects on Gr/Si junction physics. We fabricate and study the electrical and optical behaviour of two types of devices: one made of a Gr/Si planar junction, the second realized with graphene on an array of Si nanotips. We show that the Gr/Si flat device exhibits a reverse photocurrent higher than the forward current and achieves a photoresponsivity of 2.5 A/W. The high photoresponse is due to the charges photogenerated in Si below a parasitic graphene/SiO2/Si structure, which are injected into the Gr/Si junction region. The other device with graphene on Si-tips displays a reverse current that grows exponentially with the bias. We explain this behaviour by taking into account the tip geometry of the substrate, which magnifies the electric field and shifts the Fermi level of graphene, thus enabling fine-tuning of the Schottky barrier height. The Gr/Si-tip device achieves a higher photoresponsivity, up to 3 A/W, likely due to photocharge internal multiplication.

Interface traps contribution on transport mechanisms under illumination in metal-oxide-semiconductor structures based on silicon nanocrystals

NASA Astrophysics Data System (ADS)

Chatbouri, S.; Troudi, M.; Kalboussi, A.; Souifi, A.

2018-02-01

The transport phenomena in metal-oxide-semiconductor (MOS) structures having silicon nanocrystals (Si-NCs) inside the dielectric layer have been investigated, in dark condition and under visible illumination. At first, using deep-level transient spectroscopy (DLTS), we find the presence of series electron traps having very close energy levels (comprised between 0.28 and 0.45 eV) for ours devices (with/without Si-NCs). And a single peak appears at low temperature only for MOS with Si-NCs related to Si-NCs DLTS response. In dark condition, the conduction mechanism is dominated by the thermionic fast emission/capture of charge carriers from the highly doped polysilicon layer to Si-substrate through interface trap states for MOS without Si-NCs. The tunneling of charge carriers from highly poly-Si to Si substrate trough the trapping/detrapping mechanism in the Si-NCs, at low temperature, contributed to the conduction mechanism for MOS with Si-NCs. The light effect on transport mechanisms has been investigated using current-voltage ( I- V), and high frequency capacitance-voltage ( C- V) methods. We have been marked the photoactive trap effect in inversion zone at room temperature in I- V characteristics, which confirm the contribution of photo-generated charge on the transport mechanisms from highly poly-Si to Si substrate trough the photo-trapping/detrapping mechanism in the Si-NCs and interfaces traps levels. These results have been confirmed by an increasing about 10 pF in capacity's values for the C- V characteristics of MOS with Si-NCs, in the inversion region for inverse high voltage applied under photoexcitation at low temperature. These results are helpful to understand the principle of charge transport in dark condition and under illumination, of MOS structures having Si-NCs in the SiO x = 1.5 oxide matrix.

XPS studies of structure-induced radiation effects at the Si/SiO2 interface. [X ray Photoelectron Spectroscopy

NASA Technical Reports Server (NTRS)

Grunthaner, F. J.; Lewis, B. F.; Zamini, N.; Maserjian, J.; Madhukar, A.

1980-01-01

The interfacial structures of radiation hard and soft oxides grown by dry and wet processes on silicon substrates have been examined by high-resolution X-ray photoelectron spectroscopy. It is found that the primary difference in the local atomic structure at the Si/SiO2 interface is the significantly higher concentration of strained 120 deg SiO2 bonds and SiO interfacial species in soft samples. Results of in situ radiation damage experiments using low energy electrons (0-20 eV) are reported which correlate with the presence of a strained layer of SiO2 (20 A) at the interface. The results are interpreted in terms of a structural model for hole and electron trap generation by ionizing radiation.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

Protein aggregation and particle formation in prefilled glass syringes.

PubMed

Gerhardt, Alana; Mcgraw, Nicole R; Schwartz, Daniel K; Bee, Jared S; Carpenter, John F; Randolph, Theodore W

2014-06-01

The stability of therapeutic proteins formulated in prefilled syringes (PFS) may be negatively impacted by the exposure of protein molecules to silicone oil-water interfaces and air-water interfaces. In addition, agitation, such as that experienced during transportation, may increase the detrimental effects (i.e., protein aggregation and particle formation) of protein interactions with interfaces. In this study, surfactant-free formulations containing either a monoclonal antibody or lysozyme were incubated in PFS, where they were exposed to silicone oil-water interfaces (siliconized syringe walls), air-water interfaces (air bubbles), and agitation stress (occurring during end-over-end rotation). Using flow microscopy, particles (≥2 μm diameter) were detected under all conditions. The highest particle concentrations were found in agitated, siliconized syringes containing an air bubble. The particles formed in this condition consisted of silicone oil droplets and aggregated protein, as well as agglomerates of protein aggregates and silicone oil. We propose an interfacial mechanism of particle generation in PFS in which capillary forces at the three-phase (silicone oil-water-air) contact line remove silicone oil and gelled protein aggregates from the interface and transport them into the bulk. This mechanism explains the synergistic effects of silicone oil-water interfaces, air-water interfaces, and agitation in the generation of particles in protein formulations. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE PAGES

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine; ...

2016-08-01

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter, E-mail: johannes.seif@alumni.epfl.ch; Ballif, Christophe; De Wolf, Stefaan

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation ofmore » such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects

PubMed Central

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Gyoo Kim, In; Hyuk Oh, Jin; Ae Kim, Sun; Park, Jaegyu; Kim, Sanggi

2015-01-01

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications. PMID:26061463

Utilizing van der Waals Slippery Interfaces to Enhance the Electrochemical Stability of Silicon Film Anodes in Lithium-Ion Batteries.

PubMed

Basu, Swastik; Suresh, Shravan; Ghatak, Kamalika; Bartolucci, Stephen F; Gupta, Tushar; Hundekar, Prateek; Kumar, Rajesh; Lu, Toh-Ming; Datta, Dibakar; Shi, Yunfeng; Koratkar, Nikhil

2018-04-25

High specific capacity anode materials such as silicon (Si) are increasingly being explored for next-generation, high performance lithium (Li)-ion batteries. In this context, Si films are advantageous compared to Si nanoparticle based anodes since in films the free volume between nanoparticles is eliminated, resulting in very high volumetric energy density. However, Si undergoes volume expansion (contraction) under lithiation (delithiation) of up to 300%. This large volume expansion leads to stress build-up at the interface between the Si film and the current collector, leading to delamination of Si from the surface of the current collector. To prevent this, adhesion promotors (such as chromium interlayers) are often used to strengthen the interface between the Si and the current collector. Here, we show that such approaches are in fact counter-productive and that far better electrochemical stability can be obtained by engineering a van der Waals "slippery" interface between the Si film and the current collector. This can be accomplished by simply coating the current collector surface with graphene sheets. For such an interface, the Si film slips with respect to the current collector under lithiation/delithiation, while retaining electrical contact with the current collector. Molecular dynamics simulations indicate (i) less stress build-up and (ii) less stress "cycling" on a van der Waals slippery substrate as opposed to a fixed interface. Electrochemical testing confirms more stable performance and much higher Coulombic efficiency for Si films deposited on graphene-coated nickel (i.e., slippery interface) as compared to conventional nickel current collectors.

Design and Fabrication of Submicron Magnetic Bubble Device Technology.

DTIC Science & Technology

1986-10-31

interface LPE bubble film GGG substrate Figure 2: Cross section of a silicon on garnet magnetodiode. I : R R R/ B>O0 B 0 z V............. ... ..AV dummy...Carnegie Mellon University, Pittsburgh, Pa 15213. Section I Introduction The main thrust of our LPE garnet film growth program is to develop> films ...shown in Table I and the best choice for an isotropic magnetostrictive film is shown by an asterik. Section IM LPE Film Growth Technique All garnet

Simulation optimizing of n-type HIT solar cells with AFORS-HET

NASA Astrophysics Data System (ADS)

Yao, Yao; Xiao, Shaoqing; Zhang, Xiumei; Gu, Xiaofeng

2017-07-01

This paper presents a study of heterojunction with intrinsic thin layer (HIT) solar cells based on n-type silicon substrates by a simulation software AFORS-HET. We have studied the influence of thickness, band gap of intrinsic layer and defect densities of every interface. Details in mechanisms are elaborated as well. The results show that the optimized efficiency reaches more than 23% which may give proper suggestions to practical preparation for HIT solar cells industry.

Deposition method for producing silicon carbide high-temperature semiconductors

DOEpatents

Hsu, George C.; Rohatgi, Naresh K.

1987-01-01

An improved deposition method for producing silicon carbide high-temperature semiconductor material comprising placing a semiconductor substrate composed of silicon carbide in a fluidized bed silicon carbide deposition reactor, fluidizing the bed particles by hydrogen gas in a mildly bubbling mode through a gas distributor and heating the substrate at temperatures around 1200.degree.-1500.degree. C. thereby depositing a layer of silicon carbide on the semiconductor substrate.

Software systems for modeling articulated figures

NASA Technical Reports Server (NTRS)

Phillips, Cary B.

1989-01-01

Research in computer animation and simulation of human task performance requires sophisticated geometric modeling and user interface tools. The software for a research environment should present the programmer with a powerful but flexible substrate of facilities for displaying and manipulating geometric objects, yet insure that future tools have a consistent and friendly user interface. Jack is a system which provides a flexible and extensible programmer and user interface for displaying and manipulating complex geometric figures, particularly human figures in a 3D working environment. It is a basic software framework for high-performance Silicon Graphics IRIS workstations for modeling and manipulating geometric objects in a general but powerful way. It provides a consistent and user-friendly interface across various applications in computer animation and simulation of human task performance. Currently, Jack provides input and control for applications including lighting specification and image rendering, anthropometric modeling, figure positioning, inverse kinematics, dynamic simulation, and keyframe animation.

Uniformity and passivation research of Al2O3 film on silicon substrate prepared by plasma-enhanced atom layer deposition.

PubMed

Jia, Endong; Zhou, Chunlan; Wang, Wenjing

2015-01-01

Plasma-enhanced atom layer deposition (PEALD) can deposit denser films than those prepared by thermal ALD. But the improvement on thickness uniformity and the decrease of defect density of the films deposited by PEALD need further research. A PEALD process from trimethyl-aluminum (TMA) and oxygen plasma was investigated to study the influence of the conditions with different plasma powers and deposition temperatures on uniformity and growth rate. The thickness and refractive index of films were measured by ellipsometry, and the passivation effect of alumina on n-type silicon before and after annealing was measured by microwave photoconductivity decay method. Also, the effects of deposition temperature and annealing temperature on effective minority carrier lifetime were investigated. Capacitance-voltage and conductance-voltage measurements were used to investigate the interface defect density of state (D it) of Al2O3/Si. Finally, Al diffusion P(+) emitter on n-type silicon was passivated by PEALD Al2O3 films. The conclusion is that the condition of lower substrate temperature accelerates the growth of films and that the condition of lower plasma power controls the films' uniformity. The annealing temperature is higher for samples prepared at lower substrate temperature in order to get the better surface passivation effects. Heavier doping concentration of Al increased passivation quality after annealing by the effective minority carrier lifetime up to 100 μs.

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

NASA Astrophysics Data System (ADS)

Li, Yunlong; Suhard, Samuel; Van Huylenbroeck, Stefaan; Meersschaut, Johan; Van Besien, Els; Stucchi, Michele; Croes, Kristof; Beyer, Gerald; Beyne, Eric

2017-12-01

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Hot Electron Injection into Uniaxially Strained Silicon

NASA Astrophysics Data System (ADS)

Kim, Hyun Soo

In semiconductor spintronics, silicon attracts great attention due to the long electron spin lifetime. Silicon is also one of the most commonly used semiconductor in microelectronics industry. The spin relaxation process of diamond crystal structure such as silicon is dominant by Elliot-Yafet mechanism. Yafet shows that intravalley scattering process is dominant. The conduction electron spin lifetime measured by electron spin resonance measurement and electronic measurement using ballistic hot electron method well agrees with Yafet's theory. However, the recent theory predicts a strong contribution of intervalley scattering process such as f-process in silicon. The conduction band minimum is close the Brillouin zone edge, X point which causes strong spin mixing at the conduction band. A recent experiment of electric field-induced hot electron spin relaxation also shows the strong effect of f-process in silicon. In uniaxially strained silicon along crystal axis [100], the suppression of f-process is predicted which leads to enhance electron spin lifetime. By inducing a change in crystal structure due to uniaxial strain, the six fold degeneracy becomes two fold degeneracy, which is valley splitting. As the valley splitting increases, intervalley scattering is reduced. A recent theory predicts 4 times longer electron spin lifetime in 0.5% uniaxially strained silicon. In this thesis, we demonstrate ballistic hot electron injection into silicon under various uniaxial strain. Spin polarized hot electron injection under strain is experimentally one of the most challenging part to measure conduction electron spin lifetime in silicon. Hot electron injection adopts tunnel junction which is a thin oxide layer between two conducting materials. Tunnel barrier, which is an oxide layer, is only 4 ˜ 5 nm thick. Also, two conducting materials are only tens of nanometer. Therefore, under high pressure to apply 0.5% strain on silicon, thin films on silicon substrate can be easily destroyed. In order to confirm the performance of tunnel junction, we use tunnel magnetoresistance(TMR). TMR consists of two kinds of ferromagnetic materials and an oxide layer as tunnel barrier in order to measure spin valve effect. Using silicon as a collector with Schottky barrier interface between metal and silicon, ballistic hot spin polarized electron injection into silicon is demonstrated. We also observed change of coercive field and magnetoresistance due to modification of local states in ferromagnetic materials and surface states at the interface between metal and silicon due to strain.

Trends and Techniques for Space Base Electronics

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Wade, T. E.; Gassaway, J. D.

1979-01-01

Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized.

Fabricating amorphous silicon solar cells by varying the temperature _of the substrate during deposition of the amorphous silicon layer

DOEpatents

Carlson, David E.

1982-01-01

An improved process for fabricating amorphous silicon solar cells in which the temperature of the substrate is varied during the deposition of the amorphous silicon layer is described. Solar cells manufactured in accordance with this process are shown to have increased efficiencies and fill factors when compared to solar cells manufactured with a constant substrate temperature during deposition of the amorphous silicon layer.

Nitrogen doped silicon-carbon multilayer protective coatings on carbon obtained by thermionic vacuum arc (TVA) method

NASA Astrophysics Data System (ADS)

Ciupinǎ, Victor; Vasile, Eugeniu; Porosnicu, Corneliu; Vladoiu, Rodica; Mandes, Aurelia; Dinca, Virginia; Nicolescu, Virginia; Manu, Radu; Dinca, Paul; Zaharia, Agripina

2018-02-01

To obtain protective nitrogen doped Si-C multilayer coatings on carbon, used to improve the oxidation resistance of carbon, was used TVA method. The initial carbon layer has been deposed on a silicon substrate in the absence of nitrogen, and then a 3nm Si thin film to cover carbon layer was deposed. Further, seven Si and C layers were alternatively deposed in the presence of nitrogen ions. In order to form silicon carbide at the interface between silicon and carbon layers, all carbon, silicon and nitrogen ions energy has increased up to 150eV. The characterization of microstructure and electrical properties of as-prepared N-Si-C multilayer structures were done using Transmission Electron Microscopy (TEM, STEM) techniques, Thermal Desorption Spectroscopy (TDS) and electrical measurements. The retention of oxygen in the protective layer of N-Si-C is due to the following phenomena: (a) The reaction between oxygen and silicon carbide resulting in silicon oxide and carbon dioxide; (b) The reaction involving oxygen, nitrogen and silicon resulting silicon oxinitride with a variable composition; (c) Nitrogen acts as a trapping barrier for oxygen. To perform electrical measurements, ohmic contacts were attached on the N-Si-C samples. Electrical conductivity was measured in constant current mode. To explain the temperature behavior of electrical conductivity we assumed a thermally activated electric transport mechanism.

Sinusoidal nanotextures for light management in silicon thin-film solar cells.

PubMed

Köppel, G; Rech, B; Becker, C

2016-04-28

Recent progresses in liquid phase crystallization enabled the fabrication of thin wafer quality crystalline silicon layers on low-cost glass substrates enabling conversion efficiencies up to 12.1%. Because of its indirect band gap, a thin silicon absorber layer demands for efficient measures for light management. However, the combination of high quality crystalline silicon and light trapping structures is still a critical issue. Here, we implement hexagonal 750 nm pitched sinusoidal and pillar shaped nanostructures at the sun-facing glass-silicon interface into 10 μm thin liquid phase crystallized silicon thin-film solar cell devices on glass. Both structures are experimentally studied regarding their optical and optoelectronic properties. Reflection losses are reduced over the entire wavelength range outperforming state of the art anti-reflective planar layer systems. In case of the smooth sinusoidal nanostructures these optical achievements are accompanied by an excellent electronic material quality of the silicon absorber layer enabling open circuit voltages above 600 mV and solar cell device performances comparable to the planar reference device. For wavelengths smaller than 400 nm and higher than 700 nm optical achievements are translated into an enhanced quantum efficiency of the solar cell devices. Therefore, sinusoidal nanotextures are a well-balanced compromise between optical enhancement and maintained high electronic silicon material quality which opens a promising route for future optimizations in solar cell designs for silicon thin-film solar cells on glass.

Low-temperature electron cyclotron resonance plasma-enhanced chemical-vapor deposition silicon dioxide as gate insulator for polycrystalline silicon thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maiolo, L.; Pecora, A.; Fortunato, G.

2006-03-15

Silicon dioxide films have been deposited at temperatures below 270 deg. C in an electron cyclotron resonance (ECR) plasma reactor from O{sub 2}, SiH{sub 4}, and He gas mixture. Pinhole density analysis as a function of substrate temperature for different microwave powers was carried out. Films deposited at higher microwave power and at room temperature show defect densities (<7 pinhole/mm{sup 2}), ensuring low-temperature process integration on large area. From Fourier transform infrared analysis and thermal desorption spectrometry we also evaluated very low hydrogen content if compared to conventional rf-plasma-enhanced chemical-vapor-deposited (PECVD) SiO{sub 2} deposited at 350 deg. C. Electrical propertiesmore » have been measured in metal-oxide-semiconductor (MOS) capacitors, depositing SiO{sub 2} at RT as gate dielectric; breakdown electric fields >10 MV/cm and charge trapping at fields >6 MV/cm have been evaluated. From the study of interface quality in MOS capacitors, we found that even for low annealing temperature (200 deg. C), it is possible to considerably reduce the interface state density down to 5x10{sup 11} cm{sup -2} eV{sup -1}. To fully validate the ECR-PECVD silicon dioxide we fabricated polycrystalline silicon thin-film transistors using RT-deposited SiO{sub 2} as gate insulator. Different postdeposition thermal treatments have been studied and good device characteristics were obtained even for annealing temperature as low as 200 deg. C.« less

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

PubMed Central

Hazut, Ori; Agarwala, Arunava; Subramani, Thangavel; Waichman, Sharon; Yerushalmi, Roie

2013-01-01

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms. In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station. PMID:24326774

Process for depositing epitaxial alkaline earth oxide onto a substrate and structures prepared with the process

DOEpatents

McKee, Rodney A.; Walker, Frederick J.

1996-01-01

A process and structure involving a silicon substrate utilize molecular beam epitaxy (MBE) and/or electron beam evaporation methods and an ultra-high vacuum facility to grow a layup of epitaxial alkaline earth oxide films upon the substrate surface. By selecting metal constituents for the oxides and in the appropriate proportions so that the lattice parameter of each oxide grown closely approximates that of the substrate or base layer upon which oxide is grown, lattice strain at the film/film or film/substrate interface of adjacent films is appreciably reduced or relieved. Moreover, by selecting constituents for the oxides so that the lattice parameters of the materials of adjacent oxide films either increase or decrease in size from one parameter to another parameter, a graded layup of films can be grown (with reduced strain levels therebetween) so that the outer film has a lattice parameter which closely approximates that of, and thus accomodates the epitaxial growth of, a pervoskite chosen to be grown upon the outer film.

Electroless epitaxial etching for semiconductor applications

DOEpatents

McCarthy, Anthony M.

2002-01-01

A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Method for forming metallic silicide films on silicon substrates by ion beam deposition

DOEpatents

Zuhr, Raymond A.; Holland, Orin W.

1990-01-01

Metallic silicide films are formed on silicon substrates by contacting the substrates with a low-energy ion beam of metal ions while moderately heating the substrate. The heating of the substrate provides for the diffusion of silicon atoms through the film as it is being formed to the surface of the film for interaction with the metal ions as they contact the diffused silicon. The metallic silicide films provided by the present invention are contaminant free, of uniform stoichiometry, large grain size, and exhibit low resistivity values which are of particular usefulness for integrated circuit production.

Back-side hydrogenation technique for defect passivation in silicon solar cells

DOEpatents

Sopori, Bhushan L.

1994-01-01

A two-step back-side hydrogenation process includes the steps of first bombarding the back side of the silicon substrate with hydrogen ions with intensities and for a time sufficient to implant enough hydrogen atoms into the silicon substrate to potentially passivate substantially all of the defects and impurities in the silicon substrate, and then illuminating the silicon substrate with electromagnetic radiation to activate the implanted hydrogen, so that it can passivate the defects and impurities in the substrate. The illumination step also annihilates the hydrogen-induced defects. The illumination step is carried out according to a two-stage illumination schedule, the first or low-power stage of which subjects the substrate to electromagnetic radiation that has sufficient intensity to activate the implanted hydrogen, yet not drive the hydrogen from the substrate. The second or high-power illumination stage subjects the substrate to higher intensity electromagnetic radiation, which is sufficient to annihilate the hydrogen-induced defects and sinter/alloy the metal contacts.

Back-side hydrogenation technique for defect passivation in silicon solar cells

DOEpatents

Sopori, B.L.

1994-04-19

A two-step back-side hydrogenation process includes the steps of first bombarding the back side of the silicon substrate with hydrogen ions with intensities and for a time sufficient to implant enough hydrogen atoms into the silicon substrate to potentially passivate substantially all of the defects and impurities in the silicon substrate, and then illuminating the silicon substrate with electromagnetic radiation to activate the implanted hydrogen, so that it can passivate the defects and impurities in the substrate. The illumination step also annihilates the hydrogen-induced defects. The illumination step is carried out according to a two-stage illumination schedule, the first or low-power stage of which subjects the substrate to electromagnetic radiation that has sufficient intensity to activate the implanted hydrogen, yet not drive the hydrogen from the substrate. The second or high-power illumination stage subjects the substrate to higher intensity electromagnetic radiation, which is sufficient to annihilate the hydrogen-induced defects and sinter/alloy the metal contacts. 3 figures.

Multiwalled Carbon Nanotube/nanofiber Arrays as Conductive and Dry Adhesive Interface Materials

NASA Technical Reports Server (NTRS)

Tong, Tao; Zhao, Yang; Delzeit, Lance; Majumdar, Arun; Kashani, Ali

2004-01-01

We demonstrate the possibility of making conductive and dry adhesive interfaces between multiwalled carbon nanotube (MWNT) and nanofiber (MWNF) arrays grown by chemical vapor deposition with transition-metal as catalyst on highly Boron doped silicon substrates. The maximum observed adhesion force between MWNT and MWNF surfaces is 3.5 mN for an apparent contact area of 2 mm by 4 mm. The minimum contact resistance measured at the same time is approx.20 Omega. Contact resistances of MWNT-MWNT and MWNT-gold interfaces were also measured as pressure forces around several mN were applied at the interface. The resulting minimum contact resistances are on the same order but with considerable variation from sample to sample. For MWNT-MWNT contacts, a minimum contact resistance of approx.1 Omega is observed for a contact area of 2 mm by 1 mm. The relatively high contact resistances, considering the area density of the nanotubes, might be explained by the high cross-tube resistances at the contact interfaces.

Interface traps and quantum size effects on the retention time in nanoscale memory devices

PubMed Central

2013-01-01

Based on the analysis of Poisson equation, an analytical surface potential model including interface charge density for nanocrystalline (NC) germanium (Ge) memory devices with p-type silicon substrate has been proposed. Thus, the effects of Pb defects at Si(110)/SiO2, Si(111)/SiO2, and Si(100)/SiO2 interfaces on the retention time have been calculated after quantum size effects have been considered. The results show that the interface trap density has a large effect on the electric field across the tunneling oxide layer and leakage current. This letter demonstrates that the retention time firstly increases with the decrease in diameter of NC Ge and then rapidly decreases with the diameter when it is a few nanometers. This implies that the interface defects, its energy distribution, and the NC size should be seriously considered in the aim to improve the retention time from different technological processes. The experimental data reported in the literature support the theoretical expectation. PMID:23984827

Extensive ionic partitioning in interfaces that membranous and biomimetic surfaces form with electrolytes: Antitheses of the gold-electrolyte interface

NASA Astrophysics Data System (ADS)

Chilcott, Terry; Guo, Chuan; Coster, Hans

2013-04-01

Maxwell-Wagner modeling of electrical impedance measurements of tetradecane-electrolyte systems yielded three interfacial layers between the tetradecane layer and the bulk electrolytes of concentration ranging from 1-300 mM KCl whereas the gold-electrolyte system yielded only one layer. The conductivity and thickness for the surface layer were orders of magnitude different from that expected for the Gouy-Chapman layer and did not reflect dependencies of the Debye length on concentration. Conductivity values for the three layers were less than those of the bulk electrolyte but exhibited a dependency on concentration similar to that expected for the bulk. Thickness values for the layers indicate an interface extending ~106 Å into the bulk electrolyte, which contrasts with the gold-electrolyte interface that extended only 20-30 Å into the bulk. Maxwell-Wagner characterizations of both interfaces were consistent with spatial distributions of ionic partitioning arising from the Born energy as determined by the dielectric properties of the substrates and electrolyte. The distributions for the membranous and silicon interfaces were similar but the antitheses of that for the gold interface.

Structural and electrical properties of atomic layer deposited Al-doped ZrO2 films and of the interface with TaN electrode

NASA Astrophysics Data System (ADS)

Spiga, S.; Rao, R.; Lamagna, L.; Wiemer, C.; Congedo, G.; Lamperti, A.; Molle, A.; Fanciulli, M.; Palma, F.; Irrera, F.

2012-07-01

Al-doped ZrO2 (Al-ZrO2) films deposited by atomic layer deposition onto silicon substrates and the interface with the TaN metal gate are investigated. In particular, structural properties of as-grown and annealed films in the 6-26 nm thickness range, as well as leakage and capacitive behavior of metal-oxide-semiconductor stacks are characterized. As-deposited Al-ZrO2 films in the mentioned thickness range are amorphous and crystallize in the ZrO2 cubic phase after thermal treatment at 900 °C. Correspondingly, the dielectric constant (k) value increases from 20 ± 1 to 27 ± 2. The Al-ZrO2 layers exhibit uniform composition through the film thickness and are thermally stable on Si, whereas chemical reactions take place at the TaN/Al-ZrO2 interface. A transient capacitance technique is adopted for monitoring charge trapping and flat band instability at short and long time scales. The role of traps nearby the TaN/Al-ZrO2 interface is discussed and compared with other metal/high-k oxide films. Further, analytical modeling of the flat band voltage shift with a power-law dependence on time allows extracting features of bulk traps close to the silicon/oxide interface, which exhibit energy levels in the 1.4-1.9 eV range above the valence band of the Al-ZrO2.

High quality silicon-based substrates for microwave and millimeter wave passive circuits

NASA Astrophysics Data System (ADS)

Belaroussi, Y.; Rack, M.; Saadi, A. A.; Scheen, G.; Belaroussi, M. T.; Trabelsi, M.; Raskin, J.-P.

2017-09-01

Porous silicon substrate is very promising for next generation wireless communication requiring the avoidance of high-frequency losses originating from the bulk silicon. In this work, new variants of porous silicon (PSi) substrates have been introduced. Through an experimental RF performance, the proposed PSi substrates have been compared with different silicon-based substrates, namely, standard silicon (Std), trap-rich (TR) and high resistivity (HR). All of the mentioned substrates have been fabricated where identical samples of CPW lines have been integrated on. The new PSi substrates have shown successful reduction in the substrate's effective relative permittivity to values as low as 3.7 and great increase in the substrate's effective resistivity to values higher than 7 kΩ cm. As a concept proof, a mm-wave bandpass filter (MBPF) centred at 27 GHz has been integrated on the investigated substrates. Compared with the conventional MBPF implemented on standard silicon-based substrates, the measured S-parameters of the PSi-based MBPF have shown high filtering performance, such as a reduction in insertion loss and an enhancement of the filter selectivity, with the joy of having the same filter performance by varying the temperature. Therefore, the efficiency of the proposed PSi substrates has been well highlighted. From 1994 to 1995, she was assistant of physics at (USTHB), Algiers . From 1998 to 2011, she was a Researcher at characterization laboratory in ionized media and laser division at the Advanced Technologies Development Center. She has integrated the Analog Radio Frequency Integrated Circuits team as Researcher since 2011 until now in Microelectronic and Nanotechnology Division at Advanced Technologies Development Center (CDTA), Algiers. She has been working towards her Ph.D. degree jointly at CDTA and Ecole Nationale Polytechnique, Algiers, since 2012. Her research interest includes fabrication and characterization of microwave passive devices on porous silicon as new substrate, such as characterization of FinFET components.

Electronic and chemical structure of metal-silicon interfaces

NASA Technical Reports Server (NTRS)

Grunthaner, P. J.; Grunthaner, F. J.

1984-01-01

This paper reviews our current understanding of the near-noble metal silicides and the interfaces formed with Si(100). Using X-ray photoemission spectroscopy, we compare the chemical composition and electronic structure of the room temperature metal-silicon and reacted silicide-silicon interfaces. The relationship between the interfacial chemistry and the Schottky barrier heights for this class of metals on silicon is explored.

Microcrystalline silicon growth for heterojunction solar cells

NASA Technical Reports Server (NTRS)

Iles, P. A.; Leung, D. C.; Fang, P. H.

1984-01-01

A single source of evaporation with B mixed with highly doped Si is used instead of the coevaporation of separate Si and B sources to reduce possible carbon contamination. The results of both the heterojunction or heteroface structures, however, are similar when evaporation is used. The best Voc of the heterojunction is about 460mV and no improvement in Voc in the heteroface structure is observed. Slight Voc degradation occurred. A study of the p m-Si/p c-Si structure showed a negative Voc in many cases. The interface properties between the two materials are such that instead of repelling minority carriers from the substrate carrier, collection actually occurred. Another study of cells made in the part of substrates not covered by n-Si results in performance lower than the controls. This indicates possible substrate degradation in the process.

Insulators obtained by electron cyclotron resonance plasmas on Si or GaAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Diniz, J.A.; Doi, I.; Swart, J.W

2003-03-15

Silicon oxynitride (SiO{sub x}N{sub y}) and nitride (SiN{sub x}) insulators have been deposited or grown (with or without silane in the gas mixture, respectively) by electron cyclotron resonance (ECR) plasmas on Si and/or GaAs substrates at room temperature (20 deg. C) and low pressures (up to 10 mTorr). Chemical bonding characteristics of the SiO{sub x}N{sub y} and SiN{sub x} films were evaluated using Fourier transform infrared spectrometry (FTIR). The profile measurements determined the film thickness, the deposition (or oxidation) rate and the etch rates in buffered HF (BHF). The refractive indexes and the thicknesses were determined by ellipsometry. The effectivemore » interface charge densities were determined by capacitance-voltage (C-V) measurements. With these processes and analyses, different films were obtained and optimized. Suitable gate insulators for metal-insulator-semiconductor (MIS) devices with low interface charge densities were developed: (a) SiN{sub x} films deposited by ECR-chemical vapor deposition (ECR-PECVD) on GaAs substrates; (b) SiO{sub x}N{sub y} insulators obtained by low-energy molecular nitrogen ion ({sup 28}N{sub 2}{sup +}) implantation (energy of 5 keV and dose of 1x10{sup 15}/cm{sup 2}) in Si substrates prior to high-density O{sub 2} ECR plasma oxidation; and (c) SiO{sub x}N{sub y} insulators grown (without silane in the gas mixture) by O{sub 2}/N{sub 2}/Ar ECR plasma 'oxynitridation'. Furthermore, some SiN{sub x} films also present very good masking characteristics for local oxidation of silicon process.« less

Method for rapid, controllable growth and thickness, of epitaxial silicon films

DOEpatents

Wang, Qi [Littleton, CO; Stradins, Paul [Golden, CO; Teplin, Charles [Boulder, CO; Branz, Howard M [Boulder, CO

2009-10-13

A method of producing epitaxial silicon films on a c-Si wafer substrate using hot wire chemical vapor deposition by controlling the rate of silicon deposition in a temperature range that spans the transition from a monohydride to a hydrogen free silicon surface in a vacuum, to obtain phase-pure epitaxial silicon film of increased thickness is disclosed. The method includes placing a c-Si substrate in a HWCVD reactor chamber. The method also includes supplying a gas containing silicon at a sufficient rate into the reaction chamber to interact with the substrate to deposit a layer containing silicon thereon at a predefined growth rate to obtain phase-pure epitaxial silicon film of increased thickness.

Electrochemical Fabrication of Nanostructures on Porous Silicon for Biochemical Sensing Platforms.

PubMed

Ko, Euna; Hwang, Joonki; Kim, Ji Hye; Lee, Joo Heon; Lee, Sung Hwan; Tran, Van-Khue; Chung, Woo Sung; Park, Chan Ho; Choo, Jaebum; Seong, Gi Hun

2016-01-01

We present a method for the electrochemical patterning of gold nanoparticles (AuNPs) or silver nanoparticles (AgNPs) on porous silicon, and explore their applications in: (1) the quantitative analysis of hydroxylamine as a chemical sensing electrode and (2) as a highly sensitive surface-enhanced Raman spectroscopy (SERS) substrate for Rhodamine 6G. For hydroxylamine detection, AuNPs-porous silicon can enhance the electrochemical oxidation of hydroxylamine. The current changed linearly for concentrations ranging from 100 μM to 1.32 mM (R(2) = 0.995), and the detection limit was determined to be as low as 55 μM. When used as SERS substrates, these materials also showed that nanoparticles decorated on porous silicon substrates have more SERS hot spots than those decorated on crystalline silicon substrates, resulting in a larger SERS signal. Moreover, AgNPs-porous silicon provided five-times higher signal compared to AuNPs-porous silicon. From these results, we expect that nanoparticles decorated on porous silicon substrates can be used in various types of biochemical sensing platforms.

Method of Forming Three-Dimensional Semiconductors Structures

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor)

2002-01-01

Silicon and metal are coevaporated onto a silicon substrate in a molecular beam epitaxy system with a larger than stoichiometric amount of silicon so as to epitaxially grow columns of metal silicide embedded in a matrix of single crystal, epitaxially grown silicon. Higher substrate temperatures and lower deposition rates yield larger columns that are farther apart while more silicon produces smaller columns. Column shapes and locations are selected by seeding the substrate with metal silicide starting regions. A variety of 3-dimensional, exemplary electronic devices are disclosed.

Method of bonding silver to glass and mirrors produced according to this method

DOEpatents

Pitts, J.R.; Thomas, T.M.; Czanderna, A.W.

1984-07-31

A method for adhering silver to a glass substrate for producing mirrors includes attaining a silicon enriched substrate surface by reducing the oxygen therein in a vacuum and then vacuum depositing a silver layer onto the silicon enriched surface. The silicon enrichment can be attained by electron beam bombardment, ion beam bombardment, or neutral beam bombardment. It can also be attained by depositing a metal, such as aluminum, on the substrate surface, allowing the metal to oxidize by pulling oxygen from the substrate surface, thereby leaving a silicon enriched surface, and then etching or eroding the metal oxide layer away to expose the silicon enriched surface. Ultraviolet rays can be used to maintain dangling silicon bonds on the enriched surface until covalent bonding with the silver can occur. This disclosure also includes encapsulated mirrors with diffusion layers built therein. One of these mirrors is assembled on a polymer substrate.

Method of bonding silver to glass and mirrors produced according to this method

DOEpatents

Pitts, John R.; Thomas, Terence M.; Czanderna, Alvin W.

1985-01-01

A method for adhering silver to a glass substrate for producing mirrors includes attaining a silicon enriched substrate surface by reducing the oxygen therein in a vacuum and then vacuum depositing a silver layer onto the silicon enriched surface. The silicon enrichment can be attained by electron beam bombardment, ion beam bombardment, or neutral beam bombardment. It can also be attained by depositing a metal, such as aluminum, on the substrate surface, allowing the metal to oxidize by pulling oxygen from the substrate surface, thereby leaving a silicon enriched surface, and then etching or eroding the metal oxide layer away to expose the silicon enriched surface. Ultraviolet rays can be used to maintain dangling silicon bonds on the enriched surface until covalent bonding with the silver can occur. This disclosure also includes encapsulated mirrors with diffusion layers built therein. One of these mirrors is assembled on a polymer substrate.

Investigations of different doping concentration of phosphorus and boron into silicon substrate on the variable temperature Raman characteristics

NASA Astrophysics Data System (ADS)

Li, Xiaoli; Ding, Kai; Liu, Jian; Gao, Junxuan; Zhang, Weifeng

2018-01-01

Different doped silicon substrates have different device applications and have been used to fabricate solar panels and large scale integrated circuits. The thermal transport in silicon substrates are dominated by lattice vibrations, doping type, and doping concentration. In this paper, a variable-temperature Raman spectroscopic system is applied to record the frequency and linewidth changes of the silicon peak at 520 cm-1 in five chips of silicon substrate with different doping concentration of phosphorus and boron at the 83K to 1473K temperature range. The doping has better heat sensitive to temperature on the frequency shift over the low temperature range from 83K to 300K but on FWHM in high temperature range from 300K to 1473K. The results will be helpful for fundamental study and practical applications of silicon substrates.

Effects of patterning induced stress relaxation in strained SOI/SiGe layers and substrate

NASA Astrophysics Data System (ADS)

Hermann, P.; Hecker, M.; Renn, F.; Rölke, M.; Kolanek, K.; Rinderknecht, J.; Eng, L. M.

2011-06-01

Local stress fields in strained silicon structures important for CMOS technology are essentially related to size effects and properties of involved materials. In the present investigation, Raman spectroscopy was utilized to analyze the stress distribution within strained silicon (sSi) and silicon-germanium (SiGe) island structures. As a result of the structuring of initially unpatterned strained films, a size-dependent relaxation of the intrinsic film stresses was obtained in agreement with model calculations. This changed stress state in the features also results in the appearance of opposing stresses in the substrate underneath the islands. Even for strained island structures on top of silicon-on-insulator (SOI) wafers, corresponding stresses in the silicon substrate underneath the oxide were detected. Within structures, the stress relaxation is more pronounced for islands on SOI substrates as compared to those on bulk silicon substrates.

Fabrication of thermal microphotonic sensors and sensor arrays

DOEpatents

Shaw, Michael J.; Watts, Michael R.; Nielson, Gregory N.

2010-10-26

A thermal microphotonic sensor is fabricated on a silicon substrate by etching an opening and a trench into the substrate, and then filling in the opening and trench with silicon oxide which can be deposited or formed by thermally oxidizing a portion of the silicon substrate surrounding the opening and trench. The silicon oxide forms a support post for an optical resonator which is subsequently formed from a layer of silicon nitride, and also forms a base for an optical waveguide formed from the silicon nitride layer. Part of the silicon substrate can be selectively etched away to elevate the waveguide and resonator. The thermal microphotonic sensor, which is useful to detect infrared radiation via a change in the evanescent coupling of light between the waveguide and resonator, can be formed as a single device or as an array.

Improved process for epitaxial deposition of silicon on prediffused substrates

NASA Technical Reports Server (NTRS)

Clarke, M. G.; Halsor, J. L.; Word, J. C.

1968-01-01

Process for fabricating integrated circuits uniformly deposits silicon epitaxially on prediffused substrates without affecting the sublayer diffusion pattern. Two silicon deposits from different sources, and deposited at different temperatures, protect the sublayer pattern from the silicon tetrachloride reaction.

Gauge Factor and Stretchability of Silicon-on-Polymer Strain Gauges

PubMed Central

Yang, Shixuan; Lu, Nanshu

2013-01-01

Strain gauges are widely applied to measure mechanical deformation of structures and specimens. While metallic foil gauges usually have a gauge factor slightly over 2, single crystalline silicon demonstrates intrinsic gauge factors as high as 200. Although silicon is an intrinsically stiff and brittle material, flexible and even stretchable strain gauges have been achieved by integrating thin silicon strips on soft and deformable polymer substrates. To achieve a fundamental understanding of the large variance in gauge factor and stretchability of reported flexible/stretchable silicon-on-polymer strain gauges, finite element and analytically models are established to reveal the effects of the length of the silicon strip, and the thickness and modulus of the polymer substrate. Analytical results for two limiting cases, i.e., infinitely thick substrate and infinitely long strip, have found good agreement with FEM results. We have discovered that strains in silicon resistor can vary by orders of magnitude with different substrate materials whereas strip length or substrate thickness only affects the strain level mildly. While the average strain in silicon reflects the gauge factor, the maximum strain in silicon governs the stretchability of the system. The tradeoff between gauge factor and stretchability of silicon-on-polymer strain gauges has been proposed and discussed. PMID:23881128

Dip-Coating Fabrication of Solar Cells

NASA Technical Reports Server (NTRS)

Koepke, B.; Suave, D.

1982-01-01

Inexpensive silicon solar cells made by simple dip technique. Cooling shoes direct flow of helium on graphite-coated ceramic substrate to solidify film of liquid silicon on graphite surface as substrate is withdrawn from molten silicon. After heaters control cooling of film and substrate to prevent cracking. Gas jets exit at points about 10 mm from substrate surfaces and 6 to 10 mm above melt surface.

Interfacial phonon scattering and transmission loss in >1 μm thick silicon-on-insulator thin films

NASA Astrophysics Data System (ADS)

Jiang, Puqing; Lindsay, Lucas; Huang, Xi; Koh, Yee Kan

2018-05-01

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1-10 μm and a temperature range of 100-300 K. The Si /SiO2 interface roughness was determined to be 0.11 ±0.04 nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

Synthesis of Poly-Silicon Thin Films on Glass Substrate Using Laser Initiated Metal Induced Crystallization of Amorphous Silicon for Space Power Application

NASA Technical Reports Server (NTRS)

Abu-Safe, Husam H.; Naseem, Hameed A.; Brown, William D.

2007-01-01

Poly-silicon thin films on glass substrates are synthesized using laser initiated metal induced crystallization of hydrogenated amorphous silicon films. These films can be used to fabricate solar cells on low cost glass and flexible substrates. The process starts by depositing 200 nm amorphous silicon films on the glass substrates. Following this, 200 nm of sputtered aluminum films were deposited on top of the silicon layers. The samples are irradiated with an argon ion cw laser beam for annealing. Laser power densities ranging from 4 to 9 W/cm2 were used in the annealing process. Each area on the sample is irradiated for a different exposure time. Optical microscopy was used to examine any cracks in the films and loss of adhesion to the substrates. X-Ray diffraction patterns from the initial results indicated the crystallization in the films. Scanning electron microscopy shows dendritic growth. The composition analysis of the crystallized films was conducted using Energy Dispersive x-ray Spectroscopy. The results of poly-silicon films synthesis on space qualified flexible substrates such as Kapton are also presented.

Enhanced Raman scattering in porous silicon grating.

PubMed

Wang, Jiajia; Jia, Zhenhong; Lv, Changwu

2018-03-19

The enhancement of Raman signal on monocrystalline silicon gratings with varying groove depths and on porous silicon grating were studied for a highly sensitive surface enhanced Raman scattering (SERS) response. In the experiment conducted, porous silicon gratings were fabricated. Silver nanoparticles (Ag NPs) were then deposited on the porous silicon grating to enhance the Raman signal of the detective objects. Results show that the enhancement of Raman signal on silicon grating improved when groove depth increased. The enhanced performance of Raman signal on porous silicon grating was also further improved. The Rhodamine SERS response based on Ag NPs/ porous silicon grating substrates was enhanced relative to the SERS response on Ag NPs/ porous silicon substrates. Ag NPs / porous silicon grating SERS substrate system achieved a highly sensitive SERS response due to the coupling of various Raman enhancement factors.

The Selective Epitaxy of Silicon at Low Temperatures.

NASA Astrophysics Data System (ADS)

Lou, Jen-Chung

1991-01-01

This dissertation has developed a process for the selective epitaxial growth (SEG) of silicon at low temperatures using a dichlorosilane-hydrogen mixture in a hot-wall low pressure chemical vapor deposition (LPCVD) reactor. Some basic issues concerning the quality of epilayers --substrate preparation, ex-situ and in-situ cleaning, and deposition cycle, have been studied. We find it necessary to use a plasma etch to open epitaxial windows for the SEG of Si. A cycled plasma etch, a thin sacrificial oxide growth, and an oxide etching step can completely remove plasma-etch-induced surface damage and contaminants, which result in high quality epilayers. A practical wafer cleaning step is developed for low temperature Si epitaxial growth. An ex-situ HF vapor treatment can completely remove chemical oxide from the silicon surface and retard the reoxidation of the silicon surface. An in-situ low-concentration DCS cycle can aid in decomposition of surface oxide during a 900 ^circC H_2 prebake step. An HF vapor treatment combined with a low-concentration of DCS cycle consistently achieves defect-free epilayers at 850^circC and lower temperatures. We also show that a BF_sp{2}{+ } or F^+ ion implantation is a potential ex-situ wafer cleaning process for SEG of Si at low temperatures. The mechanism for the formation of surface features on Si epilayers is also discussed. Based on O ^+ ion implantation, we showed that the oxygen incorporation in silicon epilayers suppresses the Si growth rate. Therefore, we attribute the formation of surface features to the local reduction of the Si growth rate due to the dissolution of oxide islands at the epi/substrate interface. Finally, with this developed process for the SEG of silicon, defect-free overgrown epilayers are also obtained. This achievement demonstrates the feasibility for the future silicon-on-oxide (SOI) manufacturing technology.

Process for Smoothing an Si Substrate after Etching of SiO2

NASA Technical Reports Server (NTRS)

Turner, Tasha; Wu, Chi

2003-01-01

A reactive-ion etching (RIE) process for smoothing a silicon substrate has been devised. The process is especially useful for smoothing those silicon areas that have been exposed by etching a pattern of holes in a layer of silicon dioxide that covers the substrate. Applications in which one could utilize smooth silicon surfaces like those produced by this process include fabrication of optical waveguides, epitaxial deposition of silicon on selected areas of silicon substrates, and preparation of silicon substrates for deposition of adherent metal layers. During etching away of a layer of SiO2 that covers an Si substrate, a polymer becomes deposited on the substrate, and the substrate surface becomes rough (roughness height approximately equal to 50 nm) as a result of over-etching or of deposition of the polymer. While it is possible to smooth a silicon substrate by wet chemical etching, the undesired consequences of wet chemical etching can include compromising the integrity of the SiO2 sidewalls and undercutting of the adjacent areas of the silicon dioxide that are meant to be left intact. The present RIE process results in anisotropic etching that removes the polymer and reduces height of roughness of the silicon substrate to less than 10 nm while leaving the SiO2 sidewalls intact and vertical. Control over substrate versus sidewall etching (in particular, preferential etching of the substrate) is achieved through selection of process parameters, including gas flow, power, and pressure. Such control is not uniformly and repeatably achievable in wet chemical etching. The recipe for the present RIE process is the following: Etch 1 - A mixture of CF4 and O2 gases flowing at rates of 25 to 75 and 75 to 125 standard cubic centimeters per minute (stdcm3/min), respectively; power between 44 and 55 W; and pressure between 45 and 55 mtorr (between 6.0 and 7.3 Pa). The etch rate lies between approximately equal to 3 and approximately equal to 6 nm/minute. Etch 2 - O2 gas flowing at 75 to 125 stdcm3/min, power between 44 and 55 W, and pressure between 50 and 100 mtorr (between 6.7 and 13.3 Pa).

A Differential Resonant Accelerometer with Low Cross-Interference and Temperature Drift

PubMed Central

Li, Bo; Zhao, Yulong; Li, Cun; Cheng, Rongjun; Sun, Dengqiang; Wang, Songli

2017-01-01

Presented in this paper is a high-performance resonant accelerometer with low cross-interference, low temperature drift and digital output. The sensor consists of two quartz double-ended tuning forks (DETFs) and a silicon substrate. A new differential silicon substrate is proposed to reduce the temperature drift and cross-interference from the undesirable direction significantly. The natural frequency of the quartz DETF is theoretically calculated, and then the axial stress on the vibration beams is verified through finite element method (FEM) under a 100 g acceleration which is loaded on x-axis, y-axis and z-axis, respectively. Moreover, sensor chip is wire-bonded to a printed circuit board (PCB) which contains two identical oscillating circuits. In addition, a steel shell is selected to package the sensor for experiments. Benefiting from the distinctive configuration of the differential structure, the accelerometer characteristics such as temperature drift and cross-interface are improved. The experimental results demonstrate that the cross-interference is lower than 0.03% and the temperature drift is about 18.16 ppm/°C. PMID:28106798

High-Temperature Annealing as a Method for the Silicon Nanoclusters Growth in Stoichiometric Silicon Dioxide

NASA Astrophysics Data System (ADS)

Ivanova, E. V.; Dementev, P. A.; Sitnikova, A. A.; Aleksandrov, O. V.; Zamoryanskaya, M. V.

2018-07-01

A method for the growth of nanocomposite layers in stoichiometric amorphous silicon dioxide is proposed. It is shown that, after annealing at a temperature of 1150°C in nitrogen atmosphere, a layer containing silicon nanoclusters is formed. Silicon nanoclusters have a crystal structure and a size of 3-6 nm. In a film grown on a n-type substrate, a layer of silicon nanoclusters with a thickness of about 10 nm is observed. In the case of a film grown on a p-type substrate, a nanocomposite layer with a thickness of about 100 nm is observed. The difference in the formation of a nanocomposite layer in films on various substrates is associated with the doping of silicon dioxide with impurities from the substrate during the growth of the film. The formation of the nanocomposite layer was confirmed by transmission electron microscopy, XPS and local cathodoluminescence studies.

Selective etching of silicon carbide films

DOEpatents

Gao, Di; Howe, Roger T.; Maboudian, Roya

2006-12-19

A method of etching silicon carbide using a nonmetallic mask layer. The method includes providing a silicon carbide substrate; forming a non-metallic mask layer by applying a layer of material on the substrate; patterning the mask layer to expose underlying areas of the substrate; and etching the underlying areas of the substrate with a plasma at a first rate, while etching the mask layer at a rate lower than the first rate.

The thermal conductivity of chemical-vapor-deposited diamond films on silicon

NASA Astrophysics Data System (ADS)

Graebner, J. E.; Mucha, J. A.; Seibles, L.; Kammlott, G. W.

1992-04-01

The thermal conductivity of chemical-vapor-deposited diamond films on silicon is measured for the case of heat flow parallel to the plane of the film. A new technique uses thin-film heaters and thermometers on a portion of the film which is made to be free standing by etching away the substrate. Effects of thermal radiation are carefully avoided by choosing the length scale properly. Data for several films yield thermal conductivities in the range 2-6 W/cm C. This is comparable to copper (4 W/cm C) and is in a range that would be useful as a thin-film dielectric material, provided that the interface thermal resistance can be minimized. The conductivity varies inversely with the growth rate and the Raman linewidth.

Transfer of micro and nano-photonic silicon nanomembrane waveguide devices on flexible substrates.

PubMed

Ghaffari, Afshin; Hosseini, Amir; Xu, Xiaochuan; Kwong, David; Subbaraman, Harish; Chen, Ray T

2010-09-13

This paper demonstrates transfer of optical devices without extra un-patterned silicon onto low-cost, flexible plastic substrates using single-crystal silicon nanomembranes. Employing this transfer technique, stacking two layers of silicon nanomembranes with photonic crystal waveguide in the first layer and multi mode interference couplers in the second layer is shown, respectively. This technique is promising to realize high density integration of multilayer hybrid structures on flexible substrates.

Giant Dirac point shift of graphene phototransistors by doped silicon substrate current

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shimatani, Masaaki; Ogawa, Shinpei, E-mail: Ogawa.Shimpei@eb.MitsubishiElectric.co.jp; Fujisawa, Daisuke

2016-03-15

Graphene is a promising new material for photodetectors due to its excellent optical properties and high-speed response. However, graphene-based phototransistors have low responsivity due to the weak light absorption of graphene. We have observed a giant Dirac point shift upon white light illumination in graphene-based phototransistors with n-doped Si substrates, but not those with p-doped substrates. The source-drain current and substrate current were investigated with and without illumination for both p-type and n-type Si substrates. The decay time of the drain-source current indicates that the Si substrate, SiO{sub 2} layer, and metal electrode comprise a metal-oxide-semiconductor (MOS) capacitor due tomore » the presence of defects at the interface between the Si substrate and SiO{sub 2} layer. The difference in the diffusion time of the intrinsic major carriers (electrons) and the photogenerated electron-hole pairs to the depletion layer delays the application of the gate voltage to the graphene channel. Therefore, the giant Dirac point shift is attributed to the n-type Si substrate current. This phenomenon can be exploited to realize high-performance graphene-based phototransistors.« less

Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

PubMed Central

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

PubMed

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Surface morphology of erbium silicide

NASA Technical Reports Server (NTRS)

Lau, S. S.; Pai, C. S.; Wu, C. S.; Kuech, T. F.; Liu, B. X.

1982-01-01

The surface of rare-earth silicides (Er, Tb, etc.), formed by the reaction of thin-film metal layers with a silicon substrate, is typically dominated by deep penetrating, regularly shaped pits. These pits may have a detrimental effect on the electronic performance of low Schottky barrier height diodes utilizing such silicides on n-type Si. This study suggests that contamination at the metal-Si or silicide-Si interface is the primary cause of surface pitting. Surface pits may be reduced in density or eliminated entirely through either the use of Si substrate surfaces prepared under ultrahigh vacuum conditions prior to metal deposition and silicide formation or by means of ion irradiation techniques. Silicide layers formed by these techniques possess an almost planar morphology.

Process for utilizing low-cost graphite substrates for polycrystalline solar cells

NASA Technical Reports Server (NTRS)

Chu, T. L. (Inventor)

1978-01-01

Low cost polycrystalline silicon solar cells supported on substrates were prepared by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical grade polycrystalline silicon, graphite and steel coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures thereof such that p-n junction devices were formed which effectively convert solar energy to electrical energy. To improve the conversion efficiency of the polycrystalline silicon solar cells, the crystallite size in the silicon was substantially increased by melting and solidifying a base layer of polycrystalline silicon before depositing the layers which form the p-n junction.

Silicon based substrate with calcium aluminosilicate/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Miller, Robert Alden (Inventor); Jacobson, Nathan S. (Inventor); Smialek, James L. (Inventor); Opila, Elizabeth J. (Inventor); Lee, Kang N. (Inventor); Nagaraj, Bangalore A. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2001-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a calcium alumino silicate.

Silicon based substrate with environmental/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Jacobson, Nathan S. (Inventor); Bansal, Narottam P. (Inventor); Opila, Elizabeth J. (Inventor); Smialek, James L. (Inventor); Lee, Kang N. (Inventor); Spitsberg, Irene T. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2002-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

Silicon based substrate with environmental/ thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Jacobson, Nathan S. (Inventor); Bansal, Nanottam P. (Inventor); Opila, Elizabeth J. (Inventor); Smialek, James L. (Inventor); Lee, Kang N. (Inventor); Spitsberg, Irene T. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2002-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

Buried oxide layer in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2001-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Silicon based substrate with calcium aluminosilicate environmental/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Miller, Robert Alden (Inventor); Jacobson, Nathan S. (Inventor); Smialek, James L. (Inventor); Opila, Elizabeth J. (Inventor); Lee, Kang N. (Inventor); Nagaraj, Bangalore A. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2001-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a calcium alumino silicate.

Chemical resistivity of self-assembled monolayer covalently attached to silicon substrate to hydrofluoric acid and ammonium fluoride

NASA Astrophysics Data System (ADS)

Saito, N.; Youda, S.; Hayashi, K.; Sugimura, H.; Takai, O.

2003-06-01

Self-assembled monolayers (SAMs) were prepared on hydrogen-terminated silicon substrates through chemical vapor deposition using 1-hexadecene (HD) as a precursor. The HD-SAMs prepared in an atmosphere under a reduced pressure (≈50 Pa) showed better chemical resistivities to hydrofluoric acid and ammonium fluoride (NH 4F) solutions than that of an organosilane SAM formed on oxide-covered silicon substrates. The surface covered with the HD-SAM was micro-patterned by vacuum ultraviolet photolithography and consequently divided into two areas terminated with HD-SAM or silicon dioxide. This micro-patterned sample was immersed in a 40 vol.% NH 4F aqueous solution. Surface images obtained by an optical microscopy clearly show that the micro-patterns of HD-SAM/silicon dioxide were successfully transferred into the silicon substrate.

Wet-chemical systems and methods for producing black silicon substrates

DOEpatents

Yost, Vernon; Yuan, Hao-Chih; Page, Matthew

2015-05-19

A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

Ultrasonic Measurement Of Silicon-Growth Interface

NASA Technical Reports Server (NTRS)

Heyser, Richard C.

1988-01-01

Position of interface between silicon melt and growing ribbon of silicon measured with aid of reflected ultrasound, according to proposal. Reflections reveal characteristics of ribbon and melt. Ultrasound pulses travel through rods to silicon ribbon growing by dendritic-web process. Rods return reflections of pulses to sonic transducers. Isolate transducers thermally, but not acoustically, from hot silicon melt.

Structure, growth kinetics, and ledge flow during vapor-solid-solid growth of copper-catalyzed silicon nanowires.

PubMed

Wen, C-Y; Reuter, M C; Tersoff, J; Stach, E A; Ross, F M

2010-02-10

We use real-time observations of the growth of copper-catalyzed silicon nanowires to determine the nanowire growth mechanism directly and to quantify the growth kinetics of individual wires. Nanowires were grown in a transmission electron microscope using chemical vapor deposition on a copper-coated Si substrate. We show that the initial reaction is the formation of a silicide, eta'-Cu(3)Si, and that this solid silicide remains on the wire tips during growth so that growth is by the vapor-solid-solid mechanism. Individual wire directions and growth rates are related to the details of orientation relation and catalyst shape, leading to a rich morphology compared to vapor-liquid-solid grown nanowires. Furthermore, growth occurs by ledge propagation at the silicide/silicon interface, and the ledge propagation kinetics suggest that the solubility of precursor atoms in the catalyst is small, which is relevant to the fabrication of abrupt heterojunctions in nanowires.

High-performance silicon nanowire field-effect transistor with silicided contacts

NASA Astrophysics Data System (ADS)

Rosaz, G.; Salem, B.; Pauc, N.; Gentile, P.; Potié, A.; Solanki, A.; Baron, T.

2011-08-01

Undoped silicon nanowire (Si NW) field-effect transistors (FETs) with a back-gate configuration have been fabricated and characterized. A thick (200 nm) Si3N4 layer was used as a gate insulator and a p++ silicon substrate as a back gate. Si NWs have been grown by the chemical vapour deposition method using the vapour-liquid-solid mechanism and gold as a catalyst. Metallic contacts have been deposited using Ni/Al (80 nm/120 nm) and characterized before and after an optimized annealing step at 400 °C, which resulted in a great decrease in the contact resistance due to the newly formed nickel silicide/Si interface at source and drain. These optimized devices show a good hole mobility of around 200 cm2 V-1 s-1, in the same range as the bulk material, with a good ON current density of about 28 kA cm-2. Finally, hysteretic behaviour of NW channel conductance is discussed to explain the importance of NW surface passivation.

High-directionality fiber-chip grating coupler with interleaved trenches and subwavelength index-matching structure.

PubMed

Benedikovic, Daniel; Alonso-Ramos, Carlos; Cheben, Pavel; Schmid, Jens H; Wang, Shurui; Xu, Dan-Xia; Lapointe, Jean; Janz, Siegfried; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, J Gonzalo; Molina-Fernández, Iñigo; Fédéli, Jean-Marc; Vivien, Laurent; Dado, Milan

2015-09-15

We present the first experimental demonstration of a new fiber-chip grating coupler concept that exploits the blazing effect by interleaving the standard full (220 nm) and shallow etch (70 nm) trenches in a 220 nm thick silicon layer. The high directionality is obtained by controlling the separation between the deep and shallow trenches to achieve constructive interference in the upward direction and destructive interference toward the silicon substrate. Utilizing this concept, the grating directionality can be maximized independent of the bottom oxide thickness. The coupler also includes a subwavelength-engineered index-matching region, designed to reduce the reflectivity at the interface between the injection waveguide and the grating. We report a measured fiber-chip coupling efficiency of -1.3  dB, the highest coupling efficiency achieved to date for a surface grating coupler in a 220 nm silicon-on-insulator platform fabricated in a conventional dual-etch process without high-index overlays or bottom mirrors.

Photovoltaic device using single wall carbon nanotubes and method of fabricating the same

DOEpatents

Biris, Alexandru S.; Li, Zhongrui

2012-11-06

A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.

Surface thiolation of silicon for antifouling application.

PubMed

Zhang, Xiaoning; Gao, Pei; Hollimon, Valerie; Brodus, DaShan; Johnson, Arion; Hu, Hongmei

2018-02-07

Thiol groups grafted silicon surface was prepared as previously described. 1H,1H,2H,2H-perfluorodecanethiol (PFDT) molecules were then immobilized on such a surface through disulfide bonds formation. To investigate the contribution of PFDT coating to antifouling, the adhesion behaviors of Botryococcus braunii (B. braunii) and Escherichia coli (E. coli) were studied through biofouling assays in the laboratory. The representative microscope images suggest reduced B. braunii and E. coli accumulation densities on PFDT integrated silicon substrate. However, the antifouling performance of PFDT integrated silicon substrate decreased over time. By incubating the aged substrate in 10 mM TCEP·HCl solution for 1 h, the fouled PFDT coating could be removed as the disulfide bonds were cleaved, resulting in reduced absorption of algal cells and exposure of non-fouled silicon substrate surface. Our results indicate that the thiol-terminated substrate can be potentially useful for restoring the fouled surface, as well as maximizing the effective usage of the substrate.

CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Research on the boron contamination at the p/i interface of microcrystalline silicon solar cells deposited in a single PECVD chamber

NASA Astrophysics Data System (ADS)

Zhang, Xiao-Dan; Sun, Fu-He; Wei, Chang-Chun; Sun, Jian; Zhang, De-Kun; Geng, Xin-Hua; Xiong, Shao-Zhen; Zhao, Ying

2009-10-01

This paper studies boron contamination at the interface between the p and i layers of μc-Si:H solar cells deposited in a single-chamber PECVD system. The boron depth profile in the i layer was measured by Secondary Ion Mass Spectroscopy. It is found that the mixed-phase μc-Si:H materials with 40% crystalline volume fraction is easy to be affected by the residual boron in the reactor. The experimental results showed that a 500-nm thick μc-Si:H covering layer or a 30-seconds of hydrogen plasma treatment can effectively reduce the boron contamination at the p/i interface. However, from viewpoint of cost reduction, the hydrogen plasma treatment is desirable for solar cell manufacture because the substrate is not moved during the hydrogen plasma treatment.

Optimization and characterization of biomolecule immobilization on silicon substrates using (3-aminopropyl)triethoxysilane (APTES) and glutaraldehyde linker

NASA Astrophysics Data System (ADS)

Gunda, Naga Siva Kumar; Singh, Minashree; Norman, Lana; Kaur, Kamaljit; Mitra, Sushanta K.

2014-06-01

In the present work, we developed and optimized a technique to produce a thin, stable silane layer on silicon substrate in a controlled environment using (3-aminopropyl)triethoxysilane (APTES). The effect of APTES concentration and silanization time on the formation of silane layer is studied using spectroscopic ellipsometry and Fourier transform infrared spectroscopy (FTIR). Biomolecules of interest are immobilized on optimized silane layer formed silicon substrates using glutaraldehyde linker. Surface analytical techniques such as ellipsometry, FTIR, contact angle measurement system, and atomic force microscopy are employed to characterize the bio-chemically modified silicon surfaces at each step of the biomolecule immobilization process. It is observed that a uniform, homogenous and highly dense layer of biomolecules are immobilized with optimized silane layer on the silicon substrate. The developed immobilization method is successfully implemented on different silicon substrates (flat and pillar). Also, different types of biomolecules such as anti-human IgG (rabbit monoclonal to human IgG), Listeria monocytogenes, myoglobin and dengue capture antibodies were successfully immobilized. Further, standard sandwich immunoassay (antibody-antigen-antibody) is employed on respective capture antibody coated silicon substrates. Fluorescence microscopy is used to detect the respective FITC tagged detection antibodies bound to the surface after immunoassay.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Ceramic with zircon coating

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor)

2003-01-01

An article comprises a silicon-containing substrate and a zircon coating. The article can comprise a silicon carbide/silicon (SiC/Si) substrate, a zircon (ZrSiO.sub.4) intermediate coating and an external environmental/thermal barrier coating.

Superhydrophobic SERS substrates based on silicon hierarchical nanostructures

NASA Astrophysics Data System (ADS)

Chen, Xuexian; Wen, Jinxiu; Zhou, Jianhua; Zheng, Zebo; An, Di; Wang, Hao; Xie, Weiguang; Zhan, Runze; Xu, Ningsheng; Chen, Jun; She, Juncong; Chen, Huanjun; Deng, Shaozhi

2018-02-01

Silicon nanostructures have been cultivated as promising surface enhanced Raman scattering (SERS) substrates in terms of their low-loss optical resonance modes, facile functionalization, and compatibility with today’s state-of-the-art CMOS techniques. However, unlike their plasmonic counterparts, the electromagnetic field enhancements induced by silicon nanostructures are relatively small, which restrict their SERS sensing limit to around 10-7 M. To tackle this problem, we propose here a strategy for improving the SERS performance of silicon nanostructures by constructing silicon hierarchical nanostructures with a superhydrophobic surface. The hierarchical nanostructures are binary structures consisted of silicon nanowires (NWs) grown on micropyramids (MPs). After being modified with perfluorooctyltriethoxysilane (PFOT), the nanostructure surface shows a stable superhydrophobicity with a high contact angle of ˜160°. The substrate can allow for concentrating diluted analyte solutions into a specific area during the evaporation of the liquid droplet, whereby the analytes are aggregated into a small volume and can be easily detected by the silicon nanostructure SERS substrate. The analyte molecules (methylene blue: MB) enriched from an aqueous solution lower than 10-8 M can be readily detected. Such a detection limit is ˜100-fold lower than the conventional SERS substrates made of silicon nanostructures. Additionally, the detection limit can be further improved by functionalizing gold nanoparticles onto silicon hierarchical nanostructures, whereby the superhydrophobic characteristics and plasmonic field enhancements can be combined synergistically to give a detection limit down to ˜10-11 M. A gold nanoparticle-functionalized superhydrophobic substrate was employed to detect the spiked melamine in liquid milk. The results showed that the detection limit can be as low as 10-5 M, highlighting the potential of the proposed superhydrophobic SERS substrate in practical food safety inspection applications.

Wetting, meniscus structure, and capillary interactions of microspheres bound to a cylindrical liquid interface.

PubMed

Kim, Paul Y; Dinsmore, Anthony D; Hoagland, David A; Russell, Thomas P

2018-03-14

Wetting, meniscus structure, and capillary interactions for polystyrene microspheres deposited on constant curvature cylindrical liquid interfaces, constructed from nonvolatile ionic or oligomeric liquids, were studied by optical interferometry and optical microscopy. The liquid interface curvature resulted from the preferential wetting of finite width lines patterned onto planar silicon substrates. Key variables included sphere diameter, nominal (or average) contact angle, and deviatoric interfacial curvature. Menisci adopted the quadrupolar symmetry anticipated by theory, with interfacial deformation closely following predicted dependences on sphere diameter and nominal contact angle. Unexpectedly, the contact angle was not constant locally around the contact line, the nominal contact angle varied among seemingly identical spheres, and the maximum interface deviation did not follow the predicted dependence on deviatoric interfacial curvature. Instead, this deviation was up to an order-of-magnitude larger than predicted. Trajectories of neighboring microspheres visually manifested quadrupole-quadrupole interactions, eventually producing square sphere packings that foreshadow interfacial assembly as a potential route to hierarchical 2D particle structures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Surface phenomenon in Electrochemical Systems

NASA Astrophysics Data System (ADS)

Gupta, Tanya

Interfaces play a critical role in the performance of electrochemical systems. This thesis focusses on interfaces in batteries and covers aspects of interfacial morphologies of metal anodes, including Silicon, Lithium and Zinc. Growth and cycling of electrochemically grown Lithium and Zinc metal structures is investigated. A new morphology of Zinc, called Hyper Dendritic Zinc is introduced. It is cycled against Prussian Blue Analogues and is shown to improve the performance of this couple significantly. Characterization of materials is done using various electron microscopy techniques ranging from Low Energy Electron Microscope (LEEM), to high energy Transmission Electron Microscope (TEM). LEEM is used for capturing subtle surface phenomenon occurring during epitaxial process of electrolyte on anode. The system studied is Silicon (100) during Chemical Vapor Deposition of Ethylene Carbonate. A strain driven relaxation theory is modeled to explain the unusual restructuring of Si substrate. The other extreme, TEM, is often used to study electrochemical processes, without clear understanding of how the high-energy electron beam can influence the sample under investigation. Here, we study the radiolysis in liquid cell TEM and emphasize on the enhancement of radiation dose at interfaces of the liquid due to generation of secondary and backscattered electrons from adjoining materials. It is shown that this effect is localized in a 10 nm region around the interface and can play a dominating role if there is an interface of liquid with heavy metals like Gold and Platinum which are frequently used as electrode materials. This analysis can be used to establish guidelines for experimentalists to follow, for accurate interpretation of their results.

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors

NASA Astrophysics Data System (ADS)

Krishnan, Anand Thiruvengadathan

2000-10-01

The proliferation of devices with built-in displays, such as personal digital assistants and cellular phones has created a demand for rugged light-weight displays. Polymeric substrates could be suited for these applications, and they offer the possibility of flexible displays also. However, driver circuitry needs to be integrated in the display if the cost is to be reduced. Low temperature (<350°C) polycrystalline silicon (poly-Si) thin film transistors, if developed, offer driver circuitry integration during pixel transistor fabrication on top of flexible substrates. This thesis addresses several issues related to the fabrication of thin film transistors at low temperatures on glass substrates. A high-density plasma (electron cyclotron resonance (ECR)) based approach was adopted for deposition of thin films. A process for deposition of n-type doped silicon (n-type doped Si) at T < 350°C and having resistivity <1 ohm/cm has been developed. Intrinsic poly-Si was deposited under different conditions of microwave power, RF bias and deposition times. The properties of n-type doped Si and intrinsic poly-Si were correlated with the structure and the deposition conditions. A novel TFT structure has been proposed and implemented in this work. This top gate TFT structure uses n-type doped Si and utilizes only two masks and one alignment step. There are no critical etch steps and good interface quality could be obtained even without post-processing hydrogenation as the poly-Si surface was not exposed to air before deposition of the gate dielectric. TFTs using this top gate structure were fabricated with no process step exceeding 340°C electrode temperature (surface temperature <300°C). These TFTs show ON/OFF ratios in excess of 105. Their sub-threshold swing is ˜0.5 V/decade and mobility is 1--10 cm2/V-s. Several TFTs were also fabricated using alternative dielectrics such as oxide deposited from tetramethyl silane in an RFPECVD chamber and silicon nitride deposited in the ECR and these TFTs also show reasonable device characteristics. TFTs processed using this high-density plasma based approach show great potential for use in applications such as driver circuitry integration on low temperature substrates.

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

DTIC Science & Technology

2011-11-01

stack between the GaN and Substrate layers. The University of Bristol recently reported that this TBR in commercial devices on Silicon Carbide ( SiC ...Circuit RF Radio Frequency PA Power Amplifier SiC Silicon Carbide FEA Finite Element Analysis heff Effective Heat transfer Coefficient (W/m 2 K...substrate material switched from sapphire to silicon , and by another factor of two from silicon to SiC . TABLE 1: SAMPLE RESULTS FROM DOUGLAS ET AL. FOR

High efficiency, low cost, thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

2001-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, Bhushan L.

1999-01-01

A semiconductor device having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer.

Cryogenic High Pressure Sensor Module

NASA Technical Reports Server (NTRS)

Chapman, John J. (Inventor); Shams, Qamar A. (Inventor); Powers, William T. (Inventor)

1999-01-01

A pressure sensor is provided for cryogenic, high pressure applications. A highly doped silicon piezoresistive pressure sensor is bonded to a silicon substrate in an absolute pressure sensing configuration. The absolute pressure sensor is bonded to an aluminum nitride substrate. Aluminum nitride has appropriate coefficient of thermal expansion for use with highly doped silicon at cryogenic temperatures. A group of sensors, either two sensors on two substrates or four sensors on a single substrate are packaged in a pressure vessel.

Cryogenic, Absolute, High Pressure Sensor

NASA Technical Reports Server (NTRS)

Chapman, John J. (Inventor); Shams. Qamar A. (Inventor); Powers, William T. (Inventor)

2001-01-01

A pressure sensor is provided for cryogenic, high pressure applications. A highly doped silicon piezoresistive pressure sensor is bonded to a silicon substrate in an absolute pressure sensing configuration. The absolute pressure sensor is bonded to an aluminum nitride substrate. Aluminum nitride has appropriate coefficient of thermal expansion for use with highly doped silicon at cryogenic temperatures. A group of sensors, either two sensors on two substrates or four sensors on a single substrate are packaged in a pressure vessel.

Compensated amorphous silicon solar cell

DOEpatents

Devaud, Genevieve

1983-01-01

An amorphous silicon solar cell including an electrically conductive substrate, a layer of glow discharge deposited hydrogenated amorphous silicon over said substrate and having regions of differing conductivity with at least one region of intrinsic hydrogenated amorphous silicon. The layer of hydrogenated amorphous silicon has opposed first and second major surfaces where the first major surface contacts the electrically conductive substrate and an electrode for electrically contacting the second major surface. The intrinsic hydrogenated amorphous silicon region is deposited in a glow discharge with an atmosphere which includes not less than about 0.02 atom percent mono-atomic boron. An improved N.I.P. solar cell is disclosed using a BF.sub.3 doped intrinsic layer.

RF Sputtering for preparing substantially pure amorphous silicon monohydride

DOEpatents

Jeffrey, Frank R.; Shanks, Howard R.

1982-10-12

A process for controlling the dihydride and monohydride bond densities in hydrogenated amorphous silicon produced by reactive rf sputtering of an amorphous silicon target. There is provided a chamber with an amorphous silicon target and a substrate therein with the substrate and the target positioned such that when rf power is applied to the target the substrate is in contact with the sputtering plasma produced thereby. Hydrogen and argon are fed to the chamber and the pressure is reduced in the chamber to a value sufficient to maintain a sputtering plasma therein, and then rf power is applied to the silicon target to provide a power density in the range of from about 7 watts per square inch to about 22 watts per square inch to sputter an amorphous silicon hydride onto the substrate, the dihydride bond density decreasing with an increase in the rf power density. Substantially pure monohydride films may be produced.

Method of forming buried oxide layers in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2000-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

On sub-T(g) dewetting of nanoconfined liquids and autophobic dewetting of crystallites.

PubMed

Souda, Ryutaro

2012-03-28

The glass transition temperature (T(g)) of thin films is reduced by nanoconfinement, but it is also influenced by the free surface and substrate interface. To gain more insights into their contributions, dewetting behaviors of n-pentane, 3-methylpentane, and toluene films are investigated on various substrates as functions of temperature and film thickness. It is found that monolayers of these molecules exhibit sub-T(g) dewetting on a perfluoro-alkyl modified Ni substrate, which is attributable to the evolution of a 2D liquid. The onset temperature of dewetting increases with film thickness because fluidity evolves via cooperative motion of many molecules; sub-T(g) dewetting is observed for films thinner than 5 monolayers. In contrast, monolayers wet substrates of graphite, silicon, and amorphous solid water until crystallization occurs. The crystallites exhibit autophobic dewetting on the substrate covered with a wetting monolayer. The presence of premelting layers is inferred from the fact that n-pentane crystallites disappear on amorphous solid water via intermixing. Thus, the properties of quasiliquid formed on the crystallite surface differ significantly from those of the 2D liquid formed before crystallization.

Automated Array Assembly, Phase 2

NASA Technical Reports Server (NTRS)

Carbajal, B. G.

1979-01-01

The Automated Array Assembly Task, Phase 2 of the Low Cost Silicon Solar Array Project is a process development task. The contract provides for the fabrication of modules from large area tandem junction cells (TJC). During this quarter, effort was focused on the design of a large area, approximately 36 sq cm, TJC and process verification runs. The large area TJC design was optimized for minimum I squared R power losses. In the TJM activity, the cell-module interfaces were defined, module substrates were formed and heat treated and clad metal interconnect strips were fabricated.

Materials Research Society Spring Meeting Symposium KK: Microbial Life on Surfaces: Biofilm-Material Interactions: Life at Interfaces. Held in San Francisco, California on 25-27 April 2011 (Abstracts)

DTIC Science & Technology

2012-05-24

distribution of protein molecules on the cell surface and relative to the substrate on which the bacteria were growing. 9:30AMKKLL3 Effects of the... Temperature and Ionic Strength of Growth Conditions on the Nanoscale Adhesion of L. monocytogenes EGDe to Silicon Nitride. Pinar Gordesli and Nehal Abu...microscopy (AFM) for bacterial cells grown under five different temperatures (10, 20, 30, 37 and 40°C) and five different ionic strengths (0.005

High frequency capacitance-voltage characteristics of thermally grown SiO2 films on beta-SiC

NASA Technical Reports Server (NTRS)

Tang, S. M.; Berry, W. B.; Kwor, R.; Zeller, M. V.; Matus, L. G.

1990-01-01

Silicon dioxide films grown under dry and wet oxidation environment on beta-SiC films have been studied. The beta-SiC films had been heteroepitaxially grown on both on-axis and 2-deg off-axis (001) Si substrates. Capacitance-voltage and conductance-voltage characteristics of metal-oxide-semiconductor structures were measured in a frequency range of 10 kHz to 1 MHz. From these measurements, the interface trap density and the effective fixed oxide charge density were observed to be generally lower for off-axis samples.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Low temperature deposition of polycrystalline silicon thin films on a flexible polymer substrate by hot wire chemical vapor deposition

NASA Astrophysics Data System (ADS)

Lee, Sang-hoon; Jung, Jae-soo; Lee, Sung-soo; Lee, Sung-bo; Hwang, Nong-moon

2016-11-01

For the applications such as flexible displays and solar cells, the direct deposition of crystalline silicon films on a flexible polymer substrate has been a great issue. Here, we investigated the direct deposition of polycrystalline silicon films on a polyimide film at the substrate temperature of 200 °C. The low temperature deposition of crystalline silicon on a flexible substrate has been successfully made based on two ideas. One is that the Si-Cl-H system has a retrograde solubility of silicon in the gas phase near the substrate temperature. The other is the new concept of non-classical crystallization, where films grow by the building block of nanoparticles formed in the gas phase during hot-wire chemical vapor deposition (HWCVD). The total amount of precipitation of silicon nanoparticles decreased with increasing HCl concentration. By adding HCl, the amount and the size of silicon nanoparticles were reduced remarkably, which is related with the low temperature deposition of silicon films of highly crystalline fraction with a very thin amorphous incubation layer. The dark conductivity of the intrinsic film prepared at the flow rate ratio of RHCl=[HCl]/[SiH4]=3.61 was 1.84×10-6 Scm-1 at room temperature. The Hall mobility of the n-type silicon film prepared at RHCl=3.61 was 5.72 cm2 V-1s-1. These electrical properties of silicon films are high enough and could be used in flexible electric devices.

Densification behavior of ceramic and crystallizable glass materials constrained on a rigid substrate

NASA Astrophysics Data System (ADS)

Calata, Jesus N.

2005-11-01

Constrained sintering is an important process for many applications. The sintering process almost always involves some form of constraint, both internal and external, such as rigid particles, reinforcing fibers and substrates to which the porous body adheres. The densification behavior of zinc oxide and cordierite-base crystallizable glass constrained on a rigid substrate was studied to add to the understanding of the behavior of various materials undergoing sintering when subjected to external substrate constraint. Porous ZnO films were isothermally sintered at temperatures between 900°C and 1050°C. The results showed that the densification of films constrained on substrates is severely reduced. This was evident in the sintered microstructures where the particles are joined together by narrower necks forming a more open structure, instead of the equiaxed grains with wide grain boundaries observed in the freestanding films. The calculated activation energies of densification were also different. For the density range of 60 to 64%, the constrained film had an activation energy of 391 +/- 34 kJ/mole compared to 242 +/- 21 kJ/mole for the freestanding film, indicating a change in the densification mechanism. In-plane stresses were observed during the sintering of the constrained films. Yielding of the films, in which the stresses dropped slight or remained unchanged, occurred at relative densities below 60% before the stresses climbed linearly with increasing density followed by a gradual relaxation. A substantial amount of the stresses remained after cooling. Free and constrained films of the cordierite-base crystallizable glass (glass-ceramic) were sintered between 900°C and 1000°C. The substrate constraint did not have a significant effect on the densification rate but the constrained films eventually underwent expansion. Calculations of the densification activation energy showed that, on average, it was close to 1077 kJ/mole, the activation energy of the glass, indicating that the prevailing mechanism was still viscous flow. The films expanded earlier and faster with increasing sintering temperature. The expansion was traced to the formation of pores at the interface with the silicon substrate and to a lesser extent on aluminum nitride. It was significantly reduced when the silicon substrate was pre-oxidized at 900°C, leading to the conclusion that the pore formation at the interface was due to poor wetting, which in turn was caused by the loss of the thin oxide layer through a reaction with the glass.

A polymer-based Fabry-Perot filter integrated with 3-D MEMS structures

NASA Astrophysics Data System (ADS)

Zhang, Ping (Cerina); Le, Kevin; Malalur-Nagaraja-Rao, Smitha; Hsu, Lun-Chen; Chiao, J.-C.

2006-01-01

Polymers have been considered as one of the most versatile materials in making optical devices for communication and sensor applications. They provide good optical transparency to form filters, lenses and many optical components with ease of fabrication. They are scalable and compatible in dimensions with requirements in optics and can be fabricated on inorganic substrates, such as silicon and quartz. Recent polymer synthesis also made great progresses on conductive and nonlinear polymers, opening opportunities for new applications. In this paper, we discussed hybrid-material integration of polymers on silicon-based microelectromechanical system (MEMS) devices. The motivation is to combine the advantages of demonstrated silicon-based MEMS actuators and excellent optical performance of polymers. We demonstrated the idea with a polymer-based out-of-plane Fabry-Perot filter that can be self-assembled by scratch drive actuators. We utilized a fabrication foundry service, MUMPS (Multi-User MEMS Process), to demonstrate the feasibility and flexibility of integration. The polysilicon, used as the structural material for construction of 3-D framework and actuators, has high absorption in the visible and near infrared ranges. Therefore, previous efforts using a polysilicon layer as optical interfaces suffer from high losses. We applied the organic compound materials on the silicon-based framework within the optical signal propagation path to form the optical interfaces. In this paper, we have shown low losses in the optical signal processing and feasibility of building a thin-film Fabry-Perot filter. We discussed the optical filter designs, mechanical design, actuation mechanism, fabrication issues, optical measurements, and results.

Understanding Protein-Interface Interactions of a Fusion Protein at Silicone Oil-Water Interface Probed by Sum Frequency Generation Vibrational Spectroscopy.

PubMed

Li, Yaoxin; Pan, Duohai; Nashine, Vishal; Deshmukh, Smeet; Vig, Balvinder; Chen, Zhan

2018-02-01

Protein adsorbed at the silicone oil-water interface can undergo a conformational change that has the potential to induce protein aggregation on storage. Characterization of the protein structures at interface is therefore critical for understanding the protein-interface interactions. In this article, we have applied sum frequency generation (SFG) spectroscopy for studying the secondary structures of a fusion protein at interface and the surfactant effect on protein adsorption to silicone oil-water interface. SFG and chiral SFG spectra from adsorbed protein in the amide I region were analyzed. The presence of beta-sheet vibrational band at 1635 cm -1 implies the protein secondary structure was likely perturbed when protein adsorbed at silicone oil interface. The time-dependent SFG study showed a significant reduction in the SFG signal of preadsorbed protein when polysorbate 20 was introduced, suggesting surfactant has stronger interaction with the interface leading to desorption of protein from the interface. In the preadsorbed surfactant and a mixture of protein/polysorbate 20, SFG analysis confirmed that surfactant can dramatically prevent the protein adsorption to silicone oil surface. This study has demonstrated the potential of SFG for providing the detailed molecular level understanding of protein conformation at interface and assessing the influence of surfactant on protein adsorption behavior. Copyright © 2018 American Pharmacists Association®. Published by Elsevier Inc. All rights reserved.

Potential energy landscape of an interstitial O2 molecule in a SiO2 film near the SiO2/Si(001) interface

NASA Astrophysics Data System (ADS)

Ohta, Hiromichi; Watanabe, Takanobu; Ohdomari, Iwao

2008-10-01

Potential energy distribution of interstitial O2 molecule in the vicinity of SiO2/Si(001) interface is investigated by means of classical molecular simulation. A 4-nm-thick SiO2 film model is built by oxidizing a Si(001) substrate, and the potential energy of an O2 molecule is calculated at Cartesian grid points with an interval of 0.05 nm in the SiO2 film region. The result shows that the potential energy of the interstitial site gradually rises with approaching the interface. The potential gradient is localized in the region within about 1 nm from the interface, which coincides with the experimental thickness of the interfacial strained layer. The potential energy is increased by about 0.62 eV at the SiO2/Si interface. The result agrees with a recently proposed kinetic model for dry oxidation of silicon [Phys. Rev. Lett. 96, 196102 (2006)], which argues that the oxidation rate is fully limited by the oxidant diffusion.

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

Fabrication and characterization of active nanostructures

NASA Astrophysics Data System (ADS)

Opondo, Noah F.

Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface. A micro-vacuum electron device based on silicon field emitters for cold cathode emission is also presented. The presented work utilizes vertical Si nanowires fabricated by means of self-assembly, standard lithography and etching techniques as field emitters in this dissertation. To obtain a high nanowire density, hence a high current density, a simple and inexpensive Langmuir Blodgett technique to deposit silica nanoparticles as a mask to etch Si is adopted. Fabrication and characterization of a metal-gated microtriode with a high current density and low operating voltage are presented.

Visible-blind ultraviolet photodetectors on porous silicon carbide substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naderi, N.; Hashim, M.R., E-mail: roslan@usm.my

2013-06-01

Highlights: • Highly reliable UV detectors are fabricated on porous silicon carbide substrates. • The optical properties of samples are enhanced by increasing the current density. • The optimized sample exhibits enhanced sensitivity to the incident UV radiation. - Abstract: Highly reliable visible-blind ultraviolet (UV) photodetectors were successfully fabricated on porous silicon carbide (PSC) substrates. High responsivity and high photoconductive gain were observed in a metal–semiconductor–metal ultraviolet photodetector that was fabricated on an optimized PSC substrate. The PSC samples were prepared via the UV-assisted photo-electrochemical etching of an n-type hexagonal silicon carbide (6H-SiC) substrate using different etching current densities. Themore » optical results showed that the current density is an outstanding etching parameter that controls the porosity and uniformity of PSC substrates. A highly porous substrate was synthesized using a suitable etching current density to enhance its light absorption, thereby improving the sensitivity of UV detector with this substrate. The electrical characteristics of fabricated devices on optimized PSC substrates exhibited enhanced sensitivity and responsivity to the incident radiation.« less

Laboratory studies of silicon vapor deposition, phase A. [feasibility of producing thin films for photovoltaic applications

NASA Technical Reports Server (NTRS)

Frost, R. T.; Racette, G. W.; Stockhoff, E. H.

1977-01-01

A system is described capable of carrying out silicon vapor deposition experiments in the low 10 to the minus 10th power torr vacuum range. The system was assembled and tested for use in a program aimed at exploration of vacuum heteroepitaxy of silicon on several substrates of potential interest for photovoltaic applications. An experiment is described in which a silicon layer 2.5 microns thick was deposited on a pyrolytically cleaned tungsten substrate held at a temperature of 400 C. Using a resistance heated silicon source, thicker layers can be deposited in periods of hours by utilizing closer source to substrate distances.

Highly stable, protein resistant thin films on SiC-modified silicon substrates.

PubMed

Qin, Guoting; Zhang, Rui; Makarenko, Boris; Kumar, Amit; Rabalais, Wayne; López Romero, J Manuel; Rico, Rodrigo; Cai, Chengzhi

2010-05-21

Thin films terminated with oligo(ethylene glycol) (OEG) could be photochemically grafted onto ultrathin silicon carbide layers that were generated on silicon substrates via carbonization with acetylene at 820 degrees C. The OEG coating reduced the non-specific adsorption of fibrinogen on the substrates by 99.5% and remained resistant after storage in PBS for 4 weeks at 37 degrees C.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Spalling of a Thin Si Layer by Electrodeposit-Assisted Stripping

NASA Astrophysics Data System (ADS)

Kwon, Youngim; Yang, Changyol; Yoon, Sang-Hwa; Um, Han-Don; Lee, Jung-Ho; Yoo, Bongyoung

2013-11-01

A major goal in solar cell research is to reduce the cost of the final module. Reducing the thickness of the crystalline silicon substrate to several tens of micrometers can reduce material costs. In this work, we describe the electrodeposition of a Ni-P alloy, which induces high stress in the silicon substrate at room temperature. The induced stress enables lift-off of the thin-film silicon substrate. After lift-off of the thin Si film, the mother substrate can be reused, reducing material costs. Moreover, the low-temperature process expected to be improved Si substrate quality.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-07-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Periodic molybdenum disc array for light trapping in amorphous silicon layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Jiwei; Deng, Changkai; Shanghai Advanced Research Institute, Chinese Academy of Sciences, 99 Haike Road, Shanghai, 201210 China

2016-05-15

We demonstrate the light trapping effect in amorphous silicon (a-Si:H) layer by inserting a layer of periodic molybdenum disc array (MDA) between the a-Si:H layer and the quartz substrate, which forms a three-layer structure of Si/MDA/SiO{sub 2}. The MDA layer was fabricated by a new cost-effective method based on nano-imprint technology. Further light absorption enhancement was realized through altering the topography of MDA by annealing it at 700°C. The mechanism of light absorption enhancement in a-Si:H interfaced with MDA was analyzed, and the electric field distribution and light absorption curve of the different layers in the Si/MDA structure under lightmore » illumination of different wavelengths were simulated by employing numerical finite difference time domain (FDTD) solutions.« less

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-03-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Forming high efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2014-09-09

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Forming high-efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2015-07-07

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Synthesis and characterization of silicon nanowire arrays for photovoltaic applications

NASA Astrophysics Data System (ADS)

Eichfeld, Sarah M.

The overall objective of this thesis was the development of processes for the fabrication of radial p-n silicon nanowires (SiNWs) using bottom-up nanowire growth techniques on silicon and glass substrates. Vapor-liquid-solid (VLS) growth was carried out on Si(111) substrates using SiCl4 as the silicon precursor. Growth conditions including temperature, PSiCl4, PH2, and position were investigated to determine the optimum growth conditions for epitaxially oriented silicon nanowire arrays. The experiments revealed that the growth rate of the silicon nanowires exhibits a maximum as a function of PSiCl4 and P H2. Gas phase equilibrium calculations were used in conjunction with a mass transport model to explain the experimental data. The modeling results demonstrate a similar maximum in the mass of solid silicon predicted to form as a function of PSiCl4 and PH2, which results from a change in the gas phase concentration of SiHxCly and SiClx species. This results in a shift in the process from growth to etching with increasing PSiCl4. In general, for the atmospheric pressure conditions employed in this study, growth at higher temperatures >1000°C and higher SiCl4 concentrations gave the best results. The growth of silicon nanowire arrays on anodized alumina (AAO)-coated glass substrates was also investigated. Glass will not hold up to the high temperatures required for Si nanowire growth with SiCl4 so SiH 4 was used as the Si precursor instead. Initial studies were carried out to measure the resistivity of p-type and n-type silicon nanowires grown in freestanding AAO membranes. A series of nanowire samples were grown in which the doping and the nanowire length inside the membrane were varied. Circular metal contacts were deposited on the top surface of the membranes and the resistance of the nanowire arrays was measured. The measured resistance versus nanowire length was plotted and the nanowire resistivity was extracted from the slope. The resistivity of the silicon nanowires grown in the AAO membranes was then compared to the resistivity of silicon nanowires grown on Si and measured using single wire four-point measurements. It was determined that the undoped silicon nanowires grown in AAO have a lower resistivity compared to nanowires grown on Si substrates. This indicates the presence of an unintentional acceptor. The resistivity of the silicon nanowires was found to change as the dopant/SiH4 ratio was varied during growth. The growth and doping conditions developed from this study were then used to fabricate p-type SiNW arrays on the AAO coated glass substrates. The final investigation in this thesis focused on the development of a process for radial coating of an n-type Si layer on the p-type Si nanowires. While prior studies demonstrated the fabrication of polycrystalline n-type Si shell layers on Si nanowires, an epitaxial n-type Si shell layer is ultimately of interest to obtain a high quality p-n interface. Initial n-type Si thin film deposition studies were carried out on sapphire substrates using SiH 4 as the silicon precursor to investigate the effect of growth conditions on thickness uniformity, growth rate and doping level. High growth temperatures (>900°C) are generally desired for achieving epitaxial growth; however, gas phase depletion of the SiH4 source along the length of the reactor resulted in poor thickness uniformity. To improve the uniformity, the substrate was shifted closer to the gas inlet at higher temperatures (950°C) and the total flow of gas through the reactor was increased to 200 sccm. A series of n-type doping experiments were also carried out. Hall measurements indicated n-type behavior and four-point measurements yielded a change in resistivity based on the PH3/SiH4 ratio. Pre-coating sample preparation was determined to be important for achieving a high quality Si shell layer. Since Au can diffuse down the sides of the nanowire during sample cooldown after growth, the Au tips were etched away prior to shell layer deposition. The effect of deposition temperature on the structural properties of the shell layer deposited on the VLS grown SiNWs was investigated. TEM revealed that the n-type Si shells were polycrystalline at low temperatures (650°C) but were single crystal at 950°C. SiNW samples grown on glass were also coated; however, due to the temperature constraints, the maximum temperature used was 650°C and therefore the n-type Si shells were polycrystalline. (Abstract shortened by UMI.)

Synthesis of metal silicide at metal/silicon oxide interface by electronic excitation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, J.-G., E-mail: jglee36@kims.re.kr; Nagase, T.; Yasuda, H.

The synthesis of metal silicide at the metal/silicon oxide interface by electronic excitation was investigated using transmission electron microscopy. A platinum silicide, α-Pt{sub 2}Si, was successfully formed at the platinum/silicon oxide interface under 25–200 keV electron irradiation. This is of interest since any platinum silicide was not formed at the platinum/silicon oxide interface by simple thermal annealing under no-electron-irradiation conditions. From the electron energy dependence of the cross section for the initiation of the silicide formation, it is clarified that the silicide formation under electron irradiation was not due to a knock-on atom-displacement process, but a process induced by electronic excitation.more » It is suggested that a mechanism related to the Knotek and Feibelman mechanism may play an important role in silicide formation within the solid. Similar silicide formation was also observed at the palladium/silicon oxide and nickel/silicon oxide interfaces, indicating a wide generality of the silicide formation by electronic excitation.« less

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

NASA Astrophysics Data System (ADS)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

Interfacial Coupling and Electronic Structure of Two-Dimensional Silicon Grown on the Ag(111) Surface at High Temperature.

PubMed

Feng, Jiagui; Wagner, Sean R; Zhang, Pengpeng

2015-06-18

Freestanding silicene, a monolayer of Si arranged in a honeycomb structure, has been predicted to give rise to massless Dirac fermions, akin to graphene. However, Si structures grown on a supporting substrate can show properties that strongly deviate from the freestanding case. Here, combining scanning tunneling microscopy/spectroscopy and differential conductance mapping, we show that the electrical properties of the (√3 x √3) phase of few-layer Si grown on Ag(111) strongly depend on film thickness, where the electron phase coherence length decreases and the free-electron-like surface state gradually diminishes when approaching the interface. These features are presumably attributable to the inelastic inter-band electron-electron scattering originating from the overlap between the surface state, interface state and the bulk state of the substrate. We further demonstrate that the intrinsic electronic structure of the as grown (√3 x √3) phase is identical to that of the (√3 x √3)R30° reconstructed Ag on Si(111), both of which exhibit the parabolic energy-momentum dispersion relation with comparable electron effective masses. These findings highlight the essential role of interfacial coupling on the properties of two-dimensional Si structures grown on supporting substrates, which should be thoroughly scrutinized in pursuit of silicene.

Nano-SiC region formation in (100) Si-on-insulator substrate: Optimization of hot-C+-ion implantation process to improve photoluminescence intensity

NASA Astrophysics Data System (ADS)

Mizuno, Tomohisa; Omata, Yuhsuke; Kanazawa, Rikito; Iguchi, Yusuke; Nakada, Shinji; Aoki, Takashi; Sasaki, Tomokazu

2018-04-01

We experimentally studied the optimization of the hot-C+-ion implantation process for forming nano-SiC (silicon carbide) regions in a (100) Si-on-insulator substrate at various hot-C+-ion implantation temperatures and C+ ion doses to improve photoluminescence (PL) intensity for future Si-based photonic devices. We successfully optimized the process by hot-C+-ion implantation at a temperature of about 700 °C and a C+ ion dose of approximately 4 × 1016 cm-2 to realize a high intensity of PL emitted from an approximately 1.5-nm-thick C atom segregation layer near the surface-oxide/Si interface. Moreover, atom probe tomography showed that implanted C atoms cluster in the Si layer and near the oxide/Si interface; thus, the C content locally condenses even in the C atom segregation layer, which leads to SiC formation. Corrector-spherical aberration transmission electron microscopy also showed that both 4H-SiC and 3C-SiC nanoareas near both the surface-oxide/Si and buried-oxide/Si interfaces partially grow into the oxide layer, and the observed PL photons are mainly emitted from the surface SiC nano areas.

Silicon spikes and impurity accumulation at interrupted growth interfaces during molecular-beam epitaxy

DOE Office of Scientific and Technical Information (OSTI.GOV)

SpringThorpe, A.J.; Moore, W.T.; Majeed, A.

1993-07-01

Recent proposals by Wood and Wilson, to explain the formation of impurity spikes at substrate/epitaxial layer interfaces in GaAs prepared by molecular-beam epitaxy (MBE), have been experimentally investigated. Their suggestion that the spikes form due to suboxide transport via reactions that involve the As{sub 2}O{sub 3} released from the substrate during oxide desorption and hot Knudsen cells, is not supported by the experimental data. The same authors have also speculated that there may be significant flux leakage from nominally closed cells. For this to occur, reflection and scattering of flux by inadequately cooled cryoshroud baffle surfaces are necessary. Secondary ionmore » mass spectrometry analyses of interfaces, at which the growth of GaAs and AlAs was interrupted for times up to 30 min, confirm that this takes place. However, flux leakage is only found to be significant for the high vapor pressure group III elements. For these elements, incorporation levels in the range 0.02%-0.1% are found under normal deposition conditions. These results suggest that careful attention should be given to increasing the internal MBE system baffling in order to eliminate cross contamination problems. 14 refs., 2 figs., 1 tab.« less

Ultrasmooth Patterned Metals for Plasmonics and Metamaterials

NASA Astrophysics Data System (ADS)

Nagpal, Prashant; Lindquist, Nathan C.; Oh, Sang-Hyun; Norris, David J.

2009-07-01

Surface plasmons are electromagnetic waves that can exist at metal interfaces because of coupling between light and free electrons. Restricted to travel along the interface, these waves can be channeled, concentrated, or otherwise manipulated by surface patterning. However, because surface roughness and other inhomogeneities have so far limited surface-plasmon propagation in real plasmonic devices, simple high-throughput methods are needed to fabricate high-quality patterned metals. We combined template stripping with precisely patterned silicon substrates to obtain ultrasmooth pure metal films with grooves, bumps, pyramids, ridges, and holes. Measured surface-plasmon-propagation lengths on the resulting surfaces approach theoretical values for perfectly flat films. With the use of our method, we demonstrated structures that exhibit Raman scattering enhancements above 107 for sensing applications and multilayer films for optical metamaterials.

Adhesion of single- and multi-walled carbon nanotubes to silicon substrate: atomistic simulations and continuum analysis

NASA Astrophysics Data System (ADS)

Yuan, Xuebo; Wang, Youshan

2017-10-01

The radial deformation of carbon nanotubes (CNTs) adhering to a substrate may prominently affect their mechanical and physical properties. In this study, both classical atomistic simulations and continuum analysis are carried out, to investigate the lateral adhesion of single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) to a silicon substrate. A linear elastic model for analyzing the adhesion of 2D shells to a rigid semi-infinite substrate is constructed in the framework of continuum mechanics. Good agreement is achieved between the cross-section profiles of adhesive CNTs obtained by the continuum model and by the atomistic simulation approach. It is found that the adhesion of a CNT to the silicon substrate is significantly influenced by its initial diameter and the number of walls. CNTs with radius larger than a certain critical radius are deformed radially on the silicon substrate with flat contact regions. With increasing number of walls, the extent of radial deformation of a MWCNT on the substrate decreases dramatically, and the flat contact area reduces—and eventually vanishes—due to increasing equivalent bending stiffness. It is analytically predicted that large-diameter MWCNTs with a large number of walls are likely to ‘stand’ on the silicon substrate. The present work can be useful for understanding the radial deformation of CNTs adhering to a solid planar substrate.

Fabrication of polycrystalline solar cells on low-cost substrates

NASA Technical Reports Server (NTRS)

Chu, T. L. (Inventor)

1976-01-01

A new method of producing p-n junction semiconductors for solar cells was described; the principal objective of this investigation is to reduce production costs significantly by depositing polycrystalline silicon on a relatively cheap substrate such as metallurgical-grade silicon, graphite, or steel. The silicon layer contains appropriate dopants, and the substrates are coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures of these compounds.

Thin SiGe virtual substrates for Ge heterostructures integration on silicon

NASA Astrophysics Data System (ADS)

Cecchi, S.; Gatti, E.; Chrastina, D.; Frigerio, J.; Müller Gubler, E.; Paul, D. J.; Guzzi, M.; Isella, G.

2014-03-01

The possibility to reduce the thickness of the SiGe virtual substrate, required for the integration of Ge heterostructures on Si, without heavily affecting the crystal quality is becoming fundamental in several applications. In this work, we present 1 μm thick Si1-xGex buffers (with x > 0.7) having different designs which could be suitable for applications requiring a thin virtual substrate. The rationale is to reduce the lattice mismatch at the interface with the Si substrate by introducing composition steps and/or partial grading. The relatively low growth temperature (475 °C) makes this approach appealing for complementary metal-oxide-semiconductor integration. For all the investigated designs, a reduction of the threading dislocation density compared to constant composition Si1-xGex layers was observed. The best buffer in terms of defects reduction was used as a virtual substrate for the deposition of a Ge/SiGe multiple quantum well structure. Room temperature optical absorption and photoluminescence analysis performed on nominally identical quantum wells grown on both a thick graded virtual substrate and the selected thin buffer demonstrates a comparable optical quality, confirming the effectiveness of the proposed approach.

Porous Silicon Covered with Silver Nanoparticles as Surface-Enhanced Raman Scattering (SERS) Substrate for Ultra-Low Concentration Detection.

PubMed

Kosović, Marin; Balarin, Maja; Ivanda, Mile; Đerek, Vedran; Marciuš, Marijan; Ristić, Mira; Gamulin, Ozren

2015-12-01

Microporous and macro-mesoporous silicon templates for surface-enhanced Raman scattering (SERS) substrates were produced by anodization of low doped p-type silicon wafers. By immersion plating in AgNO3, the templates were covered with silver metallic film consisting of different silver nanostructures. Scanning electron microscopy (SEM) micrographs of these SERS substrates showed diverse morphology with significant difference in an average size and size distribution of silver nanoparticles. Ultraviolet-visible-near-infrared (UV-Vis-NIR) reflection spectroscopy showed plasmonic absorption at 398 and 469 nm, which is in accordance with the SEM findings. The activity of the SERS substrates was tested using rhodamine 6G (R6G) dye molecules and 514.5 nm laser excitation. Contrary to the microporous silicon template, the SERS substrate prepared from macro-mesoporous silicon template showed significantly broader size distribution of irregular silver nanoparticles as well as localized surface plasmon resonance closer to excitation laser wavelength. Such silver morphology has high SERS sensitivity that enables ultralow concentration detection of R6G dye molecules up to 10(-15) M. To our knowledge, this is the lowest concentration detected of R6G dye molecules on porous silicon-based SERS substrates, which might even indicate possible single molecule detection.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

2002-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Increased voltage photovoltaic cell

NASA Technical Reports Server (NTRS)

Ross, B.; Bickler, D. B.; Gallagher, B. D. (Inventor)

1985-01-01

A photovoltaic cell, such as a solar cell, is provided which has a higher output voltage than prior cells. The improved cell includes a substrate of doped silicon, a first layer of silicon disposed on the substrate and having opposite doping, and a second layer of silicon carbide disposed on the first layer. The silicon carbide preferably has the same type of doping as the first layer.

Molybdenum enhanced low-temperature deposition of crystalline silicon nitride

DOEpatents

Lowden, Richard A.

1994-01-01

A process for chemical vapor deposition of crystalline silicon nitride which comprises the steps of: introducing a mixture of a silicon source, a molybdenum source, a nitrogen source, and a hydrogen source into a vessel containing a suitable substrate; and thermally decomposing the mixture to deposit onto the substrate a coating comprising crystalline silicon nitride containing a dispersion of molybdenum silicide.

Growth behavior and properties of atomic layer deposited tin oxide on silicon from novel tin(II)acetylacetonate precursor and ozone

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kannan Selvaraj, Sathees; Feinerman, Alan; Takoudis, Christos G., E-mail: takoudis@uic.edu

In this work, a novel liquid tin(II) precursor, tin(II)acetylacetonate [Sn(acac){sub 2}], was used to deposit tin oxide films on Si(100) substrate, using a custom-built hot wall atomic layer deposition (ALD) reactor. Three different oxidizers, water, oxygen, and ozone, were tried. Resulting growth rates were studied as a function of precursor dosage, oxidizer dosage, reactor temperature, and number of ALD cycles. The film growth rate was found to be 0.1 ± 0.01 nm/cycle within the wide ALD temperature window of 175–300 °C using ozone; no film growth was observed with water or oxygen. Characterization methods were used to study the composition, interface quality, crystallinity, microstructure,more » refractive index, surface morphology, and resistivity of the resulting films. X-ray photoelectron spectra showed the formation of a clean SnO{sub x}–Si interface. The resistivity of the SnO{sub x} films was calculated to be 0.3 Ω cm. Results of this work demonstrate the possibility of introducing Sn(acac){sub 2} as tin precursor to deposit conducting ALD SnO{sub x} thin films on a silicon surface, with clean interface and no formation of undesired SiO{sub 2} or other interfacial reaction products, for transparent conducting oxide applications.« less

Electro-induced protein deposition on low-fouling surfaces

NASA Astrophysics Data System (ADS)

Cole, M. A.; Voelcker, N. H.; Thissen, H.

2007-12-01

Control over protein adsorption is a key issue for numerous biomedical applications ranging from diagnostic microarrays to tissue-engineered medical devices. Here, we describe a method for creating surfaces that prevent non-specific protein adsorption, which upon application of an external trigger can be transformed into surfaces showing high protein adsorption on demand. Silicon wafers were used as substrate materials upon which thin functional coatings were constructed by the deposition of an allylamine plasma polymer followed by high-density grafting of poly(ethylene oxide) aldehyde, resulting in a low-fouling surface. When the underlying highly doped silicon substrate was used as an electrode, the resulting electrostatic attraction between the electrode and charged proteins in solution induced protein deposition at the low-fouling interface. X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM) were used to characterize the surface modifications. Controlled protein adsorption experiments were carried out using horseradish peroxidase. The amount of protein deposited at the surface was then investigated by means of a colorimetric assay. It is expected that the concept described here will find use in a variety of biotechnological and biomedical applications, particularly in the area of biochips.

Strong room temperature electroluminescence from lateral p-SiGe/i-Ge/n-SiGe heterojunction diodes on silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Lin, Guangyang; Yi, Xiaohui; Li, Cheng; Chen, Ningli; Zhang, Lu; Chen, Songyan; Huang, Wei; Wang, Jianyuan; Xiong, Xihuan; Sun, Jiaming

2016-10-01

A lateral p-Si0.05Ge0.95/i-Ge/n-Si0.05Ge0.95 heterojunction light emitting diode on a silicon-on-insulator (SOI) substrate was proposed, which is profitable to achieve higher luminous extraction compared to vertical junctions. Due to the high carrier injection ratio of heterostructures and optical reflection at the SiO2/Si interface of the SOI, strong room temperature electroluminescence (EL) at around 1600 nm from the direct bandgap of i-Ge with 0.30% tensile strain was observed. The EL peak intensity of the lateral heterojunction is enhanced by ˜4 folds with a larger peak energy than that of the vertical Ge p-i-n homojunction, suggesting that the light emitting efficiency of the lateral heterojunction is effectively improved. The EL peak intensity of the lateral heterojunction, which increases quadratically with injection current density, becomes stronger for diodes with a wider i-Ge region. The CMOS compatible fabrication process of the lateral heterojunctions paves the way for the integration of the light source with the Ge metal-oxide-semiconductor field-effect-transistor.

Toward Intelligent Synthetic Neural Circuits: Directing and Accelerating Neuron Cell Growth by Self-Rolled-Up Silicon Nitride Microtube Array

PubMed Central

2015-01-01

In neural interface platforms, cultures are often carried out on a flat, open, rigid, and opaque substrate, posing challenges to reflecting the native microenvironment of the brain and precise engagement with neurons. Here we present a neuron cell culturing platform that consists of arrays of ordered microtubes (2.7–4.4 μm in diameter), formed by strain-induced self-rolled-up nanomembrane (s-RUM) technology using ultrathin (<40 nm) silicon nitride (SiNx) film on transparent substrates. These microtubes demonstrated robust physical confinement and unprecedented guidance effect toward outgrowth of primary cortical neurons, with a coaxially confined configuration resembling that of myelin sheaths. The dynamic neural growth inside the microtube, evaluated with continuous live-cell imaging, showed a marked increase (20×) of the growth rate inside the microtube compared to regions outside the microtubes. We attribute the dramatic accelerating effect and precise guiding of the microtube array to three-dimensional (3D) adhesion and electrostatic interaction with the SiNx microtubes, respectively. This work has clear implications toward building intelligent synthetic neural circuits by arranging the size, site, and patterns of the microtube array, for potential treatment of neurological disorders. PMID:25329686

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

Dislocation-free strained silicon-on-silicon by in-place bonding

NASA Astrophysics Data System (ADS)

Cohen, G. M.; Mooney, P. M.; Paruchuri, V. K.; Hovel, H. J.

2005-06-01

In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as "bonded in-place". We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained.

Method of deposition of silicon carbide layers on substrates

DOEpatents

Angelini, P.; DeVore, C.E.; Lackey, W.J.; Blanco, R.E.; Stinton, D.P.

1982-03-19

A method for direct chemical vapor deposition of silicon carbide to substrates, especially nuclear waste particles, is provided by the thermal decomposition of methylsilane at 800 to 1050/sup 0/C when the substrates have been confined within a suitable coating environment.

Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias

NASA Astrophysics Data System (ADS)

Araga, Yuuki; Kikuchi, Katsuya; Aoyagi, Masahiro

2018-04-01

Substrate noise from a single through-silicon via (TSV) and the noise attenuation by a substrate tap and a guard ring are clarified. A CMOS test vehicle is designed, and 6-µm-diameter TSVs are manufactured on a 20-µm-thick silicon substrate by the via-last method. An on-chip waveform-capturing circuitry is embedded in the test vehicle to capture transient waveforms of substrate noise. The embedded waveform-capturing circuitry demonstrates small and local noise propagation. Experimental results show increased substrate noise level induced by TSVs and the effectiveness of the substrate tap and guard ring for mitigating the crosstalk among TSVs. An analytical model to explain substrate noise propagation is developed to validate experimental results. Results obtained using the substrate model with a multilayer mesh shows good consistency with experimental results, indicating that the model can be used for examination of noise suppression methods.

Atomic Structure of Interface States in Silicon Heterojunction Solar Cells

NASA Astrophysics Data System (ADS)

George, B. M.; Behrends, J.; Schnegg, A.; Schulze, T. F.; Fehr, M.; Korte, L.; Rech, B.; Lips, K.; Rohrmüller, M.; Rauls, E.; Schmidt, W. G.; Gerstmann, U.

2013-03-01

Combining orientation dependent electrically detected magnetic resonance and g tensor calculations based on density functional theory we assign microscopic structures to paramagnetic states involved in spin-dependent recombination at the interface of hydrogenated amorphous silicon crystalline silicon (a-Si:H/c-Si) heterojunction solar cells. We find that (i) the interface exhibits microscopic roughness, (ii) the electronic structure of the interface defects is mainly determined by c-Si, (iii) we identify the microscopic origin of the conduction band tail state in the a-Si:H layer, and (iv) present a detailed recombination mechanism.

Optical gradients in a-Si:H thin films detected using real-time spectroscopic ellipsometry with virtual interface analysis

NASA Astrophysics Data System (ADS)

Junda, Maxwell M.; Karki Gautam, Laxmi; Collins, Robert W.; Podraza, Nikolas J.

2018-04-01

Virtual interface analysis (VIA) is applied to real time spectroscopic ellipsometry measurements taken during the growth of hydrogenated amorphous silicon (a-Si:H) thin films using various hydrogen dilutions of precursor gases and on different substrates during plasma enhanced chemical vapor deposition. A procedure is developed for optimizing VIA model configurations by adjusting sampling depth into the film and the analyzed spectral range such that model fits with the lowest possible error function are achieved. The optimal VIA configurations are found to be different depending on hydrogen dilution, substrate composition, and instantaneous film thickness. A depth profile in the optical properties of the films is then extracted that results from a variation in an optical absorption broadening parameter in a parametric a-Si:H model as a function of film thickness during deposition. Previously identified relationships are used linking this broadening parameter to the overall shape of the optical properties. This parameter is observed to converge after about 2000-3000 Å of accumulated thickness in all layers, implying that similar order in the a-Si:H network can be reached after sufficient thicknesses. In the early stages of growth, however, significant variations in broadening resulting from substrate- and processing-induced order are detected and tracked as a function of bulk layer thickness yielding an optical property depth profile in the final film. The best results are achieved with the simplest film-on-substrate structures while limitations are identified in cases where films have been deposited on more complex substrate structures.

Melting in Superheated Silicon Films Under Pulsed-Laser Irradiation

NASA Astrophysics Data System (ADS)

Wang, Jin Jimmy

This thesis examines melting in superheated silicon films in contact with SiO2 under pulsed laser irradiation. An excimer-laser pulse was employed to induce heating of the film by irradiating the film through the transparent fused-quartz substrate such that most of the beam energy was deposited near the bottom Si-SiO2 interface. Melting dynamics were probed via in situ transient reflectance measurements. The temperature profile was estimated computationally by incorporating temperature- and phase-dependent physical parameters and the time-dependent intensity profile of the incident excimer-laser beam obtained from the experiments. The results indicate that a significant degree of superheating occurred in the subsurface region of the film. Surface-initiated melting was observed in spite of the internal heating scheme, which resulted in the film being substantially hotter at and near the bottom Si-SiO2 interface. By considering that the surface melts at the equilibrium melting point, the solid-phase-only heat-flow analysis estimates that the bottom Si-SiO2 interface can be superheated by at least 220 K during excimer-laser irradiation. It was found that at higher laser fluences (i.e., at higher temperatures), melting can be triggered internally. At heating rates of 1010 K/s, melting was observed to initiate at or near the (100)-oriented Si-SiO2 interface at temperatures estimated to be over 300 K above the equilibrium melting point. Based on theoretical considerations, it was deduced that melting in the superheated solid initiated via a nucleation and growth process. Nucleation rates were estimated from the experimental data using Johnson-Mehl-Avrami-Kolmogorov (JMAK) analysis. Interpretation of the results using classical nucleation theory suggests that nucleation of the liquid phase occurred via the heterogeneous mechanism along the Si-SiO2 interface.

Molybdenum enhanced low-temperature deposition of crystalline silicon nitride

DOEpatents

Lowden, R.A.

1994-04-05

A process for chemical vapor deposition of crystalline silicon nitride is described which comprises the steps of: introducing a mixture of a silicon source, a molybdenum source, a nitrogen source, and a hydrogen source into a vessel containing a suitable substrate; and thermally decomposing the mixture to deposit onto the substrate a coating comprising crystalline silicon nitride containing a dispersion of molybdenum silicide. 5 figures.

Electron Beam "Writes" Silicon On Sapphire

NASA Technical Reports Server (NTRS)

Heinemann, Klaus

1988-01-01

Method of growing silicon on sapphire substrate uses beam of electrons to aid growth of semiconductor material. Silicon forms as epitaxial film in precisely localized areas in micron-wide lines. Promising fabrication method for fast, densely-packed integrated circuits. Silicon deposited preferentially in contaminated substrate zones and in clean zone irradiated by electron beam. Electron beam, like surface contamination, appears to stimulate decomposition of silane atmosphere.

Distributed Capacitive Sensor for Sample Mass Measurement

NASA Technical Reports Server (NTRS)

Toda, Risaku; McKinney, Colin; Jackson, Shannon P.; Mojarradi, Mohammad; Manohara, Harish; Trebi-Ollennu, Ashitey

2011-01-01

Previous robotic sample return missions lacked in situ sample verification/ quantity measurement instruments. Therefore, the outcome of the mission remained unclear until spacecraft return. In situ sample verification systems such as this Distributed Capacitive (DisC) sensor would enable an unmanned spacecraft system to re-attempt the sample acquisition procedures until the capture of desired sample quantity is positively confirmed, thereby maximizing the prospect for scientific reward. The DisC device contains a 10-cm-diameter pressure-sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in close proximity to an opposing rigid substrate with a narrow gap. The deformation of the membrane makes the gap narrower, resulting in increased capacitance between the two parallel plates (elastic membrane and rigid substrate). C-V conversion circuits on a nearby PCB (printed circuit board) provide capacitance readout via LVDS (low-voltage differential signaling) interface. The capacitance method was chosen over other potential approaches such as the piezoelectric method because of its inherent temperature stability advantage. A reference capacitor and temperature sensor are embedded in the system to compensate for temperature effects. The pressure-sensitive membranes are aluminum 6061, stainless steel (SUS) 403, and metal-coated polyimide plates. The thicknesses of these membranes range from 250 to 500 m. The rigid substrate is made with a 1- to 2-mm-thick wafer of one of the following materials depending on the application requirements glass, silicon, polyimide, PCB substrate. The glass substrate is fabricated by a microelectromechanical systems (MEMS) fabrication approach. Several concentric electrode patterns are printed on the substrate. The initial gap between the two plates, 100 m, is defined by a silicon spacer ring that is anodically bonded to the glass substrate. The fabricated proof-of-concept devices have successfully demonstrated tens to hundreds of picofarads of capacitance change when a simulated sample (100 g to 500 g) is placed on the membrane.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Purified silicon production system

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2004-03-30

Method and apparatus for producing purified bulk silicon from highly impure metallurgical-grade silicon source material at atmospheric pressure. Method involves: (1) initially reacting iodine and metallurgical-grade silicon to create silicon tetraiodide and impurity iodide byproducts in a cold-wall reactor chamber; (2) isolating silicon tetraiodide from the impurity iodide byproducts and purifying it by distillation in a distillation chamber; and (3) transferring the purified silicon tetraiodide back to the cold-wall reactor chamber, reacting it with additional iodine and metallurgical-grade silicon to produce silicon diiodide and depositing the silicon diiodide onto a substrate within the cold-wall reactor chamber. The two chambers are at atmospheric pressure and the system is open to allow the introduction of additional source material and to remove and replace finished substrates.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Harrison, W. B.; Wolner, H. A.; Hendrickson, G.; Nelson, L. D.

1976-01-01

To date, an experimental dip-coating facility was constructed. Using this facility, relatively thin (1 mm) mullite and alumina substrates were successfully dip-coated with 2.5 - 3.0 ohm-cm, p-type silicon with areas of approximately 20 sq cm. The thickness and grain size of these coatings are influenced by the temperature of the melt and the rate at which the substrate is pulled from the melt. One mullite substrate had dendrite-like crystallites of the order of 1 mm wide and 1 to 2 cm long. Their axes were aligned along the direction of pulling. A large variety of substrate materials were purchased or developed enabling the program to commence a substrate definition evaluation. Due to the insulating nature of the substrate, the bottom layer of the p-n junction may have to be made via the top surface. The feasibility of accomplishing this was demonstrated using single crystal wafers.

Interfacial phonon scattering and transmission loss in > 1 µm thick silicon-on-insulator thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Puqing; Lindsay, Lucas R.; Huang, Xi

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. Here, to better understand the interfacial scattering of phonons and to test the validity of Ziman'smore » theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1–10 μm and a temperature range of 100–300 K. The Si/SiO 2 interface roughness was determined to be 0.11±0.04nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. Finally, we derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.« less

Interfacial phonon scattering and transmission loss in > 1 µm thick silicon-on-insulator thin films

DOE PAGES

Jiang, Puqing; Lindsay, Lucas R.; Huang, Xi; ...

2018-05-17

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. Here, to better understand the interfacial scattering of phonons and to test the validity of Ziman'smore » theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1–10 μm and a temperature range of 100–300 K. The Si/SiO 2 interface roughness was determined to be 0.11±0.04nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. Finally, we derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.« less

Silicon carbide thyristor

NASA Technical Reports Server (NTRS)

Edmond, John A. (Inventor); Palmour, John W. (Inventor)

1996-01-01

The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.

Bidisperse silica nanoparticles close-packed monolayer on silicon substrate by three step spin method

NASA Astrophysics Data System (ADS)

Khanna, Sakshum; Marathey, Priyanka; Utsav, Chaliawala, Harsh; Mukhopadhyay, Indrajit

2018-05-01

We present the studies on the structural properties of monolayer Bidisperse silica (SiO2) nanoparticles (BDS) on Silicon (Si-100) substrate using spin coating technique. The Bidisperse silica nanoparticle was synthesised by the modified sol-gel process. Nanoparticles on the substrate are generally assembled in non-close/close-packed monolayer (CPM) form. The CPM form is obtained by depositing the colloidal suspension onto the silicon substrate using complex techniques. Here we report an effective method for forming a monolayer of bidisperse silica nanoparticle by three step spin coating technique. The samples were prepared by mixing the monodisperse solutions of different particles size 40 and 100 nm diameters. The bidisperse silica nanoparticles were self-assembled on the silicon substrate forming a close-packed monolayer film. The scanning electron microscope images of bidisperse films provided in-depth film structure of the film. The maximum surface coverage obtained was around 70-80%.

High efficiency low cost thin film silicon solar cell design and method for making

DOEpatents

Sopori, B.L.

1999-04-27

A semiconductor device is described having a substrate, a conductive intermediate layer deposited onto said substrate, wherein the intermediate layer serves as a back electrode, an optical reflector, and an interface for impurity gettering, and a semiconductor layer deposited onto said intermediate layer, wherein the semiconductor layer has a grain size at least as large as the layer thickness, and preferably about ten times the layer thickness. The device is formed by depositing a metal layer on a substrate, depositing a semiconductive material on the metal-coated substrate to produce a composite structure, and then optically processing the composite structure by illuminating it with infrared electromagnetic radiation according to a unique time-energy profile that first produces pits in the backside surface of the semiconductor material, then produces a thin, highly reflective, low resistivity alloy layer over the entire area of the interface between the semiconductor material and the metal layer, and finally produces a grain-enhanced semiconductor layer. The time-energy profile includes increasing the energy to a first energy level to initiate pit formation and create the desired pit size and density, then ramping up to a second energy level in which the entire device is heated to produce an interfacial melt, and finally reducing the energy to a third energy level and holding for a period of time to allow enhancement in the grain size of the semiconductor layer. 9 figs.

Fabrication of novel plasmonics-active substrates

NASA Astrophysics Data System (ADS)

Dhawan, Anuj; Gerhold, Michael; Du, Yan; Misra, Veena; Vo-Dinh, Tuan

2009-02-01

This paper describes methodologies for fabricating of highly efficient plasmonics-active SERS substrates - having metallic nanowire structures with pointed geometries and sub-5 nm gap between the metallic nanowires enabling concentration of high EM fields in these regions - on a wafer-scale by a reproducible process that is compatible with large-scale development of these substrates. Excitation of surface plasmons in these nanowire structures leads to substantial enhancement in the Raman scattering signal obtained from molecules lying in the vicinity of the nanostructure surface. The methodologies employed included metallic coating of silicon nanowires fabricated by employing deep UV lithography as well as controlled growth of silicon germanium on silicon nanostructures to form diamond-shaped nanowire structures followed by metallic coating. These SERS substrates were employed for detecting chemical and biological molecules of interest. In order to characterize the SERS substrates developed in this work, we obtained SERS signals from molecules such as p-mercaptobenzoic acid (pMBA) and cresyl fast violet (CFV) attached to or adsorbed on the metal-coated SERS substrates. It was observed that both gold-coated triangular shaped nanowire substrates as well as gold-coated diamond shaped nanowire substrates provided very high SERS signals for the nanowires having sub-15 nm gaps and that the SERS signal depends on the closest spacing between the metal-coated silicon and silicon germanium nanowires. SERS substrates developed by the different processes were also employed for detection of biological molecules such as DPA (Dipicolinic Acid), an excellent marker for spores of bacteria such as Anthrax.

Crystalline silicon growth in nickel/a-silicon bilayer

NASA Astrophysics Data System (ADS)

Mohiddon, Md Ahamad; Naidu, K. Lakshun; Dalba, G.; Rocca, F.; Krishna, M. Ghanashyam

2013-02-01

The effect of substrate temperature on amorphous Silicon crystallization, mediated by metal impurity is reported. Bilayers of Ni(200nm)/Si(400nm) are deposited on fused silica substrate by electron beam evaporator at 200 and 500 °C. Raman mapping shows that, 2 to 5 micron size crystalline silicon clusters are distributed over the entire surface of the sample. X-ray diffraction and X-ray absorption spectroscopy studies demonstrate silicon crystallizes over the metal silicide seeds and grow with the annealing temperature.

Solar cell with silicon oxynitride dielectric layer

DOEpatents

Shepherd, Michael; Smith, David D

2015-04-28

Solar cells with silicon oxynitride dielectric layers and methods of forming silicon oxynitride dielectric layers for solar cell fabrication are described. For example, an emitter region of a solar cell includes a portion of a substrate having a back surface opposite a light receiving surface. A silicon oxynitride (SiO.sub.xN.sub.y, 0

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

DOEpatents

Feng, Tom; Ghosh, Amal K.

1980-01-01

Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300.degree. C. to about 400.degree. C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250.degree. C. Preferably the insulating layer is naturally grown silicon oxide layer.

Direct Growth of Graphene on Silicon by Metal-Free Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Tai, Lixuan; Zhu, Daming; Liu, Xing; Yang, Tieying; Wang, Lei; Wang, Rui; Jiang, Sheng; Chen, Zhenhua; Xu, Zhongmin; Li, Xiaolong

2018-06-01

The metal-free synthesis of graphene on single-crystal silicon substrates, the most common commercial semiconductor, is of paramount significance for many technological applications. In this work, we report the growth of graphene directly on an upside-down placed, single-crystal silicon substrate using metal-free, ambient-pressure chemical vapor deposition. By controlling the growth temperature, in-plane propagation, edge-propagation, and core-propagation, the process of graphene growth on silicon can be identified. This process produces atomically flat monolayer or bilayer graphene domains, concave bilayer graphene domains, and bulging few-layer graphene domains. This work would be a significant step toward the synthesis of large-area and layer-controlled, high-quality graphene on single-crystal silicon substrates. [Figure not available: see fulltext.

Methods of repairing a substrate

NASA Technical Reports Server (NTRS)

Riedell, James A. (Inventor); Easler, Timothy E. (Inventor)

2011-01-01

A precursor of a ceramic adhesive suitable for use in a vacuum, thermal, and microgravity environment. The precursor of the ceramic adhesive includes a silicon-based, preceramic polymer and at least one ceramic powder selected from the group consisting of aluminum oxide, aluminum nitride, boron carbide, boron oxide, boron nitride, hafnium boride, hafnium carbide, hafnium oxide, lithium aluminate, molybdenum silicide, niobium carbide, niobium nitride, silicon boride, silicon carbide, silicon oxide, silicon nitride, tin oxide, tantalum boride, tantalum carbide, tantalum oxide, tantalum nitride, titanium boride, titanium carbide, titanium oxide, titanium nitride, yttrium oxide, zirconium boride, zirconium carbide, zirconium oxide, and zirconium silicate. Methods of forming the ceramic adhesive and of repairing a substrate in a vacuum and microgravity environment are also disclosed, as is a substrate repaired with the ceramic adhesive.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

1997-01-01

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

A proposal for digital electro-optic switches with free-carrier dispersion effect and Goos-Hanchen shift in silicon-on-insulator waveguide corner mirror

NASA Astrophysics Data System (ADS)

Sun, DeGui

2013-09-01

In a silicon-on-insulator (SOI) waveguide corner mirror (WCM) structure, with the quantum process of a frustrated total internal reflection (FTIR) phenomenon and the time delay principle in the two-dimensional potential barrier tunneling process of a mass of particles, we derive an accurate physical model for the Goos-Hanchen (GH) shift of optical guided-mode in the FTIR process, and in principle match the GH shift jumping states with the independent guided-modes. Then, we propose and demonstrate a new regime of 1 × N digital optical switches with a matching state between the free-carrier dispersion (FCD) based refractive index modulation (RIM) of silicon to create a GH shift jumping function of a photonic signal at the reflecting interface and the independent guided-modes in the FTIR process, where a MOS-capacitor type electro-optic modulation regime is proposed and discussed to realize an effective FCD-based RIM. At the critical matching state, i.e., the incident of an optical beam is at the vicinity of Brewster angle in the WCM, a mini-change of refractive index of waveguide material can cause a great jump of GH shift along the FTIR reflecting interface, and further a 1 × N digital optical switching process could be realized. For a 350-500 nm single-mode rib waveguide made on the 220 nm CMOS-compatible SOI substrate and with the FCD effect based RIM of silicon crystal, a concentration variation of 1018-1019 cm-3 has caused a 0.5-2.5 μm GH shift of reflected beam, which is at 2-5 times of a mode-size and hence radically convinces an optical switching function with a 1 × 3-1 × 10 scale.

Study of silicon crystal surface formation based on molecular dynamics simulation results

NASA Astrophysics Data System (ADS)

Barinovs, G.; Sabanskis, A.; Muiznieks, A.

2014-04-01

The equilibrium shape of <110>-oriented single crystal silicon nanowire, 8 nm in cross-section, was found from molecular dynamics simulations using LAMMPS molecular dynamics package. The calculated shape agrees well to the shape predicted from experimental observations of nanocavities in silicon crystals. By parametrization of the shape and scaling to a known value of {111} surface energy, Wulff form for solid-vapor interface was obtained. The Wulff form for solid-liquid interface was constructed using the same model of the shape as for the solid-vapor interface. The parameters describing solid-liquid interface shape were found using values of surface energies in low-index directions known from published molecular dynamics simulations. Using an experimental value of the liquid-vapor interface energy for silicon and graphical solution of Herring's equation, we constructed angular diagram showing relative equilibrium orientation of solid-liquid, liquid-vapor and solid-vapor interfaces at the triple phase line. The diagram gives quantitative predictions about growth angles for different growth directions and formation of facets on the solid-liquid and solid-vapor interfaces. The diagram can be used to describe growth ridges appearing on the crystal surface grown from a melt. Qualitative comparison to the ridges of a Float zone silicon crystal cone is given.

Method of producing novel silicon carbide articles. [Patent application

DOEpatents

Milewski, J.V.

1982-06-18

A method of producing articles comprising reaction-bonded silicon carbide (SiC) and graphite (and/or carbon) is given. The process converts the graphite (and/or carbon) in situ to SiC, thus providing the capability of economically obtaining articles made up wholly or partially of SiC having any size and shape in which graphite (and/or carbon) can be found or made. When the produced articles are made of an inner graphite (and/or carbon) substrate to which SiC is reaction bonded, these articles distinguish SiC-coated graphite articles found in the prior art by the feature of a strong bond having a gradual (as opposed to a sharply defined) interface which extends over a distance of mils. A method for forming SiC whisker-reinforced ceramic matrices is also given. The whisker-reinforced articles comprise SiC whiskers which substantially retain their structural integrity.

Method of producing silicon carbide articles

DOEpatents

Milewski, John V.

1985-01-01

A method of producing articles comprising reaction-bonded silicon carbide (SiC) and graphite (and/or carbon) is given. The process converts the graphite (and/or carbon) in situ to SiC, thus providing the capability of economically obtaining articles made up wholly or partially of SiC having any size and shape in which graphite (and/or carbon) can be found or made. When the produced articles are made of an inner graphite (and/or carbon) substrate to which SiC is reaction bonded, these articles distinguish SiC-coated graphite articles found in the prior art by the feature of a strong bond having a gradual (as opposed to a sharply defined) interface which extends over a distance of mils. A method for forming SiC whisker-reinforced ceramic matrices is also given. The whisker-reinforced articles comprise SiC whiskers which substantially retain their structural integrity.

Three-dimensional conformal graphene microstructure for flexible and highly sensitive electronic skin

NASA Astrophysics Data System (ADS)

Yang, Jun; Ran, Qincui; Wei, Dapeng; Sun, Tai; Yu, Leyong; Song, Xuefen; Pu, Lichun; Shi, Haofei; Du, Chunlei

2017-03-01

We demonstrate a highly stretchable electronic skin (E-skin) based on the facile combination of microstructured graphene nanowalls (GNWs) and a polydimethylsiloxane (PDMS) substrate. The microstructure of the GNWs was endowed by conformally growing them on the unpolished silicon wafer without the aid of nanofabrication technology. Then a stamping transfer method was used to replicate the micropattern of the unpolished silicon wafer. Due to the large contact interface between the 3D graphene network and the PDMS, this type of E-skin worked under a stretching ratio of nearly 100%, and showed excellent mechanical strength and high sensitivity, with a change in relative resistance of up to 6500% and a gauge factor of 65.9 at 99.64% strain. Furthermore, the E-skin exhibited an obvious highly sensitive response to joint movement, eye movement and sound vibration, demonstrating broad potential applications in healthcare, body monitoring and wearable devices.

Fabrication of near-field optical apertures in aluminium by a highly selective corrosion process in the evanescent field.

PubMed

Haefliger, D; Stemmer, A

2003-03-01

A simple, one-step process to fabricate high-quality apertures for scanning near-field optical microscope probes based on aluminium-coated silicon nitride cantilevers is presented. A thin evanescent optical field at a glass-water interface was used to heat the aluminium at the tip apex due to light absorption. The heat induced a breakdown of the passivating oxide layer and local corrosion of the metal, which selectively exposed the front-most part of the probe tip from the aluminium. Apertures with a protruding silicon nitride tip up to 72 nm in height were fabricated. The height of the protrusion was controlled by the extent of the evanescent field, whereas the diameter depended on the geometry of the probe substrate. The corrosion process proved to be self-terminating, yielding highly reproducible tip heights. Near-field optical resolution in a transmission mode of 85 nm was demonstrated.

Optical properties of p–i–n structures based on amorphous hydrogenated silicon with silicon nanocrystals formed via nanosecond laser annealing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krivyakin, G. K.; Volodin, V. A., E-mail: volodin@isp.nsc.ru; Kochubei, S. A.

Silicon nanocrystals are formed in the i layers of p–i–n structures based on a-Si:H using pulsed laser annealing. An excimer XeCl laser with a wavelength of 308 nm and a pulse duration of 15 ns is used. The laser fluence is varied from 100 (below the melting threshold) to 250 mJ/cm{sup 2} (above the threshold). The nanocrystal sizes are estimated by analyzing Raman spectra using the phonon confinement model. The average is from 2.5 to 3.5 nm, depending on the laser-annealing parameters. Current–voltage measurements show that the fabricated p–i–n structures possess diode characteristics. An electroluminescence signal in the infrared (IR)more » range is detected for the p–i–n structures with Si nanocrystals; the peak position (0.9–1 eV) varies with the laser-annealing parameters. Radiative transitions are presumably related to the nanocrystal–amorphous-matrix interface states. The proposed approach can be used to produce light-emitting diodes on non-refractory substrates.« less

Fully Tunable Silicon Nanowire Arrays Fabricated by Soft Nanoparticle Templating.

PubMed

Rey, By Marcel; Elnathan, Roey; Ditcovski, Ran; Geisel, Karen; Zanini, Michele; Fernandez-Rodriguez, Miguel-Angel; Naik, Vikrant V; Frutiger, Andreas; Richtering, Walter; Ellenbogen, Tal; Voelcker, Nicolas H; Isa, Lucio

2016-01-13

We demonstrate a fabrication breakthrough to produce large-area arrays of vertically aligned silicon nanowires (VA-SiNWs) with full tunability of the geometry of the single nanowires and of the whole array, paving the way toward advanced programmable designs of nanowire platforms. At the core of our fabrication route, termed "Soft Nanoparticle Templating", is the conversion of gradually compressed self-assembled monolayers of soft nanoparticles (microgels) at a water-oil interface into customized lithographical masks to create VA-SiNW arrays by means of metal-assisted chemical etching (MACE). This combination of bottom-up and top-down techniques affords excellent control of nanowire etching site locations, enabling independent control of nanowire spacing, diameter and height in a single fabrication route. We demonstrate the fabrication of centimeter-scale two-dimensional gradient photonic crystals exhibiting continuously varying structural colors across the entire visible spectrum on a single silicon substrate, and the formation of tunable optical cavities supported by the VA-SiNWs, as unambiguously demonstrated through numerical simulations. Finally, Soft Nanoparticle Templating is combined with optical lithography to create hierarchical and programmable VA-SiNW patterns.

Method of deposition of silicon carbide layers on substrates and product

DOEpatents

Angelini, Peter; DeVore, Charles E.; Lackey, Walter J.; Blanco, Raymond E.; Stinton, David P.

1984-01-01

A method for direct chemical vapor deposition of silicon carbide to substrates, especially nuclear waste particles, is provided by the thermal decomposition of methylsilane at about 800.degree. C. to 1050.degree. C. when the substrates have been confined within a suitable coating environment.

Chronic recording of regenerating VIIIth nerve axons with a sieve electrode

NASA Technical Reports Server (NTRS)

Mensinger, A. F.; Anderson, D. J.; Buchko, C. J.; Johnson, M. A.; Martin, D. C.; Tresco, P. A.; Silver, R. B.; Highstein, S. M.

2000-01-01

A micromachined silicon substrate sieve electrode was implanted within transected toadfish (Opsanus tau) otolith nerves. High fidelity, single unit neural activity was recorded from seven alert and unrestrained fish 30 to 60 days after implantation. Fibrous coatings of genetically engineered bioactive protein polymers and nerve guide tubes increased the number of axons regenerating through the electrode pores when compared with controls. Sieve electrodes have potential as permanent interfaces to the nervous system and to bridge missing connections between severed or damaged nerves and muscles. Recorded impulses might also be amplified and used to control prosthetic devices.

Hollow tin/chromium whiskers

NASA Astrophysics Data System (ADS)

Cheng, Jing; Vianco, Paul T.; Li, James C. M.

2010-05-01

Tin whiskers have been an engineering challenge for over five decades. The mechanism has not been agreed upon thus far. This experiment aimed to identify a mechanism by applying compressive stresses to a tin film evaporated on silicon substrate with an adhesion layer of chromium in between. A phenomenon was observed in which hollow whiskers grew inside depleted areas. Using focused ion beam, the hollow whiskers were found to contain both tin and chromium. At the bottom of the depleted areas, thin tin/tin oxide film remained over the chromium layer. It indicates that tin transport occurred along the interface between tin and chromium layers.

Interface Engineering to Create a Strong Spin Filter Contact to Silicon

NASA Astrophysics Data System (ADS)

Caspers, C.; Gloskovskii, A.; Gorgoi, M.; Besson, C.; Luysberg, M.; Rushchanskii, K. Z.; Ležaić, M.; Fadley, C. S.; Drube, W.; Müller, M.

2016-03-01

Integrating epitaxial and ferromagnetic Europium Oxide (EuO) directly on silicon is a perfect route to enrich silicon nanotechnology with spin filter functionality. To date, the inherent chemical reactivity between EuO and Si has prevented a heteroepitaxial integration without significant contaminations of the interface with Eu silicides and Si oxides. We present a solution to this long-standing problem by applying two complementary passivation techniques for the reactive EuO/Si interface: (i) an in situ hydrogen-Si (001) passivation and (ii) the application of oxygen-protective Eu monolayers-without using any additional buffer layers. By careful chemical depth profiling of the oxide-semiconductor interface via hard x-ray photoemission spectroscopy, we show how to systematically minimize both Eu silicide and Si oxide formation to the sub-monolayer regime-and how to ultimately interface-engineer chemically clean, heteroepitaxial and ferromagnetic EuO/Si (001) in order to create a strong spin filter contact to silicon.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, Stephen M.; Tao, Hongyi; Todd-Copley, Judith A.

1991-01-01

A process for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, S.M.; Tao, H.; Todd-Copley, J.A.

1991-06-11

A process is disclosed for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength. 1 figure.

Improved toughness of silicon carbide

NASA Technical Reports Server (NTRS)

Palm, J. A.

1976-01-01

Impact energy absorbing layers (EALs) comprised of partially densified silicon carbide were formed in situ on fully sinterable silicon carbide substrates. After final sintering, duplex silicon carbide structures resulted which were comprised of a fully sintered, high density silicon carbide substrate or core, overlayed with an EAL of partially sintered silicon carbide integrally bonded to its core member. Thermal cycling tests proved such structures to be moderately resistant to oxidation and highly resistant to thermal shock stresses. The strength of the developed structures in some cases exceeded but essentially it remained the same as the fully sintered silicon carbide without the EAL. Ballistic impact tests indicated that substantial improvements in the toughness of sintered silicon carbide were achieved by the use of the partially densified silicon carbide EALs.

Microfluid oscillator based on thermocapillarity

NASA Astrophysics Data System (ADS)

Huang, Teng-chao; Shen, Yi-bing; Liu, Xu; Bai, Jian; Hou, Xiyun; Ye, Hui; Lou, Di

2004-12-01

A novel micro fluid oscillator with a boron diffused resistor is proposed in this paper. The actuation principle is based on the combination of Marangoni effect. The contemporary microfabrication technique enables us to fabricate microheater tiny enough to control temperature so quickly and precisely in micro length scale. The devices exhibiting the Marangoni effect in square channels were designed and fabricated from one silicon substrate and two quartz substrates. And the three substrates were aligned, bonded and packaged for testing. In this actuator there is a pair of micro-heaters to produce a thermal gradient along the slit. The driving wattage is about 0.1W and the resistors can make a temperature difference about 100 degrees during 0.1s with a pulsewidth of 20us for 0.1A current pulses. Then the movement is driven towards the lower temperature direction by the interfacial tension of the air-liquid interface. This micro fluid actuator can play important role in many liquid micro-systems such as in micromotor and micro valve.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Zook, J. D.; Harrison, W. B.; Scott, M. W.; Hendrickson, G.; Wolner, H. A.; Nelson, L. D.; Schuller, T. L.; Peterson, A. A.

1976-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon by dip-coating one surface of carbonized ceramic substrates with a thin layer of large grain polycrystalline silicon was investigated. The dip-coating methods studied were directed toward a minimum cost process with the ultimate objective of producing solar cells with a conversion efficiency of 10% or greater. The technique shows excellent promise for low cost, labor-saving, scale-up potentialities and would provide an end product of sheet silicon with a rigid and strong supportive backing. An experimental dip-coating facility was designed and constructed, several substrates were successfully dip-coated with areas as large as 25 sq cm and thicknesses of 12 micron to 250 micron. There appears to be no serious limitation on the area of a substrate that could be coated. Of the various substrate materials dip-coated, mullite appears to best satisfy the requirement of the program. An inexpensive process was developed for producing mullite in the desired geometry.

Interaction of a single acetophenone molecule with group III-IV elements mediated by Si(001)

NASA Astrophysics Data System (ADS)

Racis, A.; Jurczyszyn, L.; Radny, M. W.

2018-03-01

A theoretical study of an influence of the acetophenone molecule adsorbed on the Si(001) on the local chemical reactivity of silicon surface is presented. The obtained results indicate that the interaction of the molecule with silicon substrate breaks the intra-dimer π bonds in four surface silicon dimers interacting directly with adsorbed molecule. This leads to the formation of two pairs of unpaired dangling bonds at two opposite sides of the molecule. It is demonstrated that these dangling bonds increase considerably the local chemical reactivity of the silicon substrate in the vicinity of the adsorbed molecule. Consequently, it is shown that such molecule bonded with Si(001) can stabilize the position of In and Pb adatoms diffusing on silicon substrate at two sides and initiate the one-dimensional aggregation of the metallic adatoms on the Si(001) substrate anchored at both sides of the adsorbed molecule. This type of aggregation leads to the growth of chain-like atomic structures in opposite directions, pinned to adsorbed molecule and oriented perpendicular to the rows of surface silicon dimers.

Low-Power RIE of SiO2 in CHF3 To Obtain Steep Sidewalls

NASA Technical Reports Server (NTRS)

Turner, Tasha; Wu, Chi

2003-01-01

A reactive-ion etching (RIE) process has been developed to enable the formation of holes with steep sidewalls in a layer of silicon dioxide that covers a silicon substrate. The holes in question are through the thickness of the SiO2 and are used to define silicon substrate areas to be etched or to be built upon through epitaxial deposition of silicon. The sidewalls of these holes are required to be vertical in order to ensure that the sidewalls of the holes to be etched in the substrate or the sidewalls of the epitaxial deposits, respectively, also turn out to be vertical.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

High-voltage SPM oxidation of ZrN: materials for multiscale applications

NASA Astrophysics Data System (ADS)

Farkas, N.; Comer, J. R.; Zhang, G.; Evans, E. A.; Ramsier, R. D.; Dagata, J. A.

2005-02-01

Scanning probe microscope (SPM) oxidation was used to form zirconium oxide features on 200 nm thick ZrN films. The features exhibit rapid yet controlled growth kinetics, even in contact mode with 70 V dc applied between the probe tip and substrate. The features grown for times longer than 10 s are higher than 200 nm, and reach more than 1000 nm in height after 300 s. Long-time oxidation experiments and selective etching of the oxides and nitrides lead us to propose that as the oxidation reaches the silicon substrate, delamination occurs with the simultaneous formation of a thin layer of new material at the ZrN/Si interface. High-voltage oxide growth on ZrN is fast and sustainable, and the robust oxide features are promising candidates for multiscale (nanometre-to-micrometre) applications.

Purification and deposition of silicon by an iodide disproportionation reaction

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2002-01-01

Method and apparatus for producing purified bulk silicon from highly impure metallurgical-grade silicon source material at atmospheric pressure. Method involves: (1) initially reacting iodine and metallurgical-grade silicon to create silicon tetraiodide and impurity iodide byproducts in a cold-wall reactor chamber; (2) isolating silicon tetraiodide from the impurity iodide byproducts and purifying it by distillation in a distillation chamber; and (3) transferring the purified silicon tetraiodide back to the cold-wall reactor chamber, reacting it with additional iodine and metallurgical-grade silicon to produce silicon diiodide and depositing the silicon diiodide onto a substrate within the cold-wall reactor chamber. The two chambers are at atmospheric pressure and the system is open to allow the introduction of additional source material and to remove and replace finished substrates.

Composition Comprising Silicon Carbide

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2012-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Method and apparatus for forming conformal SiN.sub.x films

DOEpatents

Wang, Qi

2007-11-27

A silicon nitride film formation method includes: Heating a substrate to be subjected to film formation to a substrate temperature; heating a wire to a wire temperature; supplying silane, ammonia, and hydrogen gases to the heating member; and forming a silicon nitride film on the substrate.

Structural and interfacial defects in c-axis oriented LiNbO3 thin films grown by pulsed laser deposition on Si using Al : ZnO conducting layer

NASA Astrophysics Data System (ADS)

Shandilya, Swati; Tomar, Monika; Sreenivas, K.; Gupta, Vinay

2009-05-01

Highly c-axis oriented LiNbO3 films are deposited using pulsed laser deposition on a silicon substrate using a transparent conducting Al doped ZnO layer. X-ray diffraction and Raman spectroscopic analysis show the fabrication of single phase and oriented LiNbO3 films under the optimized deposition condition. An extra peak at 905 cm-1 was observed in the Raman spectra of LiNbO3 film deposited at higher substrate temperature and higher oxygen pressure, and attributed to the presence of niobium antisite defects in the lattice. Dielectric constant and ac conductivity of oriented LiNbO3 films deposited under the static and rotating substrate modes have been studied. Films deposited under the rotating substrate mode exhibit dielectric properties close to the LiNbO3 single crystal. The cause of deviation in the dielectric properties of the film deposited under the static substrate mode, in comparison with the bulk, are discussed in the light of the possible formation of an interdiffusion layer at the interface of the LiNbO3 film and the Al : ZnO layer.

Inter-diffusion of copper and hafnium as studied by x-ray photoelectron spectroscopy

NASA Astrophysics Data System (ADS)

Pearson, Justin; Chourasia, A. R.

The Cu/Hf interface has been characterized by x-ray photoelectron spectroscopy. Thin films (thicknesses ranging from 100 nm to 150 nm) of hafnium were deposited on a silicon substrate. About 80 nm of copper was then deposited on such samples. The e-beam method was used for the deposition. The samples were annealed for 30 min at temperatures of 100, 200, 300, 400, and 500°C. The inter-diffusion of copper and hafnium was investigated by sequential sputter depth profiling and x-ray photoelectron spectroscopy. The interdiffusion in each case was analyzed by the Matano-Boltzmann's procedure using the Fick's second law. The interdiffusion coefficients and the width of the interface as determined from the data have been correlated with the annealing temperature. Supported by Organized Research, TAMU-Commerce.

Improved Work Function of Poly(3,4-ethylenedioxythiophene): Poly(styrenesulfonic acid) and its Effect on Hybrid Silicon/Organic Heterojunction Solar Cells.

PubMed

Shen, Xiaojuan; Chen, Ling; Pan, Jianmei; Hu, Yue; Li, Songjun; Zhao, Jie

2016-12-01

Hybrid silicon/organic solar cells have been recently extensively investigated due to their simple structure and low-cost fabrication process. However, the efficiency of the solar cells is greatly limited by the barrier height as well as the carrier recombination at the silicon/organic interface. In this work, hydrochloroplatinic acid (H 2 PtCl 6 ) is employed into the poly(3,4-ethlenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) solution, and the work function (WF) of the PEDOT:PSS layer has been successfully improved. Based on the Pt-modified PEDOT:PSS layer, the efficiency of the silicon/PEDOT:PSS cell can be increased to 11.46%, corresponding to ~20% enhancement to the one without platinum (Pt) modification. Theoretical and experimental results show that, when increasing the WF of the PEDO:PSS layer, the barrier height between the silicon/PEDOT:PSS interface can be effectively enhanced. Meanwhile, the carrier recombination at the interface is significantly reduced. These results can contribute to better understanding of the interfacial mechanism of silicon/PEDOT:PSS interface, and further improving the device performance of silicon/organic solar cells.

Improved Work Function of Poly(3,4-ethylenedioxythiophene): Poly(styrenesulfonic acid) and its Effect on Hybrid Silicon/Organic Heterojunction Solar Cells

NASA Astrophysics Data System (ADS)

Shen, Xiaojuan; Chen, Ling; Pan, Jianmei; Hu, Yue; Li, Songjun; Zhao, Jie

2016-11-01

Hybrid silicon/organic solar cells have been recently extensively investigated due to their simple structure and low-cost fabrication process. However, the efficiency of the solar cells is greatly limited by the barrier height as well as the carrier recombination at the silicon/organic interface. In this work, hydrochloroplatinic acid (H2PtCl6) is employed into the poly(3,4-ethlenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) solution, and the work function (WF) of the PEDOT:PSS layer has been successfully improved. Based on the Pt-modified PEDOT:PSS layer, the efficiency of the silicon/PEDOT:PSS cell can be increased to 11.46%, corresponding to 20% enhancement to the one without platinum (Pt) modification. Theoretical and experimental results show that, when increasing the WF of the PEDO:PSS layer, the barrier height between the silicon/PEDOT:PSS interface can be effectively enhanced. Meanwhile, the carrier recombination at the interface is significantly reduced. These results can contribute to better understanding of the interfacial mechanism of silicon/PEDOT:PSS interface, and further improving the device performance of silicon/organic solar cells.

Ultra-thin silicon oxide layers on crystalline silicon wafers: Comparison of advanced oxidation techniques with respect to chemically abrupt SiO2/Si interfaces with low defect densities

NASA Astrophysics Data System (ADS)

Stegemann, Bert; Gad, Karim M.; Balamou, Patrice; Sixtensson, Daniel; Vössing, Daniel; Kasemann, Martin; Angermann, Heike

2017-02-01

Six advanced oxidation techniques were analyzed, evaluated and compared with respect to the preparation of high-quality ultra-thin oxide layers on crystalline silicon. The resulting electronic and chemical SiO2/Si interface properties were determined by a combined x-ray photoemission (XPS) and surface photovoltage (SPV) investigation. Depending on the oxidation technique, chemically abrupt SiO2/Si interfaces with low densities of interface states were fabricated on c-Si either at low temperatures, at short times, or in wet-chemical environment, resulting in each case in excellent interface passivation. Moreover, the beneficial effect of a subsequent forming gas annealing (FGA) step for the passivation of the SiO2/Si interface of ultra-thin oxide layers has been proven. Chemically abrupt SiO2/Si interfaces have been shown to generate less interface defect states.

Silicon on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Pickering, C.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon was investigated. It was hoped this could be done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Work was directed towards the solution of unique cell processing/design problems encountered with the silicon-ceramic (SOC) material due to its intimate contact with the ceramic substrate. Significant progress was demonstrated in the following areas; (1) the continuous coater succeeded in producing small-area coatings exhibiting unidirectional solidification and substatial grain size; (2) dip coater succeeded in producing thick (more than 500 micron) dendritic layers at coating speeds of 0.2-0.3 cm/sec; and (3) a standard for producing total area SOC solar cells using slotted ceramic substrates was developed.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, A.M.

1995-03-07

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics. 15 figs.

Separation and Detection of Toxic Gases with a Silicon Micromachined Gas Chromatography System

NASA Technical Reports Server (NTRS)

Kolesar, Edward S.; Reston, Rocky R.

1995-01-01

A miniature gas chromatography (GC) system was designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 microliter sample loop; a 0.9 meter long, rectangular shaped (300 micrometer width and 10 micrometer height) capillary column coated with a 0.2 micrometer thick copper phthalocyanine (CuPc) stationary phase; and a dual detector scheme based upon a CuPc-coated chemiresistor and a commercially available 125 micrometer diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex (r) cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH3) and nitrogen dioxide (NO2) when isothermally operated (55-80 degrees C). With a helium carrier gas and nitrogen diluent, a 10 microliter sample volume containing ammonia and nitrogen dioxide injected at 40 psi ((2.8 x 10(exp 5)Pa)) can be separated in less than 30 minutes.

Conformable large-area position-sensitive photodetectors based on luminescence-collecting silicone waveguides

NASA Astrophysics Data System (ADS)

Bartu, Petr; Koeppe, Robert; Arnold, Nikita; Neulinger, Anton; Fallon, Lisa; Bauer, Siegfried

2010-06-01

Position sensitive detection schemes based on the lateral photoeffect rely on inorganic semiconductors. Such position sensitive devices (PSDs) are reliable and robust, but preparation with large active areas is expensive and use on curved substrates is impossible. Here we present a novel route for the fabrication of conformable PSDs which allows easy preparation on large areas, and use on curved surfaces. Our device is based on stretchable silicone waveguides with embedded fluorescent dyes, used in conjunction with small silicon photodiodes. Impinging laser light (e.g., from a laser pointer) is absorbed by the dye in the PSD and re-emitted as fluorescence light at a larger wavelength. Due to the isotropic emission from the fluorescent dye molecules, most of the re-emitted light is coupled into the planar silicone waveguide and directed to the edges of the device. Here the light signals are detected via embedded small silicon photodiodes arranged in a regular pattern. Using a mathematical algorithm derived by extensive using of models from global positioning system (GPS) systems and human activity monitoring, the position of light spots is easily calculated. Additionally, the device shows high durability against mechanical stress, when clamped in an uniaxial stretcher and mechanically loaded up to 15% strain. The ease of fabrication, conformability, and durability of the device suggests its use as interface devices and as sensor skin for future robots.

Surface Attachment of Gold Nanoparticles Guided by Block Copolymer Micellar Films and Its Application in Silicon Etching

PubMed Central

Wei, Mingjie; Wang, Yong

2015-01-01

Patterning metallic nanoparticles on substrate surfaces is important in a number of applications. However, it remains challenging to fabricate such patterned nanoparticles with easily controlled structural parameters, including particle sizes and densities, from simple methods. We report on a new route to directly pattern pre-formed gold nanoparticles with different diameters on block copolymer micellar monolayers coated on silicon substrates. Due to the synergetic effect of complexation and electrostatic interactions between the micellar cores and the gold particles, incubating the copolymer-coated silicon in a gold nanoparticles suspension leads to a monolayer of gold particles attached on the coated silicon. The intermediate micellar film was then removed using oxygen plasma treatment, allowing the direct contact of the gold particles with the Si substrate. We further demonstrate that the gold nanoparticles can serve as catalysts for the localized etching of the silicon substrate, resulting in nanoporous Si with a top layer of straight pores. PMID:28793407

RF sputtering for controlling dihydride and monohydride bond densities in amorphous silicon hydride

DOEpatents

Jeffery, F.R.; Shanks, H.R.

1980-08-26

A process is described for controlling the dihydride and monohydride bond densities in hydrogenated amorphous silicone produced by reactive rf sputtering of an amorphous silicon target. There is provided a chamber with an amorphous silicon target and a substrate therein with the substrate and the target positioned such that when rf power is applied to the target the substrate is in contact with the sputtering plasma produced thereby. Hydrogen and argon are fed to the chamber and the pressure is reduced in the chamber to a value sufficient to maintain a sputtering plasma therein, and then rf power is applied to the silicon target to provide a power density in the range of from about 7 watts per square inch to about 22 watts per square inch to sputter an amorphous solicone hydride onto the substrate, the dihydride bond density decreasing with an increase in the rf power density. Substantially pure monohydride films may be produced.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

Method of forming contacts for a back-contact solar cell

DOEpatents

Manning, Jane

2015-10-20

Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.

Method of forming contacts for a back-contact solar cell

DOEpatents

Manning, Jane

2014-07-15

Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

III-V compound semiconductor growth on silicon via germanium buffer and surface passivation for CMOS technology

NASA Astrophysics Data System (ADS)

Choi, Donghun

Integration of III-V compound semiconductors on silicon substrates has recently received much attention for the development of optoelectronic and high speed electronic devices. However, it is well known that there are some key challenges for the realization of III-V device fabrication on Si substrates: (i) the large lattice mismatch (in case of GaAs: 4.1%), and (ii) the formation of antiphase domain (APD) due to the polar compound semiconductor growth on non-polar elemental structure. Besides these growth issues, the lack of a useful surface passivation technology for compound semiconductors has precluded development of metal-oxide-semiconductor (MOS) devices and causes high surface recombination parasitics in scaled devices. This work demonstrates the growth of high quality III-V materials on Si via an intermediate Ge buffer layer and some surface passivation methods to reduce interface defect density for the fabrication of MOS devices. The initial goal was to achieve both low threading dislocation density (TDD) and low surface roughness on Ge-on-Si heterostructure growth. This was achieved by repeating a deposition-annealing cycle consisting of low temperature deposition + high temperature-high rate deposition + high temperature hydrogen annealing, using reduced-pressure chemical-vapor deposition (CVD). We then grew III-V materials on the Ge/Si virtual substrates using molecular-beam epitaxy (MBE). The relationship between initial Ge surface configuration and antiphase boundary formation was investigated using surface reflection high-energy electron diffraction (RHEED) patterns and atomic force microscopy (AFM) image analysis. In addition, some MBE growth techniques, such as migration enhanced epitaxy (MEE) and low temperature GaAs growth, were adopted to improve surface roughness and solve the Ge self-doping problem. Finally, an Al2O3 gate oxide layer was deposited using atomic-layer-deposition (ALD) system after HCl native oxide etching and ALD in-situ pre-annealing at 400 °C. A 100 nm thick aluminum layer was deposited to form the gate contact for a MOS device fabrication. C-V measurement results show very small frequency dispersion and 200-300 mV hysteresis, comparable to our best results for InGaAs/GaAs MOS structures on GaAs substrate. Most notably, the quasi-static C-V curve demonstrates clear inversion layer formation. I-V curves show a reasonable leakage current level. The inferred midgap interface state density, Dit, of 2.4 x 1012 eV-1cm-2 was calculated by combined high-low frequency capacitance method. In addition, we investigated the interface properties of amorphous LaAlO 3/GaAs MOS capacitors fabricated on GaAs substrate. The surface was protected during sample transfer between III-V and oxide molecular beam deposition (MBD) chambers by a thick arsenic-capping layer. An annealing method, a low temperature-short time RTA followed by a high temperature RTA, was developed, yielding extremely small hysteresis (˜ 30 mV), frequency dispersion (˜ 60 mV), and interface trap density (mid 1010 eV-1cm -2). We used capacitance-voltage (C-V) and current-voltage (I-V) measurements for electrical characterization of MOS devices, tapping-mode AFM for surface morphology analysis, X-ray photoelectron spectroscopy (XPS) for chemical elements analysis of interface, cross section transmission-electron microscopy (TEM), X-ray diffraction (XRD), secondary ion mass spectrometry (SIMS), and photoluminescence (PL) measurement for film quality characterization. This successful growth and appropriate surface treatments of III-V materials provides a first step for the fabrication of III-V optical and electrical devices on the same Si-based electronic circuits.

Circularly polarized Raman study on diamond structure crystals

NASA Astrophysics Data System (ADS)

Lee, Je-Ho; Kim, Sera; Seong, Maeng-Je

2018-01-01

Circularly polarized Raman and/or photoluminescence (PL) analyses have recently been very important in studying physical properties of many layered materials that were either mechanically exfoliated or grown by chemical-vapor-deposition (CVD) on silicon substrates. Since silicon Raman signal is always accompanied by the circularly polarized Raman and/or PL signal from the layered materials, observation of proper circularly polarized Raman selection rules on silicon substrates would be extremely good indicator that the circularly polarized Raman and/or PL measurements on the layered materials were done properly. We have performed circularly polarized Raman measurements on silicon substrates and compared the results with the Raman intensities calculated by using Raman tensors of the diamond crystal structure. Our experimental results were in excellent agreement with the calculation. Similar circularly polarized Raman analysis done on germanium substrate also showed good agreement.

Nitrogen doped silicon-carbon multilayer protective coatings on carbon obtained by TVA method

NASA Astrophysics Data System (ADS)

Ciupina, Victor; Vasile, Eugeniu; Porosnicu, Corneliu; Lungu, Cristian P.; Vladoiu, Rodica; Jepu, Ionut; Mandes, Aurelia; Dinca, Virginia; Caraiane, Aureliana; Nicolescu, Virginia; Cupsa, Ovidiu; Dinca, Paul; Zaharia, Agripina

2017-08-01

Protective nitrogen doped Si-C multilayer coatings on carbon, used to improve the oxidation resistance of carbon, were obtained by Thermionic Vacuum Arc (TVA) method. The initial carbon layer having a thickness of 100nm has been deposed on a silicon substrate in the absence of nitrogen, and then a 3nm Si thin film to cover carbon layer was deposed. Further, seven Si and C layers were alternatively deposed in the presence of nitrogen ions, each having a thickness of 40nm. In order to form silicon carbide at the interface between silicon and carbon layers, all carbon, silicon and nitrogen ions energy has increased up to 150eV . The characterization of microstructure and electrical properties of as-prepared N-Si-C multilayer structures were done using Transmission Electron Microscopy (TEM, STEM) techniques, Thermal Desorption Spectroscopy (TDS) and electrical measurements. Oxidation protection of carbon is based on the reaction between oxygen and silicon carbide, resulting in SiO2, SiO and CO2, and also by reaction involving N, O and Si, resulting in silicon oxynitride (SiNxOy) with a continuously variable composition, and on the other hand, since nitrogen acts as a trapping barrier for oxygen. To perform electrical measurements, 80% silver filled two-component epoxy-based glue ohmic contacts were attached on the N-Si-C samples. Electrical conductivity was measured in constant current mode. The experimental data show the increase of conductivity with the increase of the nitrogen content. To explain the temperature behavior of electrical conductivity we assumed a thermally activated electric transport mechanism.

Effect of substrates and thickness on optical properties in atomic layer deposition grown ZnO thin films

NASA Astrophysics Data System (ADS)

Pal, Dipayan; Singhal, Jaya; Mathur, Aakash; Singh, Ajaib; Dutta, Surjendu; Zollner, Stefan; Chattopadhyay, Sudeshna

2017-11-01

Atomic Layer Deposition technique was used to grow high quality, very low roughness, crystalline, Zinc Oxide (ZnO) thin films on silicon (Si) and fused quartz (SiO2) substrates to study the optical properties. Spectroscopic ellipsometry results of ZnO/Si system, staggered type-II quantum well, demonstrate that there is a significant drop in the magnitudes of both the real and imaginary parts of complex dielectric constants and in near-band gap absorption along with a blue shift of the absorption edge with decreasing film thickness at and below ∼20 nm. Conversely, UV-vis absorption spectroscopy of ZnO/SiO2, thin type-I quantum well, consisting of a narrower-band gap semiconductor grown on a wider-band gap (insulator) substrate, shows the similar thickness dependent blue-shift of the absorption edge but with an increase in the magnitude of near-band gap absorption with decreasing film thickness. Thickness dependent blue shift, energy vs. 1/d2, in two different systems, ZnO/Si and ZnO/SiO2, show a difference in their slopes. The observed phenomena can be consistently explained by the corresponding exciton (or carrier/s) deconfinement and confinement effects at the ZnO/Si and ZnO/SiO2 interface respectively, where Tanguy-Elliott amplitude pre-factor plays the key role through the electron-hole overlap factor at the interface.

Interfacial Coupling and Electronic Structure of Two-Dimensional Silicon Grown on the Ag(111) Surface at High Temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feng, Jiagui; Wagner, Sean R.; Zhang, Pengpeng

Freestanding silicene, a monolayer of Si arranged in a honeycomb structure, has been predicted to give rise to massless Dirac fermions, akin to graphene. However, Si structures grown on a supporting substrate can show properties that strongly deviate from the freestanding case. Here, combining scanning tunneling microscopy/spectroscopy and differential conductance mapping, we show that the electrical properties of the (√3 x √3) phase of few-layer Si grown on Ag(111) strongly depend on film thickness, where the electron phase coherence length decreases and the free-electron-like surface state gradually diminishes when approaching the interface. These features are presumably attributable to the inelasticmore » inter-band electron-electron scattering originating from the overlap between the surface state, interface state and the bulk state of the substrate. We further demonstrate that the intrinsic electronic structure of the as grown (√3 x √3) phase is identical to that of the (√3 x √3) R30° reconstructed Ag on Si(111), both of which exhibit the parabolic energy-momentum dispersion relation with comparable electron effective masses. Lastly, these findings highlight the essential role of interfacial coupling on the properties of two-dimensional Si structures grown on supporting substrates, which should be thoroughly scrutinized in pursuit of silicene.« less

Encapsulating Elastically Stretchable Neural Interfaces: Yield, Resolution, and Recording/Stimulation of Neural Activity

PubMed Central

Morrison, Barclay; Goletiani, Cezar; Yu, Zhe; Wagner, Sigurd

2013-01-01

A high resolution elastically stretchable microelectrode array (SMEA) to interface with neural tissue is described. The SMEA consists of an elastomeric substrate, such as poly(dimethylsiloxane) (PDMS), elastically stretchable gold conductors, and an electrically insulating encapsulating layer in which contact holes are opened. We demonstrate the feasibility of producing contact holes with 40 µm × 40 µm openings, show why the adhesion of the encapsulation layer to the underlying silicone substrate is weakened during contact hole fabrication, and provide remedies. These improvements result in greatly increased fabrication yield and reproducibility. An SMEA with 28 microelectrodes was fabricated. The contact holes (100 µm × 100 µm) in the encapsulation layer are only ~10% the size of the previous generation, allowing a larger number of microelectrodes per unit area, thus affording the capability to interface with a smaller neural population per electrode. This new SMEA is used to record spontaneous and evoked activity in organotypic hippocampal tissue slices at 0% strain before stretching, at 5 % and 10 % equibiaxial strain, and again at 0% strain after relaxation. The noise of the recordings increases with increasing strain. The frequency of spontaneous neural activity also increases when the SMEA is stretched. Upon relaxation, the noise returns to pre-stretch levels, while the frequency of neural activity remains elevated. Stimulus-response curves at each strain level are measured. The SMEA shows excellent biocompatibility for at least two weeks. PMID:24093006

Decal transfer microfabrication

DOEpatents

Nuzzo, Ralph G.; Childs, William Robert

2004-10-19

A method of making a microstructure includes forming a pattern in a surface of a silicon-containing elastomer, oxidizing the pattern, contacting the pattern with a substrate; and bonding the oxidized pattern and the substrate such that the pattern and the substrate are irreversibly attached. The silicon-containing elastomer may be removably attached to a transfer pad.

Modification of surface properties of cellulosic substrates by quaternized silicone emulsions.

PubMed

Purohit, Parag S; Somasundaran, P

2014-07-15

The present work describes the effect of quaternization of silicones as well as the relevant treatment parameter pH on the frictional, morphological and relaxation properties of fabric substrates. Due to their unique surface properties, silicone polymers are extensively used to modify surface properties of various materials, although the effects of functionalization of silicones and relevant process conditions on modification of substrates are not well understood. Specifically we show a considerable reduction in fabric friction, roughness and waviness upon treatment with quaternized silicones. The treatment at acidic pH results in better deposition of silicone polymers onto the fabric as confirmed through streaming potential measurements which show charge reversal of the fabric. Interestingly, Raman spectroscopy studies show the band of C-O ring stretching mode at ∼1095 cm(-1) shift towards higher wavenumber indicating lowering of stress in fibers upon appropriate silicone treatment. Thus along with the morphological and frictional properties being altered, silicone treatment can lead to a reduction in fabric strain. It is concluded that the electrostatic interactions play an initial role in modification of the fiber substrate followed by multilayer deposition of polymer. This multi-technique approach to study fiber properties upon treatment by combining macro to molecular level methods has helped in understanding of new functional coating materials. Copyright © 2014 Elsevier Inc. All rights reserved.

Probing low noise at the MOS interface with a spin-orbit qubit.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jock, Ryan Michael; Jacobson, Noah Tobias; Harvey-Collard, Patrick

The silicon metal-oxide-semiconductor (MOS) material system is technologically important for the implementation of electron spin-based quantum information technologies. Researchers predict the need for an integrated platform in order to implement useful computation, and decades of advancements in silicon microelectronics fabrication lends itself to this challenge. However, fundamental concerns have been raised about the MOS interface (e.g. trap noise, variations in electron g-factor and practical implementation of multi-QDs). Furthermore, two-axis control of silicon qubits has, to date, required the integration of non-ideal components (e.g. microwave strip-lines, micro-magnets, triple quantum dots, or introduction of donor atoms). In this paper, we introduce amore » spin-orbit (SO) driven singlet- triplet (ST) qubit in silicon, demonstrating all-electrical two-axis control that requires no additional integrated elements and exhibits charge noise properties equivalent to other more model, but less commercially mature, semiconductor systems. We demonstrate the ability to tune an intrinsic spin-orbit interface effect, which is consistent with Rashba and Dresselhaus contributions that are remarkably strong for a low spin-orbit material such as silicon. The qubit maintains the advantages of using isotopically enriched silicon for producing a quiet magnetic environment, measuring spin dephasing times of 1.6 μs using 99.95% 28Si epitaxy for the qubit, comparable to results from other isotopically enhanced silicon ST qubit systems. This work, therefore, demonstrates that the interface inherently provides properties for two-axis control, and the technologically important MOS interface does not add additional detrimental qubit noise. isotopically enhanced silicon ST qubit systems« less

Modifying Surface Fluctuations of Polymer Melt Films with Substrate Modification

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Yang; He, Qiming; Zhang, Fan

Deposition of a plasma polymerized film on a silicon substrate substantially changes the fluctuations on the surface of a sufficiently thin, melt polystyrene (PS) film atop the substrate. Surface fluctuation relaxation times measured with X-ray photon correlation spectroscopy (XPCS) for ca. 4R g thick melt films of 131 kg/mol linear PS on silicon and on a plasma polymer modified silicon wafer can both be described using a hydrodynamic continuum theory (HCT) that assumes the film is characterized throughout its depth by the bulk viscosity. However, when the film thickness is reduced to ~3R g, confinement effects are evident. The surfacemore » fluctuations are slower than predicted using the HCT, and the confinement effect for the PS on silicon is larger than that for the PS on the plasma polymerized film. This deviation is thus due to a difference in the thicknesses of the strongly adsorbed layers at the substrate which are impacted by the substrate surface energy.« less

Modifying Surface Fluctuations of Polymer Melt Films with Substrate Modification

DOE PAGES

Zhou, Yang; He, Qiming; Zhang, Fan; ...

2017-08-14

Deposition of a plasma polymerized film on a silicon substrate substantially changes the fluctuations on the surface of a sufficiently thin, melt polystyrene (PS) film atop the substrate. Surface fluctuation relaxation times measured with X-ray photon correlation spectroscopy (XPCS) for ca. 4R g thick melt films of 131 kg/mol linear PS on silicon and on a plasma polymer modified silicon wafer can both be described using a hydrodynamic continuum theory (HCT) that assumes the film is characterized throughout its depth by the bulk viscosity. However, when the film thickness is reduced to ~3R g, confinement effects are evident. The surfacemore » fluctuations are slower than predicted using the HCT, and the confinement effect for the PS on silicon is larger than that for the PS on the plasma polymerized film. This deviation is thus due to a difference in the thicknesses of the strongly adsorbed layers at the substrate which are impacted by the substrate surface energy.« less

Diamond Composite Films for Protective Coatings on Metals and Method of Formation

NASA Technical Reports Server (NTRS)

Ong, Tiong P. (Inventor); Shing, Yuh-Han (Inventor)

1997-01-01

Composite films consisting of diamond crystallites and hard amorphous films such as diamond-like carbon, titanium nitride, and titanium oxide are provided as protective coatings for metal substrates against extremely harsh environments. A composite layer having diamond crystallites and a hard amorphous film is affixed to a metal substrate via an interlayer including a bottom metal silicide film and a top silicon carbide film. The interlayer is formed either by depositing metal silicide and silicon carbide directly onto the metal substrate, or by first depositing an amorphous silicon film, then allowing top and bottom portions of the amorphous silicon to react during deposition of the diamond crystallites, to yield the desired interlayer structure.

Silicon nitride films deposited with an electron beam created plasma

NASA Technical Reports Server (NTRS)

Bishop, D. C.; Emery, K. A.; Rocca, J. J.; Thompson, L. R.; Zamani, H.; Collins, G. J.

1984-01-01

The electron beam assisted chemical vapor deposition (EBCVD) of silicon nitride films using NH3, N2, and SiH4 as the reactant gases is reported. The films have been deposited on aluminum, SiO2, and polysilicon film substrates as well as on crystalline silicon substrates. The range of experimental conditions under which silicon nitrides have been deposited includes substrate temperatures from 50 to 400 C, electron beam currents of 2-40 mA, electron beam energies of 1-5 keV, total ambient pressures of 0.1-0.4 Torr, and NH3/SiH4 mass flow ratios of 1-80. The physical, electrical, and chemical properties of the EBCVD films are discussed.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Polycrystalline La1-xSrxMnO3 films on silicon: Influence of post-Deposition annealing on structural, (Magneto-)Optical, and (Magneto-)Electrical properties

NASA Astrophysics Data System (ADS)

Thoma, Patrick; Monecke, Manuel; Buja, Oana-Maria; Solonenko, Dmytro; Dudric, Roxana; Ciubotariu, Oana-Tereza; Albrecht, Manfred; Deac, Iosif G.; Tetean, Romulus; Zahn, Dietrich R. T.; Salvan, Georgeta

2018-01-01

The integration of La1-xSrxMnO3 (LSMO) thin film technology into established industrial silicon processes is regarded as challenging due to lattice mismatch, thermal expansion, and chemical reactions at the interface of LSMO and silicon. In this work, we investigated the physical properties of thin La0.73Sr0.27MnO3 films deposited by magnetron sputtering on silicon without a lattice matching buffer layer. The influence of a post-deposition annealing treatment on the structural, (magneto-)optical, and (magneto-)electrical properties was investigated by a variety of techniques. Using Rutherford backscattering spectroscopy, atomic force microscopy, Raman spectroscopy, and X-ray diffraction we could show that the thin films exhibit a polycrystalline, rhombohedral structure after a post-deposition annealing of at least 700 °C. The dielectric tensor in the spectral range from 1.7 eV to 5 eV determined from spectroscopic ellipsometry in combination with magneto-optical Kerr effect spectroscopy was found to be comparable to that of lattice matched films on single crystal substrates reported in literature [1]. The values of the metal-isolator transition temperature and temperature-dependent resistivities also reflect a high degree of crystalline quality of the thermally treated films.

Diffusion reaction of oxygen in HfO2/SiO2/Si stacks.

PubMed

Ferrari, S; Fanciulli, M

2006-08-03

We study the oxidation mechanism of silicon in the presence of a thin HfO2 layer. We performed a set of annealing in 18O2 atmosphere on HfO2/SiO2/Si stacks observing the 18O distribution in the SiO2 layer with time-of-flight secondary ion mass spectrometry (ToF-SIMS). The 18O distribution in HfO2/SiO2/Si stacks upon 18O2 annealing suggests that what is responsible for SiO2 growth is the molecular O2, whereas no contribution is found of the atomic oxygen to the oxidation. By studying the dependence of the oxidation velocity from oxygen partial pressure and annealing temperature, we demonstrate that the rate-determining step of the oxidation is the oxygen exchange at the HfO2/SiO2 interface. When moisture is chemisorbed in HfO2 films, the oxidation of the underlying silicon substrate becomes extremely fast and its kinetics can be described as a wet silicon oxidation process. The silicon oxidation during O2 annealing of the atomic layer deposited HfO2/Si is fast in its early stage due to chemisorbed moisture and becomes slow after the first 10 s.

Reaction layer characterization of the braze joint of silicon nitride to stainless steel

NASA Astrophysics Data System (ADS)

Xu, R.; Indacochea, J. E.

1994-10-01

This investigation studies the role of titanium in the development of the reaction layer in braze joining silicon nitride to stainless steel using titanium-active copper-silver filler metals. This reaction layer formed as a result of titanium diffusing to the filler metal/silicon nitride interface and reacting with the silicon nitride to form the intermetallics, titanium nitride (TiN) and titanium suicide (Ti 5Si3). This reaction layer, as recognized in the literature, allows wetting of the ceramic substrate by the molten filler metal. The reaction layer thickness increases with temperature and time. Its growth rate obeys the parabolic relationship. Activation energies of 220.1 and 210.9 kj/mol were calculated for growth of the reaction layer for the two filler metals used. These values are close to the activation energy of nitrogen in TiN (217.6 kj/mol). Two filler metals were used in this study, Ticusil (68.8 wt% Ag, 26.7 wt% Cu, 4.5 wt% Ti) and CB4 (70.5 wt% Ag, 26.5 wt% Cu, 3.0 wt% Ti). The joints were processed in vacuum at temperatures of 840 to 900 °C at various times. Bonding strength is affected by reaction layer thickness in the absence of Ti-Cu intermetallics in the filler metal matrix.

Surface preparation for high purity alumina ceramics enabling direct brazing in hydrogen atmospheres

DOEpatents

Cadden, Charles H.; Yang, Nancy Yuan Chi; Hosking, Floyd M.

2001-01-01

The present invention relates to a method for preparing the surface of a high purity alumina ceramic or sapphire specimen that enables direct brazing in a hydrogen atmosphere using an active braze alloy. The present invention also relates to a method for directly brazing a high purity alumina ceramic or sapphire specimen to a ceramic or metal member using this method of surface preparation, and to articles produced by this brazing method. The presence of silicon, in the form of a SiO.sub.2 -containing surface layer, can more than double the tensile bond strength in alumina ceramic joints brazed in a hydrogen atmosphere using an active Au-16Ni-0.75 Mo-1.75V filler metal. A thin silicon coating applied by PVD processing can, after air firing, produce a semi-continuous coverage of the alumina surface with a SiO.sub.2 film. Room temperature tensile strength was found to be proportional to the fraction of air fired surface covered by silicon-containing films. Similarly, the ratio of substrate fracture versus interface separation was also related to the amount of surface silicon present prior to brazing. This process can replace the need to perform a "moly-manganese" metallization step.

Methods for passivating silicon devices at low temperature to achieve low interface state density and low recombination velocity while preserving carrier lifetime

DOEpatents

Chen, Zhizhang; Rohatgi, Ajeet

1995-01-01

A new process has been developed to achieve a very low SiO.sub.x /Si interface state density D.sub.it, low recombination velocity S (<2 cm/s), and high effective carrier lifetime T.sub.eff (>5 ms) for oxides deposited on silicon substrates at low temperature. The technique involves direct plasma-enhanced chemical vapor deposition (PECVD), with appropriate growth conditions, followed by a photo-assisted rapid thermal annealing (RTA) process. Approximately 500-A-thick SiO.sub.x layers are deposited on Si by PECVD at 250.degree. C. with 0.02 W/cm.sup.-2 rf power, then covered with SiN or an evaporated thin aluminum layer, and subjected to a photo-assisted anneal in forming gas ambient at 350.degree. C., resulting in an interface state density D.sub.it in the range of about 1-4.times.10.sup.10 cm.sup.-2 eV.sup.-1, which sets a record for the lowest interface state density D.sub.it for PECVD oxides fabricated to date. Detailed analysis shows that the PECVD deposition conditions, photo-assisted anneal, forming gas ambient, and the presence of an aluminum layer on top of the oxides during the anneal, all contributed to this low value of interface state density D.sub.it. Detailed metal-oxide semiconductor analysis and model calculations show that such a low recombination velocity S is the result of moderately high positive oxide charge (5.times.10.sup.11 -1.times.10.sup.12 cm.sup.-2) and relatively low midgap interface state density (1.times.10.sup.10 -4.times.10.sup.10 cm.sup.-2 eV.sup.-1). Photo-assisted anneal was found to be superior to furnace annealing, and a forming gas ambient was better than a nitrogen ambient for achieving a very low surface recombination velocity S.

Rough SERS substrate based on gold coated porous silicon layer prepared on the silicon backside surface

NASA Astrophysics Data System (ADS)

Dridi, H.; Haji, L.; Moadhen, A.

2017-04-01

We report in this paper a novel method to elaborate rough Surface Enhanced Raman Scattering (SERS) substrate. A single layer of porous silicon was formed on the silicon backside surface. Morphological characteristics of the porous silicon layer before and after gold deposition were influenced by the rough character (gold size). The reflectance measurements showed a dependence of the gold nano-grains size on the surface nature, through the Localized Surface Plasmon (LSP) band properties. SERS signal of Rhodamine 6G used as a model analyte, adsorbed on the rough porous silicon layer revealed a marked enhancement of its vibrational modes intensities.

Silicon Nanowire Growth at Chosen Positions and Orientations

NASA Technical Reports Server (NTRS)

Getty, Stephanie A.

2009-01-01

It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.

A study of using femtosecond LIBS in analyzing metallic thin film-semiconductor interface

NASA Astrophysics Data System (ADS)

Galmed, A. H.; Kassem, A. K.; von Bergmann, H.; Harith, M. A.

2011-01-01

Metals and metal alloys are usually employed as interconnections to guide electrical signals between components into the very large scale integrated (VLSI) devices. These devices demand higher complexity, better performance and lower cost. Thin film is a common geometry for these metallic applications, requiring a substrate for rigidity. Accurate depth profile analysis of coatings is becoming increasingly important with expanding industrial use in technological fields. A number of articles devoted to LIBS applications for depth-resolved analysis have been published in recent years. In the present work, we are studying the ability of femtosecond LIBS to make depth profiling for a Ti thin film of thickness 213 nm deposited onto a silicon (100) substrate before and after thermal annealing. The measurements revealed that an average ablation rates of 15 nm per pulse have been achieved. The thin film was examined using X-Ray Diffraction (XRD) and Atomic Force Microscope (AFM), while the formation of the interface was examined using Rutherford Back Scattering (RBS) before and after annealing. To verify the depth profiling results, a theoretical simulation model is presented that gave a very good agreement with the experimental results.

Electrowetting-actuated optical switch based on total internal reflection.

PubMed

Liu, Chao; Wang, Di; Yao, Li-Xiao; Li, Lei; Wang, Qiong-Hua

2015-04-01

In this paper we demonstrate a liquid optical switch based on total internal reflection. Two indium tin oxide electrodes are fabricated on the bottom substrate. A conductive liquid (Liquid 1) is placed on one side of the chamber and surrounded by a density-matched silicone oil (Liquid 2). In initial state, when the light beam illuminates the interface of the two liquids, it just meets the conditions of total internal reflection. The light is totally reflected by Liquid 2, and the device shows light-off state. When we apply a voltage to the other side of the indium tin oxide electrode, Liquid 1 stretched towards this side of the substrate and the curvature of the liquid-liquid interface changes. The light beam is refracted by Liquid 1 and the device shows light-on state. So the device can achieve the functions of an optical switch. Because the light beam can be totally reflected by the liquid, the device can attain 100% light intensity attenuation. Our experiments show that the response time from light-on (off) to light-off (on) are 130 and 132 ms, respectively. The proposed optical switch has potential applications in variable optical attenuators, information displays, and light shutters.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

2003-11-04

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D [Fairfield, CA; Theiss, Steven D [Woodbury, MN; Carey, Paul G [Mountain View, CA; Smith, Patrick M [San Ramon, CA; Wickbold, Paul [Walnut Creek, CA

2006-09-26

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Effect of PECVD SiNx/SiOyNx-Si interface property on surface passivation of silicon wafer

NASA Astrophysics Data System (ADS)

Jia, Xiao-Jie; Zhou, Chun-Lan; Zhu, Jun-Jie; Zhou, Su; Wang, Wen-Jing

2016-12-01

It is studied in this paper that the electrical characteristics of the interface between SiOyNx/SiNx stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiOyNx layer on interface parameters, such as interface state density Dit and fixed charge Qf, and the surface passivation quality of silicon are observed. Capacitance-voltage measurements reveal that inserting a thin SiOyNx layer between the SiNx and the silicon wafer can suppress Qf in the film and Dit at the interface. The positive Qf and Dit and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiOyNx film increasing. Prepared by deposition at a low temperature and a low ratio of N2O/SiH4 flow rate, the SiOyNx/SiNx stacks result in a low effective surface recombination velocity (Seff) of 6 cm/s on a p-type 1 Ω·cm-5 Ω·cm FZ silicon wafer. The positive relationship between Seff and Dit suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA050302) and the National Natural Science Foundation of China (Grant No. 61306076).

Silicon based multilayer photoelectrodes for photoelectrolysis of water to produce hydrogen from the sun

NASA Astrophysics Data System (ADS)

Faruque, Faisal

The main objective of this work is to study different materials for the direct photosynthesis of hydrogen from water. A variety of photocatalysts such as titanium dioxide, titanium oxy-nitride, silicon carbide, and gallium nitride are being investigated by others for the clean production of hydrogen for fuel cells and hydrogen economy. Our approach was to deposit suitable metallic regions on photocatalyst nanoparticles to direct the efficient synthesis of hydrogen to a particular site for convenient collection. We studied different electrode metals such as gold, platinum, titanium, palladium, and tungsten. We also studied different solar cell materials such as silicon (p- and n-types), silicon carbide and titanium dioxide semiconductors in order to efficiently generate electrons under illumination. We introduced a novel silicon-based multilayer photosynthesis device to take advantage of suitable properties of silicon and tungsten to efficiently produce hydrogen. The device consisted of a silicon (0.5mm) substrate, a deposited atomic layer of Al2O 3 (1nm), a doped polysilicon (0.1microm), and finally a tungsten nanoporous (5-10nm) layer acting as an interface electrode with water. The Al2O 3 layer was introduced to reduce leakage current and to prevent the spreading of the diffused p-n junction layer between the silicon and doped polysilicon layers. The surface of the photoelectrode was coated with nanotextured tungsten nanopores (TNP), which increased the surface area of the electrodes to the electrolyte, assisting in electron-hole mobility, and acting as a photocatalyst. The reported device exhibited a fill factor (%FF) of 27.22% and solar-to-hydrogen conversion efficiency of 0.03174%. This thesis describes the structures of the device, and offers a characterization and comparison between different photoelectrodes.

Formation of porous silicon oxide from substrate-bound silicon rich silicon oxide layers by continuous-wave laser irradiation

NASA Astrophysics Data System (ADS)

Wang, Nan; Fricke-Begemann, Th.; Peretzki, P.; Ihlemann, J.; Seibt, M.

2018-03-01

Silicon nanocrystals embedded in silicon oxide that show room temperature photoluminescence (PL) have great potential in silicon light emission applications. Nanocrystalline silicon particle formation by laser irradiation has the unique advantage of spatially controlled heating, which is compatible with modern silicon micro-fabrication technology. In this paper, we employ continuous wave laser irradiation to decompose substrate-bound silicon-rich silicon oxide films into crystalline silicon particles and silicon dioxide. The resulting microstructure is studied using transmission electron microscopy techniques with considerable emphasis on the formation and properties of laser damaged regions which typically quench room temperature PL from the nanoparticles. It is shown that such regions consist of an amorphous matrix with a composition similar to silicon dioxide which contains some nanometric silicon particles in addition to pores. A mechanism referred to as "selective silicon ablation" is proposed which consistently explains the experimental observations. Implications for the damage-free laser decomposition of silicon-rich silicon oxides and also for controlled production of porous silicon dioxide films are discussed.

Galvanic displacement reaction and rapid thermal annealing in size/shape controlling silver nanoparticles on silicon substrate

NASA Astrophysics Data System (ADS)

Ghosh, Tapas; Satpati, Biswarup

2017-05-01

The effect of the thermal annealing on silver nanoparticles deposited on silicon surface has been studied. The silver nanoparticles have been deposited by the galvanic displacement reaction. Rapid thermal annealing (RTA) has been performed on the Si substrate, containing the silver nanoparticles. The scanning transmission electron microscopy (STEM), energy dispersive X-ray (EDX) spectroscopy and scanning electron microscopy (SEM) study show that the galvanic displacement reaction and subsequent rapid thermal annealing could lead to well separated and spherical shaped larger silver nanoparticles on silicon substrate.

Carbon nanotube-copper exhibiting metal-like thermal conductivity and silicon-like thermal expansion for efficient cooling of electronics.

PubMed

Subramaniam, Chandramouli; Yasuda, Yuzuri; Takeya, Satoshi; Ata, Seisuke; Nishizawa, Ayumi; Futaba, Don; Yamada, Takeo; Hata, Kenji

2014-03-07

Increasing functional complexity and dimensional compactness of electronic devices have led to progressively higher power dissipation, mainly in the form of heat. Overheating of semiconductor-based electronics has been the primary reason for their failure. Such failures originate at the interface of the heat sink (commonly Cu and Al) and the substrate (silicon) due to the large mismatch in thermal expansion coefficients (∼300%) of metals and silicon. Therefore, the effective cooling of such electronics demands a material with both high thermal conductivity and a similar coefficient of thermal expansion (CTE) to silicon. Addressing this demand, we have developed a carbon nanotube-copper (CNT-Cu) composite with high metallic thermal conductivity (395 W m(-1) K(-1)) and a low, silicon-like CTE (5.0 ppm K(-1)). The thermal conductivity was identical to that of Cu (400 W m(-1) K(-1)) and higher than those of most metals (Ti, Al, Au). Importantly, the CTE mismatch between CNT-Cu and silicon was only ∼10%, meaning an excellent compatibility. The seamless integration of CNTs and Cu was achieved through a unique two-stage electrodeposition approach to create an extensive and continuous interface between the Cu and CNTs. This allowed for thermal contributions from both Cu and CNTs, resulting in high thermal conductivity. Simultaneously, the high volume fraction of CNTs balanced the thermal expansion of Cu, accounting for the low CTE of the CNT-Cu composite. The experimental observations were in good quantitative concurrence with the theoretically described 'matrix-bubble' model. Further, we demonstrated identical in-situ thermal strain behaviour of the CNT-Cu composite to Si-based dielectrics, thereby generating the least interfacial thermal strain. This unique combination of properties places CNT-Cu as an isolated spot in an Ashby map of thermal conductivity and CTE. Finally, the CNT-Cu composite exhibited the greatest stability to temperature as indicated by its low thermal distortion parameter (TDP). Thus, this material presents a viable and efficient alternative to existing materials for thermal management in electronics.

Improving performance of Si/CdS micro-/nanoribbon p-n heterojunction light emitting diodes by trenched structure

NASA Astrophysics Data System (ADS)

Huang, Shiyuan; Wu, Yuanpeng; Ma, Xiangyang; Yang, Zongyin; Liu, Xu; Yang, Qing

2018-05-01

Realizing high performance silicon based light sources has been an unremitting pursuit for researchers. In this letter, we propose a simple structure to enhance electroluminescence emission and reduce the threshold of injected current of silicon/CdS micro-/nanoribbon p-n heterojunction visible light emitting diodes, by fabricating trenched structure on silicon substrate to mount CdS micro-/nanoribbon. A series of experiments and simulation analysis favors the rationality and validity of our mounting design. After mounting the CdS micro-/nanoribbon, the optical field confinement increases, and absorption and losses from high refractive silicon substrate are effectively reduced. Meanwhile the sharp change of silicon substrate near heterojunction also facilitates the balance between electron current and hole current, which substantially conduces to the stable amplification of electroluminescence emission in CdS micro-/nanoribbon.

Hot-electron-induced hydrogen redistribution and defect generation in metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Buchanan, D. A.; Marwick, A. D.; Dimaria, D. J.; Dori, L.

1994-09-01

Redistribution of hydrogen caused by hot-electron injection has been studied by hydrogen depth profiling with N-15 nuclear reaction analysis and electrical methods. Internal photoemission and Fowler-Nordheim injection were used for electron injection into large Al-gate and polysilicon-gate capacitors, respectively. A hydrogen-rich layer (about 10(exp 15) atoms/sq cm) observed at the Al/SiO2 interface was found to serve as the source of hydrogen during the hot-electron stress. A small fraction of the hydrogen released from this layer was found to be retrapped near the Si/SiO2 interface for large electron fluences in the Al-gate samples. Within the limit of detectability, about 10(exp 14)/sq cm, no hydrogen was measured using nuclear reaction analysis in the polysilicon-gate samples. The buildup of hydrogen at the Si/SiO2 interface exhibits a threshold at about 1 MV/cm, consistent with the threshold for electron heating in SiO2. In the 'wet' SiO2 films with purposely introduced excess hydrogen, the rate of hydrogen buildup at the Si/SiO2 interface is found to be significantly greater than that found in the 'dry' films. During electron injection, hydrogen redistribution was also confirmed via the deactivation of boron dopant in the silicon substrate. The generation rates of interface states, neutral electron traps, and anomalous positive charge are found to increase with increasing hydrogen buildup in the substrate and the initial hydrogen concentration in the film. It is concluded that the generation of defects is preceded by the hot-electron-induced release and transport of atomic hydrogen and it is the chemical reaction of this species within the metal-oxide-semiconductor structure that generates the electrically active defects.

Interface Engineering to Create a Strong Spin Filter Contact to Silicon

PubMed Central

Caspers, C.; Gloskovskii, A.; Gorgoi, M.; Besson, C.; Luysberg, M.; Rushchanskii, K. Z.; Ležaić, M.; Fadley, C. S.; Drube, W.; Müller, M.

2016-01-01

Integrating epitaxial and ferromagnetic Europium Oxide (EuO) directly on silicon is a perfect route to enrich silicon nanotechnology with spin filter functionality. To date, the inherent chemical reactivity between EuO and Si has prevented a heteroepitaxial integration without significant contaminations of the interface with Eu silicides and Si oxides. We present a solution to this long-standing problem by applying two complementary passivation techniques for the reactive EuO/Si interface: (i) an in situ hydrogen-Si (001) passivation and (ii) the application of oxygen-protective Eu monolayers–without using any additional buffer layers. By careful chemical depth profiling of the oxide-semiconductor interface via hard x-ray photoemission spectroscopy, we show how to systematically minimize both Eu silicide and Si oxide formation to the sub-monolayer regime–and how to ultimately interface-engineer chemically clean, heteroepitaxial and ferromagnetic EuO/Si (001) in order to create a strong spin filter contact to silicon. PMID:26975515

Electron-irradiation-induced crystallization at metallic amorphous/silicon oxide interfaces caused by electronic excitation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nagase, Takeshi, E-mail: t-nagase@uhvem.osaka-u.ac.jp; Division of Materials and Manufacturing Science, Graduate School of Engineering, Osaka University, 2-1, Yamada-Oka, Suita, Osaka 565-0871; Yamashita, Ryo

2016-04-28

Irradiation-induced crystallization of an amorphous phase was stimulated at a Pd-Si amorphous/silicon oxide (a(Pd-Si)/SiO{sub x}) interface at 298 K by electron irradiation at acceleration voltages ranging between 25 kV and 200 kV. Under irradiation, a Pd-Si amorphous phase was initially formed at the crystalline face-centered cubic palladium/silicon oxide (Pd/SiO{sub x}) interface, followed by the formation of a Pd{sub 2}Si intermetallic compound through irradiation-induced crystallization. The irradiation-induced crystallization can be considered to be stimulated not by defect introduction through the electron knock-on effects and electron-beam heating, but by the electronic excitation mechanism. The observed irradiation-induced structural change at the a(Pd-Si)/SiO{sub x} and Pd/SiO{sub x}more » interfaces indicates multiple structural modifications at the metal/silicon oxide interfaces through electronic excitation induced by the electron-beam processes.« less

Chemical Bonding Technology: Direct Investigation of Interfacial Bonds

NASA Technical Reports Server (NTRS)

Koenig, J. L.; Boerio, F. J.; Plueddemann, E. P.; Miller, J.; Willis, P. B.; Cuddihy, E. F.

1986-01-01

This is the third Flat-Plate Solar Array (FSA) Project document reporting on chemical bonding technology for terrestrial photovoltaic (PV) modules. The impetus for this work originated in the late 1970s when PV modules employing silicone encapsulation materials were undergoing delamination during outdoor exposure. At that time, manufacturers were not employing adhesion promoters and, hence, module interfaces in common with the silicone materials were only in physical contact and therefore easily prone to separation if, for example, water were to penetrate to the interfaces. Delamination with silicone materials virtually vanished when adhesion promoters, recommended by silicone manufacturers, were used. The activities related to the direct investigation of chemically bonded interfaces are described.

Hybrid emitter all back contact solar cell

DOEpatents

Loscutoff, Paul; Rim, Seung

2016-04-12

An all back contact solar cell has a hybrid emitter design. The solar cell has a thin dielectric layer formed on a backside surface of a single crystalline silicon substrate. One emitter of the solar cell is made of doped polycrystalline silicon that is formed on the thin dielectric layer. The other emitter of the solar cell is formed in the single crystalline silicon substrate and is made of doped single crystalline silicon. The solar cell includes contact holes that allow metal contacts to connect to corresponding emitters.

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2007-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Coated silicon comprising material for protection against environmental corrosion

NASA Technical Reports Server (NTRS)

Hazel, Brian Thomas (Inventor)

2009-01-01

In accordance with an embodiment of the invention, an article is disclosed. The article comprises a gas turbine engine component substrate comprising a silicon material; and an environmental barrier coating overlying the substrate, wherein the environmental barrier coating comprises cerium oxide, and the cerium oxide reduces formation of silicate glass on the substrate upon exposure to corrodant sulfates.

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy (Inventor)

2011-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Enhanced optical output power of InGaN/GaN light-emitting diodes grown on a silicon (111) substrate with a nanoporous GaN layer.

PubMed

Lee, Kwang Jae; Chun, Jaeyi; Kim, Sang-Jo; Oh, Semi; Ha, Chang-Soo; Park, Jung-Won; Lee, Seung-Jae; Song, Jae-Chul; Baek, Jong Hyeob; Park, Seong-Ju

2016-03-07

We report the growth of InGaN/GaN multiple quantum wells blue light-emitting diodes (LEDs) on a silicon (111) substrate with an embedded nanoporous (NP) GaN layer. The NP GaN layer is fabricated by electrochemical etching of n-type GaN on the silicon substrate. The crystalline quality of crack-free GaN grown on the NP GaN layer is remarkably improved and the residual tensile stress is also decreased. The optical output power is increased by 120% at an injection current of 20 mA compared with that of conventional LEDs without a NP GaN layer. The large enhancement of optical output power is attributed to the reduction of threading dislocation, effective scattering of light in the LED, and the suppression of light propagation into the silicon substrate by the NP GaN layer.

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, V.K.

1990-08-21

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications is disclosed. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al[sub x]N[sub y]O[sub z] layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al[sub x]N[sub y]O[sub z] layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, Vinod K.

1990-01-01

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al.sub.x N.sub.y O.sub.z layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al.sub.x N.sub.y O.sub.z layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Phosphorene-directed self-assembly of asymmetric PS-b-PMMA block copolymer for perpendicularly-oriented sub-10 nm PS nanopore arrays

NASA Astrophysics Data System (ADS)

Zhang, Ziming; Zheng, Lu; Khurram, Muhammad; Yan, Qingfeng

2017-10-01

Few-layer black phosphorus, also known as phosphorene, is a new two-dimensional material which is of enormous interest for applications, mainly in electronics and optoelectronics. Herein, we for the first time employ phosphorene for directing the self-assembly of asymmetric polystyrene-block-polymethylmethacrylate (PS-b-PMMA) block copolymer (BCP) thin film to form the perpendicular orientation of sub-10 nm PS nanopore arrays in a hexagonal fashion normal to the interface. We experimentally demonstrate that none of the PS and PMMA blocks exhibit preferential affinity to the phosphorene-modified surface. Furthermore, the perpendicularly-oriented PS nanostructures almost stay unchanged with the variation of number of layers of few-layer phosphorene nanoflakes between 15-30 layers. Differing from the neutral polymer brushes which are widely used for chemical modification of the silicon substrate, phosphorene provides a novel physical way to control the interfacial interactions between the asymmetric PS-b-PMMA BCP thin film and the silicon substrate. Based on our results, it is possible to build a new scheme for producing sub-10 nm PS nanopore arrays oriented perpendicularly to the few-layer phosphorene nanoflakes. Furthermore, the nanostructural microdomains could serve as a promising nanolithography template for surface patterning of phosphorene nanoflakes.

Boron depth profiles and residual damage following rapid thermal annealing of low-temperature BSi molecular ion implantation in silicon

NASA Astrophysics Data System (ADS)

Liang, J. H.; Wang, S. C.

2007-08-01

The influence of substrate temperature on both the implantation and post-annealing characteristics of molecular-ion-implanted 5 × 1014 cm-2 77 keV BSi in silicon was investigated in terms of boron depth profiles and damage microstructures. The substrate temperatures under investigation consisted of room temperature (RT) and liquid nitrogen temperature (LT). Post-annealing treatments were performed using rapid thermal annealing (RTA) at 1050 °C for 25 s. Boron depth profiles and damage microstructures in both the as-implanted and as-annealed specimens were determined using secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM), respectively. The as-implanted results revealed that, compared to the RT specimen, the LT specimen yields a shallower boron depth profile with a reduced tail into the bulk. An amorphous layer containing a smooth amorphous-to-crystalline (a/c) interface is evident in the LT specimen while just the opposite is true in the as-implanted RT one. The as-annealed results illustrated that the extension of the boron depth profile into the bulk via transient-enhanced diffusion (TED) in the LT specimen is less than it is in the RT one. Only residual defects are visible in the LT specimen while two clear bands of dislocation loops appear in the RT one.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Study on Silicon Microstructure Processing Technology Based on Porous Silicon

NASA Astrophysics Data System (ADS)

Shang, Yingqi; Zhang, Linchao; Qi, Hong; Wu, Yalin; Zhang, Yan; Chen, Jing

2018-03-01

Aiming at the heterogeneity of micro - sealed cavity in silicon microstructure processing technology, the technique of preparing micro - sealed cavity of porous silicon is proposed. The effects of different solutions, different substrate doping concentrations, different current densities, and different etching times on the rate, porosity, thickness and morphology of the prepared porous silicon were studied. The porous silicon was prepared by different process parameters and the prepared porous silicon was tested and analyzed. For the test results, optimize the process parameters and experiments. The experimental results show that the porous silicon can be controlled by optimizing the parameters of the etching solution and the doping concentration of the substrate, and the preparation of porous silicon with different porosity can be realized by different doping concentration, so as to realize the preparation of silicon micro-sealed cavity, to solve the sensor sensitive micro-sealed cavity structure heterogeneous problem, greatly increasing the application of the sensor.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon.

PubMed

Ben Slama, Sonia; Hajji, Messaoud; Ezzaouia, Hatem

2012-08-17

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon

PubMed Central

2012-01-01

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications. PMID:22901341

Exceptional cracking behavior in H-implanted Si/B-doped Si0.70Ge0.30/Si heterostructures

NASA Astrophysics Data System (ADS)

Chen, Da; Wang, Dadi; Chang, Yongwei; Li, Ya; Ding, Rui; Li, Jiurong; Chen, Xiao; Wang, Gang; Guo, Qinglei

2018-01-01

The cracking behavior in H-implanted Si/B-doped Si0.70Ge0.30/Si structures after thermal annealing was investigated. The crack formation position is found to closely correlate with the thickness of the buried Si0.70Ge0.30 layer. For H-implanted Si containing a buried 3-nm-thick B-doped Si0.70Ge0.30 layer, localized continuous cracking occurs at the interfaces on both sides of the Si0.70Ge0.30 interlayer. Once the thickness of the buried Si0.70Ge0.30 layer increases to 15 and 70 nm, however, a continuous sharp crack is individually observed along the interface between the Si substrate and the B-doped Si0.70Ge0.30 interlayer. We attribute this exceptional cracking behavior to the existence of shear stress on both sides of the buried Si0.70Ge0.30 layer and the subsequent trapping of hydrogen, which leads to a crack in a well-controlled manner. This work may pave the way for high-quality Si or SiGe membrane transfer in a feasible manner, thus expediting its potential applications to ultrathin silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI) production.

Inhibition of thrombus formation on intravascular sensors by electrical polarization.

PubMed

Schmitt, J M; Baer, M; Meindl, J D; Anderson, M F; Mihm, F G

1984-09-01

Implantable biomedical sensors built on a silicon substrate capped with glass are currently being developed for intravascular applications. Electrical techniques for inhibiting thrombus formation on the surface of a proposed optical sensor in direct contact with blood have been investigated. Glass-on-silicon specimens (4 X 1.2 X 0.4 mm3) were coated with indium-tin oxide, a transparent conductor, and implanted in the vena cava and iliac veins of three dogs for 10, 20, or 33 days. The equilibrium surface-blood interface potentials of the specimens were modified by implanted current sources which supplied either direct current (8-15 microA) or 100 KHz alternating current (5 microA, root mean square). Light-microscopic and scanning electron-microscopic analyses showed each of the DC-polarized specimens to be free of thrombus, in contrast to nonpolarized (control) specimens on which varying amounts of adsorbed protein and thrombus deposits were found. Like the control specimens, the AC-polarized specimens formed thrombus, but the appearance of the deposits differed. These findings support the view that the polarity, magnitude and time dependence of the potential across conducting surface-blood interface significantly influence thrombogenicity. Further work is necessary to determine the roles of electrochemical and electrostatic factors in preventing thrombus formation on foreign materials.

Functional and Selective Bacterial Interfaces Using Cross-Scaffold Gold Binding Peptides

NASA Astrophysics Data System (ADS)

Adams, Bryn L.; Hurley, Margaret M.; Jahnke, Justin P.; Stratis-Cullum, Dimitra N.

2015-11-01

We investigated the functional and selective activity of three phage-derived gold-binding peptides on the Escherichia coli ( E. coli) bacterial cell surface display scaffold (eCPX) for the first time. Gold-binding peptides, p3-Au12 (LKAHLPPSRLPS), p8#9 (VSGSSPDS), and Midas-2 (TGTSVLIATPYV), were compared side-by-side through experiment and simulation. All exhibited strong binding to an evaporated gold film, with approximately a 4-log difference in binding between each peptide and the control sample. The increased affinity for gold was also confirmed by direct visualization of samples using Scanning Electron Microscopy (SEM). Peptide dynamics in solution were performed to analyze innate structure, and all three were found to have a high degree of flexibility. Preferential binding to gold over silicon for all three peptides was demonstrated, with up to four orders of magnitude selectivity exhibited by p3-Au12. The selectivity was also clearly evident through SEM analysis of the boundary between the gold film and silicon substrate. Functional activity of bound E. coli cells was further demonstrated by stimulating filamentation and all three peptides were characterized as prolific relative to control samples. This work shows great promise towards functional and active bacterial-hybrid gold surfaces and the potential to enable the next generation living material interfaces.

Fabrication and Gas-Sensing Properties of Ni-Silicide/Si Nanowires.

PubMed

Hsu, Hsun-Feng; Chen, Chun-An; Liu, Shang-Wu; Tang, Chun-Kai

2017-12-01

Ni-silicide/Si nanowires were fabricated by atomic force microscope nano-oxidation on silicon-on-insulator substrates, selective wet etching, and reactive deposition epitaxy. Ni-silicide nanocrystal-modified Si nanowire and Ni-silicide/Si heterostructure multi-stacked nanowire were formed by low- and high-coverage depositions of Ni, respectively. The Ni-silicide/Si Schottky junction and Ni-silicide region were attributed high- and low-resistance parts of nanowire, respectively, causing the resistance of the Ni-silicide nanocrystal-modified Si nanowire and the Ni-silicide/Si heterostructure multi-stacked nanowire to be a little higher and much lower than that of Si nanowire. An O 2 sensing device was formed from a nanowire that was mounted on Pt electrodes. When the nanowires exposed to O 2 , the increase in current in the Ni-silicide/Si heterostructure multi-stacked nanowire was much larger than that in the other nanowires. The Ni-silicide nanocrystal-modified Si nanowire device had the highest sensitivity. The phenomenon can be explained by the formation of a Schottky junction at the Ni-silicide/Si interface in these two types of Ni-Silicide/Si nanowire and the formation of a hole channel at the silicon nanowire/native oxide interface after exposing the nanowires to O 2 .

Hybrid graphene/silicon Schottky photodiode with intrinsic gating effect

NASA Astrophysics Data System (ADS)

Di Bartolomeo, Antonio; Luongo, Giuseppe; Giubileo, Filippo; Funicello, Nicola; Niu, Gang; Schroeder, Thomas; Lisker, Marco; Lupina, Grzegorz

2017-06-01

We propose a hybrid device consisting of a graphene/silicon (Gr/Si) Schottky diode in parallel with a Gr/SiO2/Si capacitor for high-performance photodetection. The device, fabricated by transfer of commercial graphene on low-doped n-type Si substrate, achieves a photoresponse as high as 3 \\text{A} {{\\text{W}}-1} and a normalized detectivity higher than 3.5× {{10}12} \\text{cm} \\text{H}{{\\text{z}}1/2} {{\\text{W}}-1} in the visible range. It exhibits a photocurrent exceeding the forward current because photo-generated minority carriers, accumulated at Si/SiO2 interface of the Gr/SiO2/Si capacitor, diffuse to the Gr/Si junction. We show that the same mechanism, when due to thermally generated carriers, although usually neglected or disregarded, causes the increased leakage often measured in Gr/Si heterojunctions. We perform extensive I-V and C-V characterization at different temperatures and we measure a zero-bias Schottky barrier height of 0.52 eV at room temperature, as well as an effective Richardson constant A **  =  4× {{10}-5} \\text{A} \\text{c}{{\\text{m}}-2} {{\\text{K}}-2} and an ideality factor n≈ 3.6 , explained by a thin (<1 nm) oxide layer at the Gr/Si interface.

Modified low-temperture direct bonding method for vacuum microelectronics application

NASA Astrophysics Data System (ADS)

Ju, Byeong-Kwon; Lee, Duck-Jung; Choi, Woo-Beom; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1997-06-01

This paper presents the process and experimental results for the improved silicon-to-glass bonding using silicon direct bonding (SDB) followed by anodic bonding. The initial bonding between glass and silicon was caused by the hydrophilic surfaces of silicon-glass ensemble using SDB method. Then the initially bonded specimen had to be strongly bonded by anodic bonding process. The effects of the bonding process parameters on the interface energy were investigated as functions of the bonding temperature and voltage. We found that the specimen which was bonded using SDB process followed by anodic bonding process had higher interface energy than one using anodic bonding process only. The main factor contributing to the higher interface energy in the glass-to-silicon assemble bonded by SDB followed by anodic bonding was investigated by secondary ion mass spectroscopy analysis.

SPS silicon reference system

NASA Technical Reports Server (NTRS)

Woodcock, G. R.

1980-01-01

The design analysis of a silicon power conversion system for the solar power satellite (SPS) is summarized. The solar array, consisting of glass encapsulated 50 micrometer silicon solar cells, is described. The general scheme for power distribution to the array/antenna interface is described. Degradation by proton irradiation is considered. The interface between the solar array and the klystron equipped power transmitter is described.

Substrate for thin silicon solar cells

DOEpatents

Ciszek, Theodore F.

1995-01-01

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1.times.10.sup.-3 ohm-cm.

Effect of the substrate on the insulator-metal transition of vanadium dioxide films

NASA Astrophysics Data System (ADS)

Kovács, György J.; Bürger, Danilo; Skorupa, Ilona; Reuther, Helfried; Heller, René; Schmidt, Heidemarie

2011-03-01

Single-phase vanadium dioxide films grown on (0001) sapphire and (001) silicon substrates show a very different insulator-metal electronic transition. A detailed description of the growth mechanisms and the substrate-film interaction is given, and the characteristics of the electronic transition are described by the morphology and grain boundary structure. (Tri-)epitaxy-stabilized columnar growth of VO2 takes place on the sapphire substrate, whereas on silicon the expected Zone II growth is identified. We have found that in the case of the Si substrate the reasons for the broader hysteresis and the lower switching amplitude are the formation of an amorphous insulating VOx (x > 2.6) phase coexisting with VO2 and the high vanadium vacancy concentration of the VO2. These phenomena are the result of the excess oxygen during the growth and the interaction between the silicon substrate and the growing film.

Die singulation method

DOEpatents

Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.

2013-06-11

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Die singulation method

DOEpatents

Swiler, Thomas P [Albuquerque, NM; Garcia, Ernest J [Albuquerque, NM; Francis, Kathryn M [Rio Rancho, NM

2014-01-07

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with a HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon

PubMed Central

Girel, Kseniya V.; Panarin, Andrei; Terekhov, Sergei N.

2018-01-01

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy. PMID:29883382

High-speed and on-chip graphene blackbody emitters for optical communications by remote heat transfer.

PubMed

Miyoshi, Yusuke; Fukazawa, Yusuke; Amasaka, Yuya; Reckmann, Robin; Yokoi, Tomoya; Ishida, Kazuki; Kawahara, Kenji; Ago, Hiroki; Maki, Hideyuki

2018-03-29

High-speed light emitters integrated on silicon chips can enable novel architectures for silicon-based optoelectronics, such as on-chip optical interconnects, and silicon photonics. However, conventional light sources based on compound semiconductors face major challenges for their integration with a silicon-based platform because of their difficulty of direct growth on a silicon substrate. Here we report ultra-high-speed (100-ps response time), highly integrated graphene-based on-silicon-chip blackbody emitters in the near-infrared region including telecommunication wavelength. Their emission responses are strongly affected by the graphene contact with the substrate depending on the number of graphene layers. The ultra-high-speed emission can be understood by remote quantum thermal transport via surface polar phonons of the substrates. We demonstrated real-time optical communications, integrated two-dimensional array emitters, capped emitters operable in air, and the direct coupling of optical fibers to the emitters. These emitters can open new routes to on-Si-chip, small footprint, and high-speed emitters for highly integrated optoelectronics and silicon photonics.

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon.

PubMed

Bandarenka, Hanna V; Girel, Kseniya V; Zavatski, Sergey A; Panarin, Andrei; Terekhov, Sergei N

2018-05-21

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy.

Graphene-silicon layered structures on single-crystalline Ir(111) thin films

DOE PAGES

Que, Yande D.; Tao, Jing; Zhang, Yong; ...

2015-01-20

Epitaxial growth of graphene on transition metal crystals, such as Ru,⁽¹⁻³⁾ Ir,⁽⁴⁻⁶⁾ and Ni,⁽⁷⁾ provides large-area, uniform graphene layers with controllable defect density, which is crucial for practical applications in future devices. To decrease the high cost of single-crystalline metal bulks, single-crystalline metal films are strongly suggested as the substrates for epitaxial growth large-scale high-quality graphene.⁽⁸⁻¹⁰⁾ Moreover, in order to weaken the interactions of graphene with its metal host, which may result in a suppression of the intrinsic properties of graphene,⁽¹¹ ¹²⁾ the method of element intercalation of semiconductors at the interface between an epitaxial graphene layer and a transitionmore » metal substrate has been successfully realized.⁽¹³⁻¹⁶⁾« less

Electron-phonon coupling in graphene placed between magnetic Li and Si layers on cobalt

NASA Astrophysics Data System (ADS)

Usachov, Dmitry Yu.; Fedorov, Alexander V.; Vilkov, Oleg Yu.; Ogorodnikov, Ilya I.; Kuznetsov, Mikhail V.; Grüneis, Alexander; Laubschat, Clemens; Vyalikh, Denis V.

2018-02-01

Using angle-resolved photoemission spectroscopy (ARPES), we study the electronic structure and electron-phonon coupling in a Li-doped graphene monolayer decoupled from the Co(0001) substrate by intercalation of silicon. Based on the photoelectron diffraction measurements, we disclose the structural properties of the Si/Co interface. Our density functional theory calculations demonstrate that in the studied Li/graphene/Si/Co system the magnetism of Co substrate induces notable magnetic moments on Li and Si atoms. At the same time graphene remains almost nonmagnetic and clamped between two magnetically active atomic layers with antiparallel magnetizations. ARPES maps of the graphene Fermi surface reveal strong electron doping, which may lead to superconductivity mediated by electron-phonon coupling (EPC). Analysis of the spectral function of photoelectrons reveals apparent anisotropy of EPC in the k space. These properties make the studied system tempting for studying the relation between superconductivity and magnetism in two-dimensional materials.

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1982-01-01

Ferroelectric films of barium titanate were synthesized on silicon and quartz substrates, and the photoelectric effect in the structure consisting of metal deposited ferroelectric barium titanate film silicon was studied. A photovoltage with polarity that depends on the direction of the remanent polarization was observed. The deposition of BaTiO3 on silicon and fused quartz substrates was accomplished by an rf sputtering technique. A series of experiments to study the growth of ferroelectric BaTiO3 films on single crystal silicon and fused quartz substrates were conducted. The ferroelectric character in these films was found on the basis of evidence from the polarization electric field hysteresis loops, capacitance voltage and capacitance temperature techniques and from X-ray diffraction studies.

Method for providing an arbitrary three-dimensional microstructure in silicon using an anisotropic deep etch

DOEpatents

Morales, Alfredo M.; Gonzales, Marcela

2004-06-15

The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch the silicon substrate and therefore provides the ability etch structures of variable depths.

Biofunctionalization on alkylated silicon substrate surfaces via "click" chemistry.

PubMed

Qin, Guoting; Santos, Catherine; Zhang, Wen; Li, Yan; Kumar, Amit; Erasquin, Uriel J; Liu, Kai; Muradov, Pavel; Trautner, Barbara Wells; Cai, Chengzhi

2010-11-24

Biofunctionalization of silicon substrates is important to the development of silicon-based biosensors and devices. Compared to conventional organosiloxane films on silicon oxide intermediate layers, organic monolayers directly bound to the nonoxidized silicon substrates via Si-C bonds enhance the sensitivity of detection and the stability against hydrolytic cleavage. Such monolayers presenting a high density of terminal alkynyl groups for bioconjugation via copper-catalyzed azide-alkyne 1,3-dipolar cycloaddition (CuAAC, a "click" reaction) were reported. However, yields of the CuAAC reactions on these monolayer platforms were low. Also, the nonspecific adsorption of proteins on the resultant surfaces remained a major obstacle for many potential biological applications. Herein, we report a new type of "clickable" monolayers grown by selective, photoactivated surface hydrosilylation of α,ω-alkenynes, where the alkynyl terminal is protected with a trimethylgermanyl (TMG) group, on hydrogen-terminated silicon substrates. The TMG groups on the film are readily removed in aqueous solutions in the presence of Cu(I). Significantly, the degermanylation and the subsequent CuAAC reaction with various azides could be combined into a single step in good yields. Thus, oligo(ethylene glycol) (OEG) with an azido tag was attached to the TMG-alkyne surfaces, leading to OEG-terminated surfaces that reduced the nonspecific adsorption of protein (fibrinogen) by >98%. The CuAAC reaction could be performed in microarray format to generate arrays of mannose and biotin with varied densities on the protein-resistant OEG background. We also demonstrated that the monolayer platform could be functionalized with mannose for highly specific capturing of living targets (Escherichia coli expressing fimbriae) onto the silicon substrates.

Injection doping of ultrathin microcrystalline silicon films prepared by CC-CVD

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koynov, S.; Grebner, S.; Schwarz, R.

1997-07-01

Recently, the authors have proposed a cyclic method, referred to as Closed Chamber CVD (CC-CVD), for the preparation of {micro}c-Si films of high crystalline fraction at increased deposition rates. In this work, they first report new process conditions of CC-CVD, which result in growth of highly crystalline films with a sharp interface on a foreign substrate. Then these conditions are further used together with a pulsed injection of B{sub 2}H{sub 6} in an appropriate moment of each cycle, so that the disturbance of the crystallization process is prevented. A series of ultrathin {micro}c-Si films, doped by this technique, is characterizedmore » by conductivity measurements, SEM, Raman Scattering, optical transmission and UV reflection. A strong reduction of the transient interface layer is achieved and conductivity as high as 2 S/cm with an activation energy of 27 meV is reached.« less

Understanding Pt-ZnO:In Schottky nanocontacts by conductive atomic force microscopy

NASA Astrophysics Data System (ADS)

Chirakkara, Saraswathi; Choudhury, Palash Roy; Nanda, K. K.; Krupanidhi, S. B.

2016-04-01

Undoped and In doped ZnO (IZO) thin films are grown on Pt coated silicon substrates Pt/Si by pulsed laser deposition to fabricate Pt/ZnO:In Schottky diodes. The Schottky diodes were investigated by conventional two-probe current-voltage (I-V) measurements and by the I-V spectroscopy tool of conductive atomic force microscopy (C-AFM). The large deviation of the ideality factor from unity and the temperature dependent Schottky barrier heights (SBHs) obtained from the conventional method imply the presence of inhomogeneous interfaces. The inhomogeneity of SBHs is confirmed by C-AFM. Interestingly, the I-V curves at different points are found to be different, and the SBHs deduced from the point diodes reveal inhomogeneity at the nanoscale at the metal-semiconductor interface. A reduction in SBH and turn-on voltage along with enhancement in forward current are observed with increasing indium concentration.

Quantum cascade lasers grown on silicon.

PubMed

Nguyen-Van, Hoang; Baranov, Alexei N; Loghmari, Zeineb; Cerutti, Laurent; Rodriguez, Jean-Baptiste; Tournet, Julie; Narcy, Gregoire; Boissier, Guilhem; Patriarche, Gilles; Bahriz, Michael; Tournié, Eric; Teissier, Roland

2018-05-08

Technological platforms offering efficient integration of III-V semiconductor lasers with silicon electronics are eagerly awaited by industry. The availability of optoelectronic circuits combining III-V light sources with Si-based photonic and electronic components in a single chip will enable, in particular, the development of ultra-compact spectroscopic systems for mass scale applications. The first circuits of such type were fabricated using heterogeneous integration of semiconductor lasers by bonding the III-V chips onto silicon substrates. Direct epitaxial growth of interband III-V laser diodes on silicon substrates has also been reported, whereas intersubband emitters grown on Si have not yet been demonstrated. We report the first quantum cascade lasers (QCLs) directly grown on a silicon substrate. These InAs/AlSb QCLs grown on Si exhibit high performances, comparable with those of the devices fabricated on their native InAs substrate. The lasers emit near 11 µm, the longest emission wavelength of any laser integrated on Si. Given the wavelength range reachable with InAs/AlSb QCLs, these results open the way to the development of a wide variety of integrated sensors.

Deposition and characterization of silicon thin-films by aluminum-induced crystallization

NASA Astrophysics Data System (ADS)

Ebil, Ozgenc

Polycrystalline silicon (poly-Si) as a thin-film solar cell material could have major advantages compared to non-silicon thin-film technologies. In theory, thin-film poly-Si may retain the performance and stability of c-Si while taking advantage of established manufacturing techniques. However, poly-Si films deposited onto foreign substrates at low temperatures typically have an average grain size of 10--50 nm. Such a grain structure presents a potential problem for device performance since it introduces an excessive number of grain boundaries which, if left unpassivated, lead to poor solar cell properties. Therefore, for optimum device performance, the grain size of the poly-Si film should be at least comparable to the thickness of the films. For this project, the objectives were the deposition of poly-Si thin-films with 2--5 mum grain size on glass substrates using in-situ and conventional aluminum-induced crystallization (AIC) and the development of a model for AIC process. In-situ AIC experiments were performed using Hot-Wire Chemical Vapor Deposition (HWCVD) both above and below the eutectic temperature (577°C) of Si-Al binary system. Conventional AIC experiments were performed using a-Si layers deposited on aluminum coated glass substrates by Electron-beam deposition, Plasma Enhanced Chemical Vapor Deposition (PECVD) and HWCVD. Continuous poly-Si films with an average grain size of 10 mum on glass substrates were achieved by both in-situ and conventional aluminum-induced crystallization of Si below eutectic temperature. The grain size was determined by three factors; the grain structure of Al layer, the nature of the interfacial oxide, and crystallization temperature. The interface oxide was found to be crucial for AIC process but not necessary for crystallization itself. The characterization of interfacial oxide layer formed on Al films revealed a bilayer structure containing Al2O3 and Al(OH)3 . The effective activation energy for AIC process was determined to be 0.9 eV and depended on the nature of the interfacial oxide layer. Poly-Si layers prepared by AIC technique can be used as seed layers for epitaxial growth of bulk Si layer or as back contacts in c-Si based solar cells.

A study of substrate-liquid crystal interaction

NASA Astrophysics Data System (ADS)

Zhang, Baoshe

This thesis concerns the study of substrate-liquid crystal interaction from two different angles. In one approach, we used the IPS (in-plane switching) technique to investigate the liquid crystal alignment by rubbed polyimide films. The IPS mode of liquid crystal cell operation is facilitated through comb electrodes capable of producing planar electric field. We have fabricated comb electrodes with a periodicity of 2 mum in order to confine the planar electric field close to the liquid crystal-substrate interface. Through optical transmittance measurements and comparison with theoretical predictions based on the Ladau-de Gennes formalism, we found the experimental data to be consistent with the physical picture of soft anchoring, in which the liquid crystal director at the substrate interface is rotated azimuthally under the planar electric field. As a result, we were able to obtain the azimuthal anchoring strength as a fitting parameter of the theory. This part of the thesis thus presents evidence(s) for director switching at the liquid crystal-substrate interface, as well as a method for measuring the azimuthal anchoring strength through optical means. In the second approach, we used nano-lithographic technique to fabricate textured two dimensional periodic patterns on silicon wafers, and examined the resulting liquid crystal alignment effect of such textured substrates. It was found that with decreasing periodicity, there exists an orientational transition from a state in which the liquid crystal alignment copies the substrate pattern at larger periodicity, to a state of uniform alignment at smaller periodicity. In our system, this transition occurs at a periodicity between 0.4 mum and 0.8 mum. Through theoretical simulations based on the model of competition between the elastic distortion energy and the interfacial anchoring potential, it was found that there is indeed a first-order abrupt transition when the periodicity is decreased. This is due to the fact that the elastic distortion energy scales as the inverse of the periodicity squared. Hence when the periodicity is decreased, the elastic distortion energy increases rapidly. At the critical periodicity the elastic distortion energy crosses the interfacial anchoring potential, below which the uniform alignment becomes the lower energy state. The uniform-aligned state was confirmed by the excellent theory-experiment agreement on spectral measurements, in conjunction with the optical microscope observations. In the uniform-aligned state, a large pretilt angle (35°) was obtained.

Method for enhancing the solubility of dopants in silicon

DOEpatents

Sadigh, Babak; Lenosky, Thomas J.; De La Rubia, Tomas Diaz

2003-09-30

A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility was largely enhanced (more than 100%) by a compressive bi-axial strain, based on a size-mismatch theory since the boron atoms are smaller than the silicon atoms. It has been found that the large enhancement or mixing properties of dopants in silicon and germanium substrates is primarily governed by their, and to second order by their size-mismatch with the substrate. Further, it has been determined that the dopant solubility enhancement with strain is most effective when the charge and the size-mismatch of the impurity favor the same type of strain. Thus, the solid solubility of small p-type (e.g., boron) as well as large n-type (e.g., arsenic) dopants can be raised most dramatically by appropriate bi-axial (compressive) strain, and that solubility of a large p-type dopant (e.g, indium) in silicon will be raised due to size-mismatch with silicon, which favors tensile strain, while its negative charge prefers compressive strain, and thus the two effects counteract each other.

Enhanced adhesion of films to semiconductors or metals by high energy bombardment

NASA Technical Reports Server (NTRS)

Tombrello, Thomas A. (Inventor); Qiu, Yuanxun (Inventor); Mendenhall, Marcus H. (Inventor)

1985-01-01

Films (12) of a metal such as gold or other non-insulator materials are firmly bonded to other non-insulators such as semiconductor substrates (10), suitably silicon or gallium arsenide by irradiating the interface with high energy ions. The process results in improved adhesion without excessive doping and provides a low resistance contact to the semiconductor. Thick layers can be bonded by depositing or doping the interfacial surfaces with fissionable elements or alpha emitters. The process can be utilized to apply very small, low resistance electrodes (78) to light-emitting solid state laser diodes (60) to form a laser device 70.

Generic process for preparing a crystalline oxide upon a group IV semiconductor substrate

DOEpatents

McKee, Rodney A.; Walker, Frederick J.; Chisholm, Matthew F.

2000-01-01

A process for growing a crystalline oxide epitaxially upon the surface of a Group IV semiconductor, as well as a structure constructed by the process, is described. The semiconductor can be germanium or silicon, and the crystalline oxide can generally be represented by the formula (AO).sub.n (A'BO.sub.3).sub.m in which "n" and "m" are non-negative integer repeats of planes of the alkaline earth oxides or the alkaline earth-containing perovskite oxides. With atomic level control of interfacial thermodynamics in a multicomponent semiconductor/oxide system, a highly perfect interface between a semiconductor and a crystalline oxide can be obtained.

Hafnium silicate and hafnium silicon oxynitride gate dielectrics for strained Si_xGe_1-x: Interface stability

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

Strained Si_xGe_1-x layers have gained considerable attention due to hole mobility enhancement, and ease of integration with Si-based CMOS technology. The deposition of stable high-κ dielectrics [1] such as hafnium silicate and hafnium silicon oxynitride in direct contact with SiGe would simultaneously improve the capacitance of the gate stack and lower the leakage current for high performance SiGe devices. However, the oxidation of the Si_xGe_1-x substrate either during dielectric deposition or post-deposition processing would degrade device performance due to the thermodynamic instability of germanium oxide [2,3]. Results from XPS, HR-TEM, and C-V, and I-V analyses after various annealing treatments will be presented for hafnium silicate and hafnium silicon oxynitride films deposited on strained Si_xGe_1-x(100), and correlated with dielectric-Si_xGe_1-x(100) interface stability. Implications to the introduction of these oxides as viable gate dielectric candidates for SiGe-based CMOS technology will be discussed. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001) [2] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [3] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995)

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Mizoguchi, Seiya; Shimatani, Naoki; Kobayashi, Mizuki; Makino, Takaomi; Yamaoka, Yu; Kodera, Tetsuo

2018-04-01

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

Microelectromechanical pump utilizing porous silicon

DOEpatents

Lantz, Jeffrey W [Albuquerque, NM; Stalford, Harold L [Norman, OK

2011-07-19

A microelectromechanical (MEM) pump is disclosed which includes a porous silicon region sandwiched between an inlet chamber and an outlet chamber. The porous silicon region is formed in a silicon substrate and contains a number of pores extending between the inlet and outlet chambers, with each pore having a cross-section dimension about equal to or smaller than a mean free path of a gas being pumped. A thermal gradient is provided along the length of each pore by a heat source which can be an electrical resistance heater or an integrated circuit (IC). A channel can be formed through the silicon substrate so that inlet and outlet ports can be formed on the same side of the substrate, or so that multiple MEM pumps can be connected in series to form a multi-stage MEM pump. The MEM pump has applications for use in gas-phase MEM chemical analysis systems, and can also be used for passive cooling of ICs.

First-Principle Investigation on the Bonding Mechanism of the Silicon Particles on the Copper Foil in Cold Spraying

NASA Astrophysics Data System (ADS)

Song, Jun; Liu, Juanfang; Chen, Qinghua

For lithium-ion batteries, the composite silicon-based electrodes can prevent from losing electrical contact and hence retain the capacity over many cycles. To uncover the adhesion mechanism on the interface formed by the copper foil and the thin silicon coatings during the cold gas dynamic spraying (CGDS) at the microscopic level, the first-principle calculations are performed to investigate the interface properties between them. The ideal work of adhesion, fracture toughness and the interface electronic properties are analyzed. It is found that all the atoms on the interface have vertical displacements, and covalent and ionic bonds are formed between the interfacial Cu and Si atoms which increases the bonding strength. However, the ideal work of adhesion on the interface is lower than one of the Cu bulk and Si bulk, so that fracture would be easier to take place on the interface.

High concentration effects of neutral-potential-well interface traps on recombination dc current-voltage lineshape in metal-oxide-silicon transistors

NASA Astrophysics Data System (ADS)

Chen, Zuhui; Jie, Bin B.; Sah, Chih-Tang

2008-11-01

Steady-state Shockley-Read-Hall kinetics is employed to explore the high concentration effect of neutral-potential-well interface traps on the electron-hole recombination direct-current current-voltage (R-DCIV) properties in metal-oxide-silicon field-effect transistors. Extensive calculations include device parameter variations in neutral-trapping-potential-well electron interface-trap density NET (charge states 0 and -1), dopant impurity concentration PIM, oxide thickness Xox, forward source/drain junction bias VPN, and transistor temperature T. It shows significant distortion of the R-DCIV lineshape by the high concentrations of the interface traps. The result suggests that the lineshape distortion observed in past experiments, previously attributed to spatial variation in surface impurity concentration and energy distribution of interface traps in the silicon energy gap, can also arise from interface-trap concentration along surface channel region.

Silicon nanomembranes as a means to evaluate stress evolution in deposited thin films

Treesearch

Anna M. Clausen; Deborah M. Paskiewicz; Alireza Sadeghirad; Joseph Jakes; Donald E. Savage; Donald S. Stone; Feng Liu; Max G. Lagally

2014-01-01

Thin-film deposition on ultra-thin substrates poses unique challenges because of the potential for a dynamic response to the film stress during deposition. While theoretical studies have investigated film stress related changes in bulk substrates, little has been done to learn how stress might evolve in a film growing on a compliant substrate. We use silicon...

Soft lithographic functionalization and patterning oxide-free silicon and germanium.

PubMed

Bowers, Carleen M; Toone, Eric J; Clark, Robert L; Shestopalov, Alexander A

2011-12-16

The development of hybrid electronic devices relies in large part on the integration of (bio)organic materials and inorganic semiconductors through a stable interface that permits efficient electron transport and protects underlying substrates from oxidative degradation. Group IV semiconductors can be effectively protected with highly-ordered self-assembled monolayers (SAMs) composed of simple alkyl chains that act as impervious barriers to both organic and aqueous solutions. Simple alkyl SAMs, however, are inert and not amenable to traditional patterning techniques. The motivation for immobilizing organic molecular systems on semiconductors is to impart new functionality to the surface that can provide optical, electronic, and mechanical function, as well as chemical and biological activity. Microcontact printing (μCP) is a soft-lithographic technique for patterning SAMs on myriad surfaces. Despite its simplicity and versatility, the approach has been largely limited to noble metal surfaces and has not been well developed for pattern transfer to technologically important substrates such as oxide-free silicon and germanium. Furthermore, because this technique relies on the ink diffusion to transfer pattern from the elastomer to substrate, the resolution of such traditional printing is essentially limited to near 1 μm. In contrast to traditional printing, inkless μCP patterning relies on a specific reaction between a surface-immobilized substrate and a stamp-bound catalyst. Because the technique does not rely on diffusive SAM formation, it significantly expands the diversity of patternable surfaces. In addition, the inkless technique obviates the feature size limitations imposed by molecular diffusion, facilitating replication of very small (<200 nm) features. However, up till now, inkless μCP has been mainly used for patterning relatively disordered molecular systems, which do not protect underlying surfaces from degradation. Here, we report a simple, reliable high-throughput method for patterning passivated silicon and germanium with reactive organic monolayers and demonstrate selective functionalization of the patterned substrates with both small molecules and proteins. The technique utilizes a preformed NHS-reactive bilayered system on oxide-free silicon and germanium. The NHS moiety is hydrolyzed in a pattern-specific manner with a sulfonic acid-modified acrylate stamp to produce chemically distinct patterns of NHS-activated and free carboxylic acids. A significant limitation to the resolution of many μCP techniques is the use of PDMS material which lacks the mechanical rigidity necessary for high fidelity transfer. To alleviate this limitation we utilized a polyurethane acrylate polymer, a relatively rigid material that can be easily functionalized with different organic moieties. Our patterning approach completely protects both silicon and germanium from chemical oxidation, provides precise control over the shape and size of the patterned features, and gives ready access to chemically discriminated patterns that can be further functionalized with both organic and biological molecules. The approach is general and applicable to other technologically-relevant surfaces.

Synthesis and metrology of conducting carbon nanotube assemblies

NASA Astrophysics Data System (ADS)

Longson, Timothy Jay

Since its discovery, the carbon nanotube (CNT) has been proposed as one of the ultimate materials for its electrical, thermal and mechanical properties due to its incredibly strong sp2 bonds, low defect density, and large aspect ratio. Many experimental results on individual CNTs have confirmed these outstanding theoretically predicted properties. However, scaling these properties to the macroscopic regime has proved to be challenging. This work focused on the synthesis and measurement of highly conducting, macroscopic, CNT assemblies. Scaling up the synthesis of vertically aligned multiwalled CNT (MWNT) forests was investigated through the development of a large, 100mm, wafer scale, cold wall chemical vapor deposition chamber. In addition to the synthesis, two distinct CNT assemblies have been investigated. A linear morphology where CNTs are strung in series for electrical transport (CNT wires) and a massively parallel 2D array of vertically aligned CNTs for Thermal Interface Material (TIM) applications. Poymer-CNT wire composites have been fabricated by developing a coaxial CNT core-polymer shell electrospinning technique. The core-shell interactions in this system have been studied by way of Hansen's solubility parameters. The most well defined CNT core was achieved using a core solvent that is semi-immiscible with the shell solution, yet still a solvent of the shell polymer. Electrical characterization of the resulting CNT core has shown a two orders of magnitude increase in conductivity over traditional, homogeneously mixed, electrospun CNT wires. A number of vertically aligned MWNT assemblies were studied for their thermal interface properties. Double-sided Silicon substrate (MWNT-Si-MWNT) TIM assemblies were characterized using a DC, 1D reference bar, thermal measurement technique. While attempts to control MWNT density via a micelle template technique produced only 'spaghetti like' CNTs, sputter deposited catalyst provided stark variations in array density. Relevant array morphologies such as density, height, and crystallinity were studied in conjunction with their thermal performance. A Euler buckling model was used to identify the transition between increasing and decreasing resistance with density over array height, these two regimes are explained by way of contact analysis. Self catalyzing Fecralloy substrate MWNT TIMs were studied in a similar vein to the Silicon based assemblies. This substrate was investigated because of its malleability, ease of CNT synthesis and increased CNT adhesion. The growth behavior was studied with respect to the array morphologies, i.e. array height, density, crystallinity, and diameter, while the contact resistance was evaluated using a DC, 1D reference bar technique. The best performing samples were found to have a factor of two increase over their Si counterparts. Temperature dependent thermal measurements offer insight into the interfacial phonon conduction physics and are found to agree with other temperature dependent studies, suggesting inelastic scattering at the MWNT-Cu interface. Due to the challenges associated with deliberately controlling a single array morphology, a statistical approach was used for identifying the influences of the multivariate array morphology on contact resistance. Showing the strongest correlation with array height, following a R ~ L-0.5. Several models were investigated to help explain this behavior, although little insight is gained over the empirical relations. To better characterize these MWNT TIM assemblies two experimental techniques were developed. A transient 3o thermal measurement technique was adapted to characterize the thermal performance of CNT TIMs, offering insight into the limiting resistance in a mulilayer material stack. The MWNT-growth substrate interface was found to dominate in the Si samples while the MWNT-opposing substrate interface dominated in the Fecralloy samples. These measurements strongly supported the DC thermal measurements and the qualitative observations of substrate adhesion. Additionally, a new technique for observing nano sized contacts was established by viewing contact loading through an electron transparent membrane, imaged under an SEM. The contrast mechanism is explained by a voltage contrast phenomenon developed by trapped charges at the interface. The resolution limits have been studied by way of electron beam interactions and the use of Monte Carlo simulations, showing nanometer resolution with appropriate experimental conditions. The real MWNT contact area was found to be less than 1/100th the apparent contact area even at moderate pressures and the number of contacting CNTs is approximately 1/10th the total number of CNTs. These results confirm experimental measurement values for van der Waals adhesion strengths and thermal interface resistance.

Towards substrate engineering of graphene-silicon Schottky diode photodetectors.

PubMed

Selvi, Hakan; Unsuree, Nawapong; Whittaker, Eric; Halsall, Matthew P; Hill, Ernie W; Thomas, Andrew; Parkinson, Patrick; Echtermeyer, Tim J

2018-02-15

Graphene-silicon Schottky diode photodetectors possess beneficial properties such as high responsivities and detectivities, broad spectral wavelength operation and high operating speeds. Various routes and architectures have been employed in the past to fabricate devices. Devices are commonly based on the removal of the silicon-oxide layer on the surface of silicon by wet-etching before deposition of graphene on top of silicon to form the graphene-silicon Schottky junction. In this work, we systematically investigate the influence of the interfacial oxide layer, the fabrication technique employed and the silicon substrate on the light detection capabilities of graphene-silicon Schottky diode photodetectors. The properties of devices are investigated over a broad wavelength range from near-UV to short-/mid-infrared radiation, radiation intensities covering over five orders of magnitude as well as the suitability of devices for high speed operation. Results show that the interfacial layer, depending on the required application, is in fact beneficial to enhance the photodetection properties of such devices. Further, we demonstrate the influence of the silicon substrate on the spectral response and operating speed. Fabricated devices operate over a broad spectral wavelength range from the near-UV to the short-/mid-infrared (thermal) wavelength regime, exhibit high photovoltage responses approaching 10 6 V W -1 and short rise- and fall-times of tens of nanoseconds.

Solution and interfacial behavior of modified silicone polymers and their interactions with solid substrates

NASA Astrophysics Data System (ADS)

Purohit, Parag

Surface treatment is very important step in many applications such as fabric finishing, coatings, cosmetics and personal care. Silicone polymers are a class of organic/inorganic materials that show unique properties such as weak intermolecular forces and high flexibility enabling even a very high molecular weight chain to achieve optimal orientation on surfaces. Material properties such as softness, repellency, bounciness and friction can therefore be tailored by using appropriately modified silicone polymers. Despite wide applications, the underlying mechanisms of material modification are unknown and tailoring silicones for applications remains mostly empirical. Thus the objective of this research is to understand the solution and interfacial behavior of functionalized silicone polymers, which govern their performance in material modification. Modified silicones are simultaneously hydrophobic and oleophobic in nature and due to this nearly universal non-compatibility, the studies of these polymers present unusual challenges. Due to this incompatible nature, the functionalized silicone polymers were emulsified into O/W emulsions to study their solution and interfacial properties. The colloidal properties such as electrokinetic and droplet distribution of these emulsions are assumed to play an important role in the observed surface and physical properties of solid substrates (in present study, cellulosic substrates) as well the stability of emulsions itself. To understand the effects of modified silicones on cellulosic substrates a variety of techniques such as frictional analysis, scanning electron microscopy and atomic force microscopy that can probe from macro to nano level were used. It is hypothesized that the size distribution and charge of silicone emulsions as well as the physiochemical conditions such as pH, control silicone conformation which in turn affect the modification of the substrate properties. With bimodal droplet distribution of silicone emulsions, the nano-sized droplets can penetrate deeper into the substrate to provide bounciness, whereas macro-sized droplets can coat the top layer leading to friction reduction. It was observed that at pH 5.5 the silicone treatment resulted in charge reversal of fibers as opposed to treatment at pH 9.5. On a macroscopic scale 20% reduction in frictional coefficient of the fabric was observed after treatment with quaternized (cationically modified) silicones as compared to untreated fibers. It was also observed using AFM that the fibrils treated with quaternized silicones are uniform, well stacked and smoother than the untreated fibers. Spectroscopic analysis of treated fibers using Raman spectroscopy indicated a decrease in fiber stress as a function of modification of silicone polymer and the interaction pH. It is concluded that the protonated amine functional silicone (below pH 7) as well as the quaternized silicone interacts with the negatively charged cellulose fibers primarily through electrostatic interactions. It is proposed that this initial surface coating is a uniform thin film which allows further deposition of polymer from the emulsion. It was observed that at high pH the zetapotential of silicone emulsions decreases drastically and the nano emulsions turn turbid. It is proposed that the observed electrophoretic and nephelometric behavior at high pH is due to flocculation of nanosized droplets to micron size, which eventually leads to droplets coalescing and emulsion destabilization. It is also postulated that the nano emulsion possess a critical dilution concentration (CDC), above which dilution leads to rapid coalescence. This critical dilution phase was further confirmed through polarity parameter and excimer formation studies which show significantly different polymer and surfactant microstructures near the CDC. Hence it is concluded that the observed surface properties of the substrate obtained above the CDC are significantly different than those below the CDC. The results reveal the vital role of physiochemical parameters such as pH, droplet size, and concentration on the emulsion stability as well as the observed physical/chemical properties of the substrates.

Substrate for thin silicon solar cells

DOEpatents

Ciszek, T.F.

1995-03-28

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1{times}10{sup {minus}3} ohm-cm. 4 figures.

Silicon-integrated thin-film structure for electro-optic applications

DOEpatents

McKee, Rodney A.; Walker, Frederick Joseph

2000-01-01

A crystalline thin-film structure suited for use in any of an number of electro-optic applications, such as a phase modulator or a component of an interferometer, includes a semiconductor substrate of silicon and a ferroelectric, optically-clear thin film of the perovskite BaTiO.sub.3 overlying the surface of the silicon substrate. The BaTiO.sub.3 thin film is characterized in that substantially all of the dipole moments associated with the ferroelectric film are arranged substantially parallel to the surface of the substrate to enhance the electro-optic qualities of the film.

Coated article and method of making

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Lee, Kang Neung (Inventor)

2003-01-01

An article includes a silicon-containing substrate and a modified mullite coating. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating. The article can further comprise a thermal barrier coating applied to the modified mullite coating. The modified mullite coating functions as a bond coating between the external environmental/thermal barrier coating and the silicon-containing substrate. In a method of forming an article, a silicon-containing substrate is formed and a modified mullite coating is applied. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating.

Coated article and method of making

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Lee, Kang Neung (Inventor)

2002-01-01

An article includes a silicon-containing substrate and a modified mullite coating. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating. The article can further comprise a thermal barrier coating applied to the modified mullite coating. The modified mullite coating functions as a bond coating between the external environmental/thermal barrier coating and the silicon-containing substrate. In a method of forming an article, a silicon-containing substrate is formed and a modified mullite coating is applied. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating.

RF Transmission Lines on Silicon Substrates

NASA Technical Reports Server (NTRS)

Ponchak, George E.

1999-01-01

A review of RF transmission lines on silicon substrates is presented. Through measurements and calculated results, it is shown that attenuation is dominated by conductor loss if silicon substrates with a resistivity greater than 2500 Ohm-cm are used. Si passivation layers affect the transmission line attenuation; however, measured results demonstrate that passivation layers do not necessarily increase attenuation. If standard, low resistivity Si wafers must be used, alternative transmission lines such as thin film microstrip and Co-Planar Waveguide (CPW) on thick polyimide layers must be used. Measured results presented here show that low loss per unit length is achievable with these transmission lines.

Thermal transport study across interface “nanostructured solid surface / fluid” by photoacoustic technique

NASA Astrophysics Data System (ADS)

Voitenko, K.; Isaiev, M.; Pastushenko, A.; Andrusenko, D.; Kuzmich, A.; Lysenko, V.; Burbelo, R.

2017-01-01

In the paper the experimental study of heat transport across the interface “porous silicon/liquid” by photoacoustic technique is reported. Two cases with and without liquid covering of porous silicon surface were considered. Thermal perturbations were excited at the surface of porous silicon as a result of absorption of the light with modulated intensity. The resulting thermal-elastic stresses arising in the system were registered with piezoelectric transducer. The amplitude-frequency dependencies of the voltage on the piezoelectric electrodes were measured. The presence of the liquid film leads to decreasing of the amplitude of photoacoustic signal as a result of the thermal energy evacuation from the porous silicon into the liquid. The experimental dependencies were fitted with the results of simulation that takes into account heat fluxes separation at the porous silicon/liquid interface. With the presented method one can precisely measure heat fluxes transferred from the solid into contacting fluid. Moreover, the presented approach can be easily adopted for the thermal conductivity study of the different nanofluids as well as thermal resistance at the interface nanostructured solid/fluid.

Charge-coupled device for low background observations

NASA Technical Reports Server (NTRS)

Loh, Edwin D. (Inventor); Cheng, Edward S. (Inventor)

2002-01-01

A charge-coupled device with a low-emissivity metal layer located between a sensing layer and a substrate provides reduction in ghost images. In a typical charge-coupled device of a silicon sensing layer, a silicon dioxide insulating layer, with a glass substrate and a metal carrier layer, a near-infrared photon, not absorbed in the first pass, enters the glass substrate, reflects from the metal carrier, thereby returning far from the original pixel in its entry path. The placement of a low-emissivity metal layer between the glass substrate and the sensing layer reflects near infrared photons before they reach the substrate so that they may be absorbed in the silicon nearer the pixel of their points of entry so that the reflected ghost image is coincident with the primary image for a sharper, brighter image.

Interfacial Thermal Conductance Limit and Thermal Rectification Across Vertical Carbon Nanotube/Graphene Nanoribbon-Silicon Interfaces

DTIC Science & Technology

2013-01-01

Interfacial thermal conductance limit and thermal rectification across vertical carbon nanotube/graphene nanoribbon-silicon interfaces Ajit K...054308 (2013) Investigation on interfacial thermal resistance and phonon scattering at twist boundary of silicon J. Appl. Phys. 113, 053513 (2013...2013 to 00-00-2013 4. TITLE AND SUBTITLE Interfacial thermal conductance limit and thermal rectification across vertical carbon nanotube/graphene

Formation of iron disilicide on amorphous silicon

NASA Astrophysics Data System (ADS)

Erlesand, U.; Östling, M.; Bodén, K.

1991-11-01

Thin films of iron disilicide, β-FeSi 2 were formed on both amorphous silicon and on crystalline silicon. The β-phase is reported to be semiconducting with a direct band-gap of about 0.85-0.89 eV. This phase is known to form via a nucleation-controlled growth process on crystalline silicon and as a consequence a rather rough silicon/silicide interface is usually formed. In order to improve the interface a bilayer structure of amorphous silicon and iron was sequentially deposited on Czochralski <111> silicon in an e-gun evaporation system. Secondary ion mass spectrometry profiling (SIMS) and scanning electron micrographs revealed an improvement of the interface sharpness. Rutherford backscattering spectrometry (RBS) and X-ray diffractiometry showed β-FeSi 2 formation already at 525°C. It was also observed that the silicide growth was diffusion-controlled, similar to what has been reported for example in the formation of NiSi 2 for the reaction of nickel on amorphous silicon. The kinetics of the FeSi 2 formation in the temperature range 525-625°C was studied by RBS and the activation energy was found to be 1.5 ± 0.1 eV.

Potential-based and non-potential-based cohesive zone formulations under mixed-mode separation and over-closure-Part II: Finite element applications

NASA Astrophysics Data System (ADS)

Máirtín, Éamonn Ó.; Parry, Guillaume; Beltz, Glenn E.; McGarry, J. Patrick

2014-02-01

This paper, the second of two parts, presents three novel finite element case studies to demonstrate the importance of normal-tangential coupling in cohesive zone models (CZMs) for the prediction of mixed-mode interface debonding. Specifically, four new CZMs proposed in Part I of this study are implemented, namely the potential-based MP model and the non-potential-based NP1, NP2 and SMC models. For comparison, simulations are also performed for the well established potential-based Xu-Needleman (XN) model and the non-potential-based model of van den Bosch, Schreurs and Geers (BSG model). Case study 1: Debonding and rebonding of a biological cell from a cyclically deforming silicone substrate is simulated when the mode II work of separation is higher than the mode I work of separation at the cell-substrate interface. An active formulation for the contractility and remodelling of the cell cytoskeleton is implemented. It is demonstrated that when the XN potential function is used at the cell-substrate interface repulsive normal tractions are computed, preventing rebonding of significant regions of the cell to the substrate. In contrast, the proposed MP potential function at the cell-substrate interface results in negligible repulsive normal tractions, allowing for the prediction of experimentally observed patterns of cell cytoskeletal remodelling. Case study 2: Buckling of a coating from the compressive surface of a stent is simulated. It is demonstrated that during expansion of the stent the coating is initially compressed into the stent surface, while simultaneously undergoing tangential (shear) tractions at the coating-stent interface. It is demonstrated that when either the proposed NP1 or NP2 model is implemented at the stent-coating interface mixed-mode over-closure is correctly penalised. Further expansion of the stent results in the prediction of significant buckling of the coating from the stent surface, as observed experimentally. In contrast, the BSG model does not correctly penalise mixed-mode over-closure at the stent-coating interface, significantly altering the stress state in the coating and preventing the prediction of buckling. Case study 3: Application of a displacement to the base of a bi-layered composite arch results in a symmetric sinusoidal distribution of normal and tangential traction at the arch interface. The traction defined mode mixity at the interface ranges from pure mode II at the base of the arch to pure mode I at the top of the arch. It is demonstrated that predicted debonding patterns are highly sensitive to normal-tangential coupling terms in a CZM. The NP2, XN, and BSG models exhibit a strong bias towards mode I separation at the top of the arch, while the NP1 model exhibits a bias towards mode II debonding at the base of the arch. Only the SMC model provides mode-independent behaviour in the early stages of debonding. This case study provides a practical example of the importance of the behaviour of CZMs under conditions of traction controlled mode mixity, following from the theoretical analysis presented in Part I of this study.

Quantifying the limits of through-plane thermal dissipation in 2D-material-based systems

NASA Astrophysics Data System (ADS)

Yasaei, Poya; Behranginia, Amirhossein; Hemmat, Zahra; El-Ghandour, Ahmed I.; Foster, Craig D.; Salehi-Khojin, Amin

2017-09-01

Through-plane thermal transport accounts for a major fraction of heat dissipation from hot-spots in many existing devices made of two-dimensional (2D) materials. In this report, we performed a set of electrical thermometry measurements and 3D finite element analyses to quantify the limits of power dissipation in monolayer graphene, a representative of 2D materials, fabricated on various technologically viable substrates such as chemical vapor deposited (CVD) diamond, tape-casted (sintered) aluminum nitride (AlN), and single crystalline c-plane sapphire as well as silicon with different oxide layers. We demonstrate that the heat dissipation through graphene on AlN substrate near room temperature outperforms those of CVD diamond and other studied substrates, owing to its superior thermal boundary conductance (TBC). At room temperature, our measurements reveal a TBC of 33.5 MW · m-2 · K-1 for graphene on AlN compared to 6.2 MW · m-2 · K-1 on diamond. This study highlights the importance of simultaneous optimization of the interfaces and the substrate and provides a route to maximize the heat removal capability of 2D-material-based devices.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Comparative study of initial stages of copper immersion deposition on bulk and porous silicon

NASA Astrophysics Data System (ADS)

Bandarenka, Hanna; Prischepa, Sergey L.; Fittipaldi, Rosalba; Vecchione, Antonio; Nenzi, Paolo; Balucani, Marco; Bondarenko, Vitaly

2013-02-01

Initial stages of Cu immersion deposition in the presence of hydrofluoric acid on bulk and porous silicon were studied. Cu was found to deposit both on bulk and porous silicon as a layer of nanoparticles which grew according to the Volmer-Weber mechanism. It was revealed that at the initial stages of immersion deposition, Cu nanoparticles consisted of crystals with a maximum size of 10 nm and inherited the orientation of the original silicon substrate. Deposited Cu nanoparticles were found to be partially oxidized to Cu2O while CuO was not detected for all samples. In contrast to porous silicon, the crystal orientation of the original silicon substrate significantly affected the sizes, density, and oxidation level of Cu nanoparticles deposited on bulk silicon.

Elemental and compound semiconductor surface chemistry: Intelligent interfacial design facilitated through novel functionalization and deposition strategies

NASA Astrophysics Data System (ADS)

Porter, Lon Alan, Jr.

The fundamental understanding of silicon surface chemistry is an essential tool for silicon's continued dominance of the semiconductor industry in the years to come. By tapping into the vast library of organic functionalities, the synthesis of organic monolayers may be utilized to prepare interfaces, tailored to a myriad of applications ranging from silicon VLSI device optimization and MEMS to physiological implants and chemical sensors. Efforts in our lab to form stable organic monolayers on porous silicon through direct silicon-carbon linkages have resulted in several efficient functionalization methods. In the first chapter of this thesis a comprehensive review of these methods, and many others is presented. The following chapter and the appendix serve to demonstrate both potential applications and studies aimed at developing a fundamental understanding of the chemistry behind the organic functionalization of silicon surfaces. The remainder of this thesis attempts to demonstrate new methods of metal deposition onto both elemental and compound semiconductor surfaces. Currently, there is considerable interest in producing patterned metallic structures with reduced dimensions for use in technologies such as ULSI device fabrication, MEMS, and arrayed nanosensors, without sacrificing throughput or cost effectiveness. Research in our laboratory has focused on the preparation of precious metal thin films on semiconductor substrates via electroless deposition. Continuous metallic films form spontaneously under ambient conditions, in the absence of a fluoride source or an externally applied current. In order to apply this metallization method toward the development of useful technologies, patterning utilizing photolithography, microcontact printing, and scanning probe nanolithography has been demonstrated.

Process for Polycrystalline film silicon growth

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2001-01-01

A process for depositing polycrystalline silicon on substrates, including foreign substrates, occurs in a chamber at about atmospheric pressure, wherein a temperature gradient is formed, and both the atmospheric pressure and the temperature gradient are maintained throughout the process. Formation of a vapor barrier within the chamber that precludes exit of the constituent chemicals, which include silicon, iodine, silicon diiodide, and silicon tetraiodide. The deposition occurs beneath the vapor barrier. One embodiment of the process also includes the use of a blanketing gas that precludes the entrance of oxygen or other impurities. The process is capable of repetition without the need to reset the deposition zone conditions.

Heteroepitaxial Writing of Silicon-on-Sapphire Nanowires.

PubMed

Xu, Mingkun; Xue, Zhaoguo; Wang, Jimmy; Zhao, Yaolong; Duan, Yao; Zhu, Guangyao; Yu, Linwei; Xu, Jun; Wang, Junzhuan; Shi, Yi; Chen, Kunji; Roca I Cabarrocas, Pere

2016-12-14

The heteroepitaxial growth of crystal silicon thin films on sapphire, usually referred to as SoS, has been a key technology for high-speed mixed-signal integrated circuits and processors. Here, we report a novel nanoscale SoS heteroepitaxial growth that resembles the in-plane writing of self-aligned silicon nanowires (SiNWs) on R-plane sapphire. During a low-temperature growth at <350 °C, compared to that required for conventional SoS fabrication at >900 °C, the bottom heterointerface cultivates crystalline Si pyramid seeds within the catalyst droplet, while the vertical SiNW/catalyst interface subsequently threads the seeds into continuous nanowires, producing self-oriented in-plane SiNWs that follow a set of crystallographic directions of the sapphire substrate. Despite the low-temperature fabrication process, the field effect transistors built on the SoS-SiNWs demonstrate a high on/off ratio of >5 × 10 4 and a peak hole mobility of >50 cm 2 /V·s. These results indicate the novel potential of deploying in-plane SoS nanowire channels in places that require high-performance nanoelectronics and optoelectronics with a drastically reduced thermal budget and a simplified manufacturing procedure.

A mechanism of charge transport in electroluminescent structures consisting of porous silicon and single-crystal silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evtukh, A. A., E-mail: dept_5@isp.kiev.ua; Kaganovich, E. B.; Manoilov, E. G.

2006-02-15

Electroluminescent structures that emit in the visible region of the spectrum and are based on porous silicon (por-Si) formed on the p-Si substrate electrolytically using an internal current source are fabricated. The photoluminescent and electroluminescent properties, as well as the current-and capacitance-voltage characteristics of the structures are studied. Electroluminescence is observed only if the forward bias voltage is applied to the structure; the electroluminescence mechanism is based on the injection and is related to the radiative recombination of electrons and holes in quantum-dimensional Si nanocrystals. The injection of holes is controlled by the condition of their accumulation in the space-chargemore » region of p-Si and by a comparatively low concentration of electronic states at the por-Si/p-Si interface. The charge transport in por-Si is caused by the direct tunneling of charge carriers between the quantum-mechanical levels, which is ensured by an appreciable number of quantum-dimensional Si nanocrystals. The leakage currents are low as a result of a small variance in the sizes of Si nanocrystals and the absence of comparatively large nanocrystals.« less

Laser desorption ionization and peptide sequencing on laser induced silicon microcolumn arrays

DOEpatents

Vertes, Akos [Reston, VA; Chen, Yong [San Diego, CA

2011-12-27

The present invention provides a method of producing a laser-patterned silicon surface, especially silicon wafers for use in laser desorption ionization (LDI-MS) (including MALDI-MS and SELDI-MS), devices containing the same, and methods of testing samples employing the same. The surface is prepared by subjecting a silicon substrate to multiple laser shots from a high-power picosecond or femtosecond laser while in a processing environment, e.g., underwater, and generates a remarkable homogenous microcolumn array capable of providing an improved substrate for LDI-MS.

Multi-gas interaction modeling on decorated semiconductor interfaces: A novel Fermi distribution-based response isotherm and the inverse hard/soft acid/base concept

NASA Astrophysics Data System (ADS)

Laminack, William; Gole, James

2015-12-01

A unique MEMS/NEMS approach is presented for the modeling of a detection platform for mixed gas interactions. Mixed gas analytes interact with nanostructured decorating metal oxide island sites supported on a microporous silicon substrate. The Inverse Hard/Soft acid/base (IHSAB) concept is used to assess a diversity of conductometric responses for mixed gas interactions as a function of these nanostructured metal oxides. The analyte conductometric responses are well represented using a combination diffusion/absorption-based model for multi-gas interactions where a newly developed response absorption isotherm, based on the Fermi distribution function is applied. A further coupling of this model with the IHSAB concept describes the considerations in modeling of multi-gas mixed analyte-interface, and analyte-analyte interactions. Taking into account the molecular electronic interaction of both the analytes with each other and an extrinsic semiconductor interface we demonstrate how the presence of one gas can enhance or diminish the reversible interaction of a second gas with the extrinsic semiconductor interface. These concepts demonstrate important considerations in the array-based formats for multi-gas sensing and its applications.

The influence of interface on spin pumping effect in Ni{sub 80}Fe{sub 20} /Tb bilayer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yue, Jinjin; Jiang, Sheng; Zhang, Dong

2016-05-15

Focusing on the interface effect of the Ni{sub 80}Fe{sub 20} (Py)/terbium (Tb) bilayer, the influence of interface on the magnetization dynamic damping is investigated systematically. Two series of Py (12 nm)/Tb (d nm) films with and without copper (Cu) (1 nm) interlayer are deposited on silicon (Si) substrates by DC magnetron sputtering at room temperature. From vibrating sample magnetometer (VSM) measurements, the saturation magnetization (M{sub s}) decreases with increasing Tb thickness in Py/Tb bilayer while the decrease of M{sub s} is suppressed efficiently by inserting a Cu layer with even 1 nm of thickness. From the frequency dependence of ferromagneticmore » resonance (FMR) linewidth, we can obtain the Gilbert damping coefficient (α), α is found to exhibit an extreme enhancement in comparison to the single Py layer and shows an increasing trend with increasing Tb thickness. By inserting the Cu layer, α decreases significantly. From theoretical fitting, the spin diffusion length (λ{sub SD}) and spin mixing conductance (g{sup ↑↓}) are determined. It shows that the interface structure influences the spin mixing conductance but not the spin diffusion length.« less

Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

NASA Astrophysics Data System (ADS)

Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

2018-01-01

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

Modification of Semiconductor Surfaces through Si-N Linkages by Wet-Chemistry Approaches and Modular Functionalization of Zinc Oxide Surfaces for Chemical Protection of Material Morphology

NASA Astrophysics Data System (ADS)

Gao, Fei

Semiconductor substrates are widely used in many applications. Multiple practical uses involving these materials require the ability to tune their physical and chemical properties to adjust those to a specific application. In recent years, surface and interface reactions have affected dramatically device fabrication and material design. Novel surface functionalization techniques with diverse chemical approaches make the desired physical, thermal, electrical, and mechanical properties attainable. Meanwhile, the modified surface can serve as one of the most important key steps for further assembly process in order to make novel devices and materials. In the following chapters, novel chemical approaches to the functionalization of silicon and zinc oxide substrates will be reviewed and discussed. The specific functionalities including amines, azides, and alkynes on surfaces of different materials will be applied to address subsequent attachment of large molecules and assembly processes. This research is aimed to develop new strategies for manipulating the surface properties of semiconductor materials in a controlled way. The findings of these investigations will be relevant for future applications in molecular and nanoelectronics, sensing, and solar energy conversion. The ultimate goals of the projects are: 1) Preparation of an oxygen-and carbon-free silicon surface based exclusively on Si-N linkages for further modification protocols.. This project involves designing the surface reaction of hydrazine on chlorine-terminated silicon surface, introduction of additional functional group through dehydrohalogenation condensation reaction and direct covalent attachment of C60. 2) Demonstrating alternative method to anchor carbon nanotubes to solid substrates directly through the carbon cage.. This project targets surface modification of silicon and gold substrates with amine-terminated organic monolayers and the covalent attachment of nonfunctionalized and carboxylic acid-functionalized carbon nanotubes. 3) Designing a universal method for the modular functionalization of zinc oxide surface for the chemical protection of material morphology.. This project involves surface modification of zinc oxide nanopowder under vacuum condition with propiolic acid, followed by "click" reaction. A combination of spectroscopy and microscopy techniques was utilized to study the surface functionalization and assembly processes. Fourier-transform infrared spectroscopy (FT-IR), X-ray photoelectron spectroscopy (XPS) and time of fight secondary ion mass spectroscopy (ToF-SIMS) were employed to elucidate the chemical structure of the modified surface. Atomic force microscopy (AFM), transmission electron microscopy (TEM) and scanning electron microscopy (SEM) were combined to obtain the surface morphological information. Density functional theory (DFT) calculations were applied to confirm the experimental results and to suggest plausible reaction mechanisms. Other complementary techniques for these projects also include nuclear magnetic resonance (NMR) spectroscopy to identify the chemical species on the surface and charge-carrier lifetime measurements to evaluate the electronic property of C60-modified silicon surface.

High Efficiency Organic/Silicon-Nanowire Hybrid Solar Cells: Significance of Strong Inversion Layer

PubMed Central

Yu, Xuegong; Shen, Xinlei; Mu, Xinhui; Zhang, Jie; Sun, Baoquan; Zeng, Lingsheng; Yang, Lifei; Wu, Yichao; He, Hang; Yang, Deren

2015-01-01

Organic/silicon nanowires (SiNWs) hybrid solar cells have recently been recognized as one of potentially low-cost candidates for photovoltaic application. Here, we have controllably prepared a series of uniform silicon nanowires (SiNWs) with various diameters on silicon substrate by metal-assisted chemical etching followed by thermal oxidization, and then fabricated the organic/SiNWs hybrid solar cells with poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT:PSS). It is found that the reflective index of SiNWs layer for sunlight depends on the filling ratio of SiNWs. Compared to the SiNWs with the lowest reflectivity (LR-SiNWs), the solar cell based on the SiNWs with low filling ratio (LF-SiNWs) has a higher open-circuit voltage and fill factor. The capacitance-voltage measurements have clarified that the built-in potential barrier at the LF-SiNWs/PEDOT:PSS interface is much larger than that at the LR-SiNWs/PEDOT one, which yields a strong inversion layer generating near the silicon surface. The formation of inversion layer can effectively suppress the carrier recombination, reducing the leakage current of solar cell, and meanwhile transfer the LF-SiNWs/PEDOT:PSS device into a p-n junction. As a result, a highest efficiency of 13.11% is achieved for the LF-SiNWs/PEDOT:PSS solar cell. These results pave a way to the fabrication of high efficiency organic/SiNWs hybrid solar cells. PMID:26610848

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

NASA Astrophysics Data System (ADS)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

High Efficiency Organic/Silicon-Nanowire Hybrid Solar Cells: Significance of Strong Inversion Layer.

PubMed

Yu, Xuegong; Shen, Xinlei; Mu, Xinhui; Zhang, Jie; Sun, Baoquan; Zeng, Lingsheng; Yang, Lifei; Wu, Yichao; He, Hang; Yang, Deren

2015-11-27

Organic/silicon nanowires (SiNWs) hybrid solar cells have recently been recognized as one of potentially low-cost candidates for photovoltaic application. Here, we have controllably prepared a series of uniform silicon nanowires (SiNWs) with various diameters on silicon substrate by metal-assisted chemical etching followed by thermal oxidization, and then fabricated the organic/SiNWs hybrid solar cells with poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) ( PSS). It is found that the reflective index of SiNWs layer for sunlight depends on the filling ratio of SiNWs. Compared to the SiNWs with the lowest reflectivity (LR-SiNWs), the solar cell based on the SiNWs with low filling ratio (LF-SiNWs) has a higher open-circuit voltage and fill factor. The capacitance-voltage measurements have clarified that the built-in potential barrier at the LF-SiNWs/ PSS interface is much larger than that at the LR-SiNWs/PEDOT one, which yields a strong inversion layer generating near the silicon surface. The formation of inversion layer can effectively suppress the carrier recombination, reducing the leakage current of solar cell, and meanwhile transfer the LF-SiNWs/ PSS device into a p-n junction. As a result, a highest efficiency of 13.11% is achieved for the LF-SiNWs/ PSS solar cell. These results pave a way to the fabrication of high efficiency organic/SiNWs hybrid solar cells.

Strain-Engineered Nanomembrane Substrates for Si/SiGe Heterostructures

NASA Astrophysics Data System (ADS)

Sookchoo, Pornsatit

For Group IV materials, including silicon, germanium, and their alloys, although they are most widely used in the electronics industry, the development of photonic devices is hindered by indirect band gaps and large lattice mismatches. Thus, any heterostructures involving Si and Ge (4.17% lattice mismatch) are subject to plastic relaxation by dislocation formation in the heterolayers. These defects make many devices impossible and at minimum degrade the performance of those that are possible. Fabrication using elastic strain engineering in Si/SiGe nanomembranes (NMs) is an approach that is showing promise to overcome this limitation. A key advantage of such NM substrates over conventional bulk substrates is that they are relaxed elastically and therefore free of dislocations that occur in the conventional fabrication of SiGe substrates, which are transferred to the epilayers and roughen film interfaces. In this thesis, I use the strain engineering of NMs or NM stacks to fabricate substrates for the epitaxial growth of many repeating units of Si/SiGe heterostructure, known as a 'superlattice', by the elastic strain sharing of a few periods of the repeating unit of Si/SiGe heterolayers or a Si/SiGe/Si tri-layer structure. In both cases, the process begins with the epitaxial growth of Si/SiGe heterolayers on silicon-on-insulator (SOI), where each layer thickness is designed to stay below its kinetic critical thickness for the formation of dislocations. The heterostructure NMs are then released by etching of the SiO2 sacrificial layer in hydrofluoric acid. The resulting freestanding NMs are elastically relaxed by the sharing of strain between the heterolayers. The NMs can be bonded in-place to their host substrate or transferred to another host substrate for the subsequent growth of many periods of superlattice film. The magnitude of strain sharing in these freestanding NMs is influenced by their layer thicknesses and layer compositions. As illustrated in this dissertation, strain-engineering of such NMs can provide the enabling basis for improved Group IV optoelectronic devices.