High-speed and high-efficiency travelling wave single-photon detectors embedded in nanophotonic circuits

PubMed Central

Pernice, W.H.P.; Schuck, C.; Minaeva, O.; Li, M.; Goltsman, G.N.; Sergienko, A.V.; Tang, H.X.

2012-01-01

Ultrafast, high-efficiency single-photon detectors are among the most sought-after elements in modern quantum optics and quantum communication. However, imperfect modal matching and finite photon absorption rates have usually limited their maximum attainable detection efficiency. Here we demonstrate superconducting nanowire detectors atop nanophotonic waveguides, which enable a drastic increase of the absorption length for incoming photons. This allows us to achieve high on-chip single-photon detection efficiency up to 91% at telecom wavelengths, repeatable across several fabricated chips. We also observe remarkably low dark count rates without significant compromise of the on-chip detection efficiency. The detectors are fully embedded in scalable silicon photonic circuits and provide ultrashort timing jitter of 18 ps. Exploiting this high temporal resolution, we demonstrate ballistic photon transport in silicon ring resonators. Our direct implementation of a high-performance single-photon detector on chip overcomes a major barrier in integrated quantum photonics. PMID:23271658

A Rapid Method for Optimizing Running Temperature of Electrophoresis through Repetitive On-Chip CE Operations

PubMed Central

Kaneda, Shohei; Ono, Koichi; Fukuba, Tatsuhiro; Nojima, Takahiko; Yamamoto, Takatoki; Fujii, Teruo

2011-01-01

In this paper, a rapid and simple method to determine the optimal temperature conditions for denaturant electrophoresis using a temperature-controlled on-chip capillary electrophoresis (CE) device is presented. Since on-chip CE operations including sample loading, injection and separation are carried out just by switching the electric field, we can repeat consecutive run-to-run CE operations on a single on-chip CE device by programming the voltage sequences. By utilizing the high-speed separation and the repeatability of the on-chip CE, a series of electrophoretic operations with different running temperatures can be implemented. Using separations of reaction products of single-stranded DNA (ssDNA) with a peptide nucleic acid (PNA) oligomer, the effectiveness of the presented method to determine the optimal temperature conditions required to discriminate a single-base substitution (SBS) between two different ssDNAs is demonstrated. It is shown that a single run for one temperature condition can be executed within 4 min, and the optimal temperature to discriminate the SBS could be successfully found using the present method. PMID:21845077

Towards a Generic and Adaptive System-On-Chip Controller for Space Exploration Instrumentation

NASA Technical Reports Server (NTRS)

Iturbe, Xabier; Keymeulen, Didier; Yiu, Patrick; Berisford, Dan; Hand, Kevin; Carlson, Robert; Ozer, Emre

2015-01-01

This paper introduces one of the first efforts conducted at NASA’s Jet Propulsion Laboratory (JPL) to develop a generic System-on-Chip (SoC) platform to control science instruments that are proposed for future NASA missions. The SoC platform is named APEX-SoC, where APEX stands for Advanced Processor for space Exploration, and is based on a hybrid Xilinx Zynq that combines an FPGA and an ARM Cortex-A9 dual-core processor on a single chip. The Zynq implements a generic and customizable on-chip infrastructure that can be reused with a variety of instruments, and it has been coupled with a set of off-chip components that are necessary to deal with the different instruments. We have taken JPL’s Compositional InfraRed Imaging Spectrometer (CIRIS), which is proposed for NASA icy moons missions, as a use-case scenario to demonstrate that the entire data processing, control and interface of an instrument can be implemented on a single device using the on-chip infrastructure described in this paper. We show that the performance results achieved in this preliminary version of the instrumentation controller are sufficient to fulfill the science requirements demanded to the CIRIS instrument in future NASA missions, such as Europa.

A single chip VLSI Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Shao, H. M.; Truong, T. K.; Hsu, I. S.; Deutsch, L. J.; Reed, I. S.

1986-01-01

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip.

Real-Time Reed-Solomon Decoder

NASA Technical Reports Server (NTRS)

Maki, Gary K.; Cameron, Kelly B.; Owsley, Patrick A.

1994-01-01

Generic Reed-Solomon decoder fast enough to correct errors in real time in practical applications designed to be implemented in fewer and smaller very-large-scale integrated, VLSI, circuit chips. Configured to operate in pipelined manner. One outstanding aspect of decoder design is that Euclid multiplier and divider modules contain Galoisfield multipliers configured as combinational-logic cells. Operates at speeds greater than older multipliers. Cellular configuration highly regular and requires little interconnection area, making it ideal for implementation in extraordinarily dense VLSI circuitry. Flight electronics single chip version of this technology implemented and available.

On-chip beamsplitter operation on single photons from quasi-resonantly excited quantum dots embedded in GaAs rib waveguides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rengstl, U.; Schwartz, M.; Herzog, T.

2015-07-13

We present an on-chip beamsplitter operating on a single-photon level by means of a quasi-resonantly driven InGaAs/GaAs quantum dot. The single photons are guided by rib waveguides and split into two arms by an evanescent field coupler. Although the waveguides themselves support the fundamental TE and TM modes, the measured degree of polarization (∼90%) reveals the main excitation and propagation of the TE mode. We observe the preserved single-photon nature of a quasi-resonantly excited quantum dot by performing a cross-correlation measurement on the two output arms of the beamsplitter. Additionally, the same quantum dot is investigated under resonant excitation, wheremore » the same splitting ratio is observed. An autocorrelation measurement with an off-chip beamsplitter on a single output arm reveal the single-photon nature after evanescent coupling inside the on-chip splitter. Due to their robustness, adjustable splitting ratio, and their easy implementation, rib waveguide beamsplitters with embedded quantum dots provide a promising step towards fully integrated quantum circuits.« less

Application of a VLSI vector quantization processor to real-time speech coding

NASA Technical Reports Server (NTRS)

Davidson, G.; Gersho, A.

1986-01-01

Attention is given to a working vector quantization processor for speech coding that is based on a first-generation VLSI chip which efficiently performs the pattern-matching operation needed for the codebook search process (CPS). Using this chip, the CPS architecture has been successfully incorporated into a compact, single-board Vector PCM implementation operating at 7-18 kbits/sec. A real time Adaptive Vector Predictive Coder system using the CPS has also been implemented.

Microcontroller-based real-time QRS detection.

PubMed

Sun, Y; Suppappola, S; Wrublewski, T A

1992-01-01

The authors describe the design of a system for real-time detection of QRS complexes in the electrocardiogram based on a single-chip microcontroller (Motorola 68HC811). A systematic analysis of the instrumentation requirements for QRS detection and of the various design techniques is also given. Detection algorithms using different nonlinear transforms for the enhancement of QRS complexes are evaluated by using the ECG database of the American Heart Association. The results show that the nonlinear transform involving multiplication of three adjacent, sign-consistent differences in the time domain gives a good performance and a quick response. When implemented with an appropriate sampling rate, this algorithm is also capable of rejecting pacemaker spikes. The eight-bit single-chip microcontroller provides sufficient throughput and shows a satisfactory performance. Implementation of multiple detection algorithms in the same system improves flexibility and reliability. The low chip count in the design also favors maintainability and cost-effectiveness.

Hybrid optofluidic biosensors

NASA Astrophysics Data System (ADS)

Parks, Joshua W.

Optofluidics, born of the desire to create a system containing microfluidic environments with integrated optical elements, has seen dramatic increases in popularity over the last 10 years. In particular, the application of this technology towards chip based molecular sensors has undergone significant development. The most sensitive of these biosensors interface liquid- and solid-core antiresonant reflecting optical waveguides (ARROWs). These sensor chips are created using conventional silicon microfabrication. As such, ARROW technology has previously been unable to utilize state-of-the-art microfluidic developments because the technology used--soft polydimethyl siloxane (PDMS) micromolded chips--is unamenable to the silicon microfabrication workflows implemented in the creation of ARROW detection chips. The original goal of this thesis was to employ hybrid integration, or the connection of independently designed and fabricated optofluidic and microfluidic chips, to create enhanced biosensors with the capability of processing and detecting biological samples on a single hybrid system. After successful demonstration of this paradigm, this work expanded into a new direction--direct integration of sensing and detection technologies on a new platform with dynamic, multi-dimensional photonic re-configurability. This thesis reports a number of firsts, including: • 1,000 fold optical transmission enhancement of ARROW optofluidic detection chips through thermal annealing, • Detection of single nucleic acids on a silicon-based ARROW chip, • Hybrid optofluidic integration of ARROW detection chips and passive PDMS microfluidic chips, • Hybrid optofluidic integration of ARROW detection chips and actively controllable PDMS microfluidic chips with integrated microvalves, • On-chip concentration and detection of clinical Ebola nucleic acids, • Multimode interference (MMI) waveguide based wavelength division multiplexing for detection of single influenza virions, • All PDMS platform created from monolithically integrated solid- and liquid-core waveguides with single particle detection efficiency and directly integrated microvalves, featuring: ∘ Tunable/tailorable PDMS MMI waveguides, ∘ Lightvalves (optical switch/fluidic microvalve) with the ability to dynamically control light and fluid flow simultaneously, ∘ Lightvalve trap architecture with the ability to physically trap, detect, and analyze single biomolecules.

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

PubMed Central

Indiveri, Giacomo

2008-01-01

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention. PMID:27873818

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems.

PubMed

Indiveri, Giacomo

2008-09-03

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

PubMed

Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

2017-08-30

Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

PubMed

Yu, Theodore; Cauwenberghs, Gert

2009-01-01

We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

A 1-channel 3-band wide dynamic range compression chip for vibration transducer of implantable hearing aids.

PubMed

Kim, Dongwook; Seong, Kiwoong; Kim, Myoungnam; Cho, Jinho; Lee, Jyunghyun

2014-01-01

In this paper, a digital audio processing chip which uses a wide dynamic range compression (WDRC) algorithm is designed and implemented for implantable hearing aids system. The designed chip operates at a single voltage of 3.3V and drives a 16 bit parallel input and output at 32 kHz sample. The designed chip has 1-channel 3-band WDRC composed of a FIR filter bank, a level detector, and a compression part. To verify the performance of the designed chip, we measured the frequency separations of bands and compression gain control to reflect the hearing threshold level.

Architectures for single-chip image computing

NASA Astrophysics Data System (ADS)

Gove, Robert J.

1992-04-01

This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

Real-time visual target tracking: two implementations of velocity-based smooth pursuit

NASA Astrophysics Data System (ADS)

Etienne-Cummings, Ralph; Longo, Paul; Van der Spiegel, Jan; Mueller, Paul

1995-06-01

Two systems for velocity-based visual target tracking are presented. The first two computational layers of both implementations are composed of VLSI photoreceptors (logarithmic compression) and edge detection (difference-of-Gaussians) arrays that mimic the outer-plexiform layer of mammalian retinas. The subsequent processing layers for measuring the target velocity and to realize smooth pursuit tracking are implemented in software and at the focal plane in the two versions, respectively. One implentation uses a hybrid of a PC and a silicon retina (39 X 38 pixels) operating at 333 frames/second. The software implementation of a real-time optical flow measurement algorithm is used to determine the target velocity, and a closed-loop control system zeroes the relative velocity of the target and retina. The second implementation is a single VLSI chip, which contains a linear array of photoreceptors, edge detectors and motion detectors at the focal plane. The closed-loop control system is also included on chip. This chip realizes all the computational properties of the hybrid system. The effects of background motion, target occlusion, and disappearance are studied as a function of retinal size and spatial distribution of the measured motion vectors (i.e. foveal/peripheral and diverging/converging measurement schemes). The hybrid system, which tested successfully, tracks targets moving as fast as 3 m/s at 1.3 meters from the camera and it can compensate for external arbitrary movements in its mounting platform. The single chip version, whose circuits tested successfully, can handle targets moving at 10 m/s.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

A 16X16 Discrete Cosine Transform Chip

NASA Astrophysics Data System (ADS)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

NASA Technical Reports Server (NTRS)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

FInal Technical Repot of the Project: Design and Implementation of Low-Power 10Gb/s/channel Laser/Silicon Photonics Modulator Drivers with SEU Tolerance for HL-LHC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gui, Ping

During the funding period of this award from May 1, 2014 through March 30, 2016, we have accomplished the design, implementation and measurement results of two laser driver chips: LpGBLD10+ which is a low-power single-channel 10Gb/s laser driver IC, and LDQ10P, which is a 4x10Gb/s driver array chip for High Energy Physics (HEP) applications. With new circuit techniques, the driver consumes a record-low power consumption, 31 mW @10Gb/s/channel and occupies a small area of 400 µm × 1750 µm for the single-channel driver IC and 1900umx1700um for the LDQ10P chip. These characteristics allow for both the LpGBLD10+ ICs and LDQ10P suitable candidatemore » for the Versatile Link PLUS (VL+) project, offering flexibility in configuring multiple Transmitters and receivers.« less

An integrated CMOS high voltage supply for lab-on-a-chip systems.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

2008-09-01

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip.

Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips

NASA Astrophysics Data System (ADS)

Drozd, A.; Szczygiel, R.; Maj, P.; Satlawa, T.; Grybos, P.

2014-12-01

The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.

On-chip III-V monolithic integration of heralded single photon sources and beamsplitters

NASA Astrophysics Data System (ADS)

Belhassen, J.; Baboux, F.; Yao, Q.; Amanti, M.; Favero, I.; Lemaître, A.; Kolthammer, W. S.; Walmsley, I. A.; Ducci, S.

2018-02-01

We demonstrate a monolithic III-V photonic circuit combining a heralded single photon source with a beamsplitter, at room temperature and telecom wavelength. Pulsed parametric down-conversion in an AlGaAs waveguide generates counterpropagating photons, one of which is used to herald the injection of its twin into the beamsplitter. We use this configuration to implement an integrated Hanbury-Brown and Twiss experiment, yielding a heralded second-order correlation gher(2 )(0 )=0.10 ±0.02 that confirms single-photon operation. The demonstrated generation and manipulation of quantum states on a single III-V semiconductor chip opens promising avenues towards real-world applications in quantum information.

Design and Implement of Low Ripple and Quasi-digital Power Supply

NASA Astrophysics Data System (ADS)

Xiangli, Li; Yanjun, Wei; Hanhong, Qi; Yan, Ma

A switch linearity hybrid power supply based on single chip microcomputer is designed which merged the merits of the switching and linear power supply. Main circuit includes pre-regulator which works in switching mode and series regulator which works in linear mode. Two-stage regulation mode was adopted in the main circuit of the power. A single chip computer (SCM) and high resolution of series D/A and A/D converters are applied to control and measurement which achieved continuous adjustable and low ripple constant current or voltage power supply

Sparse matrix-vector multiplication on network-on-chip

NASA Astrophysics Data System (ADS)

Sun, C.-C.; Götze, J.; Jheng, H.-Y.; Ruan, S.-J.

2010-12-01

In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. However, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have already implemented the proposed SMVM-NoC architecture with the size 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.

A hybrid approach to device integration on a genetic analysis platform

NASA Astrophysics Data System (ADS)

Brennan, Des; Jary, Dorothee; Kurg, Ants; Berik, Evgeny; Justice, John; Aherne, Margaret; Macek, Milan; Galvin, Paul

2012-10-01

Point-of-care (POC) systems require significant component integration to implement biochemical protocols associated with molecular diagnostic assays. Hybrid platforms where discrete components are combined in a single platform are a suitable approach to integration, where combining multiple device fabrication steps on a single substrate is not possible due to incompatible or costly fabrication steps. We integrate three devices each with a specific system functionality: (i) a silicon electro-wetting-on-dielectric (EWOD) device to move and mix sample and reagent droplets in an oil phase, (ii) a polymer microfluidic chip containing channels and reservoirs and (iii) an aqueous phase glass microarray for fluorescence microarray hybridization detection. The EWOD device offers the possibility of fully integrating on-chip sample preparation using nanolitre sample and reagent volumes. A key challenge is sample transfer from the oil phase EWOD device to the aqueous phase microarray for hybridization detection. The EWOD device, waveguide performance and functionality are maintained during the integration process. An on-chip biochemical protocol for arrayed primer extension (APEX) was implemented for single nucleotide polymorphism (SNiP) analysis. The prepared sample is aspirated from the EWOD oil phase to the aqueous phase microarray for hybridization. A bench-top instrumentation system was also developed around the integrated platform to drive the EWOD electrodes, implement APEX sample heating and image the microarray after hybridization.

JPIC-Rad-Hard JPEG2000 Image Compression ASIC

NASA Astrophysics Data System (ADS)

Zervas, Nikos; Ginosar, Ran; Broyde, Amitai; Alon, Dov

2010-08-01

JPIC is a rad-hard high-performance image compression ASIC for the aerospace market. JPIC implements tier 1 of the ISO/IEC 15444-1 JPEG2000 (a.k.a. J2K) image compression standard [1] as well as the post compression rate-distortion algorithm, which is part of tier 2 coding. A modular architecture enables employing a single JPIC or multiple coordinated JPIC units. JPIC is designed to support wide data sources of imager in optical, panchromatic and multi-spectral space and airborne sensors. JPIC has been developed as a collaboration of Alma Technologies S.A. (Greece), MBT/IAI Ltd (Israel) and Ramon Chips Ltd (Israel). MBT IAI defined the system architecture requirements and interfaces, The JPEG2K-E IP core from Alma implements the compression algorithm [2]. Ramon Chips adds SERDES interfaces and host interfaces and integrates the ASIC. MBT has demonstrated the full chip on an FPGA board and created system boards employing multiple JPIC units. The ASIC implementation, based on Ramon Chips' 180nm CMOS RadSafe[TM] RH cell library enables superior radiation hardness.

Magnetic domain wall conduits for single cell applications.

PubMed

Donolato, M; Torti, A; Kostesha, N; Deryabina, M; Sogne, E; Vavassori, P; Hansen, M F; Bertacco, R

2011-09-07

The ability to trap, manipulate and release single cells on a surface is important both for fundamental studies of cellular processes and for the development of novel lab-on-chip miniaturized tools for biological and medical applications. In this paper we demonstrate how magnetic domain walls generated in micro- and nano-structures fabricated on a chip surface can be used to handle single yeast cells labeled with magnetic beads. In detail, first we show that the proposed approach maintains the microorganism viable, as proven by monitoring the division of labeled yeast cells trapped by domain walls over 16 hours. Moreover, we demonstrate the controlled transport and release of individual yeast cells via displacement and annihilation of individual domain walls in micro- and nano-sized magnetic structures. These results pave the way to the implementation of magnetic devices based on domain walls technology in lab-on-chip systems devoted to accurate individual cell trapping and manipulation.

FEC decoder design optimization for mobile satellite communications

NASA Technical Reports Server (NTRS)

Roy, Ashim; Lewi, Leng

1990-01-01

A new telecommunications service for location determination via satellite is being proposed for the continental USA and Europe, which provides users with the capability to find the location of, and communicate from, a moving vehicle to a central hub and vice versa. This communications system is expected to operate in an extremely noisy channel in the presence of fading. In order to achieve high levels of data integrity, it is essential to employ forward error correcting (FEC) encoding and decoding techniques in such mobile satellite systems. A constraint length k = 7 FEC decoder has been implemented in a single chip for such systems. The single chip implementation of the maximum likelihood decoder helps to minimize the cost, size, and power consumption, and improves the bit error rate (BER) performance of the mobile earth terminal (MET).

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.

PubMed

Chen, Zhiyuan; Law, Man-Kay; Mak, Pui-In; Martins, Rui P

2017-02-01

In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 × efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 V in gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- [Formula: see text] CMOS technology and occupies an active area of 1.54 [Formula: see text]. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 [Formula: see text] from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 [Formula: see text] at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.

Sub-micro-liter Electrochemical Single-Nucleotide-Polymorphism Detector for Lab-on-a-Chip System

NASA Astrophysics Data System (ADS)

Tanaka, Hiroyuki; Fiorini, Paolo; Peeters, Sara; Majeed, Bivragh; Sterken, Tom; de Beeck, Maaike Op; Hayashi, Miho; Yaku, Hidenobu; Yamashita, Ichiro

2012-04-01

A sub-micro-liter single-nucleotide-polymorphism (SNP) detector for lab-on-a-chip applications is developed. This detector enables a fast, sensitive, and selective SNP detection directly from human blood. The detector is fabricated on a Si substrate by a standard complementary metal oxide semiconductor/micro electro mechanical systems (CMOS/MEMS) process and Polydimethylsiloxane (PDMS) molding. Stable and reproducible measurements are obtained by implementing an on-chip Ag/AgCl electrode and encapsulating the detector. The detector senses the presence of SNPs by measuring the concentration of pyrophosphoric acid generated during selective DNA amplification. A 0.5-µL-volume detector enabled the successful performance of the typing of a SNP within the ABO gene using human blood. The measured sensitivity is 566 pA/µM.

Programmable lab-on-a-chip system for single cell analysis

NASA Astrophysics Data System (ADS)

Thalhammer, S.

2009-05-01

The collection, selection, amplification and detection of minimum genetic samples became a part of everyday life in medical and biological laboratories, to analyze DNA-fragments of pathogens, patient samples and traces on crime scenes. About a decade ago, a handful of researchers began discussing an intriguing idea. Could the equipment needed for everyday chemistry and biology procedures be shrunk to fit on a chip in the size of a fingernail? Miniature devices for, say, analysing DNA and proteins should be faster and cheaper than conventional versions. Lab-on-a-chip is an advanced technology that integrates a microfluidic system on a microscale chip device. The "laboratory" is created by means of channels, mixers, reservoirs, diffusion chambers, integrated electrodes, pumps, valves and more. With lab-ona- chip technology, complete laboratories on a square centimetre can be created. Here, a multifunctional programmable Lab-on-a-Chip driven by nanofluidics and controlled by surface acoustic waves (SAW) is presented. This system combines serial DNA-isolation-, amplification- and array-detection-process on a modified glass-platform. The fluid actuation is controlled via SAW by interdigital transducers implemented in the chemical modified chip surface. The chemical surface modification allows fluid handling in the sub-microliter range. Minute amount of sample material is extracted by laser-based microdissection out of e.g. histological sections at the single cell level. A few picogram of genetic material are isolated and transferred via a low-pressure transfer system (SPATS) onto the chip. Subsequently the genetic material inside single droplets, which behave like "virtual" beaker, is transported to the reaction and analysis centers on the chip surface via surface acoustic waves, mainly known as noise dumping filters in mobile phones. At these "biological reactors" the genetic material is processed, e.g. amplified via polymerase chain reaction methods, and genetically characterized.

VASP-4096: a very high performance programmable device for digital media processing applications

NASA Astrophysics Data System (ADS)

Krikelis, Argy

2001-03-01

Over the past few years, technology drivers for microprocessors have changed significantly. Media data delivery and processing--such as telecommunications, networking, video processing, speech recognition and 3D graphics--is increasing in importance and will soon dominate the processing cycles consumed in computer-based systems. This paper presents the architecture of the VASP-4096 processor. VASP-4096 provides high media performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the VASP-4096 is the integration of thousands of processing units in a single chip that are capable of support software programmable high-performance mathematical functions as well as abstract data processing. In addition to 4096 processing units, VASP-4096 integrates on a single chip a RISC controller that is an implementation of the SPARC architecture, 128 Kbytes of Data Memory, and I/O interfaces. The SIMD processing in VASP-4096 implements the ASProCore architecture, which is a proprietary implementation of SIMD processing, operates at 266 MHz with program instructions issued by the RISC controller. The device also integrates a 64-bit synchronous main memory interface operating at 133 MHz (double-data rate), and a 64- bit 66 MHz PCI interface. VASP-4096, compared with other processors architectures that support media processing, offers true performance scalability, support for deterministic and non-deterministic data processing on a single device, and software programmability that can be re- used in future chip generations.

1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner.

PubMed

Seo, Yeong-Hyeon; Hwang, Kyungmin; Jeong, Ki-Hun

2018-02-19

We report a 1.65 mm diameter forward-viewing confocal endomicroscopic catheter using a flip-chip bonded electrothermal MEMS fiber scanner. Lissajous scanning was implemented by the electrothermal MEMS fiber scanner. The Lissajous scanned MEMS fiber scanner was precisely fabricated to facilitate flip-chip connection, and bonded with a printed circuit board. The scanner was successfully combined with a fiber-based confocal imaging system. A two-dimensional reflectance image of the metal pattern 'OPTICS' was successfully obtained with the scanner. The flip-chip bonded scanner minimizes electrical packaging dimensions. The inner diameter of the flip-chip bonded MEMS fiber scanner is 1.3 mm. The flip-chip bonded MEMS fiber scanner is fully packaged with a 1.65 mm diameter housing tube, 1 mm diameter GRIN lens, and a single mode optical fiber. The packaged confocal endomicroscopic catheter can provide a new breakthrough for diverse in-vivo endomicroscopic applications.

The design of an adaptive predictive coder using a single-chip digital signal processor

NASA Astrophysics Data System (ADS)

Randolph, M. A.

1985-01-01

A speech coding processor architecture design study has been performed in which Texas Instruments TMS32010 has been selected from among three commercially available digital signal processing integrated circuits and evaluated in an implementation study of real-time Adaptive Predictive Coding (APC). The TMS32010 has been compared with AR&T Bell Laboratories DSP I and Nippon Electric Co. PD7720 and was found to be most suitable for a single chip implementation of APC. A preliminary design system based on TMS32010 has been performed, and several of the hardware and software design issues are discussed. Particular attention was paid to the design of an external memory controller which permits rapid sequential access of external RAM. As a result, it has been determined that a compact hardware implementation of the APC algorithm is feasible based of the TSM32010. Originator-supplied keywords include: vocoders, speech compression, adaptive predictive coding, digital signal processing microcomputers, speech processor architectures, and special purpose processor.

Versatile single-chip event sequencer for atomic physics experiments

NASA Astrophysics Data System (ADS)

Eyler, Edward

2010-03-01

A very inexpensive dsPIC microcontroller with internal 32-bit counters is used to produce a flexible timing signal generator with up to 16 TTL-compatible digital outputs, with a time resolution and accuracy of 50 ns. This time resolution is easily sufficient for event sequencing in typical experiments involving cold atoms or laser spectroscopy. This single-chip device is capable of triggered operation and can also function as a sweeping delay generator. With one additional chip it can also concurrently produce accurately timed analog ramps, and another one-chip addition allows real-time control from an external computer. Compared to an FPGA-based digital pattern generator, this design is slower but simpler and more flexible, and it can be reprogrammed using ordinary `C' code without special knowledge. I will also describe the use of the same microcontroller with additional hardware to implement a digital lock-in amplifier and PID controller for laser locking, including a simple graphics-based control unit. This work is supported in part by the NSF.

Indistinguishable and efficient single photons from a quantum dot in a planar nanobeam waveguide

NASA Astrophysics Data System (ADS)

KiršanskÄ--, Gabija; Thyrrestrup, Henri; Daveau, Raphaël S.; Dreeßen, Chris L.; Pregnolato, Tommaso; Midolo, Leonardo; Tighineanu, Petru; Javadi, Alisa; Stobbe, Søren; Schott, Rüdiger; Ludwig, Arne; Wieck, Andreas D.; Park, Suk In; Song, Jin D.; Kuhlmann, Andreas V.; Söllner, Immo; Löbl, Matthias C.; Warburton, Richard J.; Lodahl, Peter

2017-10-01

We demonstrate a high-purity source of indistinguishable single photons using a quantum dot embedded in a nanophotonic waveguide. The source features a near-unity internal coupling efficiency and the collected photons are efficiently coupled off chip by implementing a taper that adiabatically couples the photons to an optical fiber. By quasiresonant excitation of the quantum dot, we measure a single-photon purity larger than 99.4 % and a photon indistinguishability of up to 94 ±1 % by using p -shell excitation combined with spectral filtering to reduce photon jitter. A temperature-dependent study allows pinpointing the residual decoherence processes, notably the effect of phonon broadening. Strict resonant excitation is implemented as well as another means of suppressing photon jitter, and the additional complexity of suppressing the excitation laser source is addressed. The paper opens a clear pathway towards the long-standing goal of a fully deterministic source of indistinguishable photons, which is integrated on a planar photonic chip.

Fault-tolerant computer study. [logic designs for building block circuits

NASA Technical Reports Server (NTRS)

Rennels, D. A.; Avizienis, A. A.; Ercegovac, M. D.

1981-01-01

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.

Mechanical design optimization of a single-axis MOEMS accelerometer based on a grating interferometry cavity for ultrahigh sensitivity

NASA Astrophysics Data System (ADS)

Lu, Qianbo; Bai, Jian; Wang, Kaiwei; Lou, Shuqi; Jiao, Xufen; Han, Dandan; Yang, Guoguang

2016-08-01

The ultrahigh static displacement-acceleration sensitivity of a mechanical sensing chip is essential primarily for an ultrasensitive accelerometer. In this paper, an optimal design to implement to a single-axis MOEMS accelerometer consisting of a grating interferometry cavity and a micromachined sensing chip is presented. The micromachined sensing chip is composed of a proof mass along with its mechanical cantilever suspension and substrate. The dimensional parameters of the sensing chip, including the length, width, thickness and position of the cantilevers are evaluated and optimized both analytically and by finite-element-method (FEM) simulation to yield an unprecedented acceleration-displacement sensitivity. Compared with one of the most sensitive single-axis MOEMS accelerometers reported in the literature, the optimal mechanical design can yield a profound sensitivity improvement with an equal footprint area, specifically, 200% improvement in displacement-acceleration sensitivity with moderate resonant frequency and dynamic range. The modified design was microfabricated, packaged with the grating interferometry cavity and tested. The experimental results demonstrate that the MOEMS accelerometer with modified design can achieve the acceleration-displacement sensitivity of about 150μm/g and acceleration sensitivity of greater than 1500V/g, which validates the effectiveness of the optimal design.

A Reconfigurable Design and Architecture of the Ethernet and HomePNA3.0 MAC

NASA Astrophysics Data System (ADS)

Khalilydermany, M.; Hosseinghadiry, M.

In this paper a reconfigurable architecture for Ethernet and HomePNA MAC is presented. By using this new architecture, Ethernet and HomePNA reconfigurable network card can be produced. This architecture has been implemented using VHDL language and after that synthesized on a chip. The differences between HomePNA (synchronized and unsynchronized mode) and Ethernet in collision detection mechanism and priority access to media have caused the need to separate architectures for Ethernet and HomePNA, but by using similarities of them, both the Ethernet and the HomePNA can be implemented in a single chip with a little extra hardware. The number of logical elements of the proposed architecture is increased by 19% in compare to when only an Ethernet MAC is implemented

Silicon-on-insulator sensors using integrated resonance-enhanced defect-mediated photodetectors.

PubMed

Fard, Sahba Talebi; Murray, Kyle; Caverley, Michael; Donzella, Valentina; Flueckiger, Jonas; Grist, Samantha M; Huante-Ceron, Edgar; Schmidt, Shon A; Kwok, Ezra; Jaeger, Nicolas A F; Knights, Andrew P; Chrostowski, Lukas

2014-11-17

A resonance-enhanced, defect-mediated, ring resonator photodetector has been implemented as a single unit biosensor on a silicon-on-insulator platform, providing a cost effective means of integrating ring resonator sensors with photodetectors for lab-on-chip applications. This method overcomes the challenge of integrating hybrid photodetectors on the chip. The demonstrated responsivity of the photodetector-sensor was 90 mA/W. Devices were characterized using refractive index modified solutions and showed sensitivities of 30 nm/RIU.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Bottom-up construction of artificial molecules for superconducting quantum processors

NASA Astrophysics Data System (ADS)

Poletto, Stefano; Rigetti, Chad; Gambetta, Jay M.; Merkel, Seth; Chow, Jerry M.; Corcoles, Antonio D.; Smolin, John A.; Rozen, Jim R.; Keefe, George A.; Rothwell, Mary B.; Ketchen, Mark B.; Steffen, Matthias

2012-02-01

Recent experiments on transmon qubits capacitively coupled to superconducting 3-dimensional cavities have shown coherence times much longer than transmons coupled to more traditional planar resonators. For the implementation of a quantum processor this approach has clear advantages over traditional techniques but it poses the challenge of scalability. We are currently implementing multi-qubits experiments based on a bottom-up scaling approach. First, transmon qubits are fabricated on individual chips and are independently characterized. Second, an artificial molecule is assembled by selecting a particular set of previously characterized single-transmon chips. We present recent data on a two-qubit artificial molecule constructed in this way. The two qubits are chosen to generate a strong Z-Z interaction by matching the 0-1 transition energy of one qubit with the 1-2 transition of the other. Single qubit manipulations and state tomography cannot be done with ``traditional'' single tone microwave pulses but instead specifically shaped pulses have to be simultaneously applied on both qubits. Coherence times, coupling strength, and optimal pulses for decoupling the two qubits and perform state tomography are presented

A polymeric micro total analysis system for single-cell analysis

NASA Astrophysics Data System (ADS)

Lai, Hsuan-Hong

The advancement of microengineering has enabled the manipulation and analysis of single cells, which is critical in understanding the molecular mechanisms underlying the basic physiological functions from the point of view of modern biologists. Unfortunately, analysis of single cells remains challenging from a technical perspective, mainly because of the miniature nature of the cell and the high throughput requirements of the analysis. Lab-on-a-chip (LOC) emerges as a research field that shows great promise in this perspective. We have demonstrated a micro total analysis system (mu-TAS) combining chip-based electrophoretic separation, fluorescence detection, and a pulsed Nd:YAG laser cell lysis system, in a Poly(dimethylsiloxane) (PDMS) microfluidic analytical platform for the implementation of single-cell analysis. To accomplish the task, a polymeric microfluidic device was fabricated and UV graft polymerization surface modification techniques were used. To optimize the conditions for the surface treatment techniques, the modified surfaces of PDMS were characterized using AIR-IR spectrum and sessile water drop contact angle measurements, and in-channel surfaces were characterized by their electroosmotic flow mobility. Accurate single-cell analysis relies on rapid cell lysis and therefore an optical measure of fast cell lysis was implemented and optimized in a microscopic station. The influences of pulse energy and the location of the laser beam with respect to the cell in the microchannel were explored. The observation from the cell disruption experiments suggested that the cell lysis was enabled mainly via a thermo-mechanical instead of a plasma-mediated mechanism. Finally, after chip-based electrophoresis and a laser-induced fluorescence (LIF) detection system were incorporated with the laser lysis system in a microfluidic analytical station, a feasibility demonstration of single-cell analysis was implemented. The analytical platform exhibited the capability of fluidic transportation, optical lysis of single cells, separation, and analysis of the lysates by electrophoresis and LIF detection. In comparison with the control experiment, the migration times of the fluorescent signals for the cytosolic fluorophores were in good agreement with those for the standard fluorophores, which confirmed the feasibility of the analytical processes.

Machine learning on-a-chip: a high-performance low-power reusable neuron architecture for artificial neural networks in ECG classifications.

PubMed

Sun, Yuwen; Cheng, Allen C

2012-07-01

Artificial neural networks (ANNs) are a promising machine learning technique in classifying non-linear electrocardiogram (ECG) signals and recognizing abnormal patterns suggesting risks of cardiovascular diseases (CVDs). In this paper, we propose a new reusable neuron architecture (RNA) enabling a performance-efficient and cost-effective silicon implementation for ANN. The RNA architecture consists of a single layer of physical RNA neurons, each of which is designed to use minimal hardware resource (e.g., a single 2-input multiplier-accumulator is used to compute the dot product of two vectors). By carefully applying the principal of time sharing, RNA can multiplexs this single layer of physical neurons to efficiently execute both feed-forward and back-propagation computations of an ANN while conserving the area and reducing the power dissipation of the silicon. A three-layer 51-30-12 ANN is implemented in RNA to perform the ECG classification for CVD detection. This RNA hardware also allows on-chip automatic training update. A quantitative design space exploration in area, power dissipation, and execution speed between RNA and three other implementations representative of different reusable hardware strategies is presented and discussed. Compared with an equivalent software implementation in C executed on an embedded microprocessor, the RNA ASIC achieves three orders of magnitude improvements in both the execution speed and the energy efficiency. Copyright © 2012 Elsevier Ltd. All rights reserved.

Optofluidic wavelength division multiplexing for single-virus detection

PubMed Central

Ozcelik, Damla; Parks, Joshua W.; Wall, Thomas A.; Stott, Matthew A.; Cai, Hong; Parks, Joseph W.; Hawkins, Aaron R.; Schmidt, Holger

2015-01-01

Optical waveguides simultaneously transport light at different colors, forming the basis of fiber-optic telecommunication networks that shuttle data in dozens of spectrally separated channels. Here, we reimagine this wavelength division multiplexing (WDM) paradigm in a novel context––the differentiated detection and identification of single influenza viruses on a chip. We use a single multimode interference (MMI) waveguide to create wavelength-dependent spot patterns across the entire visible spectrum and enable multiplexed single biomolecule detection on an optofluidic chip. Each target is identified by its time-dependent fluorescence signal without the need for spectral demultiplexing upon detection. We demonstrate detection of individual fluorescently labeled virus particles of three influenza A subtypes in two implementations: labeling of each virus using three different colors and two-color combinatorial labeling. By extending combinatorial multiplexing to three or more colors, MMI-based WDM provides the multiplexing power required for differentiated clinical tests and the growing field of personalized medicine. PMID:26438840

Single chip camera active pixel sensor

NASA Technical Reports Server (NTRS)

Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

2003-01-01

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Modal and polarization qubits in Ti:LiNbO3 photonic circuits for a universal quantum logic gate.

PubMed

Saleh, Mohammed F; Di Giuseppe, Giovanni; Saleh, Bahaa E A; Teich, Malvin Carl

2010-09-13

Lithium niobate photonic circuits have the salutary property of permitting the generation, transmission, and processing of photons to be accommodated on a single chip. Compact photonic circuits such as these, with multiple components integrated on a single chip, are crucial for efficiently implementing quantum information processing schemes.We present a set of basic transformations that are useful for manipulating modal qubits in Ti:LiNbO(3) photonic quantum circuits. These include the mode analyzer, a device that separates the even and odd components of a state into two separate spatial paths; the mode rotator, which rotates the state by an angle in mode space; and modal Pauli spin operators that effect related operations. We also describe the design of a deterministic, two-qubit, single-photon, CNOT gate, a key element in certain sets of universal quantum logic gates. It is implemented as a Ti:LiNbO(3) photonic quantum circuit in which the polarization and mode number of a single photon serve as the control and target qubits, respectively. It is shown that the effects of dispersion in the CNOT circuit can be mitigated by augmenting it with an additional path. The performance of all of these components are confirmed by numerical simulations. The implementation of these transformations relies on selective and controllable power coupling among single- and two-mode waveguides, as well as the polarization sensitivity of the Pockels coefficients in LiNbO(3).

Single-bead arrays for fluorescence-based immunoassays on capillary-driven microfluidic chips

NASA Astrophysics Data System (ADS)

Temiz, Yuksel; Lim, Michel; Delamarche, Emmanuel

2016-03-01

We report a concept for the simple fabrication of easy-to-use chips for immunoassays in the context of point-of-care diagnostics. The chip concept comprises mainly three features: (1) the efficient integration of reagents using beads functionalized with receptors, (2) the generation of capillary-driven liquid flows without using external pumps, and (3) a high-sensitivity detection of analytes using fluorescence microscopy. We fabricated prototype chips using dry etching of Si wafers. 4.5-μm-diameter beads were integrated into hexagonal arrays by sedimentation and removing the excess using a stream of water. We studied the effect of different parameters and showed that array occupancies from 30% to 50% can be achieved by pipetting a 250 nL droplet of 1% bead solution and allowing the beads sediment for 3 min. Chips with integrated beads were sealed using a 50-μm-thick dry-film resist laminated at 45 °C. Liquids pipetted to loading pads were autonomously pulled by capillary pumps at a rate of 0.35 nL s-1 for about 30 min. We studied ligand-receptor interactions and binding kinetics using time-lapse fluorescence microscopy and demonstrated a 5 pM limit of detection (LOD) for an anti-biotin immunoassay. As a clinically-relevant example, we implemented an immunoassay to detect prostate specific antigen (PSA) and showed an LOD of 108 fM (i.e. 3.6 pg mL-1). While a specific implementation is provided here for the detection of PSA, we believe that combining capillary-driven microfluidics with arrays of single beads and fluorescence readout to be very flexible and sufficiently sensitive for the detection of other clinically-relevant analytes.

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

NASA Technical Reports Server (NTRS)

Truong, T. K.; Hsu, I. S.; Chang, J. J.; Shyu, H. C.; Reed, I. S.

1986-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

NASA Technical Reports Server (NTRS)

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems

PubMed Central

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G.; Blaauw, David; Dutta, Prabal

2015-01-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized—yet reusable—components with an interconnect that permits tiny, ultra-low power systems. In contrast to today’s interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two “shoot-through” rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient’s power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus’s feature set. PMID:26855555

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

PubMed

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G; Blaauw, David; Dutta, Prabal

2015-06-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus , a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm 3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

Adaptive WTA with an analog VLSI neuromorphic learning chip.

PubMed

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

NASA Astrophysics Data System (ADS)

Hamada, Tsuyoshi; Fukushige, Toshiyuki; Kawai, Atsushi; Makino, Junichiro

2000-10-01

We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and ``traditional'' GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydro\\-dynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

NASA Astrophysics Data System (ADS)

Wu, Chang-Hsi; You, Hong-Cheng; Huang, Shun-Zhao

2018-02-01

An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of -9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

First results of the front-end ASIC for the strip detector of the PANDA MVD

NASA Astrophysics Data System (ADS)

Quagli, T.; Brinkmann, K.-T.; Calvo, D.; Di Pietro, V.; Lai, A.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Wheadon, R.; Zambanini, A.

2017-03-01

PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

Optofluidic analysis system for amplification-free, direct detection of Ebola infection

NASA Astrophysics Data System (ADS)

Cai, H.; Parks, J. W.; Wall, T. A.; Stott, M. A.; Stambaugh, A.; Alfson, K.; Griffiths, A.; Mathies, R. A.; Carrion, R.; Patterson, J. L.; Hawkins, A. R.; Schmidt, H.

2015-09-01

The massive outbreak of highly lethal Ebola hemorrhagic fever in West Africa illustrates the urgent need for diagnostic instruments that can identify and quantify infections rapidly, accurately, and with low complexity. Here, we report on-chip sample preparation, amplification-free detection and quantification of Ebola virus on clinical samples using hybrid optofluidic integration. Sample preparation and target preconcentration are implemented on a PDMS-based microfluidic chip (automaton), followed by single nucleic acid fluorescence detection in liquid-core optical waveguides on a silicon chip in under ten minutes. We demonstrate excellent specificity, a limit of detection of 0.2 pfu/mL and a dynamic range of thirteen orders of magnitude, far outperforming other amplification-free methods. This chip-scale approach and reduced complexity compared to gold standard RT-PCR methods is ideal for portable instruments that can provide immediate diagnosis and continued monitoring of infectious diseases at the point-of-care.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

SVM classifier on chip for melanoma detection.

PubMed

Afifi, Shereen; GholamHosseini, Hamid; Sinha, Roopak

2017-07-01

Support Vector Machine (SVM) is a common classifier used for efficient classification with high accuracy. SVM shows high accuracy for classifying melanoma (skin cancer) clinical images within computer-aided diagnosis systems used by skin cancer specialists to detect melanoma early and save lives. We aim to develop a medical low-cost handheld device that runs a real-time embedded SVM-based diagnosis system for use in primary care for early detection of melanoma. In this paper, an optimized SVM classifier is implemented onto a recent FPGA platform using the latest design methodology to be embedded into the proposed device for realizing online efficient melanoma detection on a single system on chip/device. The hardware implementation results demonstrate a high classification accuracy of 97.9% and a significant acceleration factor of 26 from equivalent software implementation on an embedded processor, with 34% of resources utilization and 2 watts for power consumption. Consequently, the implemented system meets crucial embedded systems constraints of high performance and low cost, resources utilization and power consumption, while achieving high classification accuracy.

Single cell digital polymerase chain reaction on self-priming compartmentalization chip

PubMed Central

Zhu, Qiangyuan; Qiu, Lin; Xu, Yanan; Li, Guang; Mu, Ying

2017-01-01

Single cell analysis provides a new framework for understanding biology and disease, however, an absolute quantification of single cell gene expression still faces many challenges. Microfluidic digital polymerase chain reaction (PCR) provides a unique method to absolutely quantify the single cell gene expression, but only limited devices are developed to analyze a single cell with detection variation. This paper describes a self-priming compartmentalization (SPC) microfluidic digital polymerase chain reaction chip being capable of performing single molecule amplification from single cell. The chip can be used to detect four single cells simultaneously with 85% of sample digitization. With the optimized protocol for the SPC chip, we first tested the ability, precision, and sensitivity of our SPC digital PCR chip by assessing β-actin DNA gene expression in 1, 10, 100, and 1000 cells. And the reproducibility of the SPC chip is evaluated by testing 18S rRNA of single cells with 1.6%–4.6% of coefficient of variation. At last, by detecting the lung cancer related genes, PLAU gene expression of A549 cells at the single cell level, the single cell heterogeneity was demonstrated. So, with the power-free, valve-free SPC chip, the gene copy number of single cells can be quantified absolutely with higher sensitivity, reduced labor time, and reagent. We expect that this chip will enable new studies for biology and disease. PMID:28191267

Single cell digital polymerase chain reaction on self-priming compartmentalization chip.

PubMed

Zhu, Qiangyuan; Qiu, Lin; Xu, Yanan; Li, Guang; Mu, Ying

2017-01-01

Single cell analysis provides a new framework for understanding biology and disease, however, an absolute quantification of single cell gene expression still faces many challenges. Microfluidic digital polymerase chain reaction (PCR) provides a unique method to absolutely quantify the single cell gene expression, but only limited devices are developed to analyze a single cell with detection variation. This paper describes a self-priming compartmentalization (SPC) microfluidic digital polymerase chain reaction chip being capable of performing single molecule amplification from single cell. The chip can be used to detect four single cells simultaneously with 85% of sample digitization. With the optimized protocol for the SPC chip, we first tested the ability, precision, and sensitivity of our SPC digital PCR chip by assessing β-actin DNA gene expression in 1, 10, 100, and 1000 cells. And the reproducibility of the SPC chip is evaluated by testing 18S rRNA of single cells with 1.6%-4.6% of coefficient of variation. At last, by detecting the lung cancer related genes, PLAU gene expression of A549 cells at the single cell level, the single cell heterogeneity was demonstrated. So, with the power-free, valve-free SPC chip, the gene copy number of single cells can be quantified absolutely with higher sensitivity, reduced labor time, and reagent. We expect that this chip will enable new studies for biology and disease.

Separation and Analysis of Adherent and Non-Adherent Cancer Cells Using a Single-Cell Microarray Chip.

PubMed

Yamamura, Shohei; Yamada, Eriko; Kimura, Fukiko; Miyajima, Kumiko; Shigeto, Hajime

2017-10-21

A new single-cell microarray chip was designed and developed to separate and analyze single adherent and non-adherent cancer cells. The single-cell microarray chip is made of polystyrene with over 60,000 microchambers of 10 different size patterns (31-40 µm upper diameter, 11-20 µm lower diameter). A drop of suspension of adherent carcinoma (NCI-H1650) and non-adherent leukocyte (CCRF-CEM) cells was placed onto the chip, and single-cell occupancy of NCI-H1650 and CCRF-CEM was determined to be 79% and 84%, respectively. This was achieved by controlling the chip design and surface treatment. Analysis of protein expression in single NCI-H1650 and CCRF-CEM cells was performed on the single-cell microarray chip by multi-antibody staining. Additionally, with this system, we retrieved positive single cells from the microchambers by a micromanipulator. Thus, this system demonstrates the potential for easy and accurate separation and analysis of various types of single cells.

Optofluidic waveguides: I. Concepts and implementations

PubMed Central

Schmidt, Holger; Hawkins, Aaron R.

2011-01-01

We review recent developments and current status of liquid-core optical waveguides in optofluidics with emphasis on suitability for creating fully planar optofluidic labs-on-a-chip. In this first of two contributions, we give an overview of the different waveguide types that are being considered for effectively combining micro and nanofluidics with integrated optics. The large number of approaches is separated into conventional index-guided waveguides and more recent implementations using wave interference. The underlying principle for waveguiding and the current status are described for each type. We then focus on reviewing recent work on microfabricated liquid-core antiresonant reflecting optical (ARROW) waveguides, including the development of intersecting 2D waveguide networks and optical fluorescence and Raman detection with planar beam geometry. Single molecule detection capability and addition of electrical control for electrokinetic manipulation and analysis of single bioparticles are demonstrated. The demonstrated performance of liquid-core ARROWs is representative of the potential of integrated waveguides for on-chip detection with ultrahigh sensitivity, and points the way towards the next generation of high-performance, low-cost and portable biomedical instruments. PMID:21442048

Partition resampling and extrapolation averaging: approximation methods for quantifying gene expression in large numbers of short oligonucleotide arrays.

PubMed

Goldstein, Darlene R

2006-10-01

Studies of gene expression using high-density short oligonucleotide arrays have become a standard in a variety of biological contexts. Of the expression measures that have been proposed to quantify expression in these arrays, multi-chip-based measures have been shown to perform well. As gene expression studies increase in size, however, utilizing multi-chip expression measures is more challenging in terms of computing memory requirements and time. A strategic alternative to exact multi-chip quantification on a full large chip set is to approximate expression values based on subsets of chips. This paper introduces an extrapolation method, Extrapolation Averaging (EA), and a resampling method, Partition Resampling (PR), to approximate expression in large studies. An examination of properties indicates that subset-based methods can perform well compared with exact expression quantification. The focus is on short oligonucleotide chips, but the same ideas apply equally well to any array type for which expression is quantified using an entire set of arrays, rather than for only a single array at a time. Software implementing Partition Resampling and Extrapolation Averaging is under development as an R package for the BioConductor project.

Multifunctional System-on-Glass for Lab-on-Chip applications.

PubMed

Petrucci, G; Caputo, D; Lovecchio, N; Costantini, F; Legnini, I; Bozzoni, I; Nascetti, A; de Cesare, G

2017-07-15

Lab-on-Chip are miniaturized systems able to perform biomolecular analysis in shorter time and with lower reagent consumption than a standard laboratory. Their miniaturization interferes with the multiple functions that the biochemical procedures require. In order to address this issue, our paper presents, for the first time, the integration on a single glass substrate of different thin film technologies in order to develop a multifunctional platform suitable for on-chip thermal treatments and on-chip detection of biomolecules. The proposed System on-Glass hosts thin metal films acting as heating sources; hydrogenated amorphous silicon diodes acting both as temperature sensors to monitor the temperature distribution and photosensors for the on-chip detection and a ground plane ensuring that the heater operation does not affect the photodiode currents. The sequence of the technological steps, the deposition temperatures of the thin films and the parameters of the photolithographic processes have been optimized in order to overcome all the issues of the technological integration. The device has been designed, fabricated and tested for the implementation of DNA amplification through the Polymerase Chain Reaction (PCR) with thermal cycling among three different temperatures on a single site. The glass has been connected to an electronic system that drives the heaters and controls the temperature and light sensors. It has been optically and thermally coupled with another glass hosting a microfluidic network made in polydimethylsiloxane that includes thermally actuated microvalves and a PCR process chamber. The successful DNA amplification has been verified off-chip by using a standard fluorometer. Copyright © 2016 Elsevier B.V. All rights reserved.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Precision Voltage Referencing Techniques in MOS Technology.

NASA Astrophysics Data System (ADS)

Song, Bang-Sup

With the increasing complexity of functions on a single MOS chip, precision analog cicuits implemented in the same technology are in great demand so as to be integrated together with digital circuits. The future development of MOS data acquisition systems will require precision on-chip MOS voltage references. This dissertation will probe two most promising configurations of on-chip voltage references both in NMOS and CMOS technologies. In NMOS, an ion-implantation effect on the temperature behavior of MOS devices is investigated to identify the fundamental limiting factors of a threshold voltage difference as an NMOS voltage source. For this kind of voltage reference, the temperature stability on the order of 20ppm/(DEGREES)C is achievable with a shallow single-threshold implant and a low-current, high-body bias operation. In CMOS, a monolithic prototype bandgap reference is designed, fabricated and tested which embodies a curvature compensation and exhibits a minimized sensitivity to the process parameter variation. Experimental results imply that an average temperature stability on the order of 10ppm/(DEGREES)C with a production spread of less than 10ppm/(DEGREES)C feasible over the commercial temperature range.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Design of an intelligent car

NASA Astrophysics Data System (ADS)

Na, Yongyi

2017-03-01

The design of simple intelligent car, using AT89S52 single chip microcomputer as the car detection and control core; The metal sensor TL - Q5MC induction to iron, to detect the way to send feedback to the signal of single chip microcomputer, make SCM according to the scheduled work mode to control the car in the area according to the predetermined speed, and the operation mode of the microcontroller choose different also can control the car driving along s-shaped iron; Use A44E hall element to detect the car speeds; Adopts 1602 LCD display time of car driving, driving the car to stop, take turns to show the car driving time, distance, average speed and the speed of time. This design has simple structure and is easy to implement, but are highly intelligent, humane, to a certain extent reflects the intelligence.

3D printed high density, reversible, chip-to-chip microfluidic interconnects.

PubMed

Gong, Hua; Woolley, Adam T; Nordin, Gregory P

2018-02-13

Our latest developments in miniaturizing 3D printed microfluidics [Gong et al., Lab Chip, 2016, 16, 2450; Gong et al., Lab Chip, 2017, 17, 2899] offer the opportunity to fabricate highly integrated chips that measure only a few mm on a side. For such small chips, an interconnection method is needed to provide the necessary world-to-chip reagent and pneumatic connections. In this paper, we introduce simple integrated microgaskets (SIMs) and controlled-compression integrated microgaskets (CCIMs) to connect a small device chip to a larger interface chip that implements world-to-chip connections. SIMs or CCIMs are directly 3D printed as part of the device chip, and therefore no additional materials or components are required to make the connection to the larger 3D printed interface chip. We demonstrate 121 chip-to-chip interconnections in an 11 × 11 array for both SIMs and CCIMs with an areal density of 53 interconnections per mm 2 and show that they withstand fluid pressures of 50 psi. We further demonstrate their reusability by testing the devices 100 times without seal failure. Scaling experiments show that 20 × 20 interconnection arrays are feasible and that the CCIM areal density can be increased to 88 interconnections per mm 2 . We then show the utility of spatially distributed discrete CCIMs by using an interconnection chip with 28 chip-to-world interconnects to test 45 3D printed valves in a 9 × 5 array. Each valve is only 300 μm in diameter (the smallest yet reported for 3D printed valves). Every row of 5 valves is tested to at least 10 000 actuations, with one row tested to 1 000 000 actuations. In all cases, there is no sign of valve failure, and the CCIM interconnections prove an effective means of using a single interface chip to test a series of valve array chips.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Asynchronous transfer mode distribution network by use of an optoelectronic VLSI switching chip.

PubMed

Lentine, A L; Reiley, D J; Novotny, R A; Morrison, R L; Sasian, J M; Beckman, M G; Buchholz, D B; Hinterlong, S J; Cloonan, T J; Richards, G W; McCormick, F B

1997-03-10

We describe a new optoelectronic switching system demonstration that implements part of the distribution fabric for a large asynchronous transfer mode (ATM) switch. The system uses a single optoelectronic VLSI modulator-based switching chip with more than 4000 optical input-outputs. The optical system images the input fibers from a two-dimensional fiber bundle onto this chip. A new optomechanical design allows the system to be mounted in a standard electronic equipment frame. A large section of the switch was operated as a 208-Mbits/s time-multiplexed space switch, which can serve as part of an ATM switch by use of an appropriate out-of-band controller. A larger section with 896 input light beams and 256 output beams was operated at 160 Mbits/s as a slowly reconfigurable space switch.

A low-power, high-throughput maximum-likelihood convolutional decoder chip for NASA's 30/20 GHz program

NASA Technical Reports Server (NTRS)

Mccallister, R. D.; Crawford, J. J.

1981-01-01

It is pointed out that the NASA 30/20 GHz program will place in geosynchronous orbit a technically advanced communication satellite which can process time-division multiple access (TDMA) information bursts with a data throughput in excess of 4 GBPS. To guarantee acceptable data quality during periods of signal attenuation it will be necessary to provide a significant forward error correction (FEC) capability. Convolutional decoding (utilizing the maximum-likelihood techniques) was identified as the most attractive FEC strategy. Design trade-offs regarding a maximum-likelihood convolutional decoder (MCD) in a single-chip CMOS implementation are discussed.

A high speed CCSDS encoder for space applications

NASA Technical Reports Server (NTRS)

Whitaker, S.; Liu, K.

1990-01-01

This paper reports a VLSI implementation of the CCSDS standard Reed Solomon encoder circuit for the Space Station. The 1.0 micron double metal CMOS chip is 5.9 mm by 3.6 mm, contains 48,000 transistors, operates at a sustained data rate of 320 Mbits/s, and executes 2,560 Mops. The chip features a pin selectable interleave depth of 1 to 8. Block lengths of up to 255 bytes, as well as shortened codes, are supported. The control circuitry uses register cells which are immune to Single Event Upset. In addition, the CMOS process used is reported to be tolerant of over 1 Mrad total dose radiation.

Multichannel Baseband Processor for Wideband CDMA

NASA Astrophysics Data System (ADS)

Jalloul, Louay M. A.; Lin, Jim

2005-12-01

The system architecture of the cellular base station modem engine (CBME) is described. The CBME is a single-chip multichannel transceiver capable of processing and demodulating signals from multiple users simultaneously. It is optimized to process different classes of code-division multiple-access (CDMA) signals. The paper will show that through key functional system partitioning, tightly coupled small digital signal processing cores, and time-sliced reuse architecture, CBME is able to achieve a high degree of algorithmic flexibility while maintaining efficiency. The paper will also highlight the implementation and verification aspects of the CBME chip design. In this paper, wideband CDMA is used as an example to demonstrate the architecture concept.

Packet Controller For Wireless Headset

NASA Technical Reports Server (NTRS)

Christensen, Kurt K.; Swanson, Richard J.

1993-01-01

Packet-message controller implements communications protocol of network of wireless headsets. Designed for headset application, readily adapted to other uses; slight modification enables controller to implement Integrated Services Digital Network (ISDN) X.25 protocol, giving far-reaching applications in telecommunications. Circuit converts continuous voice signals into digital packets of data and vice versa. Operates in master or slave mode. Controller reduced to single complementary metal oxide/semiconductor integrated-circuit chip. Occupies minimal space in headset and consumes little power, extending life of headset battery.

Implementing inverted master-slave 3D semiconductor stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Coteus, Paul W.; Hall, Shawn A.; Takken, Todd E.

2016-03-08

A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap regionmore » defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.« less

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

PubMed Central

Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

2012-01-01

A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

Real-time bacterial microcolony counting using on-chip microscopy

NASA Astrophysics Data System (ADS)

Jung, Jae Hee; Lee, Jung Eun

2016-02-01

Observing microbial colonies is the standard method for determining the microbe titer and investigating the behaviors of microbes. Here, we report an automated, real-time bacterial microcolony-counting system implemented on a wide field-of-view (FOV), on-chip microscopy platform, termed ePetri. Using sub-pixel sweeping microscopy (SPSM) with a super-resolution algorithm, this system offers the ability to dynamically track individual bacterial microcolonies over a wide FOV of 5.7 mm × 4.3 mm without requiring a moving stage or lens. As a demonstration, we obtained high-resolution time-series images of S. epidermidis at 20-min intervals. We implemented an image-processing algorithm to analyze the spatiotemporal distribution of microcolonies, the development of which could be observed from a single bacterial cell. Test bacterial colonies with a minimum diameter of 20 μm could be enumerated within 6 h. We showed that our approach not only provides results that are comparable to conventional colony-counting assays but also can be used to monitor the dynamics of colony formation and growth. This microcolony-counting system using on-chip microscopy represents a new platform that substantially reduces the detection time for bacterial colony counting. It uses chip-scale image acquisition and is a simple and compact solution for the automation of colony-counting assays and microbe behavior analysis with applications in antibacterial drug discovery.

Point of care optical device for sepsis diagnosis

NASA Astrophysics Data System (ADS)

Baldini, F.; Bolzoni, L.; Giannetti, A.; Porro, G.; Senesi, F.; Trono, C.

2009-10-01

The discrimination of viral and bacterial sepsis is an important issue in intensive care patients. For this purpose, the simultaneous measurements of different analytes are necessary. Among the possible candidates, C-reactive protein (CRP) and procalcitonin (PCT) are probably the most important ones. A novel optical platform was designed and realised for the implementation of fluorescence-based immunoassays. The core of the optical platform is a plastic biochip, constituted by 13 microchannels (50 μm high, 600 μm width, 10 mm long) through which the sample flows. The sensing layer, where the immunochemical reaction takes place, is located on the upper part of each microchannel. The chip is interrogated with a novel optoelectronic platform, based on fluorescence anisotropy. A line-shaped beam from a 635-nm laser-diode excites perpendicularly the sensing layer and great many of the emitted remains entrapped inside the chip. The particular shape of the top of the chip allows to guide the emitted fluorescence along the same direction of the microchannel. The fluorescence which comes out on the lateral side from the chip is collected by a single plastic optical fibre and sent to an amplified photodiode. The device was characterised by the implementation of the sandwich assay for CRP and PCT spiked in serum. Limit of quantifications of 4.5 and of 6 μg L-1 in serum solution were achieved for CRP and PCT, respectively.

Real-time bacterial microcolony counting using on-chip microscopy

PubMed Central

Jung, Jae Hee; Lee, Jung Eun

2016-01-01

Observing microbial colonies is the standard method for determining the microbe titer and investigating the behaviors of microbes. Here, we report an automated, real-time bacterial microcolony-counting system implemented on a wide field-of-view (FOV), on-chip microscopy platform, termed ePetri. Using sub-pixel sweeping microscopy (SPSM) with a super-resolution algorithm, this system offers the ability to dynamically track individual bacterial microcolonies over a wide FOV of 5.7 mm × 4.3 mm without requiring a moving stage or lens. As a demonstration, we obtained high-resolution time-series images of S. epidermidis at 20-min intervals. We implemented an image-processing algorithm to analyze the spatiotemporal distribution of microcolonies, the development of which could be observed from a single bacterial cell. Test bacterial colonies with a minimum diameter of 20 μm could be enumerated within 6 h. We showed that our approach not only provides results that are comparable to conventional colony-counting assays but also can be used to monitor the dynamics of colony formation and growth. This microcolony-counting system using on-chip microscopy represents a new platform that substantially reduces the detection time for bacterial colony counting. It uses chip-scale image acquisition and is a simple and compact solution for the automation of colony-counting assays and microbe behavior analysis with applications in antibacterial drug discovery. PMID:26902822

On-Chip generation of polymer microcapsules through droplet coalescence

NASA Astrophysics Data System (ADS)

Eqbal, Md Danish; Gundabala, Venkat; Gundabala lab Team

Alginate microbeads and microcapsules have numerous applications in drug delivery, tissue engineering and other biomedical areas due to their unique properties. Microcapsules with liquid core are of particular interest in the area of cell encapsulation. Various methods such as coacervation, emulsification, micro-nozzle, etc. exist for the generation of microbeads and microcapsules. However, these methods have several drawbacks like coagulation, non-uniformity, and polydispersity. In this work we present a method for complete on chip generation of alginate microcapsules (single core as well as double core) through the use of droplet merging technique. For this purpose, a combined Coflow and T-junction configuration is implemented in a hybrid glass-PDMS (Polydimethylsiloxane) microfluidic device. Efficient generation is achieved through precise matching of the generation rates of the coalescing drops. Through this approach, microcapsules with intact single and double (liquid) cores surrounded by alginate shell have been successfully generated and characterized.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.

PubMed

Kirk, Andrew G; Plant, David V; Szymanski, Ted H; Vranesic, Zvonko G; Tooley, Frank A P; Rolston, David R; Ayliffe, Michael H; Lacroix, Frederic K; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F

2003-05-10

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

NASA Astrophysics Data System (ADS)

Kirk, Andrew G.; Plant, David V.; Szymanski, Ted H.; Vranesic, Zvonko G.; Tooley, Frank A. P.; Rolston, David R.; Ayliffe, Michael H.; Lacroix, Frederic K.; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F.

2003-05-01

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

On-chip microsystems in silicon: opportunities and limitations

NASA Astrophysics Data System (ADS)

Wolffenbuttel, R. F.

1996-03-01

Integrated on-chip micro-instrumentation systems in silicon are complete data acquisition systems on a single chip. This concept has appeared to be the ultimate solution in many applications, as it enables in principle the metamorphosis of a basic sensing element, affected with many shortcomings, into an on-chip data acquisition unit that provides an output digital data stream in a standard format not corrupted by sensor non-idealities. Market acceptance would be maximum, as no special knowledge about the internal operation is required, self-test and self-calibration can be included and the dimensions are not different from those of the integrated circuit. The various aspects that are relevant in estimating the constraints for successful implementation of the integrated silicon smart sensor will be outlined in comparison with the properties of more conventional sensor fabrication technologies. It will be shown that the acceptance of on-chip functional integration in an application depends primarily on the added value in terms of improved specification or functionality that the resulting device provides in that application. The economic viability is therefore decisive rather than the technological constraints. This is in contrast to the traditional technology push prevailing in sensor research over market pull mechanisms.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

NASA Astrophysics Data System (ADS)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

Multi-beam and single-chip LIDAR with discrete beam steering by digital micromirror device

NASA Astrophysics Data System (ADS)

Rodriguez, Joshua; Smith, Braden; Hellman, Brandon; Gin, Adley; Espinoza, Alonzo; Takashima, Yuzuru

2018-02-01

A novel Digital Micromirror Device (DMD) based beam steering enables a single chip Light Detection and Ranging (LIDAR) system for discrete scanning points. We present increasing number of scanning point by using multiple laser diodes for Multi-beam and Single-chip DMD-based LIDAR.

Implementation of the Timepix ASIC in the Scalable Readout System

NASA Astrophysics Data System (ADS)

Lupberger, M.; Desch, K.; Kaminski, J.

2016-09-01

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

COED Transactions, Vol. IX, No. 6, June 1977. An Introductory Course in Microprocessors and Microcomputers.

ERIC Educational Resources Information Center

Marcovitz, Alan B., Ed.

This paper describes an introductory course in microprocessors and microcomputers implemented at Grossmont College. The current state-of-the-art in the microprocessor field is discussed, with special emphasis on the 8-bit MOS single-chip processors which are the most commonly used devices. Objectives and guidelines for the course are presented,…

An ultra-low-power pulse oximeter implemented with an energy-efficient transimpedance amplifier.

PubMed

Tavakoli, M; Turicchia, L; Sarpeshkar, R

2010-02-01

Pulse oximeters are ubiquitous in modern medicine to noninvasively measure the percentage of oxygenated hemoglobin in a patient's blood by comparing the transmission characteristics of red and infrared light-emitting diode light through the patient's finger with a photoreceptor. We present an analog single-chip pulse oximeter with 4.8-mW total power dissipation, which is an order of magnitude below our measurements on commercial implementations. The majority of this power reduction is due to the use of a novel logarithmic transimpedance amplifier with inherent contrast sensitivity, distributed amplification, unilateralization, and automatic loop gain control. The transimpedance amplifier, together with a photodiode current source, form a high-performance photoreceptor with characteristics similar to those found in nature, which allows LED power to be reduced. Therefore, our oximeter is well suited for portable medical applications, such as continuous home-care monitoring for elderly or chronic patients, emergency patient transport, remote soldier monitoring, and wireless medical sensing. Furthermore, our design obviates the need for an A-to-D and digital signal processor and leads to a small single-chip solution. We outline how extensions of our work could lead to submilliwatt oximeters.

Advanced techniques and technology for efficient data storage, access, and transfer

NASA Technical Reports Server (NTRS)

Rice, Robert F.; Miller, Warner

1991-01-01

Advanced techniques for efficiently representing most forms of data are being implemented in practical hardware and software form through the joint efforts of three NASA centers. These techniques adapt to local statistical variations to continually provide near optimum code efficiency when representing data without error. Demonstrated in several earlier space applications, these techniques are the basis of initial NASA data compression standards specifications. Since the techniques clearly apply to most NASA science data, NASA invested in the development of both hardware and software implementations for general use. This investment includes high-speed single-chip very large scale integration (VLSI) coding and decoding modules as well as machine-transferrable software routines. The hardware chips were tested in the laboratory at data rates as high as 700 Mbits/s. A coding module's definition includes a predictive preprocessing stage and a powerful adaptive coding stage. The function of the preprocessor is to optimally process incoming data into a standard form data source that the second stage can handle.The built-in preprocessor of the VLSI coder chips is ideal for high-speed sampled data applications such as imaging and high-quality audio, but additionally, the second stage adaptive coder can be used separately with any source that can be externally preprocessed into the 'standard form'. This generic functionality assures that the applicability of these techniques and their recent high-speed implementations should be equally broad outside of NASA.

Single-Chip T/R Module for 1.2 GHz

NASA Technical Reports Server (NTRS)

Moussessian, Alina; Mojarradi, Mohammad; Johnson, Travis; Davis, John; Grigorian, Edwin; Hoffman, James; Caro, Edward; Kuhn, William

2006-01-01

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Development and applications of 3-dimensional integration nanotechnologies.

PubMed

Kim, Areum; Choi, Eunmi; Son, Hyungbin; Pyo, Sung Gyu

2014-02-01

Unlike conventional two-dimensional (2D) planar structures, signal or power is supplied through through-silicon via (TSV) in three-dimensional (3D) integration technology to replace wires for binding the chip/wafer. TSVs have becomes an essential technology, as they satisfy Moore's law. This 3D integration technology enables system and sensor functions at a nanoscale via the implementation of a highly integrated nano-semiconductor as well as the fabrication of a single chip with multiple functions. Thus, this technology is considered to be a new area of development for the systemization of the nano-bio area. In this review paper, the basic technology required for such 3D integration is described and methods to measure the bonding strength in order to measure the void occurring during bonding are introduced. Currently, CMOS image sensors and memory chips associated with nanotechnology are being realized on the basis of 3D integration technology. In this paper, we intend to describe the applications of high-performance nano-biosensor technology currently under development and the direction of development of a high performance lab-on-a-chip (LOC).

Design of an MR image processing module on an FPGA chip.

PubMed

Li, Limin; Wyrwicz, Alice M

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. Copyright © 2015 Elsevier Inc. All rights reserved.

Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

NASA Astrophysics Data System (ADS)

Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

2016-01-01

The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

Process for 3D chip stacking

DOEpatents

Malba, V.

1998-11-10

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

Process for 3D chip stacking

DOEpatents

Malba, Vincent

1998-01-01

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Reliability study of high-brightness multiple single emitter diode lasers

NASA Astrophysics Data System (ADS)

Zhu, Jing; Yang, Thomas; Zhang, Cuipeng; Lang, Chao; Jiang, Xiaochen; Liu, Rui; Gao, Yanyan; Guo, Weirong; Jiang, Yuhua; Liu, Yang; Zhang, Luyan; Chen, Louisa

2015-03-01

In this study the chip bonding processes for various chips from various chip suppliers around the world have been optimized to achieve reliable chip on sub-mount for high performance. These chip on sub-mounts, for examples, includes three types of bonding, 8xx nm-1.2W/10.0W Indium bonded lasers, 9xx nm 10W-20W AuSn bonded lasers and 1470 nm 6W Indium bonded lasers will be reported below. The MTTF@25 of 9xx nm chip on sub-mount (COS) is calculated to be more than 203,896 hours. These chips from various chip suppliers are packaged into many multiple single emitter laser modules, using similar packaging techniques from 2 emitters per module to up to 7 emitters per module. A reliability study including aging test is performed on those multiple single emitter laser modules. With research team's 12 years' experienced packaging design and techniques, precise optical and fiber alignment processes and superior chip bonding capability, we have achieved a total MTTF exceeding 177,710 hours of life time with 60% confidence level for those multiple single emitter laser modules. Furthermore, a separated reliability study on wavelength stabilized laser modules have shown this wavelength stabilized module packaging process is reliable as well.

Analog design of wireless control for home equipment

NASA Astrophysics Data System (ADS)

Zheng, Shiyong; Li, Zhao; Li, Biqing; Jiang, Suping

2018-04-01

This design consists of a STC89C52 microcontroller, a serial Bluetooth module and the Android system. Production of STC89C52 controlled by single-chip computer telephone systems. The system is composed of mobile phone Android system as a master in the family centre,via serial Bluetooth module pass instructions and information to implement wireless transceiver using STC89C52 MCU wireless Bluetooth transmission to control homedevices. System high reliability, low cost easy to use, stong applicability and other characerristics, can be used in single-user family, has great significance.

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

Miniaturized devices towards an integrated lab-on-a-chip platform for DNA diagnostics

NASA Astrophysics Data System (ADS)

Kaprou, G.; Papadakis, G.; Kokkoris, G.; Papadopoulos, V.; Kefala, I.; Papageorgiou, D.; Gizeli, E.; Tserepi, A.

2015-06-01

Microfluidics is an emerging technology enabling the development of Lab-on-a-chip (LOC) systems for clinical diagnostics, drug discovery and screening, food safety and environmental analysis. LOC systems integrate and scale down one or several laboratory functions on a single chip of a few mm2 to cm2 in size, and account for many advantages on biochemical analyses, such as low sample and reagent consumption, low cost, reduced analysis time, portability and point-of-need compatibility. Currently, available nucleic acid diagnostic tests take advantage of Polymerase Chain Reaction (PCR) that allows exponential amplification of portions of nucleic acid sequences that can be used as indicators for the identification of various diseases. Here, we present a comparison between static chamber and continuous flow miniaturized PCR devices, in terms of energy consumption for devices fabricated on the same material stack, with identical sample volume and channel dimensions. The comparison is implemented by a computational study coupling heat transfer in both solid and fluid, mass conservation of species, and joule heating. Based on the conclusions of this study, we develop low-cost and fast DNA amplification devices for both PCR and isothermal amplification, and we implement them in the detection of mutations related to breast cancer. The devices are fabricated by mass production amenable technologies on printed circuit board (PCB) substrates, where copper facilitates the incorporation of on-chip microheaters, defining the thermal zones necessary for PCR or isothermal amplification methods.

Evaluation of hardware costs of implementing PSK signal detection circuit based on "system on chip"

NASA Astrophysics Data System (ADS)

Sokolovskiy, A. V.; Dmitriev, D. D.; Veisov, E. A.; Gladyshev, A. B.

2018-05-01

The article deals with the choice of the architecture of digital signal processing units for implementing the PSK signal detection scheme. As an assessment of the effectiveness of architectures, the required number of shift registers and computational processes are used when implementing the "system on a chip" on the chip. A statistical estimation of the normalized code sequence offset in the signal synchronization scheme for various hardware block architectures is used.

Real-time time-division color electroholography using a single GPU and a USB module for synchronizing reference light.

PubMed

Araki, Hiromitsu; Takada, Naoki; Niwase, Hiroaki; Ikawa, Shohei; Fujiwara, Masato; Nakayama, Hirotaka; Kakue, Takashi; Shimobaba, Tomoyoshi; Ito, Tomoyoshi

2015-12-01

We propose real-time time-division color electroholography using a single graphics processing unit (GPU) and a simple synchronization system of reference light. To facilitate real-time time-division color electroholography, we developed a light emitting diode (LED) controller with a universal serial bus (USB) module and the drive circuit for reference light. A one-chip RGB LED connected to a personal computer via an LED controller was used as the reference light. A single GPU calculates three computer-generated holograms (CGHs) suitable for red, green, and blue colors in each frame of a three-dimensional (3D) movie. After CGH calculation using a single GPU, the CPU can synchronize the CGH display with the color switching of the one-chip RGB LED via the LED controller. Consequently, we succeeded in real-time time-division color electroholography for a 3D object consisting of around 1000 points per color when an NVIDIA GeForce GTX TITAN was used as the GPU. Furthermore, we implemented the proposed method in various GPUs. The experimental results showed that the proposed method was effective for various GPUs.

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Property-driven functional verification technique for high-speed vision system-on-chip processor

NASA Astrophysics Data System (ADS)

Nshunguyimfura, Victor; Yang, Jie; Liu, Liyuan; Wu, Nanjian

2017-04-01

The implementation of functional verification in a fast, reliable, and effective manner is a challenging task in a vision chip verification process. The main reason for this challenge is the stepwise nature of existing functional verification techniques. This vision chip verification complexity is also related to the fact that in most vision chip design cycles, extensive efforts are focused on how to optimize chip metrics such as performance, power, and area. Design functional verification is not explicitly considered at an earlier stage at which the most sound decisions are made. In this paper, we propose a semi-automatic property-driven verification technique. The implementation of all verification components is based on design properties. We introduce a low-dimension property space between the specification space and the implementation space. The aim of this technique is to speed up the verification process for high-performance parallel processing vision chips. Our experimentation results show that the proposed technique can effectively improve the verification effort up to 20% for the complex vision chip design while reducing the simulation and debugging overheads.

Three-dimensional fit-to-flow microfluidic assembly.

PubMed

Chen, Arnold; Pan, Tingrui

2011-12-01

Three-dimensional microfluidics holds great promise for large-scale integration of versatile, digitalized, and multitasking fluidic manipulations for biological and clinical applications. Successful translation of microfluidic toolsets to these purposes faces persistent technical challenges, such as reliable system-level packaging, device assembly and alignment, and world-to-chip interface. In this paper, we extended our previously established fit-to-flow (F2F) world-to-chip interconnection scheme to a complete system-level assembly strategy that addresses the three-dimensional microfluidic integration on demand. The modular F2F assembly consists of an interfacial chip, pluggable alignment modules, and multiple monolithic layers of microfluidic channels, through which convoluted three-dimensional microfluidic networks can be easily assembled and readily sealed with the capability of reconfigurable fluid flow. The monolithic laser-micromachining process simplifies and standardizes the fabrication of single-layer pluggable polymeric modules, which can be mass-produced as the renowned Lego(®) building blocks. In addition, interlocking features are implemented between the plug-and-play microfluidic chips and the complementary alignment modules through the F2F assembly, resulting in facile and secure alignment with average misalignment of 45 μm. Importantly, the 3D multilayer microfluidic assembly has a comparable sealing performance as the conventional single-layer devices, providing an average leakage pressure of 38.47 kPa. The modular reconfigurability of the system-level reversible packaging concept has been demonstrated by re-routing microfluidic flows through interchangeable modular microchannel layers.

A three channel telemetry system

NASA Technical Reports Server (NTRS)

Lesho, Jeffery C.; Eaton, Harry A. C.

1993-01-01

A three channel telemetry system intended for biomedical applications is described. The transmitter is implemented in a single chip using a 2 micron BiCMOS processes. The operation of the system and the test results from the latest chip are discussed. One channel is always dedicated to temperature measurement while the other two channels are generic. The generic channels carry information from transducers that are interfaced to the system through on-chip general purpose operational amplifiers. The generic channels have different bandwidths: one from dc to 250 Hz and the other from dc to 1300 Hz. Each generic channel modulates a current controlled oscillator to produce a frequency modulated signal. The two frequency modulated signals are summed and used to amplitude modulate the temperature signal which acts as a carrier. A near-field inductive link telemeters the combined signals over a short distance. The chip operates on a supply voltage anywhere from 2.5 to 3.6 Volts and draws less than 1 mA when transmitting a signal. The chip can be incorporated into ingestible, implantable and other configurations. The device can free the patient from tethered data collection systems and reduces the possibility of infection from subcutaneous leads. Data telemetry can increase patient comfort leading to a greater acceptance of monitoring.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Experimental single-chip color HDTV image acquisition system with 8M-pixel CMOS image sensor

NASA Astrophysics Data System (ADS)

Shimamoto, Hiroshi; Yamashita, Takayuki; Funatsu, Ryohei; Mitani, Kohji; Nojiri, Yuji

2006-02-01

We have developed an experimental single-chip color HDTV image acquisition system using 8M-pixel CMOS image sensor. The sensor has 3840 × 2160 effective pixels and is progressively scanned at 60 frames per second. We describe the color filter array and interpolation method to improve image quality with a high-pixel-count single-chip sensor. We also describe an experimental image acquisition system we used to measured spatial frequency characteristics in the horizontal direction. The results indicate good prospects for achieving a high quality single chip HDTV camera that reduces pseudo signals and maintains high spatial frequency characteristics within the frequency band for HDTV.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

Single instruction computer architecture and its application in image processing

NASA Astrophysics Data System (ADS)

Laplante, Phillip A.

1992-03-01

A single processing computer system using only half-adder circuits is described. In addition, it is shown that only a single hard-wired instruction is needed in the control unit to obtain a complete instruction set for this general purpose computer. Such a system has several advantages. First it is intrinsically a RISC machine--in fact the 'ultimate RISC' machine. Second, because only a single type of logic element is employed the entire computer system can be easily realized on a single, highly integrated chip. Finally, due to the homogeneous nature of the computer's logic elements, the computer has possible implementations as an optical or chemical machine. This in turn suggests possible paradigms for neural computing and artificial intelligence. After showing how we can implement a full-adder, min, max and other operations using the half-adder, we use an array of such full-adders to implement the dilation operation for two black and white images. Next we implement the erosion operation of two black and white images using a relative complement function and the properties of erosion and dilation. This approach was inspired by papers by van der Poel in which a single instruction is used to furnish a complete set of general purpose instructions and by Bohm- Jacopini where it is shown that any problem can be solved using a Turing machine with one entry and one exit.

Capacitively coupled hybrid pixel assemblies for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Tehrani, N. Alipour; Arfaoui, S.; Benoit, M.; Dannheim, D.; Dette, K.; Hynds, D.; Kulis, S.; Perić, I.; Petrič, M.; Redford, S.; Sicking, E.; Valerio, P.

2016-07-01

The vertex detector at the proposed CLIC multi-TeV linear e+e- collider must have minimal material content and high spatial resolution, combined with accurate time-stamping to cope with the expected high rate of beam-induced backgrounds. One of the options being considered is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel ASICs. A prototype of such an assembly, using two custom designed chips (CCPDv3 as active sensor glued to a CLICpix readout chip), has been characterised both in the lab and in beam tests at the CERN SPS using 120 GeV/c positively charged hadrons. Results of these characterisation studies are presented both for single and dual amplification stages in the active sensor, where efficiencies of greater than 99% have been achieved at -60 V substrate bias, with a single hit resolution of 6.1 μm . Pixel cross-coupling results are also presented, showing the sensitivity to placement precision and planarity of the glue layer.

Digital Filter ASIC for NASA Deep Space Radio Science

NASA Technical Reports Server (NTRS)

Kowalski, James E.

1995-01-01

This paper is about the implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB. The chip uses two decimation by five units and six decimations by two executed by a single decimation by two units. The six decimations by two consist of six halfband filters, five having 30-taps and one having 51-taps. Use of a 16x16 register file for the digital delay lines enables implementation in the Vitesse 350K gate array.

CCD correlation techniques

NASA Technical Reports Server (NTRS)

Hewes, C. R.; Bosshart, P. W.; Eversole, W. L.; Dewit, M.; Buss, D. D.

1976-01-01

Two CCD techniques were discussed for performing an N-point sampled data correlation between an input signal and an electronically programmable reference function. The design and experimental performance of an implementation of the direct time correlator utilizing two analog CCDs and MOS multipliers on a single IC were evaluated. The performance of a CCD implementation of the chirp z transform was described, and the design of a new CCD integrated circuit for performing correlation by multiplication in the frequency domain was presented. This chip provides a discrete Fourier transform (DFT) or inverse DFT, multipliers, and complete support circuitry for the CCD CZT. The two correlation techniques are compared.

Fabrication of polydimethylsiloxane (PDMS) nanofluidic chips with controllable channel size and spacing.

PubMed

Peng, Ran; Li, Dongqing

2016-10-07

The ability to create reproducible and inexpensive nanofluidic chips is essential to the fundamental research and applications of nanofluidics. This paper presents a novel and cost-effective method for fabricating a single nanochannel or multiple nanochannels in PDMS chips with controllable channel size and spacing. Single nanocracks or nanocrack arrays, positioned by artificial defects, are first generated on a polystyrene surface with controllable size and spacing by a solvent-induced method. Two sets of optimal working parameters are developed to replicate the nanocracks onto the polymer layers to form the nanochannel molds. The nanochannel molds are used to make the bi-layer PDMS microchannel-nanochannel chips by simple soft lithography. An alignment system is developed for bonding the nanofluidic chips under an optical microscope. Using this method, high quality PDMS nanofluidic chips with a single nanochannel or multiple nanochannels of sub-100 nm width and height and centimeter length can be obtained with high repeatability.

Single-Cell Isolation of Circulating Tumor Cells from Whole Blood by Lateral Magnetophoretic Microseparation and Microfluidic Dispensing.

PubMed

Kim, Jinho; Cho, Hyungseok; Han, Song-I; Han, Ki-Ho

2016-05-03

This paper introduces a single-cell isolation technology for circulating tumor cells (CTCs) using a microfluidic device (the "SIM-Chip"). The SIM-Chip comprises a lateral magnetophoretic microseparator and a microdispenser as a two-step cascade platform. First, CTCs were enriched from whole blood by the lateral magnetophoretic microseparator based on immunomagnetic nanobeads. Next, the enriched CTCs were electrically identified by single-cell impedance cytometer and isolated as single cells using the microshooter. Using 200 μL of whole blood spiked with 50 MCF7 breast cancer cells, the analysis demonstrated that the single-cell isolation efficiency of the SIM-Chip was 82.4%, and the purity of the isolated MCF7 cells with respect to WBCs was 92.45%. The data also showed that the WBC depletion rate of the SIM-Chip was 2.5 × 10(5) (5.4-log). The recovery rates were around 99.78% for spiked MCF7 cells ranging in number from 10 to 90. The isolated single MCF7 cells were intact and could be used for subsequent downstream genetic assays, such as RT-PCR. Single-cell culture evaluation of the proliferation of MCF7 cells isolated by the SIM-Chip showed that 84.1% of cells at least doubled in 5 days. Consequently, the SIM-Chip could be used for single-cell isolation of rare target cells from whole blood with high purity and recovery without cell damage.

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shao, H.M.; Reed, I.S.

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous paper is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area, therefore making it possible to build a pipelinemore » Reed-Solomon decoder on a single VLSI chip.« less

Optomechanical Design and Characterization of a Printed-Circuit-Board-Based Free-Space Optical Interconnect Package

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Marchand, Philippe J.; Huang, Dawei; Kibar, Osman; Ozkan, Nur S. E.; Esener, Sadik C.

1999-09-01

We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI s) can be integrated simply on electronic multichip modules (MCM s) for intra-MCM board interconnects. Our system-level packaging architecture is based on a modified folded 4 f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than 20 dB at low frequency have been measured. The system is compact at only 10 in. 3 (25.4 cm 3 ) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

Systolic array IC for genetic computation

NASA Technical Reports Server (NTRS)

Anderson, D.

1991-01-01

Measuring similarities between large sequences of genetic information is a formidable task requiring enormous amounts of computer time. Geneticists claim that nearly two months of CRAY-2 time are required to run a single comparison of the known database against the new bases that will be found this year, and more than a CRAY-2 year for next year's genetic discoveries, and so on. The DNA IC, designed at HP-ICBD in cooperation with the California Institute of Technology and the Jet Propulsion Laboratory, is being implemented in order to move the task of genetic comparison onto workstations and personal computers, while vastly improving performance. The chip is a systolic (pumped) array comprised of 16 processors, control logic, and global RAM, totaling 400,000 FETS. At 12 MHz, each chip performs 2.7 billion 16 bit operations per second. Using 35 of these chips in series on one PC board (performing nearly 100 billion operations per second), a sequence of 560 bases can be compared against the eventual total genome of 3 billion bases, in minutes--on a personal computer. While the designed purpose of the DNA chip is for genetic research, other disciplines requiring similarity measurements between strings of 7 bit encoded data could make use of this chip as well. Cryptography and speech recognition are two examples. A mix of full custom design and standard cells, in CMOS34, were used to achieve these goals. Innovative test methods were developed to enhance controllability and observability in the array. This paper describes these techniques as well as the chip's functionality. This chip was designed in the 1989-90 timeframe.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

A digital pixel cell for address event representation image convolution processing

NASA Astrophysics Data System (ADS)

Camunas-Mesa, Luis; Acosta-Jimenez, Antonio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

45 CFR 155.545 - Appeal decisions.

Code of Federal Regulations, 2014 CFR

2014-10-01

..., and if the Medicaid or CHIP agencies delegate authority to conduct the Medicaid fair hearing or CHIP... the Exchange or the Medicaid or CHIP agency, as applicable. (c) Implementation of appeal decisions...

45 CFR 155.545 - Appeal decisions.

Code of Federal Regulations, 2013 CFR

2013-10-01

..., and if the Medicaid or CHIP agencies delegate authority to conduct the Medicaid fair hearing or CHIP... the Exchange or the Medicaid or CHIP agency, as applicable. (c) Implementation of appeal decisions...

μOrgano: A Lego®-Like Plug & Play System for Modular Multi-Organ-Chips.

PubMed

Loskill, Peter; Marcus, Sivan G; Mathur, Anurag; Reese, Willie Mae; Healy, Kevin E

2015-01-01

Human organ-on-a-chip systems for drug screening have evolved as feasible alternatives to animal models, which are unreliable, expensive, and at times erroneous. While chips featuring single organs can be of great use for both pharmaceutical testing and basic organ-level studies, the huge potential of the organ-on-a-chip technology is revealed by connecting multiple organs on one chip to create a single integrated system for sophisticated fundamental biological studies and devising therapies for disease. Furthermore, since most organ-on-a-chip systems require special protocols with organ-specific media for the differentiation and maturation of the tissues, multi-organ systems will need to be temporally customizable and flexible in terms of the time point of connection of the individual organ units. We present a customizable Lego®-like plug & play system, μOrgano, which enables initial individual culture of single organ-on-a-chip systems and subsequent connection to create integrated multi-organ microphysiological systems. As a proof of concept, the μOrgano system was used to connect multiple heart chips in series with excellent cell viability and spontaneously physiological beat rates.

μOrgano: A Lego®-Like Plug & Play System for Modular Multi-Organ-Chips

PubMed Central

Loskill, Peter; Marcus, Sivan G.; Mathur, Anurag; Reese, Willie Mae; Healy, Kevin E.

2015-01-01

Human organ-on-a-chip systems for drug screening have evolved as feasible alternatives to animal models, which are unreliable, expensive, and at times erroneous. While chips featuring single organs can be of great use for both pharmaceutical testing and basic organ-level studies, the huge potential of the organ-on-a-chip technology is revealed by connecting multiple organs on one chip to create a single integrated system for sophisticated fundamental biological studies and devising therapies for disease. Furthermore, since most organ-on-a-chip systems require special protocols with organ-specific media for the differentiation and maturation of the tissues, multi-organ systems will need to be temporally customizable and flexible in terms of the time point of connection of the individual organ units. We present a customizable Lego®-like plug & play system, μOrgano, which enables initial individual culture of single organ-on-a-chip systems and subsequent connection to create integrated multi-organ microphysiological systems. As a proof of concept, the μOrgano system was used to connect multiple heart chips in series with excellent cell viability and spontaneously physiological beat rates. PMID:26440672

Fabrication and characterization of high-efficiency double-sided blazed x-ray optics.

PubMed

Mohacsi, Istvan; Vartiainen, Ismo; Guizar-Sicairos, Manuel; Karvinen, Petri; Guzenko, Vitaliy A; Müller, Elisabeth; Kewish, Cameron M; Somogyi, Andrea; David, Christian

2016-01-15

The focusing efficiency of conventional diffractive x-ray lenses is fundamentally limited due to their symmetric binary structures and the corresponding symmetry of their focusing and defocusing diffraction orders. Fresnel zone plates with asymmetric structure profiles can break this limitation; yet existing implementations compromise either on resolution, ease of use, or stability. We present a new way for the fabrication of such blazed lenses by patterning two complementary binary Fresnel zone plates on the front and back sides of the same membrane chip to provide a compact, inherently stable, single-chip device. The presented blazed double-sided zone plates with 200 nm smallest half-pitch provide up to 54.7% focusing efficiency at 6.2 keV, which is clearly beyond the value obtainable by their binary counterparts.

On-chip detection of non-classical light by scalable integration of single-photon detectors

PubMed Central

Najafi, Faraz; Mower, Jacob; Harris, Nicholas C.; Bellei, Francesco; Dane, Andrew; Lee, Catherine; Hu, Xiaolong; Kharel, Prashanta; Marsili, Francesco; Assefa, Solomon; Berggren, Karl K.; Englund, Dirk

2015-01-01

Photonic-integrated circuits have emerged as a scalable platform for complex quantum systems. A central goal is to integrate single-photon detectors to reduce optical losses, latency and wiring complexity associated with off-chip detectors. Superconducting nanowire single-photon detectors (SNSPDs) are particularly attractive because of high detection efficiency, sub-50-ps jitter and nanosecond-scale reset time. However, while single detectors have been incorporated into individual waveguides, the system detection efficiency of multiple SNSPDs in one photonic circuit—required for scalable quantum photonic circuits—has been limited to <0.2%. Here we introduce a micrometer-scale flip-chip process that enables scalable integration of SNSPDs on a range of photonic circuits. Ten low-jitter detectors are integrated on one circuit with 100% device yield. With an average system detection efficiency beyond 10%, and estimated on-chip detection efficiency of 14–52% for four detectors operated simultaneously, we demonstrate, to the best of our knowledge, the first on-chip photon correlation measurements of non-classical light. PMID:25575346

Optimized FPGA Implementation of the Thyroid Hormone Secretion Mechanism Using CAD Tools.

PubMed

Alghazo, Jaafar M

2017-02-01

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

Single-chip microcomputer application in high-altitude balloon orientation system

NASA Technical Reports Server (NTRS)

Lim, T. S.; Ehrmann, C. H.; Allison, S. R.

1980-01-01

This paper describes the application of a single-chip microcomputer in a high-altitude balloon instrumentation system. The system, consisting of a magnetometer, a stepping motor, a microcomputer and a gray code shaft encoder, is used to provide an orientation reference to point a scientific instrument at an object in space. The single-chip microcomputer, Intel's 8748, consisting of a CPU, program memory, data memory and I/O ports, is used to control the orientation of the system.

puma: a Bioconductor package for propagating uncertainty in microarray analysis.

PubMed

Pearson, Richard D; Liu, Xuejun; Sanguinetti, Guido; Milo, Marta; Lawrence, Neil D; Rattray, Magnus

2009-07-09

Most analyses of microarray data are based on point estimates of expression levels and ignore the uncertainty of such estimates. By determining uncertainties from Affymetrix GeneChip data and propagating these uncertainties to downstream analyses it has been shown that we can improve results of differential expression detection, principal component analysis and clustering. Previously, implementations of these uncertainty propagation methods have only been available as separate packages, written in different languages. Previous implementations have also suffered from being very costly to compute, and in the case of differential expression detection, have been limited in the experimental designs to which they can be applied. puma is a Bioconductor package incorporating a suite of analysis methods for use on Affymetrix GeneChip data. puma extends the differential expression detection methods of previous work from the 2-class case to the multi-factorial case. puma can be used to automatically create design and contrast matrices for typical experimental designs, which can be used both within the package itself but also in other Bioconductor packages. The implementation of differential expression detection methods has been parallelised leading to significant decreases in processing time on a range of computer architectures. puma incorporates the first R implementation of an uncertainty propagation version of principal component analysis, and an implementation of a clustering method based on uncertainty propagation. All of these techniques are brought together in a single, easy-to-use package with clear, task-based documentation. For the first time, the puma package makes a suite of uncertainty propagation methods available to a general audience. These methods can be used to improve results from more traditional analyses of microarray data. puma also offers improvements in terms of scope and speed of execution over previously available methods. puma is recommended for anyone working with the Affymetrix GeneChip platform for gene expression analysis and can also be applied more generally.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

PubMed

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

PubMed Central

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A.; Wu, Wen-Jung; Lin, Chih-Ting

2014-01-01

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems. PMID:24859027

High data rate Reed-Solomon encoding and decoding using VLSI technology

NASA Technical Reports Server (NTRS)

Miller, Warner; Morakis, James

1987-01-01

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

A CMOS ASIC Design for SiPM Arrays

PubMed Central

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2012-01-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

Effect of increasing the number of single-nucleotide polymorphisms from 60,000 to 85,000 in genomic evaluation of Holsteins

USDA-ARS?s Scientific Manuscript database

The periodic need to restock reagent pools for genotyping chips provides an opportunity to increase the number of single-nucleotide polymorphisms (SNP) on a chip at no increase in cost. A high-density chip with >140,000 SNP has been developed by GeneSeek Inc. (Lincoln, NE) to increase accuracy of ge...

Helicase dependent OnChip-amplification and its use in multiplex pathogen detection.

PubMed

Andresen, Dennie; von Nickisch-Rosenegk, Markus; Bier, Frank F

2009-05-01

The need for fast, specific and sensitive multiparametric detection methods is an ever growing demand in molecular diagnostics. Here we report on a newly developed method, the helicase dependent OnChip amplification (OnChip-HDA). This approach integrates the analysis and detection in one single reaction thus leading to time and cost savings in multiparametric analysis. HDA is an isothermal amplification method that is not depending on thermocycling as known from PCR due to the helicases' ability to unwind DNA double-strands. We have combined the HDA with microarray based detection, making it suitable for multiplex detection. As an example we used the OnChip HDA in single and multiplex amplifications for the detection of the two pathogens N. gonorrhoeae and S. aureus directly on surface bound primers. We have successfully shown the OnChip-HDA and applied it for single- and duplex-detection of the pathogens N. gonorrhoeae and S. aureus. We have developed a new method, the OnChip-HDA for the multiplex detection of pathogens. Its simplicity in reaction setup and potential for miniaturization and multiparametric analysis is advantageous for the integration in miniaturized Lab on Chip systems, e.g. needed in point of care diagnostics.

[A heart function measuring and analyzing instrument based on single-chip microcomputer].

PubMed

Rong, Z; Liang, H; Wang, S

1999-05-01

An Introduction a measuring and analyzing instrument, based on the single-chip microcomputer, which provides sample gathering, processing, controlling, adjusting, keyboard and printing. All informations are provided and displayed in Chinese.

Multiple-Event, Single-Photon Counting Imaging Sensor

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Cunningham, Thomas J.; Sun, Chao; Wang, Kang L.

2011-01-01

The single-photon counting imaging sensor is typically an array of silicon Geiger-mode avalanche photodiodes that are monolithically integrated with CMOS (complementary metal oxide semiconductor) readout, signal processing, and addressing circuits located in each pixel and the peripheral area of the chip. The major problem is its single-event method for photon count number registration. A single-event single-photon counting imaging array only allows registration of up to one photon count in each of its pixels during a frame time, i.e., the interval between two successive pixel reset operations. Since the frame time can t be too short, this will lead to very low dynamic range and make the sensor merely useful for very low flux environments. The second problem of the prior technique is a limited fill factor resulting from consumption of chip area by the monolithically integrated CMOS readout in pixels. The resulting low photon collection efficiency will substantially ruin any benefit gained from the very sensitive single-photon counting detection. The single-photon counting imaging sensor developed in this work has a novel multiple-event architecture, which allows each of its pixels to register as more than one million (or more) photon-counting events during a frame time. Because of a consequently boosted dynamic range, the imaging array of the invention is capable of performing single-photon counting under ultra-low light through high-flux environments. On the other hand, since the multiple-event architecture is implemented in a hybrid structure, back-illumination and close-to-unity fill factor can be realized, and maximized quantum efficiency can also be achieved in the detector array.

Digital LAMP in a sample self-digitization (SD) chip

PubMed Central

Herrick, Alison M.; Dimov, Ivan K.; Lee, Luke P.; Chiu, Daniel T.

2012-01-01

This paper describes the realization of digital loop-mediated DNA amplification (dLAMP) in a sample self-digitization (SD) chip. Digital DNA amplification has become an attractive technique to quantify absolute concentrations of DNA in a sample. While digital polymerase chain reaction is still the most widespread implementation, its use in resource—limited settings is impeded by the need for thermal cycling and robust temperature control. In such situations, isothermal protocols that can amplify DNA or RNA without thermal cycling are of great interest. Here, we showed the successful amplification of single DNA molecules in a stationary droplet array using isothermal digital loop-mediated DNA amplification. Unlike most (if not all) existing methods for sample discretization, our design allows for automated, loss-less digitization of sample volumes on-chip. We demonstrated accurate quantification of relative and absolute DNA concentrations with sample volumes of less than 2 μl. We assessed the homogeneity of droplet size during sample self-digitization in our device, and verified that the size variation was small enough such that straightforward counting of LAMP-active droplets sufficed for data analysis. We anticipate that the simplicity and robustness of our SD chip make it attractive as an inexpensive and easy-to-operate device for DNA amplification, for example in point-of-care settings. PMID:22399016

Gbps wireless transceivers for high bandwidth interconnections in distributed cyber physical systems

NASA Astrophysics Data System (ADS)

Saponara, Sergio; Neri, Bruno

2015-05-01

In Cyber Physical Systems there is a growing use of high speed sensors like photo and video camera, radio and light detection and ranging (Radar/Lidar) sensors. Hence Cyber Physical Systems can benefit from the high communication data rate, several Gbps, that can be provided by mm-wave wireless transceivers. At such high frequency the wavelength is few mm and hence the whole transceiver including the antenna can be integrated in a single chip. To this aim this paper presents the design of 60 GHz transceiver architecture to ensure connection distances up to 10 m and data rate up to 4 Gbps. At 60 GHz there are more than 7 GHz of unlicensed bandwidth (available for free for development of new services). By using a CMOS SOI technology RF, analog and digital baseband circuitry can be integrated in the same chip minimizing noise coupling. Even the antenna is integrated on chip reducing cost and size vs. classic off-chip antenna solutions. Therefore the proposed transceiver can enable at physical layer the implementation of low cost nodes for a Cyber Physical System with data rates of several Gbps and with a communication distance suitable for home/office scenarios, or on-board vehicles such as cars, trains, ships, airplanes

From Genes to Protein Mechanics on a Chip

PubMed Central

Milles, Lukas F.; Verdorfer, Tobias; Pippig, Diana A.; Nash, Michael A.; Gaub, Hermann E.

2014-01-01

Single-molecule force spectroscopy enables mechanical testing of individual proteins, however low experimental throughput limits the ability to screen constructs in parallel. We describe a microfluidic platform for on-chip protein expression and measurement of single-molecule mechanical properties. We constructed microarrays of proteins covalently attached to a chip surface, and found that a single cohesin-modified cantilever that bound to the terminal dockerin-tag of each protein remained stable over thousands of pulling cycles. The ability to synthesize and mechanically probe protein libraries presents new opportunities for high-throughput mechanical phenotyping. PMID:25194847

Optical Interconnections for VLSI Computational Systems Using Computer-Generated Holography.

NASA Astrophysics Data System (ADS)

Feldman, Michael Robert

Optical interconnects for VLSI computational systems using computer generated holograms are evaluated in theory and experiment. It is shown that by replacing particular electronic connections with free-space optical communication paths, connection of devices on a single chip or wafer and between chips or modules can be improved. Optical and electrical interconnects are compared in terms of power dissipation, communication bandwidth, and connection density. Conditions are determined for which optical interconnects are advantageous. Based on this analysis, it is shown that by applying computer generated holographic optical interconnects to wafer scale fine grain parallel processing systems, dramatic increases in system performance can be expected. Some new interconnection networks, designed to take full advantage of optical interconnect technology, have been developed. Experimental Computer Generated Holograms (CGH's) have been designed, fabricated and subsequently tested in prototype optical interconnected computational systems. Several new CGH encoding methods have been developed to provide efficient high performance CGH's. One CGH was used to decrease the access time of a 1 kilobit CMOS RAM chip. Another was produced to implement the inter-processor communication paths in a shared memory SIMD parallel processor array.

On-chip Magnetic Separation and Cell Encapsulation in Droplets

NASA Astrophysics Data System (ADS)

Chen, A.; Byvank, T.; Bharde, A.; Miller, B. L.; Chalmers, J. J.; Sooryakumar, R.; Chang, W.-J.; Bashir, R.

2012-02-01

The demand for high-throughput single cell assays is gaining importance because of the heterogeneity of many cell suspensions, even after significant initial sorting. These suspensions may display cell-to-cell variability at the gene expression level that could impact single cell functional genomics, cancer, stem-cell research and drug screening. The on-chip monitoring of individual cells in an isolated environment could prevent cross-contamination, provide high recovery yield and ability to study biological traits at a single cell level These advantages of on-chip biological experiments contrast to conventional methods, which require bulk samples that provide only averaged information on cell metabolism. We report on a device that integrates microfluidic technology with a magnetic tweezers array to combine the functionality of separation and encapsulation of objects such as immunomagnetically labeled cells or magnetic beads into pico-liter droplets on the same chip. The ability to control the separation throughput that is independent of the hydrodynamic droplet generation rate allows the encapsulation efficiency to be optimized. The device can potentially be integrated with on-chip labeling and/or bio-detection to become a powerful single-cell analysis device.

Passive UHF RFID Tag with Multiple Sensing Capabilities

PubMed Central

Fernández-Salmerón, José; Rivadeneyra, Almudena; Martínez-Martí, Fernando; Capitán-Vallvey, Luis Fermín; Palma, Alberto J.; Carvajal, Miguel A.

2015-01-01

This work presents the design, fabrication, and characterization of a printed radio frequency identification tag in the ultra-high frequency band with multiple sensing capabilities. This passive tag is directly screen printed on a cardboard box with the aim of monitoring the packaging conditions during the different stages of the supply chain. This tag includes a commercial force sensor and a printed opening detector. Hence, the force applied to the package can be measured as well as the opening of the box can be detected. The architecture presented is a passive single-chip RFID tag. An electronic switch has been implemented to be able to measure both sensor magnitudes in the same access without including a microcontroller or battery. Moreover, the chip used here integrates a temperature sensor and, therefore, this tag provides three different parameters in every reading. PMID:26506353

Research on single-chip microcomputer controlled rotating magnetic field mineralization model

NASA Astrophysics Data System (ADS)

Li, Yang; Qi, Yulin; Yang, Junxiao; Li, Na

2017-08-01

As one of the method of selecting ore, the magnetic separation method has the advantages of stable operation, simple process flow, high beneficiation efficiency and no chemical environment pollution. But the existing magnetic separator are more mechanical, the operation is not flexible, and can not change the magnetic field parameters according to the precision of the ore needed. Based on the existing magnetic separator is mechanical, the rotating magnetic field can be used for single chip microcomputer control as the research object, design and trial a rotating magnetic field processing prototype, and through the single-chip PWM pulse output to control the rotation of the magnetic field strength and rotating magnetic field speed. This method of using pure software to generate PWM pulse to control rotary magnetic field beneficiation, with higher flexibility, accuracy and lower cost, can give full play to the performance of single-chip.

Single-chip source-free terahertz spectroscope across 0.04-0.99 THz: combining sub-wavelength near-field sensing and regression analysis.

PubMed

Wu, Xue; Sengupta, Kaushik

2018-03-19

This paper demonstrates a methodology to miniaturize THz spectroscopes into a single silicon chip by eliminating traditional solid-state architectural components such as complex tunable THz and optical sources, nonlinear mixing and amplifiers. The proposed method achieves this by extracting incident THz spectral signatures from the surface of an on-chip antenna itself. The information is sensed through the spectrally-sensitive 2D distribution of the impressed current surface under the THz incident field. By converting the antenna from a single-port to a massively multi-port architecture with integrated electronics and deep subwavelength sensing, THz spectral estimation is converted into a linear estimation problem. We employ rigorous regression techniques and analysis to demonstrate a single silicon chip system operating at room temperature across 0.04-0.99 THz with 10 MHz accuracy in spectrum estimation of THz tones across the entire spectrum.

Inherent polarization entanglement generated from a monolithic semiconductor chip

PubMed Central

Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng; Abolghasem, Payam; Scarcella, Carmelo; Frera, Adriano Della; Tosi, Alberto; Helt, Lukas G.; Zhukovsky, Sergei V.; Sipe, J. E.; Weihs, Gregor; Helmy, Amr S.; Jennewein, Thomas

2013-01-01

Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral filtering or post-selection. After splitting the twin-photons immediately after they emerge from the chip, we perform a variety of correlation tests on the photon pairs and show non-classical behaviour in their polarization. Combined with the BRW's versatile architecture our results signify the BRW design as a serious contender on which to build large scale implementations of optical quantum processing devices. PMID:23896982

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Rapid prototyping of update algorithm of discrete Fourier transform for real-time signal processing

NASA Astrophysics Data System (ADS)

Kakad, Yogendra P.; Sherlock, Barry G.; Chatapuram, Krishnan V.; Bishop, Stephen

2001-10-01

An algorithm is developed in the companion paper, to update the existing DFT to represent the new data series that results when a new signal point is received. Updating the DFT in this way uses less computation than directly evaluating the DFT using the FFT algorithm, This reduces the computational order by a factor of log2 N. The algorithm is able to work in the presence of data window function, for use with rectangular window, the split triangular, Hanning, Hamming, and Blackman windows. In this paper, a hardware implementation of this algorithm, using FPGA technology, is outlined. Unlike traditional fully customized VLSI circuits, FPGAs represent a technical break through in the corresponding industry. The FPGA implements thousands of gates of logic in a single IC chip and it can be programmed by users at their site in a few seconds or less depending on the type of device used. The risk is low and the development time is short. The advantages have made FPGAs very popular for rapid prototyping of algorithms in the area of digital communication, digital signal processing, and image processing. Our paper addresses the related issues of implementation using hardware descriptive language in the development of the design and the subsequent downloading on the programmable hardware chip.

A monolithic K-band phase-locked loop for microwave radar application

NASA Astrophysics Data System (ADS)

Zhou, Guangyao; Ma, Shunli; Li, Ning; Ye, Fan; Ren, Junyan

2017-02-01

A monolithic K-band phase-locked loop (PLL) for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator (VCO) achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic (CML) divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency. Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components. The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of ‑0.84 dBm and phase noise of ‑91.92 dBc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm2 without pads under a 1.2 V single voltage supply. Project supported by the National High-Tech Research and Development Program of China (No. 2013AA014101).

Neuron array with plastic synapses and programmable dendrites.

PubMed

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

A 32-bit NMOS microprocessor with a large register file

NASA Astrophysics Data System (ADS)

Sherburne, R. W., Jr.; Katevenis, M. G. H.; Patterson, D. A.; Sequin, C. H.

1984-10-01

Two scaled versions of a 32-bit NMOS reduced instruction set computer CPU, called RISC II, have been implemented on two different processing lines using the simple Mead and Conway layout rules with lambda values of 2 and 1.5 microns (corresponding to drawn gate lengths of 4 and 3 microns), respectively. The design utilizes a small set of simple instructions in conjunction with a large register file in order to provide high performance. This approach has resulted in two surprisingly powerful single-chip processors.

The artificial satellite observation chronograph controlled by single chip microcomputer.

NASA Astrophysics Data System (ADS)

Pan, Guangrong; Tan, Jufan; Ding, Yuanjun

1991-06-01

The instrument specifications, hardware structure, software design, and other characteristics of the chronograph mounting on a theodolite used for artificial satellite observation are presented. The instrument is a real time control system with a single chip microcomputer.

CMOS-array design-automation techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardt, T.

1979-01-01

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Chip-set for quality of service support in passive optical networks

NASA Astrophysics Data System (ADS)

Ringoot, Edwin; Hoebeke, Rudy; Slabbinck, B. Hans; Verhaert, Michel

1998-10-01

In this paper the design of a chip-set for QoS provisioning in ATM-based Passive Optical Networks is discussed. The implementation of a general-purpose switch chip on the Optical Network Unit is presented, with focus on the design of the cell scheduling and buffer management logic. The cell scheduling logic supports `colored' grants, priority jumping and weighted round-robin scheduling. The switch chip offers powerful buffer management capabilities enabling the efficient support of GFR and UBR services. Multicast forwarding is also supported. In addition, the architecture of a MAC controller chip developed for a SuperPON access network is introduced. In particular, the permit scheduling logic and its implementation on the Optical Line Termination will be discussed. The chip-set enables the efficient support of services with different service requirements on the SuperPON. The permit scheduling logic built into the MAC controller chip in combination with the cell scheduling and buffer management capabilities of the switch chip can be used by network operators to offer guaranteed service performance to delay sensitive services, and to efficiently and fairly distribute any spare capacity to delay insensitive services.

FPGA-Based, Self-Checking, Fault-Tolerant Computers

NASA Technical Reports Server (NTRS)

Some, Raphael; Rennels, David

2004-01-01

A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.

In vitro large-scale experimental and theoretical studies for the realization of bi-directional brain-prostheses.

PubMed

Bonifazi, Paolo; Difato, Francesco; Massobrio, Paolo; Breschi, Gian L; Pasquale, Valentina; Levi, Timothée; Goldin, Miri; Bornat, Yannick; Tedesco, Mariateresa; Bisio, Marta; Kanner, Sivan; Galron, Ronit; Tessadori, Jacopo; Taverna, Stefano; Chiappalone, Michela

2013-01-01

Brain-machine interfaces (BMI) were born to control "actions from thoughts" in order to recover motor capability of patients with impaired functional connectivity between the central and peripheral nervous system. The final goal of our studies is the development of a new proof-of-concept BMI-a neuromorphic chip for brain repair-to reproduce the functional organization of a damaged part of the central nervous system. To reach this ambitious goal, we implemented a multidisciplinary "bottom-up" approach in which in vitro networks are the paradigm for the development of an in silico model to be incorporated into a neuromorphic device. In this paper we present the overall strategy and focus on the different building blocks of our studies: (i) the experimental characterization and modeling of "finite size networks" which represent the smallest and most general self-organized circuits capable of generating spontaneous collective dynamics; (ii) the induction of lesions in neuronal networks and the whole brain preparation with special attention on the impact on the functional organization of the circuits; (iii) the first production of a neuromorphic chip able to implement a real-time model of neuronal networks. A dynamical characterization of the finite size circuits with single cell resolution is provided. A neural network model based on Izhikevich neurons was able to replicate the experimental observations. Changes in the dynamics of the neuronal circuits induced by optical and ischemic lesions are presented respectively for in vitro neuronal networks and for a whole brain preparation. Finally the implementation of a neuromorphic chip reproducing the network dynamics in quasi-real time (10 ns precision) is presented.

Language Classification using N-grams Accelerated by FPGA-based Bloom Filters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacob, A; Gokhale, M

N-Gram (n-character sequences in text documents) counting is a well-established technique used in classifying the language of text in a document. In this paper, n-gram processing is accelerated through the use of reconfigurable hardware on the XtremeData XD1000 system. Our design employs parallelism at multiple levels, with parallel Bloom Filters accessing on-chip RAM, parallel language classifiers, and parallel document processing. In contrast to another hardware implementation (HAIL algorithm) that uses off-chip SRAM for lookup, our highly scalable implementation uses only on-chip memory blocks. Our implementation of end-to-end language classification runs at 85x comparable software and 1.45x the competing hardware design.

Controlled and tunable polymer particles' production using a single microfluidic device

NASA Astrophysics Data System (ADS)

Amoyav, Benzion; Benny, Ofra

2018-04-01

Microfluidics technology offers a new platform to control liquids under flow in small volumes. The advantage of using small-scale reactions for droplet generation along with the capacity to control the preparation parameters, making microfluidic chips an attractive technology for optimizing encapsulation formulations. However, one of the drawback in this methodology is the ability to obtain a wide range of droplet sizes, from sub-micron to microns using a single chip design. In fact, typically, droplet chips are used for micron-dimension particles, while nanoparticles' synthesis requires complex chips design (i.e., microreactors and staggered herringbone micromixer). Here, we introduce the development of a highly tunable and controlled encapsulation technique, using two polymer compositions, for generating particles ranging from microns to nano-size using the same simple single microfluidic chip design. Poly(lactic-co-glycolic acid) (PLGA 50:50) or PLGA/polyethylene glycol polymeric particles were prepared with focused-flow chip, yielding monodisperse particle batches. We show that by varying flow rate, solvent, surfactant and polymer composition, we were able to optimize particles' size and decrease polydispersity index, using simple chip designs with no further related adjustments or costs. Utilizing this platform, which offers tight tuning of particle properties, could offer an important tool for formulation development and can potentially pave the way towards a better precision nanomedicine.

The development of the time-keeping clock with TS-1 single chip microcomputer.

NASA Astrophysics Data System (ADS)

Zhou, Jiguang; Li, Yongan

The authors have developed a time-keeping clock with Intel 8751 single chip microcomputer that has been successfully used in time-keeping station. The hard-soft ware design and performance of the clock are introduced.

Optics-Integrated Microfluidic Platforms for Biomolecular Analyses

PubMed Central

Bates, Kathleen E.; Lu, Hang

2016-01-01

Compared with conventional optical methods, optics implemented on microfluidic chips provide small, and often much cheaper ways to interrogate biological systems from the level of single molecules up to small model organisms. The optical probing of single molecules has been used to investigate the mechanical properties of individual biological molecules; however, multiplexing of these measurements through microfluidics and nanofluidics confers many analytical advantages. Optics-integrated microfluidic systems can significantly simplify sample processing and allow a more user-friendly experience; alignments of on-chip optical components are predetermined during fabrication and many purely optical techniques are passively controlled. Furthermore, sample loss from complicated preparation and fluid transfer steps can be virtually eliminated, a particularly important attribute for biological molecules at very low concentrations. Excellent fluid handling and high surface area/volume ratios also contribute to faster detection times for low abundance molecules in small sample volumes. Although integration of optical systems with classical microfluidic analysis techniques has been limited, microfluidics offers a ready platform for interrogation of biophysical properties. By exploiting the ease with which fluids and particles can be precisely and dynamically controlled in microfluidic devices, optical sensors capable of unique imaging modes, single molecule manipulation, and detection of minute changes in concentration of an analyte are possible. PMID:27119629

Next Generation Instrumentation Bus Test Plan for Fibre Channel

DTIC Science & Technology

1999-09-30

sample for port testing. The heart of the Fibre Xpress network cards is the tachyon chip from Hewlett Packard. The tachyon chip is basically a single...be to test the protocols. 1.5.1.1 Tachyon chip The user’s manual for the Tachyon controller chip identifies the following FC-AL specification

Single chip camera device having double sampling operation

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nixon, Robert (Inventor)

2002-01-01

A single chip camera device is formed on a single substrate including an image acquisition portion for control portion and the timing circuit formed on the substrate. The timing circuit also controls the photoreceptors in a double sampling mode in which are reset level is first read and then after an integration time a charged level is read.

Adjustment of multi-CCD-chip-color-camera heads

NASA Astrophysics Data System (ADS)

Guyenot, Volker; Tittelbach, Guenther; Palme, Martin

1999-09-01

The principle of beam-splitter-multi-chip cameras consists in splitting an image into differential multiple images of different spectral ranges and in distributing these onto separate black and white CCD-sensors. The resulting electrical signals from the chips are recombined to produce a high quality color picture on the monitor. Because this principle guarantees higher resolution and sensitivity in comparison to conventional single-chip camera heads, the greater effort is acceptable. Furthermore, multi-chip cameras obtain the compete spectral information for each individual object point while single-chip system must rely on interpolation. In a joint project, Fraunhofer IOF and STRACON GmbH and in future COBRA electronic GmbH develop methods for designing the optics and dichroitic mirror system of such prism color beam splitter devices. Additionally, techniques and equipment for the alignment and assembly of color beam splitter-multi-CCD-devices on the basis of gluing with UV-curable adhesives have been developed, too.

Multi-petascale highly efficient parallel supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time andmore » supports DMA functionality allowing for parallel processing message-passing.« less

Architecture, Design and Implementation of RC64, a Many-Core High-Performance DSP for Space Applications

NASA Astrophysics Data System (ADS)

Ginosar, Ran; Aviely, Peleg; Liran, Tuvia; Alon, Dov; Dobkin, Reuven; Goldberg, Michael

2013-08-01

RC64, a novel 64-core many-core signal processing chip targets DSP performance of 12.8 GIPS, 100 GOPS and 12.8 single precision GFLOS while dissipating only 3 Watts. RC64 employs advanced DSP cores, a multi-bank shared memory and a hardware scheduler, supports DDR2 memory and communicates over five proprietary 6.4 Gbps channels. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 200 MHz ASIC on Tower 130nm CMOS technology, assembled in hermetically sealed ceramic QFP package and qualified to the highest space standards.

Algorithms for a very high speed universal noiseless coding module

NASA Technical Reports Server (NTRS)

Rice, Robert F.; Yeh, Pen-Shu

1991-01-01

The algorithmic definitions and performance characterizations are presented for a high performance adaptive coding module. Operation of at least one of these (single chip) implementations is expected to exceed 500 Mbits/s under laboratory conditions. Operation of a companion decoding module should operate at up to half the coder's rate. The module incorporates a powerful noiseless coder for Standard Form Data Sources (i.e., sources whose symbols can be represented by uncorrelated non-negative integers where the smaller integers are more likely than the larger ones). Performance close to data entropies can be expected over a Dynamic Range of from 1.5 to 12 to 14 bits/sample (depending on the implementation).

A Data Acquisition System Using Single-Chip Microcomputer

NASA Astrophysics Data System (ADS)

Yonyjiang, Dai; Jingkuan, Gao; Lin, Wan; Mingjia, Pi; Jingda, Nan

1989-12-01

A data acquisition system by single-chip microcomputer was designed. It is suitable to the future devlopment of the miniature tidar signal processing epuipment . The characteristics of frequecy response, SNR, D* and NEP of FM-CW CO2 coherent tidar were discussed.

Hybrid integration of carbon nanotubes in silicon photonic structures

NASA Astrophysics Data System (ADS)

Durán-Valdeiglesias, E.; Zhang, W.; Alonso-Ramos, C.; Le Roux, X.; Serna, S.; Hoang, H. C.; Marris-Morini, D.; Cassan, E.; Intonti, F.; Sarti, F.; Caselli, N.; La China, F.; Gurioli, M.; Balestrieri, M.; Vivien, L.; Filoramo, A.

2017-02-01

Silicon photonics, due to its compatibility with the CMOS platform and unprecedented integration capability, has become the preferred solution for the implementation of next generation optical interconnects to accomplish high efficiency, low energy consumption, low cost and device miniaturization in one single chip. However, it is restricted by silicon itself. Silicon does not have efficient light emission or detection in the telecommunication wavelength range (1.3 μm-1.5 μm) or any electro-optic effect (i.e. Pockels effect). Hence, silicon photonic needs to be complemented with other materials for the realization of optically-active devices, including III-V for lasing and Ge for detection. The very different requirement of these materials results in complex fabrication processes that offset the cost-effectiveness of the Si photonics approach. For this purpose, carbon nanotubes (CNTs) have recently been proposed as an attractive one-dimensional light emitting material. Interestingly, semiconducting single walled CNTs (SWNTs) exhibit room-temperature photo- and electro-luminescence in the near-IR that could be exploited for the implementation of integrated nano-sources. They can also be considered for the realization of photo-detectors and optical modulators, since they rely on intrinsically fast non-linear effects, such as Stark and Kerr effect. All these properties make SWNTs ideal candidates in order to fabricate a large variety of optoelectronic devices, including near-IR sources, modulators and photodetectors on Si photonic platforms. In addition, solution processed SWNTs can be integrated on Si using spin-coating or drop-casting techniques, obviating the need of complex epitaxial growth or chip bonding approaches. Here, we report on our recent progress in the coupling of SWNTs light emission into optical resonators implemented on the silicon-on-insulator (SOI) platform. .

275 C Downhole Microcomputer System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chris Hutchens; Hooi Miin Soo

2008-08-31

An HC11 controller IC and along with serial SRAM and ROM support ICs chip set were developed to support a data acquisition and control for extreme temperature/harsh environment conditions greater than 275 C. The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and signal processing applications and was the logical choice for a downhole controller. This extreme temperature version of the 68HC11 enables new high temperature designs and additionally allows 68HC11-based well logging tools and MWD tools to be upgraded for high temperature operation in deep gas reservoirs, The microcomputer chip consists of the microprocessormore » ALU, a small boot ROM, 4 kbyte data RAM, counter/timer unit, serial peripheral interface (SPI), asynchronous serial interface (SCI), and the A, B, C, and D parallel ports. The chip is code compatible with the single chip mode commercial 68HC11 except for the absence of the analog to digital converter system. To avoid mask programmed internal ROM, a boot program is used to load the microcomputer program from an external mask SPI ROM. A SPI RAM IC completes the chip set and allows data RAM to be added in 4 kbyte increments. The HC11 controller IC chip set is implemented in the Peregrine Semiconductor 0.5 micron Silicon-on-Sapphire (SOS) process using a custom high temperature cell library developed at Oklahoma State University. Yield data is presented for all, the HC11, SPI-RAM and ROM. The lessons learned in this project were extended to the successful development of two high temperature versions of the LEON3 and a companion 8 Kbyte SRAM, a 200 C version for the Navy and a 275 C version for the gas industry.« less

[The joint applications of DNA chips and single nucleotide polymorphisms in forensic science].

PubMed

Bai, Peng; Tian, Li; Zhou, Xue-ping

2005-05-01

DNA chip technology, being a new high-technology, shows its vigorous life and rapid growth. Single Nucleotide Polymorphisms (SNPs) is the most common diversity in the human genome. It provides suitable genetic markers which play a key role in disease linkage study, pharmacogenomics, forensic medicine, population evolution and immigration study. Their advantage such as being analyzed with DNA chips technology, is predicted to play an important role in the field of forensic medicine, especially in paternity test and individual identification. This report mainly reviews the characteristics of DNA chip and SNPs, and their joint applications in the practice of forensic medicine.

Special-purpose computing for dense stellar systems

NASA Astrophysics Data System (ADS)

Makino, Junichiro

2007-08-01

I'll describe the current status of the GRAPE-DR project. The GRAPE-DR is the next-generation hardware for N-body simulation. Unlike the previous GRAPE hardwares, it is programmable SIMD machine with a large number of simple processors integrated into a single chip. The GRAPE-DR chip consists of 512 simple processors and operates at the clock speed of 500 MHz, delivering the theoretical peak speed of 512/226 Gflops (single/double precision). As of August 2006, the first prototype board with the sample chip successfully passed the test we prepared. The full GRAPE-DR system will consist of 4096 chips, reaching the theoretical peak speed of 2 Pflops.

Chips: A Tool for Developing Software Interfaces Interactively.

ERIC Educational Resources Information Center

Cunningham, Robert E.; And Others

This report provides a detailed description of Chips, an interactive tool for developing software employing graphical/computer interfaces on Xerox Lisp machines. It is noted that Chips, which is implemented as a collection of customizable classes, provides the programmer with a rich graphical interface for the creation of rich graphical…

Multifunctional microvalves control by optical illumination on nanoheaters and its application in centrifugal microfluidic devices.

PubMed

Park, Jong-Myeon; Cho, Yoon-Kyoung; Lee, Beom-Seok; Lee, Jeong-Gun; Ko, Christopher

2007-05-01

Valving is critical in microfluidic systems. Among many innovative microvalves used in lab-on-a-chip applications, phase change based microvalves using paraffin wax are particularly attractive for disposable biochip applications because they are simple to implement, cost-effective and biocompatible. However, previously reported paraffin-based valves require embedded microheaters and therefore multi-step operation of many microvalves was a difficult problem. Besides, the operation time was relatively long, 2-10 s. In this paper, we report a unique phase change based microvalve for rapid and versatile operation of multiple microvalves using a single laser diode. The valve is made of nanocomposite materials in which 10 nm-sized iron oxide nanoparticles are dispersed in paraffin wax and used as nanoheaters when excited by laser irradiation. Laser light of relatively weak intensity was able to melt the paraffin wax with the embedded iron oxide nanoparticles, whereas even a very intense laser beam does not melt wax alone. The microvalves are leak-free up to 403.0 +/- 7.6 kPa and the response times to operate both normally closed and normally opened microvalves are less than 0.5 s. Furthermore, a sequential operation of multiple microvalves on a centrifugal microfluidic device using a single laser diode was demonstrated. It showed that the optical control of multiple microvalves is fast, robust, simple to operate, and requires minimal chip space and thus is well suited for fully integrated lab-on-a-chip applications.

FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

NASA Astrophysics Data System (ADS)

Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

2017-06-01

A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

A dynamic magneto-optical trap for atom chips

NASA Astrophysics Data System (ADS)

Rushton, Jo; Roy, Ritayan; Bateman, James; Himsworth, Matt

2016-11-01

We describe a dynamic magneto-optical trap (MOT) suitable for the use with vacuum systems in which optical access is limited to a single window. This technique facilitates the long-standing desire of producing integrated atom chips, many of which are likely to have severely restricted optical access compared with conventional vacuum chambers. This ‘switching-MOT’ relies on the synchronized pulsing of optical and magnetic fields at audio frequencies. The trap’s beam geometry is obtained using a planar mirror surface, and does not require a patterned substrate or bulky optics inside the vacuum chamber. Central to the design is a novel magnetic field geometry that requires no external quadrupole or bias coils which leads toward a very compact system. We have implemented the trap for 85Rb and shown that it is capable of capturing 2 million atoms and directly cooling below the Doppler temperature.

Quantitative detection of liver-relevant biomarkers by SERS-immunolabeled gold nanoparticles

NASA Astrophysics Data System (ADS)

Payne, William Mark

Lab-on-a-chip technology has the potential to rapidly change the way experiments are conducted in a variety of fields ranging from medicine to environmental science. Specifically, sensors, detectors, and monitoring devices are increasingly being miniaturized to perform many experiments or measurements on a single chip. In this research, we develop an immunolabeled gold nanoparticle complex capable of detecting liver organoid biomarkers intended for use in a microfluidic device. Human Serum Albumin (HSA) and alpha-Glutathione S-Transferase (alpha-GST) are liver biomarkers that indicate liver health and damage respectively. Herein we demonstrate detection of the liver organoid biomarkers at nanomolar concentrations. Through plasmonic coupling induced by aggregation in the presence of analyte, the SERS signal obtained from the nanoparticles is dramatically increased. Furthermore, detection is demonstrated in a simple fluidic device to show the feasibility of implementing an optimized SERS-immunolabeled nanoparticle for translational application.

CMOS imager for pointing and tracking applications

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Digitally Controllable Current Amplifier and Current Conveyors in Practical Application of Controllable Frequency Filter

NASA Astrophysics Data System (ADS)

Polak, Josef; Jerabek, Jan; Langhammer, Lukas; Sotner, Roman; Dvorak, Jan; Panek, David

2016-07-01

This paper presents the simulations results in comparison with the measured results of the practical realization of the multifunctional second order frequency filter with a Digitally Adjustable Current Amplifier (DACA) and two Dual-Output Controllable Current Conveyors (CCCII +/-). This filter is designed for use in current mode. The filter was designed of the single input multiple outputs (SIMO) type, therefore it has only one input and three outputs with individual filtering functions. DACA element used in a newly proposed circuit is present in form of an integrated chip and the current conveyors are implemented using the Universal Current Conveyor (UCC) chip with designation UCC-N1B. Proposed frequency filter enables independent control of the pole frequency using parameters of two current conveyors and also independent control of the quality factor by change of a current gain of DACA.

Powerful timing generator using mono-chip timers: An application to pulsed nuclear magnetic resonance

NASA Astrophysics Data System (ADS)

Saint-Jalmes, Hervé; Barjhoux, Yves

1982-01-01

We present a 10 line-7 MHz timing generator built on a single board around two LSI timer chips interfaced to a 16-bit microcomputer. Once programmed from the host computer, this device is able to generate elaborate logic sequences on its 10 output lines without further interventions from the CPU. Powerful architecture introduces new possibilities over conventional memory-based timing simulators and word generators. Loop control on a given sequence of events, loop nesting, and various logic combinations can easily be implemented through a software interface, using a symbolic command language. Typical applications of such a device range from development, emulation, and test of integrated circuits, circuit boards, and communication systems to pulse-controlled instrumentation (radar, ultrasonic systems). A particular application to a pulsed Nuclear Magnetic Resonance (NMR) spectrometer is presented, along with customization of the device for generating four-channel radio-frequency pulses and the necessary sequence for subsequent data acquisition.

CMOS capacitive biosensors for highly sensitive biosensing applications.

PubMed

Chang, An-Yu; Lu, Michael S-C

2013-01-01

Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

Design of a digital, ultra-broadband electro-optic switch for reconfigurable optical networks-on-chip.

PubMed

Van Campenhout, Joris; Green, William M J; Vlasov, Yurii A

2009-12-21

We present a novel design for a noise-tolerant, ultra-broadband electro-optic switch, based on a Mach-Zehnder lattice (MZL) interferometer. We analyze the switch performance through rigorous optical simulations, for devices implemented in silicon-on-insulator with carrier-injection-based phase shifters. We show that such a MZL switch can be designed to have a step-like switching response, resulting in improved tolerance to drive-voltage noise and temperature variations as compared to a single-stage Mach-Zehnder switch. Furthermore, we show that degradation in switching crosstalk and insertion loss due to free-carrier absorption can be largely overcome by a MZL switch design. Finally, MZL switches can be designed for having an ultra-wide, temperature-insensitive optical bandwidth of more than 250 nm. The proposed device shows good potential as a broadband optical switch in reconfigurable optical networks-on-chip.

Implementation of the State Children's Health Insurance Program: Outreach, Enrollment, and Provider Participation in Rural Areas.

ERIC Educational Resources Information Center

Dunbar, Jennifer L.; Sloane, Harvey I.; Mueller, Curt D.

The state Children's Health Insurance Program (CHIP) funds state programs to help low-income, uninsured children overcome financial barriers to medical care. Previous research found that rural children were more likely to be uninsured than urban children. This report examines the implementation of CHIP and related outreach, enrollment, and…

Two-step single slope/SAR ADC with error correction for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Amira, Abbes; Amor Benammar, Mohieddine; He, Debiao; Zhao, Xiaojin

2014-01-01

Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μ m CMOS technology. The chip area of the proposed ADC is 7 μ m × 500 μ m. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k  μ m(2) · cycles/sample.

A Facile Droplet-Chip-Time-Resolved Inductively Coupled Plasma Mass Spectrometry Online System for Determination of Zinc in Single Cell.

PubMed

Wang, Han; Chen, Beibei; He, Man; Hu, Bin

2017-05-02

Single cell analysis is a significant research field in recent years reflecting the heterogeneity of cells in a biological system. In this work, a facile droplet chip was fabricated and online combined with time-resolved inductively coupled plasma mass spectrometry (ICPMS) via a microflow nebulizer for the determination of zinc in single HepG2 cells. On the focusing geometric designed PDMS microfluidic chip, the aqueous cell suspension was ejected and divided by hexanol to generate droplets. The droplets encapsulated single cells remain intact during the transportation into ICP for subsequent detection. Under the optimized conditions, the frequency of droplet generation is 3-6 × 10 6 min -1 , and the injected cell number is 2500 min -1 , which can ensure the single cell encapsulation. ZnO nanoparticles (NPs) were used for the quantification of zinc in single cells, and the accuracy was validated by conventional acid digestion-ICPMS method. The ZnO NPs incubated HepG2 cells were analyzed as model samples, and the results exhibit the heterogeneity of HepG2 cells in the uptake/adsorption of ZnO NPs. The developed online droplet-chip-ICPMS analysis system achieves stable single cell encapsulation and has high throughput for single cell analysis. It has the potential in monitoring the content as well as distribution of trace elements/NPs at the single cell level.

Built-in self-repair of VLSI memories employing neural nets

NASA Astrophysics Data System (ADS)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

A configurable and low-power mixed signal SoC for portable ECG monitoring applications.

PubMed

Kim, Hyejung; Kim, Sunyoung; Van Helleputte, Nick; Artes, Antonio; Konijnenburg, Mario; Huisken, Jos; Van Hoof, Chris; Yazicioglu, Refet Firat

2014-04-01

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

NASA Astrophysics Data System (ADS)

Park, Chester Sungchung; Park, Sungkyung

2018-07-01

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.

Compact Receiver Front Ends for Submillimeter-Wave Applications

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

A self-testing dynamic RAM chip

NASA Astrophysics Data System (ADS)

You, Y.; Hayes, J. P.

1985-02-01

A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts: on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64 K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.

All over the Map: A Progress Report on the State Children's Health Insurance Program (CHIP).

ERIC Educational Resources Information Center

Edmunds, Margo; Teitelbaum, Martha; Gleason, Cassy

The State Children's Health Insurance Program (CHIP) was designed in 1997 to support working families by providing affordable, quality health coverage for their children in an efficient, effective, and coordinated way. This report examines the progress made in implementing CHIP nationwide. Information sources included the following: (1) federal…

European Seminar on Neural Computing

DTIC Science & Technology

1988-08-31

elements can be fabricated on a single chip . Two specific oriented language (for example, SMALLTALK or cellular arrays, namely, the programmable systolic... chip POOL) the basic concepts are: objects are viewed as (Fisher, 1983) and the connection machine (Treleaven, active, they may contain state, and...flow computer the availability of 1. Programmable Systolic Chip . Programmable Sys- input operands triggers the execution of the instruction tolic Chips

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

PubMed Central

Valente, Virgilio; Demosthenous, Andreas

2016-01-01

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)

PubMed Central

Zhang, Xiang; Chen, Zhangwei

2013-01-01

This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users' configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels. PMID:23459385

A Charge Sensitive Pre-Amplifier for Smart Point-of-Care Devices Employing Polymer Based Lab-on-a-Chip

DOE PAGES

Wang, Hanfeng; Britton, Charles; Quaiyum, Farhan; ...

2018-01-01

With increasing emphasis on implantable and portable medical devices, low-power, small-chip-area sensor readout system realized in lab-on-a-chip (LOC) platform is gaining more and more importance these days. The main building blocks of the LOC system include a front-end transducer that generates an electrical signal in response to the presence of an analyte of interest, signal processing electronics to process the signal to comply with a specific transmission protocol and a low-power transmitter, all realized in a single integrated circuit platform. Low power consumption and compactness of the components are essential requirements of the LOC system. This paper presents a novelmore » charge sensitive pre-amplifier developed in a standard 180-nm CMOS process suitable for implementing in an LOC platform. The pre-amplifier converts the charge generated by a pyroelectric transducer into a voltage signal, which provides a measurement of the temperature variation in biological fluids. The proposed design is capable of providing 0.8-mV/pC gain while consuming only 2.1 μW of power. Finally, the pre-amplifier composed of integrated components occupies an area of 0.038 mm 2.« less

Continuously monitoring the parity of superconducting qubits in a 2D cQED architecture

NASA Astrophysics Data System (ADS)

Blok, Machiel; Flurin, Emmanuel; Livingston, William; Colless, James; Dove, Allison; Siddiqi, Irfan

Continuous measurements of joint qubit properties such as their parity can reveal insight into the collapse dynamics of entangled states and are a prerequisite for implementing continuous quantum error correction. Here it is crucial that the measurement collects no information other than the parity to avoid measurement induced dephasing. In a cQED architecture, a full-parity measurement can be implemented by strongly coupling two transmon qubits to a single high-Q planar resonator (χ >> κ). We will discuss the experimental implementation of this on-chip technique and the prospects to extend it to more qubits. This will allow us to monitor, in real-time, the projection into multi-partite entangled states and continuously detect errors on a logical qubit encoded in an entangled subspace. This work was supported by Army Research Office.

Observation of entanglement between a quantum dot spin and a single photon.

PubMed

Gao, W B; Fallahi, P; Togan, E; Miguel-Sanchez, J; Imamoglu, A

2012-11-15

Entanglement has a central role in fundamental tests of quantum mechanics as well as in the burgeoning field of quantum information processing. Particularly in the context of quantum networks and communication, a main challenge is the efficient generation of entanglement between stationary (spin) and propagating (photon) quantum bits. Here we report the observation of quantum entanglement between a semiconductor quantum dot spin and the colour of a propagating optical photon. The demonstration of entanglement relies on the use of fast, single-photon detection, which allows us to project the photon into a superposition of red and blue frequency components. Our results extend the previous demonstrations of single-spin/single-photon entanglement in trapped ions, neutral atoms and nitrogen-vacancy centres to the domain of artificial atoms in semiconductor nanostructures that allow for on-chip integration of electronic and photonic elements. As a result of its fast optical transitions and favourable selection rules, the scheme we implement could in principle generate nearly deterministic entangled spin-photon pairs at a rate determined ultimately by the high spontaneous emission rate. Our observation constitutes a first step towards implementation of a quantum network with nodes consisting of semiconductor spin quantum bits.

Large-Constraint-Length, Fast Viterbi Decoder

NASA Technical Reports Server (NTRS)

Collins, O.; Dolinar, S.; Hsu, In-Shek; Pollara, F.; Olson, E.; Statman, J.; Zimmerman, G.

1990-01-01

Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

A label-free, fluorescence based assay for microarray

NASA Astrophysics Data System (ADS)

Niu, Sanjun

DNA chip technology has drawn tremendous attention since it emerged in the mid 90's as a method that expedites gene sequencing by over 100-fold. DNA chip, also called DNA microarray, is a combinatorial technology in which different single-stranded DNA (ssDNA) molecules of known sequences are immobilized at specific spots. The immobilized ssDNA strands are called probes. In application, the chip is exposed to a solution containing ssDNA of unknown sequence, called targets, which are labeled with fluorescent dyes. Due to specific molecular recognition among the base pairs in the DNA, the binding or hybridization occurs only when the probe and target sequences are complementary. The nucleotide sequence of the target is determined by imaging the fluorescence from the spots. The uncertainty of background in signal detection and statistical error in data analysis, primarily due to the error in the DNA amplification process and statistical distribution of the tags in the target DNA, have become the fundamental barriers in bringing the technology into application for clinical diagnostics. Furthermore, the dye and tagging process are expensive, making the cost of DNA chips inhibitive for clinical testing. These limitations and challenges make it difficult to implement DNA chip methods as a diagnostic tool in a pathology laboratory. The objective of this dissertation research is to provide an alternative approach that will address the above challenges. In this research, a label-free assay is designed and studied. Polystyrene (PS), a commonly used polymeric material, serves as the fluorescence agent. Probe ssDNA is covalently immobilized on polystyrene thin film that is supported by a reflecting substrate. When this chip is exposed to excitation light, fluorescence light intensity from PS is detected as the signal. Since the optical constants and conformations of ssDNA and dsDNA (double stranded DNA) are different, the measured fluorescence from PS changes for the same intensity of excitation light. The fluorescence contrast is used to quantify the amount of probe-target hybridization. A mathematical model that considers multiple reflections and scattering is developed to explain the mechanism of the fluorescence contrast which depends on the thickness of the PS film. Scattering is the dominant factor that contributes to the contrast. The potential of this assay to detect single nucleotide polymorphism is also tested.

An on-chip coupled resonator optical waveguide single-photon buffer

PubMed Central

Takesue, Hiroki; Matsuda, Nobuyuki; Kuramochi, Eiichi; Munro, William J.; Notomi, Masaya

2013-01-01

Integrated quantum optical circuits are now seen as one of the most promising approaches with which to realize single-photon quantum information processing. Many of the core elements for such circuits have been realized, including sources, gates and detectors. However, a significant missing function necessary for photonic quantum information processing on-chip is a buffer, where single photons are stored for a short period of time to facilitate circuit synchronization. Here we report an on-chip single-photon buffer based on coupled resonator optical waveguides (CROW) consisting of 400 high-Q photonic crystal line-defect nanocavities. By using the CROW, a pulsed single photon is successfully buffered for 150 ps with 50-ps tunability while maintaining its non-classical properties. Furthermore, we show that our buffer preserves entanglement by storing and retrieving one photon from a time-bin entangled state. This is a significant step towards an all-optical integrated quantum information processor. PMID:24217422

On-chip low loss heralded source of pure single photons.

PubMed

Spring, Justin B; Salter, Patrick S; Metcalf, Benjamin J; Humphreys, Peter C; Moore, Merritt; Thomas-Peter, Nicholas; Barbieri, Marco; Jin, Xian-Min; Langford, Nathan K; Kolthammer, W Steven; Booth, Martin J; Walmsley, Ian A

2013-06-03

A key obstacle to the experimental realization of many photonic quantum-enhanced technologies is the lack of low-loss sources of single photons in pure quantum states. We demonstrate a promising solution: generation of heralded single photons in a silica photonic chip by spontaneous four-wave mixing. A heralding efficiency of 40%, corresponding to a preparation efficiency of 80% accounting for detector performance, is achieved due to efficient coupling of the low-loss source to optical fibers. A single photon purity of 0.86 is measured from the source number statistics without narrow spectral filtering, and confirmed by direct measurement of the joint spectral intensity. We calculate that similar high-heralded-purity output can be obtained from visible to telecom spectral regions using this approach. On-chip silica sources can have immediate application in a wide range of single-photon quantum optics applications which employ silica photonics.

On-Chip Single-Plasmon Nanocircuit Driven by a Self-Assembled Quantum Dot.

PubMed

Wu, Xiaofei; Jiang, Ping; Razinskas, Gary; Huo, Yongheng; Zhang, Hongyi; Kamp, Martin; Rastelli, Armando; Schmidt, Oliver G; Hecht, Bert; Lindfors, Klas; Lippitz, Markus

2017-07-12

Quantum photonics holds great promise for future technologies such as secure communication, quantum computation, quantum simulation, and quantum metrology. An outstanding challenge for quantum photonics is to develop scalable miniature circuits that integrate single-photon sources, linear optical components, and detectors on a chip. Plasmonic nanocircuits will play essential roles in such developments. However, for quantum plasmonic circuits, integration of stable, bright, and narrow-band single photon sources in the structure has so far not been reported. Here we present a plasmonic nanocircuit driven by a self-assembled GaAs quantum dot. Through a planar dielectric-plasmonic hybrid waveguide, the quantum dot efficiently excites narrow-band single plasmons that are guided in a two-wire transmission line until they are converted into single photons by an optical antenna. Our work demonstrates the feasibility of fully on-chip plasmonic nanocircuits for quantum optical applications.

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor

PubMed Central

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-01-01

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation. PMID:27983714

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

PubMed

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-12-15

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.

Application of the ANNA neural network chip to high-speed character recognition.

PubMed

Sackinger, E; Boser, B E; Bromley, J; Lecun, Y; Jackel, L D

1992-01-01

A neural network with 136000 connections for recognition of handwritten digits has been implemented using a mixed analog/digital neural network chip. The neural network chip is capable of processing 1000 characters/s. The recognition system has essentially the same rate (5%) as a simulation of the network with 32-b floating-point precision.

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip.

PubMed

Huys, Roeland; Braeken, Dries; Jans, Danny; Stassen, Andim; Collaert, Nadine; Wouters, Jan; Loo, Josine; Severi, Simone; Vleugels, Frank; Callewaert, Geert; Verstreken, Kris; Bartic, Carmen; Eberle, Wolfgang

2012-04-07

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks. This journal is © The Royal Society of Chemistry 2012

WFC3/UVIS External CTE Monitor: Single-Chip CTE Measurements

NASA Astrophysics Data System (ADS)

Gosmeyer, C. M.; Baggett, S.

2016-12-01

We present the first results of single-chip measurements of charge transfer efficiency (CTE) in the UVIS channel of the Hubble Space Telescope Wide Field Camera 3 (HST/WFC3). This test was performed in Cycle 20 in two visits. In the first visit a field in the star cluster NGC 6583 was observed. In a second visit, the telescope returned to the field, but rotated by 180 degrees and with a shift in pointing that allowed the same stars to be imaged, near and far from the amplifiers, on the same chip of the two-chip UVIS field of-view. This dataset enables a measurement of CTE loss on each separate chip. The current CTE monitor measures CTE loss as an average of the two chips because it dithers by a chip-height to obtain observations of the same sources near and far from the amplifiers, instead of the more difficult to-schedule 180-degree rotation. We find that CTE loss is worse on Chip 1 than on Chip 2 across all cases for which we had data: short and long exposures and w! ith and without the pixel-based CTE correction. In the best case, for long exposures with the CTE correction applied, the max difference between the two chip's flux losses is 3%/2048 pixels. This case should apply for most science observations where the background is 12 e-/pixel. In the worst case of low-background short exposures, e.g. those without post-flash, the max difference between the two chips is 17% flux loss/2048 pixels. Uncertainties are <0.01% flux loss/2048 pixels. Because of the two chips' different CTE loss rates, we will consider adding this test as part of the routine yearly monitor and creating a chip-specific CTE correction software.

Single cell HaloChip assay on paper for point-of-care diagnosis.

PubMed

Ma, Liyuan; Qiao, Yong; Jones, Ross; Singh, Narendra; Su, Ming

2016-11-01

This article describes a paper-based low cost single cell HaloChip assay that can be used to assess drug- and radiation-induced DNA damage at point-of-care. Printing ink on paper effectively blocks fluorescence of paper materials, provides high affinity to charged polyelectrolytes, and prevents penetration of water in paper. After exposure to drug or ionizing radiation, cells are patterned on paper to create discrete and ordered single cell arrays, embedded inside an agarose gel, lysed with alkaline solution to allow damaged DNA fragments to diffuse out of nucleus cores, and form diffusing halos in the gel matrix. After staining DNA with a fluorescent dye, characteristic halos formed around cells, and the level of DNA damage can be quantified by determining sizes of halos and nucleus with an image processing program based on MATLAB. With its low fabrication cost and easy operation, this HaloChip on paper platform will be attractive to rapidly and accurately determine DNA damage for point-of-care evaluation of drug efficacy and radiation condition. Graphical Abstract Single cell HaloChip on paper.

VLSI research

NASA Astrophysics Data System (ADS)

Brodersen, R. W.

1984-04-01

A scaled version of the RISC II chip has been fabricated and tested and these new chips have a cycle time that would outperform a VAX 11/780 by about a factor of two on compiled integer C programs. The architectural work on a RISC chip designed for a Smalltalk implementation has been completed. This chip, called SOAR (Smalltalk On a RISC), should run program s4-15 times faster than the Xerox 1100 (Dolphin), a TTL minicomputer, and about as fast as the Xerox 1132 (Dorado), a $100,000 ECL minicomputer. The 1983 VLSI tools tape has been converted for use under the latest UNIX release (4.2). The Magic (formerly called Caddy) layout system will be a unified set of highly automated tools that cover all aspects of the layout process, including stretching, compaction, tiling and routing. A multiple window package and design rule checker for this system have just been completed and compaction and stretching are partially implemented. New slope-based timing models for the Crystal timing analyzer are now fully implemented and in regular use. In an accuracy test using a dozen critical paths from the RISC II processor and cache chips it was found that Crystal's estimates were within 5-10% of SPICE's estimates, while being a factor of 10,000 times faster.

Digital algorithms for parallel pipelined single-detector homodyne fringe counting in laser interferometry

NASA Astrophysics Data System (ADS)

Rerucha, Simon; Sarbort, Martin; Hola, Miroslava; Cizek, Martin; Hucl, Vaclav; Cip, Ondrej; Lazar, Josef

2016-12-01

The homodyne detection with only a single detector represents a promising approach in the interferometric application which enables a significant reduction of the optical system complexity while preserving the fundamental resolution and dynamic range of the single frequency laser interferometers. We present the design, implementation and analysis of algorithmic methods for computational processing of the single-detector interference signal based on parallel pipelined processing suitable for real time implementation on a programmable hardware platform (e.g. the FPGA - Field Programmable Gate Arrays or the SoC - System on Chip). The algorithmic methods incorporate (a) the single detector signal (sine) scaling, filtering, demodulations and mixing necessary for the second (cosine) quadrature signal reconstruction followed by a conic section projection in Cartesian plane as well as (a) the phase unwrapping together with the goniometric and linear transformations needed for the scale linearization and periodic error correction. The digital computing scheme was designed for bandwidths up to tens of megahertz which would allow to measure the displacements at the velocities around half metre per second. The algorithmic methods were tested in real-time operation with a PC-based reference implementation that employed the advantage pipelined processing by balancing the computational load among multiple processor cores. The results indicate that the algorithmic methods are suitable for a wide range of applications [3] and that they are bringing the fringe counting interferometry closer to the industrial applications due to their optical setup simplicity and robustness, computational stability, scalability and also a cost-effectiveness.

FISH-in-CHIPS: A Microfluidic Platform for Molecular Typing of Cancer Cells.

PubMed

Perez-Toralla, Karla; Mottet, Guillaume; Tulukcuoglu-Guneri, Ezgi; Champ, Jérôme; Bidard, François-Clément; Pierga, Jean-Yves; Klijanienko, Jerzy; Draskovic, Irena; Malaquin, Laurent; Viovy, Jean-Louis; Descroix, Stéphanie

2017-01-01

Microfluidics offer powerful tools for the control, manipulation, and analysis of cells, in particular for the assessment of cell malignancy or the study of cell subpopulations. However, implementing complex biological protocols on chip remains a challenge. Sample preparation is often performed off chip using multiple manually performed steps, and protocols usually include different dehydration and drying steps that are not always compatible with a microfluidic format.Here, we report the implementation of a Fluorescence in situ Hybridization (FISH) protocol for the molecular typing of cancer cells in a simple and low-cost device. The geometry of the chip allows integrating the sample preparation steps to efficiently assess the genomic content of individual cells using a minute amount of sample. The FISH protocol can be fully automated, thus enabling its use in routine clinical practice.

Medicaid and Children's Health Insurance Programs: Eligibility Notices, Fair Hearing and Appeal Processes for Medicaid and Other Provisions Related to Eligibility and Enrollment for Medicaid and CHIP. Final rule.

PubMed

2016-11-30

This final rule implements provisions of the Affordable Care Act that expand access to health coverage through improvements in Medicaid and coordination between Medicaid, CHIP, and Exchanges. This rule finalizes most of the remaining provisions from the "Medicaid, Children's Health Insurance Programs, and Exchanges: Essential Health Benefits in Alternative Benefit Plans, Eligibility Notices, Fair Hearing and Appeal Processes for Medicaid and Exchange Eligibility Appeals and Other Provisions Related to Eligibility and Enrollment for Exchanges, Medicaid and CHIP, and Medicaid Premiums and Cost Sharing; Proposed Rule" that we published in the January 22, 2013, Federal Register. This final rule continues our efforts to assist states in implementing Medicaid and CHIP eligibility, appeals, and enrollment changes required by the Affordable Care Act.

InGaAs/InP SPAD photon-counting module with auto-calibrated gate-width generation and remote control

NASA Astrophysics Data System (ADS)

Tosi, Alberto; Ruggeri, Alessandro; Bahgat Shehata, Andrea; Della Frera, Adriano; Scarcella, Carmelo; Tisa, Simone; Giudice, Andrea

2013-01-01

We present a photon-counting module based on InGaAs/InP SPAD (Single-Photon Avalanche Diode) for detecting single photons up to 1.7 μm. The module exploits a novel architecture for generating and calibrating the gate width, along with other functions (such as module supervision, counting and processing of detected photons, etc.). The gate width, i.e. the time interval when the SPAD is ON, is user-programmable in the range from 500 ps to 1.5 μs, by means of two different delay generation methods implemented with an FPGA (Field-Programmable Gate Array). In order to compensate chip-to-chip delay variation, an auto-calibration circuit picks out a combination of delays in order to match at best the selected gate width. The InGaAs/InP module accepts asynchronous and aperiodic signals and introduces very low timing jitter. Moreover the photon counting module provides other new features like a microprocessor for system supervision, a touch-screen for local user interface, and an Ethernet link for smart remote control. Thanks to the fullyprogrammable and configurable architecture, the overall instrument provides high system flexibility and can easily match all requirements set by many different applications requiring single photon-level sensitivity in the near infrared with very low photon timing jitter.

Nanoliter-Scale Oil-Air-Droplet Chip-Based Single Cell Proteomic Analysis.

PubMed

Li, Zi-Yi; Huang, Min; Wang, Xiu-Kun; Zhu, Ying; Li, Jin-Song; Wong, Catherine C L; Fang, Qun

2018-04-17

Single cell proteomic analysis provides crucial information on cellular heterogeneity in biological systems. Herein, we describe a nanoliter-scale oil-air-droplet (OAD) chip for achieving multistep complex sample pretreatment and injection for single cell proteomic analysis in the shotgun mode. By using miniaturized stationary droplet microreaction and manipulation techniques, our system allows all sample pretreatment and injection procedures to be performed in a nanoliter-scale droplet with minimum sample loss and a high sample injection efficiency (>99%), thus substantially increasing the analytical sensitivity for single cell samples. We applied the present system in the proteomic analysis of 100 ± 10, 50 ± 5, 10, and 1 HeLa cell(s), and protein IDs of 1360, 612, 192, and 51 were identified, respectively. The OAD chip-based system was further applied in single mouse oocyte analysis, with 355 protein IDs identified at the single oocyte level, which demonstrated its special advantages of high enrichment of sequence coverage, hydrophobic proteins, and enzymatic digestion efficiency over the traditional in-tube system.

Pyrolysis of ground pine chip and ground pellet particles

DOE PAGES

Rezaei, Hamid; Yazdanpanah, Fahimeh; Lim, C. Jim; ...

2016-08-04

In addition to particle size, biomass density influences heat and mass transfer rates during the thermal treatment processes. In this research, thermal behaviour of ground pine chip particles and ground pine pellet particles in the range of 0.25–5 mm was investigated. A single particle from ground pellets was almost 3 to 4 times denser than a single particle from ground chips at a similar size and volume of particle. Temperature was ramped up from room temperature (~25 °C) to 600 °C with heating rates of 10, 20, 30, and 50 °C/min. Pellet particles took 25–88 % longer time to drymore » than the chip particles. Microscopic examination of 3 mm and larger chip particles showed cracks during drying. No cracks were observed for pellet particles. The mass loss due to treatment at temperatures higher than 200 °C was about 80% both for chip and pellet particles. It took 4 min for chip and pellet particles to lose roughly 63% of their dry mass at a heating rate of 50 °C/min. The SEM structural analysis showed enlarged pores and cracks in cell walls of the pyrolyzed wood chips. As a result, these pores were not observed in pyrolyzed pellet particles.« less

Evolvable Smartphone-Based Platforms for Point-of-Care In-Vitro Diagnostics Applications.

PubMed

Patou, François; AlZahra'a Alatraktchi, Fatima; Kjægaard, Claus; Dimaki, Maria; Madsen, Jan; Svendsen, Winnie E

2016-09-03

The association of smart mobile devices and lab-on-chip technologies offers unprecedented opportunities for the emergence of direct-to-consumer in vitro medical diagnostics applications. Despite their clear transformative potential, obstacles remain to the large-scale disruption and long-lasting success of these systems in the consumer market. For instance, the increasing level of complexity of instrumented lab-on-chip devices, coupled to the sporadic nature of point-of-care testing, threatens the viability of a business model mainly relying on disposable/consumable lab-on-chips. We argued recently that system evolvability, defined as the design characteristic that facilitates more manageable transitions between system generations via the modification of an inherited design, can help remedy these limitations. In this paper, we discuss how platform-based design can constitute a formal entry point to the design and implementation of evolvable smart device/lab-on-chip systems. We present both a hardware/software design framework and the implementation details of a platform prototype enabling at this stage the interfacing of several lab-on-chip variants relying on current- or impedance-based biosensors. Our findings suggest that several change-enabling mechanisms implemented in the higher abstraction software layers of the system can promote evolvability, together with the design of change-absorbing hardware/software interfaces. Our platform architecture is based on a mobile software application programming interface coupled to a modular hardware accessory. It allows the specification of lab-on-chip operation and post-analytic functions at the mobile software layer. We demonstrate its potential by operating a simple lab-on-chip to carry out the detection of dopamine using various electroanalytical methods.

Evolvable Smartphone-Based Platforms for Point-of-Care In-Vitro Diagnostics Applications

PubMed Central

Patou, François; AlZahra’a Alatraktchi, Fatima; Kjægaard, Claus; Dimaki, Maria; Madsen, Jan; Svendsen, Winnie E.

2016-01-01

The association of smart mobile devices and lab-on-chip technologies offers unprecedented opportunities for the emergence of direct-to-consumer in vitro medical diagnostics applications. Despite their clear transformative potential, obstacles remain to the large-scale disruption and long-lasting success of these systems in the consumer market. For instance, the increasing level of complexity of instrumented lab-on-chip devices, coupled to the sporadic nature of point-of-care testing, threatens the viability of a business model mainly relying on disposable/consumable lab-on-chips. We argued recently that system evolvability, defined as the design characteristic that facilitates more manageable transitions between system generations via the modification of an inherited design, can help remedy these limitations. In this paper, we discuss how platform-based design can constitute a formal entry point to the design and implementation of evolvable smart device/lab-on-chip systems. We present both a hardware/software design framework and the implementation details of a platform prototype enabling at this stage the interfacing of several lab-on-chip variants relying on current- or impedance-based biosensors. Our findings suggest that several change-enabling mechanisms implemented in the higher abstraction software layers of the system can promote evolvability, together with the design of change-absorbing hardware/software interfaces. Our platform architecture is based on a mobile software application programming interface coupled to a modular hardware accessory. It allows the specification of lab-on-chip operation and post-analytic functions at the mobile software layer. We demonstrate its potential by operating a simple lab-on-chip to carry out the detection of dopamine using various electroanalytical methods. PMID:27598208

Hardware architecture design of a fast global motion estimation method

NASA Astrophysics Data System (ADS)

Liang, Chaobing; Sang, Hongshi; Shen, Xubang

2015-12-01

VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

Design of Water Temperature Control System Based on Single Chip Microcomputer

NASA Astrophysics Data System (ADS)

Tan, Hanhong; Yan, Qiyan

2017-12-01

In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

An Algorithm of an X-ray Hit Allocation to a Single Pixel in a Cluster and Its Test-Circuit Implementation

DOE PAGES

Deptuch, Grzegorz W.; Fahim, Farah; Grybos, Pawel; ...

2017-06-28

An on-chip implementable algorithm for allocation of an X-ray photon imprint, called a hit, to a single pixel in the presence of charge sharing in a highly segmented pixel detector is described. Its proof-of-principle implementation is also given supported by the results of tests using a highly collimated X-ray photon beam from a synchrotron source. The algorithm handles asynchronous arrivals of X-ray photons. Activation of groups of pixels, comparisons of peak amplitudes of pulses within an active neighborhood and finally latching of the results of these comparisons constitute the three procedural steps of the algorithm. A grouping of pixels tomore » one virtual pixel, that recovers composite signals and event driven strobes, to control comparisons of fractional signals between neighboring pixels are the actuators of the algorithm. The circuitry necessary to implement the algorithm requires an extensive inter-pixel connection grid of analog and digital signals, that are exchanged between pixels. A test-circuit implementation of the algorithm was achieved with a small array of 32 × 32 pixels and the device was exposed to an 8 keV highly collimated to a diameter of 3-μm X-ray beam. Furthermore, the results of these tests are given in this paper assessing physical implementation of the algorithm.« less

Trucking Characteristics for an In-woods Biomass Chipping Operation

Treesearch

J. D. Thompson; J. Klepac; W. and Sprinkle

2012-01-01

A study was implemented to evaluate the transportation of woody biomass. This paper reports on the results of transporting wood chips produced in the field from transpirationally dried trees. For the study, a stand of timber was felled and allowed to dry in the field for approximately six weeks. The timber was then chipped in the woods and transported to market. In...

Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection

NASA Astrophysics Data System (ADS)

Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

2015-02-01

This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50  ×  55 µm (width × height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75 °C) bonding adhesive and as etch mask during 300 µm deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10 µm size could be detected with a mean signal amplitude of 0.39  ±  0.13 V (n=439 ) at particle velocities of up to 9.6 mm s-1 inside the chip.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

NASA Technical Reports Server (NTRS)

Bar-Cohen, Avram; Robinson, Franklin L.; Deisenroth, David C.

2018-01-01

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

Micromagnet arrays for on-chip focusing, switching, and separation of superparamagnetic beads and single cells.

PubMed

Rampini, S; Kilinc, D; Li, P; Monteil, C; Gandhi, D; Lee, G U

2015-08-21

Nonlinear magnetophoresis (NLM) is a novel approach for on-chip transport and separation of superparamagnetic (SPM) beads, based on a travelling magnetic field wave generated by the combination of a micromagnet array (MMA) and an applied rotating magnetic field. Here, we present two novel MMA designs that allow SPM beads to be focused, sorted, and separated on-chip. Converging MMAs were used to rapidly collect the SPM beads from a large region of the chip and focus them into synchronised lines. We characterise the collection efficiency of the devices and demonstrate that they can facilitate on-chip analysis of populations of SPM beads using a single-point optical detector. The diverging MMAs were used to control the transport of the beads and to separate them based on their size. The separation efficiency of these devices was determined by the orientation of the magnetisation of the micromagnets relative to the external magnetic field and the size of the beads and relative to that of micromagnets. By controlling these parameters and the rotation of the external magnetic field we demonstrated the controlled transport of SPM bead-labelled single MDA-MB-231 cells. The use of these novel MMAs promises to allow magnetically-labelled cells to be efficiently isolated and then manipulated on-chip for analysis with high-resolution chemical and physical techniques.

Nanohole Array-directed Trapping of Mammalian Mitochondria Enabling Single Organelle Analysis

PubMed Central

Kumar, Shailabh; Wolken, Gregory G.; Wittenberg, Nathan J.; Arriaga, Edgar A.; Oh, Sang-Hyun

2016-01-01

We present periodic nanohole arrays fabricated in free-standing metal-coated nitride films as a platform for trapping and analyzing single organelles. When a microliter-scale droplet containing mitochondria is dispensed above the nanohole array, the combination of evaporation and capillary flow directs individual mitochondria to the nanoholes. Mammalian mitochondria arrays were rapidly formed on chip using this technique without any surface modification steps, microfluidic interconnects or external power sources. The trapped mitochondria were depolarized on chip using an ionophore with results showing that the organelle viability and behavior were preserved during the on-chip assembly process. Fluorescence signal related to mitochondrial membrane potential was obtained from single mitochondria trapped in individual nanoholes revealing statistical differences between the behavior of polarized vs. depolarized mammalian mitochondria. This technique provides a fast and stable route for droplet-based directed localization of organelles-on-a-chip with minimal limitations and complexity, as well as promotes integration with other optical or electrochemical detection techniques. PMID:26593329

Label-free isolation of a prostate cancer cell among blood cells and the single-cell measurement of drug accumulation using an integrated microfluidic chip.

PubMed

Khamenehfar, A; Beischlag, T V; Russell, P J; Ling, M T P; Nelson, C; Li, P C H

2015-11-01

Circulating tumor cells (CTCs) are found in the blood of patients with cancer. Although these cells are rare, they can provide useful information for chemotherapy. However, isolation of these rare cells from blood is technically challenging because they are small in numbers. An integrated microfluidic chip, dubbed CTC chip, was designed and fabricated for conducting tumor cell isolation. As CTCs usually show multidrug resistance (MDR), the effect of MDR inhibitors on chemotherapeutic drug accumulation in the isolated single tumor cell is measured. As a model of CTC isolation, human prostate cancer cells were mixed with mouse blood cells and the label-free isolation of the tumor cells was conducted based on cell size difference. The major advantages of the CTC chip are the ability for fast cell isolation, followed by multiple rounds of single-cell measurements, suggesting a potential assay for detecting the drug responses based on the liquid biopsy of cancer patients.

Deterministic Integration of Quantum Dots into on-Chip Multimode Interference Beamsplitters Using in Situ Electron Beam Lithography.

PubMed

Schnauber, Peter; Schall, Johannes; Bounouar, Samir; Höhne, Theresa; Park, Suk-In; Ryu, Geun-Hwan; Heindel, Tobias; Burger, Sven; Song, Jin-Dong; Rodt, Sven; Reitzenstein, Stephan

2018-04-11

The development of multinode quantum optical circuits has attracted great attention in recent years. In particular, interfacing quantum-light sources, gates, and detectors on a single chip is highly desirable for the realization of large networks. In this context, fabrication techniques that enable the deterministic integration of preselected quantum-light emitters into nanophotonic elements play a key role when moving forward to circuits containing multiple emitters. Here, we present the deterministic integration of an InAs quantum dot into a 50/50 multimode interference beamsplitter via in situ electron beam lithography. We demonstrate the combined emitter-gate interface functionality by measuring triggered single-photon emission on-chip with g (2) (0) = 0.13 ± 0.02. Due to its high patterning resolution as well as spectral and spatial control, in situ electron beam lithography allows for integration of preselected quantum emitters into complex photonic systems. Being a scalable single-step approach, it paves the way toward multinode, fully integrated quantum photonic chips.

A micro-computer-based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, Rajan

1987-01-01

A mathematical model of magnetic variation in the continental United States was implemented in the Ohio University Loran-C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based Loran-C receiver is possible with the help of a math chip which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter is used to communicate between the 6502 based microcomputer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

Single-mode glass waveguide technology for optical interchip communication on board level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

From genes to protein mechanics on a chip.

PubMed

Otten, Marcus; Ott, Wolfgang; Jobst, Markus A; Milles, Lukas F; Verdorfer, Tobias; Pippig, Diana A; Nash, Michael A; Gaub, Hermann E

2014-11-01

Single-molecule force spectroscopy enables mechanical testing of individual proteins, but low experimental throughput limits the ability to screen constructs in parallel. We describe a microfluidic platform for on-chip expression, covalent surface attachment and measurement of single-molecule protein mechanical properties. A dockerin tag on each protein molecule allowed us to perform thousands of pulling cycles using a single cohesin-modified cantilever. The ability to synthesize and mechanically probe protein libraries enables high-throughput mechanical phenotyping.

Design and qualification of the SEU/TD Radiation Monitor chip

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Soli, George A.; Zamani, Nasser; Hicks, Kenneth A.

1992-01-01

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Single event effects on the APV25 front-end chip

NASA Astrophysics Data System (ADS)

Friedl, M.; Bauer, T.; Pernicka, M.

2003-03-01

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider at CERN will include a Silicon Strip Tracker covering a sensitive area of 206 m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25 μm deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets are inevitable. Moreover, localized ionization can also produce fake signals in the analog circuitry. Eight APV25 chips were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

Picoradio: Communication/Computation Piconodes for Sensor Networks

DTIC Science & Technology

2003-01-02

diagram of PicoNode III, or Quark node. It is made from two custom chips, Strange RF and Charm digital processor , and is complemented by a set of...the chipset comprising of Strange (analog OOK transceiver) and Charm (digital processor ) chips. 44 Figure 33: System block diagram of the Quark node...19 2.B PICONODE II - TWO-CHIP PICONODE IMPLEMENTATION ......................................... 21 2.B.1 Baseband processor (BBP

Transparent Nanopore Cavity Arrays Enable Highly Parallelized Optical Studies of Single Membrane Proteins on Chip.

PubMed

Diederichs, Tim; Nguyen, Quoc Hung; Urban, Michael; Tampé, Robert; Tornow, Marc

2018-06-13

Membrane proteins involved in transport processes are key targets for pharmaceutical research and industry. Despite continuous improvements and new developments in the field of electrical readouts for the analysis of transport kinetics, a well-suited methodology for high-throughput characterization of single transporters with nonionic substrates and slow turnover rates is still lacking. Here, we report on a novel architecture of silicon chips with embedded nanopore microcavities, based on a silicon-on-insulator technology for high-throughput optical readouts. Arrays containing more than 14 000 inverted-pyramidal cavities of 50 femtoliter volumes and 80 nm circular pore openings were constructed via high-resolution electron-beam lithography in combination with reactive ion etching and anisotropic wet etching. These cavities feature both, an optically transparent bottom and top cap. Atomic force microscopy analysis reveals an overall extremely smooth chip surface, particularly in the vicinity of the nanopores, which exhibits well-defined edges. Our unprecedented transparent chip design provides parallel and independent fluorescent readout of both cavities and buffer reservoir for unbiased single-transporter recordings. Spreading of large unilamellar vesicles with efficiencies up to 96% created nanopore-supported lipid bilayers, which are stable for more than 1 day. A high lipid mobility in the supported membrane was determined by fluorescent recovery after photobleaching. Flux kinetics of α-hemolysin were characterized at single-pore resolution with a rate constant of 0.96 ± 0.06 × 10 -3 s -1 . Here, we deliver an ideal chip platform for pharmaceutical research, which features high parallelism and throughput, synergistically combined with single-transporter resolution.

UW VLSI chip tester

NASA Astrophysics Data System (ADS)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Fabrication and characterization of microfabricated on-chip microelectrochemical cell for biosensing applications

NASA Astrophysics Data System (ADS)

Said, N. A. Mohd; Twomey, K.; Herzog, G.; Ogurtsov, V. I.

2017-03-01

The fabrication of on-chip microelectrochemical cell on Si wafer by means of photolithography is described here. The single on-chip microelectrochemical cell device has dimensions of 100 × 380 mm with integrated Pt counter electrode (CE), Ag/AgCl reference electrode (RE) and gold microelectrode array of 500 nm recess depth as the working electrode (WE). Two geometries of electrode array were implemented, band and disc, with fixed diameter/width of 10 µm; and varied centre-to-centre spacing (d) and number of electrodes (N) in the array. The on-chip microelectrochemical cell structure has been designed to facilitate further WE biomodifications. Firstly, the developed microelectrochemical cell does not require packaging hence reducing the production cost and time. Secondly, the working electrode (WE) on the microelectrochemical cell is positioned towards the end of the chip enabling modification of the working electrode surface to be carried out for surface bio-functionalisation without affecting both the RE and CE surface conditions. The developed on-chip microelectrochemical cell was examined with scanning electron microscopy (SEM) and characterised by two electrochemical techniques. Both cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS) were performed in 1 mM ferrocenecarboxylic acid (FCA) in 0.01 M phosphate buffered saline (PBS) solution at pH7.4. Electrochemical experiments showed that in the case of halving the interspacing distance of the microdisc WE array (50 nm instead of 100 nm), the voltammogram shifted from a steady-state CV (feature of hemispherical diffusion) to an inclined peak-shaped CV (feature of linear diffusion) albeit the arrays had the same surface area. In terms of EIS it was also found that linear diffusion dominates the surface instead of hemispherical diffusion once the interspacing distance was reduced, supporting the fact that closely packed arrays may behave like a macroelectrode

Learning and optimization with cascaded VLSI neural network building-block chips

NASA Technical Reports Server (NTRS)

Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

1992-01-01

To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

A Streaming Language Implementation of the Discontinuous Galerkin Method

NASA Technical Reports Server (NTRS)

Barth, Timothy; Knight, Timothy

2005-01-01

We present a Brook streaming language implementation of the 3-D discontinuous Galerkin method for compressible fluid flow on tetrahedral meshes. Efficient implementation of the discontinuous Galerkin method using the streaming model of computation introduces several algorithmic design challenges. Using a cycle-accurate simulator, performance characteristics have been obtained for the Stanford Merrimac stream processor. The current Merrimac design achieves 128 Gflops per chip and the desktop board is populated with 16 chips yielding a peak performance of 2 Teraflops. Total parts cost for the desktop board is less than $20K. Current cycle-accurate simulations for discretizations of the 3-D compressible flow equations yield approximately 40-50% of the peak performance of the Merrimac streaming processor chip. Ongoing work includes the assessment of the performance of the same algorithm on the 2 Teraflop desktop board with a target goal of achieving 1 Teraflop performance.

Accelerating Smith-Waterman Algorithm for Biological Database Search on CUDA-Compatible GPUs

NASA Astrophysics Data System (ADS)

Munekawa, Yuma; Ino, Fumihiko; Hagihara, Kenichi

This paper presents a fast method capable of accelerating the Smith-Waterman algorithm for biological database search on a cluster of graphics processing units (GPUs). Our method is implemented using compute unified device architecture (CUDA), which is available on the nVIDIA GPU. As compared with previous methods, our method has four major contributions. (1) The method efficiently uses on-chip shared memory to reduce the data amount being transferred between off-chip video memory and processing elements in the GPU. (2) It also reduces the number of data fetches by applying a data reuse technique to query and database sequences. (3) A pipelined method is also implemented to overlap GPU execution with database access. (4) Finally, a master/worker paradigm is employed to accelerate hundreds of database searches on a cluster system. In experiments, the peak performance on a GeForce GTX 280 card reaches 8.32 giga cell updates per second (GCUPS). We also find that our method reduces the amount of data fetches to 1/140, achieving approximately three times higher performance than a previous CUDA-based method. Our 32-node cluster version is approximately 28 times faster than a single GPU version. Furthermore, the effective performance reaches 75.6 giga instructions per second (GIPS) using 32 GeForce 8800 GTX cards.

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

NASA Astrophysics Data System (ADS)

Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

2018-01-01

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

Development of the output monitor with single-chip microcomputer in a time-keeping system.

NASA Astrophysics Data System (ADS)

Zhou, Jiguang; Gong, Yuanfang

An output monitor has been designed with Intel 8031 single-chip microcomputer for a time working station. The functions of the instrument include the comparable measurement of the clocks, the buffer output of time and frequency signals, the monitoring and alarming of working state etc. The principle and application of the instrument are described.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Single-Cell Electric Lysis on an Electroosmotic-Driven Microfluidic Chip with Arrays of Microwells

PubMed Central

Jen, Chun-Ping; Amstislavskaya, Tamara G.; Liu, Ya-Hui; Hsiao, Ju-Hsiu; Chen, Yu-Hung

2012-01-01

Accurate analysis at the single-cell level has become a highly attractive tool for investigating cellular content. An electroosmotic-driven microfluidic chip with arrays of 30-μm-diameter microwells was developed for single-cell electric lysis in the present study. The cellular occupancy in the microwells when the applied voltage was 5 V (82.4%) was slightly higher than that at an applied voltage of 10 V (81.8%). When the applied voltage was increased to 15 V, the cellular occupancy in the microwells dropped to 64.3%. More than 50% of the occupied microwells contain individual cells. The results of electric lysis experiments at the single-cell level indicate that the cells were gradually lysed as the DC voltage of 30 V was applied; the cell was fully lysed after 25 s. Single-cell electric lysis was demonstrated in the proposed microfluidic chip, which is suitable for high-throughput cell lysis. PMID:22969331

Electrical lysis: dynamics revisited and advances in On-chip operation.

PubMed

Morshed, Bashir; Shams, Maitham; Mussivand, Tofy

2013-01-01

Electrical lysis (EL) is the process of breaking the cell membrane to expose the internal contents under an applied high electric field. Lysis is an important phenomenon for cellular analysis, medical treatment, and biofouling control. This paper aims to review, summarize, and analyze recent advancements on EL. Major databases including PubMed, Ei Engineering Village, IEEE Xplore, and Scholars Portal were searched using relevant keywords. More than 50 articles published in English since 1997 are cited in this article. EL has several key advantages compared to other lysis techniques such as chemical, mechanical, sonication, or laser, including rapid speed of operation, ability to control, miniaturization, low cost, and low power requirement. A variety of cell types have been investigated for including protoplasts, E. coli, yeasts, blood cells, and cancer cells. EL has been developed and applied for decontamination, cytology, genetics, single-cell analysis, cancer treatment, and other applications. On-chip EL is a promising technology for multiplexed automated implementation of cell-sample preparation and processing with micro- or nanoliter reagents.

A single-chip event sequencer and related microcontroller instrumentation for atomic physics research.

PubMed

Eyler, E E

2011-01-01

A 16-bit digital event sequencer with 50 ns resolution and 50 ns trigger jitter is implemented by using an internal 32-bit timer on a dsPIC30F4013 microcontroller, controlled by an easily modified program written in standard C. It can accommodate hundreds of output events, and adjacent events can be spaced as closely as 1.5 μs. The microcontroller has robust 5 V inputs and outputs, allowing a direct interface to common laboratory equipment and other electronics. A USB computer interface and a pair of analog ramp outputs can be added with just two additional chips. An optional display/keypad unit allows direct interaction with the sequencer without requiring an external computer. Minor additions also allow simple realizations of other complex instruments, including a precision high-voltage ramp generator for driving spectrum analyzers or piezoelectric positioners, and a low-cost proportional integral differential controller and lock-in amplifier for laser frequency stabilization with about 100 kHz bandwidth.

Surface-Wave Pulse Routing around Sharp Right Angles

NASA Astrophysics Data System (ADS)

Gao, Z.; Xu, H.; Gao, F.; Zhang, Y.; Luo, Y.; Zhang, B.

2018-04-01

Surface-plasmon polaritons (SPPs), or localized electromagnetic surface waves propagating on a metal-dielectric interface, are deemed promising information carriers for future subwavelength terahertz and optical photonic circuitry. However, surface waves fundamentally suffer from scattering loss when encountering sharp corners in routing and interconnection of photonic signals. Previous approaches enabling scattering-free surface-wave guidance around sharp corners are limited to either volumetric waveguide environments or extremely narrow bandwidth, being unable to guide a surface-wave pulse (SPP wave packet) on an on-chip platform. Here, in a surface-wave band-gap crystal implemented on a single metal surface, we demonstrate in time-domain routing a surface-wave pulse around multiple sharp right angles without perceptible scattering. Our work not only offers a solution to on-chip surface-wave pulse routing along an arbitrary path, but it also provides spatiotemporal information on the interplay between surface-wave pulses and sharp corners, both of which are desirable in developing high-performance large-scale integrated photonic circuits.

A TMS320-based modem for the aeronautical-satellite core data service

NASA Astrophysics Data System (ADS)

Moher, Michael L.; Lodge, John H.

The International Civil Aviation Organization (ICAO) Future Air Navigation Systems (FANS) committee, the Airlines Electronics Engineering Committee (AEEC), and Inmarsat have been developing standards for an aeronautical satellite communications service. These standards encompass a satellite communications system architecture to provide comprehensive aeronautical communications services. Incorporated into the architecture is a core service capability, providing only low rate data communications, which all service providers and all aircraft earth terminals are required to support. In this paper an implementation of the physical layer of this standard for the low data rate core service is described. This is a completely digital modem (up to a low intermediate frequency). The implementation uses a single TMS320C25 chip for the transmit baseband functions of scrambling, encoding, interleaving, block formatting and modulation. The receiver baseband unit uses a dual processor configuration to implement the functions of demodulation, synchronization, de-interleaving, decoding and de-scrambling. The hardware requirements, the software structure and the algorithms of this implementation are described.

Wireless spread-spectrum telesensor chip with synchronous digital architecture

DOEpatents

Smith, Stephen F.; Turner, Gary W.; Wintenberg, Alan L.; Emery, Michael Steven

2005-03-08

A fully integrated wireless spread-spectrum sensor incorporating all elements of an "intelligent" sensor on a single circuit chip is capable of telemetering data to a receiver. Synchronous control of all elements of the chip provides low-cost, low-noise, and highly robust data transmission, in turn enabling the use of low-cost monolithic receivers.

On-chip beam positioning sensor via frequency locked cascaded ring resonators

NASA Astrophysics Data System (ADS)

Naiman, Alex; Stern, Liron; Levy, Uriel

2018-05-01

We demonstrate an approach for on-chip beam positioning with a position accuracy of up to 100 nm. This approach is based on tracking the resonance of two adjacent microring resonators that are implemented on a silicon on insulator chip. We demonstrate the functionality of our approach by illuminating the chip through a Near Field Scanning Optical Microscope tip and monitoring the shift of the microring resonances due to the thermo-optic effect. We also discuss the contribution of different effects such as free carrier absorption and dispersion to the resonance shift.

Design and status of the RF-digitizer integrated circuit

NASA Technical Reports Server (NTRS)

Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

1991-01-01

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Hybridization of active and passive elements for planar photonic components and interconnects

NASA Astrophysics Data System (ADS)

Pearson, M.; Bidnyk, S.; Balakrishnan, A.

2007-02-01

The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

Surface transport and stable trapping of particles and cells by an optical waveguide loop.

PubMed

Hellesø, Olav Gaute; Løvhaugen, Pål; Subramanian, Ananth Z; Wilkinson, James S; Ahluwalia, Balpreet Singh

2012-09-21

Waveguide trapping has emerged as a useful technique for parallel and planar transport of particles and biological cells and can be integrated with lab-on-a-chip applications. However, particles trapped on waveguides are continuously propelled forward along the surface of the waveguide. This limits the practical usability of the waveguide trapping technique with other functions (e.g. analysis, imaging) that require particles to be stationary during diagnosis. In this paper, an optical waveguide loop with an intentional gap at the centre is proposed to hold propelled particles and cells. The waveguide acts as a conveyor belt to transport and deliver the particles/cells towards the gap. At the gap, the diverging light fields hold the particles at a fixed position. The proposed waveguide design is numerically studied and experimentally implemented. The optical forces on the particle at the gap are calculated using the finite element method. Experimentally, the method is used to transport and trap micro-particles and red blood cells at the gap with varying separations. The waveguides are only 180 nm thick and thus could be integrated with other functions on the chip, e.g. microfluidics or optical detection, to make an on-chip system for single cell analysis and to study the interaction between cells.

Rapid self-assembly of DNA on a microfluidic chip

PubMed Central

Zheng, Yao; Footz, Tim; Manage, Dammika P; Backhouse, Christopher James

2005-01-01

Background DNA self-assembly methods have played a major role in enabling methods for acquiring genetic information without having to resort to sequencing, a relatively slow and costly procedure. However, even self-assembly processes tend to be very slow when they rely upon diffusion on a large scale. Miniaturisation and integration therefore hold the promise of greatly increasing this speed of operation. Results We have developed a rapid method for implementing the self-assembly of DNA within a microfluidic system by electrically extracting the DNA from an environment containing an uncharged denaturant. By controlling the parameters of the electrophoretic extraction and subsequent analysis of the DNA we are able to control when the hybridisation occurs as well as the degree of hybridisation. By avoiding off-chip processing or long thermal treatments we are able to perform this hybridisation rapidly and can perform hybridisation, sizing, heteroduplex analysis and single-stranded conformation analysis within a matter of minutes. The rapidity of this analysis allows the sampling of transient effects that may improve the sensitivity of mutation detection. Conclusions We believe that this method will aid the integration of self-assembly methods upon microfluidic chips. The speed of this analysis also appears to provide information upon the dynamics of the self-assembly process. PMID:15717935

Chip-based wide field-of-view nanoscopy

NASA Astrophysics Data System (ADS)

Diekmann, Robin; Helle, Øystein I.; Øie, Cristina I.; McCourt, Peter; Huser, Thomas R.; Schüttpelz, Mark; Ahluwalia, Balpreet S.

2017-04-01

Present optical nanoscopy techniques use a complex microscope for imaging and a simple glass slide to hold the sample. Here, we demonstrate the inverse: the use of a complex, but mass-producible optical chip, which hosts the sample and provides a waveguide for the illumination source, and a standard low-cost microscope to acquire super-resolved images via two different approaches. Waveguides composed of a material with high refractive-index contrast provide a strong evanescent field that is used for single-molecule switching and fluorescence excitation, thus enabling chip-based single-molecule localization microscopy. Additionally, multimode interference patterns induce spatial fluorescence intensity variations that enable fluctuation-based super-resolution imaging. As chip-based nanoscopy separates the illumination and detection light paths, total-internal-reflection fluorescence excitation is possible over a large field of view, with up to 0.5 mm × 0.5 mm being demonstrated. Using multicolour chip-based nanoscopy, we visualize fenestrations in liver sinusoidal endothelial cells.

Chip level modeling of LSI devices

NASA Technical Reports Server (NTRS)

Armstrong, J. R.

1984-01-01

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of the LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

Reconfigurable tree architectures using subtree oriented fault tolerance

NASA Technical Reports Server (NTRS)

Lowrie, Matthew B.

1987-01-01

An approach to the design of reconfigurable tree architecture is presented in which spare processors are allocated at the leaves. The approach is unique in that spares are associated with subtrees and sharing of spares between these subtrees can occur. The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links. VLSI layout is 0(n) for binary trees and is directly extensible to N-ary trees and fault tolerance through performance degradation.

A Bionic Neural Link for peripheral nerve repair.

PubMed

Xu, Yong Ping; Yen, Shih-Cheng; Ng, Kian Ann; Liu, Xu; Tan, Ter Chyan

2012-01-01

Peripheral nerve injuries with large gaps and long nerve regrowth paths are difficult to repair using existing surgical techniques, due to nerve degeneration and muscle atrophy. This paper proposes a Bionic Neural Link (BNL) as an alternative way for peripheral nerve repair. The concept of the BNL is described, along with the hypothetical benefits. A prototype monolithic single channel BNL has been developed, which consists of 16 neural recording channels and one stimulation channel, and is implemented in a 0.35-µm CMOS technology. The BNL has been tested in in-vivo animal experiments. Full function of the BNL chip has been demonstrated.

Apparatus and Method for Packaging and Integrating Microphotonic Devices

NASA Technical Reports Server (NTRS)

Nguyen, Hung (Inventor)

2008-01-01

An apparatus is disclosed that includes a carrier structure and an optical coupling arrangement. The carrier structure is made of a silicon material and allows for the packaging and integrating of microphotonic devices onto a single chip. The optical coupling mechanism enables laser light to be coupled into and out of a microphotonic resonant disk integrated on the carrier. The carrier provides first, second and third cavities that are dimensioned so as to accommodate the insertion and snug fitting of the microphotonic resonant disk and first and second prisms that are implemented by the optical coupling arrangement to accommodate the laser coupling.

A Hardware Platform for Tuning of MEMS Devices Using Closed-Loop Frequency Response

NASA Technical Reports Server (NTRS)

Ferguson, Michael I.; MacDonald, Eric; Foor, David

2005-01-01

We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing Post-Resonator MEMS gyroscope. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the micro-gyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

The clinical performance evaluation of novel protein chips for eleven biomarkers detection and the diagnostic model study.

PubMed

Luo, Yuan; Zhu, Xu; Zhang, Pengjun; Shen, Qian; Wang, Zi; Wen, Xinyu; Wang, Ling; Gao, Jing; Dong, Jin; Yang, Caie; Wu, Tangming; Zhu, Zheng; Tian, Yaping

2015-01-01

We aimed to develop and validate two novel protein chips, which are based on microarray chemiluminescence immunoassay and can simultaneously detected 11 biomarkers, and then to evaluate their clinical diagnostic value by comparing with the traditional methods. Protein chips were evaluated for limit of detection, specificity, common interferences, linearity, precision and accuracy. 11 biomarkers were simultaneously detected by traditional methods and protein chips in 3683 samples, which included 1723 cancer patients, 1798 benign diseases patients and 162 healthy controls. After assay validation, protein chips demonstrated high sensitivity, high specificity, good linearity, low imprecision and were free of common interferences. Compared with the traditional methods, protein chips have good correlation in the detection of all the 13 kinds of biomarkers (r≥0.935, P<0.001). For specific cancer detection, there were no statistically significant differences between the traditional method and novel protein chips, except that male protein chip showed significantly better diagnostic value on NSE detection (P=0.004) but significantly worse value on pro-GRP detection (P=0.012), female chip showed significantly better diagnostic value on pro-GRP detection (P=0.005). Furthermore, both male and female multivariate diagnostic models had significantly better diagnostic value than single detection of PGI, PG II, pro-GRP, NSE and CA125 (P<0.05). In addition, male models had significantly better diagnostic value than single CA199 and free-PSA (P<0.05), while female models observed significantly better diagnostic value than single CA724 and β-HCG (P<0.05). For total disease or cancer detection, the AUC of multivariate logistic regression for the male and female disease detection was 0.981 (95% CI: 0.975-0.987) and 0.836 (95% CI: 0.798-0.874), respectively. While, that for total cancer detection was 0.691 (95% CI: 0.666-0.717) and 0.753 (95% CI: 0.731-0.775), respectively. The new designed protein chips are simple, multiplex and reliable clinical assays and the multi-parameter diagnostic models based on them could significantly improve their clinical performance.

The clinical performance evaluation of novel protein chips for eleven biomarkers detection and the diagnostic model study

PubMed Central

Luo, Yuan; Zhu, Xu; Zhang, Pengjun; Shen, Qian; Wang, Zi; Wen, Xinyu; Wang, Ling; Gao, Jing; Dong, Jin; Yang, Caie; Wu, Tangming; Zhu, Zheng; Tian, Yaping

2015-01-01

We aimed to develop and validate two novel protein chips, which are based on microarray chemiluminescence immunoassay and can simultaneously detected 11 biomarkers, and then to evaluate their clinical diagnostic value by comparing with the traditional methods. Protein chips were evaluated for limit of detection, specificity, common interferences, linearity, precision and accuracy. 11 biomarkers were simultaneously detected by traditional methods and protein chips in 3683 samples, which included 1723 cancer patients, 1798 benign diseases patients and 162 healthy controls. After assay validation, protein chips demonstrated high sensitivity, high specificity, good linearity, low imprecision and were free of common interferences. Compared with the traditional methods, protein chips have good correlation in the detection of all the 13 kinds of biomarkers (r≥0.935, P<0.001). For specific cancer detection, there were no statistically significant differences between the traditional method and novel protein chips, except that male protein chip showed significantly better diagnostic value on NSE detection (P=0.004) but significantly worse value on pro-GRP detection (P=0.012), female chip showed significantly better diagnostic value on pro-GRP detection (P=0.005). Furthermore, both male and female multivariate diagnostic models had significantly better diagnostic value than single detection of PGI, PG II, pro-GRP, NSE and CA125 (P<0.05). In addition, male models had significantly better diagnostic value than single CA199 and free-PSA (P<0.05), while female models observed significantly better diagnostic value than single CA724 and β-HCG (P<0.05). For total disease or cancer detection, the AUC of multivariate logistic regression for the male and female disease detection was 0.981 (95% CI: 0.975-0.987) and 0.836 (95% CI: 0.798-0.874), respectively. While, that for total cancer detection was 0.691 (95% CI: 0.666-0.717) and 0.753 (95% CI: 0.731-0.775), respectively. The new designed protein chips are simple, multiplex and reliable clinical assays and the multi-parameter diagnostic models based on them could significantly improve their clinical performance. PMID:26884957

Plasmonic SERS nanochips and nanoprobes for medical diagnostics and bio-energy applications

NASA Astrophysics Data System (ADS)

Ngo, Hoan T.; Wang, Hsin-Neng; Crawford, Bridget M.; Fales, Andrew M.; Vo-Dinh, Tuan

2017-02-01

The development of rapid, easy-to-use, cost-effective, high accuracy, and high sensitive DNA detection methods for molecular diagnostics has been receiving increasing interest. Over the last five years, our laboratory has developed several chip-based DNA detection techniques including the molecular sentinel-on-chip (MSC), the multiplex MSC, and the inverse molecular sentinel-on-chip (iMS-on-Chip). In these techniques, plasmonic surface-enhanced Raman scattering (SERS) Nanowave chips were functionalized with DNA probes for single-step DNA detection. Sensing mechanisms were based on hybridization of target sequences and DNA probes, resulting in a distance change between SERS reporters and the Nanowave chip's gold surface. This distance change resulted in change in SERS intensity, thus indicating the presence and capture of the target sequences. Our techniques were single-step DNA detection techniques. Target sequences were detected by simple delivery of sample solutions onto DNA probe-functionalized Nanowave chips and SERS signals were measured after 1h - 2h incubation. Target sequence labeling or washing to remove unreacted components was not required, making the techniques simple, easy-to-use, and cost effective. The usefulness of the techniques for medical diagnostics was illustrated by the detection of genetic biomarkers for respiratory viral infection and of dengue virus 4 DNA.

NMR spectroscopy of single sub-nL ova with inductive ultra-compact single-chip probes

PubMed Central

Grisi, Marco; Vincent, Franck; Volpe, Beatrice; Guidetti, Roberto; Harris, Nicola; Beck, Armin; Boero, Giovanni

2017-01-01

Nuclear magnetic resonance (NMR) spectroscopy enables non-invasive chemical studies of intact living matter. However, the use of NMR at the volume scale typical of microorganisms is hindered by sensitivity limitations, and experiments on single intact organisms have so far been limited to entities having volumes larger than 5 nL. Here we show NMR spectroscopy experiments conducted on single intact ova of 0.1 and 0.5 nL (i.e. 10 to 50 times smaller than previously achieved), thereby reaching the relevant volume scale where life development begins for a broad variety of organisms, humans included. Performing experiments with inductive ultra-compact (1 mm2) single-chip NMR probes, consisting of a low noise transceiver and a multilayer 150 μm planar microcoil, we demonstrate that the achieved limit of detection (about 5 pmol of 1H nuclei) is sufficient to detect endogenous compounds. Our findings suggest that single-chip probes are promising candidates to enable NMR-based study and selection of microscopic entities at biologically relevant volume scales. PMID:28317887

Atom chip microscopy: A novel probe for strongly correlated materials

NASA Astrophysics Data System (ADS)

Kasch, Brian; Naides, Matthew; Turner, Richard; Ray, Ushnish; Lev, Benjamin

2010-03-01

Atom chip technology---substrates supporting micron-sized current-carrying wires that create magnetic microtraps near surfaces for thermal or degenerate gases of neutral atoms---will enable single-shot, large area detection of magnetic flux below the 10-7 flux quantum level. By harnessing the extreme sensitivity of Bose-Einstein condensates (BECs) to external perturbations, cryogenic atom chips could provide a magnetic flux detection capability that surpasses all other techniques by a factor of 10^2--10^3. We describe the merits of atom chip microscopy, our Rb BEC and atom chip apparatus, and prospects for imaging strongly correlated condensed matter materials.

Implementation of a Synchronized Oscillator Circuit for Fast Sensing and Labeling of Image Objects

PubMed Central

Kowalski, Jacek; Strzelecki, Michal; Kim, Hyongsuk

2011-01-01

We present an application-specific integrated circuit (ASIC) CMOS chip that implements a synchronized oscillator cellular neural network with a matrix size of 32 × 32 for object sensing and labeling in binary images. Networks of synchronized oscillators are a recently developed tool for image segmentation and analysis. Its parallel network operation is based on a “temporary correlation” theory that attempts to describe scene recognition as if performed by the human brain. The synchronized oscillations of neuron groups attract a person’s attention if he or she is focused on a coherent stimulus (image object). For more than one perceived stimulus, these synchronized patterns switch in time between different neuron groups, thus forming temporal maps that code several features of the analyzed scene. In this paper, a new oscillator circuit based on a mathematical model is proposed, and the network architecture and chip functional blocks are presented and discussed. The proposed chip is implemented in AMIS 0.35 μm C035M-D 5M/1P technology. An application of the proposed network chip for the segmentation of insulin-producing pancreatic islets in magnetic resonance liver images is presented. PMID:22163803

A two-step A/D conversion and column self-calibration technique for low noise CMOS image sensors.

PubMed

Bae, Jaeyoung; Kim, Daeyun; Ham, Seokheon; Chae, Youngcheol; Song, Minkyu

2014-07-04

In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

Cosmology Large Angular Scale Surveyor (CLASS) Focal Plane Development

NASA Technical Reports Server (NTRS)

Chuss, D. T.; Ali, A.; Amiri, M.; Appel, J.; Bennett, C. L.; Colazo, F.; Denis, K. L.; Dunner, R.; Essinger-Hileman, T.; Eimer, J.;

Cosmology Large Angular Scale Surveyor (CLASS) Focal Plane Development

NASA Astrophysics Data System (ADS)

Chuss, D. T.; Ali, A.; Amiri, M.; Appel, J.; Bennett, C. L.; Colazo, F.; Denis, K. L.; Dünner, R.; Essinger-Hileman, T.; Eimer, J.; Fluxa, P.; Gothe, D.; Halpern, M.; Harrington, K.; Hilton, G.; Hinshaw, G.; Hubmayr, J.; Iuliano, J.; Marriage, T. A.; Miller, N.; Moseley, S. H.; Mumby, G.; Petroff, M.; Reintsema, C.; Rostem, K.; U-Yen, K.; Watts, D.; Wagner, E.; Wollack, E. J.; Xu, Z.; Zeng, L.

2016-08-01

The Cosmology Large Angular Scale Surveyor (CLASS) will measure the polarization of the Cosmic Microwave Background to search for and characterize the polarized signature of inflation. CLASS will operate from the Atacama Desert and observe ˜ 70 % of the sky. A variable-delay polarization modulator provides modulation of the polarization at ˜ 10 Hz to suppress the 1/ f noise of the atmosphere and enable the measurement of the large angular scale polarization modes. The measurement of the inflationary signal across angular scales that spans both the recombination and reionization features allows a test of the predicted shape of the polarized angular power spectra in addition to a measurement of the energy scale of inflation. CLASS is an array of telescopes covering frequencies of 38, 93, 148, and 217 GHz. These frequencies straddle the foreground minimum and thus allow the extraction of foregrounds from the primordial signal. Each focal plane contains feedhorn-coupled transition-edge sensors that simultaneously detect two orthogonal linear polarizations. The use of single-crystal silicon as the dielectric for the on-chip transmission lines enables both high efficiency and uniformity in fabrication. Integrated band definition has been implemented that both controls the bandpass of the single-mode transmission on the chip and prevents stray light from coupling to the detectors.

Development of an Acceptance Test for Chip Seal Projects : final report.

DOT National Transportation Integrated Search

2016-11-21

Chip seals are among the most popular preventive maintenance techniques implemented by many DOTs, county road departments and cities. The deteriorated pavement surface is sprayed with an asphalt emulsion or binder, and then a layer of uniformly-grade...

On-Chip Magnetic Platform for Single-Particle Manipulation with Integrated Electrical Feedback.

PubMed

Monticelli, Marco; Torti, Andrea; Cantoni, Matteo; Petti, Daniela; Albisetti, Edoardo; Manzin, Alessandra; Guerriero, Erica; Sordan, Roman; Gervasoni, Giacomo; Carminati, Marco; Ferrari, Giorgio; Sampietro, Marco; Bertacco, Riccardo

2016-02-17

Methods for the manipulation of single magnetic particles have become very interesting, in particular for in vitro biological studies. Most of these studies require an external microscope to provide the operator with feedback for controlling the particle motion, thus preventing the use of magnetic particles in high-throughput experiments. In this paper, a simple and compact system with integrated electrical feedback is presented, implementing in the very same device both the manipulation and detection of the transit of single particles. The proposed platform is based on zig-zag shaped magnetic nanostructures, where transverse magnetic domain walls are pinned at the corners and attract magnetic particles in suspension. By applying suitable external magnetic fields, the domain walls move to the nearest corner, thus causing the step by step displacement of the particles along the nanostructure. The very same structure is also employed for detecting the bead transit. Indeed, the presence of the magnetic particle in suspension over the domain wall affects the depinning field required for its displacement. This characteristic field can be monitored through anisotropic magnetoresistance measurements, thus implementing an integrated electrical feedback of the bead transit. In particular, the individual manipulation and detection of single 1-μm sized beads is demonstrated. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

On-chip Magnetic Separation and Cell Encapsulation in Droplets†

PubMed Central

Chen, Aaron; Byvank, Tom; Chang, Woo-Jin; Bharde, Atul; Vieira, Greg; Miller, Brandon; Chalmers, Jeffrey J.; Bashir, Rashid; Sooryakumar, Ratnasingham

2014-01-01

The demand for high-throughput single cell assays is gaining importance because of the heterogeneity of many cell suspensions, even after significant initial sorting. These suspensions may display cell-to-cell variability at the gene expression level that could impact single cell functional genomics, cancer, stem-cell research and drug screening. The on-chip monitoring of individual cells in an isolated environment would prevent cross-contamination, provide high recovery yield, and enable study of biological traits at a single cell level. These advantages of on-chip biological experiments is a significant improvement for myriad of cell analyses over conventional methods, which require bulk samples providing only averaged information on cell metabolism. We report on a device that integrates mobile magnetic trap array with microfluidic technology to provide, combined functionality of separation of immunomagnetically labeled cells or magnetic beads and their encapsulation with reagents into pico-liter droplets. This scheme of simultaneous reagent delivery and compartmentalization of the cells immediately after sorting, all performed seamlessly within the same chip, offers unique advantages such as the ability to capture cell traits as originated from its native environment, reduced chance of contamination, minimal use and freshness of the reagent solution that reacts only with separated objects, and tunable encapsulation characteristics independent of the input flow. In addition to the demonstrated preliminary cell viability assay, the device can potentially be integrated with other up- or downstream on-chip modules to become a powerful single-cell analysis tool. PMID:23370785

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Tarsa, Eric; Ibbetson, James; Morgan, Frederick; Dowling, Kevin; Lys, Ihor

2017-10-17

An LED component according to the present invention comprising an array of LED chips mounted on a submount with the LED chips capable of emitting light in response to an electrical signal. The array can comprise LED chips emitting at two colors of light wherein the LED component emits light comprising the combination of the two colors of light. A single lens is included over the array of LED chips. The LED chip array can emit light of greater than 800 lumens with a drive current of less than 150 milli-Amps. The LED chip component can also operate at temperatures less than 3000 degrees K. In one embodiment, the LED array is in a substantially circular pattern on the submount.

Research on NC motion controller based on SOPC technology

NASA Astrophysics Data System (ADS)

Jiang, Tingbiao; Meng, Biao

2006-11-01

With the rapid development of the digitization and informationization, the application of numerical control technology in the manufacturing industry becomes more and more important. However, the conventional numerical control system usually has some shortcomings such as the poor in system openness, character of real-time, cutability and reconfiguration. In order to solve these problems, this paper investigates the development prospect and advantage of the application in numerical control area with system-on-a-Programmable-Chip (SOPC) technology, and puts forward to a research program approach to the NC controller based on SOPC technology. Utilizing the characteristic of SOPC technology, we integrate high density logic device FPGA, memory SRAM, and embedded processor ARM into a single programmable logic device. We also combine the 32-bit RISC processor with high computing capability of the complicated algorithm with the FPGA device with strong motivable reconfiguration logic control ability. With these steps, we can greatly resolve the defect described in above existing numerical control systems. For the concrete implementation method, we use FPGA chip embedded with ARM hard nuclear processor to construct the control core of the motion controller. We also design the peripheral circuit of the controller according to the requirements of actual control functions, transplant real-time operating system into ARM, design the driver of the peripheral assisted chip, develop the application program to control and configuration of FPGA, design IP core of logic algorithm for various NC motion control to configured it into FPGA. The whole control system uses the concept of modular and structured design to develop hardware and software system. Thus the NC motion controller with the advantage of easily tailoring, highly opening, reconfigurable, and expandable can be implemented.

Analog signal processing for optical coherence imaging systems

NASA Astrophysics Data System (ADS)

Xu, Wei

Optical coherence tomography (OCT) and optical coherence microscopy (OCM) are non-invasive optical coherence imaging techniques, which enable micron-scale resolution, depth resolved imaging capability. Both OCT and OCM are based on Michelson interferometer theory. They are widely used in ophthalmology, gastroenterology and dermatology, because of their high resolution, safety and low cost. OCT creates cross sectional images whereas OCM obtains en face images. In this dissertation, the design and development of three increasingly complicated analog signal processing (ASP) solutions for optical coherence imaging are presented. The first ASP solution was implemented for a time domain OCT system with a Rapid Scanning Optical Delay line (RSOD)-based optical signal modulation and logarithmic amplifier (Log amp) based demodulation. This OCT system can acquire up to 1600 A-scans per second. The measured dynamic range is 106dB at 200A-scan per second. This OCT signal processing electronics includes an off-the-shelf filter box with a Log amp circuit implemented on a PCB board. The second ASP solution was developed for an OCM system with synchronized modulation and demodulation and compensation for interferometer phase drift. This OCM acquired micron-scale resolution, high dynamic range images at acquisition speeds up to 45,000 pixels/second. This OCM ASP solution is fully custom designed on a perforated circuit board. The third ASP solution was implemented on a single 2.2 mm x 2.2 mm complementary metal oxide semiconductor (CMOS) chip. This design is expandable to a multiple channel OCT system. A single on-chip CMOS photodetector and ASP channel was used for coherent demodulation in a time domain OCT system. Cross-sectional images were acquired with a dynamic range of 76dB (limited by photodetector responsivity). When incorporated with a bump-bonded InGaAs photodiode with higher responsivity, the expected dynamic range is close to 100dB.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grisi, Marco, E-mail: marco.grisi@epfl.ch; Gualco, Gabriele; Boero, Giovanni

In this article, we present an integrated broadband complementary metal-oxide semiconductor single-chip transceiver suitable for the realization of multi-nuclear pulsed nuclear magnetic resonance (NMR) probes. The realized single-chip transceiver can be interfaced with on-chip integrated microcoils or external LC resonators operating in the range from 1 MHz to 1 GHz. The dimension of the chip is about 1 mm{sup 2}. It consists of a radio-frequency (RF) power amplifier, a low-noise RF preamplifier, a frequency mixer, an audio-frequency amplifier, and fully integrated transmit-receive switches. As specific example, we show its use for multi-nuclear NMR spectroscopy. With an integrated coil of aboutmore » 150 μm external diameter, a {sup 1}H spin sensitivity of about 1.5 × 10{sup 13} spins/Hz{sup 1/2} is achieved at 7 T.« less

A micro-computer based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, R.

1984-01-01

A mathematical model of magnetic variation in the continental United States (COT48) was implemented in the Ohio University LORAN C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based LORAN C receiver is possible with the help of a math chip, Am9511 which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter (M6520) is used to communicate between the 6502 based micro-computer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

Quad-Chip Double-Balanced Frequency Tripler

NASA Technical Reports Server (NTRS)

Lin, Robert H.; Ward, John S.; Bruneau, Peter J.; Mehdi, Imran; Thomas, Bertrand C.; Maestrini, Alain

2010-01-01

Solid-state frequency multipliers are used to produce tunable broadband sources at millimeter and submillimeter wavelengths. The maximum power produced by a single chip is limited by the electrical breakdown of the semiconductor and by the thermal management properties of the chip. The solution is to split the drive power to a frequency tripler using waveguides to divide the power among four chips, then recombine the output power from the four chips back into a single waveguide. To achieve this, a waveguide branchline quadrature hybrid coupler splits a 100-GHz input signal into two paths with a 90 relative phase shift. These two paths are split again by a pair of waveguide Y-junctions. The signals from the four outputs of the Y-junctions are tripled in frequency using balanced Schottky diode frequency triplers before being recombined with another pair of Y-junctions. A final waveguide branchline quadrature hybrid coupler completes the combination. Using four chips instead of one enables using four-times higher power input, and produces a nearly four-fold power output as compared to using a single chip. The phase shifts introduced by the quadrature hybrid couplers provide isolation for the input and output waveguides, effectively eliminating standing waves between it and surrounding components. This is accomplished without introducing the high losses and expense of ferrite isolators. A practical use of this technology is to drive local oscillators as was demonstrated around 300 GHz for a heterodyne spectrometer operating in the 2-3-THz band. Heterodyne spectroscopy in this frequency band is especially valuable for astrophysics due to the presence of a very large number of molecular spectral lines. Besides high-resolution radar and spectrographic screening applications, this technology could also be useful for laboratory spectroscopy.

75 FR 447 - In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-05

... review (1) the finding that the claim term ``top layer'' recited in claim 1 of the '106 patent means ``an outer layer of the chip assembly upon which the terminals are fixed,'' the requirement that ``the `top layer' is a single layer,'' and the effect of the findings on the infringement analysis, invalidity...

Selective attention in multi-chip address-event systems.

PubMed

Bartolozzi, Chiara; Indiveri, Giacomo

2009-01-01

Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the "Selective Attention Chip" (SAC), which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

Cascaded VLSI Chips Help Neural Network To Learn

NASA Technical Reports Server (NTRS)

Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

1993-01-01

Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

Deterministic Integration of Quantum Dots into on-Chip Multimode Interference Beamsplitters Using in Situ Electron Beam Lithography

NASA Astrophysics Data System (ADS)

Schnauber, Peter; Schall, Johannes; Bounouar, Samir; Höhne, Theresa; Park, Suk-In; Ryu, Geun-Hwan; Heindel, Tobias; Burger, Sven; Song, Jin-Dong; Rodt, Sven; Reitzenstein, Stephan

2018-04-01

The development of multi-node quantum optical circuits has attracted great attention in recent years. In particular, interfacing quantum-light sources, gates and detectors on a single chip is highly desirable for the realization of large networks. In this context, fabrication techniques that enable the deterministic integration of pre-selected quantum-light emitters into nanophotonic elements play a key role when moving forward to circuits containing multiple emitters. Here, we present the deterministic integration of an InAs quantum dot into a 50/50 multi-mode interference beamsplitter via in-situ electron beam lithography. We demonstrate the combined emitter-gate interface functionality by measuring triggered single-photon emission on-chip with $g^{(2)}(0) = 0.13\\pm 0.02$. Due to its high patterning resolution as well as spectral and spatial control, in-situ electron beam lithography allows for integration of pre-selected quantum emitters into complex photonic systems. Being a scalable single-step approach, it paves the way towards multi-node, fully integrated quantum photonic chips.

Silicone polymer waveguide bridge for Si to glass optical fibers

NASA Astrophysics Data System (ADS)

Kruse, Kevin L.; Riegel, Nicholas J.; Middlebrook, Christopher T.

2015-03-01

Multimode step index polymer waveguides achieve high-speed, (<10 Gb/s) low bit-error-rates for onboard and embedded circuit applications. Using several multimode waveguides in parallel enables overall capacity to reach beyond 100 Gb/s, but the intrinsic bandwidth limitations due to intermodal dispersion limit the data transmission rates within multimode waveguides. Single mode waveguides, where intermodal dispersion is not present, have the potential to further improve data transmission rates. Single mode waveguide size is significantly less than their multimode counterparts allowing for greater density of channels leading to higher bandwidth capacity per layer. Challenges in implementation of embedded single mode waveguides within printed circuit boards involves mass production fabrication techniques to create precision dimensional waveguides, precision alignment tolerances necessary to launch a mode, and effective coupling between adjoining waveguides and devices. An emerging need in which single mode waveguides can be utilized is providing low loss fan out techniques and coupling between on-chip transceiver devices containing Si waveguide structures to traditional single mode optical fiber. A polymer waveguide bridge for Si to glass optical fibers can be implemented using silicone polymers at 1310 nm. Fabricated and measured prototype devices with modeling and simulation analysis are reported for a 12 member 1-D tapered PWG. Recommendations and designs are generated with performance factors such as numerical aperture and alignment tolerances.

Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

PubMed

Dante, V; Del Giudice, P; Mattia, M

2001-01-01

We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Rapid and Low-Cost CRP Measurement by Integrating a Paper-Based Microfluidic Immunoassay with Smartphone (CRP-Chip).

PubMed

Dong, Meili; Wu, Jiandong; Ma, Zimin; Peretz-Soroka, Hagit; Zhang, Michael; Komenda, Paul; Tangri, Navdeep; Liu, Yong; Rigatto, Claudio; Lin, Francis

2017-03-26

Traditional diagnostic tests for chronic diseases are expensive and require a specialized laboratory, therefore limiting their use for point-of-care (PoC) testing. To address this gap, we developed a method for rapid and low-cost C-reactive protein (CRP) detection from blood by integrating a paper-based microfluidic immunoassay with a smartphone (CRP-Chip). We chose CRP for this initial development because it is a strong biomarker of prognosis in chronic heart and kidney disease. The microfluidic immunoassay is realized by lateral flow and gold nanoparticle-based colorimetric detection of the target protein. The test image signal is acquired and analyzed using a commercial smartphone with an attached microlens and a 3D-printed chip-phone interface. The CRP-Chip was validated for detecting CRP in blood samples from chronic kidney disease patients and healthy subjects. The linear detection range of the CRP-Chip is up to 2 μg/mL and the detection limit is 54 ng/mL. The CRP-Chip test result yields high reproducibility and is consistent with the standard ELISA kit. A single CRP-Chip can perform the test in triplicate on a single chip within 15 min for less than 50 US cents of material cost. This CRP-Chip with attractive features of low-cost, fast test speed, and integrated easy operation with smartphones has the potential to enable future clinical PoC chronic disease diagnosis and risk stratification by parallel measurements of a panel of protein biomarkers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Medicaid/CHIP Program; Medicaid Program and Children's Health Insurance Program (CHIP); Changes to the Medicaid Eligibility Quality Control and Payment Error Rate Measurement Programs in Response to the Affordable Care Act. Final rule.

PubMed

2017-07-05

This final rule updates the Medicaid Eligibility Quality Control (MEQC) and Payment Error Rate Measurement (PERM) programs based on the changes to Medicaid and the Children's Health Insurance Program (CHIP) eligibility under the Patient Protection and Affordable Care Act. This rule also implements various other improvements to the PERM program.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

NASA Astrophysics Data System (ADS)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Actuation of digital micro drops by electrowetting on open microfluidic chips fabricated in photolithography.

PubMed

Ko, Hyojin; Lee, Jeong Soo; Jung, Chan-Hee; Choi, Jae-Hak; Kwon, Oh-Sun; Shin, Kwanwoo

2014-08-01

Basic manipulations of discrete liquid drops on opened microfluidic chips based on electrowetting on dielectrics were described. While most developed microfluidic chips are closed systems equipped with a top plate to cover mechanically and to contact electrically to drop samples, our chips are opened systems with a single plate without any electric contact to drops directly. The chips consist of a linear array of patterned electrodes at 1.8 mm pitch was fabricated on a glass plate coated with thin hydrophobic and dielectric layers by using various methods including photolithography, spin coating and ion sputtering. Several actuations such as lateral oscillation, colliding mergence and translational motion for 3-10 μL water drops have been demonstrated satisfactory. All these kinetic performances of opened chips were similar to those of closed chip systems, indicating superiority of a none-contact method for the transport of drops on opened microfluidic chips actuated by using electrowetting technique.

Trapping and Collection of Lymphocytes Using Microspot Array Chip and Magnetic Beads

NASA Astrophysics Data System (ADS)

Hashioka, Shingi; Obata, Tsutomu; Tokimitsu, Yoshiharu; Fujiki, Satoshi; Nakazato, Hiroyoshi; Muraguchi, Atsushi; Kishi, Hiroyuki; Tanino, Katsumi

2006-04-01

A microspot array chip, which has microspots of a magnetic thin film patterned on a glass substrate, was fabricated for trapping individual cells and for measuring their cellular response. The chip was easily fabricated by conventional semiconductor fabrication techniques on a mass production level as a disposable medical device. When a solution of lymphocyte-bound-magnetic beads was poured into the magnetized chip, each lymphocyte was trapped on each microspot of the magnetic thin film. The trapped cells were easily recovered from the chip using a micromanipulator. The micro-spot array chip can be utilized for arraying live cells and for measuring the response of each cell. The chip will be useful for preparing on array of different kinds of cells and for analyzing cellular response at the single cell level. The chip will be particularly useful for detecting antigen-specific B-lymphocytes and antigen-specific antibody complementary deoxyribonucleic acid (cDNA).

Development of an Integrated Chip for Automatic Tracking and Positioning Manipulation for Single Cell Lysis

PubMed Central

Young, Chao-Wang; Hsieh, Jia-Ling; Ay, Chyung

2012-01-01

This study adopted a microelectromechanical fabrication process to design a chip integrated with electroosmotic flow and dielectrophoresis force for single cell lysis. Human histiocytic lymphoma U937 cells were driven rapidly by electroosmotic flow and precisely moved to a specific area for cell lysis. By varying the frequency of AC power, 15 V AC at 1 MHz of frequency configuration achieved 100% cell lysing at the specific area. The integrated chip could successfully manipulate single cells to a specific position and lysis. The overall successful rate of cell tracking, positioning, and cell lysis is 80%. The average speed of cell driving was 17.74 μm/s. This technique will be developed for DNA extraction in biomolecular detection. It can simplify pre-treatment procedures for biotechnological analysis of samples. PMID:22736957

Development of an integrated chip for automatic tracking and positioning manipulation for single cell lysis.

PubMed

Young, Chao-Wang; Hsieh, Jia-Ling; Ay, Chyung

2012-01-01

This study adopted a microelectromechanical fabrication process to design a chip integrated with electroosmotic flow and dielectrophoresis force for single cell lysis. Human histiocytic lymphoma U937 cells were driven rapidly by electroosmotic flow and precisely moved to a specific area for cell lysis. By varying the frequency of AC power, 15 V AC at 1 MHz of frequency configuration achieved 100% cell lysing at the specific area. The integrated chip could successfully manipulate single cells to a specific position and lysis. The overall successful rate of cell tracking, positioning, and cell lysis is 80%. The average speed of cell driving was 17.74 μm/s. This technique will be developed for DNA extraction in biomolecular detection. It can simplify pre-treatment procedures for biotechnological analysis of samples.

On-chip coherent conversion of photonic quantum entanglement between different degrees of freedom

PubMed Central

Feng, Lan-Tian; Zhang, Ming; Zhou, Zhi-Yuan; Li, Ming; Xiong, Xiao; Yu, Le; Shi, Bao-Sen; Guo, Guo-Ping; Dai, Dao-Xin; Ren, Xi-Feng; Guo, Guang-Can

2016-01-01

In the quantum world, a single particle can have various degrees of freedom to encode quantum information. Controlling multiple degrees of freedom simultaneously is necessary to describe a particle fully and, therefore, to use it more efficiently. Here we introduce the transverse waveguide-mode degree of freedom to quantum photonic integrated circuits, and demonstrate the coherent conversion of a photonic quantum state between path, polarization and transverse waveguide-mode degrees of freedom on a single chip. The preservation of quantum coherence in these conversion processes is proven by single-photon and two-photon quantum interference using a fibre beam splitter or on-chip beam splitters. These results provide us with the ability to control and convert multiple degrees of freedom of photons for quantum photonic integrated circuit-based quantum information process. PMID:27321821

On-chip coherent conversion of photonic quantum entanglement between different degrees of freedom.

PubMed

Feng, Lan-Tian; Zhang, Ming; Zhou, Zhi-Yuan; Li, Ming; Xiong, Xiao; Yu, Le; Shi, Bao-Sen; Guo, Guo-Ping; Dai, Dao-Xin; Ren, Xi-Feng; Guo, Guang-Can

2016-06-20

In the quantum world, a single particle can have various degrees of freedom to encode quantum information. Controlling multiple degrees of freedom simultaneously is necessary to describe a particle fully and, therefore, to use it more efficiently. Here we introduce the transverse waveguide-mode degree of freedom to quantum photonic integrated circuits, and demonstrate the coherent conversion of a photonic quantum state between path, polarization and transverse waveguide-mode degrees of freedom on a single chip. The preservation of quantum coherence in these conversion processes is proven by single-photon and two-photon quantum interference using a fibre beam splitter or on-chip beam splitters. These results provide us with the ability to control and convert multiple degrees of freedom of photons for quantum photonic integrated circuit-based quantum information process.

Process-Hardened, Multi-Analyte Sensor for Characterizing Rocket Plume Constituents

NASA Technical Reports Server (NTRS)

Goswami, Kisholoy

2011-01-01

A multi-analyte sensor was developed that enables simultaneous detection of rocket engine combustion-product molecules in a launch-vehicle ground test stand. The sensor was developed using a pin-printing method by incorporating multiple sensor elements on a single chip. It demonstrated accurate and sensitive detection of analytes such as carbon dioxide, carbon monoxide, kerosene, isopropanol, and ethylene from a single measurement. The use of pin-printing technology enables high-volume fabrication of the sensor chip, which will ultimately eliminate the need for individual sensor calibration since many identical sensors are made in one batch. Tests were performed using a single-sensor chip attached to a fiber-optic bundle. The use of a fiber bundle allows placement of the opto-electronic readout device at a place remote from the test stand. The sensors are rugged for operation in harsh environments.

Ag2S atomic switch-based `tug of war' for decision making

NASA Astrophysics Data System (ADS)

Lutz, C.; Hasegawa, T.; Chikyow, T.

2016-07-01

For a computing process such as making a decision, a software controlled chip of several transistors is necessary. Inspired by how a single cell amoeba decides its movements, the theoretical `tug of war' computing model was proposed but not yet implemented in an analogue device suitable for integrated circuits. Based on this model, we now developed a new electronic element for decision making processes, which will have no need for prior programming. The devices are based on the growth and shrinkage of Ag filaments in α-Ag2+δS gap-type atomic switches. Here we present the adapted device design and the new materials. We demonstrate the basic `tug of war' operation by IV-measurements and Scanning Electron Microscopy (SEM) observation. These devices could be the base for a CMOS-free new computer architecture.For a computing process such as making a decision, a software controlled chip of several transistors is necessary. Inspired by how a single cell amoeba decides its movements, the theoretical `tug of war' computing model was proposed but not yet implemented in an analogue device suitable for integrated circuits. Based on this model, we now developed a new electronic element for decision making processes, which will have no need for prior programming. The devices are based on the growth and shrinkage of Ag filaments in α-Ag2+δS gap-type atomic switches. Here we present the adapted device design and the new materials. We demonstrate the basic `tug of war' operation by IV-measurements and Scanning Electron Microscopy (SEM) observation. These devices could be the base for a CMOS-free new computer architecture. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00690f

Development of integrated semiconductor optical sensors for functional brain imaging

NASA Astrophysics Data System (ADS)

Lee, Thomas T.

Optical imaging of neural activity is a widely accepted technique for imaging brain function in the field of neuroscience research, and has been used to study the cerebral cortex in vivo for over two decades. Maps of brain activity are obtained by monitoring intensity changes in back-scattered light, called Intrinsic Optical Signals (IOS), that correspond to fluctuations in blood oxygenation and volume associated with neural activity. Current imaging systems typically employ bench-top equipment including lamps and CCD cameras to study animals using visible light. Such systems require the use of anesthetized or immobilized subjects with craniotomies, which imposes limitations on the behavioral range and duration of studies. The ultimate goal of this work is to overcome these limitations by developing a single-chip semiconductor sensor using arrays of sources and detectors operating at near-infrared (NIR) wavelengths. A single-chip implementation, combined with wireless telemetry, will eliminate the need for immobilization or anesthesia of subjects and allow in vivo studies of free behavior. NIR light offers additional advantages because it experiences less absorption in animal tissue than visible light, which allows for imaging through superficial tissues. This, in turn, reduces or eliminates the need for traumatic surgery and enables long-term brain-mapping studies in freely-behaving animals. This dissertation concentrates on key engineering challenges of implementing the sensor. This work shows the feasibility of using a GaAs-based array of vertical-cavity surface emitting lasers (VCSELs) and PIN photodiodes for IOS imaging. I begin with in-vivo studies of IOS imaging through the skull in mice, and use these results along with computer simulations to establish minimum performance requirements for light sources and detectors. I also evaluate the performance of a current commercial VCSEL for IOS imaging, and conclude with a proposed prototype sensor.

High-performance, scalable optical network-on-chip architectures

NASA Astrophysics Data System (ADS)

Tan, Xianfang

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption.

Generating single microwave photons in a circuit.

PubMed

Houck, A A; Schuster, D I; Gambetta, J M; Schreier, J A; Johnson, B R; Chow, J M; Frunzio, L; Majer, J; Devoret, M H; Girvin, S M; Schoelkopf, R J

2007-09-20

Microwaves have widespread use in classical communication technologies, from long-distance broadcasts to short-distance signals within a computer chip. Like all forms of light, microwaves, even those guided by the wires of an integrated circuit, consist of discrete photons. To enable quantum communication between distant parts of a quantum computer, the signals must also be quantum, consisting of single photons, for example. However, conventional sources can generate only classical light, not single photons. One way to realize a single-photon source is to collect the fluorescence of a single atom. Early experiments measured the quantum nature of continuous radiation, and further advances allowed triggered sources of photons on demand. To allow efficient photon collection, emitters are typically placed inside optical or microwave cavities, but these sources are difficult to employ for quantum communication on wires within an integrated circuit. Here we demonstrate an on-chip, on-demand single-photon source, where the microwave photons are injected into a wire with high efficiency and spectral purity. This is accomplished in a circuit quantum electrodynamics architecture, with a microwave transmission line cavity that enhances the spontaneous emission of a single superconducting qubit. When the qubit spontaneously emits, the generated photon acts as a flying qubit, transmitting the quantum information across a chip. We perform tomography of both the qubit and the emitted photons, clearly showing that both the quantum phase and amplitude are transferred during the emission. Both the average power and voltage of the photon source are characterized to verify performance of the system. This single-photon source is an important addition to a rapidly growing toolbox for quantum optics on a chip.

A monolithically integrated polarization entangled photon pair source on a silicon chip

PubMed Central

Matsuda, Nobuyuki; Le Jeannic, Hanna; Fukuda, Hiroshi; Tsuchizawa, Tai; Munro, William John; Shimizu, Kaoru; Yamada, Koji; Tokura, Yasuhiro; Takesue, Hiroki

2012-01-01

Integrated photonic circuits are one of the most promising platforms for large-scale photonic quantum information systems due to their small physical size and stable interferometers with near-perfect lateral-mode overlaps. Since many quantum information protocols are based on qubits defined by the polarization of photons, we must develop integrated building blocks to generate, manipulate, and measure the polarization-encoded quantum state on a chip. The generation unit is particularly important. Here we show the first integrated polarization-entangled photon pair source on a chip. We have implemented the source as a simple and stable silicon-on-insulator photonic circuit that generates an entangled state with 91 ± 2% fidelity. The source is equipped with versatile interfaces for silica-on-silicon or other types of waveguide platforms that accommodate the polarization manipulation and projection devices as well as pump light sources. Therefore, we are ready for the full-scale implementation of photonic quantum information systems on a chip. PMID:23150781

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

PubMed

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

2015-01-12

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip

PubMed Central

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T.; Xuan, Yi; Leaird, Daniel E.; Wang, Xi; Gan, Fuwan; Weiner, Andrew M.; Qi, Minghao

2015-01-01

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics. PMID:25581847

Lensless high-resolution on-chip optofluidic microscopes for Caenorhabditis elegans and cell imaging

PubMed Central

Cui, Xiquan; Lee, Lap Man; Heng, Xin; Zhong, Weiwei; Sternberg, Paul W.; Psaltis, Demetri; Yang, Changhuei

2008-01-01

Low-cost and high-resolution on-chip microscopes are vital for reducing cost and improving efficiency for modern biomedicine and bioscience. Despite the needs, the conventional microscope design has proven difficult to miniaturize. Here, we report the implementation and application of two high-resolution (≈0.9 μm for the first and ≈0.8 μm for the second), lensless, and fully on-chip microscopes based on the optofluidic microscopy (OFM) method. These systems abandon the conventional microscope design, which requires expensive lenses and large space to magnify images, and instead utilizes microfluidic flow to deliver specimens across array(s) of micrometer-size apertures defined on a metal-coated CMOS sensor to generate direct projection images. The first system utilizes a gravity-driven microfluidic flow for sample scanning and is suited for imaging elongate objects, such as Caenorhabditis elegans; and the second system employs an electrokinetic drive for flow control and is suited for imaging cells and other spherical/ellipsoidal objects. As a demonstration of the OFM for bioscience research, we show that the prototypes can be used to perform automated phenotype characterization of different Caenorhabditis elegans mutant strains, and to image spores and single cellular entities. The optofluidic microscope design, readily fabricable with existing semiconductor and microfluidic technologies, offers low-cost and highly compact imaging solutions. More functionalities, such as on-chip phase and fluorescence imaging, can also be readily adapted into OFM systems. We anticipate that the OFM can significantly address a range of biomedical and bioscience needs, and engender new microscope applications. PMID:18663227

Programmable bio-nano-chip system: a flexible point-of-care platform for bioscience and clinical measurements

PubMed Central

McRae, Michael. P.; Simmons, Glennon. W.; Wong, Jorge; Shadfan, Basil; Gopalkrishnan, Sanjiv; Christodoulides, Nicolaos

2015-01-01

The development of integrated instrumentation for universal bioassay systems serves as a key goal for the lab-on-a-chip community. The programmable bio-nano-chip (p-BNC) system is a versatile multiplexed and multiclass chemical- and bio-sensing system for bioscience and clinical measurements. The system is comprised of two main components, a disposable cartridge and a portable analyzer. The customizable single-use plastic cartridges, which now can be manufactured in high volumes using injection molding, are designed for analytical performance, ease of use, reproducibility, and low cost. These labcard devices implement high surface area nano-structured biomarker capture elements that enable high performance signaling and are index matched to real-world biological specimens. This detection modality, along with the convenience of on-chip fluid storage in blisters and self-contained waste, represents a standard process to digitize biological signatures at the point-of-care. A companion portable analyzer prototype has been developed to integrate fluid motivation, optical detection, and automated data analysis, and it serves as the human interface for complete assay automation. In this report, we provide a systems-level perspective of the p-BNC universal biosensing platform with an emphasis on flow control, device integration, and automation. To demonstrate the flexibility of the p-BNC, we distinguish diseased and non-case patients across three significant disease applications: prostate cancer, ovarian cancer, and acute myocardial infarction. Progress towards developing a rapid 7 minute myoglobin assay is presented using the fully automated p-BNC system. PMID:26308851

Design of three-phased SPWM based on AT89C52

NASA Astrophysics Data System (ADS)

Wu, Xiaorui

2018-05-01

According to the AT89C52 and the area equivalent principle, a three phase SPWM algorithm based on the 8 bit single chip is obtained. Through computer programming, three-phase SPWM wave generated by a single chip microcomputer is applied to the circuit of the static reactive power generator. The result shows that this method is feasible and can reduce the cost of SVG.

[3-channels data acquisition system based on single-chip-microcomputer used in the measurement of coronary sinus blood flow].

PubMed

Li, Z; Fan, Y; Chen, G

1999-07-01

The coronary sinus blood flow can be figured out, which based on the principle of thermodilution, so long as gets the temperature of blood, indicator and mixture of blood and indicator respectively. This system is a smart slave module with single-chip-microcomputer. The structure and principles of hardware and the flow chart of software are described in detail.

Towards Single-Step Biofabrication of Organs on a Chip via 3D Printing.

PubMed

Knowlton, Stephanie; Yenilmez, Bekir; Tasoglu, Savas

2016-09-01

Organ-on-a-chip engineering employs microfabrication of living tissues within microscale fluid channels to create constructs that closely mimic human organs. With the advent of 3D printing, we predict that single-step fabrication of these devices will enable rapid design and cost-effective iterations in the development stage, facilitating rapid innovation in this field. Copyright © 2016 Elsevier Ltd. All rights reserved.

Hybridization of Environmental Microbial Community Nucleic Acids by GeoChip.

PubMed

Van Nostrand, Joy D; Yin, Huaqin; Wu, Liyou; Yuan, Tong; Zhou, Jizhong

2016-01-01

Functional gene arrays, like the GeoChip, allow for the study of tens of thousands of genes in a single assay. The GeoChip array (5.0) contains probes for genes involved in geochemical cycling (N, C, S, and P), metal homeostasis, stress response, organic contaminant degradation, antibiotic resistance, secondary metabolism, and virulence factors as well as genes specific for fungi, protists, and viruses. Here, we briefly describe GeoChip design strategies (gene selection and probe design) and discuss minimum quantity and quality requirements for nucleic acids. We then provide detailed protocols for amplification, labeling, and hybridization of samples to the GeoChip.

Highly specific detection of genetic modification events using an enzyme-linked probe hybridization chip.

PubMed

Zhang, M Z; Zhang, X F; Chen, X M; Chen, X; Wu, S; Xu, L L

2015-08-10

The enzyme-linked probe hybridization chip utilizes a method based on ligase-hybridizing probe chip technology, with the principle of using thio-primers for protection against enzyme digestion, and using lambda DNA exonuclease to cut multiple PCR products obtained from the sample being tested into single-strand chains for hybridization. The 5'-end amino-labeled probe was fixed onto the aldehyde chip, and hybridized with the single-stranded PCR product, followed by addition of a fluorescent-modified probe that was then enzymatically linked with the adjacent, substrate-bound probe in order to achieve highly specific, parallel, and high-throughput detection. Specificity and sensitivity testing demonstrated that enzyme-linked probe hybridization technology could be applied to the specific detection of eight genetic modification events at the same time, with a sensitivity reaching 0.1% and the achievement of accurate, efficient, and stable results.

Quantum Logic with Cavity Photons From Single Atoms.

PubMed

Holleczek, Annemarie; Barter, Oliver; Rubenok, Allison; Dilley, Jerome; Nisbet-Jones, Peter B R; Langfahl-Klabes, Gunnar; Marshall, Graham D; Sparrow, Chris; O'Brien, Jeremy L; Poulios, Konstantinos; Kuhn, Axel; Matthews, Jonathan C F

2016-07-08

We demonstrate quantum logic using narrow linewidth photons that are produced with an a priori nonprobabilistic scheme from a single ^{87}Rb atom strongly coupled to a high-finesse cavity. We use a controlled-not gate integrated into a photonic chip to entangle these photons, and we observe nonclassical correlations between photon detection events separated by periods exceeding the travel time across the chip by 3 orders of magnitude. This enables quantum technology that will use the properties of both narrow-band single photon sources and integrated quantum photonics.

Electro-optic routing of photons from a single quantum dot in photonic integrated circuits

NASA Astrophysics Data System (ADS)

Midolo, Leonardo; Hansen, Sofie L.; Zhang, Weili; Papon, Camille; Schott, Rüdiger; Ludwig, Arne; Wieck, Andreas D.; Lodahl, Peter; Stobbe, Søren

2017-12-01

Recent breakthroughs in solid-state photonic quantum technologies enable generating and detecting single photons with near-unity efficiency as required for a range of photonic quantum technologies. The lack of methods to simultaneously generate and control photons within the same chip, however, has formed a main obstacle to achieving efficient multi-qubit gates and to harness the advantages of chip-scale quantum photonics. Here we propose and demonstrate an integrated voltage-controlled phase shifter based on the electro-optic effect in suspended photonic waveguides with embedded quantum emitters. The phase control allows building a compact Mach-Zehnder interferometer with two orthogonal arms, taking advantage of the anisotropic electro-optic response in gallium arsenide. Photons emitted by single self-assembled quantum dots can be actively routed into the two outputs of the interferometer. These results, together with the observed sub-microsecond response time, constitute a significant step towards chip-scale single-photon-source de-multiplexing, fiber-loop boson sampling, and linear optical quantum computing.

On-chip interference of single photons from an embedded quantum dot and an external laser

DOE Office of Scientific and Technical Information (OSTI.GOV)

Prtljaga, N., E-mail: n.prtljaga@sheffield.ac.uk; Bentham, C.; O'Hara, J.

2016-06-20

In this work, we demonstrate the on-chip two-photon interference between single photons emitted by a single self-assembled InGaAs quantum dot and an external laser. The quantum dot is embedded within one arm of an air-clad directional coupler which acts as a beam-splitter for incoming light. Photons originating from an attenuated external laser are coupled to the second arm of the beam-splitter and then combined with the quantum dot photons, giving rise to two-photon quantum interference between dissimilar sources. We verify the occurrence of on-chip Hong-Ou-Mandel interference by cross-correlating the optical signal from the separate output ports of the directional coupler.more » This experimental approach allows us to use a classical light source (laser) to assess in a single step the overall device performance in the quantum regime and probe quantum dot photon indistinguishability on application realistic time scales.« less

Enabling Large Focal Plane Arrays through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Costen, Nick; Benford, Dominic J.

2012-01-01

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

PubMed

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

Implementation of a pulse coupled neural network in FPGA.

PubMed

Waldemark, J; Millberg, M; Lindblad, T; Waldemark, K; Becanovic, V

2000-06-01

The Pulse Coupled neural network, PCNN, is a biologically inspired neural net and it can be used in various image analysis applications, e.g. time-critical applications in the field of image pre-processing like segmentation, filtering, etc. a VHDL implementation of the PCNN targeting FPGA was undertaken and the results presented here. The implementation contains many interesting features. By pipelining the PCNN structure a very high throughput of 55 million neuron iterations per second could be achieved. By making the coefficients re-configurable during operation, a complete recognition system could be implemented on one, or maybe two, chip(s). Reconsidering the ranges and resolutions of the constants may save a lot of hardware, since the higher resolution requires larger multipliers, adders, memories etc.

Lab on chip microdevices for cellular mechanotransduction in urothelial cells

NASA Astrophysics Data System (ADS)

Maziz, A.; Guan, N.; Svennersten, K.; Hallén-Grufman, K.; Jager, Edwin W. H.

2016-04-01

Cellular mechanotransduction is crucial for physiological function in the lower urinary tract. The bladder is highly dependent on the ability to sense and process mechanical inputs, illustrated by the regulated filling and voiding of the bladder. However, the mechanisms by which the bladder integrates mechanical inputs, such as intravesicular pressure, and controls the smooth muscles, remain unknown. To date no tools exist that satisfactorily mimic in vitro the dynamic micromechanical events initiated e.g. by an emerging inflammatory process or a growing tumour mass in the urinary tract. More specifically, there is a need for tools to study these events on a single cell level or in a small population of cells. We have developed a micromechanical stimulation chip that can apply physiologically relevant mechanical stimuli to single cells to study mechanosensitive cells in the urinary tract. The chips comprise arrays of microactuators based on the electroactive polymer polypyrrole (PPy). PPy offers unique possibilities and is a good candidate to provide such physiological mechanical stimulation, since it is driven at low voltages, is biocompatible, and can be microfabricated. The PPy microactuators can provide mechanical stimulation at different strains and/or strain rates to single cells or clusters of cells, including controls, all integrated on one single chip, without the need to preprepare the cells. This paper reports initial results on the mechano-response of urothelial cells using the micromechanical stimulation chips. We show that urothelial cells are viable on our microdevices and do respond with intracellular Ca2+ increase when subjected to a micro-mechanical stimulation.

A single-chip 32-channel analog beamformer with 4-ns delay resolution and 768-ns maximum delay range for ultrasound medical imaging with a linear array transducer.

PubMed

Um, Ji-Yong; Kim, Yoon-Jee; Cho, Seong-Eun; Chae, Min-Kyun; Kim, Byungsub; Sim, Jae-Yoon; Park, Hong-June

2015-02-01

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- μ m CMOS process with an active area of 16 mm (2). The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.

Lab-on-a-chip technologies for proteomic analysis from isolated cells.

PubMed

Sedgwick, H; Caron, F; Monaghan, P B; Kolch, W; Cooper, J M

2008-10-06

Lab-on-a-chip systems offer a versatile environment in which low numbers of cells and molecules can be manipulated, captured, detected and analysed. We describe here a microfluidic device that allows the isolation, electroporation and lysis of single cells. A431 human epithelial carcinoma cells, expressing a green fluorescent protein-labelled actin, were trapped by dielectrophoresis within an integrated lab-on-a-chip device containing saw-tooth microelectrodes. Using these same trapping electrodes, on-chip electroporation was performed, resulting in cell lysis. Protein release was monitored by confocal fluorescence microscopy.

System-on-Chip Design and Implementation

ERIC Educational Resources Information Center

Brackenbury, L. E. M.; Plana, L. A.; Pepper, J.

2010-01-01

The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant…

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

NASA Astrophysics Data System (ADS)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

VLSI chips for vision-based vehicle guidance

NASA Astrophysics Data System (ADS)

Masaki, Ichiro

1994-02-01

Sensor-based vehicle guidance systems are gathering rapidly increasing interest because of their potential for increasing safety, convenience, environmental friendliness, and traffic efficiency. Examples of applications include intelligent cruise control, lane following, collision warning, and collision avoidance. This paper reviews the research trends in vision-based vehicle guidance with an emphasis on VLSI chip implementations of the vision systems. As an example of VLSI chips for vision-based vehicle guidance, a stereo vision system is described in detail.

Ultra-low-power wireless transmitter for neural prostheses with modified pulse position modulation.

PubMed

Goodarzy, Farhad; Skafidas, Stan E

2014-01-01

An ultra-low-power wireless transmitter for embedded bionic systems is proposed, which achieves 40 pJ/b energy efficiency and delivers 500 kb/s data using the medical implant communication service frequency band (402-405 MHz). It consumes a measured peak power of 200 µW from a 1.2 V supply while occupying an active area of 0.0016 mm(2) in a 130 nm technology. A modified pulse position modulation technique called saturated amplified signal is proposed and implemented, which can reduce the overall and per bit transferred power consumption of the transmitter while reducing the complexity of the transmitter architectures, and hence potentially shrinking the size of the implemented circuitry. The design is capable of being fully integrated on single-chip solutions for surgically implanted bionic systems, wearable devices and neural embedded systems.

Implementation of kernels on the Maestro processor

NASA Astrophysics Data System (ADS)

Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

Optical Manipulation of Single Magnetic Beads in a Microwell Array on a Digital Microfluidic Chip.

PubMed

Decrop, Deborah; Brans, Toon; Gijsenbergh, Pieter; Lu, Jiadi; Spasic, Dragana; Kokalj, Tadej; Beunis, Filip; Goos, Peter; Puers, Robert; Lammertyn, Jeroen

2016-09-06

The detection of single molecules in magnetic microbead microwell array formats revolutionized the development of digital bioassays. However, retrieval of individual magnetic beads from these arrays has not been realized until now despite having great potential for studying captured targets at the individual level. In this paper, optical tweezers were implemented on a digital microfluidic platform for accurate manipulation of single magnetic beads seeded in a microwell array. Successful optical trapping of magnetic beads was found to be dependent on Brownian motion of the beads, suggesting a 99% chance of trapping a vibrating bead. A tailor-made experimental design was used to screen the effect of bead type, ionic buffer strength, surfactant type, and concentration on the Brownian activity of beads in microwells. With the optimal conditions, the manipulation of magnetic beads was demonstrated by their trapping, retrieving, transporting, and repositioning to a desired microwell on the array. The presented platform combines the strengths of digital microfluidics, digital bioassays, and optical tweezers, resulting in a powerful dynamic microwell array system for single molecule and single cell studies.

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS circuits with 500 nm thick Si, operating around 3.8 µm wavelength. Results on facet coupling and sub-wavelength engineered grating coupler solutions in the mid-IR regime will be compared.

A one-step strategy for ultra-fast and low-cost mass production of plastic membrane microfluidic chips.

PubMed

Hu, Chong; Lin, Sheng; Li, Wanbo; Sun, Han; Chen, Yangfan; Chan, Chiu-Wing; Leung, Chung-Hang; Ma, Dik-Lung; Wu, Hongkai; Ren, Kangning

2016-10-05

An ultra-fast, extremely cost-effective, and environmentally friendly method was developed for fabricating flexible microfluidic chips with plastic membranes. With this method, we could fabricate plastic microfluidic chips rapidly (within 12 seconds per piece) at an extremely low cost (less than $0.02 per piece). We used a heated perfluoropolymer perfluoroalkoxy (often called Teflon PFA) solid stamp to press a pile of two pieces of plastic membranes, low density polyethylene (LDPE) and polyethylene terephthalate (PET) coated with an ethylene-vinyl acetate copolymer (EVA). During the short period of contact with the heated PFA stamp, the pressed area of the membranes permanently bonded, while the LDPE membrane spontaneously rose up at the area not pressed, forming microchannels automatically. These two regions were clearly distinguishable even at the micrometer scale so we were able to fabricate microchannels with widths down to 50 microns. This method combines the two steps in the conventional strategy for microchannel fabrication, generating microchannels and sealing channels, into a single step. The production is a green process without using any solvent or generating any waste. Also, the chips showed good resistance against the absorption of Rhodamine 6G, oligonucleotides, and green fluorescent protein (GFP). We demonstrated some typical microfluidic manipulations with the flexible plastic membrane chips, including droplet formation, on-chip capillary electrophoresis, and peristaltic pumping for quantitative injection of samples and reagents. In addition, we demonstrated convenient on-chip detection of lead ions in water samples by a peristaltic-pumping design, as an example of the application of the plastic membrane chips in a resource-limited environment. Due to the high speed and low cost of the fabrication process, this single-step method will facilitate the mass production of microfluidic chips and commercialization of microfluidic technologies.

Color design model of high color rendering index white-light LED module.

PubMed

Ying, Shang-Ping; Fu, Han-Kuei; Hsieh, Hsin-Hsin; Hsieh, Kun-Yang

2017-05-10

The traditional white-light light-emitting diode (LED) is packaged with a single chip and a single phosphor but has a poor color rendering index (CRI). The next-generation package comprises two chips and a single phosphor, has a high CRI, and retains high luminous efficacy. This study employs two chips and two phosphors to improve the diode's color tunability with various proportions of two phosphors and various densities of phosphor in the silicone used. A color design model is established for color fine-tuning of the white-light LED module. The maximum difference between the measured and color-design-model simulated CIE 1931 color coordinates is approximately 0.0063 around a correlated color temperature (CCT) of 2500 K. This study provides a rapid method to obtain the color fine-tuning of a white-light LED module with a high CRI and luminous efficacy.

Single-Mode Near-Infrared Lasing in a GaAsSb-Based Nanowire Superlattice at Room Temperature

NASA Astrophysics Data System (ADS)

Ren, Dingding; Ahtapodov, Lyubomir; Nilsen, Julie S.; Yang, Jianfeng; Gustafsson, Anders; Huh, Junghwan; Conibeer, Gavin J.; van Helvoort, Antonius T. J.; Fimland, Bjørn-Ove; Weman, Helge

2018-04-01

Semiconductor nanowire lasers can produce guided coherent light emission with miniaturized geometry, bringing about new possibility for a variety of applications including nanophotonic circuits, optical sensing, and on-chip and chip-to-chip optical communications. Here, we report on the realization of single-mode room-temperature lasing from 890 nm to 990 nm utilizing a novel design of single nanowires with GaAsSb-based multiple superlattices as gain medium under optical pumping. The wavelength tunability with comprehensively enhanced lasing performance is shown to result from the unique nanowire structure with efficient gain materials, which delivers a lasing quality factor as high as 1250, a reduced lasing threshold ~ 6 kW cm-2 and a high characteristic temperature ~ 129 K. These results present a major advancement for the design and synthesis of nanowire laser structures, which can pave the way towards future nanoscale integrated optoelectronic systems with stunning performance.

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping.

PubMed

Faigle, Christoph; Lautenschläger, Franziska; Whyte, Graeme; Homewood, Philip; Martín-Badosa, Estela; Guck, Jochen

2015-03-07

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custom-built optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

DOE and JAEA Field Trial of the Single Chip Shift Register (SCSR)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Newell, Matthew R.

2016-03-23

Los Alamos National Laboratories (LANL) has recently developed a new data acquisition system for multiplicity analysis of neutron detector pulse streams. This new technology, the Single Chip Shift Register (SCSR), places the entire data acquisition system along with the communications hardware onto a single chip. This greatly simplifies the instrument and reduces the size. The SCSR is designed to be mounted into the neutron detector head alongside the instrument amplifiers. The user’s computer connects via USB directly to the neutron detector eliminating the external data acquisition electronics entirely. JAEA, through the INSEP program, asked LANL to demonstrate the functionality ofmore » the SCSR in Tokai using the JAEA Epithermal Neutron Multiplicity Counter, ENMC. In late September of 2015 LANL traveled to Tokai to install, demonstrate and uninstall the SCSR in the ENMC. This report documents the results of that field trial.« less

Tracking Silent Hypersensitivity Reactions to Asparaginase during Leukemia Therapy Using Single-Chip Indirect Plasmonic and Fluorescence Immunosensing.

PubMed

Charbonneau, David M; Breault-Turcot, Julien; Sinnett, Daniel; Krajinovic, Maja; Leclerc, Jean-Marie; Masson, Jean-François; Pelletier, Joelle N

2017-12-22

Microbial asparaginase is an essential component of chemotherapy for the treatment of childhood acute lymphoblastic leukemia (cALL). Silent hypersensitivity reactions to this microbial enzyme need to be monitored accurately during treatment to avoid adverse effects of the drug and its silent inactivation. Here, we present a dual-response anti-asparaginase sensor that combines indirect SPR and fluorescence on a single chip to perform ELISA-type immunosensing, and correlate measurements with classical ELISA. Analysis of serum samples from children undergoing cALL therapy revealed a clear correlation between single-chip indirect SPR/fluorescence immunosensing and ELISA used in clinical settings (R 2 > 0.9). We also report that the portable SPR/fluorescence system had a better sensitivity than classical ELISA to detect antibodies in clinical samples with low antigenicity. This work demonstrates the reliability of dual sensing for monitoring clinically relevant antibody titers in clinical serum samples.

A robotics platform for automated batch fabrication of high density, microfluidics-based DNA microarrays, with applications to single cell, multiplex assays of secreted proteins

NASA Astrophysics Data System (ADS)

Ahmad, Habib; Sutherland, Alex; Shin, Young Shik; Hwang, Kiwook; Qin, Lidong; Krom, Russell-John; Heath, James R.

2011-09-01

Microfluidics flow-patterning has been utilized for the construction of chip-scale miniaturized DNA and protein barcode arrays. Such arrays have been used for specific clinical and fundamental investigations in which many proteins are assayed from single cells or other small sample sizes. However, flow-patterned arrays are hand-prepared, and so are impractical for broad applications. We describe an integrated robotics/microfluidics platform for the automated preparation of such arrays, and we apply it to the batch fabrication of up to eighteen chips of flow-patterned DNA barcodes. The resulting substrates are comparable in quality with hand-made arrays and exhibit excellent substrate-to-substrate consistency. We demonstrate the utility and reproducibility of robotics-patterned barcodes by utilizing two flow-patterned chips for highly parallel assays of a panel of secreted proteins from single macrophage cells.

A robotics platform for automated batch fabrication of high density, microfluidics-based DNA microarrays, with applications to single cell, multiplex assays of secreted proteins

PubMed Central

Ahmad, Habib; Sutherland, Alex; Shin, Young Shik; Hwang, Kiwook; Qin, Lidong; Krom, Russell-John; Heath, James R.

2011-01-01

Microfluidics flow-patterning has been utilized for the construction of chip-scale miniaturized DNA and protein barcode arrays. Such arrays have been used for specific clinical and fundamental investigations in which many proteins are assayed from single cells or other small sample sizes. However, flow-patterned arrays are hand-prepared, and so are impractical for broad applications. We describe an integrated robotics/microfluidics platform for the automated preparation of such arrays, and we apply it to the batch fabrication of up to eighteen chips of flow-patterned DNA barcodes. The resulting substrates are comparable in quality with hand-made arrays and exhibit excellent substrate-to-substrate consistency. We demonstrate the utility and reproducibility of robotics-patterned barcodes by utilizing two flow-patterned chips for highly parallel assays of a panel of secreted proteins from single macrophage cells. PMID:21974603

A robotics platform for automated batch fabrication of high density, microfluidics-based DNA microarrays, with applications to single cell, multiplex assays of secreted proteins.

PubMed

Ahmad, Habib; Sutherland, Alex; Shin, Young Shik; Hwang, Kiwook; Qin, Lidong; Krom, Russell-John; Heath, James R

2011-09-01

Microfluidics flow-patterning has been utilized for the construction of chip-scale miniaturized DNA and protein barcode arrays. Such arrays have been used for specific clinical and fundamental investigations in which many proteins are assayed from single cells or other small sample sizes. However, flow-patterned arrays are hand-prepared, and so are impractical for broad applications. We describe an integrated robotics/microfluidics platform for the automated preparation of such arrays, and we apply it to the batch fabrication of up to eighteen chips of flow-patterned DNA barcodes. The resulting substrates are comparable in quality with hand-made arrays and exhibit excellent substrate-to-substrate consistency. We demonstrate the utility and reproducibility of robotics-patterned barcodes by utilizing two flow-patterned chips for highly parallel assays of a panel of secreted proteins from single macrophage cells. © 2011 American Institute of Physics

Effect of thermal cycling ramp rate on CSP assembly reliability

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2001-01-01

A JPL-led chip scale package consortium of enterprises recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages for a variety of projects. The experience of the consortium in building more than 150 test vehicle assemblies, single and double sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document.

A Low Cost Single Chip VDL Compatible Transceiver ASIC

NASA Technical Reports Server (NTRS)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

Smart single-chip gas sensor microsystem

NASA Astrophysics Data System (ADS)

Hagleitner, C.; Hierlemann, A.; Lange, D.; Kummer, A.; Kerness, N.; Brand, O.; Baltes, H.

2001-11-01

Research activity in chemical gas sensing is currently directed towards the search for highly selective (bio)chemical layer materials, and to the design of arrays consisting of different partially selective sensors that permit subsequent pattern recognition and multi-component analysis. Simultaneous use of various transduction platforms has been demonstrated, and the rapid development of integrated-circuit technology has facilitated the fabrication of planar chemical sensors and sensors based on three-dimensional microelectromechanical systems. Complementary metal-oxide silicon processes have previously been used to develop gas sensors based on metal oxides and acoustic-wave-based sensor devices. Here we combine several of these developments to fabricate a smart single-chip chemical microsensor system that incorporates three different transducers (mass-sensitive, capacitive and calorimetric), all of which rely on sensitive polymeric layers to detect airborne volatile organic compounds. Full integration of the microelectronic and micromechanical components on one chip permits control and monitoring of the sensor functions, and enables on-chip signal amplification and conditioning that notably improves the overall sensor performance. The circuitry also includes analog-to-digital converters, and an on-chip interface to transmit the data to off-chip recording units. We expect that our approach will provide a basis for the further development and optimization of gas microsystems.

Standby Power Management Architecture for Deep-Submicron Systems

DTIC Science & Technology

2006-05-19

Driver 61 5.1 Quark PicoNode System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 Power Domain Architecture... Quark system protocol stack. . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 Quark system block diagram...the implementation of the chip using an industry-standard place and route design flow. Lastly some measurements from the chip are presented. 5.1 Quark

Identifying EGFR-Expressed Cells and Detecting EGFR Multi-Mutations at Single-Cell Level by Microfluidic Chip

NASA Astrophysics Data System (ADS)

Li, Ren; Zhou, Mingxing; Li, Jine; Wang, Zihua; Zhang, Weikai; Yue, Chunyan; Ma, Yan; Peng, Hailin; Wei, Zewen; Hu, Zhiyuan

2018-03-01

EGFR mutations companion diagnostics have been proved to be crucial for the efficacy of tyrosine kinase inhibitor targeted cancer therapies. To uncover multiple mutations occurred in minority of EGFR-mutated cells, which may be covered by the noises from majority of un-mutated cells, is currently becoming an urgent clinical requirement. Here we present the validation of a microfluidic-chip-based method for detecting EGFR multi-mutations at single-cell level. By trapping and immunofluorescently imaging single cells in specifically designed silicon microwells, the EGFR-expressed cells were easily identified. By in situ lysing single cells, the cell lysates of EGFR-expressed cells were retrieved without cross-contamination. Benefited from excluding the noise from cells without EGFR expression, the simple and cost-effective Sanger's sequencing, but not the expensive deep sequencing of the whole cell population, was used to discover multi-mutations. We verified the new method with precisely discovering three most important EGFR drug-related mutations from a sample in which EGFR-mutated cells only account for a small percentage of whole cell population. The microfluidic chip is capable of discovering not only the existence of specific EGFR multi-mutations, but also other valuable single-cell-level information: on which specific cells the mutations occurred, or whether different mutations coexist on the same cells. This microfluidic chip constitutes a promising method to promote simple and cost-effective Sanger's sequencing to be a routine test before performing targeted cancer therapy.[Figure not available: see fulltext.

Thread-Level Parallelization and Optimization of NWChem for the Intel MIC Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shan, Hongzhang; Williams, Samuel; Jong, Wibe de

In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors' greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments.more » In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in tt native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant effort was required to safely and efficiently thread the TEXAS integral package when constructing the Fock matrix. Ultimately, our new MPI OpenMP hybrid implementations attain up to 65x better performance for the triples part of the CCSD(T) due in large part to the fact that the limited on-card memory limits the existing MPI implementation to a single process per card. Additionally, we obtain up to 1.6x better performance on Fock matrix constructions when compared with the best MPI implementations running multiple processes per card.« less

Thread-level parallelization and optimization of NWChem for the Intel MIC architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shan, Hongzhang; Williams, Samuel; de Jong, Wibe

In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors' greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments.more » In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant e ort was required to safely and efeciently thread the TEXAS integral package when constructing the Fock matrix. Ultimately, our new MPI+OpenMP hybrid implementations attain up to 65× better performance for the triples part of the CCSD(T) due in large part to the fact that the limited on-card memory limits the existing MPI implementation to a single process per card. Additionally, we obtain up to 1.6× better performance on Fock matrix constructions when compared with the best MPI implementations running multiple processes per card.« less

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

3D Silicon Coincidence Avalanche Detector (3D-SiCAD) for charged particle detection

NASA Astrophysics Data System (ADS)

Vignetti, M. M.; Calmon, F.; Pittet, P.; Pares, G.; Cellier, R.; Quiquerez, L.; Chaves de Albuquerque, T.; Bechetoille, E.; Testa, E.; Lopez, J.-P.; Dauvergne, D.; Savoy-Navarro, A.

2018-02-01

Single-Photon Avalanche Diodes (SPADs) are p-n junctions operated in Geiger Mode by applying a reverse bias above the breakdown voltage. SPADs have the advantage of featuring single photon sensitivity with timing resolution in the picoseconds range. Nevertheless, their relatively high Dark Count Rate (DCR) is a major issue for charged particle detection, especially when it is much higher than the incoming particle rate. To tackle this issue, we have developed a 3D Silicon Coincidence Avalanche Detector (3D-SiCAD). This novel device implements two vertically aligned SPADs featuring on-chip electronics for the detection of coincident avalanche events occurring on both SPADs. Such a coincidence detection mode allows an efficient discrimination of events related to an incoming charged particle (producing a quasi-simultaneous activation of both SPADs) from dark counts occurring independently on each SPAD. A 3D-SiCAD detector prototype has been fabricated in CMOS technology adopting a 3D flip-chip integration technique, and the main results of its characterization are reported in this work. The particle detection efficiency and noise rejection capability for this novel device have been evaluated by means of a β- strontium-90 radioactive source. Moreover the impact of the main operating parameters (i.e. the hold-off time, the coincidence window duration, the SPAD excess bias voltage) over the particle detection efficiency has been studied. Measurements have been performed with different β- particles rates and show that a 3D-SiCAD device outperforms single SPAD detectors: the former is indeed capable to detect particle rates much lower than the individual DCR observed in a single SPAD-based detectors (i.e. 2 to 3 orders of magnitudes lower).

Conical Refraction Bottle Beams for Entrapment of Absorbing Droplets.

PubMed

Esseling, Michael; Alpmann, Christina; Schnelle, Jens; Meissner, Robert; Denz, Cornelia

2018-03-22

Conical refraction (CR) optical bottle beams for photophoretic trapping of airborne absorbing droplets are introduced and experimentally demonstrated. CR describes the circular split-up of unpolarised light propagating along an optical axis in a biaxial crystal. The diverging and converging cones lend themselves to the construction of optical bottle beams with flexible entry points. The interaction of single inkjet droplets with an open or partly open bottle beam is shown implementing high-speed video microscopy in a dual-view configuration. Perpendicular image planes are visualized on a single camera chip to characterize the integral three-dimensional movement dynamics of droplets. We demonstrate how a partly opened optical bottle transversely confines liquid objects. Furthermore we observe and analyse transverse oscillations of absorbing droplets as they hit the inner walls and simultaneously measure both transverse and axial velocity components.

Rapid and Low-Cost CRP Measurement by Integrating a Paper-Based Microfluidic Immunoassay with Smartphone (CRP-Chip)

PubMed Central

Dong, Meili; Wu, Jiandong; Ma, Zimin; Peretz-Soroka, Hagit; Zhang, Michael; Komenda, Paul; Tangri, Navdeep; Liu, Yong; Rigatto, Claudio; Lin, Francis

2017-01-01

Traditional diagnostic tests for chronic diseases are expensive and require a specialized laboratory, therefore limiting their use for point-of-care (PoC) testing. To address this gap, we developed a method for rapid and low-cost C-reactive protein (CRP) detection from blood by integrating a paper-based microfluidic immunoassay with a smartphone (CRP-Chip). We chose CRP for this initial development because it is a strong biomarker of prognosis in chronic heart and kidney disease. The microfluidic immunoassay is realized by lateral flow and gold nanoparticle-based colorimetric detection of the target protein. The test image signal is acquired and analyzed using a commercial smartphone with an attached microlens and a 3D-printed chip–phone interface. The CRP-Chip was validated for detecting CRP in blood samples from chronic kidney disease patients and healthy subjects. The linear detection range of the CRP-Chip is up to 2 μg/mL and the detection limit is 54 ng/mL. The CRP-Chip test result yields high reproducibility and is consistent with the standard ELISA kit. A single CRP-Chip can perform the test in triplicate on a single chip within 15 min for less than 50 US cents of material cost. This CRP-Chip with attractive features of low-cost, fast test speed, and integrated easy operation with smartphones has the potential to enable future clinical PoC chronic disease diagnosis and risk stratification by parallel measurements of a panel of protein biomarkers. PMID:28346363

A modular microfluidic architecture for integrated biochemical analysis.

PubMed

Shaikh, Kashan A; Ryu, Kee Suk; Goluch, Edgar D; Nam, Jwa-Min; Liu, Juewen; Thaxton, C Shad; Chiesl, Thomas N; Barron, Annelise E; Lu, Yi; Mirkin, Chad A; Liu, Chang

2005-07-12

Microfluidic laboratory-on-a-chip (LOC) systems based on a modular architecture are presented. The architecture is conceptualized on two levels: a single-chip level and a multiple-chip module (MCM) system level. At the individual chip level, a multilayer approach segregates components belonging to two fundamental categories: passive fluidic components (channels and reaction chambers) and active electromechanical control structures (sensors and actuators). This distinction is explicitly made to simplify the development process and minimize cost. Components belonging to these two categories are built separately on different physical layers and can communicate fluidically via cross-layer interconnects. The chip that hosts the electromechanical control structures is called the microfluidic breadboard (FBB). A single LOC module is constructed by attaching a chip comprised of a custom arrangement of fluid routing channels and reactors (passive chip) to the FBB. Many different LOC functions can be achieved by using different passive chips on an FBB with a standard resource configuration. Multiple modules can be interconnected to form a larger LOC system (MCM level). We demonstrated the utility of this architecture by developing systems for two separate biochemical applications: one for detection of protein markers of cancer and another for detection of metal ions. In the first case, free prostate-specific antigen was detected at 500 aM concentration by using a nanoparticle-based bio-bar-code protocol on a parallel MCM system. In the second case, we used a DNAzyme-based biosensor to identify the presence of Pb(2+) (lead) at a sensitivity of 500 nM in <1 nl of solution.

Universal lab-on-a-chip platform for complex, perfused 3D cell cultures

NASA Astrophysics Data System (ADS)

Sonntag, F.; Schmieder, F.; Ströbel, J.; Grünzner, S.; Busek, M.; Günther, K.; Steege, T.; Polk, C.; Klotzbach, U.

2016-03-01

The miniaturization, rapid prototyping and automation of lab-on-a-chip technology play nowadays a very important role. Lab-on-a-chip technology is successfully implemented not only for environmental analysis and medical diagnostics, but also as replacement of animals used for the testing of substances in the pharmaceutical and cosmetics industries. For that purpose the Fraunhofer IWS and partners developed a lab-on-a-chip platform for perfused cell-based assays in the last years, which includes different micropumps, valves, channels, reservoirs and customized cell culture modules. This technology is already implemented for the characterization of different human cell cultures and organoids, like skin, liver, endothelium, hair follicle and nephron. The advanced universal lab-on-a-chip platform for complex, perfused 3D cell cultures is divided into a multilayer basic chip with integrated micropump and application-specific 3D printed cell culture modules. Moreover a technology for surface modification of the printed cell culture modules by laser micro structuring and a complex and flexibly programmable controlling device based on an embedded Linux system was developed. A universal lab-on-a-chip platform with an optional oxygenator and a cell culture module for cubic scaffolds as well as first cell culture experiments within the cell culture device will be presented. The module is designed for direct interaction with robotic dispenser systems. This offers the opportunity to combine direct organ printing of cells and scaffolds with the microfluidic cell culture module. The characterization of the developed system was done by means of Micro-Particle Image Velocimetry (μPIV) and an optical oxygen measuring system.

Bio-inspired optical rotation sensor

NASA Astrophysics Data System (ADS)

O'Carroll, David C.; Shoemaker, Patrick A.; Brinkworth, Russell S. A.

2007-01-01

Traditional approaches to calculating self-motion from visual information in artificial devices have generally relied on object identification and/or correlation of image sections between successive frames. Such calculations are computationally expensive and real-time digital implementation requires powerful processors. In contrast flies arrive at essentially the same outcome, the estimation of self-motion, in a much smaller package using vastly less power. Despite the potential advantages and a few notable successes, few neuromorphic analog VLSI devices based on biological vision have been employed in practical applications to date. This paper describes a hardware implementation in aVLSI of our recently developed adaptive model for motion detection. The chip integrates motion over a linear array of local motion processors to give a single voltage output. Although the device lacks on-chip photodetectors, it includes bias circuits to use currents from external photodiodes, and we have integrated it with a ring-array of 40 photodiodes to form a visual rotation sensor. The ring configuration reduces pattern noise and combined with the pixel-wise adaptive characteristic of the underlying circuitry, permits a robust output that is proportional to image rotational velocity over a large range of speeds, and is largely independent of either mean luminance or the spatial structure of the image viewed. In principle, such devices could be used as an element of a velocity-based servo to replace or augment inertial guidance systems in applications such as mUAVs.

Flip-chip light emitting diode with resonant optical microcavity

DOEpatents

Gee, James M.; Bogart, Katherine H.A.; Fischer, Arthur J.

2005-11-29

A flip-chip light emitting diode with enhanced efficiency. The device structure employs a microcavity structure in a flip-chip configuration. The microcavity enhances the light emission in vertical modes, which are readily extracted from the device. Most of the rest of the light is emitted into waveguided lateral modes. Flip-chip configuration is advantageous for light emitting diodes (LEDs) grown on dielectric substrates (e.g., gallium nitride LEDs grown on sapphire substrates) in general due to better thermal dissipation and lower series resistance. Flip-chip configuration is advantageous for microcavity LEDs in particular because (a) one of the reflectors is a high-reflectivity metal ohmic contact that is already part of the flip-chip configuration, and (b) current conduction is only required through a single distributed Bragg reflector. Some of the waveguided lateral modes can also be extracted with angled sidewalls used for the interdigitated contacts in the flip-chip configuration.

A primary battery-on-a-chip using monolayer graphene.

PubMed

Iost, Rodrigo M; Crespilho, Frank N; Kern, Klaus; Balasubramanian, Kannan

2016-06-14

We present here a bottom-up approach for realizing on-chip on-demand batteries starting out with chemical vapor deposition-grown graphene. Single graphene monolayers contacted by electrode lines on a silicon chip serve as electrodes. The anode and cathode are realized by electrodeposition of zinc and copper respectively onto graphene, leading to the realization of a miniature graphene-based Daniell cell on a chip. The electrolyte is housed partly in a gel and partly in liquid form in an on-chip enclosure molded using a 3d printer or made out of poly(dimethylsiloxane). The realized batteries provide a stable voltage (∼1.1 V) for many hours and exhibit capacities as high as 15 μAh, providing enough power to operate a pocket calculator. The realized batteries show promise for deployment as on-chip power sources for autonomous systems in lab-on-a-chip or biomedical applications.

A primary battery-on-a-chip using monolayer graphene

NASA Astrophysics Data System (ADS)

Iost, Rodrigo M.; Crespilho, Frank N.; Kern, Klaus; Balasubramanian, Kannan

2016-07-01

We present here a bottom-up approach for realizing on-chip on-demand batteries starting out with chemical vapor deposition-grown graphene. Single graphene monolayers contacted by electrode lines on a silicon chip serve as electrodes. The anode and cathode are realized by electrodeposition of zinc and copper respectively onto graphene, leading to the realization of a miniature graphene-based Daniell cell on a chip. The electrolyte is housed partly in a gel and partly in liquid form in an on-chip enclosure molded using a 3d printer or made out of poly(dimethylsiloxane). The realized batteries provide a stable voltage (∼1.1 V) for many hours and exhibit capacities as high as 15 μAh, providing enough power to operate a pocket calculator. The realized batteries show promise for deployment as on-chip power sources for autonomous systems in lab-on-a-chip or biomedical applications.

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

NASA Technical Reports Server (NTRS)

Ruiz, B. Ian; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †.

PubMed

Nose, Atsushi; Yamazaki, Tomohiro; Katayama, Hironobu; Uehara, Shuji; Kobayashi, Masatsugu; Shida, Sayaka; Odahara, Masaki; Takamiya, Kenichi; Matsumoto, Shizunori; Miyashita, Leo; Watanabe, Yoshihiro; Izawa, Takashi; Muramatsu, Yoshinori; Nitta, Yoshikazu; Ishikawa, Masatoshi

2018-04-24

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

NASA Astrophysics Data System (ADS)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

NASA Astrophysics Data System (ADS)

Sordo-Ibáñez, Samuel; Piñero-García, Blanca; Muñoz-Díaz, Manuel; Ragel-Morales, Antonio; Ceballos-Cáceres, Joaquín; Carranza-González, Luis; Espejo-Meana, Servando; Arias-Drake, Alberto; Ramos-Martos, Juan; Mora-Gutiérrez, José Miguel; Lagos-Florido, Miguel Angel

2016-08-01

This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

Functionalization and Characterization of Nanomaterial Gated Field-Effect Transistor-Based Biosensors and the Design of a Multi-Analyte Implantable Biosensing Platform

NASA Astrophysics Data System (ADS)

Croce, Robert A., Jr.

Advances in semiconductor research and complementary-metal-oxide semiconductor fabrication allow for the design and implementation of miniaturized metabolic monitoring systems, as well as advanced biosensor design. The first part of this dissertation will focus on the design and fabrication of nanomaterial (single-walled carbon nanotube and quantum dot) gated field-effect transistors configured as protein sensors. These novel device structures have been functionalized with single-stranded DNA aptamers, and have shown sensor operation towards the protein Thrombin. Such advanced transistor-based sensing schemes present considerable advantages over traditional sensing methodologies in view of its miniaturization, low cost, and facile fabrication, paving the way for the ultimate realization of a multi-analyte lab-on-chip. The second part of this dissertation focuses on the design and fabrication of a needle-implantable glucose sensing platform which is based solely on photovoltaic powering and optical communication. By employing these powering and communication schemes, this design negates the need for bulky on-chip RF-based transmitters and batteries in an effort to attain extreme miniaturization required for needle-implantable/extractable applications. A complete single-sensor system coupled with a miniaturized amperometric glucose sensor has been demonstrated to exhibit reality of this technology. Furthermore, an optical selection scheme of multiple potentiostats for four different analytes (glucose, lactate, O 2 and CO2) as well as the optical transmission of sensor data has been designed for multi-analyte applications. The last part of this dissertation will focus on the development of a computational model for the amperometric glucose sensors employed in the aforementioned implantable platform. This model has been applied to single-layer single-enzyme systems, as well as multi-layer (single enzyme) systems utilizing glucose flux limiting layer-by-layer assembled outer membranes. The concentration of glucose and hydrogen peroxide within the sensor geometry, the transient response and the device response time has been simulated for both systems.

Route to one-step microstructure mold fabrication for PDMS microfluidic chip

NASA Astrophysics Data System (ADS)

Lv, Xiaoqing; Geng, Zhaoxin; Fan, Zhiyuan; Wang, Shicai; Su, Yue; Fang, Weihao; Pei, Weihua; Chen, Hongda

2018-04-01

The microstructure mold fabrication for PDMS microfluidic chip remains complex and time-consuming process requiring special equipment and protocols: photolithography and etching. Thus, a rapid and cost-effective method is highly needed. Comparing with the traditional microfluidic chip fabricating process based on the micro-electromechanical system (MEMS), this method is simple and easy to implement, and the whole fabrication process only requires 1-2 h. Different size of microstructure from 100 to 1000 μm was fabricated, and used to culture four kinds of breast cancer cell lines. Cell viability and morphology was assessed when they were cultured in the micro straight channels, micro square holes and the bonding PDMS-glass microfluidic chip. The experimental results indicate that the microfluidic chip is good and meet the experimental requirements. This method can greatly reduce the process time and cost of the microfluidic chip, and provide a simple and effective way for the structure design and in the field of biological microfabrications and microfluidic chips.

Three levels of neuroelectronic interfacing: silicon chips with ion channels, nerve cells, and brain tissue.

PubMed

Fromherz, Peter

2006-12-01

We consider the direct electrical interfacing of semiconductor chips with individual nerve cells and brain tissue. At first, the structure of the cell-chip contact is studied. Then we characterize the electrical coupling of ion channels--the electrical elements of nerve cells--with transistors and capacitors in silicon chips. On that basis it is possible to implement signal transmission between microelectronics and the microionics of nerve cells in both directions. Simple hybrid neuroelectronic systems are assembled with neuron pairs and with small neuronal networks. Finally, the interfacing with capacitors and transistors is extended to brain tissue cultured on silicon chips. The application of highly integrated silicon chips allows an imaging of neuronal activity with high spatiotemporal resolution. The goal of the work is an integration of neuronal network dynamics with digital electronics on a microscopic level with respect to experiments in brain research, medical prosthetics, and information technology.

Neuromorphic implementations of neurobiological learning algorithms for spiking neural networks.

PubMed

Walter, Florian; Röhrbein, Florian; Knoll, Alois

2015-12-01

The application of biologically inspired methods in design and control has a long tradition in robotics. Unlike previous approaches in this direction, the emerging field of neurorobotics not only mimics biological mechanisms at a relatively high level of abstraction but employs highly realistic simulations of actual biological nervous systems. Even today, carrying out these simulations efficiently at appropriate timescales is challenging. Neuromorphic chip designs specially tailored to this task therefore offer an interesting perspective for neurorobotics. Unlike Von Neumann CPUs, these chips cannot be simply programmed with a standard programming language. Like real brains, their functionality is determined by the structure of neural connectivity and synaptic efficacies. Enabling higher cognitive functions for neurorobotics consequently requires the application of neurobiological learning algorithms to adjust synaptic weights in a biologically plausible way. In this paper, we therefore investigate how to program neuromorphic chips by means of learning. First, we provide an overview over selected neuromorphic chip designs and analyze them in terms of neural computation, communication systems and software infrastructure. On the theoretical side, we review neurobiological learning techniques. Based on this overview, we then examine on-die implementations of these learning algorithms on the considered neuromorphic chips. A final discussion puts the findings of this work into context and highlights how neuromorphic hardware can potentially advance the field of autonomous robot systems. The paper thus gives an in-depth overview of neuromorphic implementations of basic mechanisms of synaptic plasticity which are required to realize advanced cognitive capabilities with spiking neural networks. Copyright © 2015 Elsevier Ltd. All rights reserved.

Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.

2016-11-01

Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

Simultaneous RGB lasing from a single-chip polymer device.

PubMed

Yamashita, Kenichi; Takeuchi, Nobutaka; Oe, Kunishige; Yanagi, Hisao

2010-07-15

This Letter describes the fabrication and operation of a single-chip white-laser device. The laser device has a multilayered structure consisting of three laser layers. Each laser layer comprises polymer claddings and a waveguide core doped with organic dye. In each laser layer, grating corrugations were fabricated by UV-nanoimprint lithography that act as distributed-feedback cavity structures. Under optical pumping, lasing output with red, green, and blue colors was simultaneously obtained from the sample edge.

Intelligent structures technology

NASA Astrophysics Data System (ADS)

Crawley, Edward F.

1991-07-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Intelligent structures technology

NASA Technical Reports Server (NTRS)

Crawley, Edward F.

1991-01-01

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Murray, E.; Floether, F. F.; Cavendish Laboratory, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0HE

Fundamental to integrated photonic quantum computing is an on-chip method for routing and modulating quantum light emission. We demonstrate a hybrid integration platform consisting of arbitrarily designed waveguide circuits and single-photon sources. InAs quantum dots (QD) embedded in GaAs are bonded to a SiON waveguide chip such that the QD emission is coupled to the waveguide mode. The waveguides are SiON core embedded in a SiO{sub 2} cladding. A tuneable Mach Zehnder interferometer (MZI) modulates the emission between two output ports and can act as a path-encoded qubit preparation device. The single-photon nature of the emission was verified using themore » on-chip MZI as a beamsplitter in a Hanbury Brown and Twiss measurement.« less

Fiber-chip edge coupler with large mode size for silicon photonic wire waveguides.

PubMed

Papes, Martin; Cheben, Pavel; Benedikovic, Daniel; Schmid, Jens H; Pond, James; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, Gonzalo; Ye, Winnie N; Xu, Dan-Xia; Janz, Siegfried; Dado, Milan; Vašinek, Vladimír

2016-03-07

Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO 2 upper cladding thin high-index Si 3 N 4 layers. The Si 3 N 4 layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.

Single-chip fully integrated direct-modulation CMOS RF transmitters for short-range wireless applications.

PubMed

El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed; Deen, M Jamal

2013-08-02

Ultra-low power radio frequency (RF) transceivers used in short-range application such as wireless sensor networks (WSNs) require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs) in addition to a 2.0 GHz phase-locked loop (PLL) based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of -122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of -120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

Design of 5.8 GHz Integrated Antenna on 180nm Complementary Metal Oxide Semiconductor (CMOS) Technology

NASA Astrophysics Data System (ADS)

Razak, A. H. A.; Shamsuddin, M. I. A.; Idros, M. F. M.; Halim, A. K.; Ahmad, A.; Junid, S. A. M. Al

2018-03-01

This project discusses the design and simulation performances of integrated loop antenna. Antenna is one of the main parts in any wireless radio frequency integrated circuit (RFIC). Naturally, antenna is the bulk in any RFIC design. Thus, this project aims to implement an integrated antenna on a single chip making the end product more compact. This project targets 5.8 GHz as the operating frequency of the integrated antenna for a transceiver module based on Silterra CMOS 180nm technology. The simulation of the antenna was done by using High Frequency Structure Simulator (HFSS). This software is industrial standard software that been used to simulate all electromagnetic effect including antenna simulation. This software has ability to simulate frequency at range of 100 MHz to 4 THz. The simulation set up in 3 dimension structure with driven terminal. The designed antenna has 1400um of diameter and placed on top metal layer. Loop configuration of the antenna has been chosen as the antenna design. From the configuration, it is able to make the chip more compact. The simulation shows that the antenna has single frequency band at center frequency 5.8 GHz with -48.93dB. The antenna radiation patterns shows, the antenna radiate at omnidirectional. From the simulation result, it could be concluded that the antenna have a good radiation pattern and propagation for wireless communication.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

Intracellular protein determination using droplet-based immunoassays.

PubMed

Martino, Chiara; Zagnoni, Michele; Sandison, Mairi E; Chanasakulniyom, Mayuree; Pitt, Andrew R; Cooper, Jonathan M

2011-07-01

This paper describes the implementation of a sensitive, on-chip immunoassay for the analysis of intracellular proteins, developed using microdroplet technology. The system offers a number of analytical functionalities, enabling the lysis of low cell numbers, as well as protein detection and quantification, integrated within a single process flow. Cells were introduced into the device in suspension and were electrically lysed in situ. The cell lysate was subsequently encapsulated together with antibody-functionalized beads into stable, water-in-oil droplets, which were stored on-chip. The binding of intracellular proteins to the beads was monitored fluorescently. By analyzing many individual droplets and quantifying the data obtained against standard additions, we measured the level of two intracellular proteins, namely, HRas-mCitrine, expressed within HEK-293 cells, and actin-EGFP, expressed within MCF-7 cells. We determined the concentrations of these proteins over 5 orders of magnitude, from ~50 pM to 1 μM. The results from this semiautomated method were compared to those for determinations made using Western blots, and were found not only to be faster, but required a smaller number of cells.

Adding the 'heart' to hanging drop networks for microphysiological multi-tissue experiments.

PubMed

Rismani Yazdi, Saeed; Shadmani, Amir; Bürgel, Sebastian C; Misun, Patrick M; Hierlemann, Andreas; Frey, Olivier

2015-11-07

Microfluidic hanging-drop networks enable culturing and analysis of 3D microtissue spheroids derived from different cell types under controlled perfusion and investigating inter-tissue communication in multi-tissue formats. In this paper we introduce a compact on-chip pumping approach for flow control in hanging-drop networks. The pump includes one pneumatic chamber located directly above one of the hanging drops and uses the surface tension at the liquid-air-interface for flow actuation. Control of the pneumatic protocol provides a wide range of unidirectional pulsatile and continuous flow profiles. With the proposed concept several independent hanging-drop networks can be operated in parallel with only one single pneumatic actuation line at high fidelity. Closed-loop medium circulation between different organ models for multi-tissue formats and multiple simultaneous assays in parallel are possible. Finally, we implemented a real-time feedback control-loop of the pump actuation based on the beating of a human iPS-derived cardiac microtissue cultured in the same system. This configuration allows for simulating physiological effects on the heart and their impact on flow circulation between the organ models on chip.

Transferrable monolithic III-nitride photonic circuit for multifunctional optoelectronics

NASA Astrophysics Data System (ADS)

Shi, Zheng; Gao, Xumin; Yuan, Jialei; Zhang, Shuai; Jiang, Yan; Zhang, Fenghua; Jiang, Yuan; Zhu, Hongbo; Wang, Yongjin

2017-12-01

A monolithic III-nitride photonic circuit with integrated functionalities was implemented by integrating multiple components with different functions into a single chip. In particular, the III-nitride-on-silicon platform is used as it integrates a transmitter, a waveguide, and a receiver into a suspended III-nitride membrane via a wafer-level procedure. Here, a 0.8-mm-diameter suspended device architecture is directly transferred from silicon to a foreign substrate by mechanically breaking the support beams. The transferred InGaN/GaN multiple-quantum-well diode (MQW-diode) exhibits a turn-on voltage of 2.8 V with a dominant electroluminescence peak at 453 nm. The transmitter and receiver share an identical InGaN/GaN MQW structure, and the integrated photonic circuit inherently works for on-chip power monitoring and in-plane visible light communication. The wire-bonded monolithic photonic circuit on glass experimentally demonstrates in-plane data transmission at 120 Mb/s, paving the way for diverse applications in intelligent displays, in-plane light communication, flexible optical sensors, and wearable III-nitride optoelectronics.

Lab-on-a-chip technologies for proteomic analysis from isolated cells

PubMed Central

Sedgwick, H.; Caron, F.; Monaghan, P.B.; Kolch, W.; Cooper, J.M.

2008-01-01

Lab-on-a-chip systems offer a versatile environment in which low numbers of cells and molecules can be manipulated, captured, detected and analysed. We describe here a microfluidic device that allows the isolation, electroporation and lysis of single cells. A431 human epithelial carcinoma cells, expressing a green fluorescent protein-labelled actin, were trapped by dielectrophoresis within an integrated lab-on-a-chip device containing saw-tooth microelectrodes. Using these same trapping electrodes, on-chip electroporation was performed, resulting in cell lysis. Protein release was monitored by confocal fluorescence microscopy. PMID:18534931

PCR amplification and genetic analysis in a microwell cell culturing chip.

PubMed

Lindström, Sara; Hammond, Maria; Brismar, Hjalmar; Andersson-Svahn, Helene; Ahmadian, Afshin

2009-12-21

We have previously described a microwell chip designed for high throughput, long-term single-cell culturing and clonal analysis in individual wells providing a controlled way of studying high numbers of individual adherent or non-adherent cells. Here we present a method for the genetic analysis of cells cultured on-chip by PCR and minisequencing, demonstrated using two human adherent cell lines: one wild type and one with a single-base mutation in the p53 gene. Five wild type or mutated cells were seeded per well (in a defined set of wells, each holding 500 nL of culture medium) in a 672-microwell chip. The cell chip was incubated overnight, or cultured for up to five days, depending on the desired colony size, after which the cells were lysed and subjected to PCR directly in the wells. PCR products were detected, in the wells, using a biotinylated primer and a fluorescently labelled primer, allowing the products to be captured on streptavidin-coated magnetic beads and detected by a fluorescence microscope. In addition, to enable genetic analysis by minisequencing, the double-stranded PCR products were denatured and the immobilized strands were kept in the wells by applying a magnetic field from the bottom of the wells while the wells were washed, a minisequencing reaction mixture was added, and after incubation in appropriate conditions the expected genotypes were detected in the investigated microwells, simultaneously, by an array scanner. We anticipate that the technique could be used in mutation frequency screening, providing the ability to correlate cells' proliferative heterogeneity to their genetic heterogeneity, in hundreds of samples simultaneously. The presented method of single-cell culture and DNA amplification thus offers a potentially powerful alternative to single-cell PCR, with advantageous robustness and sensitivity.

A scalable self-priming fractal branching microchannel net chip for digital PCR.

PubMed

Zhu, Qiangyuan; Xu, Yanan; Qiu, Lin; Ma, Congcong; Yu, Bingwen; Song, Qi; Jin, Wei; Jin, Qinhan; Liu, Jinyu; Mu, Ying

2017-05-02

As an absolute quantification method at the single-molecule level, digital PCR has been widely used in many bioresearch fields, such as next generation sequencing, single cell analysis, gene editing detection and so on. However, existing digital PCR methods still have some disadvantages, including high cost, sample loss, and complicated operation. In this work, we develop an exquisite scalable self-priming fractal branching microchannel net digital PCR chip. This chip with a special design inspired by natural fractal-tree systems has an even distribution and 100% compartmentalization of the sample without any sample loss, which is not available in existing chip-based digital PCR methods. A special 10 nm nano-waterproof layer was created to prevent the solution from evaporating. A vacuum pre-packaging method called self-priming reagent introduction is used to passively drive the reagent flow into the microchannel nets, so that this chip can realize sequential reagent loading and isolation within a couple of minutes, which is very suitable for point-of-care detection. When the number of positive microwells stays in the range of 100 to 4000, the relative uncertainty is below 5%, which means that one panel can detect an average of 101 to 15 374 molecules by the Poisson distribution. This chip is proved to have an excellent ability for single molecule detection and quantification of low expression of hHF-MSC stem cell markers. Due to its potential for high throughput, high density, low cost, lack of sample and reagent loss, self-priming even compartmentalization and simple operation, we envision that this device will significantly expand and extend the application range of digital PCR involving rare samples, liquid biopsy detection and point-of-care detection with higher sensitivity and accuracy.

Single-Cell mRNA-Seq Using the Fluidigm C1 System and Integrated Fluidics Circuits.

PubMed

Gong, Haibiao; Do, Devin; Ramakrishnan, Ramesh

2018-01-01

Single-cell mRNA-seq is a valuable tool to dissect expression profiles and to understand the regulatory network of genes. Microfluidics is well suited for single-cell analysis owing both to the small volume of the reaction chambers and easiness of automation. Here we describe the workflow of single-cell mRNA-seq using C1 IFC, which can isolate and process up to 96 cells. Both on-chip procedure (lysis, reverse transcription, and preamplification PCR) and off-chip sequencing library preparation protocols are described. The workflow generates full-length mRNA information, which is more valuable compared to 3' end counting method for many applications.

ALPIDE: the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

NASA Astrophysics Data System (ADS)

Šuljić, M.

2016-11-01

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ~10 m2, thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10-6 and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 1013 1 MeV neq/cm2, which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm2. This contribution will provide a summary of the ALPIDE features and main test results.

Design rules for quantum imaging devices: experimental progress using CMOS single-photon detectors

NASA Astrophysics Data System (ADS)

Charbon, Edoardo; Gunther, Neil J.; Boiko, Dmitri L.; Beretta, Giordano B.

2006-08-01

We continue our previous program1 where we introduced a set of quantum-based design rules directed at quantum engineers who design single-photon quantum communications and quantum imaging devices. Here, we report on experimental progress using SPAD (single photon avalanche diode) arrays of our design and fabricated in CMOS (complementary metal oxide semiconductor) technology. Emerging high-resolution imaging techniques based on SPAD arrays have proven useful in a variety of disciplines including bio-fluorescence microscopy and 3D vision systems. They have also been particularly successful for intra-chip optical communications implemented entirely in CMOS technology. More importantly for our purposes, a very low dark count allows SPADs to detect rare photon events with a high dynamic range and high signal-to-noise ratio. Our CMOS SPADs support multi-channel detection of photon arrivals with picosecond accuracy, several million times per second, due to a very short detection cycle. The tiny chip area means they are suitable for highly miniaturized quantum imaging devices and that is how we employ them in this paper. Our quantum path integral analysis of the Young-Afshar-Wheeler interferometer showed that Bohr's complementarity principle was not violated due the previously overlooked effect of photon bifurcation within the lens--a phenomenon consistent with our quantum design rules--which accounts for the loss of which-path information in the presence of interference. In this paper, we report on our progress toward the construction of quantitative design rules as well as some proposed tests for quantum imaging devices using entangled photon sources with our SPAD imager.

Flux qubit interaction with rapid single-flux quantum logic circuits: Control and readout

NASA Astrophysics Data System (ADS)

Klenov, N. V.; Kuznetsov, A. V.; Soloviev, I. I.; Bakurskiy, S. V.; Denisenko, M. V.; Satanin, A. M.

2017-07-01

We present the results of an analytical study and numerical simulation of the dynamics of a superconducting three-Josephson-junction (3JJ) flux qubit magnetically coupled with rapid single-flux quantum (RSFQ) logic circuit, which demonstrate the fundamental possibility of implementing the simplest logic operations at picosecond times, as well as rapid non-destructive readout. It is shown that when solving optimization problems, the qubit dynamics can be conveniently interpreted as a precession of the magnetic moment vector around the direction of the magnetic field. In this case, the role of magnetic field components is played by combinations of the Hamiltonian matrix elements, and the role of the magnetic moment is played by the Bloch vector. Features of the 3JJ qubit model are discussed during the analysis of how the qubit is affected by exposure to a short control pulse, as are the similarities between the Bloch and Landau-Lifshitz-Gilbert equations. An analysis of solutions to the Bloch equations made it possible to develop recommendations for the use of readout RSFQ circuits in implementing an optimal interface between the classical and quantum parts of the computer system, as well as to justify the use of single-quantum logic in order to control superconducting quantum circuits on a chip.

On board processor development for NASA's spaceborne imaging radar with system-on-chip technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

2004-01-01

This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with system-on-chip technology. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Associative architecture for image processing

NASA Astrophysics Data System (ADS)

Adar, Rutie; Akerib, Avidan

1997-09-01

This article presents a new generation in parallel processing architecture for real-time image processing. The approach is implemented in a real time image processor chip, called the XiumTM-2, based on combining a fully associative array which provides the parallel engine with a serial RISC core on the same die. The architecture is fully programmable and can be programmed to implement a wide range of color image processing, computer vision and media processing functions in real time. The associative part of the chip is based on patented pending methodology of Associative Computing Ltd. (ACL), which condenses 2048 associative processors, each of 128 'intelligent' bits. Each bit can be a processing bit or a memory bit. At only 33 MHz and 0.6 micron manufacturing technology process, the chip has a computational power of 3 billion ALU operations per second and 66 billion string search operations per second. The fully programmable nature of the XiumTM-2 chip enables developers to use ACL tools to write their own proprietary algorithms combined with existing image processing and analysis functions from ACL's extended set of libraries.

System-level protection and hardware Trojan detection using weighted voting.

PubMed

Amin, Hany A M; Alkabani, Yousra; Selim, Gamal M I

2014-07-01

The problem of hardware Trojans is becoming more serious especially with the widespread of fabless design houses and design reuse. Hardware Trojans can be embedded on chip during manufacturing or in third party intellectual property cores (IPs) during the design process. Recent research is performed to detect Trojans embedded at manufacturing time by comparing the suspected chip with a golden chip that is fully trusted. However, Trojan detection in third party IP cores is more challenging than other logic modules especially that there is no golden chip. This paper proposes a new methodology to detect/prevent hardware Trojans in third party IP cores. The method works by gradually building trust in suspected IP cores by comparing the outputs of different untrusted implementations of the same IP core. Simulation results show that our method achieves higher probability of Trojan detection over a naive implementation of simple voting on the output of different IP cores. In addition, experimental results show that the proposed method requires less hardware overhead when compared with a simple voting technique achieving the same degree of security.

Efficient fiber-coupled single-photon source based on quantum dots in a photonic-crystal waveguide

PubMed Central

DAVEAU, RAPHAËL S.; BALRAM, KRISHNA C.; PREGNOLATO, TOMMASO; LIU, JIN; LEE, EUN H.; SONG, JIN D.; VERMA, VARUN; MIRIN, RICHARD; NAM, SAE WOO; MIDOLO, LEONARDO; STOBBE, SØREN; SRINIVASAN, KARTIK; LODAHL, PETER

2017-01-01

Many photonic quantum information processing applications would benefit from a high brightness, fiber-coupled source of triggered single photons. Here, we present a fiber-coupled photonic-crystal waveguide single-photon source relying on evanescent coupling of the light field from a tapered out-coupler to an optical fiber. A two-step approach is taken where the performance of the tapered out-coupler is recorded first on an independent device containing an on-chip reflector. Reflection measurements establish that the chip-to-fiber coupling efficiency exceeds 80 %. The detailed characterization of a high-efficiency photonic-crystal waveguide extended with a tapered out-coupling section is then performed. The corresponding overall single-photon source efficiency is 10.9 % ± 2.3 %, which quantifies the success probability to prepare an exciton in the quantum dot, couple it out as a photon in the waveguide, and subsequently transfer it to the fiber. The applied out-coupling method is robust, stable over time, and broadband over several tens of nanometers, which makes it a highly promising pathway to increase the efficiency and reliability of planar chip-based single-photon sources. PMID:28584859

Detection of solder bump defects on a flip chip using vibration analysis

NASA Astrophysics Data System (ADS)

Liu, Junchao; Shi, Tielin; Xia, Qi; Liao, Guanglan

2012-03-01

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

CMOS active pixel sensor type imaging system on a chip

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nixon, Robert (Inventor)

2011-01-01

A single chip camera which includes an .[.intergrated.]. .Iadd.integrated .Iaddend.image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the .[.intergrated.]. .Iadd.integrated .Iaddend.structure reduces the noise that is picked up during imaging.

Integration of image capture and processing: beyond single-chip digital camera

NASA Astrophysics Data System (ADS)

Lim, SukHwan; El Gamal, Abbas

2001-05-01

An important trend in the design of digital cameras is the integration of capture and processing onto a single CMOS chip. Although integrating the components of a digital camera system onto a single chip significantly reduces system size and power, it does not fully exploit the potential advantages of integration. We argue that a key advantage of integration is the ability to exploit the high speed imaging capability of CMOS image senor to enable new applications such as multiple capture for enhancing dynamic range and to improve the performance of existing applications such as optical flow estimation. Conventional digital cameras operate at low frame rates and it would be too costly, if not infeasible, to operate their chips at high frame rates. Integration solves this problem. The idea is to capture images at much higher frame rates than he standard frame rate, process the high frame rate data on chip, and output the video sequence and the application specific data at standard frame rate. This idea is applied to optical flow estimation, where significant performance improvements are demonstrate over methods using standard frame rate sequences. We then investigate the constraints on memory size and processing power that can be integrated with a CMOS image sensor in a 0.18 micrometers process and below. We show that enough memory and processing power can be integrated to be able to not only perform the functions of a conventional camera system but also to perform applications such as real time optical flow estimation.

Scalable fabrication of high-power graphene micro-supercapacitors for flexible and on-chip energy storage

NASA Astrophysics Data System (ADS)

El-Kady, Maher F.; Kaner, Richard B.

2013-02-01

The rapid development of miniaturized electronic devices has increased the demand for compact on-chip energy storage. Microscale supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. However, conventional micro-fabrication techniques have proven to be cumbersome in building cost-effective micro-devices, thus limiting their widespread application. Here we demonstrate a scalable fabrication of graphene micro-supercapacitors over large areas by direct laser writing on graphite oxide films using a standard LightScribe DVD burner. More than 100 micro-supercapacitors can be produced on a single disc in 30 min or less. The devices are built on flexible substrates for flexible electronics and on-chip uses that can be integrated with MEMS or CMOS in a single chip. Remarkably, miniaturizing the devices to the microscale results in enhanced charge-storage capacity and rate capability. These micro-supercapacitors demonstrate a power density of ~200 W cm-3, which is among the highest values achieved for any supercapacitor.

A three-channel LED driver with single line transportation technique

NASA Astrophysics Data System (ADS)

Yu, Caideng; Du, Yiying; Jiang, Qiao; Zhou, Yun; Lv, Jian

2012-10-01

Designed a three-channel LED driver, realized the single-wire transmission of cascade signal between the drive IC of LED. Including the MCU digital interface, date register, clock synchronization, PWM grayscale adjustment circuit, as well as high voltage driver circuit for LED, etc… The driver control LED displaying 256 gray. Chip will generate synchronous sampling clock signals according to the received serial signals, when 24 bits dates have been received, the output pin begins to transport the dates followed-up which are automotive shaped to the input of the next chip. When the date receiving becomes low level that represent RESET, the red, green and blue channels will export different signals based on different input dates. Through the external MCU, it is realized the Separate luminance, and by connecting chips in series it achieved the control of outdoor big screen' colorful display. The automatic shaping forward technique makes the number of chips cascading immune to the limitations of signal transmission, but only limited by the refresh speed.

Spin-photon interface and spin-controlled photon switching in a nanobeam waveguide

NASA Astrophysics Data System (ADS)

Javadi, Alisa; Ding, Dapeng; Appel, Martin Hayhurst; Mahmoodian, Sahand; Löbl, Matthias Christian; Söllner, Immo; Schott, Rüdiger; Papon, Camille; Pregnolato, Tommaso; Stobbe, Søren; Midolo, Leonardo; Schröder, Tim; Wieck, Andreas Dirk; Ludwig, Arne; Warburton, Richard John; Lodahl, Peter

2018-05-01

The spin of an electron is a promising memory state and qubit. Connecting spin states that are spatially far apart will enable quantum nodes and quantum networks based on the electron spin. Towards this goal, an integrated spin-photon interface would be a major leap forward as it combines the memory capability of a single spin with the efficient transfer of information by photons. Here, we demonstrate such an efficient and optically programmable interface between the spin of an electron in a quantum dot and photons in a nanophotonic waveguide. The spin can be deterministically prepared in the ground state with a fidelity of up to 96%. Subsequently, the system is used to implement a single-spin photonic switch, in which the spin state of the electron directs the flow of photons through the waveguide. The spin-photon interface may enable on-chip photon-photon gates, single-photon transistors and the efficient generation of a photonic cluster state.

Defense Against Chip Cloning Attacks Based on Fractional Hopfield Neural Networks.

PubMed

Pu, Yi-Fei; Yi, Zhang; Zhou, Ji-Liu

2017-06-01

This paper presents a state-of-the-art application of fractional hopfield neural networks (FHNNs) to defend against chip cloning attacks, and provides insight into the reason that the proposed method is superior to physically unclonable functions (PUFs). In the past decade, PUFs have been evolving as one of the best types of hardware security. However, the development of the PUFs has been somewhat limited by its implementation cost, its temperature variation effect, its electromagnetic interference effect, the amount of entropy in it, etc. Therefore, it is imperative to discover, through promising mathematical methods and physical modules, some novel mechanisms to overcome the aforementioned weaknesses of the PUFs. Motivated by this need, in this paper, we propose applying the FHNNs to defend against chip cloning attacks. At first, we implement the arbitrary-order fractor of a FHNN. Secondly, we describe the implementation cost of the FHNNs. Thirdly, we propose the achievement of the constant-order performance of a FHNN when ambient temperature varies. Fourthly, we analyze the electrical performance stability of the FHNNs under electromagnetic disturbance conditions. Fifthly, we study the amount of entropy of the FHNNs. Lastly, we perform experiments to analyze the pass-band width of the fractor of an arbitrary-order FHNN and the defense against chip cloning attacks capability of the FHNNs. In particular, the capabilities of defense against chip cloning attacks, anti-electromagnetic interference, and anti-temperature variation of a FHNN are illustrated experimentally in detail. Some significant advantages of the FHNNs are that their implementation cost is considerably lower than that of the PUFs, their electrical performance is much more stable than that of the PUFs under different temperature conditions, their electrical performance stability of the FHNNs under electromagnetic disturbance conditions is much more robust than that of the PUFs, and their amount of entropy is significantly higher than that of the PUFs with the same rank circuit scale.

An Energy-Efficient Algorithm for Wearable Electrocardiogram Signal Processing in Ubiquitous Healthcare Applications

PubMed Central

Sodhro, Ali Hassan; Sodhro, Gul Hassan; Lohano, Sonia; Pirbhulal, Sandeep

2018-01-01

Rapid progress and emerging trends in miniaturized medical devices have enabled the un-obtrusive monitoring of physiological signals and daily activities of everyone’s life in a prominent and pervasive manner. Due to the power-constrained nature of conventional wearable sensor devices during ubiquitous sensing (US), energy-efficiency has become one of the highly demanding and debatable issues in healthcare. This paper develops a single chip-based wearable wireless electrocardiogram (ECG) monitoring system by adopting analog front end (AFE) chip model ADS1292R from Texas Instruments. The developed chip collects real-time ECG data with two adopted channels for continuous monitoring of human heart activity. Then, these two channels and the AFE are built into a right leg drive right leg drive (RLD) driver circuit with lead-off detection and medical graded test signal. Human ECG data was collected at 60 beats per minute (BPM) to 120 BPM with 60 Hz noise and considered throughout the experimental set-up. Moreover, notch filter (cutoff frequency 60 Hz), high-pass filter (cutoff frequency 0.67 Hz), and low-pass filter (cutoff frequency 100 Hz) with cut-off frequencies of 60 Hz, 0.67 Hz, and 100 Hz, respectively, were designed with bilinear transformation for rectifying the power-line noise and artifacts while extracting real-time ECG signals. Finally, a transmission power control-based energy-efficient (ETPC) algorithm is proposed, implemented on the hardware and then compared with the several conventional TPC methods. Experimental results reveal that our developed chip collects real-time ECG data efficiently, and the proposed ETPC algorithm achieves higher energy savings of 35.5% with a slightly larger packet loss ratio (PLR) as compared to conventional TPC (e.g., constant TPC, Gao’s, and Xiao’s methods). PMID:29558433

An Energy-Efficient Algorithm for Wearable Electrocardiogram Signal Processing in Ubiquitous Healthcare Applications.

PubMed

Sodhro, Ali Hassan; Sangaiah, Arun Kumar; Sodhro, Gul Hassan; Lohano, Sonia; Pirbhulal, Sandeep

2018-03-20

Rapid progress and emerging trends in miniaturized medical devices have enabled the un-obtrusive monitoring of physiological signals and daily activities of everyone's life in a prominent and pervasive manner. Due to the power-constrained nature of conventional wearable sensor devices during ubiquitous sensing (US), energy-efficiency has become one of the highly demanding and debatable issues in healthcare. This paper develops a single chip-based wearable wireless electrocardiogram (ECG) monitoring system by adopting analog front end (AFE) chip model ADS1292R from Texas Instruments. The developed chip collects real-time ECG data with two adopted channels for continuous monitoring of human heart activity. Then, these two channels and the AFE are built into a right leg drive right leg drive (RLD) driver circuit with lead-off detection and medical graded test signal. Human ECG data was collected at 60 beats per minute (BPM) to 120 BPM with 60 Hz noise and considered throughout the experimental set-up. Moreover, notch filter (cutoff frequency 60 Hz), high-pass filter (cutoff frequency 0.67 Hz), and low-pass filter (cutoff frequency 100 Hz) with cut-off frequencies of 60 Hz, 0.67 Hz, and 100 Hz, respectively, were designed with bilinear transformation for rectifying the power-line noise and artifacts while extracting real-time ECG signals. Finally, a transmission power control-based energy-efficient (ETPC) algorithm is proposed, implemented on the hardware and then compared with the several conventional TPC methods. Experimental results reveal that our developed chip collects real-time ECG data efficiently, and the proposed ETPC algorithm achieves higher energy savings of 35.5% with a slightly larger packet loss ratio (PLR) as compared to conventional TPC (e.g., constant TPC, Gao's, and Xiao's methods).

Empirical modeling of Single-Event Upset (SEU) in NMOS depletion-mode-load static RAM (SRAM) chips

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Smith, S. L.; Atwood, G. E.

1986-01-01

A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.

Neuromorphic vision sensors and preprocessors in system applications

NASA Astrophysics Data System (ADS)

Kramer, Joerg; Indiveri, Giacomo

1998-09-01

A partial review of neuromorphic vision sensors that are suitable for use in autonomous systems is presented. Interfaces are being developed to multiplex the high- dimensional output signals of arrays of such sensors and to communicate them in standard formats to off-chip devices for higher-level processing, actuation, storage and display. Alternatively, on-chip processing stages may be implemented to extract sparse image parameters, thereby obviating the need for multiplexing. Autonomous robots are used to test neuromorphic vision chips in real-world environments and to explore the possibilities of data fusion from different sensing modalities. Examples of autonomous mobile systems that use neuromorphic vision chips for line tracking and optical flow matching are described.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital receiver module with direct data acquisition for magnetic resonance imaging systems.

PubMed

Tang, Weinan; Sun, Hongyu; Wang, Weimin

2012-10-01

A digital receiver module for magnetic resonance imaging (MRI) with detailed hardware implementations is presented. The module is based on a direct sampling scheme using the latest mixed-signal circuit design techniques. A single field-programmable gate array chip is employed to perform software-based digital down conversion for radio frequency signals. The modular architecture of the receiver allows multiple acquisition channels to be implemented on a highly integrated printed circuit board. To maintain the phase coherence of the receiver and the exciter in the context of direct sampling, an effective phase synchronization method was proposed to achieve a phase deviation as small as 0.09°. The performance of the described receiver module was verified in the experiments for both low- and high-field (0.5 T and 1.5 T) MRI scanners and was compared to a modern commercial MRI receiver system.

Report on the formal specification and partial verification of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Brock, Bishop; Hunt, Warren A., Jr.

1991-01-01

The VIPER microprocessor chip is partitioned into four levels of abstractions. At the highest level, VIPER is described with decreasingly abstract sets of functions in LCF-LSM. At the lowest level are the gate-level models in proprietary CAD languages. The block-level and gate-level specifications are also given in the ELLA simulation language. Among VIPER's deficiencies are the fact that there is no notion of external events in the top-level specification, and it is impossible to use the top-level specifications to prove abstract properties of programs running on VIPER computers. There is no complete proof that the gate-level specifications implement the top-level specifications. Cohn's proof that the major-state machine correctly implements the top-level specifications has no formal connection with any of the other proof attempts. None of the latter address resetting the machine, memory timeout, forced error, or single step modes.

A Novel and Simple Spike Sorting Implementation.

PubMed

Petrantonakis, Panagiotis C; Poirazi, Panayiota

2017-04-01

Monitoring the activity of multiple, individual neurons that fire spikes in the vicinity of an electrode, namely perform a Spike Sorting (SS) procedure, comprises one of the most important tools for contemporary neuroscience in order to reverse-engineer the brain. As recording electrodes' technology rabidly evolves by integrating thousands of electrodes in a confined spatial setting, the algorithms that are used to monitor individual neurons from recorded signals have to become even more reliable and computationally efficient. In this work, we propose a novel framework of the SS approach in which a single-step processing of the raw (unfiltered) extracellular signal is sufficient for both the detection and sorting of the activity of individual neurons. Despite its simplicity, the proposed approach exhibits comparable performance with state-of-the-art approaches, especially for spike detection in noisy signals, and paves the way for a new family of SS algorithms with the potential for multi-recording, fast, on-chip implementations.

Intelligent Home Control System Based on Single Chip Microcomputer

NASA Astrophysics Data System (ADS)

Yang, Libo

2017-12-01

Intelligent home as a way to achieve the realization of the family information has become an important part of the development of social information, Internet of Things because of its huge application prospects, will be smart home industry in the development process of a more realistic breakthrough in the smart home industry development has great significance. This article is based on easy to implement, easy to operate, close to the use of the design concept, the use of STC89C52 microcontroller as the control core for the control terminal, and including infrared remote control, buttons, Web interface, including multiple control sources to control household appliances. The second chapter of this paper describes the design of the hardware and software part of the specific implementation, the fifth chapter is based on the design of a good function to build a specific example of the environment.

Rutger's CAM2000 chip architecture

NASA Technical Reports Server (NTRS)

Smith, Donald E.; Hall, J. Storrs; Miyake, Keith

1993-01-01

This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.

Semi-contact-writing of polymer molds for prototyping PDMS chips with low surface roughness, sharp edges and locally varying channel heights

NASA Astrophysics Data System (ADS)

Gutzweiler, Ludwig; Stumpf, Fabian; Tanguy, Laurent; Roth, Guenter; Koltay, Peter; Zengerle, Roland; Riegger, Lutz

2016-04-01

Microfluidic systems fabricated in polydimethylsiloxane (PDMS) enable a broad variety of applications and are widespread in the field of Lab-on-a-Chip. Here we demonstrate semi-contact-writing, a novel method for fabrication of polymer based molds for casting microfluidic PDMS chips in a highly flexible, time and cost-efficient manner. The method is related to direct-writing of an aqueous polymer solution on a planar glass substrate and substitutes conventional, time- and cost-consuming UV-lithography. This technique facilitates on-demand prototyping in a low-cost manner and is therefore ideally suited for rapid chip layout iterations. No cleanroom facilities and less expertise are required. Fabrication time from scratch to ready-to-use PDMS-chip is less than 5 h. This polymer writing method enables structure widths down to 140 μm and controllable structure heights ranging from 5.5 μm for writing single layers up to 98 μm by stacking. As a unique property, freely selectable height variations across a substrate can be achieved by application of local stacking. Furthermore, the molds exhibit low surface roughness (R a   =  24 nm, R RMS  =  28 nm) and high fidelity edge sharpness. We validated the method by fabrication of molds to cast PDMS chips for droplet based flow-through PCR with single-cell sensitivity.

[Theoretical foundations of protein chips and their possible use in medical research and diagnostics].

PubMed

Spisák, Sándor; Molnár, Béla; Galamb, Orsolya; Sipos, Ferenc; Tulassay, Zsolt

2007-08-12

The confirmation of mRNA expression studies by protein chips is of high recent interest due to the widespread application of expression arrays. In this review the advantages, technical limitations, application fields and the first results of the protein arrays is described. The bottlenecks of the increasing protein array applications are the fast decomposition of proteins, the problem with aspecific binding and the lack of amplification techniques. Today glass slide based printed, SELDI (MS) based, electrophoresis based and tissue microarray based technologies are available. The advantage of the glass slide based chips are the simplicity of their application, and relatively low cost. The SELDI based protein chip technique is applicable to minute amounts of starting material (<1 microg) but it is the most expensive one. The electrophoresis based techniques are still under intensive development. The tissue microarrays can be used for the parallel testing of the sensitivity and specificity of single antibodies on a broad range of histological specimens on a single slide. Protein chips were successfully used for serum tumor marker detection, cancer research, cell physiology studies and for the verification of mRNA expression studies. Protein chips are envisioned to be available for routine diagnostic applications if the ongoing technology development will be successful in increase in sensitivity, specificity, costs reduction and for the reduction of the necessary sample volume.

High-volume production of single and compound emulsions in a microfluidic parallelization arrangement coupled with coaxial annular world-to-chip interfaces.

PubMed

Nisisako, Takasi; Ando, Takuya; Hatsuzawa, Takeshi

2012-09-21

This study describes a microfluidic platform with coaxial annular world-to-chip interfaces for high-throughput production of single and compound emulsion droplets, having controlled sizes and internal compositions. The production module consists of two distinct elements: a planar square chip on which many copies of a microfluidic droplet generator (MFDG) are arranged circularly, and a cubic supporting module with coaxial annular channels for supplying fluids evenly to the inlets of the mounted chip, assembled from blocks with cylinders and holes. Three-dimensional flow was simulated to evaluate the distribution of flow velocity in the coaxial multiple annular channels. By coupling a 1.5 cm × 1.5 cm microfluidic chip with parallelized 144 MFDGs and a supporting module with two annular channels, for example, we could produce simple oil-in-water (O/W) emulsion droplets having a mean diameter of 90.7 μm and a coefficient of variation (CV) of 2.2% at a throughput of 180.0 mL h(-1). Furthermore, we successfully demonstrated high-throughput production of Janus droplets, double emulsions and triple emulsions, by coupling 1.5 cm × 1.5 cm - 4.5 cm × 4.5 cm microfluidic chips with parallelized 32-128 MFDGs of various geometries and supporting modules with 3-4 annular channels.

Perspective: Fabrication of integrated organ-on-a-chip via bioprinting.

PubMed

Yang, Qingzhen; Lian, Qin; Xu, Feng

2017-05-01

Organ-on-a-chip has emerged as a powerful platform with widespread applications in biomedical engineering, such as pathology studies and drug screening. However, the fabrication of organ-on-a-chip is still a challenging task due to its complexity. For an integrated organ-on-a-chip, it may contain four key elements, i.e., a microfluidic chip, live cells/microtissues that are cultured in this chip, components for stimulus loading to mature the microtissues, and sensors for results readout. Recently, bioprinting has been used for fabricating organ-on-a-chip as it enables the printing of multiple materials, including biocompatible materials and even live cells in a programmable manner with a high spatial resolution. Besides, all four elements for organ-on-a-chip could be printed in a single continuous procedure on one printer; in other words, the fabrication process is assembly free. In this paper, we discuss the recent advances of organ-on-a-chip fabrication by bioprinting. Light is shed on the printing strategies, materials, and biocompatibility. In addition, some specific bioprinted organs-on-chips are analyzed in detail. Because the bioprinted organ-on-a-chip is still in its early stage, significant efforts are still needed. Thus, the challenges presented together with possible solutions and future trends are also discussed.

On-chip integrated functional near infra-red spectroscopy (fNIRS) photoreceiver for portable brain imaging

NASA Astrophysics Data System (ADS)

Kamrani, Ehsan

Optical brain imaging using functional near infra-red spectroscopy (fNIRS) offers a direct and noninvasive tool for monitoring of blood oxygenation. fNIRS is a noninvasive, safe, minimally intrusive, and high temporal-resolution technique for real-time and long-term brain imaging. It allows detecting both fast-neuronal and slow-hemodynamic signals. Besides the significant advantages of fNIRS systems, they still suffer from few drawbacks including low spatial-resolution, moderately high-level noise and high-sensitivity to movement. In order to overcome the limitations of currently available non-portable fNIRS systems, we have introduced a new low-power, miniaturized on-chip photodetector front-end intended for portable fNIRS systems. It includes silicon avalanche photodiode (SiAPD), Transimpedance amplifier (TIA), and Quench- Reset circuitry implemented using standard CMOS technologies to operate in both linear and Geiger modes. So it can be applied for both continuous-wave fNIRS (CW-fNIRS) and also single-photon counting applications. Several SiAPDs have been implemented in novel structures and shapes (Rectangular, Octagonal, Dual, Nested, Netted, Quadratic and Hexadecagonal) using different premature edge breakdown prevention techniques. The main characteristics of the SiAPDs are validated and the impact of each parameter and the device simulators (TCAD, COMSOL, etc.) have been studied based on the simulation and measurement results. Proposed techniques exhibit SiAPDs with high avalanche-gain (up to 119), low breakdown-voltage (around 12V) and high photon-detection efficiency (up to 72% in NIR region) in additional to a low dark-count rate (down to 30Hz at 1V excess bias voltage). Three new high gain-bandwidth product (GBW) and low-noise TIAs are introduced and implemented based on distributed-gain concept, logarithmic-amplification and automatic noise-rejection and have been applied in linear-mode of operation. The implemented TIAs offer a power-consumption around 0.4 mW, transimpedance gain of 169 dBO, and input-output current/voltage noises in fA/pV range accompanied with ability to tune the gain, bandwidth and power-consumption in a wide range. The implemented mixed quench-reset circuit (MQC) and controllable MQC (CMQC) front-ends offer a quench-time of 10ns, a maximum power-consumption of 0.4 mW, with a controllable hold-off and reset-times. The on-chip integration of SiAPDs with TIA and photon-counting circuitries has been demonstrated showing improvement of the photodetection-efficiency, specially regarding to the sensitivity, power-consumption and signal-to-noise ratio (SNR) characteristics.

Neural Imaging Using Single-Photon Avalanche Diodes

PubMed Central

Karami, Mohammad Azim; Ansarian, Misagh

2017-01-01

Introduction: This paper analyses the ability of single-photon avalanche diodes (SPADs) for neural imaging. The current trend in the production of SPADs moves toward the minimum dark count rate (DCR) and maximum photon detection probability (PDP). Moreover, the jitter response which is the main measurement characteristic for the timing uncertainty is progressing. Methods: The neural imaging process using SPADs can be performed by means of florescence lifetime imaging (FLIM), time correlated single-photon counting (TCSPC), positron emission tomography (PET), and single-photon emission computed tomography (SPECT). Results: This trend will result in more precise neural imaging cameras. While achieving low DCR SPADs is difficult in deep submicron technologies because of using higher doping profiles, higher PDPs are reported in green and blue part of light. Furthermore, the number of pixels integrated in the same chip is increasing with the technology progress which can result in the higher resolution of imaging. Conclusion: This study proposes implemented SPADs in Deep-submicron technologies to be used in neural imaging cameras, due to the small size pixels and higher timing accuracies. PMID:28446946

Wiring up pre-characterized single-photon emitters by laser lithography

NASA Astrophysics Data System (ADS)

Shi, Q.; Sontheimer, B.; Nikolay, N.; Schell, A. W.; Fischer, J.; Naber, A.; Benson, O.; Wegener, M.

2016-08-01

Future quantum optical chips will likely be hybrid in nature and include many single-photon emitters, waveguides, filters, as well as single-photon detectors. Here, we introduce a scalable optical localization-selection-lithography procedure for wiring up a large number of single-photon emitters via polymeric photonic wire bonds in three dimensions. First, we localize and characterize nitrogen vacancies in nanodiamonds inside a solid photoresist exhibiting low background fluorescence. Next, without intermediate steps and using the same optical instrument, we perform aligned three-dimensional laser lithography. As a proof of concept, we design, fabricate, and characterize three-dimensional functional waveguide elements on an optical chip. Each element consists of one single-photon emitter centered in a crossed-arc waveguide configuration, allowing for integrated optical excitation and efficient background suppression at the same time.

Design and validation of a real-time spiking-neural-network decoder for brain-machine interfaces.

PubMed

Dethier, Julie; Nuyujukian, Paul; Ryu, Stephen I; Shenoy, Krishna V; Boahen, Kwabena

2013-06-01

Cortically-controlled motor prostheses aim to restore functions lost to neurological disease and injury. Several proof of concept demonstrations have shown encouraging results, but barriers to clinical translation still remain. In particular, intracortical prostheses must satisfy stringent power dissipation constraints so as not to damage cortex. One possible solution is to use ultra-low power neuromorphic chips to decode neural signals for these intracortical implants. The first step is to explore in simulation the feasibility of translating decoding algorithms for brain-machine interface (BMI) applications into spiking neural networks (SNNs). Here we demonstrate the validity of the approach by implementing an existing Kalman-filter-based decoder in a simulated SNN using the Neural Engineering Framework (NEF), a general method for mapping control algorithms onto SNNs. To measure this system's robustness and generalization, we tested it online in closed-loop BMI experiments with two rhesus monkeys. Across both monkeys, a Kalman filter implemented using a 2000-neuron SNN has comparable performance to that of a Kalman filter implemented using standard floating point techniques. These results demonstrate the tractability of SNN implementations of statistical signal processing algorithms on different monkeys and for several tasks, suggesting that a SNN decoder, implemented on a neuromorphic chip, may be a feasible computational platform for low-power fully-implanted prostheses. The validation of this closed-loop decoder system and the demonstration of its robustness and generalization hold promise for SNN implementations on an ultra-low power neuromorphic chip using the NEF.

Genome-wide Target Enrichment-aided Chip Design: a 66 K SNP Chip for Cashmere Goat.

PubMed

Qiao, Xian; Su, Rui; Wang, Yang; Wang, Ruijun; Yang, Ting; Li, Xiaokai; Chen, Wei; He, Shiyang; Jiang, Yu; Xu, Qiwu; Wan, Wenting; Zhang, Yaolei; Zhang, Wenguang; Chen, Jiang; Liu, Bin; Liu, Xin; Fan, Yixing; Chen, Duoyuan; Jiang, Huaizhi; Fang, Dongming; Liu, Zhihong; Wang, Xiaowen; Zhang, Yanjun; Mao, Danqing; Wang, Zhiying; Di, Ran; Zhao, Qianjun; Zhong, Tao; Yang, Huanming; Wang, Jian; Wang, Wen; Dong, Yang; Chen, Xiaoli; Xu, Xun; Li, Jinquan

2017-08-17

Compared with the commercially available single nucleotide polymorphism (SNP) chip based on the Bead Chip technology, the solution hybrid selection (SHS)-based target enrichment SNP chip is not only design-flexible, but also cost-effective for genotype sequencing. In this study, we propose to design an animal SNP chip using the SHS-based target enrichment strategy for the first time. As an update to the international collaboration on goat research, a 66 K SNP chip for cashmere goat was created from the whole-genome sequencing data of 73 individuals. Verification of this 66 K SNP chip with the whole-genome sequencing data of 436 cashmere goats showed that the SNP call rates was between 95.3% and 99.8%. The average sequencing depth for target SNPs were 40X. The capture regions were shown to be 200 bp that flank target SNPs. This chip was further tested in a genome-wide association analysis of cashmere fineness (fiber diameter). Several top hit loci were found marginally associated with signaling pathways involved in hair growth. These results demonstrate that the 66 K SNP chip is a useful tool in the genomic analyses of cashmere goats. The successful chip design shows that the SHS-based target enrichment strategy could be applied to SNP chip design in other species.

Netlist Oriented Sensitivity Evaluation (NOSE)

DTIC Science & Technology

2017-03-01

developing methodologies to assess sensitivities of alternative chip design netlist implementations. The research is somewhat foundational in that such...Netlist-Oriented Sensitivity Evaluation (NOSE) project was to develop methodologies to assess sensitivities of alternative chip design netlist...analysis to devise a methodology for scoring the sensitivity of circuit nodes in a netlist and thus providing the raw data for any meaningful

The Level 0 Pixel Trigger system for the ALICE experiment

NASA Astrophysics Data System (ADS)

Aglieri Rinella, G.; Kluge, A.; Krivda, M.; ALICE Silicon Pixel Detector project

2007-01-01

The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper.

BANSAI - An optofluidic approach for biomedical analysis

NASA Astrophysics Data System (ADS)

Knoerzer, Markus; Prokop, Christoph; Rodrigues Ribeiro, Graciete M.; Mayer, Horst; Brümmer, Jens; Mitchell, Arnan; Rabus, Dominik G.; Karnutsch, Christian

2015-12-01

Lab-on-a-chip based portable blood analysis systems would allow point-of-care measurements, e.g. in an ambulance, or in remote areas with no fast access to medical care. Such a systemwould provide much faster information about the health of a patient. Here,we present a system that is based on absorption spectroscopy and uses an organic laser, which is tunable in the visible range. The feasibility of the system is shown with a table-top setup using laboratory equipment. Measurements of human albumin show linear behaviour in a range from 2.5 g/L to 60 g/L. In a consecutive setup the system is implemented on a microfluidic chip and is capable of measuring simultaneously transmitted and side scattered intensities, even with ambient light present. Air-suspended grating couplers on polymers are shown as the first element of a lab-on-a-chip implementation.

BANSAI - An optofluidic approach for biomedical analysis

NASA Astrophysics Data System (ADS)

Knoerzer, Markus; Prokop, Christoph; Rodrigues Ribeiro, Graciete M.; Mayer, Horst; Brümmer, Jens; Mitchell, Arnan; Rabus, Dominik G.; Karnutsch, Christian

2016-02-01

Lab-on-a-chip based portable blood analysis systems would allow point-of-care measurements, e.g. in an ambulance, or in remote areas with no fast access to medical care. Such a systemwould provide much faster information about the health of a patient. Here,we present a system that is based on absorption spectroscopy and uses an organic laser, which is tunable in the visible range. The feasibility of the system is shown with a table-top setup using laboratory equipment. Measurements of human albumin show linear behaviour in a range from 2.5 g/L to 60 g/L. In a consecutive setup the system is implemented on a microfluidic chip and is capable of measuring simultaneously transmitted and side scattered intensities, even with ambient light present. Air-suspended grating couplers on polymers are shown as the first element of a lab-on-a-chip implementation.

Biosensor system-on-a-chip including CMOS-based signal processing circuits and 64 carbon nanotube-based sensors for the detection of a neurotransmitter.

PubMed

Lee, Byung Yang; Seo, Sung Min; Lee, Dong Joon; Lee, Minbaek; Lee, Joohyung; Cheon, Jun-Ho; Cho, Eunju; Lee, Hyunjoong; Chung, In-Young; Park, Young June; Kim, Suhwan; Hong, Seunghun

2010-04-07

We developed a carbon nanotube (CNT)-based biosensor system-on-a-chip (SoC) for the detection of a neurotransmitter. Here, 64 CNT-based sensors were integrated with silicon-based signal processing circuits in a single chip, which was made possible by combining several technological breakthroughs such as efficient signal processing, uniform CNT networks, and biocompatible functionalization of CNT-based sensors. The chip was utilized to detect glutamate, a neurotransmitter, where ammonia, a byproduct of the enzymatic reaction of glutamate and glutamate oxidase on CNT-based sensors, modulated the conductance signals to the CNT-based sensors. This is a major technological advancement in the integration of CNT-based sensors with microelectronics, and this chip can be readily integrated with larger scale lab-on-a-chip (LoC) systems for various applications such as LoC systems for neural networks.

Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network

NASA Astrophysics Data System (ADS)

Cohen, Marc H.; Andreou, Andreas G.

1992-05-01

The translinear circuits in subthreshold MOS technology and current-mode design techniques for the implementation of neuromorphic analog network processing are investigated. The architecture, also known as the Herault-Jutten network, performs an independent component analysis and is essentially a continuous-time recursive linear adaptive filter. Analog I/O interface, weight coefficients, and adaptation blocks are all integrated on the chip. A small network with six neurons and 30 synapses was fabricated in a 2-microns n-well double-polysilicon, double-metal CMOS process. Circuit designs at the transistor level yield area-efficient implementations for neurons, synapses, and the adaptation blocks. The design methodology and constraints as well as test results from the fabricated chips are discussed.

Observing fermionic statistics with photons in arbitrary processes

PubMed Central

Matthews, Jonathan C. F.; Poulios, Konstantinos; Meinecke, Jasmin D. A.; Politi, Alberto; Peruzzo, Alberto; Ismail, Nur; Wörhoff, Kerstin; Thompson, Mark G.; O'Brien, Jeremy L.

2013-01-01

Quantum mechanics defines two classes of particles-bosons and fermions-whose exchange statistics fundamentally dictate quantum dynamics. Here we develop a scheme that uses entanglement to directly observe the correlated detection statistics of any number of fermions in any physical process. This approach relies on sending each of the entangled particles through identical copies of the process and by controlling a single phase parameter in the entangled state, the correlated detection statistics can be continuously tuned between bosonic and fermionic statistics. We implement this scheme via two entangled photons shared across the polarisation modes of a single photonic chip to directly mimic the fermion, boson and intermediate behaviour of two-particles undergoing a continuous time quantum walk. The ability to simulate fermions with photons is likely to have applications for verifying boson scattering and for observing particle correlations in analogue simulation using any physical platform that can prepare the entangled state prescribed here. PMID:23531788

Optical spectroscopy and photo modification of individual single-photon emitters in hexagonal boron nitride

NASA Astrophysics Data System (ADS)

Jayakumar, Harishankar; Shotan, Zav; Considine, Christopher; Mazkoit, Mažena; Fedder, Helmut; Wrachtrup, Joerg; Alkauskas, Audrius; Doherty, Marcus; Menon, Vinod; Meriles, Carlos

Fluorescent defects recently observed under ambient conditions in hexagonal boron nitride (h-BN) promise to open novel opportunities for the implementation of on-chip photonic devices that rely on identical photons from single emitters. Here we report on the room temperature photo-luminescence dynamics of individual emitters in multilayer h-BN flakes exposed to blue laser light. Comparison of optical spectra recorded at successive times reveals considerable spectral diffusion, possibly the result of slowly fluctuating, trapped-carrier-induced stark shifts. Large spectral jumps - reaching up to 100 nm - followed by bleaching are observed in most cases upon prolonged exposure to blue light, an indication of one-directional, photo-chemical changes likely taking place on the flake surface. Remarkably, only a fraction of the observed emitters also fluoresces on green illumination suggesting a more complex optical excitation dynamics than previously anticipated and raising questions on the physical nature of the atomic defect at play.

The Nano-Patch-Clamp Array: Microfabricated Glass Chips for High-Throughput Electrophysiology

NASA Astrophysics Data System (ADS)

Fertig, Niels

2003-03-01

Electrophysiology (i.e. patch clamping) remains the gold standard for pharmacological testing of putative ion channel active drugs (ICADs), but suffers from low throughput. A new ion channel screening technology based on microfabricated glass chip devices will be presented. The glass chips contain very fine apertures, which are used for whole-cell voltage clamp recordings as well as single channel recordings from mammalian cell lines. Chips containing multiple patch clamp wells will be used in a first bench-top device, which will allow perfusion and electrical readout of each well. This scalable technology will allow for automated, rapid and parallel screening on ion channel drug targets.

Droplet-based micro oscillating-flow PCR chip

NASA Astrophysics Data System (ADS)

Wang, Wei; Li, Zhi-Xin; Luo, Rong; Lü, Shu-Hai; Xu, Ai-Dong; Yang, Yong-Jun

2005-08-01

Polymerase chain reactions (PCR), thermally activated chemical reactions which are widely used for nucleic acid amplification, have recently received much attention in microelectromechanical systems and micro total analysis systems because a wide variety of DNA/RNA molecules can be enriched by PCR for further analyses. In the present work, a droplet-based micro oscillating-flow PCR chip was designed and fabricated by the silicon microfabrication technique. Three different temperature zones, which were stable at denaturation, extension and annealing temperatures and isolated from each other by a thin-wall linkage, were integrated with a single, simple and straight microchannel to form the chip's basic functional structure. The PCR mixture was injected into the chip as a single droplet and flowed through the three temperature zones in the main microchannel in an oscillating manner to achieve the temperature maintenance and transitions. The chip's thermal performance was theoretically analyzed and numerically simulated. The results indicated that the time needed for the temperature of the droplet to change to the target value is less than 1 s, and the root mean square error of temperature is less than 0.2 °C. A droplet of 1 µl PCR mixture with standard HPV (Human Papilloma Virus)-DNA sample inside was amplified by the present chip and the results were analyzed by slab gel electrophoresis with separation of DNA markers in parallel. The electrophoresis results demonstrated that the micro oscillating-flow PCR chip successfully amplified the HPV-DNA, with a processing time of about 15 min which is significantly reduced compared to that for the conventional PCR instrument.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Nonreciprocal frequency conversion in a multimode microwave optomechanical circuit

NASA Astrophysics Data System (ADS)

Feofanov, A. K.; Bernier, N. R.; Toth, L. D.; Koottandavida, A.; Kippenberg, T. J.

Nonreciprocal devices such as isolators, circulators, and directional amplifiers are pivotal to quantum signal processing with superconducting circuits. In the microwave domain, commercially available nonreciprocal devices are based on ferrite materials. They are barely compatible with superconducting quantum circuits, lossy, and cannot be integrated on chip. Significant potential exists for implementing non-magnetic chip-scale nonreciprocal devices using microwave optomechanical circuits. Here we demonstrate a possibility of nonreciprocal frequency conversion in a multimode microwave optomechanical circuit using solely optomechanical interaction between modes. The conversion scheme and the results reflecting the actual progress on the experimental implementation of the scheme will be presented.

Digital Microfluidics Assisted Sealing of Individual Magnetic Particles in Femtoliter-Sized Reaction Wells for Single-Molecule Detection.

PubMed

Decrop, Deborah; Ruiz, Elena Pérez; Kumar, Phalguni Tewari; Tripodi, Lisa; Kokalj, Tadej; Lammertyn, Jeroen

2017-01-01

Digital microfluidics has emerged in the last years as a promising liquid handling technology for a variety of applications. Here, we describe in detail how to build up an electrowetting-on-dielectric-based digital microfluidic chip with unique advantages for performing single-molecule detection. We illustrate how superparamagnetic particles can be printed with very high loading efficiency (over 98 %) and single-particle resolution in the microwell array patterned in the Teflon-AF ® surface of the grounding plate of the chip. Finally, the potential of the device for its application to single-molecule detection is demonstrated by the ultrasensitive detection of the biotinylated enzyme β-Galactosidase captured on streptavidin-coated particles in the described platform.

Engineering on-chip nanoporous gold material libraries via precision photothermal treatment [Precision Photothermal Annealing of Nanoporous Gold Thin Films for the Microfabrication of a Single-ship Material Libraries

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chapman, Christopher A. R.; Wang, Ling; Biener, Juergen

Single-chip material libraries of thin films of nanostructured materials are a promising approach for high throughput studies of structure-property relationship in the fields of physics and biology. Nanoporous gold (np-Au), produced by an alloy corrosion process, is a nanostructured material of specific interest in both these fields. One attractive property of np-Au is its self-similar coarsening behavior by thermally induced surface diffusion. However, traditional heat application techniques for the modification of np-Au are bulk processes that cannot be used to generate a library of different pore sizes on a single chip. Laser micromachining offers an attractive solution to this problemmore » by providing a means to apply energy with high spatial and temporal resolution. In our present study we use finite element multiphysics simulations to predict the effects of laser mode (continuous-wave vs. pulsed) and supporting substrate thermal conductivity on the local np-Au film temperatures during photothermal annealing and subsequently investigate the mechanisms by which the np-Au network is coarsening. Our simulations predict that continuous-wave mode laser irradiation on a silicon supporting substrate supports the widest range of morphologies that can be created through the photothermal annealing of thin film np-Au. Using this result we successfully fabricate a single-chip material library consisting of 81 np-Au samples of 9 different morphologies for use in increased throughput material interaction studies.« less

Precision Photothermal Annealing of Nanoporous Gold Thin Films for the Microfabrication of a Single-chip Material Libraries

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harris, C. D.; Shen, N.; Rubenchik, A.

2015-06-30

Single-chip material libraries of thin films of nanostructured materials are a promising approach for high throughput studies of structure-property relationship in the fields of physics and biology. Nanoporous gold (np-Au), produced by an alloy corrosion process, is a nanostructured material of specific interest in both these fields. One attractive property of np-Au is its self-similar coarsening behavior by thermally induced surface diffusion. However, traditional heat application techniques for the modification of np-Au are bulk processes that cannot be used to generate a library of different pore sizes on a single chip. Laser micromachining offers an attractive solution to this problemmore » by providing a means to apply energy with high spatial and temporal resolution. In the present study we use finite element multiphysics simulations to predict the effects of laser mode (continuous-wave vs. pulsed) and supporting substrate thermal conductivity on the local np-Au film temperatures during photothermal annealing and subsequently investigate the mechanisms by which the np-Au network is coarsening. Our simulations predict that continuous-wave mode laser irradiation on a silicon supporting substrate supports the widest range of morphologies that can be created through the photothermal annealing of thin film np-Au. Using this result we successfully fabricate a single-chip material library consisting of 81 np-Au samples of 9 different morphologies for use in increased throughput material interaction studies.« less

Engineering on-chip nanoporous gold material libraries via precision photothermal treatment [Precision Photothermal Annealing of Nanoporous Gold Thin Films for the Microfabrication of a Single-ship Material Libraries

DOE PAGES

Chapman, Christopher A. R.; Wang, Ling; Biener, Juergen; ...

2016-01-01

Single-chip material libraries of thin films of nanostructured materials are a promising approach for high throughput studies of structure-property relationship in the fields of physics and biology. Nanoporous gold (np-Au), produced by an alloy corrosion process, is a nanostructured material of specific interest in both these fields. One attractive property of np-Au is its self-similar coarsening behavior by thermally induced surface diffusion. However, traditional heat application techniques for the modification of np-Au are bulk processes that cannot be used to generate a library of different pore sizes on a single chip. Laser micromachining offers an attractive solution to this problemmore » by providing a means to apply energy with high spatial and temporal resolution. In our present study we use finite element multiphysics simulations to predict the effects of laser mode (continuous-wave vs. pulsed) and supporting substrate thermal conductivity on the local np-Au film temperatures during photothermal annealing and subsequently investigate the mechanisms by which the np-Au network is coarsening. Our simulations predict that continuous-wave mode laser irradiation on a silicon supporting substrate supports the widest range of morphologies that can be created through the photothermal annealing of thin film np-Au. Using this result we successfully fabricate a single-chip material library consisting of 81 np-Au samples of 9 different morphologies for use in increased throughput material interaction studies.« less

ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

NASA Astrophysics Data System (ADS)

Shao, Rui; Zhong, Sheng; Yan, Luxin

2015-12-01

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium-large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

Tough silk fibers prepared in air using a biomimetic microfluidic chip.

PubMed

Luo, Jie; Zhang, Lele; Peng, Qingfa; Sun, Mengjie; Zhang, Yaopeng; Shao, Huili; Hu, Xuechao

2014-05-01

Microfluidic chips with single channel were built to mimic the shear and elongation conditions in the spinning apparatus of spider and silkworm. Silk fibers dry-spun from regenerated silk fibroin (RSF) aqueous solution using the chip could be tougher than degummed natural silk. The artificial silk exhibited a breaking strength up to 614 MPa, a breaking elongation up to 27% and a breaking energy of 101 kJ/kg. Copyright © 2014 Elsevier B.V. All rights reserved.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Microfluidic "Pouch" Chips for Immunoassays and Nucleic Acid Amplification Tests.

PubMed

Mauk, Michael G; Liu, Changchun; Qiu, Xianbo; Chen, Dafeng; Song, Jinzhao; Bau, Haim H

2017-01-01

Microfluidic cassettes ("chips") for processing and analysis of clinical specimens and other sample types facilitate point-of-care (POC) immunoassays and nucleic acid based amplification tests. These single-use test chips can be self-contained and made amenable to autonomous operation-reducing or eliminating supporting instrumentation-by incorporating laminated, pliable "pouch" and membrane structures for fluid storage, pumping, mixing, and flow control. Materials and methods for integrating flexible pouch compartments and diaphragm valves into hard plastic (e.g., acrylic and polycarbonate) microfluidic "chips" for reagent storage, fluid actuation, and flow control are described. We review several versions of these pouch chips for immunoassay and nucleic acid amplification tests, and describe related fabrication techniques. These protocols thus offer a "toolbox" of methods for storage, pumping, and flow control functions in microfluidic devices.

Flexible High Speed Codec (FHSC)

NASA Technical Reports Server (NTRS)

Segallis, G. P.; Wernlund, J. V.

1991-01-01

The ongoing NASA/Harris Flexible High Speed Codec (FHSC) program is described. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K emitter coupled logic (ECL) which can be easily translated to an ECL gate array.

Transferrable monolithic multicomponent system for near-ultraviolet optoelectronics

NASA Astrophysics Data System (ADS)

Qin, Chuan; Gao, Xumin; Yuan, Jialei; Shi, Zheng; Jiang, Yuan; Liu, Yuhuai; Wang, Yongjin; Amano, Hiroshi

2018-05-01

A monolithic near-ultraviolet multicomponent system is implemented on a 0.8-mm-diameter suspended membrane by integrating a transmitter, waveguide, and receiver into a single chip. Two identical InGaN/Al0.10Ga0.90N multiple-quantum well (MQW) diodes are fabricated using the same process flow, which separately function as a transmitter and receiver. There is a spectral overlap between the emission and detection spectra of the MQW diodes. Therefore, the receiver can respond to changes in the emission of the transmitter. The multicomponent system is mechanically transferred from silicon, and the wire-bonded transmitter on glass experimentally demonstrates spatial light transmission at 200 Mbps using non-return-to-zero on–off keying modulation.

A CBLT and MCST capable VME slave interface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wuerthwein, F.; Strohman, C.; Honscheid, K.

1996-12-31

We report on the development of a VME slave interface for the CLEO III detector implemented in an ALTERA EPM7256 CPLD. This includes the first implementation of the chained block transfer protocol (CBLT) and multi-cast cycles (MCST) as defined by the VME-P task group of VIPA. Within VME64 there is no operation that guarantees efficient readout of large blocks of data that are sparsely distributed among a series of slave modules in a VME crate. This has led the VME-P task group of VIPA to specify protocols that enable a master to address many slaves at a single address. Whichmore » slave is to drive the data bus is determined by a token passing mechanism that uses the *IACKOUT, *IACKIN daisy chain. This protocol requires no special features from the master besides conformance to VME64. Non-standard features are restricted to the VME slave interface. The CLEO III detector comprises {approximately}400,000 electronic channels that have to be digitized, sparsified, and stored within 20{mu}s in order to incur less than 2% dead time at an anticipated trigger rate of 1000Hz. 95% of these channels are accounted for by only two detector subsystems, the silicon microstrip detector (125,000 channels), and the ring imaging Cerenkov detector (RICH) (230,400 channels). After sparsification either of these two detector subsystems is expected to provide event fragments on the order of 10KBytes, spread over 4, and 8 VME crates, respectively. We developed a chip set that sparsifies, tags, and stores the incoming digital data on the data boards, and includes a VME slave interface that implements MCST and CUT protocols. In this poster, we briefly describe this chip set and then discuss the VME slave interface in detail.« less

FPGA-based digital signal processing for the next generation radio astronomy instruments: ultra-pure sideband separation and polarization detection

NASA Astrophysics Data System (ADS)

Alvear, Andrés.; Finger, Ricardo; Fuentes, Roberto; Sapunar, Raúl; Geelen, Tom; Curotto, Franco; Rodríguez, Rafael; Monasterio, David; Reyes, Nicolás.; Mena, Patricio; Bronfman, Leonardo

2016-07-01

Field Programmable Gate Arrays (FPGAs) capacity and Analog to Digital Converters (ADCs) speed have largely increased in the last decade. Nowadays we can find one million or more logic blocks (slices) as well as several thousand arithmetic units (ALUs/DSP) available on a single FPGA chip. We can also commercially procure ADC chips reaching 10 GSPS, with 8 bits resolution or more. This unprecedented power of computing hardware has allowed the digitalization of signal processes traditionally performed by analog components. In radio astronomy, the clearest example has been the development of digital sideband separating receivers which, by replacing the IF hybrid and calibrating the system imbalances, have exhibited a sideband rejection above 40dB; this is 20 to 30dB higher than traditional analog sideband separating (2SB) receivers. In Rodriguez et al.,1 and Finger et al.,2 we have demonstrated very high digital sideband separation at 3mm and 1mm wavelengths, using laboratory setups. We here show the first implementation of such technique with a 3mm receiver integrated into a telescope, where the calibration was performed by quasi-optical injection of the test tone in front of the Cassegrain antenna. We also reported progress in digital polarization synthesis, particularly in the implementation of a calibrated Digital Ortho-Mode Transducer (DOMT) based on the Morgan et al. proof of concept.3 They showed off- line synthesis of polarization with isolation higher than 40dB. We plan to implement a digital polarimeter in a real-time FPGA-based (ROACH-2) platform, to show ultra-pure polarization isolation in a non-stop integrating spectrometer.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Quantitative phase imaging of biological cells and tissues using singleshot white light interference microscopy and phase subtraction method for extended range of measurement

NASA Astrophysics Data System (ADS)

Mehta, Dalip Singh; Sharma, Anuradha; Dubey, Vishesh; Singh, Veena; Ahmad, Azeem

2016-03-01

We present a single-shot white light interference microscopy for the quantitative phase imaging (QPI) of biological cells and tissues. A common path white light interference microscope is developed and colorful white light interferogram is recorded by three-chip color CCD camera. The recorded white light interferogram is decomposed into the red, green and blue color wavelength component interferograms and processed it to find out the RI for different color wavelengths. The decomposed interferograms are analyzed using local model fitting (LMF)" algorithm developed for reconstructing the phase map from single interferogram. LMF is slightly off-axis interferometric QPI method which is a single-shot method that employs only a single image, so it is fast and accurate. The present method is very useful for dynamic process where path-length changes at millisecond level. From the single interferogram a wavelength-dependent quantitative phase imaging of human red blood cells (RBCs) are reconstructed and refractive index is determined. The LMF algorithm is simple to implement and is efficient in computation. The results are compared with the conventional phase shifting interferometry and Hilbert transform techniques.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

[Development of molecular detection of food-borne pathogenic bacteria using miniaturized microfluidic devices].

PubMed

Iván, Kristóf; Maráz, Anna

2015-12-20

Detection and identification of food-borne pathogenic bacteria are key points for the assurance of microbiological food safety. Traditional culture-based methods are more and more replaced by or supplemented with nucleic acid based molecular techniques, targeting specific (preferably virulence) genes in the genomes. Internationally validated DNA amplification - most frequently real-time polymerase chain reaction - methods are applied by the food microbiological testing laboratories for routine analysis, which will result not only in shortening the time for results but they also improve the performance characteristics (e.g. sensitivity, specificity) of the methods. Beside numerous advantages of the polymerase chain reaction based techniques for routine microbiological analysis certain drawbacks have to be mentioned, such as the high cost of the equipment and reagents, as well as the risk of contamination of the laboratory environment by the polymerase chain reaction amplicons, which require construction of an isolated laboratory system. Lab-on-a-chip systems can integrate most of these laboratory processes within a miniaturized device that delivers the same specificity and reliability as the standard protocols. The benefits of miniaturized devices are: simple - often automated - use, small overall size, portability, sterility due to single use possibility. These miniaturized rapid diagnostic tests are being researched and developed at the best research centers around the globe implementing various sample preparation and molecular DNA amplification methods on-chip. In parallel, the aim of the authors' research is to develop microfluidic Lab-on-a-chip devices for the detection and identification of food-borne pathogenic bacteria.

Plug-and-play, infrared, laser-mediated PCR in a microfluidic chip.

PubMed

Pak, Nikita; Saunders, D Curtis; Phaneuf, Christopher R; Forest, Craig R

2012-04-01

Microfluidic polymerase chain reaction (PCR) systems have set milestones for small volume (100 nL-5 μL), amplification speed (100-400 s), and on-chip integration of upstream and downstream sample handling including purification and electrophoretic separation functionality. In practice, the microfluidic chips in these systems require either insertion of thermocouples or calibration prior to every amplification. These factors can offset the speed advantages of microfluidic PCR and have likely hindered commercialization. We present an infrared, laser-mediated, PCR system that features a single calibration, accurate and repeatable precision alignment, and systematic thermal modeling and management for reproducible, open-loop control of PCR in 1 μL chambers of a polymer microfluidic chip. Total cycle time is less than 12 min: 1 min to fill and seal, 10 min to amplify, and 1 min to recover the sample. We describe the design, basis for its operation, and the precision engineering in the system and microfluidic chip. From a single calibration, we demonstrate PCR amplification of a 500 bp amplicon from λ-phage DNA in multiple consecutive trials on the same instrument as well as multiple identical instruments. This simple, relatively low-cost plug-and-play design is thus accessible to persons who may not be skilled in assembly and engineering.

3D nanofabrication inside rapid prototyped microfluidic channels showcased by wet-spinning of single micrometre fibres.

PubMed

Lölsberg, Jonas; Linkhorst, John; Cinar, Arne; Jans, Alexander; Kuehne, Alexander J C; Wessling, Matthias

2018-05-01

Microfluidics is an established multidisciplinary research domain with widespread applications in the fields of medicine, biotechnology and engineering. Conventional production methods of microfluidic chips have been limited to planar structures, preventing the exploitation of truly three-dimensional architectures for applications such as multi-phase droplet preparation or wet-phase fibre spinning. Here the challenge of nanofabrication inside a microfluidic chip is tackled for the showcase of a spider-inspired spinneret. Multiphoton lithography, an additive manufacturing method, was used to produce free-form microfluidic masters, subsequently replicated by soft lithography. Into the resulting microfluidic device, a three-dimensional spider-inspired spinneret was directly fabricated in-chip via multiphoton lithography. Applying this unprecedented fabrication strategy, the to date smallest printed spinneret nozzle is produced. This spinneret resides tightly sealed, connecting it to the macroscopic world. Its functionality is demonstrated by wet-spinning of single-digit micron fibres through a polyacrylonitrile coagulation process induced by a water sheath layer. The methodology developed here demonstrates fabrication strategies to interface complex architectures into classical microfluidic platforms. Using multiphoton lithography for in-chip fabrication adopts a high spatial resolution technology for improving geometry and thus flow control inside microfluidic chips. The showcased fabrication methodology is generic and will be applicable to multiple challenges in fluid control and beyond.

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

NASA Astrophysics Data System (ADS)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

Micromachined mirrors for raster-scanning displays and optical fiber switches

NASA Astrophysics Data System (ADS)

Hagelin, Paul Merritt

Micromachines and micro-optics have the potential to shrink the size and cost of free-space optical systems, enabling a new generation of high-performance, compact projection displays and telecommunications equipment. In raster-scanning displays and optical fiber switches, a free-space optical beam can interact with multiple tilt- up micromirrors fabricated on a single substrate. The size, rotation angle, and flatness of the mirror surfaces determine the number of pixels in a raster-display or ports in an optical switch. Single-chip and two-chip optical raster display systems demonstrate static mirror curvature correction, an integrated electronic driver board, and dynamic micromirror performance. Correction for curvature caused by a stress gradient in the micromirror leads to resolution of 102 by 119 pixels in the single-chip display. The optical design of the two-chip display features in-situ mirror curvature measurement and adjustable image magnification with a single output lens. An electronic driver board synchronizes modulation of the optical source with micromirror actuation for the display of images. Dynamic off-axis mirror motion is shown to have minimal influence on resolution. The confocal switch, a free-space optical fiber cross- connect, incorporates micromirrors having a design similar to the image-refresh scanner. Two micromirror arrays redirect optical beams from an input fiber array to the output fibers. The switch architecture supports simultaneous switching of multiple wavelength channels. A 2x2 switch configuration, using single-mode optical fiber at 1550 mn, is demonstrated with insertion loss of -4.2 dB and cross-talk of -50.5 dB. The micromirrors have sufficient size and angular range for scaling to a 32x32 cross-connect switch that has low insertion-loss and low cross-talk.

Application of quantum-dot multi-wavelength lasers and silicon photonic ring resonators to data-center optical interconnects

NASA Astrophysics Data System (ADS)

Beckett, Douglas J. S.; Hickey, Ryan; Logan, Dylan F.; Knights, Andrew P.; Chen, Rong; Cao, Bin; Wheeldon, Jeffery F.

2018-02-01

Quantum dot comb sources integrated with silicon photonic ring-resonator filters and modulators enable the realization of optical sub-components and modules for both inter- and intra-data-center applications. Low-noise, multi-wavelength, single-chip, laser sources, PAM4 modulation and direct detection allow a practical, scalable, architecture for applications beyond 400 Gb/s. Multi-wavelength, single-chip light sources are essential for reducing power dissipation, space and cost, while silicon photonic ring resonators offer high-performance with space and power efficiency.

K-band single-chip electron spin resonance detector.

PubMed

Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

2012-04-01

We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

Reconfigurable Solid-state Dye-doped Polymer Ring Resonator Lasers

NASA Astrophysics Data System (ADS)

Chandrahalim, Hengky; Fan, Xudong

2015-12-01

This paper presents wavelength configurable on-chip solid-state ring lasers fabricated by a single-mask standard lithography. The single- and coupled-ring resonator hosts were fabricated on a fused-silica wafer and filled with 3,3‧-Diethyloxacarbocyanine iodide (CY3), Rhodamine 6G (R6G), and 3,3‧-Diethylthiadicarbocyanine iodide (CY5)-doped polymer as the reconfigurable gain media. The recorded lasing threshold was ~220 nJ/mm2 per pulse for the single-ring resonator laser with R6G, marking the lowest threshold shown by solid-state dye-doped polymer lasers fabricated with a standard lithography process on a chip. A single-mode lasing from a coupled-ring resonator system with the lasing threshold of ~360 nJ/mm2 per pulse was also demonstrated through the Vernier effect. The renewability of the dye-doped polymer was examined by removing and redepositing the dye-doped polymer on the same resonator hosts for multiple cycles. We recorded consistent emissions from the devices for all trials, suggesting the feasibility of employing this technology for numerous photonic and biochemical sensing applications that entail for sustainable, reconfigurable, and low lasing threshold coherent light sources on a chip.

Reconfigurable Solid-state Dye-doped Polymer Ring Resonator Lasers

PubMed Central

Chandrahalim, Hengky; Fan, Xudong

2015-01-01

This paper presents wavelength configurable on-chip solid-state ring lasers fabricated by a single-mask standard lithography. The single- and coupled-ring resonator hosts were fabricated on a fused-silica wafer and filled with 3,3′-Diethyloxacarbocyanine iodide (CY3), Rhodamine 6G (R6G), and 3,3′-Diethylthiadicarbocyanine iodide (CY5)-doped polymer as the reconfigurable gain media. The recorded lasing threshold was ~220 nJ/mm2 per pulse for the single-ring resonator laser with R6G, marking the lowest threshold shown by solid-state dye-doped polymer lasers fabricated with a standard lithography process on a chip. A single-mode lasing from a coupled-ring resonator system with the lasing threshold of ~360 nJ/mm2 per pulse was also demonstrated through the Vernier effect. The renewability of the dye-doped polymer was examined by removing and redepositing the dye-doped polymer on the same resonator hosts for multiple cycles. We recorded consistent emissions from the devices for all trials, suggesting the feasibility of employing this technology for numerous photonic and biochemical sensing applications that entail for sustainable, reconfigurable, and low lasing threshold coherent light sources on a chip. PMID:26674508

Reconfigurable Solid-state Dye-doped Polymer Ring Resonator Lasers.

PubMed

Chandrahalim, Hengky; Fan, Xudong

2015-12-17

This paper presents wavelength configurable on-chip solid-state ring lasers fabricated by a single-mask standard lithography. The single- and coupled-ring resonator hosts were fabricated on a fused-silica wafer and filled with 3,3'-Diethyloxacarbocyanine iodide (CY3), Rhodamine 6G (R6G), and 3,3'-Diethylthiadicarbocyanine iodide (CY5)-doped polymer as the reconfigurable gain media. The recorded lasing threshold was ~220 nJ/mm(2) per pulse for the single-ring resonator laser with R6G, marking the lowest threshold shown by solid-state dye-doped polymer lasers fabricated with a standard lithography process on a chip. A single-mode lasing from a coupled-ring resonator system with the lasing threshold of ~360 nJ/mm(2) per pulse was also demonstrated through the Vernier effect. The renewability of the dye-doped polymer was examined by removing and redepositing the dye-doped polymer on the same resonator hosts for multiple cycles. We recorded consistent emissions from the devices for all trials, suggesting the feasibility of employing this technology for numerous photonic and biochemical sensing applications that entail for sustainable, reconfigurable, and low lasing threshold coherent light sources on a chip.

Self-digitization microfluidic chip for absolute quantification of mRNA in single cells.

PubMed

Thompson, Alison M; Gansen, Alexander; Paguirigan, Amy L; Kreutz, Jason E; Radich, Jerald P; Chiu, Daniel T

2014-12-16

Quantification of mRNA in single cells provides direct insight into how intercellular heterogeneity plays a role in disease progression and outcomes. Quantitative polymerase chain reaction (qPCR), the current gold standard for evaluating gene expression, is insufficient for providing absolute measurement of single-cell mRNA transcript abundance. Challenges include difficulties in handling small sample volumes and the high variability in measurements. Microfluidic digital PCR provides far better sensitivity for minute quantities of genetic material, but the typical format of this assay does not allow for counting of the absolute number of mRNA transcripts samples taken from single cells. Furthermore, a large fraction of the sample is often lost during sample handling in microfluidic digital PCR. Here, we report the absolute quantification of single-cell mRNA transcripts by digital, one-step reverse transcription PCR in a simple microfluidic array device called the self-digitization (SD) chip. By performing the reverse transcription step in digitized volumes, we find that the assay exhibits a linear signal across a wide range of total RNA concentrations and agrees well with standard curve qPCR. The SD chip is found to digitize a high percentage (86.7%) of the sample for single-cell experiments. Moreover, quantification of transferrin receptor mRNA in single cells agrees well with single-molecule fluorescence in situ hybridization experiments. The SD platform for absolute quantification of single-cell mRNA can be optimized for other genes and may be useful as an independent control method for the validation of mRNA quantification techniques.

Single-use thermoplastic microfluidic burst valves enabling on-chip reagent storage

PubMed Central

Rahmanian, Omid D.

2014-01-01

A simple and reliable method for fabricating single-use normally closed burst valves in thermoplastic microfluidic devices is presented, using a process flow that is readily integrated into established workflows for the fabrication of thermoplastic microfluidics. An experimental study of valve performance reveals the relationships between valve geometry and burst pressure. The technology is demonstrated in a device employing multiple valves engineered to actuate at different inlet pressures that can be generated using integrated screw pumps. On-chip storage and reconstitution of fluorescein salt sealed within defined reagent chambers are demonstrated. By taking advantage of the low gas and water permeability of cyclic olefin copolymer, the robust burst valves allow on-chip hermetic storage of reagents, making the technology well suited for the development of integrated and disposable assays for use at the point of care. PMID:25972774

Comparison between genotyping by sequencing and SNP-chip genotyping in QTL mapping in wheat

USDA-ARS?s Scientific Manuscript database

Array- or chip-based single nucleotide polymorphism (SNP) markers are widely used in genomic studies because of their abundance in a genome and cost less per data point compared to older marker technologies. Genotyping by sequencing (GBS), a relatively newer approach of genotyping, suggests equal or...

Compression debarking of wood chips.

Treesearch

Rodger A. Arola; John R. Erickson

1973-01-01

Presents results from 2 years testing of a single-pass compression process for debarking wood chips of several species. The most significant variable was season of cut. Depending on species, approximately 70% of the bark was removed from wood cut in the growing season while approximately 45% was removed from wood cut in the dormant season.

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Laser-induced forward transfer for flip-chip packaging of single dies.

PubMed

Kaur, Kamal S; Van Steenberge, Geert

2015-03-20

Flip-chip (FC) packaging is a key technology for realizing high performance, ultra-miniaturized and high-density circuits in the micro-electronics industry. In this technique the chip and/or the substrate is bumped and the two are bonded via these conductive bumps. Many bumping techniques have been developed and intensively investigated since the introduction of the FC technology in 1960(1) such as stencil printing, stud bumping, evaporation and electroless/electroplating2. Despite the progress that these methods have made they all suffer from one or more than one drawbacks that need to be addressed such as cost, complex processing steps, high processing temperatures, manufacturing time and most importantly the lack of flexibility. In this paper, we demonstrate a simple and cost-effective laser-based bump forming technique known as Laser-induced Forward Transfer (LIFT)3. Using the LIFT technique a wide range of bump materials can be printed in a single-step with great flexibility, high speed and accuracy at RT. In addition, LIFT enables the bumping and bonding down to chip-scale, which is critical for fabricating ultra-miniature circuitry.

Generation and transfer of single photons on a photonic crystal chip.

PubMed

Englund, Dirk; Faraon, Andrei; Zhang, Bingyang; Yamamoto, Yoshihisa; Vucković, Jelena

2007-04-30

We present a basic building block of a quantum network consisting of a quantum dot coupled to a source cavity, which in turn is coupled to a target cavity via a waveguide. The single photon emission from the high-Q/V source cavity is characterized by twelve-fold spontaneous emission (SE) rate enhancement, SE coupling efficiency beta ~ 0.98 into the source cavity mode, and mean wavepacket indistinguishability of ~67%. Single photons are efficiently transferred into the target cavity via the waveguide, with a target/source field intensity ratio of 0.12 +/- 0.01. This system shows great promise as a building block of future on-chip quantum information processing systems.

A high-speed on-chip pseudo-random binary sequence generator for multi-tone phase calibration

NASA Astrophysics Data System (ADS)

Gommé, Liesbeth; Vandersteen, Gerd; Rolain, Yves

2011-07-01

An on-chip reference generator is conceived by adopting the technique of decimating a pseudo-random binary sequence (PRBS) signal in parallel sequences. This is of great benefit when high-speed generation of PRBS and PRBS-derived signals is the objective. The design implemented standard CMOS logic is available in commercial libraries to provide the logic functions for the generator. The design allows the user to select the periodicity of the PRBS and the PRBS-derived signals. The characterization of the on-chip generator marks its performance and reveals promising specifications.

Gold-coated polydimethylsiloxane microwells for high-throughput electrochemiluminescence analysis of intracellular glucose at single cells.

PubMed

Xia, Juan; Zhou, Junyu; Zhang, Ronggui; Jiang, Dechen; Jiang, Depeng

2018-06-04

In this communication, a gold-coated polydimethylsiloxane (PDMS) chip with cell-sized microwells was prepared through a stamping and spraying process that was applied directly for high-throughput electrochemiluminescence (ECL) analysis of intracellular glucose at single cells. As compared with the previous multiple-step fabrication of photoresist-based microwells on the electrode, the preparation process is simple and offers fresh electrode surface for higher luminescence intensity. More luminescence intensity was recorded from cell-retained microwells than that at the planar region among the microwells that was correlated with the content of intracellular glucose. The successful monitoring of intracellular glucose at single cells using this PDMS chip will provide an alternative strategy for high-throughput single-cell analysis. Graphical abstract ᅟ.

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

NASA Astrophysics Data System (ADS)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

Parallel confocal detection of single biomolecules using diffractive optics and integrated detector units.

PubMed

Blom, H; Gösch, M

2004-04-01

The past few years we have witnessed a tremendous surge of interest in so-called array-based miniaturised analytical systems due to their value as extremely powerful tools for high-throughput sequence analysis, drug discovery and development, and diagnostic tests in medicine (see articles in Issue 1). Terminologies that have been used to describe these array-based bioscience systems include (but are not limited to): DNA-chip, microarrays, microchip, biochip, DNA-microarrays and genome chip. Potential technological benefits of introducing these miniaturised analytical systems include improved accuracy, multiplexing, lower sample and reagent consumption, disposability, and decreased analysis times, just to mention a few examples. Among the many alternative principles of detection-analysis (e.g.chemiluminescence, electroluminescence and conductivity), fluorescence-based techniques are widely used, examples being fluorescence resonance energy transfer, fluorescence quenching, fluorescence polarisation, time-resolved fluorescence, and fluorescence fluctuation spectroscopy (see articles in Issue 11). Time-dependent fluctuations of fluorescent biomolecules with different molecular properties, like molecular weight, translational and rotational diffusion time, colour and lifetime, potentially provide all the kinetic and thermodynamic information required in analysing complex interactions. In this mini-review article, we present recent extensions aimed to implement parallel laser excitation and parallel fluorescence detection that can lead to even further increase in throughput in miniaturised array-based analytical systems. We also report on developments and characterisations of multiplexing extension that allow multifocal laser excitation together with matched parallel fluorescence detection for parallel confocal dynamical fluorescence fluctuation studies at the single biomolecule level.

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

PubMed Central

Ballini, Marco; Müller, Jan; Livi, Paolo; Chen, Yihui; Frey, Urs; Stettler, Alexander; Shadmani, Amir; Viswam, Vijay; Jones, Ian Lloyd; Jäckel, David; Radivojevic, Milos; Lewandowska, Marta K.; Gong, Wei; Fiscella, Michele; Bakkum, Douglas J.; Heer, Flavio; Hierlemann, Andreas

2017-01-01

To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm2) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μVrms in the action-potential band (300 Hz–10 kHz) and 5.4 μVrms in the local-field-potential band (1 Hz–300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures. PMID:28502989

Novel Highly Parallel and Systolic Architectures Using Quantum Dot-Based Hardware

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Benny N.; Spotnitz, Matthew

1997-01-01

VLSI technology has made possible the integration of massive number of components (processors, memory, etc.) into a single chip. In VLSI design, memory and processing power are relatively cheap and the main emphasis of the design is on reducing the overall interconnection complexity since data routing costs dominate the power, time, and area required to implement a computation. Communication is costly because wires occupy the most space on a circuit and it can also degrade clock time. In fact, much of the complexity (and hence the cost) of VLSI design results from minimization of data routing. The main difficulty in VLSI routing is due to the fact that crossing of the lines carrying data, instruction, control, etc. is not possible in a plane. Thus, in order to meet this constraint, the VLSI design aims at keeping the architecture highly regular with local and short interconnection. As a result, while the high level of integration has opened the way for massively parallel computation, practical and full exploitation of such a capability in many applications of interest has been hindered by the constraints on interconnection pattern. More precisely. the use of only localized communication significantly simplifies the design of interconnection architecture but at the expense of somewhat restricted class of applications. For example, there are currently commercially available products integrating; hundreds of simple processor elements within a single chip. However, the lack of adequate interconnection pattern among these processing elements make them inefficient for exploiting a large degree of parallelism in many applications.

VCSEL technology for medical diagnostics and therapeutics

NASA Astrophysics Data System (ADS)

Hibbs-Brenner, M. K.; Johnson, K. L.; Bendett, M.

2009-02-01

In the 1990's a new laser technology, Vertical Cavity Surface Emitting Lasers, or VCSELs, emerged and transformed the data communication industry. The combination of performance characteristics, reliability and performance/cost ratio allowed high data rate communication to occur over short distances at a commercially viable price. VCSELs have not been widely used outside of this application space, but with the development of new attributes, such as a wider range of available wavelengths, the demonstration of arrays of VCSELs on a single chip, and a variety of package form factors, VCSELs can have a significant impact on medical diagnostic and therapeutic applications. One area of potential application is neurostimulation. Researchers have previously demonstrated the feasibility of using 1850nm light for nerve stimulation. The ability to create an array of VCSELs emitting at this wavelength would allow significantly improved spatial resolution, and multiple parallel channels of stimulation. For instance, 2D arrays of 100 lasers or more can be integrated on a single chip less than 2mm on a side. A second area of interest is non-invasive sensing. Performance attributes such as the narrow spectral width, low power consumption, and packaging flexibility open up new possibilities in non-invasive and/or continuous sensing. This paper will suggest ways in which VCSELs can be implemented within these application areas, and the advantages provided by the unique performance characteristics of the VCSEL. The status of VCSEL technology as a function of available wavelength and array size and form factors will be summarized.

A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maj, Piotr; Grybos, P.; Szczgiel, R.

2013-11-07

We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e ₋rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largestmore » charge deposition. The chip architecture and preliminary measurements are reported.« less

Design and validation of a real-time spiking-neural-network decoder for brain-machine interfaces

NASA Astrophysics Data System (ADS)

Dethier, Julie; Nuyujukian, Paul; Ryu, Stephen I.; Shenoy, Krishna V.; Boahen, Kwabena

2013-06-01

Objective. Cortically-controlled motor prostheses aim to restore functions lost to neurological disease and injury. Several proof of concept demonstrations have shown encouraging results, but barriers to clinical translation still remain. In particular, intracortical prostheses must satisfy stringent power dissipation constraints so as not to damage cortex. Approach. One possible solution is to use ultra-low power neuromorphic chips to decode neural signals for these intracortical implants. The first step is to explore in simulation the feasibility of translating decoding algorithms for brain-machine interface (BMI) applications into spiking neural networks (SNNs). Main results. Here we demonstrate the validity of the approach by implementing an existing Kalman-filter-based decoder in a simulated SNN using the Neural Engineering Framework (NEF), a general method for mapping control algorithms onto SNNs. To measure this system’s robustness and generalization, we tested it online in closed-loop BMI experiments with two rhesus monkeys. Across both monkeys, a Kalman filter implemented using a 2000-neuron SNN has comparable performance to that of a Kalman filter implemented using standard floating point techniques. Significance. These results demonstrate the tractability of SNN implementations of statistical signal processing algorithms on different monkeys and for several tasks, suggesting that a SNN decoder, implemented on a neuromorphic chip, may be a feasible computational platform for low-power fully-implanted prostheses. The validation of this closed-loop decoder system and the demonstration of its robustness and generalization hold promise for SNN implementations on an ultra-low power neuromorphic chip using the NEF.

The development and validation of EpiComet-Chip, a modified high-throughput comet assay for the assessment of DNA methylation status.

PubMed

Townsend, Todd A; Parrish, Marcus C; Engelward, Bevin P; Manjanatha, Mugimane G

2017-08-01

DNA damage and alterations in global DNA methylation status are associated with multiple human diseases and are frequently correlated with clinically relevant information. Therefore, assessing DNA damage and epigenetic modifications, including DNA methylation, is critical for predicting human exposure risk of pharmacological and biological agents. We previously developed a higher-throughput platform for the single cell gel electrophoresis (comet) assay, CometChip, to assess DNA damage and genotoxic potential. Here, we utilized the methylation-dependent endonuclease, McrBC, to develop a modified alkaline comet assay, "EpiComet," which allows single platform evaluation of genotoxicity and global DNA methylation [5-methylcytosine (5-mC)] status of single-cell populations under user-defined conditions. Further, we leveraged the CometChip platform to create an EpiComet-Chip system capable of performing quantification across simultaneous exposure protocols to enable unprecedented speed and simplicity. This system detected global methylation alterations in response to exposures which included chemotherapeutic and environmental agents. Using EpiComet-Chip on 63 matched samples, we correctly identified single-sample hypermethylation (≥1.5-fold) at 87% (20/23), hypomethylation (≥1.25-fold) at 100% (9/9), with a 4% (2/54) false-negative rate (FNR), and 10% (4/40) false-positive rate (FPR). Using a more stringent threshold to define hypermethylation (≥1.75-fold) allowed us to correctly identify 94% of hypermethylation (17/18), but increased our FPR to 16% (7/45). The successful application of this novel technology will aid hazard identification and risk characterization of FDA-regulated products, while providing utility for investigating epigenetic modes of action of agents in target organs, as the assay is amenable to cultured cells or nucleated cells from any tissue. Environ. Mol. Mutagen. 58:508-521, 2017. © 2017 Wiley Periodicals, Inc. © 2017 Wiley Periodicals, Inc.

Room temperature 1040fps, 1 megapixel photon-counting image sensor with 1.1um pixel pitch

NASA Astrophysics Data System (ADS)

Masoodian, S.; Ma, J.; Starkey, D.; Wang, T. J.; Yamashita, Y.; Fossum, E. R.

2017-05-01

A 1Mjot single-bit quanta image sensor (QIS) implemented in a stacked backside-illuminated (BSI) process is presented. This is the first work to report a megapixel photon-counting CMOS-type image sensor to the best of our knowledge. A QIS with 1.1μm pitch tapered-pump-gate jots is implemented with cluster-parallel readout, where each cluster of jots is associated with its own dedicated readout electronics stacked under the cluster. Power dissipation is reduced with this cluster readout because of the reduced column bus parasitic capacitance, which is important for the development of 1Gjot arrays. The QIS functions at 1040fps with binary readout and dissipates only 17.6mW, including I/O pads. The readout signal chain uses a fully differential charge-transfer amplifier (CTA) gain stage before a 1b-ADC to achieve an energy/bit FOM of 16.1pJ/b and 6.9pJ/b for the whole sensor and gain stage+ADC, respectively. Analog outputs with on-chip gain are implemented for pixel characterization purposes.

Stress analysis of ultra-thin silicon chip-on-foil electronic assembly under bending

NASA Astrophysics Data System (ADS)

Wacker, Nicoleta; Richter, Harald; Hoang, Tu; Gazdzicki, Pawel; Schulze, Mathias; Angelopoulos, Evangelos A.; Hassan, Mahadi-Ul; Burghartz, Joachim N.

2014-09-01

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness \\leqslant 20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the built-in devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chip's edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.