Mitigating Upsets in SRAM Based FPGAs from the Xilinix Virtex 2 Family

NASA Technical Reports Server (NTRS)

Swift, Gary M.; Yui, Candice C.; Carmichael, Carl; Koga, Rocky; George, Jeffrey S.

2003-01-01

This slide presentation reviews the single event upset static testing of the Virtex II field programmable gate arrays (FPGA) that were tested in protons and heavy-ions. The test designs and static and dynamic test results are reviewed.

Single Event Testing on Complex Devices: Test Like You Fly versus Test-Specific Design Structures

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth A.

2014-01-01

We present a framework for evaluating complex digital systems targeted for harsh radiation environments such as space. Focus is limited to analyzing the single event upset (SEU) susceptibility of designs implemented inside Field Programmable Gate Array (FPGA) devices. Tradeoffs are provided between application-specific versus test-specific test structures.

Evolutionary Based Techniques for Fault Tolerant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Larchev, Gregory V.; Lohn, Jason D.

2006-01-01

The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.

Wire like link for cycle reproducible and cycle accurate hardware accelerator

DOEpatents

Asaad, Sameh; Kapur, Mohit; Parker, Benjamin D

2015-04-07

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth; Campola, Michael; Xapsos, Michael

2017-01-01

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

InGaAs/InP SPAD photon-counting module with auto-calibrated gate-width generation and remote control

NASA Astrophysics Data System (ADS)

Tosi, Alberto; Ruggeri, Alessandro; Bahgat Shehata, Andrea; Della Frera, Adriano; Scarcella, Carmelo; Tisa, Simone; Giudice, Andrea

2013-01-01

We present a photon-counting module based on InGaAs/InP SPAD (Single-Photon Avalanche Diode) for detecting single photons up to 1.7 μm. The module exploits a novel architecture for generating and calibrating the gate width, along with other functions (such as module supervision, counting and processing of detected photons, etc.). The gate width, i.e. the time interval when the SPAD is ON, is user-programmable in the range from 500 ps to 1.5 μs, by means of two different delay generation methods implemented with an FPGA (Field-Programmable Gate Array). In order to compensate chip-to-chip delay variation, an auto-calibration circuit picks out a combination of delays in order to match at best the selected gate width. The InGaAs/InP module accepts asynchronous and aperiodic signals and introduces very low timing jitter. Moreover the photon counting module provides other new features like a microprocessor for system supervision, a touch-screen for local user interface, and an Ethernet link for smart remote control. Thanks to the fullyprogrammable and configurable architecture, the overall instrument provides high system flexibility and can easily match all requirements set by many different applications requiring single photon-level sensitivity in the near infrared with very low photon timing jitter.

FPGA-based gating and logic for multichannel single photon counting

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G

2012-01-01

We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidencemore » measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)« less

Rad-Hard/HI-REL FPGA

NASA Technical Reports Server (NTRS)

Wang, Jih-Jong; Cronquist, Brian E.; McGowan, John E.; Katz, Richard B.

1997-01-01

The goals for a radiation hardened (RAD-HARD) and high reliability (HI-REL) field programmable gate array (FPGA) are described. The first qualified manufacturer list (QML) radiation hardened RH1280 and RH1020 were developed. The total radiation dose and single event effects observed on the antifuse FPGA RH1280 are reported on. Tradeoffs and the limitations in the single event upset hardening are discussed.

Spacecube V2.0 Micro Single Board Computer

NASA Technical Reports Server (NTRS)

Petrick, David J. (Inventor); Geist, Alessandro (Inventor); Lin, Michael R. (Inventor); Crum, Gary R. (Inventor)

2017-01-01

A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm.times.7 cm.

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

DNA and RNA sequencing by nanoscale reading through programmable electrophoresis and nanoelectrode-gated tunneling and dielectric detection

DOEpatents

Lee, James W.; Thundat, Thomas G.

2005-06-14

An apparatus and method for performing nucleic acid (DNA and/or RNA) sequencing on a single molecule. The genetic sequence information is obtained by probing through a DNA or RNA molecule base by base at nanometer scale as though looking through a strip of movie film. This DNA sequencing nanotechnology has the theoretical capability of performing DNA sequencing at a maximal rate of about 1,000,000 bases per second. This enhanced performance is made possible by a series of innovations including: novel applications of a fine-tuned nanometer gap for passage of a single DNA or RNA molecule; thin layer microfluidics for sample loading and delivery; and programmable electric fields for precise control of DNA or RNA movement. Detection methods include nanoelectrode-gated tunneling current measurements, dielectric molecular characterization, and atomic force microscopy/electrostatic force microscopy (AFM/EFM) probing for nanoscale reading of the nucleic acid sequences.

Single Event Effects (SEE) Testing of Embedded DSP Cores within Microsemi RTAX4000D Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Perez, Christopher E.; Berg, Melanie D.; Friendlich, Mark R.

2011-01-01

Motivation for this work is: (1) Accurately characterize digital signal processor (DSP) core single-event effect (SEE) behavior (2) Test DSP cores across a large frequency range and across various input conditions (3) Isolate SEE analysis to DSP cores alone (4) Interpret SEE analysis in terms of single-event upsets (SEUs) and single-event transients (SETs) (5) Provide flight missions with accurate estimate of DSP core error rates and error signatures.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

[Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

PubMed

Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

2015-12-01

Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

An Analysis of Heavy-Ion Single Event Effects for a Variety of Finite State-Machine Mitigation Strategies

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; Label, Kenneth A.; Kim, Hak; Phan, Anthony; Seidleck, Christina

2014-01-01

Finite state-machines (FSMs) are used to control operational flow in application specific integrated circuits (ASICs) and field programmable gate array (FPGA) devices. Because of their ease of interpretation, FSMs simplify the design and verification process and consequently are significant components in a synchronous design.

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

A simple laser locking system based on a field-programmable gate array.

PubMed

Jørgensen, N B; Birkmose, D; Trelborg, K; Wacker, L; Winter, N; Hilliard, A J; Bason, M G; Arlt, J J

2016-07-01

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The locking system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.

A simple laser locking system based on a field-programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jørgensen, N. B.; Birkmose, D.; Trelborg, K.

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The lockingmore » system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.« less

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

NASA Astrophysics Data System (ADS)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

PubMed Central

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

ERIC Educational Resources Information Center

Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

2010-01-01

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

Semantically Aware Foundation Environment (SAFE) for Clean-Slate Design of Resilient, Adaptive Secure Hosts (CRASH)

DTIC Science & Technology

2016-02-01

system consists of a high-fidelity hardware simulation using field programmable gate arrays (FPGAs), with a set of runtime services (ConcreteWare...perimeter protection, patch, and pray” is not aligned with the threat. Programmers will not bail us out of this situation (by writing defect free code...hosted on a Field Programmable Gate Array (FPGA), with a set of runtime services (concreteware) running on the hardware. Secure applications can be

Field-Free Programmable Spin Logics via Chirality-Reversible Spin-Orbit Torque Switching.

PubMed

Wang, Xiao; Wan, Caihua; Kong, Wenjie; Zhang, Xuan; Xing, Yaowen; Fang, Chi; Tao, Bingshan; Yang, Wenlong; Huang, Li; Wu, Hao; Irfan, Muhammad; Han, Xiufeng

2018-06-21

Spin-orbit torque (SOT)-induced magnetization switching exhibits chirality (clockwise or counterclockwise), which offers the prospect of programmable spin-logic devices integrating nonvolatile spintronic memory cells with logic functions. Chirality is usually fixed by an applied or effective magnetic field in reported studies. Herein, utilizing an in-plane magnetic layer that is also switchable by SOT, the chirality of a perpendicular magnetic layer that is exchange-coupled with the in-plane layer can be reversed in a purely electrical way. In a single Hall bar device designed from this multilayer structure, three logic gates including AND, NAND, and NOT are reconfigured, which opens a gateway toward practical programmable spin-logic devices. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Berg, M.; Kim, H.; Phan, A.; Seidleck, C.; LaBel, K.; Pellish, J.; Campola, M.

2015-01-01

Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Convolutional Neural Network on Embedded Linux(trademark) System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Convolutional Neural Network on Embedded Linux System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Field Programmable Gate Aray (FPGA) Radiation Data: All Data is Not Equal

NASA Technical Reports Server (NTRS)

Label, Kenneth A.; Berg, Melanie D.

2016-01-01

Electronic parts (integrated circuits) have grown in complexity such that determining all failure modes and risks based on single particle event radiation testing is impossible. In this presentation, the authors will present why this is so and provide some realism on what this means to FPGAs. Its all about understanding actual risks and not making assumptions.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Citterio, M.; Camplani, A.; Cannon, M.

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

DTIC Science & Technology

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

Radiation Effects on Current Field Programmable Technologies

NASA Technical Reports Server (NTRS)

Katz, R.; LaBel, K.; Wang, J. J.; Cronquist, B.; Koga, R.; Penzin, S.; Swift, G.

1997-01-01

Manufacturers of field programmable gate arrays (FPGAS) take different technological and architectural approaches that directly affect radiation performance. Similar y technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

NASA Astrophysics Data System (ADS)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

NASA Astrophysics Data System (ADS)

Hamada, Tsuyoshi; Fukushige, Toshiyuki; Kawai, Atsushi; Makino, Junichiro

2000-10-01

We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and ``traditional'' GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydro\\-dynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

A modularized pulse programmer for NMR spectroscopy

NASA Astrophysics Data System (ADS)

Mao, Wenping; Bao, Qingjia; Yang, Liang; Chen, Yiqun; Liu, Chaoyang; Qiu, Jianqing; Ye, Chaohui

2011-02-01

A modularized pulse programmer for a NMR spectrometer is described. It consists of a networked PCI-104 single-board computer and a field programmable gate array (FPGA). The PCI-104 is dedicated to translate the pulse sequence elements from the host computer into 48-bit binary words and download these words to the FPGA, while the FPGA functions as a sequencer to execute these binary words. High-resolution NMR spectra obtained on a home-built spectrometer with four pulse programmers working concurrently demonstrate the effectiveness of the pulse programmer. Advantages of the module include (1) once designed it can be duplicated and used to construct a scalable NMR/MRI system with multiple transmitter and receiver channels, (2) it is a totally programmable system in which all specific applications are determined by software, and (3) it provides enough reserve for possible new pulse sequences.

Compact universal logic gates realized using quantization of current in nanodevices.

PubMed

Zhang, Wancheng; Wu, Nan-Jian; Yang, Fuhua

2007-12-12

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device.

PubMed

Picone, Rico A R; Davis, Solomon; Devine, Cameron; Garbini, Joseph L; Sidles, John A

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

NASA Astrophysics Data System (ADS)

Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

DOE PAGES

Citterio, M.; Camplani, A.; Cannon, M.; ...

2015-11-19

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

NASA Technical Reports Server (NTRS)

Straka, Bartholomew

2013-01-01

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

Apertureless near-field/far-field CW two-photon microscope for biological and material imaging and spectroscopic applications.

PubMed

Nowak, Derek B; Lawrence, A J; Sánchez, Erik J

2010-12-10

We present the development of a versatile spectroscopic imaging tool to allow for imaging with single-molecule sensitivity and high spatial resolution. The microscope allows for near-field and subdiffraction-limited far-field imaging by integrating a shear-force microscope on top of a custom inverted microscope design. The instrument has the ability to image in ambient conditions with optical resolutions on the order of tens of nanometers in the near field. A single low-cost computer controls the microscope with a field programmable gate array data acquisition card. High spatial resolution imaging is achieved with an inexpensive CW multiphoton excitation source, using an apertureless probe and simplified optical pathways. The high-resolution, combined with high collection efficiency and single-molecule sensitive optical capabilities of the microscope, are demonstrated with a low-cost CW laser source as well as a mode-locked laser source.

Synchronized operation by field programmable gate array based signal controller for the Thomson scattering diagnostic system in KSTAR.

PubMed

Lee, W R; Kim, H S; Park, M K; Lee, J H; Kim, K H

2012-09-01

The Thomson scattering diagnostic system is successfully installed in the Korea Superconducting Tokamak Advanced Research (KSTAR) facility. We got the electron temperature and electron density data for the first time in 2011, 4th campaign using a field programmable gate array (FPGA) based signal control board. It operates as a signal generator, a detector, a controller, and a time measuring device. This board produces two configurable trigger pulses to operate Nd:YAG laser system and receives a laser beam detection signal from a photodiode detector. It allows a trigger pulse to be delivered to a time delay module to make a scattered signal measurement, measuring an asynchronous time value between the KSTAR timing board and the laser system injection signal. All functions are controlled by the embedded processor running on operating system within a single FPGA. It provides Ethernet communication interface and is configured with standard middleware to integrate with KSTAR. This controller has operated for two experimental campaigns including commissioning and performed the reconfiguration of logic designs to accommodate varying experimental situation without hardware rebuilding.

Field programmable gate array based fuzzy neural signal processing system for differential diagnosis of QRS complex tachycardia and tachyarrhythmia in noisy ECG signals.

PubMed

Chowdhury, Shubhajit Roy

2012-04-01

The paper reports of a Field Programmable Gate Array (FPGA) based embedded system for detection of QRS complex in a noisy electrocardiogram (ECG) signal and thereafter differential diagnosis of tachycardia and tachyarrhythmia. The QRS complex has been detected after application of entropy measure of fuzziness to build a detection function of ECG signal, which has been previously filtered to remove power line interference and base line wander. Using the detected QRS complexes, differential diagnosis of tachycardia and tachyarrhythmia has been performed. The entire algorithm has been realized in hardware on an FPGA. Using the standard CSE ECG database, the algorithm performed highly effectively. The performance of the algorithm in respect of QRS detection with sensitivity (Se) of 99.74% and accuracy of 99.5% is achieved when tested using single channel ECG with entropy criteria. The performance of the QRS detection system has been compared and found to be better than most of the QRS detection systems available in literature. Using the system, 200 patients have been diagnosed with an accuracy of 98.5%.

High-performance computing for airborne applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Manuzzato, Andrea; Fairbanks, Tom

2010-06-28

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even thoughmore » the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.« less

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application

NASA Technical Reports Server (NTRS)

Sheldon, Douglas; Schone, Harald

2005-01-01

This viewgraph document reviews the issue of using Field Programmable Gate Arrays (FPGAs) in Space Application, and the some of the strategies for qualifying the FPGA. Qualification and risk management of such complex systems requires new approaches. The paper presents a matrix approach to qualification has been presented that: - Complements historical specifications - Highlights the importance of device physics as a cornerstone to qualification. - Provides levels of risk management that expressly document trade offs. - Stresses the role of the FPGA vendor as team member in the development of modern spacecraft.

Programmable diagnostic devices made from paper and tape.

PubMed

Martinez, Andres W; Phillips, Scott T; Nie, Zhihong; Cheng, Chao-Min; Carrilho, Emanuel; Wiley, Benjamin J; Whitesides, George M

2010-10-07

This paper describes three-dimensional microfluidic paper-based analytical devices (3-D microPADs) that can be programmed (postfabrication) by the user to generate multiple patterns of flow through them. These devices are programmed by pressing single-use 'on' buttons, using a stylus or a ballpoint pen. Pressing a button closes a small space (gap) between two vertically aligned microfluidic channels, and allows fluids to wick from one channel to the other. These devices are simple to fabricate, and are made entirely out of paper and double-sided adhesive tape. Programmable devices expand the capabilities of microPADs and provide a simple method for controlling the movement of fluids in paper-based channels. They are the conceptual equivalent of field-programmable gate arrays (FPGAs) widely used in electronics.

Universal Quantum Computing with Measurement-Induced Continuous-Variable Gate Sequence in a Loop-Based Architecture.

PubMed

Takeda, Shuntaro; Furusawa, Akira

2017-09-22

We propose a scalable scheme for optical quantum computing using measurement-induced continuous-variable quantum gates in a loop-based architecture. Here, time-bin-encoded quantum information in a single spatial mode is deterministically processed in a nested loop by an electrically programmable gate sequence. This architecture can process any input state and an arbitrary number of modes with almost minimum resources, and offers a universal gate set for both qubits and continuous variables. Furthermore, quantum computing can be performed fault tolerantly by a known scheme for encoding a qubit in an infinite-dimensional Hilbert space of a single light mode.

Universal Quantum Computing with Measurement-Induced Continuous-Variable Gate Sequence in a Loop-Based Architecture

NASA Astrophysics Data System (ADS)

Takeda, Shuntaro; Furusawa, Akira

2017-09-01

We propose a scalable scheme for optical quantum computing using measurement-induced continuous-variable quantum gates in a loop-based architecture. Here, time-bin-encoded quantum information in a single spatial mode is deterministically processed in a nested loop by an electrically programmable gate sequence. This architecture can process any input state and an arbitrary number of modes with almost minimum resources, and offers a universal gate set for both qubits and continuous variables. Furthermore, quantum computing can be performed fault tolerantly by a known scheme for encoding a qubit in an infinite-dimensional Hilbert space of a single light mode.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

PubMed

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Liang, Futian; Jin, Ge

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Kun; Wang, Xu; Li, Feng

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Field programmable gate array-assigned complex-valued computation and its limits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com; Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien; Zwick, Wolfgang

We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

A control system based on field programmable gate array for papermaking sewage treatment

NASA Astrophysics Data System (ADS)

Zhang, Zi Sheng; Xie, Chang; Qing Xiong, Yan; Liu, Zhi Qiang; Li, Qing

2013-03-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

Focusing light through dynamical samples using fast continuous wavefront optimization.

PubMed

Blochet, B; Bourdieu, L; Gigan, S

2017-12-01

We describe a fast continuous optimization wavefront shaping system able to focus light through dynamic scattering media. A micro-electro-mechanical system-based spatial light modulator, a fast photodetector, and field programmable gate array electronics are combined to implement a continuous optimization of a wavefront with a single-mode optimization rate of 4.1 kHz. The system performances are demonstrated by focusing light through colloidal solutions of TiO 2 particles in glycerol with tunable temporal stability.

Virtex-5QV Self Scrubber

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojahn, Christopher K.

2015-10-20

This HDL code (hereafter referred to as "software") implements circuitry in Xilinx Virtex-5QV Field Programmable Gate Array (FPGA) hardware. This software allows the device to self-check the consistency of its own configuration memory for radiation-induced errors. The software then provides the capability to correct any single-bit errors detected in the memory using the device's inherent circuitry, or reload corrupted memory frames when larger errors occur that cannot be corrected with the device's built-in error correction and detection scheme.

Memory Device and Nanofabrication Techniques Using Electrically Configurable Materials

NASA Astrophysics Data System (ADS)

Ascenso Simões, Bruno

Development of novel nanofabrication techniques and single-walled carbon nanotubes field configurable transistor (SWCNT-FCT) memory devices using electrically configurable materials is presented. A novel lithographic technique, electric lithography (EL), that uses electric field for pattern generation has been demonstrated. It can be used for patterning of biomolecules on a polymer surface and patterning of resist as well. Using electrical resist composed of a polymer having Boc protected amine group and iodonium salt, Boc group on the surface of polymer was modified to free amine by applying an electric field. On the modified surface of the polymer, Streptavidin pattern was fabricated with a sub-micron scale. Also patterning of polymer resin composed of epoxy monomers and diaryl iodonium salt by EL has been demonstrated. Reaction mechanism for electric resist configuration is believed to be induced by an acid generation via electrochemical reduction in the resist. We show a novel field configurable transistor (FCT) based on single-walled carbon nanotube network field-effect transistors in which poly (ethylene glycol) crosslinked by electron-beam is incorporated into the gate. The device conductance can be configured to arbitrary states reversibly and repeatedly by applying external gate voltages. Raman spectroscopy revealed that evolution of the ratio of D- to G-band intensity in the SWCNTs of the FCT progressively increases as the device is configured to lower conductance states. Electron transport studies at low temperatures showed a strong temperature dependence of the resistance. Band gap widening of CNTs up to ˜ 4 eV has been observed by examining the differential conductance-gate voltage-bias voltage relationship. The switching mechanism of the FCT is attributed a structural transformation of CNTs via reversible hydrogenation and dehydrogenations induced by gate voltages, which tunes the CNT bandgap continuously and reversibly to non-volatile analog values. The CNT transistors with field tunable band gaps would facilitate field programmable circuits based on the self-organized CNTs, and might also lead to novel analog memory, neuromorphic, and photonic devices.

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

ERIC Educational Resources Information Center

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

Start Up Application Concerns with Field Programmable Gate Arrays (FPGAs)

NASA Technical Reports Server (NTRS)

Katz, Richard B.

1999-01-01

This note is being published to improve the visibility of this subject, as we continue to see problems surface in designs, as well as to add additional information to the previously published note for design engineers. The original application note focused on designing systems with no single point failures using Actel Field Programmable Gate Arrays (FPGAs) for critical applications. Included in that note were the basic principles of operation of the Actel FPGA and a discussion of potential single-point failures. The note also discussed the issue of startup transients for that class of device. It is unfortunate that we continue to see some design problems using these devices. This note will focus on the startup properties of certain electronic components, in general, and current Actel FPGAs, in particular. Devices that are "power-on friendly" are currently being developed by Actel, as a variant of the new SX series of FPGAs. In the ideal world, electronic components would behave much differently than they do in the real world, The chain, of course, starts with the power supply. Ideally, the voltage will immediately rise to a stable V(sub cc) level, of course, it does not. Aside from practical design considerations, inrush current limits of certain capacitors must be observed and the power supply's output may be intentionally slew rate limited to prevent a large current spike on the system power bus. In any event, power supply rise time may range from less than I msec to 100 msec or more.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms.

PubMed

Pruttivarasin, Thaned; Katori, Hidetoshi

2015-11-01

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp; Katori, Hidetoshi; Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Field programmable gate array processing of eye-safe all-fiber coherent wind Doppler lidar return signals

NASA Astrophysics Data System (ADS)

Abdelazim, S.; Santoro, D.; Arend, M.; Moshary, F.; Ahmed, S.

2011-11-01

A field deployable all-fiber eye-safe Coherent Doppler LIDAR is being developed at the Optical Remote Sensing Lab at the City College of New York (CCNY) and is designed to monitor wind fields autonomously and continuously in urban settings. Data acquisition is accomplished by sampling lidar return signals at 400 MHz and performing onboard processing using field programmable gate arrays (FPGAs). The FPGA is programmed to accumulate signal information that is used to calculate the power spectrum of the atmospherically back scattered signal. The advantage of using FPGA is that signal processing will be performed at the hardware level, reducing the load on the host computer and allowing for 100% return signal processing. An experimental setup measured wind speeds at ranges of up to 3 km.

Self-aligned gated field emission devices using single carbon nanofiber cathodes

NASA Astrophysics Data System (ADS)

Guillorn, M. A.; Melechko, A. V.; Merkulov, V. I.; Hensley, D. K.; Simpson, M. L.; Lowndes, D. H.

2002-11-01

We report on the fabrication and operation of integrated gated field emission devices using single vertically aligned carbon nanofiber (VACNF) cathodes where the gate aperture has been formed using a self-aligned technique based on chemical mechanical polishing. We find that this method for producing gated cathode devices easily achieves structures with gate apertures on the order of 2 mum that show good concentric alignment to the VACNF emitter. The operation of these devices was explored and field emission characteristics that fit well to the Fowler-Nordheim model of emission was demonstrated.

High-performance reconfigurable coincidence counting unit based on a field programmable gate array.

PubMed

Park, Byung Kwon; Kim, Yong-Su; Kwon, Osung; Han, Sang-Wook; Moon, Sung

2015-05-20

We present a high-performance reconfigurable coincidence counting unit (CCU) using a low-end field programmable gate array (FPGA) and peripheral circuits. Because of the flexibility guaranteed by the FPGA program, we can easily change system parameters, such as internal input delays, coincidence configurations, and the coincidence time window. In spite of a low-cost implementation, the proposed CCU architecture outperforms previous ones in many aspects: it has 8 logic inputs and 4 coincidence outputs that can measure up to eight-fold coincidences. The minimum coincidence time window and the maximum input frequency are 0.47 ns and 163 MHz, respectively. The CCU will be useful in various experimental research areas, including the field of quantum optics and quantum information.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

DTIC Science & Technology

2011-12-01

Bit 1 ,Bit 0P  . (V.3) Equation (V.3) is implemented with a string of XOR gates and Bit Basher blocks, as shown in Figure 31. As discussed in...5], the string of Bit Basher blocks are used to separate each 35-bit value into 35 one-bit values, and the string of XOR gates is used to

Clock and carrier recovery in high-speed coherent optical communication systems

NASA Astrophysics Data System (ADS)

Amado, Sofia B.; Ferreira, Ricardo; Costa, Pedro S.; Guiomar, Fernando P.; Ziaie, Somayeh; Teixeira, António L.; Muga, Nelson J.; Pinto, Armando N.

2014-08-01

In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 Field-Programmable Gate Array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).

Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

NASA Technical Reports Server (NTRS)

Swift, G. M.; Yui, C. C.; Carmichael, C.; Koga, R.; George, J. S.

2003-01-01

Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

PubMed Central

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Programmable logic construction kits for hyper-real-time neuronal modeling.

PubMed

Guerrero-Rivera, Ruben; Morrison, Abigail; Diesmann, Markus; Pearce, Tim C

2006-11-01

Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Abdolmohammadi, Hamid Reza; Khalaf, Abdul Jalil M.; Panahi, Shirin; Rajagopal, Karthikeyan; Pham, Viet-Thanh; Jafari, Sajad

2018-06-01

Nowadays, designing chaotic systems with hidden attractor is one of the most interesting topics in nonlinear dynamics and chaos. In this paper, a new 4D chaotic system is proposed. This new chaotic system has no equilibria, and so it belongs to the category of systems with hidden attractors. Dynamical features of this system are investigated with the help of its state-space portraits, bifurcation diagram, Lyapunov exponents diagram, and basin of attraction. Also a hardware realisation of this system is proposed by using field programmable gate arrays (FPGA). In addition, an electronic circuit design for the chaotic system is introduced.

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Single-Event Upset Characterization of Common First- and Second-Order All-Digital Phase-Locked Loops

NASA Astrophysics Data System (ADS)

Chen, Y. P.; Massengill, L. W.; Kauppila, J. S.; Bhuva, B. L.; Holman, W. T.; Loveless, T. D.

2017-08-01

The single-event upset (SEU) vulnerability of common first- and second-order all-digital-phase-locked loops (ADPLLs) is investigated through field-programmable gate array-based fault injection experiments. SEUs in the highest order pole of the loop filter and fraction-based phase detectors (PDs) may result in the worst case error response, i.e., limit cycle errors, often requiring system restart. SEUs in integer-based linear PDs may result in loss-of-lock errors, while SEUs in bang-bang PDs only result in temporary-frequency errors. ADPLLs with the same frequency tuning range but fewer bits in the control word exhibit better overall SEU performance.

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Zebulum, Ricardo; Rajeshuni, Ramesham; Stoica, Adrian; Katkoori, Srinivas; Graves, Sharon; Novak, Frank; Antill, Charles

2006-01-01

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

ERIC Educational Resources Information Center

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

A reconfigurable continuous-flow fluidic routing fabric using a modular, scalable primitive.

PubMed

Silva, Ryan; Bhatia, Swapnil; Densmore, Douglas

2016-07-05

Microfluidic devices, by definition, are required to move liquids from one physical location to another. Given a finite and frequently fixed set of physical channels to route fluids, a primitive design element that allows reconfigurable routing of that fluid from any of n input ports to any n output ports will dramatically change the paradigms by which these chips are designed and applied. Furthermore, if these elements are "regular" regarding their design, the programming and fabrication of these elements becomes scalable. This paper presents such a design element called a transposer. We illustrate the design, fabrication and operation of a single transposer. We then scale this design to create a programmable fabric towards a general-purpose, reconfigurable microfluidic platform analogous to the Field Programmable Gate Array (FPGA) found in digital electronics.

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin

Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sourcesmore » and detectors through an external clock with adjustable delay.« less

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

PubMed Central

Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; de Jesus Romero-Troncoso, Rene

2010-01-01

Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node. PMID:22163602

A field programmable gate array-based reconfigurable smart-sensor network for wireless monitoring of new generation computer numerically controlled machines.

PubMed

Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; Romero-Troncoso, Rene de Jesus

2010-01-01

Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node.

A single-board NMR spectrometer based on a software defined radio architecture

NASA Astrophysics Data System (ADS)

Tang, Weinan; Wang, Weimin

2011-01-01

A single-board software defined radio (SDR) spectrometer for nuclear magnetic resonance (NMR) is presented. The SDR-based architecture, realized by combining a single field programmable gate array (FPGA) and a digital signal processor (DSP) with peripheral radio frequency (RF) front-end circuits, makes the spectrometer compact and reconfigurable. The DSP, working as a pulse programmer, communicates with a personal computer via a USB interface and controls the FPGA through a parallel port. The FPGA accomplishes digital processing tasks such as a numerically controlled oscillator (NCO), digital down converter (DDC) and gradient waveform generator. The NCO, with agile control of phase, frequency and amplitude, is part of a direct digital synthesizer that is used to generate an RF pulse. The DDC performs quadrature demodulation, multistage low-pass filtering and gain adjustment to produce a bandpass signal (receiver bandwidth from 3.9 kHz to 10 MHz). The gradient waveform generator is capable of outputting shaped gradient pulse waveforms and supports eddy-current compensation. The spectrometer directly acquires an NMR signal up to 30 MHz in the case of baseband sampling and is suitable for low-field (<0.7 T) application. Due to the featured SDR architecture, this prototype has flexible add-on ability and is expected to be suitable for portable NMR systems.

A Hardware Platform for Tuning of MEMS Devices Using Closed-Loop Frequency Response

NASA Technical Reports Server (NTRS)

Ferguson, Michael I.; MacDonald, Eric; Foor, David

2005-01-01

We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing Post-Resonator MEMS gyroscope. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the micro-gyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Increasing feasibility of the field-programmable gate array implementation of an iterative image registration using a kernel-warping algorithm

NASA Astrophysics Data System (ADS)

Nguyen, An Hung; Guillemette, Thomas; Lambert, Andrew J.; Pickering, Mark R.; Garratt, Matthew A.

2017-09-01

Image registration is a fundamental image processing technique. It is used to spatially align two or more images that have been captured at different times, from different sensors, or from different viewpoints. There have been many algorithms proposed for this task. The most common of these being the well-known Lucas-Kanade (LK) and Horn-Schunck approaches. However, the main limitation of these approaches is the computational complexity required to implement the large number of iterations necessary for successful alignment of the images. Previously, a multi-pass image interpolation algorithm (MP-I2A) was developed to considerably reduce the number of iterations required for successful registration compared with the LK algorithm. This paper develops a kernel-warping algorithm (KWA), a modified version of the MP-I2A, which requires fewer iterations to successfully register two images and less memory space for the field-programmable gate array (FPGA) implementation than the MP-I2A. These reductions increase feasibility of the implementation of the proposed algorithm on FPGAs with very limited memory space and other hardware resources. A two-FPGA system rather than single FPGA system is successfully developed to implement the KWA in order to compensate insufficiency of hardware resources supported by one FPGA, and increase parallel processing ability and scalability of the system.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

TID Effects of High-Z Material Spot Shields on FPGA Using MPTB Data

NASA Technical Reports Server (NTRS)

Hardage, Donna (Technical Monitor); Crain, S. H.; Mazur, J. E.; Looper, M. D.

2003-01-01

An experiment on the Microelectronics and Photonics Test Bed (MPTB) was testing lield programmable gate arrays using spot shields to extend the life of some of the devices being tested. It was expected that the unshielded parts would fail from a total ionizing dose (TID) and yet the opposite occurred. The data show that the devices failing from the TID effects are those with the spot shields attached. This effort is to determine the mechanism by which the environment is interacting with the high-Z material to enhance the TID in these field programmable gate arrays.

Trapped-ion quantum logic gates based on oscillating magnetic fields.

PubMed

Ospelkaus, C; Langer, C E; Amini, J M; Brown, K R; Leibfried, D; Wineland, D J

2008-08-29

Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing (QIP). With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ion crystal and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering, a fundamental source of decoherence in laser-mediated gates.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Real-time field programmable gate array architecture for computer vision

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2001-01-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very- large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

PubMed Central

Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-01-01

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Slowing DNA Translocation in a Nanofluidic Field-Effect Transistor.

PubMed

Liu, Yifan; Yobas, Levent

2016-04-26

Here, we present an experimental demonstration of slowing DNA translocation across a nanochannel by modulating the channel surface charge through an externally applied gate bias. The experiments were performed on a nanofluidic field-effect transistor, which is a monolithic integrated platform featuring a 50 nm-diameter in-plane alumina nanocapillary whose entire length is surrounded by a gate electrode. The field-effect transistor behavior was validated on the gating of ionic conductance and protein transport. The gating of DNA translocation was subsequently studied by measuring discrete current dips associated with single λ-DNA translocation events under a source-to-drain bias of 1 V. The translocation speeds under various gate bias conditions were extracted by fitting event histograms of the measured translocation time to the first passage time distributions obtained from a simple 1D biased diffusion model. A positive gate bias was observed to slow the translocation of single λ-DNA chains markedly; the translocation speed was reduced by an order of magnitude from 18.4 mm/s obtained under a floating gate down to 1.33 mm/s under a positive gate bias of 9 V. Therefore, a dynamic and flexible regulation of the DNA translocation speed, which is vital for single-molecule sequencing, can be achieved on this device by simply tuning the gate bias. The device is realized in a conventional semiconductor microfabrication process without the requirement of advanced lithography, and can be potentially further developed into a compact electronic single-molecule sequencer.

Introduction to FPGA Devices and The Challenges for Critical Application - A User's Perspective

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth

2015-01-01

This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.

Analyzing Single-Event Gate Ruptures In Power MOSFET's

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

A Flexible Annular-Array Imaging Platform for Micro-Ultrasound

PubMed Central

Qiu, Weibao; Yu, Yanyan; Chabok, Hamid Reza; Liu, Cheng; Tsang, Fu Keung; Zhou, Qifa; Shung, K. Kirk; Zheng, Hairong; Sun, Lei

2013-01-01

Micro-ultrasound is an invaluable imaging tool for many clinical and preclinical applications requiring high resolution (approximately several tens of micrometers). Imaging systems for micro-ultrasound, including single-element imaging systems and linear-array imaging systems, have been developed extensively in recent years. Single-element systems are cheaper, but linear-array systems give much better image quality at a higher expense. Annular-array-based systems provide a third alternative, striking a balance between image quality and expense. This paper presents the development of a novel programmable and real-time annular-array imaging platform for micro-ultrasound. It supports multi-channel dynamic beamforming techniques for large-depth-of-field imaging. The major image processing algorithms were achieved by a novel field-programmable gate array technology for high speed and flexibility. Real-time imaging was achieved by fast processing algorithms and high-speed data transfer interface. The platform utilizes a printed circuit board scheme incorporating state-of-the-art electronics for compactness and cost effectiveness. Extensive tests including hardware, algorithms, wire phantom, and tissue mimicking phantom measurements were conducted to demonstrate good performance of the platform. The calculated contrast-to-noise ratio (CNR) of the tissue phantom measurements were higher than 1.2 in the range of 3.8 to 8.7 mm imaging depth. The platform supported more than 25 images per second for real-time image acquisition. The depth-of-field had about 2.5-fold improvement compared to single-element transducer imaging. PMID:23287923

Thermal Stress Analysis of Floating-Gate Tunneling Oxide Electrically Erasable Programmable Read Only Memory During Manufacturing Process

NASA Astrophysics Data System (ADS)

Zong, Xiang-fu; Wang, Xu; Weng, Yu-min; Yan, Ren-jin; Tang, Guo-an; Zhang, Zhao-qiang

1998-10-01

In this study, finite element modeling was used to evaluate the residual thermal stress in floating-gate tunneling oxide electrically erasable programmable read only memory (FLOTOX E2 PROMs) manufacturing process. Special attention is paid to the tunnel oxide region, in which high field electron injection is the basis to E2 PROMs operation. Calculated results show the presence of large stresses and stress gradients at the fringe. This may contribute to the invalidation of E2 PROMs. A possible failure mechanism of E2 PROM related to residual thermal stress-induced leakage is proposed.

Rapid wide-field Mueller matrix polarimetry imaging based on four photoelastic modulators with no moving parts.

PubMed

Alali, Sanaz; Gribble, Adam; Vitkin, I Alex

2016-03-01

A new polarimetry method is demonstrated to image the entire Mueller matrix of a turbid sample using four photoelastic modulators (PEMs) and a charge coupled device (CCD) camera, with no moving parts. Accurate wide-field imaging is enabled with a field-programmable gate array (FPGA) optical gating technique and an evolutionary algorithm (EA) that optimizes imaging times. This technique accurately and rapidly measured the Mueller matrices of air, polarization elements, and turbid phantoms. The system should prove advantageous for Mueller matrix analysis of turbid samples (e.g., biological tissues) over large fields of view, in less than a second.

Optimal quantum control of multimode couplings between trapped ion qubits for scalable entanglement.

PubMed

Choi, T; Debnath, S; Manning, T A; Figgatt, C; Gong, Z-X; Duan, L-M; Monroe, C

2014-05-16

We demonstrate entangling quantum gates within a chain of five trapped ion qubits by optimally shaping optical fields that couple to multiple collective modes of motion. We individually address qubits with segmented optical pulses to construct multipartite entangled states in a programmable way. This approach enables high-fidelity gates that can be scaled to larger qubit registers for quantum computation and simulation.

Software Graphics Processing Unit (sGPU) for Deep Space Applications

NASA Technical Reports Server (NTRS)

McCabe, Mary; Salazar, George; Steele, Glen

2015-01-01

A graphics processing capability will be required for deep space missions and must include a range of applications, from safety-critical vehicle health status to telemedicine for crew health. However, preliminary radiation testing of commercial graphics processing cards suggest they cannot operate in the deep space radiation environment. Investigation into an Software Graphics Processing Unit (sGPU)comprised of commercial-equivalent radiation hardened/tolerant single board computers, field programmable gate arrays, and safety-critical display software shows promising results. Preliminary performance of approximately 30 frames per second (FPS) has been achieved. Use of multi-core processors may provide a significant increase in performance.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Zheming; Yoshii, Kazutomo; Finkel, Hal

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication andmore » kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.« less

Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems.

PubMed

Park, Jongkil; Yu, Theodore; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

2017-10-01

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at 3.6×10 7 synaptic events per second per 16k-neuron node in the hierarchy.

Vacuum lamination approach to fabrication of high-performance single-crystal organic field-effect transistors.

PubMed

Yi, H T; Chen, Y; Czelen, K; Podzorov, V

2011-12-22

A novel vacuum lamination approach to fabrication of high-performance single-crystal organic field-effect transistors has been developed. The non-destructive nature of this method allows a direct comparison of field-effect mobilities achieved with various gate dielectrics using the same single-crystal sample. The method also allows gating delicate systems, such as n -type crystals and SAM-coated surfaces, without perturbation. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Independent component analysis algorithm FPGA design to perform real-time blind source separation

NASA Astrophysics Data System (ADS)

Meyer-Baese, Uwe; Odom, Crispin; Botella, Guillermo; Meyer-Baese, Anke

2015-05-01

The conditions that arise in the Cocktail Party Problem prevail across many fields creating a need for of Blind Source Separation. The need for BSS has become prevalent in several fields of work. These fields include array processing, communications, medical signal processing, and speech processing, wireless communication, audio, acoustics and biomedical engineering. The concept of the cocktail party problem and BSS led to the development of Independent Component Analysis (ICA) algorithms. ICA proves useful for applications needing real time signal processing. The goal of this research was to perform an extensive study on ability and efficiency of Independent Component Analysis algorithms to perform blind source separation on mixed signals in software and implementation in hardware with a Field Programmable Gate Array (FPGA). The Algebraic ICA (A-ICA), Fast ICA, and Equivariant Adaptive Separation via Independence (EASI) ICA were examined and compared. The best algorithm required the least complexity and fewest resources while effectively separating mixed sources. The best algorithm was the EASI algorithm. The EASI ICA was implemented on hardware with Field Programmable Gate Arrays (FPGA) to perform and analyze its performance in real time.

A Re-programmable Platform for Dynamic Burn-in Test of Xilinx Virtexll 3000 FPGA for Military and Aerospace Applications

NASA Technical Reports Server (NTRS)

Roosta, Ramin; Wang, Xinchen; Sadigursky, Michael; Tracton, Phil

2004-01-01

Field Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).

NASA Electronic Parts and Packaging Field Programmable Gate Array Single Event Effects Test Guideline Update

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.

2018-01-01

The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.

NASA Electronic Parts and Packaging (NEPP) Field Programmable Gate Array (FPGA) Single Event Effects (SEE) Test Guideline Update

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.

2018-01-01

The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.

A binary link tracker for the BaBar level 1 trigger system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berenyi, A.; Chen, H.K.; Dao, K.

1999-08-01

The BaBar detector at PEP-II will operate in a high-luminosity e{sup +}e{sup {minus}} collider environment near the {Upsilon}(4S) resonance with the primary goal of studying CP violation in the B meson system. In this environment, typical physics events of interest involve multiple charged particles. These events are identified by counting these tracks in a fast first level (Level 1) trigger system, by reconstructing the tracks in real time. For this purpose, a Binary Link Tracker Module (BLTM) was designed and fabricated for the BaBar Level 1 Drift Chamber trigger system. The BLTM is responsible for linking track segments, constructed bymore » the Track Segment Finder Modules (TSFM), into complete tracks. A single BLTM module processes a 360 MBytes/s stream of segment hit data, corresponding to information from the entire Drift Chamber, and implements a fast and robust algorithm that tolerates high hit occupancies as well as local inefficiencies of the Drift Chamber. The algorithms and the necessary control logic of the BLTM were implemented in Field Programmable Gate Arrays (FPGAs), using the VHDL hardware description language. The finished 9U x 400 mm Euro-format board contains roughly 75,000 gates of programmable logic or about 10,000 lines of VHDL code synthesized into five FPGAs.« less

The IMPACT Common Module - A Low Cost, Reconfigurable Building Block for Next Generation Phased Arrays

DTIC Science & Technology

2016-03-31

The SiGe receiver has two stages of programmable RF filtering and one stage of IF filtering. Each filter can be tuned in center frequency and...distribution unlimited. transmit, with an IF to RF upconversion chain that is split to programmable phase shifters and VGAs at each output port. Figure 2...These are optimized to run on medium grade Field Programmable Gate Arrays (FPGAs), such as the Altera Arria 10, and represent a few of the many

Risk Reduction for Use of Complex Devices in Space Projects

NASA Technical Reports Server (NTRS)

Berg, Melanie; Poivey, Christian; Friendlich, Mark; Petrick, Dave; LaBel, Kenneth; Stansberry, Scott

2007-01-01

We present guidel!nes to reduce risk to an acceptable level when using complex devices in space applications. Application to Virtex 4 Field Programmable Gate Array (FPGA) on Express Logistic Carrier (ELC) project is presented.

Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

NASA Astrophysics Data System (ADS)

Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

2010-12-01

An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

NASA Astrophysics Data System (ADS)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

A field programmable gate array unit for the diagnosis and control of neoclassical tearing modes on MAST

DOE Office of Scientific and Technical Information (OSTI.GOV)

O'Gorman, T.; Gibson, K. J.; Snape, J. A.

2012-10-15

A real-time system has been developed to trigger both the MAST Thomson scattering (TS) system and the plasma control system on the phase and amplitude of neoclassical tearing modes (NTMs), extending the capabilities of the original system. This triggering system determines the phase and amplitude of a given NTM using magnetic coils at different toroidal locations. Real-time processing of the raw magnetic data occurs on a low cost field programmable gate array (FPGA) based unit which permits triggering of the TS lasers on specific amplitudes and phases of NTM evolution. The MAST plasma control system can receive a separate triggermore » from the FPGA unit that initiates a vertical shift of the MAST magnetic axis. Such shifts have fully removed m/n= 2/1 NTMs instabilities on a number of MAST discharges.« less

Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

NASA Technical Reports Server (NTRS)

King, K. D.

2003-01-01

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.

An acceleration framework for synthetic aperture radar algorithms

NASA Astrophysics Data System (ADS)

Kim, Youngsoo; Gloster, Clay S.; Alexander, Winser E.

2017-04-01

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.

A programmable metasurface with dynamic polarization, scattering and focusing control

NASA Astrophysics Data System (ADS)

Yang, Huanhuan; Cao, Xiangyu; Yang, Fan; Gao, Jun; Xu, Shenheng; Li, Maokun; Chen, Xibi; Zhao, Yi; Zheng, Yuejun; Li, Sijia

2016-10-01

Diverse electromagnetic (EM) responses of a programmable metasurface with a relatively large scale have been investigated, where multiple functionalities are obtained on the same surface. The unit cell in the metasurface is integrated with one PIN diode, and thus a binary coded phase is realized for a single polarization. Exploiting this anisotropic characteristic, reconfigurable polarization conversion is presented first. Then the dynamic scattering performance for two kinds of sources, i.e. a plane wave and a point source, is carefully elaborated. To tailor the scattering properties, genetic algorithm, normally based on binary coding, is coupled with the scattering pattern analysis to optimize the coding matrix. Besides, inverse fast Fourier transform (IFFT) technique is also introduced to expedite the optimization process of a large metasurface. Since the coding control of each unit cell allows a local and direct modulation of EM wave, various EM phenomena including anomalous reflection, diffusion, beam steering and beam forming are successfully demonstrated by both simulations and experiments. It is worthwhile to point out that a real-time switch among these functionalities is also achieved by using a field-programmable gate array (FPGA). All the results suggest that the proposed programmable metasurface has great potentials for future applications.

A programmable metasurface with dynamic polarization, scattering and focusing control

PubMed Central

Yang, Huanhuan; Cao, Xiangyu; Yang, Fan; Gao, Jun; Xu, Shenheng; Li, Maokun; Chen, Xibi; Zhao, Yi; Zheng, Yuejun; Li, Sijia

2016-01-01

Diverse electromagnetic (EM) responses of a programmable metasurface with a relatively large scale have been investigated, where multiple functionalities are obtained on the same surface. The unit cell in the metasurface is integrated with one PIN diode, and thus a binary coded phase is realized for a single polarization. Exploiting this anisotropic characteristic, reconfigurable polarization conversion is presented first. Then the dynamic scattering performance for two kinds of sources, i.e. a plane wave and a point source, is carefully elaborated. To tailor the scattering properties, genetic algorithm, normally based on binary coding, is coupled with the scattering pattern analysis to optimize the coding matrix. Besides, inverse fast Fourier transform (IFFT) technique is also introduced to expedite the optimization process of a large metasurface. Since the coding control of each unit cell allows a local and direct modulation of EM wave, various EM phenomena including anomalous reflection, diffusion, beam steering and beam forming are successfully demonstrated by both simulations and experiments. It is worthwhile to point out that a real-time switch among these functionalities is also achieved by using a field-programmable gate array (FPGA). All the results suggest that the proposed programmable metasurface has great potentials for future applications. PMID:27774997

A programmable metasurface with dynamic polarization, scattering and focusing control.

PubMed

Yang, Huanhuan; Cao, Xiangyu; Yang, Fan; Gao, Jun; Xu, Shenheng; Li, Maokun; Chen, Xibi; Zhao, Yi; Zheng, Yuejun; Li, Sijia

2016-10-24

Diverse electromagnetic (EM) responses of a programmable metasurface with a relatively large scale have been investigated, where multiple functionalities are obtained on the same surface. The unit cell in the metasurface is integrated with one PIN diode, and thus a binary coded phase is realized for a single polarization. Exploiting this anisotropic characteristic, reconfigurable polarization conversion is presented first. Then the dynamic scattering performance for two kinds of sources, i.e. a plane wave and a point source, is carefully elaborated. To tailor the scattering properties, genetic algorithm, normally based on binary coding, is coupled with the scattering pattern analysis to optimize the coding matrix. Besides, inverse fast Fourier transform (IFFT) technique is also introduced to expedite the optimization process of a large metasurface. Since the coding control of each unit cell allows a local and direct modulation of EM wave, various EM phenomena including anomalous reflection, diffusion, beam steering and beam forming are successfully demonstrated by both simulations and experiments. It is worthwhile to point out that a real-time switch among these functionalities is also achieved by using a field-programmable gate array (FPGA). All the results suggest that the proposed programmable metasurface has great potentials for future applications.

Programmable Pulse-Position-Modulation Encoder

NASA Technical Reports Server (NTRS)

Zhu, David; Farr, William

2006-01-01

A programmable pulse-position-modulation (PPM) encoder has been designed for use in testing an optical communication link. The encoder includes a programmable state machine and an electronic code book that can be updated to accommodate different PPM coding schemes. The encoder includes a field-programmable gate array (FPGA) that is programmed to step through the stored state machine and code book and that drives a custom high-speed serializer circuit board that is capable of generating subnanosecond pulses. The stored state machine and code book can be updated by means of a simple text interface through the serial port of a personal computer.

High-Performance, Radiation-Hardened Electronics for Space Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.; Frazier, Donald O.; Adams, James H.; Johnson, Michael A.; Kolawa, Elizabeth A.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog Arrays (FPAA)s for use in reconfigurable architectures. As these component/chip level technologies mature, the RHESE project emphasis shifts to focus on efforts encompassing total processor hardening techniques and board-level electronic reconfiguration techniques featuring spare and interface modularity. This phased approach to distributing emphasis between technology developments provides hardened FPGA/FPAAs for early mission infusion, then migrates to hardened, board-level, high speed processors with associated memory elements and high density storage for the longer duration missions encountered for Lunar Outpost and Mars Exploration occurring later in the Constellation schedule.

A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

PubMed Central

Guo, Xinyu; Wang, Hong; Devabhaktuni, Vijay

2012-01-01

A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle. Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit. These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures. PMID:25969747

FPGA implementation of current-sharing strategy for parallel-connected SEPICs

NASA Astrophysics Data System (ADS)

Ezhilarasi, A.; Ramaswamy, M.

2016-01-01

The attempt echoes to evolve an equal current-sharing algorithm over a number of single-ended primary inductance converters connected in parallel. The methodology involves the development of state-space model to predict the condition for the existence of a stable equilibrium portrait. It acquires the role of a variable structure controller to guide the trajectory, with a view to circumvent the circuit non-linearities and arrive at a stable performance through a preferred operating range. The design elicits an acceptable servo and regulatory characteristics, the desired time response and ensures regulation of the load voltage. The simulation results validated through a field programmable gate array-based prototype serves to illustrate its suitability for present-day applications.

Single-Event Transient Testing of Low Dropout PNP Series Linear Voltage Regulators

NASA Technical Reports Server (NTRS)

Adell, Philippe; Allen, Gregory

2013-01-01

As demand for high-speed, on-board, digital-processing integrated circuits on spacecraft increases (field-programmable gate arrays and digital signal processors in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The goal of this task is to perform SET characterization of several commercial POL converters, and provide a discussion of the impact of these results to state-of-the-art digital processing IC through laser and heavy ion testing

Implementation of a Configurable Fault Tolerant Processor (CFTP) Using Internal Triple Modular Redundancy (TMR)

DTIC Science & Technology

2005-12-01

Upsets in SRAM FPGAs,” Military and Aerospace Applications of Programmable Logic Devices, September 2002. 8. Wakerly , John F,. “Microcomputer...change. The goal of the Configurable Fault Tolerant Processor (CFTP) Project is to explore, develop and demonstrate the applicability of using off-the...develop and demonstrate the applicability of using commercial-of-the-shelf (COTS) Field Programmable Gate Arrays (FPGA) in the design of

Field-Programmable Gate Array Computer in Structural Analysis: An Initial Exploration

NASA Technical Reports Server (NTRS)

Singleterry, Robert C., Jr.; Sobieszczanski-Sobieski, Jaroslaw; Brown, Samuel

2002-01-01

This paper reports on an initial assessment of using a Field-Programmable Gate Array (FPGA) computational device as a new tool for solving structural mechanics problems. A FPGA is an assemblage of binary gates arranged in logical blocks that are interconnected via software in a manner dependent on the algorithm being implemented and can be reprogrammed thousands of times per second. In effect, this creates a computer specialized for the problem that automatically exploits all the potential for parallel computing intrinsic in an algorithm. This inherent parallelism is the most important feature of the FPGA computational environment. It is therefore important that if a problem offers a choice of different solution algorithms, an algorithm of a higher degree of inherent parallelism should be selected. It is found that in structural analysis, an 'analog computer' style of programming, which solves problems by direct simulation of the terms in the governing differential equations, yields a more favorable solution algorithm than current solution methods. This style of programming is facilitated by a 'drag-and-drop' graphic programming language that is supplied with the particular type of FPGA computer reported in this paper. Simple examples in structural dynamics and statics illustrate the solution approach used. The FPGA system also allows linear scalability in computing capability. As the problem grows, the number of FPGA chips can be increased with no loss of computing efficiency due to data flow or algorithmic latency that occurs when a single problem is distributed among many conventional processors that operate in parallel. This initial assessment finds the FPGA hardware and software to be in their infancy in regard to the user conveniences; however, they have enormous potential for shrinking the elapsed time of structural analysis solutions if programmed with algorithms that exhibit inherent parallelism and linear scalability. This potential warrants further development of FPGA-tailored algorithms for structural analysis.

New Developments in Error Detection and Correction Strategies for Critical Applications

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Ken

2017-01-01

The presentation will cover a variety of mitigation strategies that were developed for critical applications. An emphasis is placed on strengths and weaknesses per mitigation technique as it pertains to different Field programmable gate array (FPGA) device types.

Results from the RF BPM Upgrade Prototype at the Advanced Photon Source

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pietryla, Anthony; Lill, Robert; Norum, Eric

2006-11-20

The Advanced Photon Source (APS), a third-generation synchrotron light source, has been in operation for 10 years. The monopulse radio frequency (RF) beam position monitor (BPM) is one of three BPM types now employed in the storage ring at the APS. It is a broadband (10 MHz) system designed to measure single-turn and multi-turn beam positions, but it suffers from an aging data acquisition system. The replacement BPM system retains the existing monopulse receivers and replaces the data acquisition system with high-speed analog-to-digital converters (ADCs) and a field programmable gate array (FPGA) that performs the signal processing. A prototype systemmore » was constructed and is currently being evaluated. This paper presents the results obtained from laboratory and field tests of the prototype system.« less

Results from the RF BPM upgrade prototype at the Advanced Photon Source.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pietryla, A.; Lill, R.; Norum, E.

2006-01-01

The Advanced Photon Source (APS), a third-generation synchrotron light source, has been in operation for 10 years. The monopulse radio frequency (RF) beam position monitor (BPM) is one of three BPM types now employed in the storage ring at the APS. It is a broadband (10 MHz) system designed to measure single-turn and multi-turn beam positions, but it suffers from an aging data acquisition system. The replacement BPM system retains the existing monopulse receivers and replaces the data acquisition system with high-speed analog-to-digital converters (ADCs) and a field programmable gate array (FPGA) that performs the signal processing. A prototype systemmore » was constructed and is currently being evaluated. This paper presents the results obtained from laboratory and field tests of the prototype system.« less

Comparison of laser Doppler and laser speckle contrast imaging using a concurrent processing system

NASA Astrophysics Data System (ADS)

Sun, Shen; Hayes-Gill, Barrie R.; He, Diwei; Zhu, Yiqun; Huynh, Nam T.; Morgan, Stephen P.

2016-08-01

Full field laser Doppler imaging (LDI) and single exposure laser speckle contrast imaging (LSCI) are directly compared using a novel instrument which can concurrently image blood flow using both LDI and LSCI signal processing. Incorporating a commercial CMOS camera chip and a field programmable gate array (FPGA) the flow images of LDI and the contrast maps of LSCI are simultaneously processed by utilizing the same detected optical signals. The comparison was carried out by imaging a rotating diffuser. LDI has a linear response to the velocity. In contrast, LSCI is exposure time dependent and does not provide a linear response in the presence of static speckle. It is also demonstrated that the relationship between LDI and LSCI can be related through a power law which depends on the exposure time of LSCI.

Auditory inhibitory gating in medial prefrontal cortex: Single unit and local field potential analysis.

PubMed

Mears, R P; Klein, A C; Cromwell, H C

2006-08-11

Medial prefrontal cortex is a crucial region involved in inhibitory processes. Damage to the medial prefrontal cortex can lead to loss of normal inhibitory control over motor, sensory, emotional and cognitive functions. The goal of the present study was to examine the basic properties of inhibitory gating in this brain region in rats. Inhibitory gating has recently been proposed as a neurophysiological assay for sensory filters in higher brain regions that potentially enable or disable information throughput. This perspective has important clinical relevance due to the findings that gating is dramatically impaired in individuals with emotional and cognitive impairments (i.e. schizophrenia). We used the standard inhibitory gating two-tone paradigm with a 500 ms interval between tones and a 10 s interval between tone pairs. We recorded both single unit and local field potentials from chronic microwire arrays implanted in the medial prefrontal cortex. We investigated short-term (within session) and long-term (between session) variability of auditory gating and additionally examined how altering the interval between the tones influenced the potency of the inhibition. The local field potentials displayed greater variability with a reduction in the amplitudes of the tone responses over both the short and long-term time windows. The decrease across sessions was most intense for the second tone response (test tone) leading to a more robust gating (lower T/C ratio). Surprisingly, single unit responses of different varieties retained similar levels of auditory responsiveness and inhibition in both the short and long-term analysis. Neural inhibition decreased monotonically related to the increase in intertone interval. This change in gating was most consistent in the local field potentials. Subsets of single unit responses did not show the lack of inhibition even for the longer intertone intervals tested (4 s interval). These findings support the idea that the medial prefrontal cortex is an important site where early inhibitory functions reside and potentially mediate psychological processes.

Designed cell consortia as fragrance-programmable analog-to-digital converters.

PubMed

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Simultaneous G-Quadruplex DNA Logic.

PubMed

Bader, Antoine; Cockroft, Scott L

2018-04-03

A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

PubMed

Bergano, Miguel; Rocha, Armando; Cupido, Luís; Barbosa, Domingos; Villela, Thyrso; Boas, José Vilas; Rocha, Graça; Smoot, George F

2016-01-01

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing subsystem levels for large projects like the square kilometer array testbeds.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Crosstalk error correction through dynamical decoupling of single-qubit gates in capacitively coupled singlet-triplet semiconductor spin qubits

NASA Astrophysics Data System (ADS)

Buterakos, Donovan; Throckmorton, Robert E.; Das Sarma, S.

2018-01-01

In addition to magnetic field and electric charge noise adversely affecting spin-qubit operations, performing single-qubit gates on one of multiple coupled singlet-triplet qubits presents a new challenge: crosstalk, which is inevitable (and must be minimized) in any multiqubit quantum computing architecture. We develop a set of dynamically corrected pulse sequences that are designed to cancel the effects of both types of noise (i.e., field and charge) as well as crosstalk to leading order, and provide parameters for these corrected sequences for all 24 of the single-qubit Clifford gates. We then provide an estimate of the error as a function of the noise and capacitive coupling to compare the fidelity of our corrected gates to their uncorrected versions. Dynamical error correction protocols presented in this work are important for the next generation of singlet-triplet qubit devices where coupling among many qubits will become relevant.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

NASA Astrophysics Data System (ADS)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology. Electronic supplementary information (ESI) available: Additional figures (Table S1, Fig. S1-S5). See DOI: 10.1039/c4nr01676a

SU-E-T-64: A Programmable Moving Insert for the ArcCHECK Phantom for Dose Verification of Respiratory-Gated VMAT

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaede, S; Jordan, K; Western University, London, ON

Purpose: To present a customized programmable moving insert for the ArcCHECK™ phantom that can, in a single delivery, check both entrance dosimetry, while simultaneously verifying the delivery of respiratory-gated VMAT. Methods: The cylindrical motion phantom uses a computer-controlled stepping motor to move an insert inside a stationery sleeve. Insert motion is programmable and can include rotational motion in addition to linear motion along the axis of the cylinder. The sleeve fits securely in the bore of the ArcCHECK™. Interchangeable inserts, including an A1SL chamber, optically-stimulated luminescence dosimeters, radiochromic film, or 3D gels, allow this combination to be used for commissioning,more » routine quality assurance, and patient-specific dosimetric verification of respiratory-gated VMAT. Before clinical implementation, the effect of a moving insert on the ArcCHECK™ measurements was considered. First, the measured dose to the ArcCHECK™ containing multiple inserts in the static position was compared to the calculated dose during multiple VMAT treatment deliveries. Then, dose was measured under both sinusoidal and real-patient motion conditions to determine any effect of the moving inserts on the ArcCHECK™ measurements. Finally, dose was measured during gated VMAT delivery to the same inserts under the same motion conditions to examine any effect of various beam “on-and-off” and dose rate ramp “up-and-down”. Multiple comparisons between measured and calculated dose to different inserts were also considered. Results: The pass rate for the static delivery exceeded 98% for all measurements (3%/3mm), suggesting a valid setup for entrance dosimetry. The pass rate was not altered for any measurement delivered under motion conditions. A similar Result was observed under gated VMAT conditions, including agreement of measured and calculated dose to the various inserts. Conclusion: Incorporating a programmable moving insert within the ArcCHECK™ phantom provides an efficient verification of respiratory-gated VMAT delivery that is useful during commissioning, routine quality assurance, and patient-specific dose verification. Prototype phantom development and testing was performed in collaboration with Modus Medical Devices Inc. (London, ON). No financial support was granted.« less

Quantum gates by periodic driving

PubMed Central

Shi, Z. C.; Wang, W.; Yi, X. X.

2016-01-01

Topological quantum computation has been extensively studied in the past decades due to its robustness against decoherence. One way to realize the topological quantum computation is by adiabatic evolutions—it requires relatively long time to complete a gate, so the speed of quantum computation slows down. In this work, we present a method to realize single qubit quantum gates by periodic driving. Compared to adiabatic evolution, the single qubit gates can be realized at a fixed time much shorter than that by adiabatic evolution. The driving fields can be sinusoidal or square-well field. With the sinusoidal driving field, we derive an expression for the total operation time in the high-frequency limit, and an exact analytical expression for the evolution operator without any approximations is given for the square well driving. This study suggests that the period driving could provide us with a new direction in regulations of the operation time in topological quantum computation. PMID:26911900

Quantum gates by periodic driving.

PubMed

Shi, Z C; Wang, W; Yi, X X

2016-02-25

Topological quantum computation has been extensively studied in the past decades due to its robustness against decoherence. One way to realize the topological quantum computation is by adiabatic evolutions-it requires relatively long time to complete a gate, so the speed of quantum computation slows down. In this work, we present a method to realize single qubit quantum gates by periodic driving. Compared to adiabatic evolution, the single qubit gates can be realized at a fixed time much shorter than that by adiabatic evolution. The driving fields can be sinusoidal or square-well field. With the sinusoidal driving field, we derive an expression for the total operation time in the high-frequency limit, and an exact analytical expression for the evolution operator without any approximations is given for the square well driving. This study suggests that the period driving could provide us with a new direction in regulations of the operation time in topological quantum computation.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

NASA Astrophysics Data System (ADS)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

2014-02-01

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of datamore » acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.« less

Catalytic nucleic acids (DNAzymes) as functional units for logic gates and computing circuits: from basic principles to practical applications.

PubMed

Orbach, Ron; Willner, Bilha; Willner, Itamar

2015-03-11

This feature article addresses the implementation of catalytic nucleic acids as functional units for the construction of logic gates and computing circuits, and discusses the future applications of these systems. The assembly of computational modules composed of DNAzymes has led to the operation of a universal set of logic gates, to field programmable logic gates and computing circuits, to the development of multiplexers/demultiplexers, and to full-adder systems. Also, DNAzyme cascades operating as logic gates and computing circuits were demonstrated. DNAzyme logic systems find important practical applications. These include the use of DNAzyme-based systems for sensing and multiplexed analyses, for the development of controlled release and drug delivery systems, for regulating intracellular biosynthetic pathways, and for the programmed synthesis and operation of cascades.

Radiation Hardened Electronics for Extreme Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Watson, Michael D.

2007-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches.

FPGA cluster for high-performance AO real-time control system

NASA Astrophysics Data System (ADS)

Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

2006-06-01

Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

A Versatile Planetary Radio Science Microreceiver

NASA Technical Reports Server (NTRS)

Fry, Craig D.; Rosenberg, T. J.

1999-01-01

We have developed a low-power. programmable radio "microreceiver" that combines the functionality of two science instruments: a Relative Ionospheric Opacity Meter (riometer) and a swept-frequency, VTF/HF radio spectrometer. The radio receiver, calibration noise source, data acquisition and processing, and command and control functions are all contained on a single circuit board. This design is suitable for miniaturizing as a complete flight instrument. Several of the subsystems were implemented in a field-programmable gate array (FPGA), including the receiver detector, the control logic, and the data acquisition and processing blocks. Considerable efforts were made to reduce the power consumption of the instrument, and eliminate or minimize RF noise and spurious emissions generated by the receiver's digital circuitry. A prototype instrument was deployed at McMurdo Station, Antarctica, and operated in parallel with a traditional riometer instrument for approximately three weeks. The attached paper (accepted for publication by Radio Science) describes in detail the microreceiver theory of operation, performance specifications and test results.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

NASA Technical Reports Server (NTRS)

Edwards, R. Timothy; Strohbehn, Kim; Jaskulek, Steven E.; Katz, Richard

1999-01-01

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Wilcox, Edward; Berg, Melanie; Friendlich, Mark; Lakeman, Joseph; KIm, Hak; Pellish, Jonathan; LaBel, Kenneth

2012-01-01

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.

Field-programmable gate array-controlled sweep velocity-locked laser pulse generator

NASA Astrophysics Data System (ADS)

Chen, Zhen; Hefferman, Gerald; Wei, Tao

2017-05-01

A field-programmable gate array (FPGA)-controlled sweep velocity-locked laser pulse generator (SV-LLPG) design based on an all-digital phase-locked loop (ADPLL) is proposed. A distributed feedback laser with modulated injection current was used as a swept-frequency laser source. An open-loop predistortion modulation waveform was calibrated using a feedback iteration method to initially improve frequency sweep linearity. An ADPLL control system was then implemented using an FPGA to lock the output of a Mach-Zehnder interferometer that was directly proportional to laser sweep velocity to an on-board system clock. Using this system, linearly chirped laser pulses with a sweep bandwidth of 111.16 GHz were demonstrated. Further testing evaluating the sensing utility of the system was conducted. In this test, the SV-LLPG served as the swept laser source of an optical frequency-domain reflectometry system used to interrogate a subterahertz range fiber structure (sub-THz-FS) array. A static strain test was then conducted and linear sensor results were observed.

Note: a 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy.

PubMed

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A M

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Fast contactless vibrating structure characterization using real time field programmable gate array-based digital signal processing: demonstrations with a passive wireless acoustic delay line probe and vision.

PubMed

Goavec-Mérou, G; Chrétien, N; Friedt, J-M; Sandoz, P; Martin, G; Lenczner, M; Ballandras, S

2014-01-01

Vibrating mechanical structure characterization is demonstrated using contactless techniques best suited for mobile and rotating equipments. Fast measurement rates are achieved using Field Programmable Gate Array (FPGA) devices as real-time digital signal processors. Two kinds of algorithms are implemented on FPGA and experimentally validated in the case of the vibrating tuning fork. A first application concerns in-plane displacement detection by vision with sampling rates above 10 kHz, thus reaching frequency ranges above the audio range. A second demonstration concerns pulsed-RADAR cooperative target phase detection and is applied to radiofrequency acoustic transducers used as passive wireless strain gauges. In this case, the 250 ksamples/s refresh rate achieved is only limited by the acoustic sensor design but not by the detection bandwidth. These realizations illustrate the efficiency, interest, and potentialities of FPGA-based real-time digital signal processing for the contactless interrogation of passive embedded probes with high refresh rates.

Note: A 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy

NASA Astrophysics Data System (ADS)

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A. M.

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Multiple Embedded Processors for Fault-Tolerant Computing

NASA Technical Reports Server (NTRS)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

Design Tools for Reconfigurable Hardware in Orbit (RHinO)

NASA Technical Reports Server (NTRS)

French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

2004-01-01

The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

Programmable computing with a single magnetoresistive element

NASA Astrophysics Data System (ADS)

Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

2003-10-01

The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

NASA Astrophysics Data System (ADS)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs

NASA Astrophysics Data System (ADS)

Sterpone, L.; Violante, M.

2007-08-01

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to successfully deploy safety- or mission-critical applications, designer need to validate the correctness of the obtained designs. In this paper we describe a system based on partial-reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs. The proposed fault-injection system uses the internal configuration capabilities that modern FPGAs offer in order to inject SEU within the configuration memory. Detailed experimental results show that the technique is orders of magnitude faster than previously proposed ones.

Hardware platforms for MEMS gyroscope tuning based on evolutionary computation using open-loop and closed -loop frequency response

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Ferguson, Michael I.; Fink, Wolfgang; Oks, Boris; Peay, Chris; Terrile, Richard; Cheng, Yen; Kim, Dennis; MacDonald, Eric; Foor, David

2005-01-01

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation. We also report on the development of a hardware platform for integrated tuning and closed loop operation of MEMS gyroscopes. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

A single FPGA-based portable ultrasound imaging system for point-of-care applications.

PubMed

Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

2012-07-01

We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

Photon-triggered nanowire transistors

NASA Astrophysics Data System (ADS)

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J.; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 106. A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Photon-triggered nanowire transistors.

PubMed

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 10 6 . A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Two-dimensional non-volatile programmable p-n junctions

NASA Astrophysics Data System (ADS)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Two-dimensional non-volatile programmable p-n junctions.

PubMed

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe 2 /hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 10 4 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)

PubMed Central

Li, Isaac TS; Shum, Warren; Truong, Kevin

2007-01-01

Background To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. Results In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. Conclusion This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching. PMID:17555593

160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA).

PubMed

Li, Isaac T S; Shum, Warren; Truong, Kevin

2007-06-07

To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching.

A digital receiver module with direct data acquisition for magnetic resonance imaging systems.

PubMed

Tang, Weinan; Sun, Hongyu; Wang, Weimin

2012-10-01

A digital receiver module for magnetic resonance imaging (MRI) with detailed hardware implementations is presented. The module is based on a direct sampling scheme using the latest mixed-signal circuit design techniques. A single field-programmable gate array chip is employed to perform software-based digital down conversion for radio frequency signals. The modular architecture of the receiver allows multiple acquisition channels to be implemented on a highly integrated printed circuit board. To maintain the phase coherence of the receiver and the exciter in the context of direct sampling, an effective phase synchronization method was proposed to achieve a phase deviation as small as 0.09°. The performance of the described receiver module was verified in the experiments for both low- and high-field (0.5 T and 1.5 T) MRI scanners and was compared to a modern commercial MRI receiver system.

High-speed sorting of grains by color and surface texture

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with different colors/textures. The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) that was programmed to execute ...

Digital algorithms for parallel pipelined single-detector homodyne fringe counting in laser interferometry

NASA Astrophysics Data System (ADS)

Rerucha, Simon; Sarbort, Martin; Hola, Miroslava; Cizek, Martin; Hucl, Vaclav; Cip, Ondrej; Lazar, Josef

2016-12-01

The homodyne detection with only a single detector represents a promising approach in the interferometric application which enables a significant reduction of the optical system complexity while preserving the fundamental resolution and dynamic range of the single frequency laser interferometers. We present the design, implementation and analysis of algorithmic methods for computational processing of the single-detector interference signal based on parallel pipelined processing suitable for real time implementation on a programmable hardware platform (e.g. the FPGA - Field Programmable Gate Arrays or the SoC - System on Chip). The algorithmic methods incorporate (a) the single detector signal (sine) scaling, filtering, demodulations and mixing necessary for the second (cosine) quadrature signal reconstruction followed by a conic section projection in Cartesian plane as well as (a) the phase unwrapping together with the goniometric and linear transformations needed for the scale linearization and periodic error correction. The digital computing scheme was designed for bandwidths up to tens of megahertz which would allow to measure the displacements at the velocities around half metre per second. The algorithmic methods were tested in real-time operation with a PC-based reference implementation that employed the advantage pipelined processing by balancing the computational load among multiple processor cores. The results indicate that the algorithmic methods are suitable for a wide range of applications [3] and that they are bringing the fringe counting interferometry closer to the industrial applications due to their optical setup simplicity and robustness, computational stability, scalability and also a cost-effectiveness.

Implementation of cascade logic gates and majority logic gate on a simple and universal molecular platform.

PubMed

Gao, Jinting; Liu, Yaqing; Lin, Xiaodong; Deng, Jiankang; Yin, Jinjin; Wang, Shuo

2017-10-25

Wiring a series of simple logic gates to process complex data is significantly important and a large challenge for untraditional molecular computing systems. The programmable property of DNA endows its powerful application in molecular computing. In our investigation, it was found that DNA exhibits excellent peroxidase-like activity in a colorimetric system of TMB/H 2 O 2 /Hemin (TMB, 3,3', 5,5'-Tetramethylbenzidine) in the presence of K + and Cu 2+ , which is significantly inhibited by the addition of an antioxidant. According to the modulated catalytic activity of this DNA-based catalyst, three cascade logic gates including AND-OR-INH (INHIBIT), AND-INH and OR-INH were successfully constructed. Interestingly, by only modulating the concentration of Cu 2+ , a majority logic gate with a single-vote veto function was realized following the same threshold value as that of the cascade logic gates. The strategy is quite straightforward and versatile and provides an instructive method for constructing multiple logic gates on a simple platform to implement complex molecular computing.

An Ultrasonic Multiple-Access Ranging Core Based on Frequency Shift Keying Towards Indoor Localization

PubMed Central

Segers, Laurent; Van Bavegem, David; De Winne, Sam; Braeken, An; Touhafi, Abdellah; Steenhaut, Kris

2015-01-01

This paper describes a new approach and implementation methodology for indoor ranging based on the time difference of arrival using code division multiple access with ultrasound signals. A novel implementation based on a field programmable gate array using finite impulse response filters and an optimized correlation demodulator implementation for ultrasound orthogonal signals is developed. Orthogonal codes are modulated onto ultrasound signals using frequency shift keying with carrier frequencies of 24.5 kHz and 26 kHz. This implementation enhances the possibilities for real-time, embedded and low-power tracking of several simultaneous transmitters. Due to the high degree of parallelism offered by field programmable gate arrays, up to four transmitters can be tracked simultaneously. The implementation requires at most 30% of the available logic gates of a Spartan-6 XC6SLX45 device and is evaluated on accuracy and precision through several ranging topologies. In the first topology, the distance between one transmitter and one receiver is evaluated. Afterwards, ranging analyses are applied between two simultaneous transmitters and one receiver. Ultimately, the position of the receiver against four transmitters using trilateration is also demonstrated. Results show enhanced distance measurements with distances ranging from a few centimeters up to 17 m, while keeping a centimeter-level accuracy. PMID:26263986

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

NASA Astrophysics Data System (ADS)

Verma, Madhulika; Sharma, Dheeraj; Pandey, Sunil; Nigam, Kaushal; Kondekar, P. N.

2017-01-01

In this work, we perform a comparative analysis between single and dual metal dielectrically modulated tunnel field-effect transistors (DMTFETs) for the application of label free biosensor. For this purpose, two different gate material with work-function as ϕM 1 and ϕM 2 are used in short-gate DMTFET, where ϕM 1 represents the work-function of gate M1 near to the drain end, while ϕM 2 denotes the work-function of gate M2 near to the source end. A nanogap cavity in the gate dielectric is formed by removing the selected portion of gate oxide for sensing the biomolecules. To investigate the sensitivity of these biosensors, dielectric constant and charge density within the cavity region are considered as governing parameters. The work-function of gate M2 is optimized and considered less than M1 to achieve abruptness at the source/channel junction, which results in better tunneling and improved ON-state current. The ATLAS device simulations show that dual metal SG-DMTFETs attains higher ON-state current and drain current sensitivity as compared to its counterpart device. Finally, a dual metal short-gate (DSG) biosensor is compared with the single metal short-gate (SG), single metal full-gate (FG), and dual metal full-gate (DFG) biosensors to analyse structurally enhanced conjugation effect on gate-channel coupling.

Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

NASA Astrophysics Data System (ADS)

Azarbayejani, M.; Jalalpour, M.; El-Osery, A. I.; Reda Taha, M. M.

2011-08-01

In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide.

Effects Of Local Oscillator Errors On Digital Beamforming

DTIC Science & Technology

2016-03-01

processor EF element factor EW electronic warfare FFM flicker frequency modulation FOV field-of-view FPGA field-programmable gate array FPM flicker...frequencies and also more difficult to measure [15]. 2. Flicker frequency modulation The source for flicker frequency modulation ( FFM ) is attributed to...a physical resonance mechanism of an oscillator or issues controlling electronic components. Some oscillators might not show FFM noise, which might

Test Bus Evaluation

DTIC Science & Technology

1998-04-01

selected is statistically based on the total number of faults and the failure rate distribution in the system under test. The fault set is also...implemented the BPM and system level emulation consolidation logic as well as statistics counters for cache misses and various bus transactions. These...instruction F22 Advanced Tactical Fighter FET Field Effect Transitor FF Flip-Flop FM Failures/Milhon hours C-3 FPGA Field Programmable Gate Array GET

Achieving High Performance with FPGA-Based Computing

PubMed Central

Herbordt, Martin C.; VanCourt, Tom; Gu, Yongfeng; Sukhwani, Bharat; Conti, Al; Model, Josh; DiSabello, Doug

2011-01-01

Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric. PMID:21603088

Hardware-based image processing for high-speed inspection of grains

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with slight color differences and small defects on grains The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) which...

Analysis of Voltage and Current Signal Processing in a Li-ion Battery Management System

DTIC Science & Technology

2010-09-01

SUBJECT TERMS Pulsed Power, Charger, Buck Converter, Field Programmable Gate Array (FPGA), Lithium - ion Batteries 16. PRICE CODE 17. SECURITY...Congressional Research Service. July 31, 2000. [3] F. E. Filler, “A Pulsed Power System Design Using Lithium - ion Batteries and One Charger per Battery

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

DTIC Science & Technology

2004-01-01

VCSEL requires placing the array far enough as to overlap the entire footprint of the signal beam in order to record the hologram. Therefore, these...hologram that self-focuses, due to phase -conjugation, on the array of detectors in the chip. VC A 10 m m 10 mm 18mm 16mm SEL RRAY OPTICAL MEMORY LOGIC...the VCSEL array , the chip and the optical material, and the requirements they have to meet for their use in the OPGA system. Section

Using quantum process tomography to characterize decoherence in an analog electronic device

NASA Astrophysics Data System (ADS)

Ostrove, Corey; La Cour, Brian; Lanham, Andrew; Ott, Granville

The mathematical structure of a universal gate-based quantum computer can be emulated faithfully on a classical electronic device using analog signals to represent a multi-qubit state. We describe a prototype device capable of performing a programmable sequence of single-qubit and controlled two-qubit gate operations on a pair of voltage signals representing the real and imaginary parts of a two-qubit quantum state. Analog filters and true-RMS voltage measurements are used to perform unitary and measurement gate operations. We characterize the degradation of the represented quantum state with successive gate operations by formally performing quantum process tomography to estimate the equivalent decoherence channel. Experimental measurements indicate that the performance of the device may be accurately modeled as an equivalent quantum operation closely resembling a depolarizing channel with a fidelity of over 99%. This work was supported by the Office of Naval Research under Grant No. N00014-14-1-0323.

Comparing Hall Effect and Field Effect Measurements on the Same Single Nanowire.

PubMed

Hultin, Olof; Otnes, Gaute; Borgström, Magnus T; Björk, Mikael; Samuelson, Lars; Storm, Kristian

2016-01-13

We compare and discuss the two most commonly used electrical characterization techniques for nanowires (NWs). In a novel single-NW device, we combine Hall effect and back-gated and top-gated field effect measurements and quantify the carrier concentrations in a series of sulfur-doped InP NWs. The carrier concentrations from Hall effect and field effect measurements are found to correlate well when using the analysis methods described in this work. This shows that NWs can be accurately characterized with available electrical methods, an important result toward better understanding of semiconductor NW doping.

Intelligent layered nanoflare: "lab-on-a-nanoparticle" for multiple DNA logic gate operations and efficient intracellular delivery.

PubMed

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-08-07

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a "lab-on-a-nanoparticle", the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.

SRAM Based Re-programmable FPGA for Space Applications

NASA Technical Reports Server (NTRS)

Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

1999-01-01

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Motion-gated acquisition for in vivo optical imaging

PubMed Central

Gioux, Sylvain; Ashitate, Yoshitomo; Hutteman, Merlijn; Frangioni, John V.

2009-01-01

Wide-field continuous wave fluorescence imaging, fluorescence lifetime imaging, frequency domain photon migration, and spatially modulated imaging have the potential to provide quantitative measurements in vivo. However, most of these techniques have not yet been successfully translated to the clinic due to challenging environmental constraints. In many circumstances, cardiac and respiratory motion greatly impair image quality and∕or quantitative processing. To address this fundamental problem, we have developed a low-cost, field-programmable gate array–based, hardware-only gating device that delivers a phase-locked acquisition window of arbitrary delay and width that is derived from an unlimited number of pseudo-periodic and nonperiodic input signals. All device features can be controlled manually or via USB serial commands. The working range of the device spans the extremes of mouse electrocardiogram (1000 beats per minute) to human respiration (4 breaths per minute), with timing resolution ⩽0.06%, and jitter ⩽0.008%, of the input signal period. We demonstrate the performance of the gating device, including dramatic improvements in quantitative measurements, in vitro using a motion simulator and in vivo using near-infrared fluorescence angiography of beating pig heart. This gating device should help to enable the clinical translation of promising new optical imaging technologies. PMID:20059276

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

UniBoard: generic hardware for radio astronomy signal processing

NASA Astrophysics Data System (ADS)

Hargreaves, J. E.

2012-09-01

UniBoard is a generic high-performance computing platform for radio astronomy, developed as a Joint Research Activity in the RadioNet FP7 Programme. The hardware comprises eight Altera Stratix IV Field Programmable Gate Arrays (FPGAs) interconnected by a high speed transceiver mesh. Each FPGA is connected to two DDR3 memory modules and three external 10Gbps ports. In addition, a total of 128 low voltage differential input lines permit connection to external ADC cards. The DSP capability of the board exceeds 644E9 complex multiply-accumulate operations per second. The first production run of eight boards was distributed to partners in The Netherlands, France, Italy, UK, China and Korea in May 2011, with a further production runs completed in December 2011 and early 2012. The function of the board is determined by the firmware loaded into its FPGAs. Current applications include beamformers, correlators, digital receivers, RFI mitigation for pulsar astronomy, and pulsar gating and search machines The new UniBoard based correlator for the European VLBI network (EVN) uses an FX architecture with half the resources of the board devoted to station based processing: delay and phase correction and channelization, and half to the correlation function. A single UniBoard can process a 64MHz band from 32 stations, 2 polarizations, sampled at 8 bit. Adding more UniBoards can expand the total bandwidth of the correlator. The design is able to process both prerecorded and real time (eVLBI) data.

Experimental limits on the fidelity of adiabatic geometric phase gates in a single solid-state spin qubit

DOE PAGES

Zhang, Kai; Nusran, N. M.; Slezak, B. R.; ...

2016-05-17

While it is often thought that the geometric phase is less sensitive to fluctuations in the control fields, a very general feature of adiabatic Hamiltonians is the unavoidable dynamic phase that accompanies the geometric phase. The effect of control field noise during adiabatic geometric quantum gate operations has not been probed experimentally, especially in the canonical spin qubit system that is of interest for quantum information. We present measurement of the Berry phase and carry out adiabatic geometric phase gate in a single solid-state spin qubit associated with the nitrogen-vacancy center in diamond. We manipulate the spin qubit geometrically bymore » careful application of microwave radiation that creates an effective rotating magnetic field, and observe the resulting Berry phase signal via spin echo interferometry. Our results show that control field noise at frequencies higher than the spin echo clock frequency causes decay of the quantum phase, and degrades the fidelity of the geometric phase gate to the classical threshold after a few (~10) operations. This occurs in spite of the geometric nature of the state preparation, due to unavoidable dynamic contributions. In conclusion, we have carried out systematic analysis and numerical simulations to study the effects of the control field noise and imperfect driving waveforms on the quantum phase gate.« less

Experimental limits on the fidelity of adiabatic geometric phase gates in a single solid-state spin qubit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Kai; Nusran, N. M.; Slezak, B. R.

While it is often thought that the geometric phase is less sensitive to fluctuations in the control fields, a very general feature of adiabatic Hamiltonians is the unavoidable dynamic phase that accompanies the geometric phase. The effect of control field noise during adiabatic geometric quantum gate operations has not been probed experimentally, especially in the canonical spin qubit system that is of interest for quantum information. We present measurement of the Berry phase and carry out adiabatic geometric phase gate in a single solid-state spin qubit associated with the nitrogen-vacancy center in diamond. We manipulate the spin qubit geometrically bymore » careful application of microwave radiation that creates an effective rotating magnetic field, and observe the resulting Berry phase signal via spin echo interferometry. Our results show that control field noise at frequencies higher than the spin echo clock frequency causes decay of the quantum phase, and degrades the fidelity of the geometric phase gate to the classical threshold after a few (~10) operations. This occurs in spite of the geometric nature of the state preparation, due to unavoidable dynamic contributions. In conclusion, we have carried out systematic analysis and numerical simulations to study the effects of the control field noise and imperfect driving waveforms on the quantum phase gate.« less

Radiation effects in reconfigurable FPGAs

NASA Astrophysics Data System (ADS)

Quinn, Heather

2017-04-01

Field-programmable gate arrays (FPGAs) are co-processing hardware used in image and signal processing. FPGA are programmed with custom implementations of an algorithm. These algorithms are highly parallel hardware designs that are faster than software implementations. This flexibility and speed has made FPGAs attractive for many space programs that need in situ, high-speed signal processing for data categorization and data compression. Most commercial FPGAs are affected by the space radiation environment, though. Problems with TID has restricted the use of flash-based FPGAs. Static random access memory based FPGAs must be mitigated to suppress errors from single-event upsets. This paper provides a review of radiation effects issues in reconfigurable FPGAs and discusses methods for mitigating these problems. With careful design it is possible to use these components effectively and resiliently.

Error-Rate Estimation Based on Multi-Signal Flow Graph Model and Accelerated Radiation Tests

PubMed Central

Wang, Yueke; Xing, Kefei; Deng, Wei; Zhang, Zelong

2016-01-01

A method of evaluating the single-event effect soft-error vulnerability of space instruments before launched has been an active research topic in recent years. In this paper, a multi-signal flow graph model is introduced to analyze the fault diagnosis and meantime to failure (MTTF) for space instruments. A model for the system functional error rate (SFER) is proposed. In addition, an experimental method and accelerated radiation testing system for a signal processing platform based on the field programmable gate array (FPGA) is presented. Based on experimental results of different ions (O, Si, Cl, Ti) under the HI-13 Tandem Accelerator, the SFER of the signal processing platform is approximately 10−3(error/particle/cm2), while the MTTF is approximately 110.7 h. PMID:27583533

Error-Rate Estimation Based on Multi-Signal Flow Graph Model and Accelerated Radiation Tests.

PubMed

He, Wei; Wang, Yueke; Xing, Kefei; Deng, Wei; Zhang, Zelong

2016-01-01

A method of evaluating the single-event effect soft-error vulnerability of space instruments before launched has been an active research topic in recent years. In this paper, a multi-signal flow graph model is introduced to analyze the fault diagnosis and meantime to failure (MTTF) for space instruments. A model for the system functional error rate (SFER) is proposed. In addition, an experimental method and accelerated radiation testing system for a signal processing platform based on the field programmable gate array (FPGA) is presented. Based on experimental results of different ions (O, Si, Cl, Ti) under the HI-13 Tandem Accelerator, the SFER of the signal processing platform is approximately 10-3(error/particle/cm2), while the MTTF is approximately 110.7 h.

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.

PubMed

Alser, Mohammed; Hassan, Hasan; Xin, Hongyi; Ergin, Oguz; Mutlu, Onur; Alkan, Can

2017-11-01

High throughput DNA sequencing (HTS) technologies generate an excessive number of small DNA segments -called short reads- that cause significant computational burden. To analyze the entire genome, each of the billions of short reads must be mapped to a reference genome based on the similarity between a read and 'candidate' locations in that reference genome. The similarity measurement, called alignment, formulated as an approximate string matching problem, is the computational bottleneck because: (i) it is implemented using quadratic-time dynamic programming algorithms and (ii) the majority of candidate locations in the reference genome do not align with a given read due to high dissimilarity. Calculating the alignment of such incorrect candidate locations consumes an overwhelming majority of a modern read mapper's execution time. Therefore, it is crucial to develop a fast and effective filter that can detect incorrect candidate locations and eliminate them before invoking computationally costly alignment algorithms. We propose GateKeeper, a new hardware accelerator that functions as a pre-alignment step that quickly filters out most incorrect candidate locations. GateKeeper is the first design to accelerate pre-alignment using Field-Programmable Gate Arrays (FPGAs), which can perform pre-alignment much faster than software. When implemented on a single FPGA chip, GateKeeper maintains high accuracy (on average >96%) while providing, on average, 90-fold and 130-fold speedup over the state-of-the-art software pre-alignment techniques, Adjacency Filter and Shifted Hamming Distance (SHD), respectively. The addition of GateKeeper as a pre-alignment step can reduce the verification time of the mrFAST mapper by a factor of 10. https://github.com/BilkentCompGen/GateKeeper. mohammedalser@bilkent.edu.tr or onur.mutlu@inf.ethz.ch or calkan@cs.bilkent.edu.tr. Supplementary data are available at Bioinformatics online. © The Author (2017). Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

An Ultra Low Cost Wireless Communications Laboratory for Education and Research

ERIC Educational Resources Information Center

Linn, Y.

2012-01-01

This paper presents an ultra-low-cost wireless communications laboratory that is based on a commercial off-the-shelf field programmable gate array (FPGA) development board that is both inexpensive and available worldwide. The total cost of the laboratory is under USD $200, but it includes complete transmission, channel emulation, reception…

Commercial Parts Radiation Testing

DTIC Science & Technology

2015-01-13

New Mexico’s COSMIAC Center performed radiation testing on a series of operational amplifiers, microcontrollers and microprocessor. The...commercial microcontroller and microprocessor equipment. The team would develop a list of the most promising commercial parts that might be utilized to...parts will include microprocessors, microcontrollers and memory modules. In addition, Field Programmable Gate Arrays (FPGAs) will also be chosen

Digital Fingerprinting of Field Programmable Gate Arrays

DTIC Science & Technology

2008-03-01

48 vii Page Appendix B . Tranistional Sampling Outputs . . . . . . . . . . . . . . 49 Appendix C. VHDL Entities...cumulative sampling outputs by pin . . . . . . . . . . . 48 B .1. FPGA outputs for Sample 0, Clk 18 . . . . . . . . . . . . . . . 49 B .2. FPGA outputs for...Sample 0, Clk 19 . . . . . . . . . . . . . . . 49 B .3. FPGA outputs for Sample 0, Clk 21 . . . . . . . . . . . . . . . 50 B .4. FPGA outputs for Sample

High altitude subsonic parachute field programmable gate array

NASA Technical Reports Server (NTRS)

Kowalski, James E.; Gromov, Konstantin; Konefat, Edward H.

2005-01-01

This paper describes a rapid, top down requirements-driven design of an FPGA used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and control storage of telemetry data from multiple sensors throughout; launch, ascent, deployment and descent phases of the subsonic parachute test.

Design for Review - Applying Lessons Learned to Improve the FPGA Review Process

NASA Technical Reports Server (NTRS)

Figueiredo, Marco A.; Li, Kenneth E.

2014-01-01

Flight Field Programmable Gate Array (FPGA) designs are required to be independently reviewed. This paper provides recommendations to Flight FPGA designers to properly prepare their designs for review in order to facilitate the review process, and reduce the impact of the review time in the overall project schedule.

Topological horseshoe analysis and field-programmable gate array implementation of a fractional-order four-wing chaotic attractor

NASA Astrophysics Data System (ADS)

Dong, En-Zeng; Wang, Zhen; Yu, Xiao; Chen, Zeng-Qiang; Wang, Zeng-Hui

2018-01-01

Not Available Project supported by the National Natural Science Foundation of China (Grant Nos. 61502340 and 61374169), the Application Base and Frontier Technology Research Project of Tianjin, China (Grant No. 15JCYBJC51800), and the South African National Research Foundation Incentive Grants (Grant No. 81705).

An Intelligent Architecture Based on Field Programmable Gate Arrays Designed to Detect Moving Objects by Using Principal Component Analysis

PubMed Central

Bravo, Ignacio; Mazo, Manuel; Lázaro, José L.; Gardel, Alfredo; Jiménez, Pedro; Pizarro, Daniel

2010-01-01

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices. PMID:22163406

An intelligent architecture based on Field Programmable Gate Arrays designed to detect moving objects by using Principal Component Analysis.

PubMed

Bravo, Ignacio; Mazo, Manuel; Lázaro, José L; Gardel, Alfredo; Jiménez, Pedro; Pizarro, Daniel

2010-01-01

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices.

In-situ Testing of the EHT High Gain and Frequency Ultra-Stable Integrators

NASA Astrophysics Data System (ADS)

Miller, Kenneth; Ziemba, Timothy; Prager, James; Slobodov, Ilia; Lotz, Dan

2014-10-01

Eagle Harbor Technologies (EHT) has developed a long-pulse integrator that exceeds the ITER specification for integration error and pulse duration. During the Phase I program, EHT improved the RPPL short-pulse integrators, added a fast digital reset, and demonstrated that the new integrators exceed the ITER integration error and pulse duration requirements. In Phase II, EHT developed Field Programmable Gate Array (FPGA) software that allows for integrator control and real-time signal digitization and processing. In the second year of Phase II, the EHT integrator will be tested at a validation platform experiment (HIT-SI) and tokamak (DIII-D). In the Phase IIB program, EHT will continue development of the EHT integrator to reduce overall cost per channel. EHT will test lower cost components, move to surface mount components, and add an onboard Field Programmable Gate Array and data acquisition to produce a stand-alone system with lower cost per channel and increased the channel density. EHT will test the Phase IIB integrator at a validation platform experiment (HIT-SI) and tokamak (DIII-D). Work supported by the DOE under Contract Number (DE-SC0006281).

The discrete Fourier transform algorithm for determining decay constants—Implementation using a field programmable gate array

NASA Astrophysics Data System (ADS)

Bostrom, G.; Atkinson, D.; Rice, A.

2015-04-01

Cavity ringdown spectroscopy (CRDS) uses the exponential decay constant of light exiting a high-finesse resonance cavity to determine analyte concentration, typically via absorption. We present a high-throughput data acquisition system that determines the decay constant in near real time using the discrete Fourier transform algorithm on a field programmable gate array (FPGA). A commercially available, high-speed, high-resolution, analog-to-digital converter evaluation board system is used as the platform for the system, after minor hardware and software modifications. The system outputs decay constants at maximum rate of 4.4 kHz using an 8192-point fast Fourier transform by processing the intensity decay signal between ringdown events. We present the details of the system, including the modifications required to adapt the evaluation board to accurately process the exponential waveform. We also demonstrate the performance of the system, both stand-alone and incorporated into our existing CRDS system. Details of FPGA, microcontroller, and circuitry modifications are provided in the Appendix and computer code is available upon request from the authors.

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

NASA Astrophysics Data System (ADS)

Chen, Yuan-Ho

2017-05-01

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [-0.54, 0.24] and [-0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Case for a field-programmable gate array multicore hybrid machine for an image-processing application

NASA Astrophysics Data System (ADS)

Rakvic, Ryan N.; Ives, Robert W.; Lira, Javier; Molina, Carlos

2011-01-01

General purpose computer designers have recently begun adding cores to their processors in order to increase performance. For example, Intel has adopted a homogeneous quad-core processor as a base for general purpose computing. PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high level. Can modern image-processing algorithms utilize these additional cores? On the other hand, modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have created an interesting question for general purpose computer designers. Is there a reason to combine FPGAs with multicore processors to create an FPGA multicore hybrid general purpose computer? Iris matching, a repeatedly executed portion of a modern iris-recognition algorithm, is parallelized on an Intel-based homogeneous multicore Xeon system, a heterogeneous multicore Cell system, and an FPGA multicore hybrid system. Surprisingly, the cheaper PS3 slightly outperforms the Intel-based multicore on a core-for-core basis. However, both multicore systems are beaten by the FPGA multicore hybrid system by >50%.

Modular design and implementation of field-programmable-gate-array-based Gaussian noise generator

NASA Astrophysics Data System (ADS)

Li, Yuan-Ping; Lee, Ta-Sung; Hwang, Jeng-Kuang

2016-05-01

The modular design of a Gaussian noise generator (GNG) based on field-programmable gate array (FPGA) technology was studied. A new range reduction architecture was included in a series of elementary function evaluation modules and was integrated into the GNG system. The approximation and quantisation errors for the square root module with a first polynomial approximation were high; therefore, we used the central limit theorem (CLT) to improve the noise quality. This resulted in an output rate of one sample per clock cycle. We subsequently applied Newton's method for the square root module, thus eliminating the need for the use of the CLT because applying the CLT resulted in an output rate of two samples per clock cycle (>200 million samples per second). Two statistical tests confirmed that our GNG is of high quality. Furthermore, the range reduction, which is used to solve a limited interval of the function approximation algorithms of the System Generator platform using Xilinx FPGAs, appeared to have a higher numerical accuracy, was operated at >350 MHz, and can be suitably applied for any function evaluation.

Implementing universal nonadiabatic holonomic quantum gates with transmons

NASA Astrophysics Data System (ADS)

Hong, Zhuo-Ping; Liu, Bao-Jie; Cai, Jia-Qi; Zhang, Xin-Ding; Hu, Yong; Wang, Z. D.; Xue, Zheng-Yuan

2018-02-01

Geometric phases are well known to be noise resilient in quantum evolutions and operations. Holonomic quantum gates provide us with a robust way towards universal quantum computation, as these quantum gates are actually induced by non-Abelian geometric phases. Here we propose and elaborate how to efficiently implement universal nonadiabatic holonomic quantum gates on simpler superconducting circuits, with a single transmon serving as a qubit. In our proposal, an arbitrary single-qubit holonomic gate can be realized in a single-loop scenario by varying the amplitudes and phase difference of two microwave fields resonantly coupled to a transmon, while nontrivial two-qubit holonomic gates may be generated with a transmission-line resonator being simultaneously coupled to the two target transmons in an effective resonant way. Moreover, our scenario may readily be scaled up to a two-dimensional lattice configuration, which is able to support large scalable quantum computation, paving the way for practically implementing universal nonadiabatic holonomic quantum computation with superconducting circuits.

Capacitance of graphenes

NASA Astrophysics Data System (ADS)

Young, Andrea; Dean, Cory; Meric, Inanc; Hone, Jim; Shepard, Ken; Kim, Philip

2010-03-01

Using a transfer procedure and single crystal hexagonal Boron Nitride gate dielectric, we are able to fabricate high mobility graphene devices with local top and back gates. The novel geometry of these devices allows us to measure the spatially averaged compressibility of mono- and bilayer graphene using the ``penetration field'' technique [Eisenstein, J.P. et al. Phys. Rev. Lett. 68, 674 (1992)]. In particular, we analyze the the effects of strong transverse electric fields on the compressibility of graphenes, especially as pertains to charged impurity scattering in single layer graphene and the opening of an energy gap in bilayer.

Assurance of Complex Electronics. What Path Do We Take?

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

Universal electronics for miniature and automated chemical assays.

PubMed

Urban, Pawel L

2015-02-21

This minireview discusses universal electronic modules (generic programmable units) and their use by analytical chemists to construct inexpensive, miniature or automated devices. Recently, open-source platforms have gained considerable popularity among tech-savvy chemists because their implementation often does not require expert knowledge and investment of funds. Thus, chemistry students and researchers can easily start implementing them after a few hours of reading tutorials and trial-and-error. Single-board microcontrollers and micro-computers such as Arduino, Teensy, Raspberry Pi or BeagleBone enable collecting experimental data with high precision as well as efficient control of electric potentials and actuation of mechanical systems. They are readily programmed using high-level languages, such as C, C++, JavaScript or Python. They can also be coupled with mobile consumer electronics, including smartphones as well as teleinformatic networks. More demanding analytical tasks require fast signal processing. Field-programmable gate arrays enable efficient and inexpensive prototyping of high-performance analytical platforms, thus becoming increasingly popular among analytical chemists. This minireview discusses the advantages and drawbacks of universal electronic modules, considering their application in prototyping and manufacture of intelligent analytical instrumentation.

A high-resolution programmable Vernier delay generator based on carry chains in FPGA

NASA Astrophysics Data System (ADS)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 2 0°C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

Fault-Tolerant Software-Defined Radio on Manycore

NASA Technical Reports Server (NTRS)

Ricketts, Scott

2015-01-01

Software-defined radio (SDR) platforms generally rely on field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), but such architectures require significant software development. In addition, application demands for radiation mitigation and fault tolerance exacerbate programming challenges. MaXentric Technologies, LLC, has developed a manycore-based SDR technology that provides 100 times the throughput of conventional radiationhardened general purpose processors. Manycore systems (30-100 cores and beyond) have the potential to provide high processing performance at error rates that are equivalent to current space-deployed uniprocessor systems. MaXentric's innovation is a highly flexible radio, providing over-the-air reconfiguration; adaptability; and uninterrupted, real-time, multimode operation. The technology is also compliant with NASA's Space Telecommunications Radio System (STRS) architecture. In addition to its many uses within NASA communications, the SDR can also serve as a highly programmable research-stage prototyping device for new waveforms and other communications technologies. It can also support noncommunication codes on its multicore processor, collocated with the communications workload-reducing the size, weight, and power of the overall system by aggregating processing jobs to a single board computer.

Technology Developments in Radiation-Hardened Electronics for Space Environments

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Howell, Joe T.

2008-01-01

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS, Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches. System level applications for the RHESE technology products are discussed.

Programmable DNA switches and their applications.

PubMed

Harroun, Scott G; Prévost-Tremblay, Carl; Lauzon, Dominic; Desrosiers, Arnaud; Wang, Xiaomeng; Pedro, Liliana; Vallée-Bélisle, Alexis

2018-03-08

DNA switches are ideally suited for numerous nanotechnological applications, and increasing efforts are being directed toward their engineering. In this review, we discuss how to engineer these switches starting from the selection of a specific DNA-based recognition element, to its adaptation and optimisation into a switch, with applications ranging from sensing to drug delivery, smart materials, molecular transporters, logic gates and others. We provide many examples showcasing their high programmability and recent advances towards their real life applications. We conclude with a short perspective on this exciting emerging field.

Design and implementation of the NaI(Tl)/CsI(Na) detectors output signal generator

NASA Astrophysics Data System (ADS)

Zhou, Xu; Liu, Cong-Zhan; Zhao, Jian-Ling; Zhang, Fei; Zhang, Yi-Fei; Li, Zheng-Wei; Zhang, Shuo; Li, Xu-Fang; Lu, Xue-Feng; Xu, Zhen-Ling; Lu, Fang-Jun

2014-02-01

We designed and implemented a signal generator that can simulate the output of the NaI(Tl)/CsI(Na) detectors' pre-amplifier onboard the Hard X-ray Modulation Telescope (HXMT). Using the development of the FPGA (Field Programmable Gate Array) with VHDL language and adding a random constituent, we have finally produced the double exponential random pulse signal generator. The statistical distribution of the signal amplitude is programmable. The occurrence time intervals of the adjacent signals contain negative exponential distribution statistically.

Single-photon three-qubit quantum logic using spatial light modulators.

PubMed

Kagalwala, Kumel H; Di Giuseppe, Giovanni; Abouraddy, Ayman F; Saleh, Bahaa E A

2017-09-29

The information-carrying capacity of a single photon can be vastly expanded by exploiting its multiple degrees of freedom: spatial, temporal, and polarization. Although multiple qubits can be encoded per photon, to date only two-qubit single-photon quantum operations have been realized. Here, we report an experimental demonstration of three-qubit single-photon, linear, deterministic quantum gates that exploit photon polarization and the two-dimensional spatial-parity-symmetry of the transverse single-photon field. These gates are implemented using a polarization-sensitive spatial light modulator that provides a robust, non-interferometric, versatile platform for implementing controlled unitary gates. Polarization here represents the control qubit for either separable or entangling unitary operations on the two spatial-parity target qubits. Such gates help generate maximally entangled three-qubit Greenberger-Horne-Zeilinger and W states, which is confirmed by tomographical reconstruction of single-photon density matrices. This strategy provides access to a wide range of three-qubit states and operations for use in few-qubit quantum information processing protocols.Photons are essential for quantum information processing, but to date only two-qubit single-photon operations have been realized. Here the authors demonstrate experimentally a three-qubit single-photon linear deterministic quantum gate by exploiting polarization along with spatial-parity symmetry.

STM studies of an atomic-scale gate electrode formed by a single charged vacancy in GaAs

NASA Astrophysics Data System (ADS)

Lee, Donghun; Daughton, David; Gupta, Jay

2009-03-01

Electric-field control of spin-spin interactions at the atomic level is desirable for the realization of spintronics and spin-based quantum computation. Here we demonstrate the realization of an atomic-scale gate electrode formed by a single charged vacancy on the GaAs(110) surface[1]. We can position these vacancies with atomic precision using the tip of a home-built, low temperature STM. Tunneling spectroscopy of single Mn acceptors is used to quantify the electrostatic field as a function of distance from the vacancy. Single Mn acceptors are formed by substituting Mn adatoms for Ga atoms in the first layer of the p-GaAs(110) surface[2]. Depending on the distance, the in-gap resonance of single Mn acceptors can shift as much as 200meV. Our data indicate that the electrostatic field decays according to a screened Coulomb potential. The charge state of the vacancy can be switched to neutral, as evidenced by the Mn resonance returning to its unperturbed position. Reversible control of the local electric field as well as charged states of defects in semiconductors can open new insights such as realizing an atomic-scale gate control and studying spin-spin interactions in semiconductors. http://www.physics.ohio-state.edu/sim jgupta [1] D. Lee and J.A. Gupta (in preparation) [2] D. Kitchen et al., Nature 442, 436-439 (2006)

Operation of a gated field emitter using an individual carbon nanofiber cathode

NASA Astrophysics Data System (ADS)

Guillorn, M. A.; Melechko, A. V.; Merkulov, V. I.; Ellis, E. D.; Britton, C. L.; Simpson, M. L.; Lowndes, D. H.; Baylor, L. R.

2001-11-01

We report on the operation of an integrated gated cathode device using a single vertically aligned carbon nanofiber as the field emission element. This device is capable of operation in a moderate vacuum for extended periods of time without experiencing a degradation of performance. Less than 1% of the total emitted current is collected by the gate electrode, indicating that the emitted electron beam is highly collimated. As a consequence, this device is ideal for applications that require well-focused electron emission from a microscale structure.

FPGA-Based Filterbank Implementation for Parallel Digital Signal Processing

NASA Technical Reports Server (NTRS)

Berner, Stephan; DeLeon, Phillip

1999-01-01

One approach to parallel digital signal processing decomposes a high bandwidth signal into multiple lower bandwidth (rate) signals by an analysis bank. After processing, the subband signals are recombined into a fullband output signal by a synthesis bank. This paper describes an implementation of the analysis and synthesis banks using (Field Programmable Gate Arrays) FPGAs.

A Field Programmable Gate Array Based Software Defined Radio Design for the Space Environment

DTIC Science & Technology

2009-12-01

CHANGING PARAMETERS ......................................................................97 APPENDIX B. ADDITIONAL APPLICATIONS ...Professor Frank Kragh was inspirational and always provided keen insight into the mathematics of signal analysis. Special thanks to Professor...and risk involved with launching a new satellite. [2] An FPGA design with potential for space applications was presented in [3]. This initial SDR

Single-shot terahertz time-domain spectroscopy in pulsed high magnetic fields.

PubMed

Noe, G Timothy; Katayama, Ikufumi; Katsutani, Fumiya; Allred, James J; Horowitz, Jeffrey A; Sullivan, David M; Zhang, Qi; Sekiguchi, Fumiya; Woods, Gary L; Hoffmann, Matthias C; Nojiri, Hiroyuki; Takeda, Jun; Kono, Junichiro

2016-12-26

We have developed a single-shot terahertz time-domain spectrometer to perform optical-pump/terahertz-probe experiments in pulsed, high magnetic fields up to 30 T. The single-shot detection scheme for measuring a terahertz waveform incorporates a reflective echelon to create time-delayed beamlets across the intensity profile of the optical gate beam before it spatially and temporally overlaps with the terahertz radiation in a ZnTe detection crystal. After imaging the gate beam onto a camera, we can retrieve the terahertz time-domain waveform by analyzing the resulting image. To demonstrate the utility of our technique, we measured cyclotron resonance absorption of optically excited carriers in the terahertz frequency range in intrinsic silicon at high magnetic fields, with results that agree well with published values.

Real-time implementation of a multispectral mine target detection algorithm

NASA Astrophysics Data System (ADS)

Samson, Joseph W.; Witter, Lester J.; Kenton, Arthur C.; Holloway, John H., Jr.

2003-09-01

Spatial-spectral anomaly detection (the "RX Algorithm") has been exploited on the USMC's Coastal Battlefield Reconnaissance and Analysis (COBRA) Advanced Technology Demonstration (ATD) and several associated technology base studies, and has been found to be a useful method for the automated detection of surface-emplaced antitank land mines in airborne multispectral imagery. RX is a complex image processing algorithm that involves the direct spatial convolution of a target/background mask template over each multispectral image, coupled with a spatially variant background spectral covariance matrix estimation and inversion. The RX throughput on the ATD was about 38X real time using a single Sun UltraSparc system. A goal to demonstrate RX in real-time was begun in FY01. We now report the development and demonstration of a Field Programmable Gate Array (FPGA) solution that achieves a real-time implementation of the RX algorithm at video rates using COBRA ATD data. The approach uses an Annapolis Microsystems Firebird PMC card containing a Xilinx XCV2000E FPGA with over 2,500,000 logic gates and 18MBytes of memory. A prototype system was configured using a Tek Microsystems VME board with dual-PowerPC G4 processors and two PMC slots. The RX algorithm was translated from its C programming implementation into the VHDL language and synthesized into gates that were loaded into the FPGA. The VHDL/synthesizer approach allows key RX parameters to be quickly changed and a new implementation automatically generated. Reprogramming the FPGA is done rapidly and in-circuit. Implementation of the RX algorithm in a single FPGA is a major first step toward achieving real-time land mine detection.

Electrofluidics in Micro/Nanofluidic Systems

NASA Astrophysics Data System (ADS)

Guan, Weihua

This work presents the efforts to study the electrofluidics, with a focus on the electric field - matter interactions in microfluidic and nanofluidic systems for lab-on-a-chip applications. The field of electrofluidics integrates the multidisciplinary knowledge in silicon technology, solid and soft condensed matter physics, fluidics, electrochemistry, and electronics. The fundamental understanding of electrofluidics in engineered micro and nano structures opens up wide opportunities for biomedical sensing and actuation devices integrated on a single chip. Using spatial and temporal properties of electric fields in top-down engineered micro/nana structures, we successfully demonstrated the precise control over a single macro-ion and a collective group of ions in aqueous solutions. In the manipulation of a single macro-ion, we revisited the long-time overlooked AC electrophoretic (ACEP) phenomena. We proved that the widely held notion of vanishing electrophoretic (EP) effects in AC fields does not apply to spatially non-uniform electric fields. In contrast to dielectrophoretic (DEP) traps, ACEP traps favor the downscaling of the particle size if it is sufficiently charged. We experimentally demonstrated the predicted ACEP trap by recognizing that the ACEP dynamics is equivalent to that of Paul traps working in an aqueous solution. Since all Paul traps realized so far have only been operated in vacuum or gaseous phase, our experimental effort represents the world's first aqueous Paul trap device. In the manipulation of a collective group of ions, we demonstrated that the ion transport in nanochannels can be directly gated by DC electric fields, an impossible property in microscale geometries. Successful fabrication techniques were developed to create the nanochannel structures with gating ability. Using the gated nanochannel structures, we demonstrated a field effect reconfigurable nanofluidic diode, whose forward/reverse direction as well as the rectification degree can be significantly modulated. We also demonstrated a solid-state protocell, whose ion selectivity and membrane potential can be modulated by external electric field. Moreover, by recognizing the key role played by the surface charge density in electrofluidic gating of nanochannels, a low-cost, off-chip extended gate field effect transistor (FET) structure to measure the surface charges at the dielectric-electrolyte interface is demonstrated. This technique simplifies and accelerates the process of dielectric selection for effective electrofluidic gating.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Field-programmable beam reconfiguring based on digitally-controlled coding metasurface

NASA Astrophysics Data System (ADS)

Wan, Xiang; Qi, Mei Qing; Chen, Tian Yi; Cui, Tie Jun

2016-02-01

Digital phase shifters have been applied in traditional phased array antennas to realize beam steering. However, the phase shifter deals with the phase of the induced current; hence, it has to be in the path of each element of the antenna array, making the phased array antennas very expensive. Metamaterials and/or metasurfaces enable the direct modulation of electromagnetic waves by designing subwavelength structures, which opens a new way to control the beam scanning. Here, we present a direct digital mechanism to control the scattered electromagnetic waves using coding metasurface, in which each unit cell loads a pin diode to produce binary coding states of “1” and “0”. Through data lines, the instant communications are established between the coding metasurface and the internal memory of field-programmable gate arrays (FPGA). Thus, we realize the digital modulation of electromagnetic waves, from which we present the field-programmable reflective antenna with good measurement performance. The proposed mechanism and functional device have great application potential in new-concept radar and communication systems.

Parallel Transport Quantum Logic Gates with Trapped Ions.

PubMed

de Clercq, Ludwig E; Lo, Hsiang-Yu; Marinelli, Matteo; Nadlinger, David; Oswald, Robin; Negnevitsky, Vlad; Kienzler, Daniel; Keitch, Ben; Home, Jonathan P

2016-02-26

We demonstrate single-qubit operations by transporting a beryllium ion with a controlled velocity through a stationary laser beam. We use these to perform coherent sequences of quantum operations, and to perform parallel quantum logic gates on two ions in different processing zones of a multiplexed ion trap chip using a single recycled laser beam. For the latter, we demonstrate individually addressed single-qubit gates by local control of the speed of each ion. The fidelities we observe are consistent with operations performed using standard methods involving static ions and pulsed laser fields. This work therefore provides a path to scalable ion trap quantum computing with reduced requirements on the optical control complexity.

Leakage and field emission in side-gate graphene field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current densitymore » as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.« less

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

PubMed

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-27

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

NASA Astrophysics Data System (ADS)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Single Event Effects (SEE) for Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie

2011-01-01

Single-event gate rupture (SEGR) continues to be a key failure mode in power MOSFETs. (1) SEGR is complex, making rate prediction difficult SEGR mechanism has two main components: (1) Oxide damage-- Reduces field required for rupture (2) Epilayer response -- Creates transient high field across the oxide.

A programmable five qubit quantum computer using trapped atomic ions

NASA Astrophysics Data System (ADS)

Debnath, Shantanu

2017-04-01

In order to harness the power of quantum information processing, several candidate systems have been investigated, and tailored to demonstrate only specific computations. In my thesis work, we construct a general-purpose multi-qubit device using a linear chain of trapped ion qubits, which in principle can be programmed to run any quantum algorithm. To achieve such flexibility, we develop a pulse shaping technique to realize a set of fully connected two-qubit rotations that entangle arbitrary pairs of qubits using multiple motional modes of the chain. Following a computation architecture, such highly expressive two-qubit gates along with arbitrary single-qubit rotations can be used to compile modular universal logic gates that are effected by targeted optical fields and hence can be reconfigured according to any algorithm circuit programmed in the software. As a demonstration, we run the Deutsch-Jozsa and Bernstein-Vazirani algorithm, and a fully coherent quantum Fourier transform, that we use to solve the `period finding' and `quantum phase estimation' problem. Combining these results with recent demonstrations of quantum fault-tolerance, Grover's search algorithm, and simulation of boson hopping establishes the versatility of such a computation module that can potentially be connected to other modules for future large-scale computations.

A programmable controller based on CAN field bus embedded microprocessor and FPGA

NASA Astrophysics Data System (ADS)

Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

2008-10-01

One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Wirthlin, Michael

A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA inmore » a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this study we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.« less

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

NASA Technical Reports Server (NTRS)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

Flexible digital signal processing architecture for narrowband and spread-spectrum lock-in detection in multiphoton microscopy and time-resolved spectroscopy

PubMed Central

Wilson, Jesse W.; Park, Jong Kang; Warren, Warren S.

2015-01-01

The lock-in amplifier is a critical component in many different types of experiments, because of its ability to reduce spurious or environmental noise components by restricting detection to a single frequency and phase. One example application is pump-probe microscopy, a multiphoton technique that leverages excited-state dynamics for imaging contrast. With this application in mind, we present here the design and implementation of a high-speed lock-in amplifier on the field-programmable gate array (FPGA) coprocessor of a data acquisition board. The most important advantage is the inherent ability to filter signals based on more complex modulation patterns. As an example, we use the flexibility of the FPGA approach to enable a novel pump-probe detection scheme based on spread-spectrum communications techniques. PMID:25832238

Flexible digital signal processing architecture for narrowband and spread-spectrum lock-in detection in multiphoton microscopy and time-resolved spectroscopy.

PubMed

Wilson, Jesse W; Park, Jong Kang; Warren, Warren S; Fischer, Martin C

2015-03-01

The lock-in amplifier is a critical component in many different types of experiments, because of its ability to reduce spurious or environmental noise components by restricting detection to a single frequency and phase. One example application is pump-probe microscopy, a multiphoton technique that leverages excited-state dynamics for imaging contrast. With this application in mind, we present here the design and implementation of a high-speed lock-in amplifier on the field-programmable gate array (FPGA) coprocessor of a data acquisition board. The most important advantage is the inherent ability to filter signals based on more complex modulation patterns. As an example, we use the flexibility of the FPGA approach to enable a novel pump-probe detection scheme based on spread-spectrum communications techniques.

Double optical gating of high-order harmonic generation with carrier-envelope phase stabilized lasers.

PubMed

Mashiko, Hiroki; Gilbertson, Steve; Li, Chengquan; Khan, Sabih D; Shakya, Mahendra M; Moon, Eric; Chang, Zenghu

2008-03-14

We demonstrated a novel optical switch to control the high-order harmonic generation process so that single attosecond pulses can be generated with multiple-cycle pulses. The technique combines two powerful optical gating methods: polarization gating and two-color gating. An extreme ultraviolet supercontinuum supporting 130 as was generated with neon gas using 9 fs laser pulses. We discovered a unique dependence of the harmonic spectra on the carrier-envelope phase of the laser fields, which repeats every 2 pi radians.

Double Optical Gating of High-Order Harmonic Generation with Carrier-Envelope Phase Stabilized Lasers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mashiko, Hiroki; Gilbertson, Steve; Li, Chengquan

2008-03-14

We demonstrated a novel optical switch to control the high-order harmonic generation process so that single attosecond pulses can be generated with multiple-cycle pulses. The technique combines two powerful optical gating methods: polarization gating and two-color gating. An extreme ultraviolet supercontinuum supporting 130 as was generated with neon gas using 9 fs laser pulses. We discovered a unique dependence of the harmonic spectra on the carrier-envelope phase of the laser fields, which repeats every 2{pi} radians.

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

On the use of programmable hardware and reduced numerical precision in earth-system modeling.

PubMed

Düben, Peter D; Russell, Francis P; Niu, Xinyu; Luk, Wayne; Palmer, T N

2015-09-01

Programmable hardware, in particular Field Programmable Gate Arrays (FPGAs), promises a significant increase in computational performance for simulations in geophysical fluid dynamics compared with CPUs of similar power consumption. FPGAs allow adjusting the representation of floating-point numbers to specific application needs. We analyze the performance-precision trade-off on FPGA hardware for the two-scale Lorenz '95 model. We scale the size of this toy model to that of a high-performance computing application in order to make meaningful performance tests. We identify the minimal level of precision at which changes in model results are not significant compared with a maximal precision version of the model and find that this level is very similar for cases where the model is integrated for very short or long intervals. It is therefore a useful approach to investigate model errors due to rounding errors for very short simulations (e.g., 50 time steps) to obtain a range for the level of precision that can be used in expensive long-term simulations. We also show that an approach to reduce precision with increasing forecast time, when model errors are already accumulated, is very promising. We show that a speed-up of 1.9 times is possible in comparison to FPGA simulations in single precision if precision is reduced with no strong change in model error. The single-precision FPGA setup shows a speed-up of 2.8 times in comparison to our model implementation on two 6-core CPUs for large model setups.

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Single-shot terahertz time-domain spectroscopy in pulsed high magnetic fields

DOE Office of Scientific and Technical Information (OSTI.GOV)

Noe, II, G. Timothy; Katayama, Ikufumi; Katsutani, Fumiya

Here, we have developed a single-shot terahertz time-domain spectrometer to perform optical-pump/terahertz-probe experiments in pulsed, high magnetic fields up to 30 T. The single-shot detection scheme for measuring a terahertz waveform incorporates a reflective echelon to create time-delayed beamlets across the intensity profile of the optical gate beam before it spatially and temporally overlaps with the terahertz radiation in a ZnTe detection crystal. After imaging the gate beam onto a camera, we can retrieve the terahertz time-domain waveform by analyzing the resulting image. To demonstrate the utility of our technique, we measured cyclotron resonance absorption of optically excited carriers inmore » the terahertz frequency range in intrinsic silicon at high magnetic fields, with results that agree well with published values.« less

Single-shot terahertz time-domain spectroscopy in pulsed high magnetic fields

DOE PAGES

Noe, II, G. Timothy; Katayama, Ikufumi; Katsutani, Fumiya; ...

2016-12-22

Here, we have developed a single-shot terahertz time-domain spectrometer to perform optical-pump/terahertz-probe experiments in pulsed, high magnetic fields up to 30 T. The single-shot detection scheme for measuring a terahertz waveform incorporates a reflective echelon to create time-delayed beamlets across the intensity profile of the optical gate beam before it spatially and temporally overlaps with the terahertz radiation in a ZnTe detection crystal. After imaging the gate beam onto a camera, we can retrieve the terahertz time-domain waveform by analyzing the resulting image. To demonstrate the utility of our technique, we measured cyclotron resonance absorption of optically excited carriers inmore » the terahertz frequency range in intrinsic silicon at high magnetic fields, with results that agree well with published values.« less

Optical π phase shift created with a single-photon pulse.

PubMed

Tiarks, Daniel; Schmidt, Steffen; Rempe, Gerhard; Dürr, Stephan

2016-04-01

A deterministic photon-photon quantum logic gate is a long-standing goal. Building such a gate becomes possible if a light pulse containing only one photon imprints a phase shift of π onto another light field. We experimentally demonstrate the generation of such a π phase shift with a single-photon pulse. A first light pulse containing less than one photon on average is stored in an atomic gas. Rydberg blockade combined with electromagnetically induced transparency creates a phase shift for a second light pulse, which propagates through the medium. We measure the π phase shift of the second pulse when we postselect the data upon the detection of a retrieved photon from the first pulse. This demonstrates a crucial step toward a photon-photon gate and offers a variety of applications in the field of quantum information processing.

Proposal for quantum gates in permanently coupled antiferromagnetic spin rings without need of local fields.

PubMed

Troiani, Filippo; Affronte, Marco; Carretta, Stefano; Santini, Paolo; Amoretti, Giuseppe

2005-05-20

We propose a scheme for the implementation of quantum gates which is based on the qubit encoding in antiferromagnetic molecular rings. We show that a proper engineering of the intercluster link would result in an effective coupling that vanishes as far as the system is kept in the computational space, while it is turned on by a selective excitation of specific auxiliary states. These are also shown to allow the performing of single-qubit and two-qubit gates without an individual addressing of the rings by means of local magnetic fields.

Rad-Hard Structured ASIC Body of Knowledge

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Implementation and Optimization of the Advanced Encryption Standard Algorithm on all 8-Bit Field Programmable Gate Array Hardware Platform

DTIC Science & Technology

2007-03-01

01101101 " => data...3401101010" => inv_data := Xං" when �" => inv_data := X്" when �" => inv_data := X"b8" when " 01101101 " => inv_data := X"b3...3400110011" when " 01101101 " => data := �" when �" => data := �" when �" => data := �"

Reduced Precision Redundancy Applied to Arithmetic Operations in Field Programmable Gate Arrays for Satellite Control and Sensor Systems

DTIC Science & Technology

2008-12-01

Figure 2. Definition of Attitude Angles and Torque Components in Spacecraft Reference Frame...Figure 5. PD controller in ideal three-axis-stabilized spacecraft ADCS. ................................16 Figure 6. Extract Position Angles function in...performance of spacecraft systems. Two categories of system architectures are discussed: recursive data management, found in feedback control systems; and

Pipelined CPU Design with FPGA in Teaching Computer Architecture

ERIC Educational Resources Information Center

Lee, Jong Hyuk; Lee, Seung Eun; Yu, Heon Chang; Suh, Taeweon

2012-01-01

This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on…

Using Multiple FPGA Architectures for Real-time Processing of Low-level Machine Vision Functions

Treesearch

Thomas H. Drayer; William E. King; Philip A. Araman; Joseph G. Tront; Richard W. Conners

1995-01-01

In this paper, we investigate the use of multiple Field Programmable Gate Array (FPGA) architectures for real-time machine vision processing. The use of FPGAs for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented...

Actel Parts Usage in GSFC Projects

NASA Technical Reports Server (NTRS)

Sahu, Kusum

2006-01-01

The purpose of this paper is to provide an overview of the Actel field programmable gate array (FPGA) issues and investigations to date, provide information to GSFC parts engineers on the risks associated with the use of these parts in flight, provide procurement options for their respective projects, and provide general guidance for use of these devices if no other acceptable options exist.

Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Kyrkou, Christos; Theocharides, Theocharis

2016-07-01

Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024×768 pixels images per second with a significantly reduced number of false positives.

Theory and implementation of a very high throughput true random number generator in field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Hui, Cong; Liu, Chong

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving,more » so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.« less

Theory and implementation of a very high throughput true random number generator in field programmable gate array.

PubMed

Wang, Yonggang; Hui, Cong; Liu, Chong; Xu, Chao

2016-04-01

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

PubMed Central

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

NASA Astrophysics Data System (ADS)

Mostafa, Sheikh Shanawaz; Sousa, L. Natércia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, Joao; Wäny, Martin; Morgado-Dias, F.

2017-01-01

Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm×1 mm×1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA.

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

PubMed Central

de Souza, Alisson C. D.; Fernandes, Marcelo A. C.

2014-01-01

This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA. PMID:25268918

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Magnetics and Power System Upgrades for the Pegasus-U Experiment

NASA Astrophysics Data System (ADS)

Preston, R. C.; Bongard, M. W.; Fonck, R. J.; Lewicki, B. T.

2014-10-01

To support the missions of developing local helicity injection startup and exploiting advanced tokamak physics studies at near unity aspect ratio, the proposed Pegasus-U will include expanded magnetic systems and associated power supplies. A new centerstack increases the toroidal field seven times to 1 T and the volt-seconds by a factor of six while maintaining operation at an aspect ratio of 1.2. The poloidal field magnet system is expanded to support improved shape control and robust double or single null divertor operation at the full plasma current of 0.3 MA. An integrated digital control system based on Field Programmable Gate Arrays (FPGAs) provides active feedback control of all magnet currents. Implementation of the FPGAs is achieved with modular noise reducing electronics. The digital feedback controllers replace the existing analog systems and switch multiplexing technology. This will reduce noise sensitivity and allow the operational Ohmic power supply voltage to increase from 2100 V to its maximum capacity of 2400 V. The feedback controller replacement also allows frequency control for ``freewheeling''--stopping the switching for a short interval and allowing the current to coast. The FPGAs assist in optimizing pulse length by having programmable switching events to minimize energy losses. They also allow for more efficient switching topologies that provide improved stored energy utilization, and support increasing the pulse length from 25 ms to 50-100 ms. Work supported by US DOE Grant DE-FG02-96ER54375.

Field ionization characteristics of an ion source array for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Resnick, P. J.; Holland, C. E.; Hertz, K. L.; Chichester, D. L.

2013-11-01

A new deuterium ion source is being developed to improve the performance of existing compact neutron generators. The ion source is a microfabricated array of metal tips with an integrated gate (i.e., grid) and produces deuterium ions by field ionizing (or field desorbing) a supply of deuterium gas. Deuterium field ion currents from arrays at source temperatures of 77 K and 293 K are studied. Ion currents from single etched-wire tips operating under the same conditions are used to help understand array results. I-F characteristics of the arrays were found to follow trends similar to those of the better understood single etched-wire tip results; however, the fields achieved by the arrays are limited by electrical breakdown of the structure. Neutron production by field ionization at 293 K was demonstrated for the first time from microfabricated array structures with integrated gates.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing: Digital Timing Analysis Tools and Techniques. Articles in this issue include: SX and SX-A Series Devices Power Sequencing; JTAG and SXISX-AISX-S Series Devices; Analysis Techniques (i.e., notes on digital timing analysis tools and techniques); Status of the Radiation Hard reconfigurable Field Programmable Gate Array Program, Input Transition Times; Apollo Guidance Computer Logic Study; RT54SX32S Prototype Data Sets; A54SX32A - 0.22 micron/UMC Test Results; Ramtron FM1608 FRAM; and Analysis of VHDL Code and Synthesizer Output.

On Field-Effect Photovoltaics: Gate Enhancement of the Power Conversion Efficiency in a Nanotube/Silicon-Nanowire Solar Cell.

PubMed

Petterson, Maureen K; Lemaitre, Maxime G; Shen, Yu; Wadhwa, Pooja; Hou, Jie; Vasilyeva, Svetlana V; Kravchenko, Ivan I; Rinzler, Andrew G

2015-09-30

Recent years have seen a resurgence of interest in crystalline silicon Schottky junction solar cells distinguished by the use of low density of electronic states (DOS) nanocarbons (nanotubes, graphene) as the metal contacting the Si. Recently, unprecedented modulation of the power conversion efficiency in a single material system has been demonstrated in such cells by the use of electronic gating. The gate field induced Fermi level shift in the low-DOS carbon serves to enhance the junction built-in potential, while a gate field induced inversion layer at the Si surface, in regions remote from the junction, keeps the photocarriers well separated there, avoiding recombination at surface traps and defects (a key loss mechanism). Here, we extend these results into the third dimension of a vertical Si nanowire array solar cell. A single wall carbon nanotube layer engineered to contact virtually each n-Si nanowire tip extracts the minority carriers, while an ionic liquid electrolytic gate drives the nanowire body into inversion. The enhanced light absorption of the vertical forest cell, at 100 mW/cm(2) AM1.5G illumination, results in a short-circuit current density of 35 mA/cm(2) and associated power conversion efficiency of 15%. These results highlight the use of local fields as opposed to surface passivation as a means of avoiding front surface recombination. A deleterious electrochemical reaction of the silicon due to the electrolyte gating is shown to be caused by oxygen/water entrained in the ionic liquid electrolyte. While encapsulation can avoid the issue, a nonencapsulation-based approach is also implemented.

On Field-Effect Photovoltaics: Gate Enhancement of the Power Conversion Efficiency in a Nanotube/Silicon-Nanowire Solar Cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petterson, Maureen K.; Lemaitre, Maxime G.; Shen, Yu

Recent years have seen a resurgence of interest in crystalline silicon Schottky junction solar cells distinguished by the use of low density of electronic states (DOS) nanocarbons (nanotubes, graphene) as the metal contacting the Si. Recently, unprecedented modulation of the power conversion efficiency in a single material system has been demonstrated in such cells by the use of electronic gating. The gate field induced Fermi level shift in the low-DOS carbon serves to enhance the junction built-in potential, while a gate field induced inversion layer at the Si surface, in regions remote from the junction, keeps the photocarriers well separatedmore » there, avoiding recombination at surface traps and defects (a key loss mechanism). Here, we extend these results into the third dimension of a vertical Si nanowire array solar cell. A single wall carbon nanotube layer engineered to contact virtually each n-Si nanowire tip extracts the minority carriers, while an ionic liquid electrolytic gate drives the nanowire body into inversion. The enhanced light absorption of the vertical forest cell, at 100 mW/cm 2 AM1.5G illumination, results in a short-circuit current density of 35 mA/cm 2 and associated power conversion efficiency of 15%. These results highlight the use of local fields as opposed to surface passivation as a means of avoiding front surface recombination. Finally, a deleterious electrochemical reaction of the silicon due to the electrolyte gating is shown to be caused by oxygen/water entrained in the ionic liquid electrolyte. While encapsulation can avoid the issue, a nonencapsulation-based approach is also implemented.« less

On Field-Effect Photovoltaics: Gate Enhancement of the Power Conversion Efficiency in a Nanotube/Silicon-Nanowire Solar Cell

DOE PAGES

Petterson, Maureen K.; Lemaitre, Maxime G.; Shen, Yu; ...

2015-09-09

Recent years have seen a resurgence of interest in crystalline silicon Schottky junction solar cells distinguished by the use of low density of electronic states (DOS) nanocarbons (nanotubes, graphene) as the metal contacting the Si. Recently, unprecedented modulation of the power conversion efficiency in a single material system has been demonstrated in such cells by the use of electronic gating. The gate field induced Fermi level shift in the low-DOS carbon serves to enhance the junction built-in potential, while a gate field induced inversion layer at the Si surface, in regions remote from the junction, keeps the photocarriers well separatedmore » there, avoiding recombination at surface traps and defects (a key loss mechanism). Here, we extend these results into the third dimension of a vertical Si nanowire array solar cell. A single wall carbon nanotube layer engineered to contact virtually each n-Si nanowire tip extracts the minority carriers, while an ionic liquid electrolytic gate drives the nanowire body into inversion. The enhanced light absorption of the vertical forest cell, at 100 mW/cm 2 AM1.5G illumination, results in a short-circuit current density of 35 mA/cm 2 and associated power conversion efficiency of 15%. These results highlight the use of local fields as opposed to surface passivation as a means of avoiding front surface recombination. Finally, a deleterious electrochemical reaction of the silicon due to the electrolyte gating is shown to be caused by oxygen/water entrained in the ionic liquid electrolyte. While encapsulation can avoid the issue, a nonencapsulation-based approach is also implemented.« less

A Single Polyaniline Nanofiber Field Effect Transistor and Its Gas Sensing Mechanisms

PubMed Central

Chen, Dajing; Lei, Sheng; Chen, Yuquan

2011-01-01

A single polyaniline nanofiber field effect transistor (FET) gas sensor fabricated by means of electrospinning was investigated to understand its sensing mechanisms and optimize its performance. We studied the morphology, field effect characteristics and gas sensitivity of conductive nanofibers. The fibers showed Schottky and Ohmic contacts based on different electrode materials. Higher applied gate voltage contributes to an increase in gas sensitivity. The nanofiber transistor showed a 7% reversible resistance change to 1 ppm NH3 with 10 V gate voltage. The FET characteristics of the sensor when exposed to different gas concentrations indicate that adsorption of NH3 molecules reduces the carrier mobility in the polyaniline nanofiber. As such, nanofiber-based sensors could be promising for environmental and industrial applications. PMID:22163969

Design and implementation of digital controllers for smart structures using field-programmable gate arrays

NASA Astrophysics Data System (ADS)

Kelly, Jamie S.; Bowman, Hiroshi C.; Rao, Vittal S.; Pottinger, Hardy J.

1997-06-01

Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controllers for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost. The level of integration assumed by the Smart Patch further exacerbates these difficulties, and any design inefficiency may render the realization of a single-package sensor-controller-actuator system infeasible. The goal of this research is to automate the controller implementation process and to relieve the design engineer of implementation concerns like quantization, computational efficiency, and device selection. We specifically target Field Programmable Gate Arrays (FPGAs) as our hardware platform because these devices are highly flexible, power efficient, and reprogrammable. The current study develops an automated implementation sequence that minimizes hardware requirements while maintaining controller performance. Beginning with a state space representation of the controller, the sequence automatically generates a configuration bitstream for a suitable FPGA implementation. MATLAB functions optimize and simulate the control algorithm before translating it into the VHSIC hardware description language. These functions improve power efficiency and simplify integration in the final implementation by performing a linear transformation that renders the controller computationally friendly. The transformation favors sparse matrices in order to reduce multiply operations and the hardware necessary to support them; simultaneously, the remaining matrix elements take on values that minimize limit cycles and parameter sensitivity. The proposed controller design methodology is implemented on a simple cantilever beam test structure using FPGA hardware. The experimental closed loop response is compared with that of an automated FPGA controller implementation. Finally, we explore the integration of FPGA based controllers into a multi-chip module, which we believe represents the next step towards the realization of the Smart Patch.

Filling the Assurance Gap on Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Software Process Assurance for Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Scalable ferroelectric MOS capacitors comprised of single crystalline SrZrxTi1-xO3 on Ge.

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Xiao, Z.-Y.; Ahmadi-Majlan, K.; Grimley, E.; Ong, P. V.; Lebeau, J. M.; Chambers, S. A.; Hong, X.; Sushko, P.; Ngai, J. H.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to field-effect devices that require very little power to operate, or that possess both logic and memory functionalities. The development of metal-oxide-semiconductor (MOS) capacitors in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel is essential in order to realize such field-effect devices. Here we demonstrate that scalable, ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x = 0.7) that has been epitaxially grown on Ge. Single crystalline SrZrxTi1-xO3 exhibits characteristics that are ideal for a ferroelectric gate material, namely, a type-I band offset with respect to Ge, large coercive fields and polarization that can be enhanced with electric field. The latter characteristic stems from the relaxor nature of SrZrxTi1-xO3. These properties enable MOS capacitors with 5 nm thick SrZrxTi1-xO3 layers to exhibit a nearly 2 V wide hysteretic window in the capacitance-voltage characteristics. The realization of ferroelectric MOS capacitors with technologically relevant gate thicknesses opens the pathway to practical field effect devices. NSF DMR 1508530.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

A synchronous serial bus for multidimensional array acoustic logging tool

NASA Astrophysics Data System (ADS)

Men, Baiyong; Ju, Xiaodong; Lu, Junqiang; Qiao, Wenxiao

2016-12-01

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master-slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Determining the Best-Fit FPGA for a Space Mission: An Analysis of Cost, SEU Sensitivity,and Reliability

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Ken

2007-01-01

This viewgraph presentation reviews the selection of the optimum Field Programmable Gate Arrays (FPGA) for space missions. Included in this review is a discussion on differentiating amongst various FPGAs, cost analysis of the various options, the investigation of radiation effects, an expansion of the evaluation criteria, and the application of the evaluation criteria to the selection process.

Computing Models for FPGA-Based Accelerators

PubMed Central

Herbordt, Martin C.; Gu, Yongfeng; VanCourt, Tom; Model, Josh; Sukhwani, Bharat; Chiu, Matt

2011-01-01

Field-programmable gate arrays are widely considered as accelerators for compute-intensive applications. A critical phase of FPGA application development is finding and mapping to the appropriate computing model. FPGA computing enables models with highly flexible fine-grained parallelism and associative operations such as broadcast and collective response. Several case studies demonstrate the effectiveness of using these computing models in developing FPGA applications for molecular modeling. PMID:21603152

Performance evaluation of coherent Ising machines against classical neural networks

NASA Astrophysics Data System (ADS)

Haribara, Yoshitaka; Ishikawa, Hitoshi; Utsunomiya, Shoko; Aihara, Kazuyuki; Yamamoto, Yoshihisa

2017-12-01

The coherent Ising machine is expected to find a near-optimal solution in various combinatorial optimization problems, which has been experimentally confirmed with optical parametric oscillators and a field programmable gate array circuit. The similar mathematical models were proposed three decades ago by Hopfield et al in the context of classical neural networks. In this article, we compare the computational performance of both models.

Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture

DTIC Science & Technology

2009-08-01

Execution with Versatile, Microarchitecture-Independent Snapshots, PhD thesis, MIT, Sep 2006. [10] Bienia, Christian, Kumar , Sanjeev, Singh , Jaswinder Pal...2] Pixie: MIPS Computer Systems, Inc. Assembly Language Programmer’s Guide, 1986. [3] Agarwal, Anant , Bianchini, Ricardo, Chaiken, David, David...pp. 68–79. [49] Woo, Steven Cameron, Ohara, Moriyoshi, Torrie, Evan, Singh , Jaswinder Pal, and Gupta, Anoop, “The SPLASH-2 programs

Step-by-Step Design of an FPGA-Based Digital Compensator for DC/DC Converters Oriented to an Introductory Course

ERIC Educational Resources Information Center

Zumel, P.; Fernandez, C.; Sanz, M.; Lazaro, A.; Barrado, A.

2011-01-01

In this paper, a short introductory course to introduce field-programmable gate array (FPGA)-based digital control of dc/dc switching power converters is presented. Digital control based on specific hardware has been at the leading edge of low-medium power dc/dc switching converters in recent years. Besides industry's interest in this topic, from…

FPGA Vision Data Architecture

NASA Technical Reports Server (NTRS)

Morfopoulos, Arin C.; Pham, Thang D.

2013-01-01

JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

FPGA Boot Loader and Scrubber

NASA Technical Reports Server (NTRS)

Wade, Randall S.; Jones, Bailey

2009-01-01

A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

Applied Digital Logic Exercises Using FPGAs

NASA Astrophysics Data System (ADS)

Wick, Kurt

2017-09-01

Applied Digital Logic Exercises Using FPGAs is appropriate for anyone interested in digital logic who needs to learn how to implement it through detailed exercises with state-of-the-art digital design tools and components. The book exposes readers to combinational and sequential digital logic concepts and implements them with hands-on exercises using the Verilog Hardware Description Language (HDL) and a Field Programmable Gate Arrays (FGPA) teaching board.

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

NASA Astrophysics Data System (ADS)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

NASA Astrophysics Data System (ADS)

Walke, Richard L.; Smith, Robert W. M.; Lightbody, Gaye

2000-11-01

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Training a molecular automaton to play a game

NASA Astrophysics Data System (ADS)

Pei, Renjun; Matamoros, Elizabeth; Liu, Manhong; Stefanovic, Darko; Stojanovic, Milan N.

2010-11-01

Research at the interface between chemistry and cybernetics has led to reports of `programmable molecules', but what does it mean to say `we programmed a set of solution-phase molecules to do X'? A survey of recently implemented solution-phase circuitry indicates that this statement could be replaced with `we pre-mixed a set of molecules to do X and functional subsets of X'. These hard-wired mixtures are then exposed to a set of molecular inputs, which can be interpreted as being keyed to human moves in a game, or as assertions of logical propositions. In nucleic acids-based systems, stemming from DNA computation, these inputs can be seen as generic oligonucleotides. Here, we report using reconfigurable nucleic acid catalyst-based units to build a multipurpose reprogrammable molecular automaton that goes beyond single-purpose `hard-wired' molecular automata. The automaton covers all possible responses to two consecutive sets of four inputs (such as four first and four second moves for a generic set of trivial two-player two-move games). This is a model system for more general molecular field programmable gate array (FPGA)-like devices that can be programmed by example, which means that the operator need not have any knowledge of molecular computing methods.

Training a molecular automaton to play a game.

PubMed

Pei, Renjun; Matamoros, Elizabeth; Liu, Manhong; Stefanovic, Darko; Stojanovic, Milan N

2010-11-01

Research at the interface between chemistry and cybernetics has led to reports of 'programmable molecules', but what does it mean to say 'we programmed a set of solution-phase molecules to do X'? A survey of recently implemented solution-phase circuitry indicates that this statement could be replaced with 'we pre-mixed a set of molecules to do X and functional subsets of X'. These hard-wired mixtures are then exposed to a set of molecular inputs, which can be interpreted as being keyed to human moves in a game, or as assertions of logical propositions. In nucleic acids-based systems, stemming from DNA computation, these inputs can be seen as generic oligonucleotides. Here, we report using reconfigurable nucleic acid catalyst-based units to build a multipurpose reprogrammable molecular automaton that goes beyond single-purpose 'hard-wired' molecular automata. The automaton covers all possible responses to two consecutive sets of four inputs (such as four first and four second moves for a generic set of trivial two-player two-move games). This is a model system for more general molecular field programmable gate array (FPGA)-like devices that can be programmed by example, which means that the operator need not have any knowledge of molecular computing methods.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brusati, M.; Camplani, A.; Cannon, M.

SRAM-ba8ed Field Programmable Gate Array (FPGA) logic devices arc very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which ismore » a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. :!\\litigation techniques such as Triple Modular Redundancy (T:t\\IR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).« less

Scintillation-Hardened GPS Receiver

NASA Technical Reports Server (NTRS)

Stephens, Donald R.

2015-01-01

CommLargo, Inc., has developed a scintillation-hardened Global Positioning System (GPS) receiver that improves reliability for low-orbit missions and complies with NASA's Space Telecommunications Radio System (STRS) architecture standards. A software-defined radio (SDR) implementation allows a single hardware element to function as either a conventional radio or as a GPS receiver, providing backup and redundancy for platforms such as the International Space Station (ISS) and high-value remote sensing platforms. The innovation's flexible SDR implementation reduces cost, weight, and power requirements. Scintillation hardening improves mission reliability and variability. In Phase I, CommLargo refactored an open-source GPS software package with Kalman filter-based tracking loops to improve performance during scintillation and also demonstrated improved navigation during a geomagnetic storm. In Phase II, the company generated a new field-programmable gate array (FPGA)-based GPS waveform to demonstrate on NASA's Space Communication and Navigation (SCaN) test bed.

Real-Time Phase Correction Based on FPGA in the Beam Position and Phase Measurement System

NASA Astrophysics Data System (ADS)

Gao, Xingshun; Zhao, Lei; Liu, Jinxin; Jiang, Zouyi; Hu, Xiaofang; Liu, Shubin; An, Qi

2016-12-01

A fully digital beam position and phase measurement (BPPM) system was designed for the linear accelerator (LINAC) in Accelerator Driven Sub-critical System (ADS) in China. Phase information is obtained from the summed signals from four pick-ups of the Beam Position Monitor (BPM). Considering that the delay variations of different analog circuit channels would introduce phase measurement errors, we propose a new method to tune the digital waveforms of four channels before summation and achieve real-time error correction. The process is based on the vector rotation method and implemented within one single Field Programmable Gate Array (FPGA) device. Tests were conducted to evaluate this correction method and the results indicate that a phase correction precision better than ± 0.3° over the dynamic range from -60 dBm to 0 dBm is achieved.

Status of the RF BPM upgrade at the Advanced Photon Source.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pietryla, A.; Bui, H.; Decker, G.

2008-01-01

The Advanced Photon Source (APS),a third-generation synchrotron light source, has been in operation for eleven years. The monopulse radio frequency (rf) beam position monitor (BPM) is one of three BPM types now employed in the storage ring at the APS. It is a broadband (10 MHz) system designed to measure single-turn and multi-turn beam positions, but it suffers from an aging data acquisition system. The replacement BPM system retains the existing monopulse receivers and replaces the data acquisition system with high-speed analog-to-digital converters (ADCs) and a field-programmable gate array (FPGA) that performs the signal processing. A first-article system has beenmore » constructed and is currently being evaluated. This paper presents the results of testing of the first-article system as well as the progress made in other areas of this upgrade effort.« less

FPGA acceleration of rigid-molecule docking codes

PubMed Central

Sukhwani, B.; Herbordt, M.C.

2011-01-01

Modelling the interactions of biological molecules, or docking, is critical both to understanding basic life processes and to designing new drugs. The field programmable gate array (FPGA) based acceleration of a recently developed, complex, production docking code is described. The authors found that it is necessary to extend their previous three-dimensional (3D) correlation structure in several ways, most significantly to support simultaneous computation of several correlation functions. The result for small-molecule docking is a 100-fold speed-up of a section of the code that represents over 95% of the original run-time. An additional 2% is accelerated through a previously described method, yielding a total acceleration of 36× over a single core and 10× over a quad-core. This approach is found to be an ideal complement to graphics processing unit (GPU) based docking, which excels in the protein–protein domain. PMID:21857870

Experimental demonstration of a real-time high-throughput digital DC blocker for compensating ADC imperfections in optical fast-OFDM receivers.

PubMed

Zhang, Lu; Ouyang, Xing; Shao, Xiaopeng; Zhao, Jian

2016-06-27

Performance degradation induced by the DC components at the output of real-time analogue-to-digital converter (ADC) is experimentally investigated for optical fast-OFDM receiver. To compensate this degradation, register transfer level (RTL) circuits for real-time digital DC blocker with 20GS/s throughput are proposed and implemented in field programmable gate array (FPGA). The performance of the proposed real-time digital DC blocker is experimentally investigated in a 15Gb/s optical fast-OFDM system with intensity modulation and direct detection over 40 km standard single-mode fibre. The results show that the fixed-point DC blocker has negligible performance penalty compared to the offline floating point one, and can overcome the error floor of the fast OFDM receiver caused by the DC components from the real-time ADC output.

Validation techniques for fault emulation of SRAM-based FPGAs

DOE PAGES

Quinn, Heather; Wirthlin, Michael

2015-08-07

A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA inmore » a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this study we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.« less

An arc tangent function demodulation method of fiber-optic Fabry-Perot high-temperature pressure sensor

NASA Astrophysics Data System (ADS)

Ren, Qianyu; Li, Junhong; Hong, Yingping; Jia, Pinggang; Xiong, Jijun

2017-09-01

A new demodulation algorithm of the fiber-optic Fabry-Perot cavity length based on the phase generated carrier (PGC) is proposed in this paper, which can be applied in the high-temperature pressure sensor. This new algorithm based on arc tangent function outputs two orthogonal signals by utilizing an optical system, which is designed based on the field-programmable gate array (FPGA) to overcome the range limit of the original PGC arc tangent function demodulation algorithm. The simulation and analysis are also carried on. According to the analysis of demodulation speed and precision, the simulation of different numbers of sampling points, and measurement results of the pressure sensor, the arc tangent function demodulation method has good demodulation results: 1 MHz processing speed of single data and less than 1% error showing practical feasibility in the fiber-optic Fabry-Perot cavity length demodulation of the Fabry-Perot high-temperature pressure sensor.

Chaos Through-Wall Imaging Radar

NASA Astrophysics Data System (ADS)

Xu, Hang; Wang, Bingjie; Zhang, Jianguo; Liu, Li; Li, Ying; Wang, Yuncai; Wang, Anbang

2017-12-01

We experimentally demonstrate a chaos through-wall imaging radar using ultra-wideband chaotic-pulse-position modulation (CPPM) microwave signal. The CPPM signal based on logistic map with 1-ns pulse width and 1-GHz bandwidth is implemented by a field programmable gate array (FPGA) and then up-converted as the radar transmitting signal. Two-dimensional image of human objects behind obstacles is obtained by correlation method and back projection algorithm. Our experiments successfully perform through-wall imaging for single and multiple human objects through 20-cm thick wall. The down-range resolution of the proposed radar is 15 cm. Furthermore, the anti-jamming properties of the proposed radar in CPPM jamming, linear frequency-modulated jamming, and Gaussian noise jamming environments are demonstrated by electromagnetic simulations using the finite-difference time-domain. The simulation results show the CPPM microwave signal possesses excellent jamming immunity to the noise and radio frequency interference, which makes it perform superbly in multiradar environments.

Experiments with arbitrary networks in time-multiplexed delay systems

NASA Astrophysics Data System (ADS)

Hart, Joseph D.; Schmadel, Don C.; Murphy, Thomas E.; Roy, Rajarshi

2017-12-01

We report a new experimental approach using an optoelectronic feedback loop to investigate the dynamics of oscillators coupled on large complex networks with arbitrary topology. Our implementation is based on a single optoelectronic feedback loop with time delays. We use the space-time interpretation of systems with time delay to create large networks of coupled maps. Others have performed similar experiments using high-pass filters to implement the coupling; this restricts the network topology to the coupling of only a few nearest neighbors. In our experiment, the time delays and coupling are implemented on a field-programmable gate array, allowing the creation of networks with arbitrary coupling topology. This system has many advantages: the network nodes are truly identical, the network is easily reconfigurable, and the network dynamics occur at high speeds. We use this system to study cluster synchronization and chimera states in both small and large networks of different topologies.

The versatile GBT astronomical spectrometer (VEGAS): Current status and future plans

NASA Astrophysics Data System (ADS)

Prestage, Richard M.; Bloss, Marty; Brandt, Joe; Chen, Hong; Creager, Ray; Demorest, Paul; Ford, John; Jones, Glenn; Kepley, Amanda; Kobelski, Adam; Marganian, Paul; Mello, Melinda; McMahon, David; McCullough, Randy; Ray, Jason; Roshi, D. Anish; Werthimer, Dan; Whitehead, Mark

2015-07-01

The VEGAS multi-beam spectrometer (VEGAS) was built for the Green Bank Telescope (GBT) through a partnership between the National Radio Astronomy Observatory (NRAO) and the University of California at Berkeley. VEGAS is based on a Field Programmable Gate Array (FPGA) frontend and a heterogeneous computing backend comprised of Graphical Processing Units (GPUs) and CPUs. This system provides processing power to analyze up to 8 dual-polarization or 16 single-polarization inputs at bandwidths of up to 1.25 GHz per input. VEGAS was released for "shared-risk" observing in March 2014 and it became the default GBT spectral line backend in August 2014. Some of the early VEGAS observations include the Radio Ammonia Mid-Plane Survey, mapping of HCN/HCO+ in nearby galaxies, and a variety of radio-recombination line and pulsar projects. We will present some of the latest VEGAS science highlights.

Upgrading the Digital Electronics of the PEP-II Bunch Current Monitors at the Stanford Linear Accelerator Center

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kline, Josh; /SLAC

2006-08-28

The testing of the upgrade prototype for the bunch current monitors (BCMs) in the PEP-II storage rings at the Stanford Linear Accelerator Center (SLAC) is the topic of this paper. Bunch current monitors are used to measure the charge in the electron/positron bunches traveling in particle storage rings. The BCMs in the PEP-II storage rings need to be upgraded because components of the current system have failed and are known to be failure prone with age, and several of the integrated chips are no longer produced making repairs difficult if not impossible. The main upgrade is replacing twelve old (1995)more » field programmable gate arrays (FPGAs) with a single Virtex II FPGA. The prototype was tested using computer synthesis tools, a commercial signal generator, and a fast pulse generator.« less

Implementation of a Multichannel Serial Data Streaming Algorithm using the Xilinx Serial RapidIO Solution

NASA Technical Reports Server (NTRS)

Doxley, Charles A.

2016-01-01

In the current world of applications that use reconfigurable technology implemented on field programmable gate arrays (FPGAs), there is a need for flexible architectures that can grow as the systems evolve. A project has limited resources and a fixed set of requirements that development efforts are tasked to meet. Designers must develop robust solutions that practically meet the current customer demands and also have the ability to grow for future performance. This paper describes the development of a high speed serial data streaming algorithm that allows for transmission of multiple data channels over a single serial link. The technique has the ability to change to meet new applications developed for future design considerations. This approach uses the Xilinx Serial RapidIO LOGICORE Solution to implement a flexible infrastructure to meet the current project requirements with the ability to adapt future system designs.

Application of SEU imaging for analysis of device architecture using a 25 MeV/u 86Kr ion microbeam at HIRFL

NASA Astrophysics Data System (ADS)

Liu, Tianqi; Yang, Zhenlei; Guo, Jinlong; Du, Guanghua; Tong, Teng; Wang, Xiaohui; Su, Hong; Liu, Wenjing; Liu, Jiande; Wang, Bin; Ye, Bing; Liu, Jie

2017-08-01

The heavy-ion imaging of single event upset (SEU) in a flash-based field programmable gate array (FPGA) device was carried out for the first time at Heavy Ion Research Facility in Lanzhou (HIRFL). The three shift register chains with separated input and output configurations in device under test (DUT) were used to identify the corresponding logical area rapidly once an upset occurred. The logic units in DUT were partly configured in order to distinguish the registers in SEU images. Based on the above settings, the partial architecture of shift register chains in DUT was imaged by employing the microbeam of 86Kr ion with energy of 25 MeV/u in air. The results showed that the physical distribution of registers in DUT had a high consistency with its logical arrangement by comparing SEU image with logic configuration in scanned area.

Radiation Tolerant Intelligent Memory Stack (RTIMS)

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2006-01-01

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Evaluation of a high framerate multi-exposure laser speckle contrast imaging setup

NASA Astrophysics Data System (ADS)

Hultman, Martin; Fredriksson, Ingemar; Strömberg, Tomas; Larsson, Marcus

2018-02-01

We present a first evaluation of a new multi-exposure laser speckle contrast imaging (MELSCI) system for assessing spatial variations in the microcirculatory perfusion. The MELSCI system is based on a 1000 frames per second 1-megapixel camera connected to a field programmable gate arrays (FPGA) capable of producing MELSCI data in realtime. The imaging system is evaluated against a single point laser Doppler flowmetry (LDF) system during occlusionrelease provocations of the arm in five subjects. Perfusion is calculated from MELSCI data using current state-of-the-art inverse models. The analysis displayed a good agreement between measured and modeled data, with an average error below 6%. This strongly indicates that the applied model is capable of accurately describing the MELSCI data and that the acquired data is of high quality. Comparing readings from the occlusion-release provocation showed that the MELSCI perfusion was significantly correlated (R=0.83) to the single point LDF perfusion, clearly outperforming perfusion estimations based on a single exposure time. We conclude that the MELSCI system provides blood flow images of enhanced quality, taking us one step closer to a system that accurately can monitor dynamic changes in skin perfusion over a large area in real-time.

Adjustable Nyquist-rate System for Single-Bit Sigma-Delta ADC with Alternative FIR Architecture

NASA Astrophysics Data System (ADS)

Frick, Vincent; Dadouche, Foudil; Berviller, Hervé

2016-09-01

This paper presents a new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator. This system dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC's sampling frequency to the input signal's fundamental frequency with a few parts per million accuracy. The trade-off between straightforwardness and performance that motivated the choice of the ADC's architecture are preliminary discussed. It particularly comes along with design considerations of an ultra-steep direct-form FIR that is optimised in terms of size and operating speed. Thanks to compact standard VHDL language description, the architecture of the proposed system is particularly suitable for application-specific integrated circuit (ASIC) implementation-oriented low-power and low-cost power meter applications. Field programmable gate array (FPGA) prototyping and experimental results validate the adjustable sampling frequency concept. They also show that the system can perform better in terms of implementation and power capabilities compared to dedicated IP resources.

Generation of optical OFDM signals using 21.4 GS/s real time digital signal processing.

PubMed

Benlachtar, Yannis; Watts, Philip M; Bouziane, Rachid; Milder, Peter; Rangaraj, Deepak; Cartolano, Anthony; Koutsoyannis, Robert; Hoe, James C; Püschel, Markus; Glick, Madeleine; Killey, Robert I

2009-09-28

We demonstrate a field programmable gate array (FPGA) based optical orthogonal frequency division multiplexing (OFDM) transmitter implementing real time digital signal processing at a sample rate of 21.4 GS/s. The QPSK-OFDM signal is generated using an 8 bit, 128 point inverse fast Fourier transform (IFFT) core, performing one transform per clock cycle at a clock speed of 167.2 MHz and can be deployed with either a direct-detection or a coherent receiver. The hardware design and the main digital signal processing functions are described, and we show that the main performance limitation is due to the low (4-bit) resolution of the digital-to-analog converter (DAC) and the 8-bit resolution of the IFFT core used. We analyze the back-to-back performance of the transmitter generating an 8.36 Gb/s optical single sideband (SSB) OFDM signal using digital up-conversion, suitable for direct-detection. Additionally, we use the device to transmit 8.36 Gb/s SSB OFDM signals over 200 km of uncompensated standard single mode fiber achieving an overall BER<10(-3).

Ultrasonic Multiple-Access Ranging System Using Spread Spectrum and MEMS Technology for Indoor Localization

PubMed Central

Segers, Laurent; Tiete, Jelmer; Braeken, An; Touhafi, Abdellah

2014-01-01

Indoor localization of persons and objects poses a great engineering challenge. Previously developed localization systems demonstrate the use of wideband techniques in ultrasound ranging systems. Direct sequence and frequency hopping spread spectrum ultrasound signals have been proven to achieve a high level of accuracy. A novel ranging method using the frequency hopping spread spectrum with finite impulse response filtering will be investigated and compared against the direct sequence spread spectrum. In the first setup, distances are estimated in a single-access environment, while in the second setup, two senders and one receiver are used. During the experiments, the micro-electromechanical systems are used as ultrasonic sensors, while the senders were implemented using field programmable gate arrays. Results show that in a single-access environment, the direct sequence spread spectrum method offers slightly better accuracy and precision performance compared to the frequency hopping spread spectrum. When two senders are used, measurements point out that the frequency hopping spread spectrum is more robust to near-far effects than the direct sequence spread spectrum. PMID:24553084

A highly manufacturable 0.2 {mu}m AlGaAs/InGaAs PHEMT fabricated using the single-layer integrated-metal FET (SLIMFET) process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Havasy, C.K.; Quach, T.K.; Bozada, C.A.

1995-12-31

This work is the development of a single-layer integrated-metal field effect transistor (SLIMFET) process for a high performance 0.2 {mu}m AlGaAs/InGaAs pseudomorphic high electron mobility transistor (PHEMT). This process is compatible with MMIC fabrication and minimizes process variations, cycle time, and cost. This process uses non-alloyed ohmic contacts, a selective gate-recess etching process, and a single gate/source/drain metal deposition step to form both Schottky and ohmic contacts at the same time.

A real-time sub-μrad laser beam tracking system

NASA Astrophysics Data System (ADS)

Buske, Ivo; Schragner, Ralph; Riede, Wolfgang

2007-10-01

We present a rugged and reliable real-time laser beam tracking system operating with a high speed, high resolution piezo-electric tip/tilt mirror. Characteristics of the piezo mirror and position sensor are investigated. An industrial programmable automation controller is used to develop a real-time digital PID controller. The controller provides a one million field programmable gate array (FPGA) to realize a high closed-loop frequency of 50 kHz. Beam tracking with a root-mean-squared accuracy better than 0.15 μrad has been laboratory confirmed. The system is intended as an add-on module for established mechanical mrad tracking systems.

Single ZnO nanowire-PZT optothermal field effect transistors.

PubMed

Hsieh, Chun-Yi; Lu, Meng-Lin; Chen, Ju-Ying; Chen, Yung-Ting; Chen, Yang-Fang; Shih, Wan Y; Shih, Wei-Heng

2012-09-07

A new type of pyroelectric field effect transistor based on a composite consisting of single zinc oxide nanowire and lead zirconate titanate (ZnO NW-PZT) has been developed. Under infrared (IR) laser illumination, the transconductance of the ZnO NW can be modulated by optothermal gating. The drain current can be increased or decreased by IR illumination depending on the polarization orientation of the Pb(Zr(0.3)Ti(0.7))O(3) (PZT) substrate. Furthermore, by combining the photocurrent behavior in the UV range and the optothermal gating effect in the IR range, the wide spectrum of response of current by light offers a variety of opportunities for nanoscale optoelectronic devices.

Single-shot detection and direct control of carrier phase drift of midinfrared pulses.

PubMed

Manzoni, Cristian; Först, Michael; Ehrke, Henri; Cavalleri, Andrea

2010-03-01

We introduce a scheme for single-shot detection and correction of the carrier-envelope phase (CEP) drift of femtosecond pulses at mid-IR wavelengths. Difference frequency mixing between the mid-IR field and a near-IR gate pulse generates a near-IR frequency-shifted pulse, which is then spectrally interfered with a replica of the gate pulse. The spectral interference pattern contains shot-to-shot information of the CEP of the mid-IR field, and it can be used for simultaneous correction of its slow drifts. We apply this technique to detect and compensate long-term phase drifts at 17 microm wavelength, reducing fluctuations to only 110 mrad over hours of operation.

The UTMOST: A Hybrid Digital Signal Processor Transforms the Molonglo Observatory Synthesis Telescope

NASA Astrophysics Data System (ADS)

Bailes, M.; Jameson, A.; Flynn, C.; Bateman, T.; Barr, E. D.; Bhandari, S.; Bunton, J. D.; Caleb, M.; Campbell-Wilson, D.; Farah, W.; Gaensler, B.; Green, A. J.; Hunstead, R. W.; Jankowski, F.; Keane, E. F.; Krishnan, V. Venkatraman; Murphy, Tara; O'Neill, M.; Osłowski, S.; Parthasarathy, A.; Ravi, V.; Rosado, P.; Temby, D.

2017-10-01

The Molonglo Observatory Synthesis Telescope (MOST) is an 18000 m2 radio telescope located 40 km from Canberra, Australia. Its operating band (820-851 MHz) is partly allocated to telecommunications, making radio astronomy challenging. We describe how the deployment of new digital receivers, Field Programmable Gate Array-based filterbanks, and server-class computers equipped with 43 Graphics Processing Units, has transformed the telescope into a versatile new instrument (UTMOST) for studying the radio sky on millisecond timescales. UTMOST has 10 times the bandwidth and double the field of view compared to the MOST, and voltage record and playback capability has facilitated rapid implementaton of many new observing modes, most of which operate commensally. UTMOST can simultaneously excise interference, make maps, coherently dedisperse pulsars, and perform real-time searches of coherent fan-beams for dispersed single pulses. UTMOST operates as a robotic facility, deciding how to efficiently target pulsars and how long to stay on source via real-time pulsar folding, while searching for single pulse events. Regular timing of over 300 pulsars has yielded seven pulsar glitches and three Fast Radio Bursts during commissioning. UTMOST demonstrates that if sufficient signal processing is applied to voltage streams, innovative science remains possible even in hostile radio frequency environments.

Microdot - A Four-Bit Microcontroller Designed for Distributed Low-End Computing in Satellites

NASA Astrophysics Data System (ADS)

2002-03-01

Many satellites are an integrated collection of sensors and actuators that require dedicated real-time control. For single processor systems, additional sensors require an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors cost more and consume more power, which taxes a satellite's power resources and may lead to shorter satellite lifetimes. An alternative design approach is a distributed network of small and low power microcontrollers designed for space that handle the computing requirements of each individual sensor and actuator. The design of microdot, a four-bit microcontroller for distributed low-end computing, is presented. The design is based on previous research completed at the Space Electronics Branch, Air Force Research Laboratory (AFRL/VSSE) at Kirtland AFB, NM, and the Air Force Institute of Technology at Wright-Patterson AFB, OH. The Microdot has 29 instructions and a 1K x 4 instruction memory. The distributed computing architecture is based on the Philips Semiconductor I2C Serial Bus Protocol. A prototype was implemented and tested using an Altera Field Programmable Gate Array (FPGA). The prototype was operable to 9.1 MHz. The design was targeted for fabrication in a radiation-hardened-by-design gate-array cell library for the TSMC 0.35 micrometer CMOS process.

Tuning the electronic properties of gated multilayer phosphorene: A self-consistent tight-binding study

NASA Astrophysics Data System (ADS)

Li, L. L.; Partoens, B.; Peeters, F. M.

2018-04-01

By taking account of the electric-field-induced charge screening, a self-consistent calculation within the framework of the tight-binding approach is employed to obtain the electronic band structure of gated multilayer phosphorene and the charge densities on the different phosphorene layers. We find charge density and screening anomalies in single-gated multilayer phosphorene and electron-hole bilayers in dual-gated multilayer phosphorene. Due to the unique puckered lattice structure, both intralayer and interlayer charge screenings are important in gated multilayer phosphorene. We find that the electric-field tuning of the band structure of multilayer phosphorene is distinctively different in the presence and absence of charge screening. For instance, it is shown that the unscreened band gap of multilayer phosphorene decreases dramatically with increasing electric-field strength. However, in the presence of charge screening, the magnitude of this band-gap decrease is significantly reduced and the reduction depends strongly on the number of phosphorene layers. Our theoretical results of the band-gap tuning are compared with recent experiments and good agreement is found.

Low-cost, high-performance and efficiency computational photometer design

NASA Astrophysics Data System (ADS)

Siewert, Sam B.; Shihadeh, Jeries; Myers, Randall; Khandhar, Jay; Ivanov, Vitaly

2014-05-01

Researchers at the University of Alaska Anchorage and University of Colorado Boulder have built a low cost high performance and efficiency drop-in-place Computational Photometer (CP) to test in field applications ranging from port security and safety monitoring to environmental compliance monitoring and surveying. The CP integrates off-the-shelf visible spectrum cameras with near to long wavelength infrared detectors and high resolution digital snapshots in a single device. The proof of concept combines three or more detectors into a single multichannel imaging system that can time correlate read-out, capture, and image process all of the channels concurrently with high performance and energy efficiency. The dual-channel continuous read-out is combined with a third high definition digital snapshot capability and has been designed using an FPGA (Field Programmable Gate Array) to capture, decimate, down-convert, re-encode, and transform images from two standard definition CCD (Charge Coupled Device) cameras at 30Hz. The continuous stereo vision can be time correlated to megapixel high definition snapshots. This proof of concept has been fabricated as a fourlayer PCB (Printed Circuit Board) suitable for use in education and research for low cost high efficiency field monitoring applications that need multispectral and three dimensional imaging capabilities. Initial testing is in progress and includes field testing in ports, potential test flights in un-manned aerial systems, and future planned missions to image harsh environments in the arctic including volcanic plumes, ice formation, and arctic marine life.

A Brain-Machine-Brain Interface for Rewiring of Cortical Circuitry after Traumatic Brain Injury

DTIC Science & Technology

2013-09-01

implemented to significantly decrease the IIR system response time, especially when artifacts were highly reproducible in consecutive stimulation...cycles. The proposed system architecture was hardware- implemented on a field- programmable gate array (FPGA) and tested using two sets of prerecorded...its FPGA implementation and testing with prerecorded neural datasets are reported in a manuscript currently in press with the IEEE Transactions on

Chrestenson transform FPGA embedded factorizations.

PubMed

Corinthios, Michael J

2016-01-01

Chrestenson generalized Walsh transform factorizations for parallel processing imbedded implementations on field programmable gate arrays are presented. This general base transform, sometimes referred to as the Discrete Chrestenson transform, has received special attention in recent years. In fact, the Discrete Fourier transform and Walsh-Hadamard transform are but special cases of the Chrestenson generalized Walsh transform. Rotations of a base-p hypercube, where p is an arbitrary integer, are shown to produce dynamic contention-free memory allocation, in processor architecture. The approach is illustrated by factorizations involving the processing of matrices of the transform which are function of four variables. Parallel operations are implemented matrix multiplications. Each matrix, of dimension N × N, where N = p (n) , n integer, has a structure that depends on a variable parameter k that denotes the iteration number in the factorization process. The level of parallelism, in the form of M = p (m) processors can be chosen arbitrarily by varying m between zero to its maximum value of n - 1. The result is an equation describing the generalised parallelism factorization as a function of the four variables n, p, k and m. Applications of the approach are shown in relation to configuring field programmable gate arrays for digital signal processing applications.

A field programmable gate array-based time-resolved scaler for collinear laser spectroscopy with bunched radioactive potassium beams

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rossi, D. M., E-mail: rossi@nscl.msu.edu; Davis, M.; Ringle, R.

A new data acquisition system including a Field Programmable Gate Array (FPGA) based time-resolved scaler was developed for laser-induced fluorescence and beam bunch coincidence measurements. The FPGA scaler was tested in a collinear laser-spectroscopy experiment on radioactive {sup 37}K at the BEam COoler and LAser spectroscopy (BECOLA) facility at the National Superconducting Cyclotron Laboratory at Michigan State University. A 1.29 μs bunch width from the buncher and a bunch repetition rate of 2.5 Hz led to a background suppression factor of 3.1 × 10{sup 5} in resonant photon detection measurements. The hyperfine structure of {sup 37}K and its isotope shiftmore » relative to the stable {sup 39}K were determined using 5 × 10{sup 4} s{sup −1} {sup 37}K ions injected into the BECOLA beam line. The obtained hyperfine coupling constants A({sup 2}S{sub 1/2}) = 120.3(1.4) MHz, A({sup 2}P{sub 1/2}) = 15.2(1.1) MHz, and A({sup 2}P{sub 3/2}) = 1.4(8) MHz, and the isotope shift δν{sup 39,} {sup 37} = −264(3) MHz are consistent with the previously determined values, where available.« less

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

A Lithography-Free and Field-Programmable Photonic Metacanvas.

PubMed

Dong, Kaichen; Hong, Sukjoon; Deng, Yang; Ma, He; Li, Jiachen; Wang, Xi; Yeo, Junyeob; Wang, Letian; Lou, Shuai; Tom, Kyle B; Liu, Kai; You, Zheng; Wei, Yang; Grigoropoulos, Costas P; Yao, Jie; Wu, Junqiao

2018-02-01

The unique correspondence between mathematical operators and photonic elements in wave optics enables quantitative analysis of light manipulation with individual optical devices. Phase-transition materials are able to provide real-time reconfigurability of these devices, which would create new optical functionalities via (re)compilation of photonic operators, as those achieved in other fields such as field-programmable gate arrays (FPGA). Here, by exploiting the hysteretic phase transition of vanadium dioxide, an all-solid, rewritable metacanvas on which nearly arbitrary photonic devices can be rapidly and repeatedly written and erased is presented. The writing is performed with a low-power laser and the entire process stays below 90 °C. Using the metacanvas, dynamic manipulation of optical waves is demonstrated for light propagation, polarization, and reconstruction. The metacanvas supports physical (re)compilation of photonic operators akin to that of FPGA, opening up possibilities where photonic elements can be field programmed to deliver complex, system-level functionalities. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Volumetric visualization algorithm development for an FPGA-based custom computing machine

NASA Astrophysics Data System (ADS)

Sallinen, Sami J.; Alakuijala, Jyrki; Helminen, Hannu; Laitinen, Joakim

1998-05-01

Rendering volumetric medical images is a burdensome computational task for contemporary computers due to the large size of the data sets. Custom designed reconfigurable hardware could considerably speed up volume visualization if an algorithm suitable for the platform is used. We present an algorithm and speedup techniques for visualizing volumetric medical CT and MR images with a custom-computing machine based on a Field Programmable Gate Array (FPGA). We also present simulated performance results of the proposed algorithm calculated with a software implementation running on a desktop PC. Our algorithm is capable of generating perspective projection renderings of single and multiple isosurfaces with transparency, simulated X-ray images, and Maximum Intensity Projections (MIP). Although more speedup techniques exist for parallel projection than for perspective projection, we have constrained ourselves to perspective viewing, because of its importance in the field of radiotherapy. The algorithm we have developed is based on ray casting, and the rendering is sped up by three different methods: shading speedup by gradient precalculation, a new generalized version of Ray-Acceleration by Distance Coding (RADC), and background ray elimination by speculative ray selection.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

High density, multi-range analog output Versa Module Europa board for control system applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, Kundan, E-mail: kundan@iuac.res.in; Das, Ajit Lal

2014-01-15

A new VMEDAC64, 12-bit 64 channel digital-to-analog converter, a Versa Module Europa (VME) module, features 64 analog voltage outputs with user selectable multiple ranges, has been developed for control system applications at Inter University Accelerator Centre. The FPGA (Field Programmable Gate Array) is the module's core, i.e., it implements the DAC control logic and complexity of VMEbus slave interface logic. The VMEbus slave interface and DAC control logic are completely designed and implemented on a single FPGA chip to achieve high density of 64 channels in a single width VME module and will reduce the module count in the controlmore » system applications, and hence will reduce the power consumption and cost of overall system. One of our early design goals was to develop the VME interface such that it can be easily integrated with the peripheral devices and satisfy the timing specifications of VME standard. The modular design of this module reduces the amount of time required to develop other custom modules for control system. The VME slave interface is written as a single component inside FPGA which will be used as a basic building block for any VMEbus interface project. The module offers multiple output voltage ranges depending upon the requirement. The output voltage range can be reduced or expanded by writing range selection bits in the control register. The module has programmable refresh rate and by default hold capacitors in the sample and hold circuit for each channel are charged periodically every 7.040 ms (i.e., update frequency 284 Hz). Each channel has software controlled output switch which disconnects analog output from the field. The modularity in the firmware design on FPGA makes the debugging very easy. On-board DC/DC converters are incorporated for isolated power supply for the analog section of the board.« less

3D modeling of dual-gate FinFET.

PubMed

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

3D modeling of dual-gate FinFET

NASA Astrophysics Data System (ADS)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-01

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V g1 > V g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Development of Gating Foils To Inhibit Ion Feedback Using FPC Production Techniques

NASA Astrophysics Data System (ADS)

Arai, D.; Ikematsu, K.; Sugiyama, A.; Iwamura, M.; Koto, A.; Katsuki, K.; Fujii, K.; Matsuda, T.

2018-02-01

Positive ion feedback from a gas amplification device to the drift region of the Time Projection Chamber for the ILC can deteriorate the position resolution. In order to inhibit the feedback ions, MPGD-based gating foils having good electron transmission have been developed to be used instead of the conventional wire gate. The gating foil needs to control the electric field locally in opening or closing the gate. The gating foil with a GEM (gas electron multiplier)-like structure has larger holes and smaller thickness than standard GEMs for gas amplification. It is known that the foil transmits over 80 % of electrons and blocks ions almost completely. We have developed the gating foils using flexible printed circuit (FPC) production techniques including an improved single-mask process. In this paper, we report on the production technique of 335 μm pitch, 12.5 μm thick gating foil with 80 % transmittance of electrons in ILC conditions.

Bio-fabrication of nanomesh channels of single-walled carbon nanotubes for locally gated field-effect transistors

NASA Astrophysics Data System (ADS)

Byeon, Hye-Hyeon; Lee, Woo Chul; Kim, Wonbin; Kim, Seong Keun; Kim, Woong; Yi, Hyunjung

2017-01-01

Single-walled carbon nanotubes (SWNTs) are one of the promising electronic components for nanoscale electronic devices such as field-effect transistors (FETs) owing to their excellent device characteristics such as high conductivity, high carrier mobility and mechanical flexibility. Localized gating gemometry of FETs enables individual addressing of active channels and allows for better electrostatics via thinner dielectric layer of high k-value. For localized gating of SWNTs, it becomes critical to define SWNTs of controlled nanostructures and functionality onto desired locations in high precision. Here, we demonstrate that a biologically templated approach in combination of microfabrication processes can successfully produce a nanostructured channels of SWNTs for localized active devices such as local bottom-gated FETs. A large-scale nanostructured network, nanomesh, of SWNTs were assembled in solution using an M13 phage with strong binding affinity toward SWNTs and micrometer-scale nanomesh channels were defined using negative photolithography and plasma-etching processes. The bio-fabrication approach produced local bottom-gated FETs with remarkably controllable nanostructures and successfully enabled semiconducting behavior out of unsorted SWNTs. In addition, the localized gating scheme enhanced the device performances such as operation voltage and I on/I off ratio. We believe that our approach provides a useful and integrative method for fabricating electronic devices out of nanoscale electronic materials for applications in which tunable electrical properties, mechanical flexibility, ambient stability, and chemical stability are of crucial importance.

Nanopore extended field-effect transistor for selective single-molecule biosensing.

PubMed

Ren, Ren; Zhang, Yanjun; Nadappuram, Binoy Paulose; Akpinar, Bernice; Klenerman, David; Ivanov, Aleksandar P; Edel, Joshua B; Korchev, Yuri

2017-09-19

There has been a significant drive to deliver nanotechnological solutions to biosensing, yet there remains an unmet need in the development of biosensors that are affordable, integrated, fast, capable of multiplexed detection, and offer high selectivity for trace analyte detection in biological fluids. Herein, some of these challenges are addressed by designing a new class of nanoscale sensors dubbed nanopore extended field-effect transistor (nexFET) that combine the advantages of nanopore single-molecule sensing, field-effect transistors, and recognition chemistry. We report on a polypyrrole functionalized nexFET, with controllable gate voltage that can be used to switch on/off, and slow down single-molecule DNA transport through a nanopore. This strategy enables higher molecular throughput, enhanced signal-to-noise, and even heightened selectivity via functionalization with an embedded receptor. This is shown for selective sensing of an anti-insulin antibody in the presence of its IgG isotype.Efficient detection of single molecules is vital to many biosensing technologies, which require analytical platforms with high selectivity and sensitivity. Ren et al. combine a nanopore sensor and a field-effect transistor, whereby gate voltage mediates DNA and protein transport through the nanopore.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

PubMed

Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

2014-12-01

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berger, Andrew J., E-mail: berger.156@osu.edu; Page, Michael R.; Young, Justin R.

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform themore » various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.« less

Software Process Assurance for Complex Electronics (SPACE)

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer

NASA Astrophysics Data System (ADS)

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-01

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd)4Ti3O12 films as insulator, and HfO2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO2 defect control layer shows a low leakage current density of 3.1 × 10-9 A/cm2 at a gate voltage of - 3 V.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer.

PubMed

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-27

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd) 4 Ti 3 O 12 films as insulator, and HfO 2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO 2 defect control layer shows a low leakage current density of 3.1 × 10 -9  A/cm 2 at a gate voltage of - 3 V.

An Implementation of Physical Layer Authentication Using Software Radio

DTIC Science & Technology

2009-07-01

USRP consists of an FPGA responsible for up/down conversions, ADCs and DACs, and various plug-in daughterboards. . . . . . . . . . . . . . . . . 7 5...seen in figure 4, the USRP consists of a USB interface, a 6 field-programmable gate array ( FPGA ), ADCs and DACs, and daughterboards. The...configuration. In the following, we detail the signal receive path to highlight the design of the hardware. FPGA Receive Daughterboar d A/D A/D Tr ansmit

Modeling and Simulation of a Non-Coherent Frequency Shift Keying Transceiver Using a Field Programmable Gate Array (FPGA)

DTIC Science & Technology

2008-09-01

Convolutional Encoder Block Diagram of code rate 1 2 r = and...most commonly used along with block codes . They were introduced in 1955 by Elias [7]. Convolutional codes are characterized by the code rate kr n... convolutional code for 1 2 r = and = 3κ , namely [7 5], is used. Figure 2 Convolutional Encoder Block Diagram of code rate 1 2 r = and

Low-Cost Space Hardware and Software

NASA Technical Reports Server (NTRS)

Shea, Bradley Franklin

2013-01-01

The goal of this project is to demonstrate and support the overall vision of NASA's Rocket University (RocketU) through the design of an electrical power system (EPS) monitor for implementation on RUBICS (Rocket University Broad Initiatives CubeSat), through the support for the CHREC (Center for High-Performance Reconfigurable Computing) Space Processor, and through FPGA (Field Programmable Gate Array) design. RocketU will continue to provide low-cost innovations even with continuous cuts to the budget.

A Fully Integrated Materials Framework for Enabling the Wireless Detection of Micro-defects in Aging and Battle-worn Structures

DTIC Science & Technology

2012-05-01

field-programmable gate array (FPGA) uses digital signal processing (DSP) algorithms to decode echo-location information from the backscattered signal ...characterizing and understanding of the physical properties of the BST and PZT thin films. Using microwave reflection spectroscopy, the complex...acoustic data, , would be encoded in the reflected MW signal by means of phase modulation (PM). By using high-Q resonators as the reactive

Model of a programmable quantum processing unit based on a quantum transistor effect

NASA Astrophysics Data System (ADS)

Ablayev, Farid; Andrianov, Sergey; Fetisov, Danila; Moiseev, Sergey; Terentyev, Alexandr; Urmanchev, Andrey; Vasiliev, Alexander

2018-02-01

In this paper we propose a model of a programmable quantum processing device realizable with existing nano-photonic technologies. It can be viewed as a basis for new high performance hardware architectures. Protocols for physical implementation of device on the controlled photon transfer and atomic transitions are presented. These protocols are designed for executing basic single-qubit and multi-qubit gates forming a universal set. We analyze the possible operation of this quantum computer scheme. Then we formalize the physical architecture by a mathematical model of a Quantum Processing Unit (QPU), which we use as a basis for the Quantum Programming Framework. This framework makes it possible to perform universal quantum computations in a multitasking environment.

A magnetoelectric flux gate: new approach for weak DC magnetic field detection.

PubMed

Chu, Zhaoqiang; Shi, Huaduo; PourhosseiniAsl, Mohammad Javad; Wu, Jingen; Shi, Weiliang; Gao, Xiangyu; Yuan, Xiaoting; Dong, Shuxiang

2017-08-17

The magnetic flux gate sensors based on Faraday's Law of Induction are widely used for DC or extremely low frequency magnetic field detection. Recently, as the fast development of multiferroics and magnetoelectric (ME) composite materials, a new technology based on ME coupling effect is emerging for potential devices application. Here, we report a magnetoelectric flux gate sensor (MEFGS) for weak DC magnetic field detection for the first time, which works on a similar magnetic flux gate principle, but based on ME coupling effect. The proposed MEFGS has a shuttle-shaped configuration made of amorphous FeBSi alloy (Metglas) serving as both magnetic and magnetostrictive cores for producing a closed-loop high-frequency magnetic flux and also a longitudinal vibration, and one pair of embedded piezoelectric PMN-PT fibers ([011]-oriented Pb(Mg,Nb)O 3 -PbTiO 3 single crystal) serving as ME flux gate in a differential mode for detecting magnetic anomaly. In this way, the relative change in output signal of the MEFGS under an applied DC magnetic anomaly of 1 nT was greatly enhanced by a factor of 4 to 5 in comparison with the previous reports. The proposed ME flux gate shows a great potential for magnetic anomaly detections, such as magnetic navigation, magnetic based medical diagnosis, etc.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

NASA Astrophysics Data System (ADS)

Lu, Zhongyuan; Serrao, Claudy; Khan, Asif Islam; You, Long; Wong, Justin C.; Ye, Yu; Zhu, Hanyu; Zhang, Xiang; Salahuddin, Sayeef

2017-07-01

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (107), and a subthreshold swing of (SS ˜ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides.

FPGA-based multiprocessor system for injection molding control.

PubMed

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

2012-10-18

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Large-current-controllable carbon nanotube field-effect transistor in electrolyte solution

NASA Astrophysics Data System (ADS)

Myodo, Miho; Inaba, Masafumi; Ohara, Kazuyoshi; Kato, Ryogo; Kobayashi, Mikinori; Hirano, Yu; Suzuki, Kazuma; Kawarada, Hiroshi

2015-05-01

Large-current-controllable carbon nanotube field-effect transistors (CNT-FETs) were fabricated with mm-long CNT sheets. The sheets, synthesized by remote-plasma-enhanced CVD, contained both single- and double-walled CNTs. Titanium was deposited on the sheet as source and drain electrodes, and an electrolyte solution was used as a gate electrode (solution gate) to apply a gate voltage to the CNTs through electric double layers formed around the CNTs. The drain current came to be well modulated as electrolyte solution penetrated into the sheets, and one of the solution gate CNT-FETs was able to control a large current of over 2.5 A. In addition, we determined the transconductance parameter per tube and compared it with values for other CNT-FETs. The potential of CNT sheets for applications requiring the control of large current is exhibited in this study.

Simulation study of short-channel effects of tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Fukuda, Koichi; Asai, Hidehiro; Hattori, Junichi; Mori, Takahiro; Morita, Yukinori; Mizubayashi, Wataru; Masahara, Meishoku; Migita, Shinji; Ota, Hiroyuki; Endo, Kazuhiro; Matsukawa, Takashi

2018-04-01

Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal-oxide-semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

Effect of electrode design on crosstalk between neighboring organic field-effect transistors based on one single crystal

NASA Astrophysics Data System (ADS)

Li, Mengjie; Tang, Qingxin; Tong, Yanhong; Zhao, Xiaoli; Zhou, Shujun; Liu, Yichun

2018-03-01

The design of high-integration organic circuits must be such that the interference between neighboring devices is eliminated. Here, rubrene crystals were used to study the effect of the electrode design on crosstalk between neighboring organic field-effect transistors (OFETs). Results show that a decreased source/drain interval and gate electrode width can decrease the diffraction distance of the current, and therefore can weaken the crosstalk. In addition, the inherent low carrier concentration in organic semiconductors can create a high-resistance barrier at the space between gate electrodes of neighboring devices, limiting or even eliminating the crosstalk as a result of the gate electrode width being smaller than the source/drain electrode width.

Continuous-variable quantum computation with spatial degrees of freedom of photons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tasca, D. S.; Gomes, R. M.; Toscano, F.

2011-05-15

We discuss the use of the transverse spatial degrees of freedom of photons propagating in the paraxial approximation for continuous-variable information processing. Given the wide variety of linear optical devices available, a diverse range of operations can be performed on the spatial degrees of freedom of single photons. Here we show how to implement a set of continuous quantum logic gates which allow for universal quantum computation. In contrast with the usual quadratures of the electromagnetic field, the entire set of single-photon gates for spatial degrees of freedom does not require optical nonlinearity and, in principle, can be performed withmore » a single device: the spatial light modulator. Nevertheless, nonlinear optical processes, such as four-wave mixing, are needed in the implementation of two-photon gates. The efficiency of these gates is at present very low; however, small-scale investigations of continuous-variable quantum computation are within the reach of current technology. In this regard, we show how novel cluster states for one-way quantum computing can be produced using spontaneous parametric down-conversion.« less

Composite multi-qubit gates dynamically corrected against charge noise and magnetic field noise for singlet-triplet qubits

NASA Astrophysics Data System (ADS)

Kestner, Jason; Barnes, Edwin; Wang, Xin; Bishop, Lev; Das Sarma, Sankar

2013-03-01

We use previously described single-qubit SUPCODE pulses on both intra-qubit and inter-qubit exchange couplings, integrated with existing strategies such as BB1, to theoretically construct a CNOT gate that is robust against both charge noise and magnetic field gradient fluctuations. We show how this allows scalable, high-fidelity implementation of arbitrary multi-qubit operations using singlet-triplet spin qubits in the presence of experimentally realistic noise. This work is supported by LPS-NSA-CMTC, IARPA-MQCO and CNAM.

Quantum phase gate based on electromagnetically induced transparency in optical cavities

NASA Astrophysics Data System (ADS)

Borges, Halyne S.; Villas-Bôas, Celso J.

2016-11-01

We theoretically investigate the implementation of a quantum controlled-phase gate in a system constituted by a single atom inside an optical cavity, based on the electromagnetically induced transparency effect. First we show that a probe pulse can experience a π phase shift due to the presence or absence of a classical control field. Considering the interplay of the cavity-EIT effect and the quantum memory process, we demonstrated a controlled-phase gate between two single photons. To this end, first one needs to store a (control) photon in the ground atomic states. In the following, a second (target) photon must impinge on the atom-cavity system. Depending on the atomic state, this second photon will be either transmitted or reflected, acquiring different phase shifts. This protocol can then be easily extended to multiphoton systems, i.e., keeping the control photon stored, it may induce phase shifts in several single photons, thus enabling the generation of multipartite entangled states. We explore the relevant parameter space in the atom-cavity system that allows the implementation of quantum controlled-phase gates using the recent technologies. In particular, we have found a lower bound for the cooperativity of the atom-cavity system which enables the implementation of phase shift on single photons. The induced shift on the phase of a photonic qubit and the controlled-phase gate between single photons, combined with optical devices, enable one to perform universal quantum computation.

Field-programmable logic devices with optical input-output.

PubMed

Szymanski, T H; Saint-Laurent, M; Tyan, V; Au, A; Supmonchai, B

2000-02-10

A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA's) on a 2 mm x 2 mm die. The devices were fabricated through the Lucent Technologies-Advanced Research Projects Agency-Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-microm complementary metal-oxide semiconductor-self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 x 4 crossbar switches, which can realize more than 190 x 10(6) unique programmable input-output permutations. The same device scaled to a 2 cm x 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems

DOEpatents

Welch, James D.

2003-09-23

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

ZnO-based multiple channel and multiple gate FinMOSFETs

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

2016-02-01

In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

Gate-defined quantum confinement in suspended bilayer graphene

NASA Astrophysics Data System (ADS)

Allen, M. T.; Martin, J.; Yacoby, A.

2012-07-01

Quantum-confined devices that manipulate single electrons in graphene are emerging as attractive candidates for nanoelectronics applications. Previous experiments have employed etched graphene nanostructures, but edge and substrate disorder severely limit device functionality. Here we present a technique that builds quantum-confined structures in suspended bilayer graphene with tunnel barriers defined by external electric fields that open a bandgap, thereby eliminating both edge and substrate disorder. We report clean quantum dot formation in two regimes: at zero magnetic field B using the energy gap induced by a perpendicular electric field and at B>0 using the quantum Hall ν=0 gap for confinement. Coulomb blockade oscillations exhibit periodicity consistent with electrostatic simulations based on local top-gate geometry, a direct demonstration of local control over the band structure of graphene. This technology integrates single electron transport with high device quality and access to vibrational modes, enabling broad applications from electromechanical sensors to quantum bits.

Goos-Hänchen-like shift in biased silicene

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, Bang-Shan; Wang, Yu, E-mail: ywang@semi.ac.cn; Lou, Yi-Yi

2016-04-28

We have theoretically studied the Goos-Hänchen-like shift of spinor-unpolarized beams tunneling through various gate-biased silicene nanostructures. Following the stationary-phase method, lateral displacement in single-, dual-, and multiple-gated silicene systems has been systematically demonstrated. It is shown for simple single-gated silicene that lateral displacement can be generally enhanced by Fabry-Perot interference, and near the transition point turning on the evanescent mode a very large lateral shift could be observed. For the dual-gated structure, we have also shown the crucial role of localized modes like quantum well states in enhancing the beam lateral displacement, while for the multiple gate-biased systems the resultingmore » superlattice subbands are also favorable for lateral displacement enhancement. Importantly, including the degeneracy-broken mechanisms such as gate-field and magnetic modulations, a fully spinor-resolved beam can be distinguished from the rest counterparts by aligning the incident beam with a proper spinor-resolved transition point, localized state, and subband, all of which can be flexibly modulated via electric means, offering the very desirable strategies to achieve the fully spinor-polarized beam for functional electronic applications.« less

Readout and DAQ for Pixel Detectors

NASA Astrophysics Data System (ADS)

Platkevic, Michal

2010-01-01

Data readout and acquisition control of pixel detectors demand the transfer of significantly a large amounts of bits between the detector and the computer. For this purpose dedicated interfaces are used which are designed with focus on features like speed, small dimensions or flexibility of use such as digital signal processors, field-programmable gate arrays (FPGA) and USB communication ports. This work summarizes the readout and DAQ system built for state-of-the-art pixel detectors of the Medipix family.

Digitization of Analog Signals using a Field Programmable Gate Array (FPGA)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aguilera, Daniel; Rusu, Vadim

The idea of this research is consolidating the electrical components used for capturing data in the Mu2e Tracker. Ideally, an FPGA will serve as the Time-Division Converters (TDC) and Analog-to-Digital Converters (ADC). The TDC is already being carried out by the FPGA, but we are still using off the shelf ADCs. This poster proposes using Low Voltage Differential Signaling as the basis for analog-to-digital conversion using and FPGA.

Evaluating De-centralised and Distributional Options for the Distributed Electronic Warfare Situation Awareness and Response Test Bed

DTIC Science & Technology

2013-12-01

effectors (deployed on ground based or aerial platforms) to detect , identify, locate, track or suppress stationary or slow moving surface based RF...ground based or aerial platforms) to detect , identify, locate, track or suppress stationary or slow moving surface based RF emitting targets. In the...Electronic Support EO Electro-Optic FPGAs Field Programmable Gate Arrays IR Infra-red LADAR Laser Detection and Ranging OSX Mac OS X; the apple

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

DTIC Science & Technology

2008-07-01

a) that the results are accepted by users, vendors, … and (b) that they can quantitatively explain HPC rules of thumb such as: “OpenMP is easier...in productivity that were demonstrated by traditional software systems. Using advances in software productivity as a guide , we have identified three...of this study we developed a productivity model to guide our investigation (14). Models have limitations and the model we propose is no exception

Aptamer-Binding Directed DNA Origami Pattern for Logic Gates.

PubMed

Yang, Jing; Jiang, Shuoxing; Liu, Xiangrong; Pan, Linqiang; Zhang, Cheng

2016-12-14

In this study, an aptamer-substrate strategy is introduced to control programmable DNA origami pattern. Combined with DNA aptamer-substrate binding and DNAzyme-cutting, small DNA tiles were specifically controlled to fill into the predesigned DNA origami frame. Here, a set of DNA logic gates (OR, YES, and AND) are performed in response to the stimuli of adenosine triphosphate (ATP) and cocaine. The experimental results are confirmed by AFM imaging and time-dependent fluorescence changes, demonstrating that the geometric patterns are regulated in a controllable and programmable manner. Our approach provides a new platform for engineering programmable origami nanopatterns and constructing complex DNA nanodevices.

Single phase dynamic CMOS PLA using charge sharing technique

NASA Technical Reports Server (NTRS)

Dhong, Y. B.; Tsang, C. P.

1991-01-01

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

The Gates Malaria Partnership: a consortium approach to malaria research and capacity development.

PubMed

Greenwood, Brian; Bhasin, Amit; Targett, Geoffrey

2012-05-01

Recently, there has been a major increase in financial support for malaria control. Most of these funds have, appropriately, been spent on the tools needed for effective prevention and treatment of malaria such as insecticide-treated bed nets, indoor residual spraying and artemisinin combination therapy. There has been less investment in the training of the scientists from malaria-endemic countries needed to support these large and increasingly complex malaria control programmes, especially in Africa. In 2000, with support from the Bill & Melinda Gates Foundation, the Gates Malaria Partnership was established to support postgraduate training of African scientists wishing to pursue a career in malaria research. The programme had three research capacity development components: a PhD fellowship programme, a postdoctoral fellowship programme and a laboratory infrastructure programme. During an 8-year period, 36 African PhD students and six postdoctoral fellows were supported, and two research laboratories were built in Tanzania. Some of the lessons learnt during this project--such as the need to improve PhD supervision in African universities and to provide better support for postdoctoral fellows--are now being applied to a successor malaria research capacity development programme, the Malaria Capacity Development Consortium, and may be of interest to other groups involved in improving postgraduate training in health sciences in African universities. © 2012 Blackwell Publishing Ltd.

Magnetoelectric domain wall dynamics and its implications for magnetoelectric memory

DOE PAGES

Belashchenko, K. D.; Tchernyshyov, O.; Kovalev, Alexey A.; ...

2016-03-30

Domain wall dynamics in a magnetoelectric antiferromagnet is analyzed, and its implications for magnetoelectric memory applications are discussed. Cr 2O 3 is used in the estimates of the materials parameters. It is found that the domain wall mobility has a maximum as a function of the electric field due to the gyrotropic coupling induced by it. In Cr 2O 3, the maximal mobility of 0.1 m/(s Oe) is reached at E≈0.06 V/nm. Fields of this order may be too weak to overcome the intrinsic depinning field, which is estimated for B-doped Cr 2O 3. These major drawbacks for device implementationmore » can be overcome by applying a small in-plane shear strain, which blocks the domain wall precession. Domain wall mobility of about 0.7 m/(s Oe) can then be achieved at E = 0.2 V/nm. Furthermore, a split-gate scheme is proposed for the domain-wall controlled bit element; its extension to multiple-gate linear arrays can offer advantages in memory density, programmability, and logic functionality.« less

Holonomic Quantum Control by Coherent Optical Excitation in Diamond.

PubMed

Zhou, Brian B; Jerger, Paul C; Shkolnikov, V O; Heremans, F Joseph; Burkard, Guido; Awschalom, David D

2017-10-06

Although geometric phases in quantum evolution are historically overlooked, their active control now stimulates strategies for constructing robust quantum technologies. Here, we demonstrate arbitrary single-qubit holonomic gates from a single cycle of nonadiabatic evolution, eliminating the need to concatenate two separate cycles. Our method varies the amplitude, phase, and detuning of a two-tone optical field to control the non-Abelian geometric phase acquired by a nitrogen-vacancy center in diamond over a coherent excitation cycle. We demonstrate the enhanced robustness of detuned gates to excited-state decoherence and provide insights for optimizing fast holonomic control in dissipative quantum systems.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

UVPROM dosimetry, microdosimetry and applications to SEU and extreme value theory

NASA Astrophysics Data System (ADS)

Scheick, Leif Zebediah

A new method is described for characterizing a device in terms of the statistical distribution of first failures. The method is based on the erasure of a commercial Ultra- Violet erasable Programmable Read Only Memory (UVPROM). The method of readout would be used on a spacecraft or in other restrictive radiation environments. The measurement of the charge remaining on the floating gate is used to determine absorbed dose. The method of determining dose does not require the detector to be destroyed or erased nor does it effect the ability for taking further measurements. This is compared to extreme value theory applied to the statistical distributions that apply to this device. This technique predicts the threshold of Single Event Effects (SEE), like anomalous changes in erasure time in programmable devices due to high microdose energy-deposition events. This technique also allows for advanced non-destructive, screening of a single microelectronic devices for predictable response in a stressful, i.e. radiation, environments.

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor

PubMed Central

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-01-01

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation. PMID:27983714

Coherent ultra dense wavelength division multiplexing passive optical networks

NASA Astrophysics Data System (ADS)

Shahpari, Ali; Ferreira, Ricardo; Ribeiro, Vitor; Sousa, Artur; Ziaie, Somayeh; Tavares, Ana; Vujicic, Zoran; Guiomar, Fernando P.; Reis, Jacklyn D.; Pinto, Armando N.; Teixeira, António

2015-12-01

In this paper, we firstly review the progress in ultra-dense wavelength division multiplexing passive optical network (UDWDM-PON), by making use of the key attributes of this technology in the context of optical access and metro networks. Besides the inherit properties of coherent technology, we explore different modulation formats and pulse shaping. The performance is experimentally demonstrated through a 12 × 10 Gb/s bidirectional UDWDM-PON over hybrid 80 km standard single mode fiber (SSMF) and optical wireless link. High density, 6.25 GHz grid, Nyquist shaped 16-ary quadrature amplitude modulation (16QAM) and digital frequency shifting are some of the properties exploited together in the tests. Also, bidirectional transmission in fiber, relevant in the context, is analyzed in terms of nonlinear and back-reflection effects on receiver sensitivity. In addition, as a basis for the discussion on market readiness, we experimentally demonstrate real-time detection of a Nyquist-shaped quaternary phase-shift keying (QPSK) signal using simple 8-bit digital signal processing (DSP) on a field-programmable gate array (FPGA).

FPGA-based photon-counting phase-modulation fluorometer and a brief comparison with that operated in a pulsed-excitation mode

NASA Astrophysics Data System (ADS)

Iwata, Tetsuo; Taga, Takanori; Mizuno, Takahiko

2018-02-01

We have constructed a high-efficiency, photon-counting phase-modulation fluorometer (PC-PMF) using a field-programmable gate array, which is a modified version of the photon-counting fluorometer (PCF) that works in a pulsed-excitation mode (Iwata and Mizuno in Meas Sci Technol 28:075501, 2017). The common working principle for both is the simultaneous detection of the photoelectron pulse train, which covers 64 ns with a 1.0-ns resolution time (1.0 ns/channel). The signal-gathering efficiency was improved more than 100 times over that of conventional time-correlated single-photon-counting at the expense of resolution time depending on the number of channels. The system dead time for building a histogram was eliminated, markedly shortening the measurement time for fluorescent samples with moderately high quantum yields. We describe the PC-PMF and make a brief comparison with the pulsed-excitation PCF in precision, demonstrating the potential advantage of PC-PMF.

Diagnostic layer integration in FPGA-based pipeline measurement systems for HEP experiments

NASA Astrophysics Data System (ADS)

Pozniak, Krzysztof T.

2007-08-01

Integrated triggering and data acquisition systems for high energy physics experiments may be considered as fast, multichannel, synchronous, distributed, pipeline measurement systems. A considerable extension of functional, technological and monitoring demands, which has recently been imposed on them, forced a common usage of large field-programmable gate array (FPGA), digital signal processing-enhanced matrices and fast optical transmission for their realization. This paper discusses modelling, design, realization and testing of pipeline measurement systems. A distribution of synchronous data stream flows is considered in the network. A general functional structure of a single network node is presented. A suggested, novel block structure of the node model facilitates full implementation in the FPGA chip, circuit standardization and parametrization, as well as integration of functional and diagnostic layers. A general method for pipeline system design was derived. This method is based on a unified model of the synchronous data network node. A few examples of practically realized, FPGA-based, pipeline measurement systems were presented. The described systems were applied in ZEUS and CMS.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design and Test of an Event Detector for the ReflectoActive Seals System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stinson, Brad J

2006-05-01

The purpose of this thesis was to research, design, develop and test a novel instrument for detecting fiber optic loop continuity and spatially locating fiber optic breaches. The work is for an active seal system called ReflectoActive Seals whose purpose is to provide real time container tamper indication. A Field Programmable Gate Array was used to implement a loop continuity detector and a spatial breach locator based on a high acquisition speed single photon counting optical time domain reflectometer. Communication and other control features were added in order to create a usable instrument that met defined requirements. A host graphicalmore » user interface was developed to illustrate system use and performance. The resulting device meets performance specifications by exhibiting a dynamic range of 27dB and a spatial resolution of 1.5 ft. The communication scheme used expands installation options and allows the device to communicate to a central host via existing Local Area Networks and/or the Internet.« less

Design and Test of an Event Detector and Locator for the ReflectoActive Seals System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stinson, Brad J

2006-06-01

The purpose of this work was to research, design, develop and test a novel instrument for detecting fiber optic loop continuity and spatially locating fiber optic breaches. The work is for an active seal system called ReflectoActive{trademark} Seals whose purpose is to provide real time container tamper indication. A Field Programmable Gate Array was used to implement a loop continuity detector and a spatial breach locator based on a high acquisition speed single photon counting optical time domain reflectometer. Communication and other control features were added in order to create a usable instrument that met defined requirements. A host graphicalmore » user interface was developed to illustrate system use and performance. The resulting device meets performance specifications by exhibiting a dynamic range of 27dB and a spatial resolution of 1.5 ft. The communication scheme used expands installation options and allows the device to communicate to a central host via existing Local Area Networks and/or the Internet.« less

A firmware-defined digital direct-sampling NMR spectrometer for condensed matter physics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pikulski, M., E-mail: marekp@ethz.ch; Shiroka, T.; Ott, H.-R.

2014-09-15

We report on the design and implementation of a new digital, broad-band nuclear magnetic resonance (NMR) spectrometer suitable for probing condensed matter. The spectrometer uses direct sampling in both transmission and reception. It relies on a single, commercially-available signal processing device with a user-accessible field-programmable gate array (FPGA). Its functions are defined exclusively by the FPGA firmware and the application software. Besides allowing for fast replication, flexibility, and extensibility, our software-based solution preserves the option to reuse the components for other projects. The device operates up to 400 MHz without, and up to 800 MHz with undersampling, respectively. Digital down-conversion with ±10 MHzmore » passband is provided on the receiver side. The system supports high repetition rates and has virtually no intrinsic dead time. We describe briefly how the spectrometer integrates into the experimental setup and present test data which demonstrates that its performance is competitive with that of conventional designs.« less

Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments

DOE PAGES

Brusati, M.; Camplani, A.; Cannon, M.; ...

2017-02-20

SRAM-ba8ed Field Programmable Gate Array (FPGA) logic devices arc very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which ismore » a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. :!\\litigation techniques such as Triple Modular Redundancy (T:t\\IR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).« less

FPGA-Based Smart Sensor for Online Displacement Measurements Using a Heterodyne Interferometer

PubMed Central

Vera-Salas, Luis Alberto; Moreno-Tapia, Sandra Veronica; Garcia-Perez, Arturo; de Jesus Romero-Troncoso, Rene; Osornio-Rios, Roque Alfredo; Serroukh, Ibrahim; Cabal-Yepez, Eduardo

2011-01-01

The measurement of small displacements on the nanometric scale demands metrological systems of high accuracy and precision. In this context, interferometer-based displacement measurements have become the main tools used for traceable dimensional metrology. The different industrial applications in which small displacement measurements are employed requires the use of online measurements, high speed processes, open architecture control systems, as well as good adaptability to specific process conditions. The main contribution of this work is the development of a smart sensor for large displacement measurement based on phase measurement which achieves high accuracy and resolution, designed to be used with a commercial heterodyne interferometer. The system is based on a low-cost Field Programmable Gate Array (FPGA) allowing the integration of several functions in a single portable device. This system is optimal for high speed applications where online measurement is needed and the reconfigurability feature allows the addition of different modules for error compensation, as might be required by a specific application. PMID:22164040

FPGA-Based Optical Cavity Phase Stabilization for Coherent Pulse Stacking

DOE PAGES

Xu, Yilun; Wilcox, Russell; Byrd, John; ...

2017-11-20

Coherent pulse stacking (CPS) is a new time-domain coherent addition technique that stacks several optical pulses into a single output pulse, enabling high pulse energy from fiber lasers. We develop a robust, scalable, and distributed digital control system with firmware and software integration for algorithms, to support the CPS application. We model CPS as a digital filter in the Z domain and implement a pulse-pattern-based cavity phase detection algorithm on an field-programmable gate array (FPGA). A two-stage (2+1 cavities) 15-pulse stacking system achieves an 11.0 peak-power enhancement factor. Each optical cavity is fed back at 1.5kHz, and stabilized at anmore » individually-prescribed round-trip phase with 0.7deg and 2.1deg rms phase errors for Stages 1 and 2, respectively. Optical cavity phase control with nanometer accuracy ensures 1.2% intensity stability of the stacked pulse over 12 h. The FPGA-based feedback control system can be scaled to large numbers of optical cavities.« less

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

A firmware-defined digital direct-sampling NMR spectrometer for condensed matter physics.

PubMed

Pikulski, M; Shiroka, T; Ott, H-R; Mesot, J

2014-09-01

We report on the design and implementation of a new digital, broad-band nuclear magnetic resonance (NMR) spectrometer suitable for probing condensed matter. The spectrometer uses direct sampling in both transmission and reception. It relies on a single, commercially-available signal processing device with a user-accessible field-programmable gate array (FPGA). Its functions are defined exclusively by the FPGA firmware and the application software. Besides allowing for fast replication, flexibility, and extensibility, our software-based solution preserves the option to reuse the components for other projects. The device operates up to 400 MHz without, and up to 800 MHz with undersampling, respectively. Digital down-conversion with ±10 MHz passband is provided on the receiver side. The system supports high repetition rates and has virtually no intrinsic dead time. We describe briefly how the spectrometer integrates into the experimental setup and present test data which demonstrates that its performance is competitive with that of conventional designs.

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

PubMed

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-12-15

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.

FPGA-Based Optical Cavity Phase Stabilization for Coherent Pulse Stacking

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu, Yilun; Wilcox, Russell; Byrd, John

Coherent pulse stacking (CPS) is a new time-domain coherent addition technique that stacks several optical pulses into a single output pulse, enabling high pulse energy from fiber lasers. We develop a robust, scalable, and distributed digital control system with firmware and software integration for algorithms, to support the CPS application. We model CPS as a digital filter in the Z domain and implement a pulse-pattern-based cavity phase detection algorithm on an field-programmable gate array (FPGA). A two-stage (2+1 cavities) 15-pulse stacking system achieves an 11.0 peak-power enhancement factor. Each optical cavity is fed back at 1.5kHz, and stabilized at anmore » individually-prescribed round-trip phase with 0.7deg and 2.1deg rms phase errors for Stages 1 and 2, respectively. Optical cavity phase control with nanometer accuracy ensures 1.2% intensity stability of the stacked pulse over 12 h. The FPGA-based feedback control system can be scaled to large numbers of optical cavities.« less

APS Storage Ring Monopulse RF BPM Upgrade

NASA Astrophysics Data System (ADS)

Lill, R.; Pietryla, A.; Norum, E.; Lenkszus, F.

2004-11-01

The Advanced Photon Source (APS) is a third-generation synchrotron light source in its ninth year of operation. The storage ring monopulse radio frequency (rf) beam position monitor (BPM) was designed to measure single-turn and multi-turn beam positions for operations and machine physics studies. Many of the components used in the original design are obsolete and costly to replace. In this paper we present a proposal to upgrade the monopulse rf BPMs in which the existing system hardware is repartitioned and the aging data acquisition system is replaced. By replacing only the data acquisition system, we will demonstrate a cost-effective approach to improved beam stability, reliability, and enhanced postmortem capabilities. An eight-channel ADC/digitizer VXI board with sampling rate of up to 105 MHz (per channel) and 14-bit resolution coupled with a field-programmable gate array and embedded central processing will provide the flexibility to revitalize this system for another decade of operation. We will discuss the upgrade system specifications, design, and prototype test results.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Dynamic tracking down-conversion signal processing method based on reference signal for grating heterodyne interferometer

NASA Astrophysics Data System (ADS)

Wang, Guochao; Yan, Shuhua; Zhou, Weihong; Gu, Chenhui

2012-08-01

Traditional displacement measurement systems by grating, which purely make use of fringe intensity to implement fringe count and subdivision, have rigid demands for signal quality and measurement condition, so they are not easy to realize measurement with nanometer precision. Displacement measurement with the dual-wavelength and single-grating design takes advantage of the single grating diffraction theory and the heterodyne interference theory, solving quite well the contradiction between large range and high precision in grating displacement measurement. To obtain nanometer resolution and nanometer precision, high-power subdivision of interference fringes must be realized accurately. A dynamic tracking down-conversion signal processing method based on the reference signal is proposed. Accordingly, a digital phase measurement module to realize high-power subdivision on field programmable gate array (FPGA) was designed, as well as a dynamic tracking down-conversion module using phase-locked loop (PLL). Experiments validated that a carrier signal after down-conversion can constantly maintain close to 100 kHz, and the phase-measurement resolution and phase precision are more than 0.05 and 0.2 deg, respectively. The displacement resolution and the displacement precision, corresponding to the phase results, are 0.139 and 0.556 nm, respectively.

An FPGA Implementation to Detect Selective Cationic Antibacterial Peptides

PubMed Central

Polanco González, Carlos; Nuño Maganda, Marco Aurelio; Arias-Estrada, Miguel; del Rio, Gabriel

2011-01-01

Exhaustive prediction of physicochemical properties of peptide sequences is used in different areas of biological research. One example is the identification of selective cationic antibacterial peptides (SCAPs), which may be used in the treatment of different diseases. Due to the discrete nature of peptide sequences, the physicochemical properties calculation is considered a high-performance computing problem. A competitive solution for this class of problems is to embed algorithms into dedicated hardware. In the present work we present the adaptation, design and implementation of an algorithm for SCAPs prediction into a Field Programmable Gate Array (FPGA) platform. Four physicochemical properties codes useful in the identification of peptide sequences with potential selective antibacterial activity were implemented into an FPGA board. The speed-up gained in a single-copy implementation was up to 108 times compared with a single Intel processor cycle for cycle. The inherent scalability of our design allows for replication of this code into multiple FPGA cards and consequently improvements in speed are possible. Our results show the first embedded SCAPs prediction solution described and constitutes the grounds to efficiently perform the exhaustive analysis of the sequence-physicochemical properties relationship of peptides. PMID:21738652

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Autonomous Telemetry Collection for Single-Processor Small Satellites

NASA Technical Reports Server (NTRS)

Speer, Dave

2003-01-01

For the Space Technology 5 mission, which is being developed under NASA's New Millennium Program, a single spacecraft processor will be required to do on-board real-time computations and operations associated with attitude control, up-link and down-link communications, science data processing, solid-state recorder management, power switching and battery charge management, experiment data collection, health and status data collection, etc. Much of the health and status information is in analog form, and each of the analog signals must be routed to the input of an analog-to-digital converter, converted to digital form, and then stored in memory. If the micro-operations of the analog data collection process are implemented in software, the processor may use up a lot of time either waiting for the analog signal to settle, waiting for the analog-to-digital conversion to complete, or servicing a large number of high frequency interrupts. In order to off-load a very busy processor, the collection and digitization of all analog spacecraft health and status data will be done autonomously by a field-programmable gate array that can configure the analog signal chain, control the analog-to-digital converter, and store the converted data in memory.

Versatile and Programmable DNA Logic Gates on Universal and Label-Free Homogeneous Electrochemical Platform.

PubMed

Ge, Lei; Wang, Wenxiao; Sun, Ximei; Hou, Ting; Li, Feng

2016-10-04

Herein, a novel universal and label-free homogeneous electrochemical platform is demonstrated, on which a complete set of DNA-based two-input Boolean logic gates (OR, NAND, AND, NOR, INHIBIT, IMPLICATION, XOR, and XNOR) is constructed by simply and rationally deploying the designed DNA polymerization/nicking machines without complicated sequence modulation. Single-stranded DNA is employed as the proof-of-concept target/input to initiate or prevent the DNA polymerization/nicking cyclic reactions on these DNA machines to synthesize numerous intact G-quadruplex sequences or binary G-quadruplex subunits as the output. The generated output strands then self-assemble into G-quadruplexes that render remarkable decrease to the diffusion current response of methylene blue and, thus, provide the amplified homogeneous electrochemical readout signal not only for the logic gate operations but also for the ultrasensitive detection of the target/input. This system represents the first example of homogeneous electrochemical logic operation. Importantly, the proposed homogeneous electrochemical logic gates possess the input/output homogeneity and share a constant output threshold value. Moreover, the modular design of DNA polymerization/nicking machines enables the adaptation of these homogeneous electrochemical logic gates to various input and output sequences. The results of this study demonstrate the versatility and universality of the label-free homogeneous electrochemical platform in the design of biomolecular logic gates and provide a potential platform for the further development of large-scale DNA-based biocomputing circuits and advanced biosensors for multiple molecular targets.

Phase-matching of attosecond XUV supercontinuum

NASA Astrophysics Data System (ADS)

Gilbertson, Steve; Mashiko, Hiroki; Li, Chengquan; Khan, Sabih; Shakya, Mahendra; Moon, Eric; Chang, Zenghu

2008-05-01

Adding a weak second harmonic field to an ellipticity dependent polarization gating field allowed for the production of XUV supercontinua from longer (˜10 fs) input pulses in argon. The spectra support 200 as single isolated pulses. This technique, dubbed double optical gating (DOG), demonstrated a large enhancement of the harmonic yield as compared with polarization gating. These results can be attributed to the reduced depletion of the ground state of the target from the leading edge of the pulse and the increased intensity inside the polarization gate width. Through optimization of the harmonic generation process under the phase matching conditions, we were able to further increase the harmonic flux. The parameters included the target gas pressure, laser focus position, input pulse duration, and polarization gate width. By varying the CE phase of the pulse, we were able to verify that the results were indeed from DOG due to its unique 2 pi dependence on the harmonic spectrum. We were able to extend our results to neon. Its higher ionization potential allowed an extension of the harmonic cutoff for the production of even shorter pulses.

Strain and deformations engineered germanene bilayer double gate-field effect transistor by first principles

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Chandrasekaran, Gopalakrishnan; Kasmir Raja, S. V.

2017-10-01

Germanene, silicene, stanene, phosphorene and graphene are some of single atomic materials with novel properties. In this paper, we explored bilayer germanene-based Double Gate-Field Effect Transistor (DG-FET) with various strains and deformations using Density Functional Theory (DFT) and Green's approach by first-principle calculations. The DG-FET of 1.6 nm width, 6 nm channel length (Lch) and HfO2 as gate dielectric has been modeled. For intrinsic deformation of germanene bilayer, we have enforced minute mechanical deformation of wrap and twist (5°) and ripple (0.5 Å) on germanene bilayer channel material. By using NEGF formalism, I-V Characteristics of various strains and deformation tailored DG-FET was calculated. Our results show that rough edge and single vacancy (5-9) in bilayer germanene diminishes the current around 47% and 58% respectively as compared with pristine bilayer germanene. In case of strain tailored bilayer DG-FET, multiple NDR regions were observed which can be utilized in building stable multiple logic states in digital circuits and high frequency oscillators using negative resistive techniques.

Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

High-Fidelity Single-Shot Toffoli Gate via Quantum Control.

PubMed

Zahedinejad, Ehsan; Ghosh, Joydip; Sanders, Barry C

2015-05-22

A single-shot Toffoli, or controlled-controlled-not, gate is desirable for classical and quantum information processing. The Toffoli gate alone is universal for reversible computing and, accompanied by the Hadamard gate, forms a universal gate set for quantum computing. The Toffoli gate is also a key ingredient for (nontopological) quantum error correction. Currently Toffoli gates are achieved by decomposing into sequentially implemented single- and two-qubit gates, which require much longer times and yields lower overall fidelities compared to a single-shot implementation. We develop a quantum-control procedure to construct a single-shot Toffoli gate for three nearest-neighbor-coupled superconducting transmon systems such that the fidelity is 99.9% and is as fast as an entangling two-qubit gate under the same realistic conditions. The gate is achieved by a nongreedy quantum control procedure using our enhanced version of the differential evolution algorithm.

Triple-mode single-transistor graphene amplifier and its applications.

PubMed

Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

2010-10-26

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.

Splash 2

NASA Technical Reports Server (NTRS)

Arnold, Jeffrey M.; Buell, Duncan A.; Kleinfelder, Walter J.

1993-01-01

Splash 2 is an attached processor system for Sun SPARC 2 workstations that uses Xilinx 4010 Field Programmable Gate Arrays (FPGA's) as its processing elements. The purpose of this paper is to describe Splash 2. The predecessor system, Splash 1, was designed to be used as a systolic processing system. Although it was very successful in that mode, there were many other applications that were not systolic, but which were successful, nonetheless, on Splash 1, or that were not implemented successfully due to one or more architectural limitations, most notably I/O bandwidth and interprocessor communication. Although other uses to increase computational performance have been found for the Xilinx FPGA's that are Splash's processing elements. Splash is unique in its goal to be programmable in a general sense.

FPGA-Based Multiprocessor System for Injection Molding Control

PubMed Central

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

2012-01-01

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

Resistance modulation in VO2 nanowires induced by an electric field via air-gap gates

NASA Astrophysics Data System (ADS)

Kanki, Teruo; Chikanari, Masashi; Wei, Tingting; Tanaka, Hidekazu; The Institute of Scientific; Industrial Research Team

Vanadium dioxide (VO2) shows huge resistance change with metal-insulator transition (MIT) at around room temperature. Controlling of the MIT by applying an electric field is a topical ongoing research toward the realization of Mott transistor. In this study, we have successfully switched channel resistance of VO2 nano-wire channels by a pure electrostatic field effect using a side-gate-type field-effect transistor (SG-FET) viaair gap and found that single crystalline VO2 nanowires and the channels with narrower width enhance transport modulation rate. The rate of change in resistance ((R0-R)/R, where R0 and R is the resistance of VO2 channel with off state and on state gate voltage (VG) , respectively) was 0.42 % at VG = 30 V in in-plane poly-crystalline VO2 channels on Al2O3(0001) substrates, while the rate in single crystalline channels on TiO2 (001) substrates was 3.84 %, which was 9 times higher than that using the poly-crystalline channels. With reducing wire width from 3000 nm to 400 nm of VO2 on TiO2 (001) substrate, furthermore, resistance modulation ratio enhanced from 0.67 % to 3.84 %. This change can not be explained by a simple free-electron model. In this presentation, we will compare the electronic properties between in-plane polycrystalline VO2 on Al2O3 (0001) and single crystalline VO2 on TiO2 (001) substrates, and show experimental data in detail..

Encoders for block-circulant LDPC codes

NASA Technical Reports Server (NTRS)

Andrews, Kenneth; Dolinar, Sam; Thorpe, Jeremy

2005-01-01

In this paper, we present two encoding methods for block-circulant LDPC codes. The first is an iterative encoding method based on the erasure decoding algorithm, and the computations required are well organized due to the block-circulant structure of the parity check matrix. The second method uses block-circulant generator matrices, and the encoders are very similar to those for recursive convolutional codes. Some encoders of the second type have been implemented in a small Field Programmable Gate Array (FPGA) and operate at 100 Msymbols/second.

Performance of a segmented HPGe detector at KRISS.

PubMed

Han, Jubong; Lee, K B; Lee, Jong-Man; Lee, S H; Park, Tae Soon; Oh, J S

2018-04-01

A 24 segmented HPGe coaxial detector was set up with a digitized data acquisition system (DAQ). The DAQ was composed of a digitizer (5 × 10 7 sampling/s), a Field-Programmable Gate Array (FPGA), and a real time operating system. The Full Width Half Maximum (FWHM), rise time, signal characteristics, and spectra of a 137 Cs source were evaluated. The data were processed using an in-house developed gamma-ray tracking system. Copyright © 2017 Elsevier Ltd. All rights reserved.

Optimization of a Fast Neutron Scintillator for Real-Time Pulse Shape Discrimination in the Transient Reactor Test Facility (TREAT) Hodoscope

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnson, James T.; Thompson, Scott J.; Watson, Scott M.

We present a multi-channel, fast neutron/gamma ray detector array system that utilizes ZnS(Ag) scintillator detectors. The system employs field programmable gate arrays (FPGAs) to do real-time all digital neutron/gamma ray discrimination with pulse height and time histograms to allow count rates in excess of 1,000,000 pulses per second per channel. The system detector number is scalable in blocks of 16 channels.

Development of a Crosstalk Suppression Algorithm for KID Readout

NASA Astrophysics Data System (ADS)

Lee, Kyungmin; Ishitsuka, H.; Oguri, S.; Suzuki, J.; Tajima, O.; Tomita, N.; Won, Eunil; Yoshida, M.

2018-06-01

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing

DTIC Science & Technology

2012-03-01

receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select an input port. The input...dual of a merge. It receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select...Transactions on Computer-Aided Design of Intergrated Circuits and Systems, Vol. 26, No. 2, February 2007. [12] Cadence Design Systems, “Clock Domain

Fly-By-Light/Power-By-Wire Fault-Tolerant Fiber-Optic Backplane

NASA Technical Reports Server (NTRS)

Malekpour, Mahyar R.

2002-01-01

The design and development of a fault-tolerant fiber-optic backplane to demonstrate feasibility of such architecture is presented. The simulation results of test cases on the backplane in the advent of induced faults are presented, and the fault recovery capability of the architecture is demonstrated. The architecture was designed, developed, and implemented using the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). The architecture was synthesized and implemented in hardware using Field Programmable Gate Arrays (FPGA) on multiple prototype boards.

Real-time Kalman filter: Cooling of an optically levitated nanoparticle

NASA Astrophysics Data System (ADS)

Setter, Ashley; Toroš, Marko; Ralph, Jason F.; Ulbricht, Hendrik

2018-03-01

We demonstrate that a Kalman filter applied to estimate the position of an optically levitated nanoparticle, and operated in real-time within a field programmable gate array, is sufficient to perform closed-loop parametric feedback cooling of the center-of-mass motion to sub-Kelvin temperatures. The translational center-of-mass motion along the optical axis of the trapped nanoparticle has been cooled by 3 orders of magnitude, from a temperature of 300 K to a temperature of 162 ±15 mK.

Note: Digital laser frequency auto-locking for inter-satellite laser ranging

DOE Office of Scientific and Technical Information (OSTI.GOV)

Luo, Yingxin; Yeh, Hsien-Chi, E-mail: yexianji@mail.hust.edu.cn; Li, Hongyin

2016-05-15

We present a prototype of a laser frequency auto-locking and re-locking control system designed for laser frequency stabilization in inter-satellite laser ranging system. The controller has been implemented on field programmable gate arrays and programmed with LabVIEW software. The controller allows initial frequency calibrating and lock-in of a free-running laser to a Fabry-Pérot cavity. Since it allows automatic recovery from unlocked conditions, benefit derives to automated in-orbit operations. Program design and experimental results are demonstrated.

Parallel algorithm for computation of second-order sequential best rotations

NASA Astrophysics Data System (ADS)

Redif, Soydan; Kasap, Server

2013-12-01

Algorithms for computing an approximate polynomial matrix eigenvalue decomposition of para-Hermitian systems have emerged as a powerful, generic signal processing tool. A technique that has shown much success in this regard is the sequential best rotation (SBR2) algorithm. Proposed is a scheme for parallelising SBR2 with a view to exploiting the modern architectural features and inherent parallelism of field-programmable gate array (FPGA) technology. Experiments show that the proposed scheme can achieve low execution times while requiring minimal FPGA resources.

Digital intermediate frequency QAM modulator using parallel processing

DOEpatents

Pao, Hsueh-Yuan [Livermore, CA; Tran, Binh-Nien [San Ramon, CA

2008-05-27

The digital Intermediate Frequency (IF) modulator applies to various modulation types and offers a simple and low cost method to implement a high-speed digital IF modulator using field programmable gate arrays (FPGAs). The architecture eliminates multipliers and sequential processing by storing the pre-computed modulated cosine and sine carriers in ROM look-up-tables (LUTs). The high-speed input data stream is parallel processed using the corresponding LUTs, which reduces the main processing speed, allowing the use of low cost FPGAs.

Upset Characterization of the PowerPC405 Hard-core Processor Embedded in Virtex-II Pro Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Swift, Gary M.; Allen, Gregory S.; Farmanesh, Farhad; George, Jeffrey; Petrick, David J.; Chayab, Fayez

2006-01-01

Shown in this presentation are recent results for the upset susceptibility of the various types of memory elements in the embedded PowerPC405 in the Xilinx V2P40 FPGA. For critical flight designs where configuration upsets are mitigated effectively through appropriate design triplication and configuration scrubbing, these upsets of processor elements can dominate the system error rate. Data from irradiations with both protons and heavy ions are given and compared using available models.

Performance Evaluation of a Field Programmable Gate Array-Based System for Detecting and Tracking Peer-to-Peer Protocols on a Gigabit Ethernet Network

DTIC Science & Technology

2010-06-01

Ron’s Code 4 . . . . . . . . . . . . . . . . . . . 18 2.3.3 Virtual Private Network and Secure Shell Tunnels 19 2.3.4 Darknets ...created using Iodine. 2.2 Analyzing and Classifying Network Traffic Before the advent of Darknets and anonymizers like Tor (see Section 2.3), ana... darknets , and the Tor network. 2.3.1 Byte Padding. Byte padding is the most primitive obfuscation method used to hide payloads in network traffic. When byte

Asymmetric Core Computing for U.S. Army High-Performance Computing Applications

DTIC Science & Technology

2009-04-01

Playstation 4 (should one be announced). 8 4.2 FPGAs Reconfigurable computing refers to performing computations using Field Programmable Gate Arrays...2008 4 . TITLE AND SUBTITLE Asymmetric Core Computing for U.S. Army High-Performance Computing Applications 5a. CONTRACT NUMBER 5b. GRANT NUMBER...Acknowledgments vi  1.  Introduction 1  2.  Relevant Technologies 2  3.  Technical Approach 5  4 .  Research and Development Highlights 7  4.1  Cell

Radiation Tolerant, FPGA-Based SmallSat Computer System

NASA Technical Reports Server (NTRS)

LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

2015-01-01

The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

Combine Flash-Based FPGA TID and Long-Term Retention Reliabilities Through VT Shift

NASA Astrophysics Data System (ADS)

Wang, Jih-Jong; Rezzak, Nadia; Dsilva, Durwyn; Xue, Fengliang; Samiee, Salim; Singaraju, Pavan; Jia, James; Nguyen, Victor; Hawley, Frank; Hamdy, Esmat

2016-08-01

Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are presented. Long-chain inverter design is recommended for reliability evaluation because it is the worst case design for both effects. Based on preliminary test data, both issues are unified and modeled by one natural decay equation. The relative contributions of TID induced threshold-voltage shift and retention mechanisms are evaluated by analyzing test data.

Respiratory gating and multifield technique radiotherapy for esophageal cancer.

PubMed

Ohta, Atsushi; Kaidu, Motoki; Tanabe, Satoshi; Utsunomiya, Satoru; Sasamoto, Ryuta; Maruyama, Katsuya; Tanaka, Kensuke; Saito, Hirotake; Nakano, Toshimichi; Shioi, Miki; Takahashi, Haruna; Kushima, Naotaka; Abe, Eisuke; Aoyama, Hidefumi

2017-03-01

To investigate the effects of a respiratory gating and multifield technique on the dose-volume histogram (DVH) in radiotherapy for esophageal cancer. Twenty patients who underwent four-dimensional computed tomography for esophageal cancer were included. We retrospectively created the four treatment plans for each patient, with or without the respiratory gating and multifield technique: No gating-2-field, No gating-4-field, Gating-2-field, and Gating-4-field plans. We compared the DVH parameters of the lung and heart in the No gating-2-field plan with the other three plans. In the comparison of the parameters in the No gating-2-field plan, there are significant differences in the Lung V 5Gy , V 20Gy , mean dose with all three plans and the Heart V 25Gy -V 40Gy with Gating-2-field plan, V 35Gy , V 40Gy , mean dose with No Gating-4-field plan and V 30Gy -V 40Gy , and mean dose with Gating-4-field plan. The lung parameters were smaller in the Gating-2-field plan and larger in the No gating-4-field and Gating-4-field plans. The heart parameters were all larger in the No gating-2-field plan. The lung parameters were reduced by the respiratory gating technique and increased by the multifield technique. The heart parameters were reduced by both techniques. It is important to select the optimal technique according to the risk of complications.

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

NASA Astrophysics Data System (ADS)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Gatemon Benchmarking and Two-Qubit Operation

NASA Astrophysics Data System (ADS)

Casparis, Lucas; Larsen, Thorvald; Olsen, Michael; Petersson, Karl; Kuemmeth, Ferdinand; Krogstrup, Peter; Nygard, Jesper; Marcus, Charles

Recent experiments have demonstrated superconducting transmon qubits with semiconductor nanowire Josephson junctions. These hybrid gatemon qubits utilize field effect tunability singular to semiconductors to allow complete qubit control using gate voltages, potentially a technological advantage over conventional flux-controlled transmons. Here, we present experiments with a two-qubit gatemon circuit. We characterize qubit coherence and stability and use randomized benchmarking to demonstrate single-qubit gate errors of ~0.5 % for all gates, including voltage-controlled Z rotations. We show coherent capacitive coupling between two gatemons and coherent SWAP operations. Finally, we perform a two-qubit controlled-phase gate with an estimated fidelity of ~91 %, demonstrating the potential of gatemon qubits for building scalable quantum processors. We acknowledge financial support from Microsoft Project Q and the Danish National Research Foundation.

Analogue spin-orbit torque device for artificial-neural-network-based associative memory operation

NASA Astrophysics Data System (ADS)

Borders, William A.; Akima, Hisanao; Fukami, Shunsuke; Moriya, Satoshi; Kurihara, Shouta; Horio, Yoshihiko; Sato, Shigeo; Ohno, Hideo

2017-01-01

We demonstrate associative memory operations reminiscent of the brain using nonvolatile spintronics devices. Antiferromagnet-ferromagnet bilayer-based Hall devices, which show analogue-like spin-orbit torque switching under zero magnetic fields and behave as artificial synapses, are used. An artificial neural network is used to associate memorized patterns from their noisy versions. We develop a network consisting of a field-programmable gate array and 36 spin-orbit torque devices. An effect of learning on associative memory operations is successfully confirmed for several 3 × 3-block patterns. A discussion on the present approach for realizing spintronics-based artificial intelligence is given.

Characteristics of camel-gate structures with active doping channel profiles

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui; Lour, Wen-Shiung; Laih, Lih-Wen; Liu, Rong-Chau; Liu, Wen-Chau

1996-03-01

In this paper, we demonstrate the influence of channel doping profile on the performances of camel-gate field effect transistors (CAMFETs). For comparison, single and tri-step doping channel structures with identical doping thickness products are employed, while other parameters are kept unchanged. The results of a theoretical analysis show that the single doping channel FET with lightly doping active layer has higher barrier height and drain-source saturation current. However, the transconductance is decreased. For a tri-step doping channel structure, it is found that the output drain-source saturation current and the barrier height are enhanced. Furthermore, the relatively voltage independent performances are improved. Two CAMFETs with single and tri-step doping channel structures have been fabricated and discussed. The devices exhibit nearly voltage independent transconductances of 144 mS mm -1 and 222 mS mm -1 for single and tri-step doping channel CAMFETs, respectively. The operation gate voltage may extend to ± 1.5 V for a tri-step doping channel CAMFET. In addition, the drain current densities of > 750 and 405 mA mm -1 are obtained for the tri-step and single doping CAMFETs. These experimental results are inconsistent with theoretical analysis.

Space charge effects on the current-voltage characteristics of gated field emitter arrays

NASA Astrophysics Data System (ADS)

Jensen, K. L.; Kodis, M. A.; Murphy, R. A.; Zaidman, E. G.

1997-07-01

Microfabricated field emitter arrays (FEAs) can provide the very high electron current densities required for rf amplifier applications, typically on the order of 100 A/cm2. Determining the dependence of emission current on gate voltage is important for the prediction of emitter performance for device applications. Field emitters use high applied fields to extract current, and therefore, unlike thermionic emitters, the current densities can exceed 103A/cm2 when averaged over an array. At such high current densities, space charge effects (i.e., the influence of charge between cathode and collector on emission) affect the emission process or initiate conditions which can lead to failure mechanisms for field emitters. A simple model of a field emitter will be used to calculate the one-dimensional space charge effects on the emission characteristics by examining two components: charge between the gate and anode, which leads to Child's law, and charge within the FEA unit cell, which gives rise to a field suppression effect which can exist for a single field emitter. The predictions of the analytical model are compared with recent experimental measurements designed to assess space charge effects and predict the onset of gate current. It is shown that negative convexity on a Fowler-Nordheim plot of Ianode(Vgate) data can be explained in terms of field depression at the emitter tip in addition to reflection of electrons by a virtual cathode created when the anode field is insufficient to extract all of the current; in particular, the effects present within the unit cell constitute a newly described effect.

Re-Verification of the IRHN57133SE and IRHN57250SE for Single Event Gate Rupture and Single Event Burnout

NASA Technical Reports Server (NTRS)

Scheick, Leif

2010-01-01

The vertical metal oxide semiconductor field-effect transistor (MOSFET) is a widely used power transistor onboard a spacecraft. The MOSFET is typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single event gate rupture (SEGR) or single event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. These radiation hardened devices are not immune to SEGR or SEB but, rather, can exhibit them at a much more damaging ion than their non-radiation hardened counterparts. See [1] through [5] for more information.This effort was to investigate the SEGR and SEB responses of two power MOSFETs from IR(the IRHN57133SE and the IRHN57250SE) that have recently been produced on a new fabrication line. These tests will serve as a limited verification of these parts, but it is acknowledged that further testing on the respective parts may be needed for some mission profiles.

Local gate control in carbon nanotube quantum devices

NASA Astrophysics Data System (ADS)

Biercuk, Michael Jordan

This thesis presents transport measurements of carbon nanotube electronic devices operated in the quantum regime. Nanotubes are contacted by source and drain electrodes, and multiple lithographically-patterned electrostatic gates are aligned to each device. Transport measurements of device conductance or current as a function of local gate voltages reveal that local gates couple primarily to the proximal section of the nanotube, hence providing spatially localized control over carrier density along the nanotube length. Further, using several different techniques we are able to produce local depletion regions along the length of a tube. This phenomenon is explored in detail for different contact metals to the nanotube. We utilize local gating techniques to study multiple quantum dots in carbon nanotubes produced both by naturally occurring defects, and by the controlled application of voltages to depletion gates. We study double quantum dots in detail, where transport measurements reveal honeycomb charge stability diagrams. We extract values of energy-level spacings, capacitances, and interaction energies for this system, and demonstrate independent control over all relevant tunneling rates. We report rf-reflectometry measurements of gate-defined carbon nanotube quantum dots with integrated charge sensors. Aluminum rf-SETs are electrostatically coupled to carbon nanotube devices and detect single electron charging phenomena in the Coulomb blockade regime. Simultaneous correlated measurements of single electron charging are made using reflected rf power from the nanotube itself and from the rf-SET on microsecond time scales. We map charge stability diagrams for the nanotube quantum dot via charge sensing, observing Coulomb charging diamonds beyond the first order. Conductance measurements of carbon nanotubes containing gated local depletion regions exhibit plateaus as a function of gate voltage, spaced by approximately 1e2/h, the quantum of conductance for a single (non-degenerate) mode. Plateau structure is investigated as a function of bias voltage, temperature, and magnetic field. We speculate on the origin of this surprising quantization, which appears to lack band and spin degeneracy.

Fully integrated free-running InGaAs/InP single-photon detector for accurate lidar applications.

PubMed

Yu, Chao; Shangguan, Mingjia; Xia, Haiyun; Zhang, Jun; Dou, Xiankang; Pan, Jian-Wei

2017-06-26

We present a fully integrated InGaAs/InP negative feedback avalanche diode (NFAD) based free-running single-photon detector (SPD) designed for accurate lidar applications. A free-piston Stirling cooler is used to cool down the NFAD with a large temperature range, and an active hold-off circuit implemented in a field programmable gate array is applied to further suppress the afterpulsing contribution. The key parameters of the free-running SPD including photon detection efficiency (PDE), dark count rate (DCR), afterpulse probability, and maximum count rate (MCR) are dedicatedly optimized for lidar application in practice. We then perform a field experiment using a Mie lidar system with 20 kHz pulse repetition frequency to compare the performance between the free-running InGaAs/InP SPD and a commercial superconducting nanowire single-photon detector (SNSPD). Our detector exhibits good performance with 1.6 Mcps MCR (0.6 μs hold-off time), 10% PDE, 950 cps DCR, and 18% afterpulse probability over 50 μs period. Such performance is worse than the SNSPD with 60% PDE and 300 cps DCR. However, after performing a specific algorithm that we have developed for afterpulse and count rate corrections, the lidar system performance in terms of range-corrected signal (Pr 2 ) distribution using our SPD agrees very well with the result using the SNSPD, with only a relative error of ∼2%. Due to the advantages of low-cost and small size of InGaAs/InP NFADs, such detector provides a practical solution for accurate lidar applications.

Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

NASA Astrophysics Data System (ADS)

Abedini-Nassab, Roozbeh

Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into integrated circuits, I have built devices which are capable of organizing a precise number of cells into individually addressable array sites, similar to how a random access memory (RAM) stores electronic data. My programmable magnetic circuits allow for the organization of both cells and single-cell pairs into large arrays. Single cells can also potentially be retrieved for downstream high-throughput genomic analysis. In order to enhance the efficiency of the tool and to increase the delivery speed of the particles, I have also developed microfluidics systems that are combined with the magnetophoretic circuits. This hybrid system, called magnetomicrofluidics, is capable of rapidly organizing an array of particles and cells with the high precision and control. I have also shown that cells can be grown inside these chips for multiple days, enabling the long-term phenotypic analysis of rare cellular events. These types of studies can reveal important insights about the intercellular signaling networks and answer crucial questions in biology and immunology.

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

NASA Astrophysics Data System (ADS)

Yan, Shi-Li; Xie, Zhi-Jian; Chen, Jian-Hao; Taniguchi, Takashi; Watanabe, Kenji

2017-03-01

The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus (BP) by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10V/nm to 0.83V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronics, thermoelectric power generation and thermal imaging.

High on/off ratios in bilayer graphene field effect transistors realized by surface dopants.

PubMed

Szafranek, B N; Schall, D; Otto, M; Neumaier, D; Kurz, H

2011-07-13

The unique property of bilayer graphene to show a band gap tunable by external electrical fields enables a variety of different device concepts with novel functionalities for electronic, optoelectronic, and sensor applications. So far the operation of bilayer graphene-based field effect transistors requires two individual gates to vary the channel's conductance and to create a band gap. In this paper, we report on a method to increase the on/off ratio in single gated bilayer graphene field effect transistors by adsorbate doping. The adsorbate dopants on the upper side of the graphene establish a displacement field perpendicular to the graphene surface breaking the inversion symmetry of the two graphene layers. Low-temperature measurements indicate that the increased on/off ratio is caused by the opening of a mobility gap.

MEMS based highly sensitive dual FET gas sensor using graphene decorated Pd-Ag alloy nanoparticles for H2 detection.

PubMed

Sharma, Bharat; Kim, Jung-Sik

2018-04-12

A low power, dual-gate field-effect transistor (FET) hydrogen gas sensor with graphene decorated Pd-Ag for hydrogen sensing applications was developed. The FET hydrogen sensor was integrated with a graphene-Pd-Ag-gate FET (GPA-FET) as hydrogen sensor coupled with Pt-gate FET as a reference sensor on a single sensor platform. The sensing gate electrode was modified with graphene by an e-spray technique followed by Pd-Ag DC/MF sputtering. Morphological and structural properties were studied by FESEM and Raman spectroscopy. FEM simulations were performed to confirm the uniform temperature control at the sensing gate electrode. The GPA-FET showed a high sensing response to hydrogen gas at the temperature of 25~254.5 °C. The as-proposed FET H 2 sensor showed the fast response time and recovery time of 16 s, 14 s, respectively at the operating temperature of 245 °C. The variation in drain current was positively related with increased working temperature and hydrogen concentration. The proposed dual-gate FET gas sensor in this study has potential applications in various fields, such as electronic noses and automobiles, owing to its low-power consumption, easy integration, good thermal stability and enhanced hydrogen sensing properties.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Mobility overestimation due to gated contacts in organic field-effect transistors

PubMed Central

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

Medical diagnosis using adaptive perceptive particle swarm optimization and its hardware realization using field programmable gate array.

PubMed

Chowdhury, Shubhajit Roy; Chakrabarti, Dipankar; Hiranmay, Saha

2009-12-01

The paper proposes to develop a field programmable gate array (FPGA) based low cost, low power and high speed novel diagnostic system that can detect in absence of the physician the approaching critical condition of a patient at an early stage and is thus suitable for diagnosis of patients in the rural areas of developing countries where availability of physicians and availability of power is really scarce. The diagnostic system could be installed in health care centres of rural areas where patients can register themselves for periodic diagnoses and thereby detect potential health hazards at an early stage. Multiple pathophysiological parameters with different weights are involved in diagnosing a particular disease. A novel variation of particle swarm optimization called as adaptive perceptive particle swarm optimization has been proposed to determine the optimal weights of these pathophysiological parameters for a more accurate diagnosis. The FPGA based smart system has been applied for early detection of renal criticality of patients. For renal diagnosis, body mass index, glucose, urea, creatinine, systolic and diastolic blood pressures have been considered as pathophysiological parameters. The detection of approaching critical condition of a patient by the instrument has also been validated with the standard Cockford Gault Equation to verify whether the patient is really approaching a critical condition or not. Using Bayesian analysis on the population of 80 patients under study an accuracy of up to 97.5% in renal diagnosis has been obtained.

Design techniques for a stable operation of cryogenic field-programmable gate arrays.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Image processing with cellular nonlinear networks implemented on field-programmable gate arrays for real-time applications in nuclear fusion

DOE Office of Scientific and Technical Information (OSTI.GOV)

Palazzo, S.; Vagliasindi, G.; Arena, P.

2010-08-15

In the past years cameras have become increasingly common tools in scientific applications. They are now quite systematically used in magnetic confinement fusion, to the point that infrared imaging is starting to be used systematically for real-time machine protection in major devices. However, in order to guarantee that the control system can always react rapidly in case of critical situations, the time required for the processing of the images must be as predictable as possible. The approach described in this paper combines the new computational paradigm of cellular nonlinear networks (CNNs) with field-programmable gate arrays and has been tested inmore » an application for the detection of hot spots on the plasma facing components in JET. The developed system is able to perform real-time hot spot recognition, by processing the image stream captured by JET wide angle infrared camera, with the guarantee that computational time is constant and deterministic. The statistical results obtained from a quite extensive set of examples show that this solution approximates very well an ad hoc serial software algorithm, with no false or missed alarms and an almost perfect overlapping of alarm intervals. The computational time can be reduced to a millisecond time scale for 8 bit 496x560-sized images. Moreover, in our implementation, the computational time, besides being deterministic, is practically independent of the number of iterations performed by the CNN - unlike software CNN implementations.« less

Design techniques for a stable operation of cryogenic field-programmable gate arrays

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Fringe pattern demodulation using the one-dimensional continuous wavelet transform: field-programmable gate array implementation.

PubMed

Abid, Abdulbasit

2013-03-01

This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

Gate-tunable carbon nanotube-MoS2 heterojunction p-n diode.

PubMed

Jariwala, Deep; Sangwan, Vinod K; Wu, Chung-Chiang; Prabhumirashi, Pradyumna L; Geier, Michael L; Marks, Tobin J; Lauhon, Lincoln J; Hersam, Mark C

2013-11-05

The p-n junction diode and field-effect transistor are the two most ubiquitous building blocks of modern electronics and optoelectronics. In recent years, the emergence of reduced dimensionality materials has suggested that these components can be scaled down to atomic thicknesses. Although high-performance field-effect devices have been achieved from monolayered materials and their heterostructures, a p-n heterojunction diode derived from ultrathin materials is notably absent and constrains the fabrication of complex electronic and optoelectronic circuits. Here we demonstrate a gate-tunable p-n heterojunction diode using semiconducting single-walled carbon nanotubes (SWCNTs) and single-layer molybdenum disulfide as p-type and n-type semiconductors, respectively. The vertical stacking of these two direct band gap semiconductors forms a heterojunction with electrical characteristics that can be tuned with an applied gate bias to achieve a wide range of charge transport behavior ranging from insulating to rectifying with forward-to-reverse bias current ratios exceeding 10(4). This heterojunction diode also responds strongly to optical irradiation with an external quantum efficiency of 25% and fast photoresponse <15 μs. Because SWCNTs have a diverse range of electrical properties as a function of chirality and an increasing number of atomically thin 2D nanomaterials are being isolated, the gate-tunable p-n heterojunction concept presented here should be widely generalizable to realize diverse ultrathin, high-performance electronics and optoelectronics.

Gate-tunable carbon nanotube–MoS2 heterojunction p-n diode

PubMed Central

Jariwala, Deep; Sangwan, Vinod K.; Wu, Chung-Chiang; Prabhumirashi, Pradyumna L.; Geier, Michael L.; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2013-01-01

The p-n junction diode and field-effect transistor are the two most ubiquitous building blocks of modern electronics and optoelectronics. In recent years, the emergence of reduced dimensionality materials has suggested that these components can be scaled down to atomic thicknesses. Although high-performance field-effect devices have been achieved from monolayered materials and their heterostructures, a p-n heterojunction diode derived from ultrathin materials is notably absent and constrains the fabrication of complex electronic and optoelectronic circuits. Here we demonstrate a gate-tunable p-n heterojunction diode using semiconducting single-walled carbon nanotubes (SWCNTs) and single-layer molybdenum disulfide as p-type and n-type semiconductors, respectively. The vertical stacking of these two direct band gap semiconductors forms a heterojunction with electrical characteristics that can be tuned with an applied gate bias to achieve a wide range of charge transport behavior ranging from insulating to rectifying with forward-to-reverse bias current ratios exceeding 104. This heterojunction diode also responds strongly to optical irradiation with an external quantum efficiency of 25% and fast photoresponse <15 μs. Because SWCNTs have a diverse range of electrical properties as a function of chirality and an increasing number of atomically thin 2D nanomaterials are being isolated, the gate-tunable p-n heterojunction concept presented here should be widely generalizable to realize diverse ultrathin, high-performance electronics and optoelectronics. PMID:24145425

Experimental Primer on the Trapped Ion Quantum Computer

DTIC Science & Technology

1998-01-01

analogously), then exposing this ion to a traveling- wave electric field E�r� � E0 cos �k rÿ wLt � j� with frequency wL, phase j, and wavevector k, results...eih�a�a y��ij � Sjÿ eÿih�a�a y�ÿij� �4� in a frame rotating at wL, where terms oscillating faster than W j �Wj wz; w0� have been neglected. Here, h...of the single bit rotation gate and the two-bit controlled-NOT gate [34]. For brevity, we concentrate on these two gates and how they can be

Tuning charge and correlation effects for a single molecule on a graphene device

DOE PAGES

Wickenburg, Sebastian; Lu, Jiong; Lischner, Johannes; ...

2016-11-25

The ability to understand and control the electronic properties of individual molecules in a device environment is crucial for developing future technologies at the nanometre scale and below. Achieving this, however, requires the creation of three-terminal devices that allow single molecules to be both gated and imaged at the atomic scale. We have accomplished this by integrating a graphene field effect transistor with a scanning tunnelling microscope, thus allowing gate-controlled charging and spectroscopic interrogation of individual tetrafluoro-tetracyanoquinodimethane molecules. We observe a non-rigid shift in the molecule’s lowest unoccupied molecular orbital energy (relative to the Dirac point) as a function ofmore » gate voltage due to graphene polarization effects. Our results show that electron–electron interactions play an important role in how molecular energy levels align to the graphene Dirac point, and may significantly influence charge transport through individual molecules incorporated in graphene-based nanodevices.« less

Pulse transmission transmitter including a higher order time derivate filter

DOEpatents

Dress, Jr., William B.; Smith, Stephen F.

2003-09-23

Systems and methods for pulse-transmission low-power communication modes are disclosed. A pulse transmission transmitter includes: a clock; a pseudorandom polynomial generator coupled to the clock, the pseudorandom polynomial generator having a polynomial load input; an exclusive-OR gate coupled to the pseudorandom polynomial generator, the exclusive-OR gate having a serial data input; a programmable delay circuit coupled to both the clock and the exclusive-OR gate; a pulse generator coupled to the programmable delay circuit; and a higher order time derivative filter coupled to the pulse generator. The systems and methods significantly reduce lower-frequency emissions from pulse transmission spread-spectrum communication modes, which reduces potentially harmful interference to existing radio frequency services and users and also simultaneously permit transmission of multiple data bits by utilizing specific pulse shapes.

Programmable logic controller performance enhancement by field programmable gate array based design.

PubMed

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification

PubMed Central

Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

2012-01-01

This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs. PMID:22778640

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

PubMed Central

Ou, Chien-Min; Li, Hui-Ya; Hwang, Wen-Jyi

2012-01-01

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

Debye screening in single-molecule carbon nanotube field-effect sensors.

PubMed

Sorgenfrei, Sebastian; Chiu, Chien-Yang; Johnston, Matthew; Nuckolls, Colin; Shepard, Kenneth L

2011-09-14

Point-functionalized carbon nanotube field-effect transistors can serve as highly sensitive detectors for biomolecules. With a probe molecule covalently bound to a defect in the nanotube sidewall, two-level random telegraph noise (RTN) in the conductance of the device is observed as a result of a charged target biomolecule binding and unbinding at the defect site. Charge in proximity to the defect modulates the potential (and transmission) of the conductance-limiting barrier created by the defect. In this Letter, we study how these single-molecule electronic sensors are affected by ionic screening. Both charge in proximity to the defect site and buffer concentration are found to affect RTN amplitude in a manner that follows from simple Debye length considerations. RTN amplitude is also dependent on the potential of the electrolyte gate as applied to the reference electrode; at high enough gate potentials, the target DNA is completely repelled and RTN is suppressed.

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

Gate-Tuned Thermoelectric Power in Black Phosphorus.

PubMed

Saito, Yu; Iizuka, Takahiko; Koretsune, Takashi; Arita, Ryotaro; Shimizu, Sunao; Iwasa, Yoshihiro

2016-08-10

The electric field effect is a useful means of elucidating intrinsic material properties as well as for designing functional devices. The electric-double-layer transistor (EDLT) enables the control of carrier density in a wide range, which is recently proved to be an effective tool for the investigation of thermoelectric properties. Here, we report the gate-tuning of thermoelectric power in a black phosphorus (BP) single crystal flake with the thickness of 40 nm. Using an EDLT configuration, we successfully control the thermoelectric power (S) and find that the S of ion-gated BP reached +510 μV/K at 210 K in the hole depleted state, which is much higher than the reported bulk single crystal value of +340 μV/K at 300 K. We compared this experimental data with the first-principles-based calculation and found that this enhancement is qualitatively explained by the effective thinning of the conduction channel of the BP flake and nonuniformity of the channel owing to the gate operation in a depletion mode. Our results provide new opportunities for further engineering BP as a thermoelectric material in nanoscale.

Measurement system of correlation functions of microwave single photon source in real time

NASA Astrophysics Data System (ADS)

Korenkov, A.; Dmitriev, A.; Astafiev, O.

2018-02-01

Several quantum setups, such as quantum key distribution networks[1] and quantum simulators (e.g. boson sampling), by their design rely on single photon sources (SPSs). These quantum setups were demonstrated to operate in optical frequency domain. However, following the steady advances in circuit quantum electrodynamics, a proposal has been made recently[2] to demonstrate boson sampling with microwave photons. This in turn requires the development of reliable microwave SPS. It's one of the most important characteristics are the first-order and the second-order correlation functions g1 and g2. The measurement technique of g1 and g2 is significantly different from that in the optical domain [3],[4] because of the current unavailability of microwave single-photon detectors. In particular, due to high levels of noise present in the system a substantial amount of statistics in needed to be acquired. This work presents a platform for measurement of g1 and g2 that processes the incoming data in real time, maximizing the efficiency of data acquisition. The use of field-programmable gate array (FPGA) electronics, common in similar experiments[3] but complex in programming, is avoided; instead, the calculations are performed on a standard desktop computer. The platform is used to perform the measurements of the first-order and the second-order correlation functions of the microwave SPS.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

2016-11-01

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Underwater single beam circumferentially scanning detection system using range-gated receiver and adaptive filter

NASA Astrophysics Data System (ADS)

Tan, Yayun; Zhang, He; Zha, Bingting

2017-09-01

Underwater target detection and ranging in seawater are of interest in unmanned underwater vehicles. This study presents an underwater detection system that synchronously scans a collimated laser beam and a narrow field of view to circumferentially detect an underwater target. Hybrid methods of range-gated and variable step-size least mean squares (VSS-LMS) adaptive filter are proposed to suppress water backscattering. The range-gated receiver eliminates the backscattering of near-field water. The VSS-LMS filter extracts the target echo in the remaining backscattering and the constant fraction discriminator timing method is used to improve ranging accuracy. The optimal constant fraction is selected by analysing the jitter noise and slope of the target echo. The prototype of the underwater detection system is constructed and tested in coastal seawater, then the effectiveness of backscattering suppression and high-ranging accuracy is verified through experimental results and analysis discussed in this paper.

Optimal Synthesis of the Joint Unitary Evolutions

NASA Astrophysics Data System (ADS)

Wei, Hai-Rui; Alsaedi, Ahmed; Hobiny, Aatef; Deng, Fu-Guo; Hu, Hui; Zhang, Dun

2018-07-01

Joint unitary operations play a central role in quantum communication and computation. We give a quantum circuit for implementing a type of unconstructed useful joint unitary evolutions in terms of controlled-NOT (CNOT) gates and single-qubit rotations. Our synthesis is optimal and possible in experiment. Two CNOT gates and seven R x , R y or R z rotations are required for our synthesis, and the arbitrary parameter contained in the evolutions can be controlled by local Hamiltonian or external fields.

Optimal Synthesis of the Joint Unitary Evolutions

NASA Astrophysics Data System (ADS)

Wei, Hai-Rui; Alsaedi, Ahmed; Hobiny, Aatef; Deng, Fu-Guo; Hu, Hui; Zhang, Dun

2018-03-01

Joint unitary operations play a central role in quantum communication and computation. We give a quantum circuit for implementing a type of unconstructed useful joint unitary evolutions in terms of controlled-NOT (CNOT) gates and single-qubit rotations. Our synthesis is optimal and possible in experiment. Two CNOT gates and seven R x , R y or R z rotations are required for our synthesis, and the arbitrary parameter contained in the evolutions can be controlled by local Hamiltonian or external fields.

The Contribution of a Particular "Kids in Parks" Programme to the Professional Development of Teachers

ERIC Educational Resources Information Center

Ferreira, J. G.

2014-01-01

This article considers the possible contribution of the "kids in parks" programme offered at Golden Gate Highlands National Park to the professional development of teachers. Focus group interviews were held with teachers who participated in the programme, and an interview with open-ended questions was held with a learning facilitator…

Expanding Access, Participation, and Success in International Baccalaureate Programmes: Year 1 Documentation Report

ERIC Educational Resources Information Center

Corcoran, Thomas B.; Gerry, Gail B.

2010-01-01

In fall 2009, the Bill and Melinda Gates Foundation funded a three-year project (IB Access Project) with International Baccalaureate (IB) to increase participation of minority students and students in poverty in the Middle Years Programme (MYP) and Diploma Programme (DP). The IB Access Project seeks to do four things: (1) Improve teacher practice…

A novel biomimetic sonarhead using beamforming technology to mimic bat echolocation.

PubMed

Steckel, Jan; Peremans, Herbert

2012-07-01

A novel biomimetic sonarhead has been developed to allow researchers of bat echolocation behavior and biomimetic sonar to perform experiments with a system similar to the bat¿s sensory system. The bat's echolocation-related transfer function (ERTF) is implemented using an array of receivers to implement the head-related transfer function (HRTF), and an array of emitters mounted on a cylindrical manifold to implement the emission pattern of the bat. The complete system is controlled by a field-programmable gate array (FPGA) based embedded system connected through a USB interface.

Characterization and Implementation of a Real-World Target Tracking Algorithm on Field Programmable Gate Arrays with Kalman Filter Test Case

DTIC Science & Technology

2008-03-01

to predict its exact position. To locate Ceres, Carl Friedrich Gauss , a mere 24 years old at the time, developed a method called least-squares...dividend to produce the quotient. This method converges to the reciprocal quadratically [11]. For the special case of: 1 H × P (:, :, k)×H ′ + R (3.9) the...high-speed computation of reciprocals within the overall system. The Newton-Raphson method is also expanded for use in calculat- ing square-roots in

Spaceborne Hybrid-FPGA System for Processing FTIR Data

NASA Technical Reports Server (NTRS)

Bekker, Dmitriy; Blavier, Jean-Francois L.; Pingree, Paula J.; Lukowiak, Marcin; Shaaban, Muhammad

2008-01-01

Progress has been made in a continuing effort to develop a spaceborne computer system for processing readout data from a Fourier-transform infrared (FTIR) spectrometer to reduce the volume of data transmitted to Earth. The approach followed in this effort, oriented toward reducing design time and reducing the size and weight of the spectrometer electronics, has been to exploit the versatility of recently developed hybrid field-programmable gate arrays (FPGAs) to run diverse software on embedded processors while also taking advantage of the reconfigurable hardware resources of the FPGAs.

Note: Design of FPGA based system identification module with application to atomic force microscopy

NASA Astrophysics Data System (ADS)

Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

2018-05-01

The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

NASA Astrophysics Data System (ADS)

Rais, Muhammad H.; Qasim, Syed M.

2010-06-01

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Radiation Hardened 10BASE-T Ethernet Physical Layer (PHY)

NASA Technical Reports Server (NTRS)

Lin, Michael R. (Inventor); Petrick, David J. (Inventor); Ballou, Kevin M. (Inventor); Espinosa, Daniel C. (Inventor); James, Edward F. (Inventor); Kliesner, Matthew A. (Inventor)

2017-01-01

Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Report on Mars Odyssey Independent Assessment Team Activities

NASA Technical Reports Server (NTRS)

Barto, R.; Day, John H. (Technical Monitor)

2001-01-01

During the week of March 26, 2001, I was asked by Rich Katz, NASA-GSFC, to participate on the Mars Odyssey Independent Assessment Team (IAT) that would investigate the implications of the failure of an Actel RP 1280 Field Programmable Gate Array (FPGA), which occurred on the Space Infrared Telescope Facility (SIRTF) spacecraft, on the Mars Odyssey spacecraft that was set to launch on April 7, 2001. We were provided with review materials from JPL and Lockheed Martin (LMA) that would be discussed at a meeting on April 2, 2001.

A Reconfigurable Communications System for Small Spacecraft

NASA Technical Reports Server (NTRS)

Chu, Pong P.; Kifle, Muli

2004-01-01

Two trends of NASA missions are the use of multiple small spacecraft and the development of an integrated space network. To achieve these goals, a robust and agile communications system is needed. Advancements in field programmable gate array (FPGA) technology have made it possible to incorporate major communication and network functionalities in FPGA chips; thus this technology has great potential as the basis for a reconfigurable communications system. This report discusses the requirements of future space communications, reviews relevant issues, and proposes a methodology to design and construct a reconfigurable communications system for small scientific spacecraft.

Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Supinski, B.; Caliga, D.

2017-09-28

The primary objective of this project was to develop memory optimization technology to efficiently deliver data to, and distribute data within, the SRC-6's Field Programmable Gate Array- ("FPGA") based Multi-Adaptive Processors (MAPs). The hardware/software approach was to explore efficient MAP configurations and generate the compiler technology to exploit those configurations. This memory accessing technology represents an important step towards making reconfigurable symmetric multi-processor (SMP) architectures that will be a costeffective solution for large-scale scientific computing.

Challenges Regarding IP Core Functional Reliability

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.

2017-01-01

For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.

A real-time multi-gases detection and concentration measurements based-on time-division multiplexed-lasers

NASA Astrophysics Data System (ADS)

Yazdandoust, Fatemeh; Tatenguem Fankem, Hervé; Milde, Tobias; Jimenez, Alvaro; Sacher, Joachim

2018-02-01

We report the development of a platform, based-on a Field-Programmable Gate Arrays (FPGAs) and suitable for Time-Division-Multiplexed DFB lasers. The designed platform is subsequently combined with a spectroscopy setup, for detection and quantification of species in a gas mixture. The experimental results show a detection limit of 460 ppm, an uncertainty of 0.1% and a computation time of less than 1000 clock cycles. The proposed system offers a high level of flexibility and is applicable to arbitrary types of gas-mixtures.

Single-Shot Quantum Nondemolition Detection of Individual Itinerant Microwave Photons

NASA Astrophysics Data System (ADS)

Besse, Jean-Claude; Gasparinetti, Simone; Collodo, Michele C.; Walter, Theo; Kurpiers, Philipp; Pechal, Marek; Eichler, Christopher; Wallraff, Andreas

2018-04-01

Single-photon detection is an essential component in many experiments in quantum optics, but it remains challenging in the microwave domain. We realize a quantum nondemolition detector for propagating microwave photons and characterize its performance using a single-photon source. To this aim, we implement a cavity-assisted conditional phase gate between the incoming photon and a superconducting artificial atom. By reading out the state of this atom in a single shot, we reach an external (internal) photon-detection fidelity of 50% (71%), limited by transmission efficiency between the source and the detector (75%) and the coherence properties of the qubit. By characterizing the coherence and average number of photons in the field reflected off the detector, we demonstrate its quantum nondemolition nature. We envisage applications in generating heralded remote entanglement between qubits and for realizing logic gates between propagating microwave photons.

Quantum information processing by weaving quantum Talbot carpets

NASA Astrophysics Data System (ADS)

Farías, Osvaldo Jiménez; de Melo, Fernando; Milman, Pérola; Walborn, Stephen P.

2015-06-01

Single-photon interference due to passage through a periodic grating is considered in a novel proposal for processing D -dimensional quantum systems (quDits) encoded in the spatial degrees of freedom of light. We show that free-space propagation naturally implements basic single-quDit gates by means of the Talbot effect: an intricate time-space carpet of light in the near-field diffraction regime. By adding a diagonal phase gate, we show that a complete set of single-quDit gates can be implemented. We then introduce a spatially dependent beam splitter that allows for projective measurements in the computational basis and can be used for the implementation of controlled operations between two quDits. Universal quantum information processing can then be implemented with linear optics and ancilla photons via postselection and feed-forward following the original proposal of Knill-Laflamme and Milburn. Although we consider photons, our scheme should be directly applicable to a number of other physical systems. Interpretation of the Talbot effect as a quantum logic operation provides a beautiful and interesting way to visualize quantum computation through wave propagation and interference.

Highly efficient gate-tunable photocurrent generation in vertical heterostructures of layered materials

PubMed Central

Yu, Woo Jong; Liu, Yuan; Zhou, Hailong; Yin, Anxiang; Li, Zheng; Huang, Yu

2014-01-01

Layered materials of graphene and MoS2, for example, have recently emerged as an exciting material system for future electronics and optoelectronics. Vertical integration of layered materials can enable the design of novel electronic and photonic devices. Here, we report highly efficient photocurrent generation from vertical heterostructures of layered materials. We show that vertically stacked graphene–MoS2–graphene and graphene–MoS2–metal junctions can be created with a broad junction area for efficient photon harvesting. The weak electrostatic screening effect of graphene allows the integration of single or dual gates under and/or above the vertical heterostructure to tune the band slope and photocurrent generation. We demonstrate that the amplitude and polarity of the photocurrent in the gated vertical heterostructures can be readily modulated by the electric field of an external gate to achieve a maximum external quantum efficiency of 55% and internal quantum efficiency up to 85%. Our study establishes a method to control photocarrier generation, separation and transport processes using an external electric field. PMID:24162001

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Photonic Programmable Tele-Cloning Network.

PubMed

Li, Wei; Chen, Ming-Cheng

2016-06-29

The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling.