Fabrication of thermal microphotonic sensors and sensor arrays

DOEpatents

Shaw, Michael J.; Watts, Michael R.; Nielson, Gregory N.

2010-10-26

A thermal microphotonic sensor is fabricated on a silicon substrate by etching an opening and a trench into the substrate, and then filling in the opening and trench with silicon oxide which can be deposited or formed by thermally oxidizing a portion of the silicon substrate surrounding the opening and trench. The silicon oxide forms a support post for an optical resonator which is subsequently formed from a layer of silicon nitride, and also forms a base for an optical waveguide formed from the silicon nitride layer. Part of the silicon substrate can be selectively etched away to elevate the waveguide and resonator. The thermal microphotonic sensor, which is useful to detect infrared radiation via a change in the evanescent coupling of light between the waveguide and resonator, can be formed as a single device or as an array.

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Mizoguchi, Seiya; Shimatani, Naoki; Kobayashi, Mizuki; Makino, Takaomi; Yamaoka, Yu; Kodera, Tetsuo

2018-04-01

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

Method of forming buried oxide layers in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2000-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

NASA Astrophysics Data System (ADS)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

Investigation of ZnSe-coated silicon substrates for GaAs solar cells

NASA Technical Reports Server (NTRS)

Huber, Daniel A.; Olsen, Larry C.; Dunham, Glen; Addis, F. William

1993-01-01

Studies are being carried out to determine the feasibility of using ZnSe as a buffer layer for GaAs solar cells grown on silicon. This study was motivated by reports in the literature indicating ZnSe films had been grown by metallorganic chemical vapor deposition (MOCVD) onto silicon with EPD values of 2 x 10(exp 5) cm(sup -2), even though the lattice mismatch between silicon and ZnSe is 4.16 percent. These results combined with the fact that ZnSe and GaAs are lattice matched to within 0.24 percent suggest that the prospects for growing high efficiency GaAs solar cells onto ZnSe-coated silicon are very good. Work to date has emphasized development of procedures for MOCVD growth of (100) ZnSe onto (100) silicon wafers, and subsequent growth of GaAs films on ZnSe/Si substrates. In order to grow high quality single crystal GaAs with a (100) orientation, which is desirable for solar cells, one must grow single crystal (100) ZnSe onto silicon substrates. A process for growth of (100) ZnSe was developed involving a two-step growth procedure at 450 C. Single crystal, (100) GaAs films were grown onto the (100) ZnSe/Si substrates at 610 C that are adherent and specular. Minority carrier diffusion lengths for the GaAs films grown on ZnSe/Si substrates were determined from photoresponse properties of Al/GaAs Schottky barriers. Diffusion lengths for n-type GaAs films are currently on the order of 0.3 microns compared to 2.0 microns for films grown simultaneously by homoepitaxy.

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

NASA Technical Reports Server (NTRS)

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Triple-junction thin-film silicon solar cell fabricated on periodically textured substrate with a stabilized efficiency of 13.6%

NASA Astrophysics Data System (ADS)

Sai, Hitoshi; Matsui, Takuya; Koida, Takashi; Matsubara, Koji; Kondo, Michio; Sugiyama, Shuichiro; Katayama, Hirotaka; Takeuchi, Yoshiaki; Yoshida, Isao

2015-05-01

We report a high-efficiency triple-junction thin-film silicon solar cell fabricated with the so-called substrate configuration. It was verified whether the design criteria for developing single-junction microcrystalline silicon (μc-Si:H) solar cells are applicable to multijunction solar cells. Furthermore, a notably high short-circuit current density of 32.9 mA/cm2 was achieved in a single-junction μc-Si:H cell fabricated on a periodically textured substrate with a high-mobility front transparent contacting layer. These technologies were also combined into a-Si:H/μc-Si:H/μc-Si:H triple-junction cells, and a world record stabilized efficiency of 13.6% was achieved.

Crystallization and growth of Ni-Si alloy thin films on inert and on silicon substrates

NASA Astrophysics Data System (ADS)

Grimberg, I.; Weiss, B. Z.

1995-04-01

The crystallization kinetics and thermal stability of NiSi2±0.2 alloy thin films coevaporated on two different substrates were studied. The substrates were: silicon single crystal [Si(100)] and thermally oxidized silicon single crystal. In situ resistance measurements, transmission electron microscopy, x-ray diffraction, Auger electron spectroscopy, and Rutherford backscattering spectroscopy were used. The postdeposition microstructure consisted of a mixture of amorphous and crystalline phases. The amorphous phase, independent of the composition, crystallizes homogeneously to NiSi2 at temperatures lower than 200 °C. The activation energy, determined in the range of 1.4-2.54 eV, depends on the type of the substrate and on the composition of the alloyed films. The activation energy for the alloys deposited on the inert substrate was found to be lower than for the alloys deposited on silicon single crystal. The lowest activation energy was obtained for nonstoichiometric NiSi2.2, the highest for NiSi2—on both substrates. The crystallization mode depends on the structure of the as-deposited films, especially the density of the existing crystalline nuclei. Substantial differences were observed in the thermal stability of the NiSi2 compound on both substrates. With the alloy films deposited on the Si substrate, only the NiSi2 phase was identified after annealing to temperatures up to 800 °C. In the films deposited on the inert substrate, NiSi and NiSi2 phases were identified when the Ni content in the alloy exceeded 33 at. %. The effects of composition and the type of substrate on the crystallization kinetics and thermal stability are discussed.

Integrated circuit with dissipative layer for photogenerated carriers

DOEpatents

Myers, D.R.

1988-04-20

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Gu, Jian

This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at pattern center is observed due to substrate enhanced edge heating. Single-grain silicon is obtained in a 50 nm x 100 nm rectangular pattern by super lateral growth (SLG). Narrow lines (such as 20-nm-wide) can serve as artificial heterogeneous nucleation sites during crystallization of large patterns, which could lead to the formation of single-crystal silicon islands in a controlled fashion. In addition to eximer laser annealing, NanoPAtterning and nickel-induced lateral C&barbelow;rystallization (NanoPAC) of a-Si lines is presented. Single-crystal silicon is achieved by NanoPAC. The line width of a-Si affects the grain structure of crystallized silicon lines significantly. Statistics show that single-crystal silicon is formed for all lines with width between 50 nm to 200 nm. Using in situ transmission electron microscopy (TEM), nickel-induced lateral crystallization (Ni-ILC) of a-Si inside a pattern is revealed; lithography-constrained single seeding (LISS) is proposed to explain the single-crystal formation. Intragrain line and two-dimensional defects are also studied. To test the electrical properties of NanoPAC silicon films, sub-100 nm thin-film transistors (TFTs) are fabricated using Patten-controlled crystallization of Ṯhin a-Si channel layer and H&barbelow;igh temperature (850°C) annealing, coined PaTH process. PaTH TFTs show excellent device performance over traditional solid phase crystallized (SPC) TFTs in terms of threshold voltage, threshold voltage roll-off, leakage current, subthreshold swing, on/off current ratio, device-to-device uniformity etc. Two-dimensional device simulations show that PaTH TFTs are comparable to silicon-on-insulator (SOI) devices, making it a promising candidate for the fabrication of future high performance, low-power 3D integrated circuits. Finally, an ultrafast nanolithography technique, laser-assisted direct imprint (LADI) is introduced. LADI shows the ability of patterning nanostructures directly in silicon in nanoseconds with sub-10 nm resolution. The process has potential applications in multiple disciplines, and could be extended to other materials and processes.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

The tensile effect on crack formation in single crystal silicon irradiated by intense pulsed ion beam

NASA Astrophysics Data System (ADS)

Liang, Guoying; Shen, Jie; Zhang, Jie; Zhong, Haowen; Cui, Xiaojun; Yan, Sha; Zhang, Xiaofu; Yu, Xiao; Le, Xiaoyun

2017-10-01

Improving antifatigue performance of silicon substrate is very important for the development of semiconductor industry. The cracking behavior of silicon under intense pulsed ion beam irradiation was studied by numerical simulation in order to understand the mechanism of induced surface peeling observed by experimental means. Using molecular dynamics simulation based on Stillinger Weber potential, tensile effect on crack growth and propagation in single crystal silicon was investigated. Simulation results reveal that stress-strain curves of single crystal silicon at a constant strain rate can be divided into three stages, which are not similar to metal stress-strain curves; different tensile load velocities induce difference of single silicon crack formation speed; the layered stress results in crack formation in single crystal silicon. It is concluded that the crack growth and propagation is more sensitive to strain rate, tensile load velocity, stress distribution in single crystal silicon.

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

NASA Technical Reports Server (NTRS)

Jhabvala, Murzy; Jhabvala, Christine A.; Ewin, Audrey J.; Hess, Larry A.; Hartmann, Thomas M.; La, Anh T.

2012-01-01

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Gauge Factor and Stretchability of Silicon-on-Polymer Strain Gauges

PubMed Central

Yang, Shixuan; Lu, Nanshu

2013-01-01

Strain gauges are widely applied to measure mechanical deformation of structures and specimens. While metallic foil gauges usually have a gauge factor slightly over 2, single crystalline silicon demonstrates intrinsic gauge factors as high as 200. Although silicon is an intrinsically stiff and brittle material, flexible and even stretchable strain gauges have been achieved by integrating thin silicon strips on soft and deformable polymer substrates. To achieve a fundamental understanding of the large variance in gauge factor and stretchability of reported flexible/stretchable silicon-on-polymer strain gauges, finite element and analytically models are established to reveal the effects of the length of the silicon strip, and the thickness and modulus of the polymer substrate. Analytical results for two limiting cases, i.e., infinitely thick substrate and infinitely long strip, have found good agreement with FEM results. We have discovered that strains in silicon resistor can vary by orders of magnitude with different substrate materials whereas strip length or substrate thickness only affects the strain level mildly. While the average strain in silicon reflects the gauge factor, the maximum strain in silicon governs the stretchability of the system. The tradeoff between gauge factor and stretchability of silicon-on-polymer strain gauges has been proposed and discussed. PMID:23881128

Hard carbon nitride and method for preparing same

DOEpatents

Haller, Eugene E.; Cohen, Marvin L.; Hansen, William L.

1992-01-01

Novel crystalline .alpha. (silicon nitride-like)-carbon nitride and .beta. (silicon nitride-like)-carbon nitride are formed by sputtering carbon in the presence of a nitrogen atmosphere onto a single crystal germanium or silicon, respectively, substrate.

Rough SERS substrate based on gold coated porous silicon layer prepared on the silicon backside surface

NASA Astrophysics Data System (ADS)

Dridi, H.; Haji, L.; Moadhen, A.

2017-04-01

We report in this paper a novel method to elaborate rough Surface Enhanced Raman Scattering (SERS) substrate. A single layer of porous silicon was formed on the silicon backside surface. Morphological characteristics of the porous silicon layer before and after gold deposition were influenced by the rough character (gold size). The reflectance measurements showed a dependence of the gold nano-grains size on the surface nature, through the Localized Surface Plasmon (LSP) band properties. SERS signal of Rhodamine 6G used as a model analyte, adsorbed on the rough porous silicon layer revealed a marked enhancement of its vibrational modes intensities.

Hard carbon nitride and method for preparing same

DOEpatents

Haller, E.E.; Cohen, M.L.; Hansen, W.L.

1992-05-05

Novel crystalline [alpha](silicon nitride-like)-carbon nitride and [beta](silicon nitride-like)-carbon nitride are formed by sputtering carbon in the presence of a nitrogen atmosphere onto a single crystal germanium or silicon, respectively, substrate. 1 figure.

Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias

NASA Astrophysics Data System (ADS)

Araga, Yuuki; Kikuchi, Katsuya; Aoyagi, Masahiro

2018-04-01

Substrate noise from a single through-silicon via (TSV) and the noise attenuation by a substrate tap and a guard ring are clarified. A CMOS test vehicle is designed, and 6-µm-diameter TSVs are manufactured on a 20-µm-thick silicon substrate by the via-last method. An on-chip waveform-capturing circuitry is embedded in the test vehicle to capture transient waveforms of substrate noise. The embedded waveform-capturing circuitry demonstrates small and local noise propagation. Experimental results show increased substrate noise level induced by TSVs and the effectiveness of the substrate tap and guard ring for mitigating the crosstalk among TSVs. An analytical model to explain substrate noise propagation is developed to validate experimental results. Results obtained using the substrate model with a multilayer mesh shows good consistency with experimental results, indicating that the model can be used for examination of noise suppression methods.

Solar cell circuit and method for manufacturing solar cells

NASA Technical Reports Server (NTRS)

Mardesich, Nick (Inventor)

2010-01-01

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Ultra-Thin Monocrystalline Silicon Solar Cell with 12.2% Efficiency Using Silicon-On-Insulator Substrate.

PubMed

Bian, Jian-Tao; Yu, Jian; Duan, Wei-Yuan; Qiu, Yu

2015-04-01

Single side heterojunction silicon solar cells were designed and fabricated using Silicon-On-Insulator (SOI) substrate. The TCAD software was used to simulate the effect of silicon layer thickness, doping concentration and the series resistance. A 10.5 µm thick monocrystalline silicon layer was epitaxially grown on the SOI with boron doping concentration of 2 x 10(16) cm(-3) by thermal CVD. Very high Voc of 678 mV was achieved by applying amorphous silicon heterojunction emitter on the front surface. The single cell efficiency of 12.2% was achieved without any light trapping structures. The rear surface recombination and the series resistance are the main limiting factors for the cell efficiency in addition to the c-Si thickness. By integrating an efficient light trapping scheme and further optimizing fabrication process, higher efficiency of 14.0% is expected for this type of cells. It can be applied to integrated circuits on a monolithic chip to meet the requirements of energy autonomous systems.

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Flexible single-crystal silicon nanomembrane photonic crystal cavity.

PubMed

Xu, Xiaochuan; Subbaraman, Harish; Chakravarty, Swapnajit; Hosseini, Amir; Covey, John; Yu, Yalin; Kwong, David; Zhang, Yang; Lai, Wei-Cheng; Zou, Yi; Lu, Nanshu; Chen, Ray T

2014-12-23

Flexible inorganic electronic devices promise numerous applications, especially in fields that could not be covered satisfactorily by conventional rigid devices. Benefits on a similar scale are also foreseeable for silicon photonic components. However, the difficulty in transferring intricate silicon photonic devices has deterred widespread development. In this paper, we demonstrate a flexible single-crystal silicon nanomembrane photonic crystal microcavity through a bonding and substrate removal approach. The transferred cavity shows a quality factor of 2.2×10(4) and could be bent to a curvature of 5 mm radius without deteriorating the performance compared to its counterparts on rigid substrates. A thorough characterization of the device reveals that the resonant wavelength is a linear function of the bending-induced strain. The device also shows a curvature-independent sensitivity to the ambient index variation.

Multi-junction solar cell device

DOEpatents

Friedman, Daniel J.; Geisz, John F.

2007-12-18

A multi-junction solar cell device (10) is provided. The multi-junction solar cell device (10) comprises either two or three active solar cells connected in series in a monolithic structure. The multi-junction device (10) comprises a bottom active cell (20) having a single-crystal silicon substrate base and an emitter layer (23). The multi-junction device (10) further comprises one or two subsequent active cells each having a base layer (32) and an emitter layer (23) with interconnecting tunnel junctions between each active cell. At least one layer that forms each of the top and middle active cells is composed of a single-crystal III-V semiconductor alloy that is substantially lattice-matched to the silicon substrate (22). The polarity of the active p-n junction cells is either p-on-n or n-on-p. The present invention further includes a method for substantially lattice matching single-crystal III-V semiconductor layers with the silicon substrate (22) by including boron and/or nitrogen in the chemical structure of these layers.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Harrison, W. B.; Wolner, H. A.; Hendrickson, G.; Nelson, L. D.

1976-01-01

To date, an experimental dip-coating facility was constructed. Using this facility, relatively thin (1 mm) mullite and alumina substrates were successfully dip-coated with 2.5 - 3.0 ohm-cm, p-type silicon with areas of approximately 20 sq cm. The thickness and grain size of these coatings are influenced by the temperature of the melt and the rate at which the substrate is pulled from the melt. One mullite substrate had dendrite-like crystallites of the order of 1 mm wide and 1 to 2 cm long. Their axes were aligned along the direction of pulling. A large variety of substrate materials were purchased or developed enabling the program to commence a substrate definition evaluation. Due to the insulating nature of the substrate, the bottom layer of the p-n junction may have to be made via the top surface. The feasibility of accomplishing this was demonstrated using single crystal wafers.

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1982-01-01

Ferroelectric films of barium titanate were synthesized on silicon and quartz substrates, and the photoelectric effect in the structure consisting of metal deposited ferroelectric barium titanate film silicon was studied. A photovoltage with polarity that depends on the direction of the remanent polarization was observed. The deposition of BaTiO3 on silicon and fused quartz substrates was accomplished by an rf sputtering technique. A series of experiments to study the growth of ferroelectric BaTiO3 films on single crystal silicon and fused quartz substrates were conducted. The ferroelectric character in these films was found on the basis of evidence from the polarization electric field hysteresis loops, capacitance voltage and capacitance temperature techniques and from X-ray diffraction studies.

Linewidth Narrowing and Purcell Enhancement in Photonic Crystal Cavities on an Er-Doped Silicon Nitride Platform

DTIC Science & Technology

2010-02-01

Low noise superconducting single photon detectors on silicon,” Appl. Phys. Lett. 93, 131101 (2008). 20. M. T. Tanner, C. M. Natarajan, V. K... wavelength sensitivity in NbTiN superconducting nanowire single-photon detectors fabricated on oxidized silicon substrates,” Proceedings of Single...cavity resonance wavelength and Q-factor for the PC cavity are shown in Figure 3. The data are taken both at low (0.050 mW) pump power and high (30 mW

Laser generation in microdisc resonators with InAs/GaAs quantum dots transferred on a silicon substrate

NASA Astrophysics Data System (ADS)

Nadtochiy, A. M.; Kryzhanovskaya, N. V.; Maximov, M. V.; Zhukov, A. E.; Moiseev, E. I.; Kulagina, M. M.; Vashanova, K. A.; Zadiranov, Yu. M.; Mukhin, I. S.; Arakcheeva, E. M.; Livshits, D.; Lipovskii, A. A.

2013-09-01

Microdisc resonators based on InAs/GaAs quantum dots separated from a GaAs substrate by selective etching and fixed to a silicon substrate by epoxy glue are studied using luminescence spectroscopy. A disc resonator 6 μm in diameter exhibits quasi-single-mode laser generation at a temperature of 78 K with a threshold power of 320 μW and λ/Δλ ˜ 27000.

Microstructure evolution of the Ir-inserted Ni silicides with additional annealing

NASA Astrophysics Data System (ADS)

Yoon, Kijeong; Song, Ohsung

2009-02-01

Thermally-evaporated 10 nm-Ni/1 nm-Ir/(poly)Si structures were fabricated in order to investigate the thermal stability of Ir-inserted nickel silicide after additional annealing. The silicide samples underwent rapid thermal annealing at 300 ° C to 1200 ° C for 40 s, followed by 30 min annealing at the given RTA temperatures. Silicides suitable for the salicide process were formed on the top of the single crystal and polycrystalline silicon substrates, mimicking actives and gates. The sheet resistance was measured using a four-point probe. High resolution x-ray diffraction and Auger depth profiling were used for phase and chemical composition analysis, respectively. Transmission electron microscope and scanning probe microscope were used to determine the cross-section structure and surface roughness. The silicide, which formed on single crystal silicon substrate with surface agglomeration after additional annealing, could defer the transformation of Ni(Ir)Si to Ni(Ir)Si2 and was stable at temperatures up to 1200 °C. Moreover, the silicide thickness doubled. There were no outstanding changes in the silicide thickness on polycrystalline silicon. However, after additional annealing, the silicon-silicide mixing became serious and showed high resistance at temperatures >700 °C. Auger depth profiling confirmed the increased thickness of the silicide layers after additional annealing without a change in composition. For a single crystal silicon substrate, the sheet resistance increased slightly due to the significant increases in surface roughness caused by surface agglomeration after additional annealing. Otherwise, there were almost no changes in surface roughness on the polycrystalline silicon substrate. The Ir-inserted nickel monosilicide was able to maintain a low resistance in a wide temperature range and is considered suitable for the nano-thick silicide process.

Studies of silicon p-n junction solar cells. [open circuit photovoltage

NASA Technical Reports Server (NTRS)

Lindholm, F. A.

1976-01-01

Single crystal silicon p-n junction solar cells made with low resistivity substrates show poorer solar energy conversion efficiency than traditional theory predicts. The physical mechanisms responsible for this discrepancy are identified and characterized. The open circuit voltage in shallow junction cells of about 0.1 ohm/cm substrate resistivity is investigated under AMO (one sun) conditions.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, A.M.

1995-03-07

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics. 15 figs.

Porous Silicon Covered with Silver Nanoparticles as Surface-Enhanced Raman Scattering (SERS) Substrate for Ultra-Low Concentration Detection.

PubMed

Kosović, Marin; Balarin, Maja; Ivanda, Mile; Đerek, Vedran; Marciuš, Marijan; Ristić, Mira; Gamulin, Ozren

2015-12-01

Microporous and macro-mesoporous silicon templates for surface-enhanced Raman scattering (SERS) substrates were produced by anodization of low doped p-type silicon wafers. By immersion plating in AgNO3, the templates were covered with silver metallic film consisting of different silver nanostructures. Scanning electron microscopy (SEM) micrographs of these SERS substrates showed diverse morphology with significant difference in an average size and size distribution of silver nanoparticles. Ultraviolet-visible-near-infrared (UV-Vis-NIR) reflection spectroscopy showed plasmonic absorption at 398 and 469 nm, which is in accordance with the SEM findings. The activity of the SERS substrates was tested using rhodamine 6G (R6G) dye molecules and 514.5 nm laser excitation. Contrary to the microporous silicon template, the SERS substrate prepared from macro-mesoporous silicon template showed significantly broader size distribution of irregular silver nanoparticles as well as localized surface plasmon resonance closer to excitation laser wavelength. Such silver morphology has high SERS sensitivity that enables ultralow concentration detection of R6G dye molecules up to 10(-15) M. To our knowledge, this is the lowest concentration detected of R6G dye molecules on porous silicon-based SERS substrates, which might even indicate possible single molecule detection.

Interaction of a single acetophenone molecule with group III-IV elements mediated by Si(001)

NASA Astrophysics Data System (ADS)

Racis, A.; Jurczyszyn, L.; Radny, M. W.

2018-03-01

A theoretical study of an influence of the acetophenone molecule adsorbed on the Si(001) on the local chemical reactivity of silicon surface is presented. The obtained results indicate that the interaction of the molecule with silicon substrate breaks the intra-dimer π bonds in four surface silicon dimers interacting directly with adsorbed molecule. This leads to the formation of two pairs of unpaired dangling bonds at two opposite sides of the molecule. It is demonstrated that these dangling bonds increase considerably the local chemical reactivity of the silicon substrate in the vicinity of the adsorbed molecule. Consequently, it is shown that such molecule bonded with Si(001) can stabilize the position of In and Pb adatoms diffusing on silicon substrate at two sides and initiate the one-dimensional aggregation of the metallic adatoms on the Si(001) substrate anchored at both sides of the adsorbed molecule. This type of aggregation leads to the growth of chain-like atomic structures in opposite directions, pinned to adsorbed molecule and oriented perpendicular to the rows of surface silicon dimers.

Effect of the substrate on the insulator-metal transition of vanadium dioxide films

NASA Astrophysics Data System (ADS)

Kovács, György J.; Bürger, Danilo; Skorupa, Ilona; Reuther, Helfried; Heller, René; Schmidt, Heidemarie

2011-03-01

Single-phase vanadium dioxide films grown on (0001) sapphire and (001) silicon substrates show a very different insulator-metal electronic transition. A detailed description of the growth mechanisms and the substrate-film interaction is given, and the characteristics of the electronic transition are described by the morphology and grain boundary structure. (Tri-)epitaxy-stabilized columnar growth of VO2 takes place on the sapphire substrate, whereas on silicon the expected Zone II growth is identified. We have found that in the case of the Si substrate the reasons for the broader hysteresis and the lower switching amplitude are the formation of an amorphous insulating VOx (x > 2.6) phase coexisting with VO2 and the high vanadium vacancy concentration of the VO2. These phenomena are the result of the excess oxygen during the growth and the interaction between the silicon substrate and the growing film.

Method of forming silicon structures with selectable optical characteristics

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor); Schowalter, Leo (Inventor)

1993-01-01

Silicon and metal are coevaporated onto a silicon substrate in a molecular beam epitaxy system with a larger than stoichiometric amount of silicon so as to epitaxially grow particles of metal silicide embedded in a matrix of single crystal epitaxially grown silicon. The particles interact with incident photons by resonant optical absorption at the surface plasmon resonance frequency. Controlling the substrate temperature and deposition rate and time allows the aspect ratio of the particles to be tailored to desired wavelength photons and polarizations. The plasmon energy may decay as excited charge carriers or phonons, either of which can be monitored to indicate the amount of incident radiation at the selected frequency and polarization.

Spectroellipsometric detection of silicon substrate damage caused by radiofrequency sputtering of niobium oxide

NASA Astrophysics Data System (ADS)

Lohner, Tivadar; Serényi, Miklós; Szilágyi, Edit; Zolnai, Zsolt; Czigány, Zsolt; Khánh, Nguyen Quoc; Petrik, Péter; Fried, Miklós

2017-11-01

Substrate surface damage induced by deposition of metal atoms by radiofrequency (rf) sputtering or ion beam sputtering onto single-crystalline silicon (c-Si) surface has been characterized earlier by electrical measurements. The question arises whether it is possible to characterize surface damage using spectroscopic ellipsometry (SE). In our experiments niobium oxide layers were deposited by rf sputtering on c-Si substrates in gas mixture of oxygen and argon. Multiple angle of incidence spectroscopic ellipsometry measurements were performed, a four-layer optical model (surface roughness layer, niobium oxide layer, native silicon oxide layer and ion implantation-amorphized silicon [i-a-Si] layer on a c-Si substrate) was created in order to evaluate the spectra. The evaluations yielded thicknesses of several nm for the i-a-Si layer. Better agreement could be achieved between the measured and the generated spectra by inserting a mixed layer (with components of c-Si and i-a-Si applying the effective medium approximation) between the silicon oxide layer and the c-Si substrate. High depth resolution Rutherford backscattering (RBS) measurements were performed to investigate the interface disorder between the deposited niobium oxide layer and the c-Si substrate. Atomic resolution cross-sectional transmission electron microscopy investigation was applied to visualize the details of the damaged subsurface region of the substrate.

A grating coupler with a trapezoidal hole array for perfectly vertical light coupling between optical fibers and waveguides

NASA Astrophysics Data System (ADS)

Mizutani, Akio; Eto, Yohei; Kikuta, Hisao

2017-12-01

A grating coupler with a trapezoidal hole array was designed and fabricated for perfectly vertical light coupling between a single-mode optical fiber and a silicon waveguide on a silicon-on-insulator (SOI) substrate. The grating coupler with an efficiency of 53% was computationally designed at a 1.1-µm-thick buried oxide (BOX) layer. The grating coupler and silicon waveguide were fabricated on the SOI substrate with a 3.0-µm-thick BOX layer by a single full-etch process. The measured coupling efficiency was 24% for TE-polarized light at 1528 nm wavelength, which was 0.69 times of the calculated coupling efficiency for the 3.0-µm-thick BOX layer.

Growing Cobalt Silicide Columns In Silicon

NASA Technical Reports Server (NTRS)

Fathauer, Obert W.

1991-01-01

Codeposition by molecular-beam epitaxy yields variety of structures. Proposed fabrication process produces three-dimensional nanometer-sized structures on silicon wafers. Enables control of dimensions of metal and semiconductor epitaxial layers in three dimensions instead of usual single dimension (perpendicular to the plane of the substrate). Process used to make arrays of highly efficient infrared sensors, high-speed transistors, and quantum wires. For fabrication of electronic devices, both shapes and locations of columns controlled. One possible technique for doing this electron-beam lithography, see "Making Submicron CoSi2 Structures on Silicon Substrates" (NPO-17736).

Lithographically defined few-electron silicon quantum dots based on a silicon-on-insulator substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horibe, Kosuke; Oda, Shunri; Kodera, Tetsuo, E-mail: kodera.t.ac@m.titech.ac.jp

2015-02-23

Silicon quantum dot (QD) devices with a proximal single-electron transistor (SET) charge sensor have been fabricated in a metal-oxide-semiconductor structure based on a silicon-on-insulator substrate. The charge state of the QDs was clearly read out using the charge sensor via the SET current. The lithographically defined small QDs enabled clear observation of the few-electron regime of a single QD and a double QD by charge sensing. Tunnel coupling on tunnel barriers of the QDs can be controlled by tuning the top-gate voltages, which can be used for manipulation of the spin quantum bit via exchange interaction between tunnel-coupled QDs. Themore » lithographically defined silicon QD device reported here is technologically simple and does not require electrical gates to create QD confinement potentials, which is advantageous for the integration of complicated constructs such as multiple QD structures with SET charge sensors for the purpose of spin-based quantum computing.« less

Self-assembled single-crystal silicon circuits on plastic

PubMed Central

Stauth, Sean A.; Parviz, Babak A.

2006-01-01

We demonstrate the use of self-assembly for the integration of freestanding micrometer-scale components, including single-crystal, silicon field-effect transistors (FETs) and diffusion resistors, onto flexible plastic substrates. Preferential self-assembly of multiple microcomponent types onto a common platform is achieved through complementary shape recognition and aided by capillary, fluidic, and gravitational forces. We outline a microfabrication process that yields single-crystal, silicon FETs in a freestanding, powder-like collection for use with self-assembly. Demonstrations of self-assembled FETs on plastic include logic inverters and measured electron mobility of 592 cm2/V-s. Finally, we extend the self-assembly process to substrates each containing 10,000 binding sites and realize 97% self-assembly yield within 25 min for 100-μm-sized elements. High-yield self-assembly of micrometer-scale functional devices as outlined here provides a powerful approach for production of macroelectronic systems. PMID:16968780

Influence of bending strains on radio frequency characteristics of flexible microwave switches using single-crystal silicon nanomembranes on plastic substrate

NASA Astrophysics Data System (ADS)

Qin, Guoxuan; Yuan, Hao-Chih; Celler, George K.; Ma, Jianguo; Ma, Zhenqiang

2011-10-01

This letter presents radio frequency (RF) characterization of flexible microwave switches using single-crystal silicon nanomembranes (SiNMs) on plastic substrate under various uniaxial mechanical tensile bending strains. The flexible switches shows significant/negligible performance enhancement on strains under on/off states from dc to 10 GHz. Furthermore, an RF/microwave strain equivalent circuit model is developed and reveals the most influential factors, and un-proportional device parameters change with bending strains. The study demonstrates that flexible microwave single-crystal SiNM switches, as a simple circuit example towards the goal of flexible monolithic microwave integrated circuits, can be properly operated and modeled under mechanical bending conditions.

Environmental Qualification of a Single-Crystal Silicon Mirror for Spaceflight Use

NASA Technical Reports Server (NTRS)

Hagopian, John; Chambers, John; Rohrback. Scott; Bly, Vincent; Morell, Armando; Budinoff, Jason

2013-01-01

This innovation is the environmental qualification of a single-crystal silicon mirror for spaceflight use. The single-crystal silicon mirror technology is a previous innovation, but until now, a mirror of this type has not been qualified for spaceflight use. The qualification steps included mounting, gravity change measurements, vibration testing, vibration- induced change measurements, thermal cycling, and testing at the cold operational temperature of 225 K. Typical mirrors used for cold applications for spaceflight instruments include aluminum, beryllium, glasses, and glass-like ceramics. These materials show less than ideal behavior after cooldown. Single-crystal silicon has been demonstrated to have the smallest change due to temperature change, but has not been spaceflight-qualified for use. The advantage of using a silicon substrate is with temperature stability, since it is formed from a stress-free single crystal. This has been shown in previous testing. Mounting and environmental qualification have not been shown until this testing.

Quantum cascade lasers grown on silicon.

PubMed

Nguyen-Van, Hoang; Baranov, Alexei N; Loghmari, Zeineb; Cerutti, Laurent; Rodriguez, Jean-Baptiste; Tournet, Julie; Narcy, Gregoire; Boissier, Guilhem; Patriarche, Gilles; Bahriz, Michael; Tournié, Eric; Teissier, Roland

2018-05-08

Technological platforms offering efficient integration of III-V semiconductor lasers with silicon electronics are eagerly awaited by industry. The availability of optoelectronic circuits combining III-V light sources with Si-based photonic and electronic components in a single chip will enable, in particular, the development of ultra-compact spectroscopic systems for mass scale applications. The first circuits of such type were fabricated using heterogeneous integration of semiconductor lasers by bonding the III-V chips onto silicon substrates. Direct epitaxial growth of interband III-V laser diodes on silicon substrates has also been reported, whereas intersubband emitters grown on Si have not yet been demonstrated. We report the first quantum cascade lasers (QCLs) directly grown on a silicon substrate. These InAs/AlSb QCLs grown on Si exhibit high performances, comparable with those of the devices fabricated on their native InAs substrate. The lasers emit near 11 µm, the longest emission wavelength of any laser integrated on Si. Given the wavelength range reachable with InAs/AlSb QCLs, these results open the way to the development of a wide variety of integrated sensors.

Structure and method for controlling band offset and alignment at a crystalline oxide-on-semiconductor interface

DOEpatents

McKee, Rodney A.; Walker, Frederick J.

2003-11-25

A crystalline oxide-on-semiconductor structure and a process for constructing the structure involves a substrate of silicon, germanium or a silicon-germanium alloy and an epitaxial thin film overlying the surface of the substrate wherein the thin film consists of a first epitaxial stratum of single atomic plane layers of an alkaline earth oxide designated generally as (AO).sub.n and a second stratum of single unit cell layers of an oxide material designated as (A'BO.sub.3).sub.m so that the multilayer film arranged upon the substrate surface is designated (AO).sub.n (A'BO.sub.3).sub.m wherein n is an integer repeat of single atomic plane layers of the alkaline earth oxide AO and m is an integer repeat of single unit cell layers of the A'BO.sub.3 oxide material. Within the multilayer film, the values of n and m have been selected to provide the structure with a desired electrical structure at the substrate/thin film interface that can be optimized to control band offset and alignment.

Hybrid stretchable circuits on silicone substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk; Liu, Q.

When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substrate—a silicone matrix carrying concentric rigid disks—ensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

Characterization of nanostructured CuO-porous silicon matrix formed on copper-coated silicon substrate via electrochemical etching

NASA Astrophysics Data System (ADS)

Naddaf, M.; Mrad, O.; Al-zier, A.

2014-06-01

A pulsed anodic etching method has been utilized for nanostructuring of a copper-coated p-type (100) silicon substrate, using HF-based solution as electrolyte. Scanning electron microscopy reveals the formation of a nanostructured matrix that consists of island-like textures with nanosize grains grown onto fiber-like columnar structures separated with etch pits of grooved porous structures. Spatial micro-Raman scattering analysis indicates that the island-like texture is composed of single-phase cupric oxide (CuO) nanocrystals, while the grooved porous structure is barely related to formation of porous silicon (PS). X-ray diffraction shows that both the grown CuO nanostructures and the etched silicon layer have the same preferred (220) orientation. Chemical composition obtained by means of X-ray photoelectron spectroscopic (XPS) analysis confirms the presence of the single-phase CuO on the surface of the patterned CuO-PS matrix. As compared to PS formed on the bare silicon substrate, the room-temperature photoluminescence (PL) from the CuO-PS matrix exhibits an additional weak `blue' PL band as well as a blue shift in the PL band of PS (S-band). This has been revealed from XPS analysis to be associated with the enhancement in the SiO2 content as well as formation of the carbonyl group on the surface in the case of the CuO-PS matrix.

Profilometry of thin films on rough substrates by Raman spectroscopy

PubMed Central

Ledinský, Martin; Paviet-Salomon, Bertrand; Vetushka, Aliaksei; Geissbühler, Jonas; Tomasi, Andrea; Despeisse, Matthieu; De Wolf , Stefaan; Ballif , Christophe; Fejfar, Antonín

2016-01-01

Thin, light-absorbing films attenuate the Raman signal of underlying substrates. In this article, we exploit this phenomenon to develop a contactless thickness profiling method for thin films deposited on rough substrates. We demonstrate this technique by probing profiles of thin amorphous silicon stripes deposited on rough crystalline silicon surfaces, which is a structure exploited in high-efficiency silicon heterojunction solar cells. Our spatially-resolved Raman measurements enable the thickness mapping of amorphous silicon over the whole active area of test solar cells with very high precision; the thickness detection limit is well below 1 nm and the spatial resolution is down to 500 nm, limited only by the optical resolution. We also discuss the wider applicability of this technique for the characterization of thin layers prepared on Raman/photoluminescence-active substrates, as well as its use for single-layer counting in multilayer 2D materials such as graphene, MoS2 and WS2. PMID:27922033

Direct observation of resonance scattering patterns in single silicon nanoparticles

NASA Astrophysics Data System (ADS)

Valuckas, Vytautas; Paniagua-Domínguez, Ramón; Fu, Yuan Hsing; Luk'yanchuk, Boris; Kuznetsov, Arseniy I.

2017-02-01

We present the first direct observation of the scattering patterns of electric and magnetic dipole resonances excited in a single silicon nanosphere. Almost perfectly spherical silicon nanoparticles were fabricated and deposited on a 30 nm-thick silicon nitride membrane in an attempt to minimize particle—substrate interaction. Measurements were carried out at visible wavelengths by means of the Fourier microscopy in a dark-field illumination setup. The obtained back-focal plane images clearly reveal the characteristic scattering patterns associated with each resonance and are found to be in a good agreement with the simulated results.

Optical detector having a plurality of matrix layers with cobalt disilicide particles embedded therein

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor); Schowalter, Leo (Inventor)

1994-01-01

Silicon and metal are coevaporated onto a silicon substrate in a molecular beam epitaxy system with a larger than stoichiometric amount of silicon so as to epitaxially grow particles of metal silicide embedded in a matrix of single crystal epitaxially grown silicon. The particles interact with incident photons by resonant optical absorption at the surface plasmon resonance frequency. Controlling the substrate temperature and deposition rate and time allows the aspect ratio of the particles to be tailored to desired wavelength photons and polarizations. The plasmon energy may decay as excited charge carriers of phonons, either of which can be monitored to indicate the amount of incident radiation at the selected frequency and polarization.

Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sakaike, Kohei; Akazawa, Muneki; Nakamura, Shogo

2013-12-02

A low-temperature local-layer technique for transferring a single-crystalline silicon (c-Si) film by using a meniscus force was proposed, and an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) was fabricated on polyethylene terephthalate (PET) substrate. It was demonstrated that it is possible to transfer and form c-Si films in the required shape at the required position on PET substrates at extremely low temperatures by utilizing a meniscus force. The proposed technique for layer transfer was applied for fabricating high-performance c-Si MOSFETs on a PET substrate. The fabricated MOSFET showed a high on/off ratio of more than 10{sup 8} and a high field-effect mobilitymore » of 609 cm{sup 2} V{sup −1} s{sup −1}.« less

Single-step fabrication of homoepitaxial silicon nanocones by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Colniţă, Alia; Marconi, Daniel; Brătfălean, Radu Tiberiu; Turcu, Ioan

2018-04-01

The purpose of this work was to optimize a single-step fabrication process of silicon (Si) cones-like nanostructures on Si(111) reconstructed substrates. The substrate temperature is the most important parameter in the Si/Si growth, due to its high influence over the surface nanostructuring and the occurrence of well defined nanocones. We investigate the effect of different substrate temperatures on the density and size distributions of Si nanocones formed during the molecular beam epitaxy (MBE) deposition of Si/Si(111) 7 × 7 reconstructed surfaces. The nanocones were characterized using scanning tunnelling microscopy (STM) and the height and the bottom area distributions of the Si nanocones were assessed. It was found that the obtained distributions are interrelated suggesting the self-similarity of the nanostructures grown during the deposition protocol.

Single crystal functional oxides on silicon

PubMed Central

Bakaul, Saidur Rahman; Serrao, Claudy Rayan; Lee, Michelle; Yeung, Chun Wing; Sarker, Asis; Hsu, Shang-Lin; Yadav, Ajay Kumar; Dedon, Liv; You, Long; Khan, Asif Islam; Clarkson, James David; Hu, Chenming; Ramesh, Ramamoorthy; Salahuddin, Sayeef

2016-01-01

Single-crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism and so on that have the potential for completely new electronic applications. Direct synthesis of such oxides on silicon remains challenging because of the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces. Here we report integration of thin (down to one unit cell) single crystalline, complex oxide films onto silicon substrates, by epitaxial transfer at room temperature. In a field-effect transistor using a transferred lead zirconate titanate layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single-crystal functional oxides on-demand on silicon. PMID:26853112

Single-crystal silicon trench etching for fabrication of highly integrated circuits

NASA Astrophysics Data System (ADS)

Engelhardt, Manfred

1991-03-01

The development of single crystal silicon trench etching for fabrication of memory cells in 4 16 and 64Mbit DRAMs is reviewed in this paper. A variety of both etch tools and process gases used for the process development is discussed since both equipment and etch chemistry had to be improved and changed respectively to meet the increasing requirements for high fidelity pattern transfer with increasing degree of integration. In additon to DRAM cell structures etch results for deep trench isolation in advanced bipolar ICs and ASICs are presented for these applications grooves were etched into silicon through a highly doped buried layer and at the borderline of adjacent p- and n-well areas respectively. Shallow trench etching of large and small exposed areas with identical etch rates is presented as an approach to replace standard LOCOS isolation by an advanced isolation technique. The etch profiles were investigated with SEM TEM and AES to get information on contathination and damage levels and on the mechanism leading to anisotropy in the dry etch process. Thermal wave measurements were performed on processed single crystal silicon substrates for a fast evaluation of the process with respect to plasma-induced substrate degradation. This useful technique allows an optimization ofthe etch process regarding high electrical performance of the fully processed memory chip. The benefits of the use of magnetic fields for the development of innovative single crystal silicon dry

Surface segregation on Fe3%Si0.04%VC(100) single crystal surfaces

NASA Astrophysics Data System (ADS)

Uebing, C.; Viefhaus, H.

1990-10-01

Surface segregation phenomena on (100) oriented single crystal surfaces of the ferritic Fe-3%Si-0.04%V-C alloy were investigated by AES and LEED. At temperatures below 635 °C vanadium and carbon cosegregation is observed after prolonged heating. At thermodynamic equilibrium the substrate surface is saturated with the binary surface compound VC. The two-dimensional VC is epitaxially arranged on the substrate surface as indicated by LEED investigations. Its structure corresponds to the (100) plane of the three-dimensional VC with rocksalt structure. Sharp above 635 °C the surface compound VC is dissolved into the bulk. At higher temperatures the substrate surface is covered with segregated silicon forming a c(2 × 2) structure. This surface phase transition is reversible. Because of the low concentration and slow diffusion of vanadium, non-equilibrium surface states are formed as intermediates upon segregation of silicon and carbon. Below 500 °C a disordered graphite layer with a characteristical asymmetrical C Auger peak is observed on the substrate surface. Above 500 °C carbon segregation leads to the formation of an ordered c(2 × 2) structure with a symmetrical C Auger peak being characteristic for carbidic or atomically adsorbed species. At increasing temperatures silicon segregation takes place leading to a c(2 × 2) structure. Between silicon and carbon site competition is effective.

Fabrication of broadband antireflection coating at terahertz frequency using a hot emboss method

NASA Astrophysics Data System (ADS)

Li, YunZhou; Cai, Bin; Zhu, YiMing

2014-11-01

We fabricated a terahertz anti-reflective structure on a polystylene by using a hot-embossing method. Polystylene was spin-coated onto a silicon substrate and then transformed by using a metallic mould comprising a bunch of Chinese acupuncture needles. The transformation layer yielded gradient refractive index profiles on the substrate which can reduce the surface reflection effectively. The samples were evaluated by a terahertz time-domain spectroscope. Compared with a bare silicon substrate, we observed an increase of ~30% in the transmittance. We also observed broader bandwidth properties compared with a single-layer antireflective structure. The process imposes no substrate limiting; i.e., it has great potential to be applied onto various THz devices.

Ultra-thin distributed Bragg reflectors via stacked single-crystal silicon nanomembranes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Minkyu; Seo, Jung-Hun; Lee, Jaeseong

2015-05-04

In this paper, we report ultra-thin distributed Bragg reflectors (DBRs) via stacked single-crystal silicon (Si) nanomembranes (NMs). Mesh hole-free single-crystal Si NMs were released from a Si-on-insulator substrate and transferred to quartz and Si substrates. Thermal oxidation was applied to the transferred Si NM to form high-quality SiO{sub 2} and thus a Si/SiO{sub 2} pair with uniform and precisely controlled thicknesses. The Si/SiO{sub 2} layers, as smooth as epitaxial grown layers, minimize scattering loss at the interface and in between the layers. As a result, a reflection of 99.8% at the wavelength range from 1350 nm to 1650 nm can be measuredmore » from a 2.5-pair DBR on a quartz substrate and 3-pair DBR on a Si substrate with thickness of 0.87 μm and 1.14 μm, respectively. The high reflection, ultra-thin DBRs developed here, which can be applied to almost any devices and materials, holds potential for application in high performance optoelectronic devices and photonics applications.« less

Graphene fixed-end beam arrays based on mechanical exfoliation

NASA Astrophysics Data System (ADS)

Li, Peng; You, Zheng; Haugstad, Greg; Cui, Tianhong

2011-06-01

A low-cost mechanical exfoliation method is presented to transfer graphite to graphene for free-standing beam arrays. Nickel film or photoresist is used to peel off and transfer patterned single-layer or multilayer graphene onto substrates with macroscopic continuity. Free-standing graphene beam arrays are fabricated on both silicon and polymer substrates. Their mechanical properties are studied by atomic force microscopy. Finally, a graphene based radio frequency switch is demonstrated, with its pull-in voltage and graphene-silicon junction investigated.

Biofunctionalization on alkylated silicon substrate surfaces via "click" chemistry.

PubMed

Qin, Guoting; Santos, Catherine; Zhang, Wen; Li, Yan; Kumar, Amit; Erasquin, Uriel J; Liu, Kai; Muradov, Pavel; Trautner, Barbara Wells; Cai, Chengzhi

2010-11-24

Biofunctionalization of silicon substrates is important to the development of silicon-based biosensors and devices. Compared to conventional organosiloxane films on silicon oxide intermediate layers, organic monolayers directly bound to the nonoxidized silicon substrates via Si-C bonds enhance the sensitivity of detection and the stability against hydrolytic cleavage. Such monolayers presenting a high density of terminal alkynyl groups for bioconjugation via copper-catalyzed azide-alkyne 1,3-dipolar cycloaddition (CuAAC, a "click" reaction) were reported. However, yields of the CuAAC reactions on these monolayer platforms were low. Also, the nonspecific adsorption of proteins on the resultant surfaces remained a major obstacle for many potential biological applications. Herein, we report a new type of "clickable" monolayers grown by selective, photoactivated surface hydrosilylation of α,ω-alkenynes, where the alkynyl terminal is protected with a trimethylgermanyl (TMG) group, on hydrogen-terminated silicon substrates. The TMG groups on the film are readily removed in aqueous solutions in the presence of Cu(I). Significantly, the degermanylation and the subsequent CuAAC reaction with various azides could be combined into a single step in good yields. Thus, oligo(ethylene glycol) (OEG) with an azido tag was attached to the TMG-alkyne surfaces, leading to OEG-terminated surfaces that reduced the nonspecific adsorption of protein (fibrinogen) by >98%. The CuAAC reaction could be performed in microarray format to generate arrays of mannose and biotin with varied densities on the protein-resistant OEG background. We also demonstrated that the monolayer platform could be functionalized with mannose for highly specific capturing of living targets (Escherichia coli expressing fimbriae) onto the silicon substrates.

Direct monolithic integration of vertical single crystalline octahedral molecular sieve nanowires on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carretero-Genevrier, Adrian; Oro-Sole, Judith; Gazquez, Jaume

2013-12-13

We developed an original strategy to produce vertical epitaxial single crystalline manganese oxide octahedral molecular sieve (OMS) nanowires with tunable pore sizes and compositions on silicon substrates by using a chemical solution deposition approach. The nanowire growth mechanism involves the use of track-etched nanoporous polymer templates combined with the controlled growth of quartz thin films at the silicon surface, which allowed OMS nanowires to stabilize and crystallize. α-quartz thin films were obtained after thermal activated crystallization of the native amorphous silica surface layer assisted by Sr 2+- or Ba 2+-mediated heterogeneous catalysis in the air at 800 °C. These α-quartzmore » thin films work as a selective template for the epitaxial growth of randomly oriented vertical OMS nanowires. Furthermore, the combination of soft chemistry and epitaxial growth opens new opportunities for the effective integration of novel technological functional tunneled complex oxides nanomaterials on Si substrates.« less

Directed dewetting of amorphous silicon film by a donut-shaped laser pulse.

PubMed

Yoo, Jae-Hyuck; In, Jung Bin; Zheng, Cheng; Sakellari, Ioanna; Raman, Rajesh N; Matthews, Manyalibo J; Elhadj, Selim; Grigoropoulos, Costas P

2015-04-24

Irradiation of a thin film with a beam-shaped laser is proposed to achieve site-selectively controlled dewetting of the film into nanoscale structures. As a proof of concept, the laser-directed dewetting of an amorphous silicon thin film on a glass substrate is demonstrated using a donut-shaped laser beam. Upon irradiation of a single laser pulse, the silicon film melts and dewets on the substrate surface. The irradiation with the donut beam induces an unconventional lateral temperature profile in the film, leading to thermocapillary-induced transport of the molten silicon to the center of the beam spot. Upon solidification, the ultrathin amorphous silicon film is transformed to a crystalline silicon nanodome of increased height. This morphological change enables further dimensional reduction of the nanodome as well as removal of the surrounding film material by isotropic silicon etching. These results suggest that laser-based dewetting of thin films can be an effective way for scalable manufacturing of patterned nanostructures.

Preferred orientations of laterally grown silicon films over amorphous substrates using the vapor-liquid-solid technique

NASA Astrophysics Data System (ADS)

LeBoeuf, J. L.; Brodusch, N.; Gauvin, R.; Quitoriano, N. J.

2014-12-01

A novel method has been optimized so that adhesion layers are no longer needed to reliably deposit patterned gold structures on amorphous substrates. Using this technique allows for the fabrication of amorphous oxide templates known as micro-crucibles, which confine a vapor-liquid-solid (VLS) catalyst of nominally pure gold to a specific geometry. Within these confined templates of amorphous materials, faceted silicon crystals have been grown laterally. The novel deposition technique, which enables the nominally pure gold catalyst, involves the undercutting of an initial chromium adhesion layer. Using electron backscatter diffraction it was found that silicon nucleated in these micro-crucibles were 30% single crystals, 45% potentially twinned crystals and 25% polycrystals for the experimental conditions used. Single, potentially twinned, and polycrystals all had an aversion to growth with the {1 0 0} surface parallel to the amorphous substrate. Closer analysis of grain boundaries of potentially twinned and polycrystalline samples revealed that the overwhelming majority of them were of the 60° Σ3 coherent twin boundary type. The large amount of coherent twin boundaries present in the grown, two-dimensional silicon crystals suggest that lateral VLS growth occurs very close to thermodynamic equilibrium. It is suggested that free energy fluctuations during growth or cooling, and impurities were the causes for this twinning.

Silica substrate or portion formed from oxidation of monocrystalline silicon

DOEpatents

Matzke, Carolyn M.; Rieger, Dennis J.; Ellis, Robert V.

2003-07-15

A method is disclosed for forming an inclusion-free silica substrate using a monocrystalline silicon substrate as the starting material and oxidizing the silicon substrate to convert it entirely to silica. The oxidation process is performed from both major surfaces of the silicon substrate using a conventional high-pressure oxidation system. The resulting product is an amorphous silica substrate which is expected to have superior etching characteristics for microfabrication than conventional fused silica substrates. The present invention can also be used to convert only a portion of a monocrystalline silicon substrate to silica by masking the silicon substrate and locally thinning a portion the silicon substrate prior to converting the silicon portion entirely to silica. In this case, the silica formed by oxidizing the thinned portion of the silicon substrate can be used, for example, as a window to provide optical access through the silicon substrate.

III-V quantum light source and cavity-QED on silicon.

PubMed

Luxmoore, I J; Toro, R; Del Pozo-Zamudio, O; Wasley, N A; Chekhovich, E A; Sanchez, A M; Beanland, R; Fox, A M; Skolnick, M S; Liu, H Y; Tartakovskii, A I

2013-01-01

Non-classical light sources offer a myriad of possibilities in both fundamental science and commercial applications. Single photons are the most robust carriers of quantum information and can be exploited for linear optics quantum information processing. Scale-up requires miniaturisation of the waveguide circuit and multiple single photon sources. Silicon photonics, driven by the incentive of optical interconnects is a highly promising platform for the passive optical components, but integrated light sources are limited by silicon's indirect band-gap. III-V semiconductor quantum-dots, on the other hand, are proven quantum emitters. Here we demonstrate single-photon emission from quantum-dots coupled to photonic crystal nanocavities fabricated from III-V material grown directly on silicon substrates. The high quality of the III-V material and photonic structures is emphasized by observation of the strong-coupling regime. This work opens-up the advantages of silicon photonics to the integration and scale-up of solid-state quantum optical systems.

Silicon/III-V laser with super-compact diffraction grating for WDM applications in electronic-photonic integrated circuits.

PubMed

Wang, Yadong; Wei, Yongqiang; Huang, Yingyan; Tu, Yongming; Ng, Doris; Lee, Cheewei; Zheng, Yunan; Liu, Boyang; Ho, Seng-Tiong

2011-01-31

We have demonstrated a heterogeneously integrated III-V-on-Silicon laser based on an ultra-large-angle super-compact grating (SCG). The SCG enables single-wavelength operation due to its high-spectral-resolution aberration-free design, enabling wavelength division multiplexing (WDM) applications in Electronic-Photonic Integrated Circuits (EPICs). The SCG based Si/III-V laser is realized by fabricating the SCG on silicon-on-insulator (SOI) substrate. Optical gain is provided by electrically pumped heterogeneous integrated III-V material on silicon. Single-wavelength lasing at 1550 nm with an output power of over 2 mW and a lasing threshold of around 150 mA were achieved.

Study of silicon strip waveguides with diffraction gratings and photonic crystals tuned to a wavelength of 1.5 µm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barabanenkov, M. Yu., E-mail: barab@iptm.ru; Vyatkin, A. F.; Volkov, V. T.

2015-12-15

Single-mode submicrometer-thick strip waveguides on silicon-on-insulator substrates, fabricated by silicon-planar-technology methods are considered. To solve the problem of 1.5-µm wavelength radiation input-output and its frequency filtering, strip diffraction gratings and two-dimensional photonic crystals are integrated into waveguides. The reflection and transmission spectra of gratings and photonic crystals are calculated. The waveguide-mode-attenuation coefficient for a polycrystalline silicon waveguide is experimentally estimated.

Oxygen-aided synthesis of polycrystalline graphene on silicon dioxide substrates.

PubMed

Chen, Jianyi; Wen, Yugeng; Guo, Yunlong; Wu, Bin; Huang, Liping; Xue, Yunzhou; Geng, Dechao; Wang, Dong; Yu, Gui; Liu, Yunqi

2011-11-09

We report the metal-catalyst-free synthesis of high-quality polycrystalline graphene on dielectric substrates [silicon dioxide (SiO(2)) or quartz] using an oxygen-aided chemical vapor deposition (CVD) process. The growth was carried out using a CVD system at atmospheric pressure. After high-temperature activation of the growth substrates in air, high-quality polycrystalline graphene is subsequently grown on SiO(2) by utilizing the oxygen-based nucleation sites. The growth mechanism is analogous to that of growth for single-walled carbon nanotubes. Graphene-modified SiO(2) substrates can be directly used in transparent conducting films and field-effect devices. The carrier mobilities are about 531 cm(2) V(-1) s(-1) in air and 472 cm(2) V(-1) s(-1) in N(2), which are close to that of metal-catalyzed polycrystalline graphene. The method avoids the need for either a metal catalyst or a complicated and skilled postgrowth transfer process and is compatible with current silicon processing techniques.

Single-crystal-like GdNdO{sub x} thin films on silicon substrates by magnetron sputtering and high-temperature annealing for crystal seed layer application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Ziwei; Xiao, Lei; Liang, Renrong, E-mail: wang-j@tsinghua.edu.cn, E-mail: liangrr@tsinghua.edu.cn

2016-06-15

Single-crystal-like rare earth oxide thin films on silicon (Si) substrates were fabricated by magnetron sputtering and high-temperature annealing processes. A 30-nm-thick high-quality GdNdO{sub x} (GNO) film was deposited using a high-temperature sputtering process at 500°C. A Gd{sub 2}O{sub 3} and Nd{sub 2}O{sub 3} mixture was used as the sputtering target, in which the proportions of Gd{sub 2}O{sub 3} and Nd{sub 2}O{sub 3} were controlled to make the GNO’s lattice parameter match that of the Si substrate. To further improve the quality of the GNO film, a post-deposition annealing process was performed at a temperature of 1000°C. The GNO films exhibitedmore » a strong preferred orientation on the Si substrate. In addition, an Al/GNO/Si capacitor was fabricated to evaluate the dielectric constant and leakage current of the GNO films. It was determined that the single-crystal-like GNO films on the Si substrates have potential for use as an insulator layer for semiconductor-on-insulator and semiconductor/insulator multilayer applications.« less

Control of biaxial strain in single-layer molybdenite using local thermal expansion of the substrate

NASA Astrophysics Data System (ADS)

Plechinger, Gerd; Castellanos-Gomez, Andres; Buscema, Michele; van der Zant, Herre S. J.; Steele, Gary A.; Kuc, Agnieszka; Heine, Thomas; Schüller, Christian; Korn, Tobias

2015-03-01

Single-layer MoS2 is a direct-gap semiconductor whose electronic band structure strongly depends on the strain applied to its crystal lattice. While uniaxial strain can be easily applied in a controlled way, e.g., by bending of a flexible substrate with the atomically thin MoS2 layer on top, experimental realization of biaxial strain is more challenging. Here, we exploit the large mismatch between the thermal expansion coefficients of MoS2 and a silicone-based substrate to apply a controllable biaxial tensile strain by heating the substrate with a focused laser. The effect of this biaxial strain is directly observable in optical spectroscopy as a redshift of the MoS2 photoluminescence. We also demonstrate the potential of this method to engineer more complex strain patterns by employing highly absorptive features on the substrate to achieve non-uniform heat profiles. By comparison of the observed redshift to strain-dependent band structure calculations, we estimate the biaxial strain applied by the silicone-based substrate to be up to 0.2%, corresponding to a band gap modulation of 105 meV per percentage of biaxial tensile strain.

ZnO buffer layer for metal films on silicon substrates

DOEpatents

Ihlefeld, Jon

2014-09-16

Dramatic improvements in metallization integrity and electroceramic thin film performance can be achieved by the use of the ZnO buffer layer to minimize interfacial energy between metallization and adhesion layers. In particular, the invention provides a substrate metallization method utilizing a ZnO adhesion layer that has a high work of adhesion, which in turn enables processing under thermal budgets typically reserved for more exotic ceramic, single-crystal, or metal foil substrates. Embodiments of the present invention can be used in a broad range of applications beyond ferroelectric capacitors, including microelectromechanical systems, micro-printed heaters and sensors, and electrochemical energy storage, where integrity of metallized silicon to high temperatures is necessary.

Preferred orientations of laterally grown silicon films over amorphous substrates using the vapor–liquid–solid technique

DOE Office of Scientific and Technical Information (OSTI.GOV)

LeBoeuf, J. L., E-mail: jerome.leboeuf@mail.mcgill.ca; Brodusch, N.; Gauvin, R.

2014-12-28

A novel method has been optimized so that adhesion layers are no longer needed to reliably deposit patterned gold structures on amorphous substrates. Using this technique allows for the fabrication of amorphous oxide templates known as micro-crucibles, which confine a vapor–liquid–solid (VLS) catalyst of nominally pure gold to a specific geometry. Within these confined templates of amorphous materials, faceted silicon crystals have been grown laterally. The novel deposition technique, which enables the nominally pure gold catalyst, involves the undercutting of an initial chromium adhesion layer. Using electron backscatter diffraction it was found that silicon nucleated in these micro-crucibles were 30%more » single crystals, 45% potentially twinned crystals and 25% polycrystals for the experimental conditions used. Single, potentially twinned, and polycrystals all had an aversion to growth with the (1 0 0) surface parallel to the amorphous substrate. Closer analysis of grain boundaries of potentially twinned and polycrystalline samples revealed that the overwhelming majority of them were of the 60° Σ3 coherent twin boundary type. The large amount of coherent twin boundaries present in the grown, two-dimensional silicon crystals suggest that lateral VLS growth occurs very close to thermodynamic equilibrium. It is suggested that free energy fluctuations during growth or cooling, and impurities were the causes for this twinning.« less

Article having an improved platinum-aluminum-hafnium protective coating

NASA Technical Reports Server (NTRS)

Nagaraj, Bangalore Aswatha (Inventor); Williams, Jeffrey Lawrence (Inventor)

2005-01-01

An article protected by a protective coating has a substrate and a protective coating having an outer layer deposited upon the substrate surface and a diffusion zone formed by interdiffusion of the outer layer and the substrate. The protective coating includes platinum, aluminum, no more than about 2 weight percent hafnium, and substantially no silicon. The outer layer is substantially a single phase.

Substrate effect on the room-temperature ferromagnetism in un-doped ZnO films

NASA Astrophysics Data System (ADS)

Zhan, Peng; Wang, Weipeng; Xie, Zheng; Li, Zhengcao; Zhang, Zhengjun; Zhang, Peng; Wang, Baoyi; Cao, Xingzhong

2012-07-01

Room-temperature ferromagnetism was achieved in un-doped ZnO films on silicon and quartz substrates. Photoluminescence measurement and positron annihilation analysis suggested that the ferromagnetism was originated from singly occupied oxygen vacancies (roughly estimated as ˜0.55 μB/vacancy), created in ZnO films by annealing in argon. The saturated magnetization of ZnO films was enhanced from ˜0.44 emu/g (on quartz) to ˜1.18 emu/g (on silicon) after annealing at 600 °C, as silicon acted as oxygen getter and created more oxygen vacancies in ZnO films. This study clarified the origin of ferromagnetism in un-doped ZnO and provides an idea to enhance the ferromagnetism.

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

NASA Astrophysics Data System (ADS)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits

DTIC Science & Technology

1995-08-01

common dimensions are given in Table 1. Almost all of the device power is dissipated in the channel. The electri- cally insulating implanted layer...data. Region or Component substrate Material SOI implanted insulating layers single-crystal silicon, 3 x 1015 boron atoms cm -3 Thermal... implanted silicon-dioxide layer in SOI wafers. The data for each device for varying powers fall near a line originating at P = 0 and T0 = 303 K

III–V quantum light source and cavity-QED on Silicon

PubMed Central

Luxmoore, I. J.; Toro, R.; Pozo-Zamudio, O. Del; Wasley, N. A.; Chekhovich, E. A.; Sanchez, A. M.; Beanland, R.; Fox, A. M.; Skolnick, M. S.; Liu, H. Y.; Tartakovskii, A. I.

2013-01-01

Non-classical light sources offer a myriad of possibilities in both fundamental science and commercial applications. Single photons are the most robust carriers of quantum information and can be exploited for linear optics quantum information processing. Scale-up requires miniaturisation of the waveguide circuit and multiple single photon sources. Silicon photonics, driven by the incentive of optical interconnects is a highly promising platform for the passive optical components, but integrated light sources are limited by silicon's indirect band-gap. III–V semiconductor quantum-dots, on the other hand, are proven quantum emitters. Here we demonstrate single-photon emission from quantum-dots coupled to photonic crystal nanocavities fabricated from III–V material grown directly on silicon substrates. The high quality of the III–V material and photonic structures is emphasized by observation of the strong-coupling regime. This work opens-up the advantages of silicon photonics to the integration and scale-up of solid-state quantum optical systems. PMID:23393621

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Passivation of InGaAs(001)-(2 × 4) by Self-Limiting Chemical Vapor Deposition of a Silicon Hydride Control Layer.

PubMed

Edmonds, Mary; Kent, Tyler; Chagarov, Evgueni; Sardashti, Kasra; Droopad, Ravi; Chang, Mei; Kachian, Jessica; Park, Jun Hong; Kummel, Andrew

2015-07-08

A saturated Si-Hx seed layer for gate oxide or contact conductor ALD has been deposited via two separate self-limiting and saturating CVD processes on InGaAs(001)-(2 × 4) at substrate temperatures of 250 and 350 °C. For the first self-limiting process, a single silicon precursor, Si3H8, was dosed at a substrate temperature of 250 °C, and XPS results show the deposited silicon hydride layer saturated at about 4 monolayers of silicon coverage with hydrogen termination. STS results show the surface Fermi level remains unpinned following the deposition of the saturated silicon hydride layer, indicating the InGaAs surface dangling bonds are electrically passivated by Si-Hx. For the second self-limiting process, Si2Cl6 was dosed at a substrate temperature of 350 °C, and XPS results show the deposited silicon chloride layer saturated at about 2.5 monolayers of silicon coverage with chlorine termination. Atomic hydrogen produced by a thermal gas cracker was subsequently dosed at 350 °C to remove the Si-Cl termination by replacing with Si-H termination as confirmed by XPS, and STS results confirm the saturated Si-Hx bilayer leaves the InGaAs(001)-(2 × 4) surface Fermi level unpinned. Density function theory modeling of silicon hydride surface passivation shows an Si-Hx monolayer can remove all the dangling bonds and leave a charge balanced surface on InGaAs.

PDSOI and Radiation Effects: An Overview

NASA Technical Reports Server (NTRS)

Forgione, Joshua B.

2005-01-01

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Enabling Large Focal Plane Arrays through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Costen, Nick; Benford, Dominic J.

2012-01-01

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

PubMed

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Oh, Jin Hyuk; Kim, Sun Ae; Park, Jaegyu; Kim, Sanggi

2015-06-10

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Subsurface Growth Of Silicide Structures In Silicon

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; George, Thomas; Pike, William T.; Schowalter, Leo

1993-01-01

Technique shows promise for fabrication of novel electronic, optoelectronic, and electro-optical devices. Experiments demonstrated feasibility of growing microscopic single-crystal CoSi2 structures beneath surfaces of Si substrates.

Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer

DOEpatents

Manginell, Ronald P.; Schubert, W. Kent; Shul, Randy J.

2005-08-16

New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.

Effect of van der Waals forces on thermal conductance at the interface of a single-wall carbon nanotube array and silicon

NASA Astrophysics Data System (ADS)

Feng, Ya; Zhu, Jie; Tang, Dawei

2014-12-01

Molecular dynamics simulations are performed to evaluate the effect of van der Waals forces among single-wall carbon nanotubes (SWNTs) on the interfacial thermal conductance between a SWNT array and silicon substrate. First, samples of SWNTs vertically aligned on silicon substrate are simulated, where both the number and arrangement of SWNTs are varied. Results reveal that the interfacial thermal conductance of a SWNT array/Si with van der Waals forces present is higher than when they are absent. To better understand how van der Waals forces affect heat transfer through the interface between SWNTs and silicon, further constructs of one SWNT surrounded by different numbers of other ones are studied, and the results show that the interfacial thermal conductance of the central SWNT increases with increasing van der Waals forces. Through analysis of the covalent bonds and vibrational density of states at the interface, we find that heat transfer across the interface is enhanced with a greater number of chemical bonds and that improved vibrational coupling of the two sides of the interface results in higher interfacial thermal conductance. Van der Waals forces stimulate heat transfer at the interface.

Close-packed monolayer self-assembly of silica nanospheres assisted by infrared irradiation

NASA Astrophysics Data System (ADS)

Minh, Nguyen Van; Hue, Nguyen Thi; Lien, Nghiem Thi Ha; Hoang, Chu Manh

2018-01-01

In this paper, we report on a fast and cost-effective drop coating technique for the self-assembly of silica nano-spheres from a mono-dispersed colloidal suspension into close-packed monolayer (CMP) on hydrophilic single-crystal silicon substrate. The technique includes the self-assembly of silica nano-spheres on slanted silicon substrate and infrared irradiation during evaporation process of the coated droplet. The influence of the substrate slant angle and infrared irradiation on the formation of silica nano-sphere monolayer is investigated. This achievement is promising for various applications, such as a mask layer for nano-sphere lithography that is employed for producing fundamental elements in photonics, plasmonics, and solar cell. [Figure not available: see fulltext.

Study of thin film production of ceramic ZrO2 on silicon wafer using second harmonic Nd-Yag laser with pulsed laser deposition technique

NASA Astrophysics Data System (ADS)

Suliyanti, Maria M.; Hidayah, Affi Nur; Kurniawan, K. H.

2012-06-01

Study about thin film production using technique pulsed laser deposition have been done. The Pulsed Laser Deposition (PLD) method has been used for growing thin film of ZrO2 on silicon wafer substrate (111 single crystal, thickness 400μm and diameter 7.5 cm). The target made from Zirconia oxide powder mixing with PVA and press using pressure 100kgN. The laser beam was focused by a lens (f = 100mm) through a quartz window onto the sample surface and the substrate was placed in parallel line with target. The distance between the target and the substrate is about 1 cm. The early results of this synthesis using 75 mJ Nd-YAG second harmonic laser pulse (532 nm Nd-YAG) and low pressure chamber surrounding gas 5 Torr. The irradiation of laser take around 6000 shoots or 10 minutes using frequencies laser 10 Hz. The micro thickness of film can be produced on silicon wafer using this technique. The results of ZrO2 thin film on substrate about 26.92%.

Plasmonic properties of gold nanoparticles on silicon substrates: Understanding Fano-like spectra observed in reflection

NASA Astrophysics Data System (ADS)

Bossard-Giannesini, Léo; Cruguel, Hervé; Lacaze, Emmanuelle; Pluchery, Olivier

2016-09-01

Gold nanoparticles (AuNPs) are known for their localized surface plasmon resonance (LSPR) that can be measured with UV-visible spectroscopy. AuNPs are often deposited on silicon substrates for various applications, and the LSPR is measured in reflection. In this case, optical spectra are measured by surface differential reflectance spectroscopy (SDRS) and the absorbance exhibits a negative peak. This article studies both experimentally and theoretically on the single layers of 16 nm diameter spherical gold nanoparticles (AuNPs) grafted on silicon. The morphology and surface density of AuNPs were investigated by atomic force microscopy (AFM). The plasmon response in transmission on the glass substrate and in reflection on the silicon substrate is described by an analytical model based on the Fresnel equations and the Maxwell-Garnett effective medium theory (FMG). The FMG model shows a strong dependence to the incidence angle of the light. At low incident angles, the peak appears negatively with a shallow intensity, and at angles above 30°, the usual positive shape of the plasmon is retrieved. The relevance of the FMG model is compared to the Mie theory within the dipolar approximation. We conclude that no Fano effect is responsible for this derivative shape. An easy-to-use formula is derived that agrees with our experimental data.

Silicon carbide - Progress in crystal growth

NASA Technical Reports Server (NTRS)

Powell, J. Anthony

1987-01-01

Recent progress in the development of two processes for producing large-area high-quality single crystals of SiC is described: (1) a modified Lely process for the growth of the alpha polytypes (e.g., 6H SiC) initially developed by Tairov and Tsvetkov (1978, 1981) and Ziegler et al. (1983), and (2) a process for the epitaxial growth of the beta polytype on single-crystal silicon or other substrates. Growth of large-area cubic SiC on Si is described together with growth of defect-free beta-SiC films on alpha-6H SiC crystals and TiC lattice. Semiconducting qualities of silicon carbide crystals grown by various techniques are discussed.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Automated assembly of Gallium Arsenide and 50-micron thick silicon solar cell modules

NASA Technical Reports Server (NTRS)

Mesch, H. G.

1984-01-01

The TRW automated solar array assembly equipment was used for the module assembly of 300 GaAs solar cells and 300 50 micron thick silicon solar cells (2 x 4 cm in size). These cells were interconnected with silver plated Invar tabs by means of welding. The GaAs cells were bonded to Kapton graphite aluminum honeycomb graphite substrates and the thin silicon cells were bonded to 0.002 inch thick single layer Kapton substrates. The GaAs solar cell module assembly resulted in a yield of 86% and the thin cell assembly produced a yield of 46% due to intermittent sticking of weld electrodes during the front cell contact welding operation. (Previously assembled thin cell solar modules produced an overall assembly yield of greater than 80%).

Metallic coatings on silicon substrates, and methods of forming metallic coatings on silicon substrates

DOEpatents

Branagan, Daniel J [Idaho Falls, ID; Hyde, Timothy A [Idaho Falls, ID; Fincke, James R [Los Alamos, NM

2008-03-11

The invention includes methods of forming a metallic coating on a substrate which contains silicon. A metallic glass layer is formed over a silicon surface of the substrate. The invention includes methods of protecting a silicon substrate. The substrate is provided within a deposition chamber along with a deposition target. Material from the deposition target is deposited over at least a portion of the silicon substrate to form a protective layer or structure which contains metallic glass. The metallic glass comprises iron and one or more of B, Si, P and C. The invention includes structures which have a substrate containing silicon and a metallic layer over the substrate. The metallic layer contains less than or equal to about 2 weight % carbon and has a hardness of at least 9.2 GPa. The metallic layer can have an amorphous microstructure or can be devitrified to have a nanocrystalline microstructure.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Floating substrate process: Large-area silicon sheet task low-cost solar array project

NASA Technical Reports Server (NTRS)

Garfinkel, M.; Hall, R. N.

1978-01-01

Supercooling of silicon-tin alloy melts was studied. Values as high as 78 C at 1100 C and 39 C at 1200 C were observed, corresponding to supersaturation parameter values 0.025 and 0.053 at 1050 C and 1150 C, respectively. The interaction of tin with silane gas streams was investigated over the temperature range 1000 to 1200 C. Single-pass conversion efficiencies exceeding 30% were obtained. The growth habit of spontaneously-nucleated surface growth was determined to be consistent with dendritic and web growth from singly-twinned triangular nucleii. Surface growth of interlocking silicon crystals, thin enough to follow the surface of the liquid and with growth velocity as high as 5 mm/min, was obtained. Large area single-crystal growth along the melt surface was not achieved. Small single-crystal surface growth was obtained which did not propagate beyond a few millimeters.

Tailoring the optical characteristics of microsized InP nanoneedles directly grown on silicon.

PubMed

Li, Kun; Sun, Hao; Ren, Fan; Ng, Kar Wei; Tran, Thai-Truong D; Chen, Roger; Chang-Hasnain, Connie J

2014-01-08

Nanoscale self-assembly offers a pathway to realize heterogeneous integration of III-V materials on silicon. However, for III-V nanowires directly grown on silicon, dislocation-free single-crystal quality could only be attained below certain critical dimensions. We recently reported a new approach that overcomes this size constraint, demonstrating the growth of single-crystal InGaAs/GaAs and InP nanoneedles with the base diameters exceeding 1 μm. Here, we report distinct optical characteristics of InP nanoneedles which are varied from mostly zincblende, zincblende/wurtzite-mixed, to pure wurtzite crystalline phase. We achieved, for the first time, pure single-crystal wurtzite-phase InP nanoneedles grown on silicon with bandgaps of 80 meV larger than that of zincblende-phase InP. Being able to attain excellent material quality while scaling up in size promises outstanding device performance of these nanoneedles. At room temperature, a high internal quantum efficiency of 25% and optically pumped lasing are demonstrated for single nanoneedle as-grown on silicon substrate. Recombination dynamics proves the excellent surface quality of the InP nanoneedles, which paves the way toward achieving multijunction photovoltaic cells, long-wavelength heterostructure lasers, and advanced photonic integrated circuits.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Collapsed adhesion of carbon nanotubes on silicon substrates: continuum mechanics and atomistic simulations

NASA Astrophysics Data System (ADS)

Yuan, Xuebo; Wang, Youshan

2018-02-01

Carbon nanotubes (CNTs) can undergo collapse from the ordinary cylindrical configurations to bilayer ribbons when adhered on substrates. In this study, the collapsed adhesion of CNTs on the silicon substrates is investigated using both classical molecular dynamics (MD) simulations and continuum analysis. The governing equations and transversality conditions are derived based on the minimum potential energy principle and the energy-variational method, considering both the van der Waals interactions between CNTs and substrates and those inside CNTs. Closed-form solutions for the collapsed configuration are obtained which show good agreement with the results of MD simulations. The stability of adhesive configurations is investigated by analyzing the energy states. It is found that the adhesive states of single-walled CNTs (SWCNTs) (n, n) on the silicon substrates can be categorized by two critical radii, 0.716 and 0.892 nm. For SWCNTs with radius larger than 0.892 nm, they would fully collapse on the silicon substrates. For SWCNTs with radius less than 0.716 nm, the initial cylindrical configuration is energetically favorable. For SWCNTs with radius between two critical radii, the radially deformed state is metastable. The non-contact ends of all collapsed SWCNTs are identical with the same arc length of 2.38 nm. Finally, the role of number of walls on the adhesive configuration is investigated quantitatively. For multi-walled CNTs with the number of walls exceeding a certain value, the cylindrical configuration is stable due to the increasing bending stiffness. The present study can be useful for the design of CNT-based nanodevices.

Monolithic integration of hybrid perovskite single crystals with heterogenous substrate for highly sensitive X-ray imaging

NASA Astrophysics Data System (ADS)

Wei, Wei; Zhang, Yang; Xu, Qiang; Wei, Haotong; Fang, Yanjun; Wang, Qi; Deng, Yehao; Li, Tao; Gruverman, Alexei; Cao, Lei; Huang, Jinsong

2017-04-01

The monolithic integration of new optoelectronic materials with well-established inexpensive silicon circuitry is leading to new applications, functionality and simple readouts. Here, we show that single crystals of hybrid perovskites can be integrated onto virtually any substrates, including silicon wafers, through facile, low-temperature, solution-processed molecular bonding. The brominated (3-aminopropyl)triethoxysilane molecule binds the native oxide of silicon and participates in the perovskite crystal with its ammonium bromide group, yielding a solid mechanical and electrical connection. The dipole of the bonding molecule reduces device noise while retaining signal intensity. The reduction of dark current enables the detectors to be operated at increased bias, resulting in a sensitivity of 2.1 × 104 µC Gyair-1 cm-2 under 8 keV X-ray radiation, which is over a thousand times higher than the sensitivity of amorphous selenium detectors. X-ray imaging with both perovskite pixel detectors and linear array detectors reduces the total dose by 15-120-fold compared with state-of-the-art X-ray imaging systems.

Interband π -like plasmon in silicene grown on silver

NASA Astrophysics Data System (ADS)

Sindona, A.; Cupolillo, A.; Alessandro, F.; Pisarra, M.; Coello Fiallos, D. C.; Osman, S. M.; Caputi, L. S.

2018-01-01

Silicene, the two-dimensional allotrope of silicon, is predicted to exist in a low-buckled honeycomb lattice, characterized by semimetallic electronic bands with graphenelike energy-momentum dispersions around the Fermi level (represented by touching Dirac cones). Single layers of silicene are mostly synthesized by depositing silicon on top of silver, where, however, the different phases observed to date are so strongly hybridized with the substrate that not only the Dirac cones, but also the whole valence and conduction states of ideal silicene appear to be lost. Here, we provide evidence that at least part of this semimetallic behavior is preserved by the coexistence of more silicene phases, epitaxially grown on Ag(111). In particular, we combine electron energy loss spectroscopy and time-dependent density functional theory to characterize the low-energy plasmon of a multiphase-silicene/Ag(111) sample, prepared at controlled silicon coverage and growth temperature. We find that this mode survives the interaction with the substrate, being perfectly matched with the π -like plasmon of ideal silicene. We therefore suggest that the weakened interaction of multiphase silicene with the substrate may provide a unique platform with the potential to develop different applications based on two-dimensional silicon systems.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects

PubMed Central

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Gyoo Kim, In; Hyuk Oh, Jin; Ae Kim, Sun; Park, Jaegyu; Kim, Sanggi

2015-01-01

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications. PMID:26061463

Laser-zone growth in a Ribbon-To-Ribbon (RTR) process. Silicon sheet growth development for the large area sheet task of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Baghdadi, A.; Gurtler, R. W.; Legge, R.; Sopori, B.; Ellis, R. J.

1978-01-01

A new calculation of the effects of thermal stresses during growth on silicon ribbon quality is reported. Thermal stress distributions are computed for ribbon growth under a variety of temperature profiles. A growth rate of 55 cu cm/min with a single ribbon was achieved. The growth of RTR ribbon with a fairly uniform parallel dendritic structure was demonstrated. Results with two approaches were obtained for reducing the Mo impurity level in polycrystalline feedstock. Coating the Mo substrate with Si3N4 does not effect thermal shear separation of the polyribbon; this process shows promise of improving cell efficiency and also increasing the useful life of the molybdenum substrate. A number of solar cells were fabricated on RTR silicon grown from CVD feedstock.

Improved toughness of silicon carbide

NASA Technical Reports Server (NTRS)

Palm, J. A.

1975-01-01

Several techniques were employed to apply or otherwise form porous layers of various materials on the surface of hot-pressed silicon carbide ceramic. From mechanical properties measurements and studies, it was concluded that although porous layers could be applied to the silicon carbide ceramic, sufficient damage was done to the silicon carbide surface by the processing required so as to drastically reduce its mechanical strength. It was further concluded that there was little promise of success in forming an effective energy absorbing layer on the surface of already densified silicon carbide ceramic that would have the mechanical strength of the untreated or unsurfaced material. Using a process for the pressureless sintering of silicon carbide powders it was discovered that porous layers of silicon carbide could be formed on a dense, strong silicon carbide substrate in a single consolidation process.

Selective-area growth of GaN nanowires on SiO{sub 2}-masked Si (111) substrates by molecular beam epitaxy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kruse, J. E.; Doundoulakis, G.; Institute of Electronic Structure and Laser, Foundation for Research and Technology–Hellas, N. Plastira 100, 70013 Heraklion

2016-06-14

We analyze a method to selectively grow straight, vertical gallium nitride nanowires by plasma-assisted molecular beam epitaxy (MBE) at sites specified by a silicon oxide mask, which is thermally grown on silicon (111) substrates and patterned by electron-beam lithography and reactive-ion etching. The investigated method requires only one single molecular beam epitaxy MBE growth process, i.e., the SiO{sub 2} mask is formed on silicon instead of on a previously grown GaN or AlN buffer layer. We present a systematic and analytical study involving various mask patterns, characterization by scanning electron microscopy, transmission electron microscopy, and photoluminescence spectroscopy, as well asmore » numerical simulations, to evaluate how the dimensions (window diameter and spacing) of the mask affect the distribution of the nanowires, their morphology, and alignment, as well as their photonic properties. Capabilities and limitations for this method of selective-area growth of nanowires have been identified. A window diameter less than 50 nm and a window spacing larger than 500 nm can provide single nanowire nucleation in nearly all mask windows. The results are consistent with a Ga diffusion length on the silicon dioxide surface in the order of approximately 1 μm.« less

Seamless lamination of a concave-convex architecture with single-layer graphene.

PubMed

Park, Ji-Hoon; Lim, Taekyung; Baik, Jaeyoon; Seo, Keumyoung; Moon, Youngkwon; Park, Noejung; Shin, Hyun-Joon; Kwak, Sang Kyu; Ju, Sanghyun; Ahn, Joung Real

2015-11-21

Graphene has been used as an electrode and channel material in electronic devices because of its superior physical properties. Recently, electronic devices have changed from a planar to a complicated three-dimensional (3D) geometry to overcome the limitations of planar devices. The evolution of electronic devices requires that graphene be adaptable to a 3D substrate. Here, we demonstrate that chemical-vapor-deposited single-layer graphene can be transferred onto a silicon dioxide substrate with a 3D geometry, such as a concave-convex architecture. A variety of silicon dioxide concave-convex architectures were uniformly and seamlessly laminated with graphene using a thermal treatment. The planar graphene was stretched to cover the concave-convex architecture, and the resulting strain on the curved graphene was spatially resolved by confocal Raman spectroscopy; molecular dynamic simulations were also conducted and supported the observations. Changes in electrical resistivity caused by the spatially varying strain induced as the graphene-silicon dioxide laminate varies dimensionally from 2D to 3D were measured by using a four-point probe. The resistivity measurements suggest that the electrical resistivity can be systematically controlled by the 3D geometry of the graphene-silicon dioxide laminate. This 3D graphene-insulator laminate will broaden the range of graphene applications beyond planar structures to 3D materials.

RF performances of inductors integrated on localized p+-type porous silicon regions

PubMed Central

2012-01-01

To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate. PMID:23009746

High-speed thin-film transistors on single-crystalline, unstrained- and strained-silicon-based nanomembranes

NASA Astrophysics Data System (ADS)

Yuan, Hao-Chih

This research focuses on developing high-performance single-crystal Si-based nanomembranes and high-frequency thin-film transistors (TFTs) using these nanomembranes on flexible plastic substrates. Unstrained Si or SiGe nanomembranes with thickness of several tens to a couple of hundred nanometers are derived from silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI) and are subsequently transferred and integrated with flexible plastic host substrates via a one-step dry printing technique. Biaxial tensile-strained Si membranes that utilize elastic strain-sharing between Si and additionally grown SiGe thin films are also successfully integrated with plastic host substrates and exhibit predicted strain status and negligible density of dislocations. Biaxial tensile strain enhances electron mobility and lowers Schottky contact resistance. As a result, flexible TFTs built on the strained Si-membranes demonstrate much higher electron effective mobility and higher drive current than the unstrained counterpart. The dependence of drive current and transconductance on uniaxial tensile strain introducing by mechanical bending is also discussed. A novel combined "hot-and-cold" TFT fabrication process is developed specifically for realizing a wide spectrum of micro-electronics that can exhibit RF performance and can be integrated on low-temperature plastic substrate. The "hot" process that consists of ion implant and high-temperature annealing for desired doping type, profile, and concentration is realized on the bulk SOI/SGOI substrates followed by the "cold" process that includes room-temperature silicon-monoxide (SiO) deposition as gate dielectric layer to ensure the process compatibility with low-temperature, low-cost plastics. With these developments flexible Si-membrane n-type RF TFTs for analog applications and complementary TFTs for digital applications are demonstrated for the first time. RF TFTs with 1.5-mum channel length have demonstrated record-high f T and fmax values of 2.04 and 7.8 GHz, respectively. A small-signal equivalent circuit model study on the RF TFTs reveals the physics of how device layout affects fT and f max, which paves the way for further performance optimization and realization of integrated circuit on flexible substrate in the future.

Novel silicon microchannels device for use in red blood cell deformability studies

NASA Astrophysics Data System (ADS)

Zheng, Xiao-Lin; Liao, Yan-Jian; Zhang, Wen-Xian

2001-10-01

Currently, a number of techniques are used to access cell deformability. We study a novel silicon microchannels device for use in red blood cell deformability. The channels are produced in silicon substrate using microengineering technology. The microgrooves formed in the surface of a single-crystal silicon substrate. They were converted to channels by tightly covering them with an optical flat glass plate. An array of flow channels (number 950 in parallel) have typical dimensions of 5 micrometers width X 5.5 Xm depth, and 30 micrometers length. There the RBC's are forced to pass through channels. Thus, the microchannels are used to simulate human blood capillaries. It provides a specific measurement of individual cell in terms of both flow velocity profile and an index of cell volume while the cell flow through the channels. It dominates the complex cellular flow behavior, such as, the viscosity of whole blood is a nonlinear function of shear rate, index of filtration, etc.

Graded Index Silicon Geranium on Lattice Matched Silicon Geranium Semiconductor Alloy

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor); Elliott, James R., Jr. (Inventor); Stoakley, Diane M. (Inventor)

2009-01-01

A lattice matched silicon germanium (SiGe) semiconductive alloy is formed when a {111} crystal plane of a cubic diamond structure SiGe is grown on the {0001} C-plane of a single crystalline Al2O3 substrate such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,-1,0> orientation of the {0001} C-plane. A lattice match between the substrate and the SiGe is achieved by using a SiGe composition that is 0.7223 atomic percent silicon and 0.2777 atomic percent germanium. A layer of Si(1-x), ,Ge(x) is formed on the cubic diamond structure SiGe. The value of X (i) defines an atomic percent of germanium satisfying 0.2277

Evaluation of mesoporous silicon thermal conductivity by electrothermal finite element simulation

PubMed Central

2012-01-01

The aim of this work is to determine the thermal conductivity of mesoporous silicon (PoSi) by fitting the experimental results with simulated ones. The electrothermal response (resistance versus applied current) of differently designed test lines integrated onto PoSi/silicon substrates and the bulk were compared to the simulations. The PoSi thermal conductivity was the single parameter used to fit the experimental results. The obtained thermal conductivity values were compared with those determined from Raman scattering measurements, and a good agreement between both methods was found. This methodology can be used to easily determine the thermal conductivity value for various porous silicon morphologies. PMID:22849851

Mechanism of the growth of amorphous and microcrystalline silicon from silicon tetrafluoride and hydrogen

NASA Astrophysics Data System (ADS)

Okada, Y.; Chen, J.; Campbell, I. H.; Fauchet, P. M.; Wagner, S.

1990-02-01

We study the growth of amorphous (a-Si:H,F) and of microcrystalline (μc-Si) silicon over trench patterns in crystalline silicon substrates. We vary the conditions of the SiF4-H2 glow discharge from deposition to etching. All deposited films form lips at the trench mouth and are uniformly thick on the trench walls. Therefore, surface diffusion is not important. The results of a Monte Carlo simulation suggest that film growth is governed by a single growth species with a low (˜0.2) sticking coefficient, in combination with a highly reactive etching species.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad H.

2004-01-01

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

Micromachined silicon parallel acoustic delay lines as time-delayed ultrasound detector array for real-time photoacoustic tomography

NASA Astrophysics Data System (ADS)

Cho, Y.; Chang, C.-C.; Wang, L. V.; Zou, J.

2016-02-01

This paper reports the development of a new 16-channel parallel acoustic delay line (PADL) array for real-time photoacoustic tomography (PAT). The PADLs were directly fabricated from single-crystalline silicon substrates using deep reactive ion etching. Compared with other acoustic delay lines (e.g., optical fibers), the micromachined silicon PADLs offer higher acoustic transmission efficiency, smaller form factor, easier assembly, and mass production capability. To demonstrate its real-time photoacoustic imaging capability, the silicon PADL array was interfaced with one single-element ultrasonic transducer followed by one channel of data acquisition electronics to receive 16 channels of photoacoustic signals simultaneously. A PAT image of an optically-absorbing target embedded in an optically-scattering phantom was reconstructed, which matched well with the actual size of the imaged target. Because the silicon PADL array allows a signal-to-channel reduction ratio of 16:1, it could significantly simplify the design and construction of ultrasonic receivers for real-time PAT.

Gold Nanoparticles on Functionalized Silicon Substrate under Coulomb Blockade Regime: An Experimental and Theoretical Investigation.

PubMed

Pluchery, Olivier; Caillard, Louis; Dollfus, Philippe; Chabal, Yves J

2018-01-18

Single charge electronics offer a way for disruptive technology in nanoelectronics. Coulomb blockade is a realistic way for controlling the electric current through a device with the accuracy of one electron. In such devices the current exhibits a step-like increase upon bias which reflects the discrete nature of the fundamental charge. We have assembled a double tunnel junction on an oxide-free silicon substrate that exhibits Coulomb staircase characteristics using gold nanoparticles (AuNPs) as Coulomb islands. The first tunnel junction is an insulating layer made of a grafted organic monolayer (GOM) developed for this purpose. The GOM also serves for attaching AuNPs covalently. The second tunnel junction is made by the tip of an STM. We show that this device exhibits reproducible Coulomb blockade I-V curves at 40 K in vacuum. We also show that depending on the doping of the silicon substrate, the whole Coulomb staircase can be adjusted. We have developed a simulation approach based on the orthodox theory that was completed by calculating the bias dependent tunnel barriers and by including an accurate calculation of the band bending. This model accounts for the experimental data and the doping dependence of Coulomb oscillations. This study opens new perspectives toward designing new kind of single electron transistors (SET) based on this dependence of the Coulomb staircase with the charge carrier concentration.

Study of surface reaction during selective epitaxy growth of silicon by thermodynamic analysis and density functional theory calculation

NASA Astrophysics Data System (ADS)

Mayangsari, Tirta R.; Yusup, Luchana L.; Park, Jae-Min; Blanquet, Elisabeth; Pons, Michel; Jung, Jongwan; Lee, Won-Jun

2017-06-01

We modeled and simulated the surface reaction of silicon precursor on different surfaces by thermodynamic analysis and density functional theory calculation. We considered SiH2Cl2 and argon as the silicon precursor and the carrier gas without etchant gas. First, the equilibrium composition of both gaseous and solid species was analyzed as a function of process temperature. SiCl4 is the dominant gaseous species at below 750 °C, and SiCl2 and HCl are dominant at higher temperatures, and the yield of silicon decreases with increasing temperature over 700 °C due to the etching of silicon by HCl. The yield of silicon for SiO2 substrate is lower than that for silicon substrate, especially at 1000 °C or higher. Zero deposition yield and the etching of SiO2 substrate at higher temperatures leads to selective growth on silicon substrate. Next, the adsorption and the reaction of silicon precursor was simulated on H-terminated silicon (100) substrate and on OH-terminated β-cristobalite substrate. The adsorption and reaction of a SiH2Cl2 molecule are spontaneous for both Si and SiO2 substrates. However, the energy barrier for reaction is very small (6×10-4 eV) for Si substrate, whereas the energy barrier is high (0.33 eV) for SiO2 substrate. This makes the differences in growth rate, which also supports the experimental results in literature.

Status of Reconstruction of Fragmented Diamond-on-Silicon Collector From Genesis Spacecraft Solar Wind Concentrator

NASA Technical Reports Server (NTRS)

Rodriquez, Melissa C.; Calaway, M. C.; McNamara, K. M.; Hittle, J. D.

2009-01-01

In addition to passive solar wind collector surfaces, the Genesis Discovery Mission science canister had on board an electrostatic concave mirror for concentrating the solar wind ions, known as the concentrator . The 30-mm-radius collector focal point (the target) was comprised of 4 quadrants: two of single crystal SiC, one of polycrystalline 13C diamond and one of diamond-like-carbon (DLC) on a silicon substrate. [DLC-on-silicon is also sometimes referenced as Diamond-on-silicon, DOS.] Three of target quadrants survived the hard landing intact, but the DLC-on-silicon quadrant fractured into numerous pieces (Fig. 1). This abstract reports the status of identifying the DLC target fragments and reconstructing their original orientation.

Epitaxial growth of silicon for layer transfer

DOEpatents

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsam (Inventor); Manohara, Harish (Inventor); Mobasser, Sohrab (Inventor); Lee, Choonsup (Inventor)

2011-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Anti- reflective device having an anti-reflection surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsman (Inventor); Mooasser, Sohrab (Inventor); Manohara, Harish (Inventor); Lee, Choonsup (Inventor); Bae, Kungsam (Inventor)

2009-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Basic research challenges in crystalline silicon photovoltaics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Werner, J.H.

1995-08-01

Silicon is abundant, non-toxic and has an ideal band gap for photovoltaic energy conversion. Experimental world record cells of 24 % conversion efficiency with around 300 {mu}m thickness are only 4 % (absolute) efficiency points below the theoretical Auger recombination-limit of around 28 %. Compared with other photovoltaic materials, crystalline silicon has only very few disadvantages. The handicap of weak light absorbance may be mastered by clever optical designs. Single crystalline cells of only 48 {mu}m thickness showed 17.3 % efficiency even without backside reflectors. A technology of solar cells from polycrystalline Si films on foreign substrates arises at themore » horizon. However, the disadvantageous, strong activity of grain boundaries in Si could be an insurmountable hurdle for a cost-effective, terrestrial photovoltaics based on polycrystalline Si on foreign substrates. This talk discusses some basic research challenges related to a Si based photovoltaics.« less

Large-Area Direct Hetero-Epitaxial Growth of 1550-nm InGaAsP Multi-Quantum-Well Structures on Patterned Exact-Oriented (001) Silicon Substrates by Metal Organic Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Megalini, Ludovico; Cabinian, Brian C.; Zhao, Hongwei; Oakley, Douglas C.; Bowers, John E.; Klamkin, Jonathan

2018-02-01

We employ a simple two-step growth technique to grow large-area 1550-nm laser structures by direct hetero-epitaxy of III-V compounds on patterned exact-oriented (001) silicon (Si) substrates by metal organic chemical vapor deposition. Densely-packed, highly uniform, flat and millimeter-long indium phosphide (InP) nanowires were grown from Si v-grooves separated by silicon dioxide (SiO2) stripes with various widths and pitches. Following removal of the SiO2 patterns, the InP nanowires were coalesced and, subsequently, 1550-nm laser structures were grown in a single overgrowth without performing any polishing for planarization. X-ray diffraction, photoluminescence, atomic force microscopy and transmission electron microscopy analyses were used to characterize the epitaxial material. PIN diodes were fabricated and diode-rectifying behavior was observed.

A new detector concept for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Sadigov, A.; Ahmadov, F.; Ahmadov, G.; Ariffin, A.; Khorev, S.; Sadygov, Z.; Suleymanov, S.; Zerrouk, F.; Madatov, R.

2016-07-01

A new design and principle of operation of silicon photomultipliers are presented. The new design comprises a semiconductor substrate and an array of independent micro-phototransistors formed on the substrate. Each micro-phototransistor comprises a photosensitive base operating in Geiger mode and an individual micro-emitter covering a small part of the base layer, thereby creating, together with this latter, a micro-transistor. Both micro-emitters and photosensitive base layers are connected with two respective independent metal grids via their individual micro-resistors. The total value of signal gain in the proposed silicon photomultiplier is a result of both the avalanche gain in the base layer and the corresponding gain in the micro-transistor. The main goals of the new design are: significantly lower both optical crosstalk and after-pulse effects at high signal amplification, improve speed of single photoelectron pulse formation, and significantly reduce the device capacitance.

Ceramic with preferential oxygen reactive layer

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Luthra, Krishan Lal (Inventor)

2001-01-01

An article comprises a silicon-containing substrate and an external environmental/thermal barrier coating. The external environmental/thermal barrier coating is permeable to diffusion of an environmental oxidant and the silicon-containing substrate is oxidizable by reaction with oxidant to form at least one gaseous product. The article comprises an intermediate layer/coating between the silicon-containing substrate and the environmental/thermal barrier coating that is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant. A method of forming an article, comprises forming a silicon-based substrate that is oxidizable by reaction with oxidant to at least one gaseous product and applying an intermediate layer/coating onto the substrate, wherein the intermediate layer/coating is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant.

Tuning of structural, light emission and wetting properties of nanostructured copper oxide-porous silicon matrix formed on electrochemically etched copper-coated silicon substrates

NASA Astrophysics Data System (ADS)

Naddaf, M.

2017-01-01

Matrices of copper oxide-porous silicon nanostructures have been formed by electrochemical etching of copper-coated silicon surfaces in HF-based solution at different etching times (5-15 min). Micro-Raman, X-ray diffraction and X-ray photoelectron spectroscopy results show that the nature of copper oxide in the matrix changes from single-phase copper (I) oxide (Cu2O) to single-phase copper (II) oxide (CuO) on increasing the etching time. This is accompanied with important variation in the content of carbon, carbon hydrides, carbonyl compounds and silicon oxide in the matrix. The matrix formed at the low etching time (5 min) exhibits a single broad "blue" room-temperature photoluminescence (PL) band. On increasing the etching time, the intensity of this band decreases and a much stronger "red" PL band emerges in the PL spectra. The relative intensity of this band with respect to the "blue" band significantly increases on increasing the etching time. The "blue" and "red" PL bands are attributed to Cu2O and porous silicon of the matrix, respectively. In addition, the water contact angle measurements reveal that the hydrophobicity of the matrix surface can be tuned from hydrophobic to superhydrophobic state by controlling the etching time.

Selective Growth of Metallic and Semiconducting Single Walled Carbon Nanotubes on Textured Silicon.

PubMed

Jang, Mira; Lee, Jongtaek; Park, Teahee; Lee, Junyoung; Yang, Jonghee; Yi, Whikun

2016-03-01

We fabricated the etched Si substrate having the pyramidal pattern size from 0.5 to 4.2 μm by changing the texturing process parameters, i.e., KOH concentration, etching time, and temperature. Single walled carbon nanotubes (SWNTs) were then synthesized on the etched Si substrates with different pyramidal pattern by chemical vapor deposition. We investigated the optical and electronic properties of SWNT film grown on the etched Si substrates of different morphology by using scanning electron microscopy, Raman spectroscopy and conducting probe atomic force microscopy. We confirmed that the morphology of substrate strongly affected the selective growth of the SWNT film. Semiconducting SWNTs were formed on larger pyramidal sized Si wafer with higher ratio compared with SWNTs on smaller pyramidal sized Si.

Chemical Interaction-Guided, Metal-Free Growth of Large-Area Hexagonal Boron Nitride on Silicon-Based Substrates.

PubMed

Behura, Sanjay; Nguyen, Phong; Debbarma, Rousan; Che, Songwei; Seacrist, Michael R; Berry, Vikas

2017-05-23

Hexagonal boron nitride (h-BN) is an ideal platform for interfacing with two-dimensional (2D) nanomaterials to reduce carrier scattering for high-quality 2D electronics. However, scalable, transfer-free growth of hexagonal boron nitride (h-BN) remains a challenge. Currently, h-BN-based 2D heterostructures require exfoliation or chemical transfer of h-BN grown on metals resulting in small areas or significant interfacial impurities. Here, we demonstrate a surface-chemistry-influenced transfer-free growth of large-area, uniform, and smooth h-BN directly on silicon (Si)-based substrates, including Si, silicon nitride (Si 3 N 4 ), and silicon dioxide (SiO 2 ), via low-pressure chemical vapor deposition. The growth rates increase with substrate electronegativity, Si < Si 3 N 4 < SiO 2 , consistent with the adsorption rates calculated for the precursor molecules via atomistic molecular dynamics simulations. Under graphene with high grain density, this h-BN film acts as a polymer-free, planar-dielectric interface increasing carrier mobility by 3.5-fold attributed to reduced surface roughness and charged impurities. This single-step, chemical interaction guided, metal-free growth mechanism of h-BN for graphene heterostructures establishes a potential pathway for the design of complex and integrated 2D-heterostructured circuitry.

Voltage-Controlled Spray Deposition of Multiwalled Carbon Nanotubes on Semiconducting and Insulating Substrates

NASA Astrophysics Data System (ADS)

Maulik, Subhodip; Sarkar, Anirban; Basu, Srismrita; Daniels-Race, Theda

2018-05-01

A facile, cost-effective, voltage-controlled, "single-step" method for spray deposition of surfactant-assisted dispersed carbon nanotube (CNT) thin films on semiconducting and insulating substrates has been developed. The fabrication strategy enables direct deposition and adhesion of CNT films on target samples, eliminating the need for substrate surface functionalization with organosilane binder agents or metal layer coatings. Spray coating experiments on four types of sample [bare silicon (Si), microscopy-grade glass samples, silicon dioxide (SiO2), and polymethyl methacrylate (PMMA)] under optimized control parameters produced films with thickness ranging from 40 nm to 6 μm with substantial surface coverage and packing density. These unique deposition results on both semiconducting and insulator target samples suggest potential applications of this technique in CNT thin-film transistors with different gate dielectrics, bendable electronics, and novel CNT-based sensing devices, and bodes well for further investigation into thin-film coatings of various inorganic, organic, and hybrid nanomaterials on different types of substrate.

Gold/silver coated nanoporous ceramic membranes: a new substrate for SERS studies

NASA Astrophysics Data System (ADS)

Kassu, A.; Robinson, P.; Sharma, A.; Ruffin, P. B.; Brantley, C.; Edwards, E.

2010-08-01

Surface Enhanced Raman Scattering (SERS) is a recently discovered powerful technique which has demonstrated sensitivity and selectivity for detecting single molecules of certain chemical species. This is due to an enhancement of Raman scattered light by factors as large as 1015. Gold and Silver-coated substrates fabricated by electron-beam lithography on Silicon are widely used in SERS technique. In this paper, we report the use of nanoporous ceramic membranes for SERS studies. Nanoporous membranes are widely used as a separation membrane in medical devices, fuel cells and other studies. Three different pore diameter sizes of commercially available nanoporous ceramic membranes: 35 nm, 55nm and 80nm are used in the study. To make the membranes SERS active, they are coated with gold/silver using sputtering techniques. We have seen that the membranes coated with gold layer remain unaffected even when immersed in water for several days. The results show that gold coated nanoporous membranes have sensitivity comparable to substrates fabricated by electron-beam lithography on Silicon substrates.

High efficiency epitaxial GaAs/GaAs and GaAs/Ge solar cell technology using OM/CVD

NASA Technical Reports Server (NTRS)

Wang, K. L.; Yeh, Y. C. M.; Stirn, R. J.; Swerdling, S.

1980-01-01

A technology for fabricating high efficiency, thin film GaAs solar cells on substrates appropriate for space and/or terrestrial applications was developed. The approach adopted utilizes organometallic chemical vapor deposition (OM-CVD) to form a GaAs layer epitaxially on a suitably prepared Ge epi-interlayer deposited on a substrate, especially a light weight silicon substrate which can lead to a 300 watt per kilogram array technology for space. The proposed cell structure is described. The GaAs epilayer growth on single crystal GaAs and Ge wafer substrates were investigated.

Back contact to film silicon on metal for photovoltaic cells

DOEpatents

Branz, Howard M.; Teplin, Charles; Stradins, Pauls

2013-06-18

A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.

Surface treatment effect on Si (111) substrate for carbon deposition using DC unbalanced magnetron sputtering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aji, A. S., E-mail: aji.ravazes70@gmail.com; Sahdan, M. F.; Hendra, I. B.

In this work, we studied the effect of HF treatment in silicon (111) substrate surface for depositing thin layer carbon. We performed the deposition of carbon by using DC Unbalanced Magnetron Sputtering with carbon pallet (5% Fe) as target. From SEM characterization results it can be concluded that the carbon layer on HF treated substrate is more uniform than on substrate without treated. Carbon deposition rate is higher as confirmed by AFM results if the silicon substrate is treated by HF solution. EDAX characterization results tell that silicon (111) substrate with HF treatment have more carbon fraction than substrate withoutmore » treatment. These results confirmed that HF treatment on silicon Si (111) substrates could enhance the carbon deposition by using DC sputtering. Afterward, the carbon atomic arrangement on silicon (111) surface is studied by performing thermal annealing process to 900 °C. From Raman spectroscopy results, thin film carbon is not changing until 600 °C thermal budged. But, when temperature increase to 900 °C, thin film carbon is starting to diffuse to silicon (111) substrates.« less

Spin Measurements of an Electron Bound to a Single Phosphorous Donor in Silicon

NASA Astrophysics Data System (ADS)

Luhman, D. R.; Nguyen, K.; Tracy, L. A.; Carr, S. M.; Borchardt, J.; Bishop, N. C.; Ten Eyck, G. A.; Pluym, T.; Wendt, J.; Carroll, M. S.; Lilly, M. P.

2014-03-01

The spin of an electron bound to a single donor implanted in silicon is potentially useful for quantum information processing. We report on our efforts to measure and manipulate the spin of an electron bound to a single P donor in silicon. A low number of P donors are implanted using a self-aligned process into a silicon substrate in close proximity to a single-electron-transistor (SET) defined by lithographically patterned polysilicon gates. The SET is used to sense the occupancy of the electron on the donor and for spin read-out. An adjacent transmission line allows the application of microwave pulses to rotate the spin of the electron. We will present data from various experiments designed to exploit these capabilities. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. The work was supported by Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

Nanophotonic applications for silicon-on-insulator (SOI)

NASA Astrophysics Data System (ADS)

de la Houssaye, Paul R.; Russell, Stephen D.; Shimabukuro, Randy L.

2004-07-01

Silicon-on-insulator is a proven technology for very large scale integration of microelectronic devices. The technology also offers the potential for development of nanophotonic devices and the ability to interface such devices to the macroscopic world. This paper will report on fabrication techniques used to form nano-structured silicon wires on an insulating structure that is amenable to interfacing nanostructured sensors with high-performance microelectronic circuitry for practical implementation. Nanostructures formed on silicon-on-sapphire can also exploit the transparent substrate for novel device geometries. This research harnesses the unique properties of a high-quality single crystal film of silicon on sapphire and uses the film thickness as one of the confinement dimensions. Lateral arrays of silicon nanowires were fabricated in the thin (5 to 20 nm) silicon layer and studied. This technique offers simplified contact to individual wires and provides wire surfaces that are more readily accessible for controlled alteration and device designs.

Metal organic chemical vapor deposition of 111-v compounds on silicon

DOEpatents

Vernon, Stanley M.

1986-01-01

Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.

Silicon insulator-based dielectrophoresis devices for minimized heating effects.

PubMed

Zellner, Phillip; Agah, Masoud

2012-08-01

Concentration of biological specimens that are extremely dilute in a solution is of paramount importance for their detection. Microfluidic chips based on insulator-based DEP (iDEP) have been used to selectively concentrate bacteria and viruses. iDEP biochips are currently fabricated with glass or polymer substrates to allow for high electric fields within the channels. Joule heating is a well-known problem in these substrates and can lead to decreased throughput and even device failure. In this work, we present, for the first time, highly efficient trapping and separation of particles in DC iDEP devices that are fabricated on silicon using a single-etch-step three-dimensional microfabrication process with greatly improved heat dissipation properties. Fabrication in silicon allows for greater heat dissipation for identical geometries and operating conditions. The 3D fabrication allows for higher performance at lower applied potentials. Thermal measurements were performed on both the presented silicon chips and previously published PDMS devices comprised of microposts. Trapping and separation of 1 and 2 μm polystyrene particles was demonstrated. These results demonstrate the feasibility of high-performance silicon iDEP devices for the next generation of sorting and concentration microsystems. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Deposition method for producing silicon carbide high-temperature semiconductors

DOEpatents

Hsu, George C.; Rohatgi, Naresh K.

1987-01-01

An improved deposition method for producing silicon carbide high-temperature semiconductor material comprising placing a semiconductor substrate composed of silicon carbide in a fluidized bed silicon carbide deposition reactor, fluidizing the bed particles by hydrogen gas in a mildly bubbling mode through a gas distributor and heating the substrate at temperatures around 1200.degree.-1500.degree. C. thereby depositing a layer of silicon carbide on the semiconductor substrate.

Solution-processed polycrystalline silicon on paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Trifunovic, M.; Ishihara, R., E-mail: r.ishihara@tudelft.nl; Shimoda, T.

Printing electronics has led to application areas which were formerly impossible with conventional electronic processes. Solutions are used as inks on top of large areas at room temperatures, allowing the production of fully flexible circuitry. Commonly, research in these inks have focused on organic and metal-oxide ink materials due to their printability, while these materials lack in the electronic performance when compared to silicon electronics. Silicon electronics, on the other hand, has only recently found their way in solution processes. Printing of cyclopentasilane as the silicon ink has been conducted and devices with far superior electric performance have been mademore » when compared to other ink materials. A thermal annealing step of this material, however, was necessary, which prevented its usage on inexpensive substrates with a limited thermal budget. In this work, we introduce a method that allows polycrystalline silicon (poly-Si) production directly from the same liquid silicon ink using excimer laser irradiation. In this way, poly-Si could be formed directly on top of paper even with a single laser pulse. Using this method, poly-Si transistors were created at a maximum temperature of only 150 °C. This method allows silicon device formation on inexpensive, temperature sensitive substrates such as polyethylene terephthalate, polyethylene naphthalate or paper, which leads to applications that require low-cost but high-speed electronics.« less

Composite Reflective Absorptive IR-Blocking Filters Embedded in Metamaterial Antireflection Coated Silicon

NASA Technical Reports Server (NTRS)

Munson, C. D.; Choi, S. K.; Coughlin, K. P.; McMahon, J. J.; Miller, K. H.; Page, L. A.; Wollack, E. J.

2017-01-01

Infrared (IR)-blocking filters are crucial for controlling the radiative loading on cryogenic systems and for optimizing the sensitivity of bolometric detectors in the far-IR. We present a new IR filter approach based on a combination of patterned frequency-selective structures on silicon and a thin (2575 micron thick) absorptive composite based on powdered reststrahlen absorbing materials. For a 300 K blackbody, this combination reflects approximately 50% of the incoming light and blocks greater than.99.8% of the total power with negligible thermal gradients and excellent low-frequency transmission. This allows a reduction in the IR thermal loading to negligible levels in a single cold filter. These composite filters are fabricated on silicon substrates, which provide excellent thermal transport laterally through the filter and ensure that the entire area of the absorptive filter stays near the bath temperature. A metamaterial antireflection coating cut into these substrates reduces in-band reflections to below 1%, and the in-band absorption of the powder mix is below 1% for signal bands below 750 GHz. This type of filter can be directly incorporated into silicon refractive optical elements.

Dielectrophoretic trapping of multilayer DNA origami nanostructures and DNA origami-induced local destruction of silicon dioxide.

PubMed

Shen, Boxuan; Linko, Veikko; Dietz, Hendrik; Toppari, J Jussi

2015-01-01

DNA origami is a widely used method for fabrication of custom-shaped nanostructures. However, to utilize such structures, one needs to controllably position them on nanoscale. Here we demonstrate how different types of 3D scaffolded multilayer origamis can be accurately anchored to lithographically fabricated nanoelectrodes on a silicon dioxide substrate by DEP. Straight brick-like origami structures, constructed both in square (SQL) and honeycomb lattices, as well as curved "C"-shaped and angular "L"-shaped origamis were trapped with nanoscale precision and single-structure accuracy. We show that the positioning and immobilization of all these structures can be realized with or without thiol-linkers. In general, structural deformations of the origami during the DEP trapping are highly dependent on the shape and the construction of the structure. The SQL brick turned out to be the most robust structure under the high DEP forces, and accordingly, its single-structure trapping yield was also highest. In addition, the electrical conductivity of single immobilized plain brick-like structures was characterized. The electrical measurements revealed that the conductivity is negligible (insulating behavior). However, we observed that the trapping process of the SQL brick equipped with thiol-linkers tended to induce an etched "nanocanyon" in the silicon dioxide substrate. The nanocanyon was formed exactly between the electrodes, that is, at the location of the DEP-trapped origami. The results show that the demonstrated DEP-trapping technique can be readily exploited in assembling and arranging complex multilayered origami geometries. In addition, DNA origamis could be utilized in DEP-assisted deformation of the substrates onto which they are attached. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Polyelectrolyte multilayer-assisted fabrication of non-periodic silicon nanocolumn substrates for cellular interface applications

NASA Astrophysics Data System (ADS)

Lee, Seyeong; Kim, Dongyoon; Kim, Seong-Min; Kim, Jeong-Ah; Kim, Taesoo; Kim, Dong-Yu; Yoon, Myung-Han

2015-08-01

Recent advances in nanostructure-based biotechnology have resulted in a growing demand for vertical nanostructure substrates with elaborate control over the nanoscale geometry and a high-throughput preparation. In this work, we report the fabrication of non-periodic vertical silicon nanocolumn substrates via polyelectrolyte multilayer-enabled randomized nanosphere lithography. Owing to layer-by-layer deposited polyelectrolyte adhesives, uniformly-separated polystyrene nanospheres were securely attached on large silicon substrates and utilized as masks for the subsequent metal-assisted silicon etching in solution. Consequently, non-periodic vertical silicon nanocolumn arrays were successfully fabricated on a wafer scale, while each nanocolumn geometric factor, such as the diameter, height, density, and spatial patterning, could be fully controlled in an independent manner. Finally, we demonstrate that our vertical silicon nanocolumn substrates support viable cell culture with minimal cell penetration and unhindered cell motility due to the blunt nanocolumn morphology. These results suggest that vertical silicon nanocolumn substrates may serve as a useful cellular interface platform for performing a statistically meaningful number of cellular experiments in the fields of biomolecular delivery, stem cell research, etc.Recent advances in nanostructure-based biotechnology have resulted in a growing demand for vertical nanostructure substrates with elaborate control over the nanoscale geometry and a high-throughput preparation. In this work, we report the fabrication of non-periodic vertical silicon nanocolumn substrates via polyelectrolyte multilayer-enabled randomized nanosphere lithography. Owing to layer-by-layer deposited polyelectrolyte adhesives, uniformly-separated polystyrene nanospheres were securely attached on large silicon substrates and utilized as masks for the subsequent metal-assisted silicon etching in solution. Consequently, non-periodic vertical silicon nanocolumn arrays were successfully fabricated on a wafer scale, while each nanocolumn geometric factor, such as the diameter, height, density, and spatial patterning, could be fully controlled in an independent manner. Finally, we demonstrate that our vertical silicon nanocolumn substrates support viable cell culture with minimal cell penetration and unhindered cell motility due to the blunt nanocolumn morphology. These results suggest that vertical silicon nanocolumn substrates may serve as a useful cellular interface platform for performing a statistically meaningful number of cellular experiments in the fields of biomolecular delivery, stem cell research, etc. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr02384j

Compact Radiative Control Structures for Millimeter Astronomy

NASA Technical Reports Server (NTRS)

Brown, Ari D.; Chuss, David T.; Chervenak, James A.; Henry, Ross M.; Moseley, s. Harvey; Wollack, Edward J.

2010-01-01

We have designed, fabricated, and tested compact radiative control structures, including antireflection coatings and resonant absorbers, for millimeter through submillimeter wave astronomy. The antireflection coatings consist of micromachined single crystal silicon dielectric sub-wavelength honeycombs. The effective dielectric constant of the structures is set by the honeycomb cell geometry. The resonant absorbers consist of pieces of solid single crystal silicon substrate and thin phosphorus implanted regions whose sheet resistance is tailored to maximize absorption by the structure. We present an implantation model that can be used to predict the ion energy and dose required for obtaining a target implant layer sheet resistance. A neutral density filter, a hybrid of a silicon dielectric honeycomb with an implanted region, has also been fabricated with this basic approach. These radiative control structures are scalable and compatible for use large focal plane detector arrays.

Fabrication of a 20.5-inch-diameter segmented silicon annular optic prototype for the ROMA program

NASA Astrophysics Data System (ADS)

Hassell, Frank R.; Groark, Frank M.

1995-10-01

Recent advancements in single crystal silicon material science and fabrication capabilities and very low absorption (VLA) multi-layer dielectric coating technology have led to the development of uncooled, large aperture, high power mirrors for high energy laser (HEL) systems. Based on this success, a segmented single-crystal silicon substrate concept has been selected as the baseline fabrication approach for uncooled 1.2 meter diameter resonator annular optics for the Alpha space based high energy laser. The objective of this Resonator Optics Materials Assessment (ROMA) task was to demonstrate all of the key fabrication processes required to fabricate the full sized annular optics for the Alpha space based high energy laser. This paper documents the fabrication of a half-scale annular optic prototype (AOP) of the Alpha laser rear cone.

Application Of Optical Processing For Growth Of Silicon Dioxide

DOEpatents

Sopori, Bhushan L.

1997-06-17

A process for producing a silicon dioxide film on a surface of a silicon substrate. The process comprises illuminating a silicon substrate in a substantially pure oxygen atmosphere with a broad spectrum of visible and infrared light at an optical power density of from about 3 watts/cm.sup.2 to about 6 watts/cm.sup.2 for a time period sufficient to produce a silicon dioxide film on the surface of the silicon substrate. An optimum optical power density is about 4 watts/cm.sup.2 for growth of a 100.ANG.-300.ANG. film at a resultant temperature of about 400.degree. C. Deep level transient spectroscopy analysis detects no measurable impurities introduced into the silicon substrate during silicon oxide production and shows the interface state density at the SiO.sub.2 /Si interface to be very low.

Fabricating amorphous silicon solar cells by varying the temperature _of the substrate during deposition of the amorphous silicon layer

DOEpatents

Carlson, David E.

1982-01-01

An improved process for fabricating amorphous silicon solar cells in which the temperature of the substrate is varied during the deposition of the amorphous silicon layer is described. Solar cells manufactured in accordance with this process are shown to have increased efficiencies and fill factors when compared to solar cells manufactured with a constant substrate temperature during deposition of the amorphous silicon layer.

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

PubMed

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

Integration of lateral porous silicon membranes into planar microfluidics.

PubMed

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

SCMOS (Scalable Complementary Metal Oxide Silicon) Silicon Compiler Organelle Design and Insertion.

DTIC Science & Technology

1987-12-01

polysilicon running horizontally), with the p-type toward Vdd and the n-type toward GND. * Substrate contacts are connected by metal to supply rails...IN’) + (CIN’) Note: The single quote (’) represents the ’not’ of the variable. Figure 2.3 Logic Expressions.. * First metal and polysilicon are... polysilicon . *All external connections to 1,10, CLOCK, Vdd and G.ND end at least 2 units past first metal that is not an 1,0 point. *All external

Self-formed cylindrical microcapillaries through surface migration of silicon and their application to single-cell analysis

NASA Astrophysics Data System (ADS)

Zeng, Fan; Luo, Yuan; Yobas, Levent; Wong, Man

2013-05-01

Surface migration of monocrystalline silicon has been applied to demonstrate self-formed cylindrical microcapillaries with diameters from 0.8 to 2.8 µm based on the microstructured substrate topography. The microcapillaries are entirely enclosed in silicon and can be conveniently etched to create fluidic access ports and microchannels for their subsequent integration into functional microfluidic devices. Moreover, the microcapillaries can be thermally oxidized through their access ports with silica walls remain intact upon release from surrounding silicon in an effort to enhance optical clarity. Straight microcapillaries and microcapillaries with perpendicular turns and crossings (junctions) have all been fabricated and validated for fluidic continuity with a fluorescein solution pumped through. The utility of the microcapillaries has been showcased on particle traps in which biological cells are probed for single-cell impedance spectroscopy. The approach disclosed, given its full compatibility with semiconductor device fabrication, offers great potential towards intelligent cell and molecule-based devices merging microelectronics and microfluidics.

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

PubMed Central

Hazut, Ori; Agarwala, Arunava; Subramani, Thangavel; Waichman, Sharon; Yerushalmi, Roie

2013-01-01

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms. In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station. PMID:24326774

Quantum dots in single electron transistors with ultrathin silicon-on-insulator structures

NASA Astrophysics Data System (ADS)

Ihara, S.; Andreev, A.; Williams, D. A.; Kodera, T.; Oda, S.

2015-07-01

We report on fabrication and transport properties of lithographically defined single quantum dots (QDs) in single electron transistors with ultrathin silicon-on-insulator (SOI) substrate. We observed comparatively large charging energy E C ˜ 20 meV derived from the stability diagram at a temperature of 4.2 K. We also carried out three-dimensional calculations of the capacitance matrix and transport properties through the QD for the real structure geometry and found an excellent quantitative agreement with experiment of the calculated main parameters of stability diagram (charging energy, period of Coulomb oscillations, and asymmetry of the diamonds). The obtained results confirm fabrication of well-defined integrated QDs as designed with ultrathin SOI that makes it possible to achieve relatively large QD charging energies, which is useful for stable and high temperature operation of single electron devices.

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Method for forming metallic silicide films on silicon substrates by ion beam deposition

DOEpatents

Zuhr, Raymond A.; Holland, Orin W.

1990-01-01

Metallic silicide films are formed on silicon substrates by contacting the substrates with a low-energy ion beam of metal ions while moderately heating the substrate. The heating of the substrate provides for the diffusion of silicon atoms through the film as it is being formed to the surface of the film for interaction with the metal ions as they contact the diffused silicon. The metallic silicide films provided by the present invention are contaminant free, of uniform stoichiometry, large grain size, and exhibit low resistivity values which are of particular usefulness for integrated circuit production.

Broadband electromagnetic dipole scattering by coupled multiple nanospheres

NASA Astrophysics Data System (ADS)

Jing, Xufeng; Ye, Qiufeng; Hong, Zhi; Zhu, Dongshuo; Shi, Guohua

2017-11-01

With the development of nanotechnology, the ability to manipulate light at the nanoscale is critical to future optical functional devices. The use of high refractive index dielectric single silicon nanoparticle can achieve electromagnetic dipole resonant properties. Compared with single nanosphere, the use of dimer and trimer introduces an additional dimension (gap size) for improving the performance of dielectric optical devices through the coupling between closely connected silicon nanospheres. When changing the gap size between the nanospheres, the interaction between the particles can be from weak to strong. Compared with single nanospheres, dimerized or trimeric nanospheres exhibit more pronounced broadband scattering properties. In addition, by introducing more complex interaction, the trimericed silicon nanospheres exhibit a more significant increase in bandwidth than expected. In addition, the presence of the substrate will also contribute to the increase in the bandwidth of the nanospheres. The broadband response in dielectric nanostructures can be effectively applied to broadband applications such as dielectric nanoantennas or solar cells.

Back-side hydrogenation technique for defect passivation in silicon solar cells

DOEpatents

Sopori, Bhushan L.

1994-01-01

A two-step back-side hydrogenation process includes the steps of first bombarding the back side of the silicon substrate with hydrogen ions with intensities and for a time sufficient to implant enough hydrogen atoms into the silicon substrate to potentially passivate substantially all of the defects and impurities in the silicon substrate, and then illuminating the silicon substrate with electromagnetic radiation to activate the implanted hydrogen, so that it can passivate the defects and impurities in the substrate. The illumination step also annihilates the hydrogen-induced defects. The illumination step is carried out according to a two-stage illumination schedule, the first or low-power stage of which subjects the substrate to electromagnetic radiation that has sufficient intensity to activate the implanted hydrogen, yet not drive the hydrogen from the substrate. The second or high-power illumination stage subjects the substrate to higher intensity electromagnetic radiation, which is sufficient to annihilate the hydrogen-induced defects and sinter/alloy the metal contacts.

Back-side hydrogenation technique for defect passivation in silicon solar cells

DOEpatents

Sopori, B.L.

1994-04-19

A two-step back-side hydrogenation process includes the steps of first bombarding the back side of the silicon substrate with hydrogen ions with intensities and for a time sufficient to implant enough hydrogen atoms into the silicon substrate to potentially passivate substantially all of the defects and impurities in the silicon substrate, and then illuminating the silicon substrate with electromagnetic radiation to activate the implanted hydrogen, so that it can passivate the defects and impurities in the substrate. The illumination step also annihilates the hydrogen-induced defects. The illumination step is carried out according to a two-stage illumination schedule, the first or low-power stage of which subjects the substrate to electromagnetic radiation that has sufficient intensity to activate the implanted hydrogen, yet not drive the hydrogen from the substrate. The second or high-power illumination stage subjects the substrate to higher intensity electromagnetic radiation, which is sufficient to annihilate the hydrogen-induced defects and sinter/alloy the metal contacts. 3 figures.

High quality silicon-based substrates for microwave and millimeter wave passive circuits

NASA Astrophysics Data System (ADS)

Belaroussi, Y.; Rack, M.; Saadi, A. A.; Scheen, G.; Belaroussi, M. T.; Trabelsi, M.; Raskin, J.-P.

2017-09-01

Porous silicon substrate is very promising for next generation wireless communication requiring the avoidance of high-frequency losses originating from the bulk silicon. In this work, new variants of porous silicon (PSi) substrates have been introduced. Through an experimental RF performance, the proposed PSi substrates have been compared with different silicon-based substrates, namely, standard silicon (Std), trap-rich (TR) and high resistivity (HR). All of the mentioned substrates have been fabricated where identical samples of CPW lines have been integrated on. The new PSi substrates have shown successful reduction in the substrate's effective relative permittivity to values as low as 3.7 and great increase in the substrate's effective resistivity to values higher than 7 kΩ cm. As a concept proof, a mm-wave bandpass filter (MBPF) centred at 27 GHz has been integrated on the investigated substrates. Compared with the conventional MBPF implemented on standard silicon-based substrates, the measured S-parameters of the PSi-based MBPF have shown high filtering performance, such as a reduction in insertion loss and an enhancement of the filter selectivity, with the joy of having the same filter performance by varying the temperature. Therefore, the efficiency of the proposed PSi substrates has been well highlighted. From 1994 to 1995, she was assistant of physics at (USTHB), Algiers . From 1998 to 2011, she was a Researcher at characterization laboratory in ionized media and laser division at the Advanced Technologies Development Center. She has integrated the Analog Radio Frequency Integrated Circuits team as Researcher since 2011 until now in Microelectronic and Nanotechnology Division at Advanced Technologies Development Center (CDTA), Algiers. She has been working towards her Ph.D. degree jointly at CDTA and Ecole Nationale Polytechnique, Algiers, since 2012. Her research interest includes fabrication and characterization of microwave passive devices on porous silicon as new substrate, such as characterization of FinFET components.

Application of optical processing for growth of silicon dioxide

DOEpatents

Sopori, B.L.

1997-06-17

A process for producing a silicon dioxide film on a surface of a silicon substrate is disclosed. The process comprises illuminating a silicon substrate in a substantially pure oxygen atmosphere with a broad spectrum of visible and infrared light at an optical power density of from about 3 watts/cm{sup 2} to about 6 watts/cm{sup 2} for a time period sufficient to produce a silicon dioxide film on the surface of the silicon substrate. An optimum optical power density is about 4 watts/cm{sup 2} for growth of a 100{angstrom}-300{angstrom} film at a resultant temperature of about 400 C. Deep level transient spectroscopy analysis detects no measurable impurities introduced into the silicon substrate during silicon oxide production and shows the interface state density at the SiO{sub 2}/Si interface to be very low. 1 fig.

A theoretical analysis of steady-state photocurrents in simple silicon diodes

NASA Technical Reports Server (NTRS)

Edmonds, L.

1995-01-01

A theoretical analysis solves for the steady-state photocurrents produced by a given photo-generation rate function with negligible recombination in simple silicon diodes, consisting of a uniformly doped quasi-neutral region (called 'substrate' below) adjacent to a p-n junction depletion region (DR). Special attention is given to conditions that produce 'funneling' (a term used by the single-eventeffects community) under steady-state conditions. Funneling occurs when carriers are generated so fast that the DR becomes flooded and partially or completely collapses. Some or nearly all of the applied voltage, plus built-in potential normally across the DR, is now across the substrate. This substrate voltage drop affects substrate currents. The steady-state problem can provide some qualitative insights into the more difficult transient problem. First, it was found that funneling can be induced from a distance, i.e., from carriers generated at locations outside of the DR. Secondly, it was found that the substrate can divide into two subregions, with one controlling substrate resistance and the other characterized by ambipolar diffusion. Finally, funneling was found to be more difficult to induce in the p(sup +)/n diode than in the n(sup +)/p diode. The carrier density exceeding the doping density in the substrate and at the DR boundary is not a sufficient condition to collapse a DR.

Hexagonal AlN Layers Grown on Sulfided Si(100) Substrate

NASA Astrophysics Data System (ADS)

Bessolov, V. N.; Gushchina, E. V.; Konenkova, E. V.; L'vova, T. V.; Panteleev, V. N.; Shcheglov, M. P.

2018-01-01

We have studied the influence of sulfide passivation on the initial stages of aluminum nitride (AlN)-layer nucleation and growth by hydride vapor-phase epitaxy (HVPE) on (100)-oriented single-crystalline silicon substrates. It is established that the substrate pretreatment in (NH4)2S aqueous solution leads to the columnar nucleation of hexagonal AlN crystals of two modifications rotated by 30° relative to each other. Based on the sulfide treatment, a simple method of oxide removal from and preparation of Si(100) substrate surface is developed that can be used for the epitaxial growth of group-III nitride layers.

Single neuronal recordings using surface micromachined polysilicon microelectrodes.

PubMed

Muthuswamy, Jit; Okandan, Murat; Jackson, Nathan

2005-03-15

Bulk micromachining techniques of silicon have been used successfully in the past several years to microfabricate microelectrodes for monitoring single neurons in acute and chronic experiments. In this study we report for the first time a novel surface micromachining technique to microfabricate a very thin polysilicon microelectrode that can be used for monitoring single-unit activity in the central nervous system. The microelectrodes are 3 mm long and 50 microm x 3.75 microm in cross-section. Excellent signal to noise ratios in the order of 25-35 dB were obtained while recording neuronal action potentials. The microelectrodes successfully penetrated the brains after a microincision of the dura mater. Chronic implantation of the microprobe for up to 33 days produced only minor gliosis. Since the polysilicon shank acts as a conductor, additional processing steps involved in laying conductor lines on silicon substrates are avoided. Further, surface micromachining allows for fabricating extremely thin microelectrodes which could result in decreased inflammatory responses. We conclude that the polysilicon microelectrode reported here could be a complementary approach to bulk-micromachined silicon microelectrodes for chronic monitoring of single neurons in the central nervous system.

Reversible gating of smart plasmonic molecular traps using thermoresponsive polymers for single-molecule detection

PubMed Central

Zheng, Yuanhui; Soeriyadi, Alexander H.; Rosa, Lorenzo; Ng, Soon Hock; Bach, Udo; Justin Gooding, J.

2015-01-01

Single-molecule surface-enhanced Raman spectroscopy (SERS) has attracted increasing interest for chemical and biochemical sensing. Many conventional substrates have a broad distribution of SERS enhancements, which compromise reproducibility and result in slow response times for single-molecule detection. Here we report a smart plasmonic sensor that can reversibly trap a single molecule at hotspots for rapid single-molecule detection. The sensor was fabricated through electrostatic self-assembly of gold nanoparticles onto a gold/silica-coated silicon substrate, producing a high yield of uniformly distributed hotspots on the surface. The hotspots were isolated with a monolayer of a thermoresponsive polymer (poly(N-isopropylacrylamide)), which act as gates for molecular trapping at the hotspots. The sensor shows not only a good SERS reproducibility but also a capability to repetitively trap and release molecules for single-molecular sensing. The single-molecule sensitivity is experimentally verified using SERS spectral blinking and bianalyte methods. PMID:26549539

Method for rapid, controllable growth and thickness, of epitaxial silicon films

DOEpatents

Wang, Qi [Littleton, CO; Stradins, Paul [Golden, CO; Teplin, Charles [Boulder, CO; Branz, Howard M [Boulder, CO

2009-10-13

A method of producing epitaxial silicon films on a c-Si wafer substrate using hot wire chemical vapor deposition by controlling the rate of silicon deposition in a temperature range that spans the transition from a monohydride to a hydrogen free silicon surface in a vacuum, to obtain phase-pure epitaxial silicon film of increased thickness is disclosed. The method includes placing a c-Si substrate in a HWCVD reactor chamber. The method also includes supplying a gas containing silicon at a sufficient rate into the reaction chamber to interact with the substrate to deposit a layer containing silicon thereon at a predefined growth rate to obtain phase-pure epitaxial silicon film of increased thickness.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Electrochemical Fabrication of Nanostructures on Porous Silicon for Biochemical Sensing Platforms.

PubMed

Ko, Euna; Hwang, Joonki; Kim, Ji Hye; Lee, Joo Heon; Lee, Sung Hwan; Tran, Van-Khue; Chung, Woo Sung; Park, Chan Ho; Choo, Jaebum; Seong, Gi Hun

2016-01-01

We present a method for the electrochemical patterning of gold nanoparticles (AuNPs) or silver nanoparticles (AgNPs) on porous silicon, and explore their applications in: (1) the quantitative analysis of hydroxylamine as a chemical sensing electrode and (2) as a highly sensitive surface-enhanced Raman spectroscopy (SERS) substrate for Rhodamine 6G. For hydroxylamine detection, AuNPs-porous silicon can enhance the electrochemical oxidation of hydroxylamine. The current changed linearly for concentrations ranging from 100 μM to 1.32 mM (R(2) = 0.995), and the detection limit was determined to be as low as 55 μM. When used as SERS substrates, these materials also showed that nanoparticles decorated on porous silicon substrates have more SERS hot spots than those decorated on crystalline silicon substrates, resulting in a larger SERS signal. Moreover, AgNPs-porous silicon provided five-times higher signal compared to AuNPs-porous silicon. From these results, we expect that nanoparticles decorated on porous silicon substrates can be used in various types of biochemical sensing platforms.

Wafer bonded epitaxial templates for silicon heterostructures

DOEpatents

Atwater, Jr., Harry A.; Zahler, James M [Pasadena, CA; Morral, Anna Fontcubera I [Paris, FR

2008-03-11

A heterostructure device layer is epitaxially grown on a virtual substrate, such as an InP/InGaAs/InP double heterostructure. A device substrate and a handle substrate form the virtual substrate. The device substrate is bonded to the handle substrate and is composed of a material suitable for fabrication of optoelectronic devices. The handle substrate is composed of a material suitable for providing mechanical support. The mechanical strength of the device and handle substrates is improved and the device substrate is thinned to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. An upper portion of the device film exfoliated from the device substrate is removed to provide a smoother and less defect prone surface for an optoelectronic device. A heterostructure is epitaxially grown on the smoothed surface in which an optoelectronic device may be fabricated.

Wafer bonded epitaxial templates for silicon heterostructures

NASA Technical Reports Server (NTRS)

Atwater, Harry A., Jr. (Inventor); Zahler, James M. (Inventor); Morral, Anna Fontcubera I (Inventor)

2008-01-01

A heterostructure device layer is epitaxially grown on a virtual substrate, such as an InP/InGaAs/InP double heterostructure. A device substrate and a handle substrate form the virtual substrate. The device substrate is bonded to the handle substrate and is composed of a material suitable for fabrication of optoelectronic devices. The handle substrate is composed of a material suitable for providing mechanical support. The mechanical strength of the device and handle substrates is improved and the device substrate is thinned to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. An upper portion of the device film exfoliated from the device substrate is removed to provide a smoother and less defect prone surface for an optoelectronic device. A heterostructure is epitaxially grown on the smoothed surface in which an optoelectronic device may be fabricated.

Method of bonding silver to glass and mirrors produced according to this method

DOEpatents

Pitts, J.R.; Thomas, T.M.; Czanderna, A.W.

1984-07-31

A method for adhering silver to a glass substrate for producing mirrors includes attaining a silicon enriched substrate surface by reducing the oxygen therein in a vacuum and then vacuum depositing a silver layer onto the silicon enriched surface. The silicon enrichment can be attained by electron beam bombardment, ion beam bombardment, or neutral beam bombardment. It can also be attained by depositing a metal, such as aluminum, on the substrate surface, allowing the metal to oxidize by pulling oxygen from the substrate surface, thereby leaving a silicon enriched surface, and then etching or eroding the metal oxide layer away to expose the silicon enriched surface. Ultraviolet rays can be used to maintain dangling silicon bonds on the enriched surface until covalent bonding with the silver can occur. This disclosure also includes encapsulated mirrors with diffusion layers built therein. One of these mirrors is assembled on a polymer substrate.

Method of bonding silver to glass and mirrors produced according to this method

DOEpatents

Pitts, John R.; Thomas, Terence M.; Czanderna, Alvin W.

1985-01-01

A method for adhering silver to a glass substrate for producing mirrors includes attaining a silicon enriched substrate surface by reducing the oxygen therein in a vacuum and then vacuum depositing a silver layer onto the silicon enriched surface. The silicon enrichment can be attained by electron beam bombardment, ion beam bombardment, or neutral beam bombardment. It can also be attained by depositing a metal, such as aluminum, on the substrate surface, allowing the metal to oxidize by pulling oxygen from the substrate surface, thereby leaving a silicon enriched surface, and then etching or eroding the metal oxide layer away to expose the silicon enriched surface. Ultraviolet rays can be used to maintain dangling silicon bonds on the enriched surface until covalent bonding with the silver can occur. This disclosure also includes encapsulated mirrors with diffusion layers built therein. One of these mirrors is assembled on a polymer substrate.

Investigations of different doping concentration of phosphorus and boron into silicon substrate on the variable temperature Raman characteristics

NASA Astrophysics Data System (ADS)

Li, Xiaoli; Ding, Kai; Liu, Jian; Gao, Junxuan; Zhang, Weifeng

2018-01-01

Different doped silicon substrates have different device applications and have been used to fabricate solar panels and large scale integrated circuits. The thermal transport in silicon substrates are dominated by lattice vibrations, doping type, and doping concentration. In this paper, a variable-temperature Raman spectroscopic system is applied to record the frequency and linewidth changes of the silicon peak at 520 cm-1 in five chips of silicon substrate with different doping concentration of phosphorus and boron at the 83K to 1473K temperature range. The doping has better heat sensitive to temperature on the frequency shift over the low temperature range from 83K to 300K but on FWHM in high temperature range from 300K to 1473K. The results will be helpful for fundamental study and practical applications of silicon substrates.

Effects of patterning induced stress relaxation in strained SOI/SiGe layers and substrate

NASA Astrophysics Data System (ADS)

Hermann, P.; Hecker, M.; Renn, F.; Rölke, M.; Kolanek, K.; Rinderknecht, J.; Eng, L. M.

2011-06-01

Local stress fields in strained silicon structures important for CMOS technology are essentially related to size effects and properties of involved materials. In the present investigation, Raman spectroscopy was utilized to analyze the stress distribution within strained silicon (sSi) and silicon-germanium (SiGe) island structures. As a result of the structuring of initially unpatterned strained films, a size-dependent relaxation of the intrinsic film stresses was obtained in agreement with model calculations. This changed stress state in the features also results in the appearance of opposing stresses in the substrate underneath the islands. Even for strained island structures on top of silicon-on-insulator (SOI) wafers, corresponding stresses in the silicon substrate underneath the oxide were detected. Within structures, the stress relaxation is more pronounced for islands on SOI substrates as compared to those on bulk silicon substrates.

Development of a physical and electronic model for RuO 2 nanorod rectenna devices

NASA Astrophysics Data System (ADS)

Dao, Justin

Ruthenium oxide (RuO2) nanorods are an emergent technology in nanostructure devices. As the physical size of electronics approaches a critical lower limit, alternative solutions to further device miniaturization are currently under investigation. Thin-film nanorod growth is an interesting technology, being investigated for use in wireless communications, sensor systems, and alternative energy applications. In this investigation, self-assembled RuO2 nanorods are grown on a variety of substrates via a high density plasma, reactive sputtering process. Nanorods have been found to grow on substrates that form native oxide layers when exposed to air, namely silicon, aluminum, and titanium. Samples were analyzed with Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) techniques. Conductive Atomic Force Microscopy (C-AFM) measurements were performed on single nanorods to characterize structure and electrical conductivity. The C-AFM probe tip is placed on a single nanorod and I-V characteristics are measured, potentially exhibiting rectifying capabilities. An analysis of these results using fundamental semiconductor physics principles is presented. Experimental data for silicon substrates was most closely approximated by the Simmons model for direct electron tunneling, whereas that of aluminum substrates was well approximated by Fowler-Nordheim tunneling. The native oxide of titanium is regarded as a semiconductor rather than an insulator and its ability to function as a rectifier is not strong. An electronic model for these nanorods is described herein.

Improved process for epitaxial deposition of silicon on prediffused substrates

NASA Technical Reports Server (NTRS)

Clarke, M. G.; Halsor, J. L.; Word, J. C.

1968-01-01

Process for fabricating integrated circuits uniformly deposits silicon epitaxially on prediffused substrates without affecting the sublayer diffusion pattern. Two silicon deposits from different sources, and deposited at different temperatures, protect the sublayer pattern from the silicon tetrachloride reaction.

Electrical leakage phenomenon in heteroepitaxial cubic silicon carbide on silicon

NASA Astrophysics Data System (ADS)

Pradeepkumar, Aiswarya; Zielinski, Marcin; Bosi, Matteo; Verzellesi, Giovanni; Gaskill, D. Kurt; Iacopi, Francesca

2018-06-01

Heteroepitaxial 3C-SiC films on silicon substrates are of technological interest as enablers to integrate the excellent electrical, electronic, mechanical, thermal, and epitaxial properties of bulk silicon carbide into well-established silicon technologies. One critical bottleneck of this integration is the establishment of a stable and reliable electronic junction at the heteroepitaxial interface of the n-type SiC with the silicon substrate. We have thus investigated in detail the electrical and transport properties of heteroepitaxial cubic silicon carbide films grown via different methods on low-doped and high-resistivity silicon substrates by using van der Pauw Hall and transfer length measurements as test vehicles. We have found that Si and C intermixing upon or after growth, particularly by the diffusion of carbon into the silicon matrix, creates extensive interstitial carbon traps and hampers the formation of a stable rectifying or insulating junction at the SiC/Si interface. Although a reliable p-n junction may not be realistic in the SiC/Si system, we can achieve, from a point of view of the electrical isolation of in-plane SiC structures, leakage suppression through the substrate by using a high-resistivity silicon substrate coupled with deep recess etching in between the SiC structures.

Crystal defects in solar cells produced by the method of thermomigration

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lozovskii, V. N.; Lomov, A. A.; Lunin, L. S.

2017-03-15

The results of studying the crystal structure of regions in silicon, recrystallized during the course of thermomigration of the liquid Si–Al zone in the volume of the silicon substrate, are reported (similar regions doped with an acceptor impurity are used to obtain high-voltage solar cells). X-ray methods (including measurements of both diffraction-reflection curves and topograms) and also high-resolution electron microscopy indicate that single-crystal regions in the form of a series of thin strips or rectangular grids are formed as a result of the thermomigration of liquid zones. Dislocation half-loops are detected in the surface layers of the front and backmore » surfaces of the substrate. (311)-type defects are observed in the recrystallized regions.« less

Dip-Coating Fabrication of Solar Cells

NASA Technical Reports Server (NTRS)

Koepke, B.; Suave, D.

1982-01-01

Inexpensive silicon solar cells made by simple dip technique. Cooling shoes direct flow of helium on graphite-coated ceramic substrate to solidify film of liquid silicon on graphite surface as substrate is withdrawn from molten silicon. After heaters control cooling of film and substrate to prevent cracking. Gas jets exit at points about 10 mm from substrate surfaces and 6 to 10 mm above melt surface.

Linear integrated optics in 3C silicon carbide.

PubMed

Martini, Francesco; Politi, Alberto

2017-05-15

The development of new photonic materials that combine diverse optical capabilities is needed to boost the integration of different quantum and classical components within the same chip. Amongst all candidates, the superior optical properties of cubic silicon carbide (3C SiC) could be merged with its crystalline point defects, enabling single photon generation, manipulation and light-matter interaction on a single device. The development of photonics devices in SiC has been limited by the presence of the silicon substrate, over which thin crystalline films are heteroepitaxially grown. By employing a novel approach in the material fabrication, we demonstrate grating couplers with coupling efficiency reaching -6 dB, sub-µm waveguides and high intrinsic quality factor (up to 24,000) ring resonators. These components are the basis for linear optical networks and essential for developing a wide range of photonics component for non-linear and quantum optics.

Nanoparticle-nanoparticle vs. nanoparticle-substrate hot spot contributions to the SERS signal: studying Raman labelled monomers, dimers and trimers.

PubMed

Sergiienko, Sergii; Moor, Kamila; Gudun, Kristina; Yelemessova, Zarina; Bukasov, Rostislav

2017-02-08

We used a combination of Raman microscopy, AFM and TEM to quantify the influence of dimerization on the surface enhanced Raman spectroscopy (SERS) signal for gold and silver nanoparticles (NPs) modified with Raman reporters and situated on gold, silver, and aluminum films and a silicon wafer. The overall increases in the mean SERS enhancement factor (EF) upon dimerization (up by 43% on average) and trimerisation (up by 96% on average) of AuNPs and AgNPs on the studied metal films are within a factor of two, which is moderate when compared to most theoretical models. However, the maximum ratio of EFs for some dimers to the mean EF of monomers can be as high as 5.5 for AgNPs on a gold substrate. In contrast, for dimerization and trimerization of gold and silver NPs on silicon, the mean EF increases by 1-2 orders of magnitude relative to the mean EF of single NPs. Therefore, hot spots in the interparticle gap between gold nanoparticles rather than hot spots between Au nanoparticles and the substrate dominate SERS enhancement for dimers and trimers on a silicon substrate. However, Raman labeled noble metal nanoparticles on plasmonic metal films generate on average SERS enhancement of the same order of magnitude for both types of hot spot zones (e.g. NP/NP and NP/metal film).

Adhesion energy of single wall carbon nanotube loops on various substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Tianjun; Department of Physics, Shaoxing University, 508 Huancheng West Rd., Shaoxing 312000; Ayari, Anthony

2015-04-28

The physics of adhesion of one-dimensional nano structures such as nanotubes, nano wires, and biopolymers on different substrates is of great interest for the study of biological adhesion and the development of nano electronics and nano mechanics. In this paper, we present force spectroscopy experiments of individual single wall carbon nanotube loops using a home-made interferometric atomic force microscope. Characteristic force plateaus during the peeling process allow the quantitative measurement of the adhesion energy per unit length on various substrates: graphite, mica, platinum, gold, and silicon. Moreover, using a time-frequency analysis of the deflection of the cantilever, we estimate themore » dynamic stiffness of the contact, providing more information on the nanotube configurations and its intrinsic mechanical properties.« less

Synthesis of Poly-Silicon Thin Films on Glass Substrate Using Laser Initiated Metal Induced Crystallization of Amorphous Silicon for Space Power Application

NASA Technical Reports Server (NTRS)

Abu-Safe, Husam H.; Naseem, Hameed A.; Brown, William D.

2007-01-01

Poly-silicon thin films on glass substrates are synthesized using laser initiated metal induced crystallization of hydrogenated amorphous silicon films. These films can be used to fabricate solar cells on low cost glass and flexible substrates. The process starts by depositing 200 nm amorphous silicon films on the glass substrates. Following this, 200 nm of sputtered aluminum films were deposited on top of the silicon layers. The samples are irradiated with an argon ion cw laser beam for annealing. Laser power densities ranging from 4 to 9 W/cm2 were used in the annealing process. Each area on the sample is irradiated for a different exposure time. Optical microscopy was used to examine any cracks in the films and loss of adhesion to the substrates. X-Ray diffraction patterns from the initial results indicated the crystallization in the films. Scanning electron microscopy shows dendritic growth. The composition analysis of the crystallized films was conducted using Energy Dispersive x-ray Spectroscopy. The results of poly-silicon films synthesis on space qualified flexible substrates such as Kapton are also presented.

Enhanced Raman scattering in porous silicon grating.

PubMed

Wang, Jiajia; Jia, Zhenhong; Lv, Changwu

2018-03-19

The enhancement of Raman signal on monocrystalline silicon gratings with varying groove depths and on porous silicon grating were studied for a highly sensitive surface enhanced Raman scattering (SERS) response. In the experiment conducted, porous silicon gratings were fabricated. Silver nanoparticles (Ag NPs) were then deposited on the porous silicon grating to enhance the Raman signal of the detective objects. Results show that the enhancement of Raman signal on silicon grating improved when groove depth increased. The enhanced performance of Raman signal on porous silicon grating was also further improved. The Rhodamine SERS response based on Ag NPs/ porous silicon grating substrates was enhanced relative to the SERS response on Ag NPs/ porous silicon substrates. Ag NPs / porous silicon grating SERS substrate system achieved a highly sensitive SERS response due to the coupling of various Raman enhancement factors.

Process for Smoothing an Si Substrate after Etching of SiO2

NASA Technical Reports Server (NTRS)

Turner, Tasha; Wu, Chi

2003-01-01

A reactive-ion etching (RIE) process for smoothing a silicon substrate has been devised. The process is especially useful for smoothing those silicon areas that have been exposed by etching a pattern of holes in a layer of silicon dioxide that covers the substrate. Applications in which one could utilize smooth silicon surfaces like those produced by this process include fabrication of optical waveguides, epitaxial deposition of silicon on selected areas of silicon substrates, and preparation of silicon substrates for deposition of adherent metal layers. During etching away of a layer of SiO2 that covers an Si substrate, a polymer becomes deposited on the substrate, and the substrate surface becomes rough (roughness height approximately equal to 50 nm) as a result of over-etching or of deposition of the polymer. While it is possible to smooth a silicon substrate by wet chemical etching, the undesired consequences of wet chemical etching can include compromising the integrity of the SiO2 sidewalls and undercutting of the adjacent areas of the silicon dioxide that are meant to be left intact. The present RIE process results in anisotropic etching that removes the polymer and reduces height of roughness of the silicon substrate to less than 10 nm while leaving the SiO2 sidewalls intact and vertical. Control over substrate versus sidewall etching (in particular, preferential etching of the substrate) is achieved through selection of process parameters, including gas flow, power, and pressure. Such control is not uniformly and repeatably achievable in wet chemical etching. The recipe for the present RIE process is the following: Etch 1 - A mixture of CF4 and O2 gases flowing at rates of 25 to 75 and 75 to 125 standard cubic centimeters per minute (stdcm3/min), respectively; power between 44 and 55 W; and pressure between 45 and 55 mtorr (between 6.0 and 7.3 Pa). The etch rate lies between approximately equal to 3 and approximately equal to 6 nm/minute. Etch 2 - O2 gas flowing at 75 to 125 stdcm3/min, power between 44 and 55 W, and pressure between 50 and 100 mtorr (between 6.7 and 13.3 Pa).

High-Temperature Annealing as a Method for the Silicon Nanoclusters Growth in Stoichiometric Silicon Dioxide

NASA Astrophysics Data System (ADS)

Ivanova, E. V.; Dementev, P. A.; Sitnikova, A. A.; Aleksandrov, O. V.; Zamoryanskaya, M. V.

2018-07-01

A method for the growth of nanocomposite layers in stoichiometric amorphous silicon dioxide is proposed. It is shown that, after annealing at a temperature of 1150°C in nitrogen atmosphere, a layer containing silicon nanoclusters is formed. Silicon nanoclusters have a crystal structure and a size of 3-6 nm. In a film grown on a n-type substrate, a layer of silicon nanoclusters with a thickness of about 10 nm is observed. In the case of a film grown on a p-type substrate, a nanocomposite layer with a thickness of about 100 nm is observed. The difference in the formation of a nanocomposite layer in films on various substrates is associated with the doping of silicon dioxide with impurities from the substrate during the growth of the film. The formation of the nanocomposite layer was confirmed by transmission electron microscopy, XPS and local cathodoluminescence studies.

Selective etching of silicon carbide films

DOEpatents

Gao, Di; Howe, Roger T.; Maboudian, Roya

2006-12-19

A method of etching silicon carbide using a nonmetallic mask layer. The method includes providing a silicon carbide substrate; forming a non-metallic mask layer by applying a layer of material on the substrate; patterning the mask layer to expose underlying areas of the substrate; and etching the underlying areas of the substrate with a plasma at a first rate, while etching the mask layer at a rate lower than the first rate.

Synthesis and characterization of silicon nanowire arrays for photovoltaic applications

NASA Astrophysics Data System (ADS)

Eichfeld, Sarah M.

The overall objective of this thesis was the development of processes for the fabrication of radial p-n silicon nanowires (SiNWs) using bottom-up nanowire growth techniques on silicon and glass substrates. Vapor-liquid-solid (VLS) growth was carried out on Si(111) substrates using SiCl4 as the silicon precursor. Growth conditions including temperature, PSiCl4, PH2, and position were investigated to determine the optimum growth conditions for epitaxially oriented silicon nanowire arrays. The experiments revealed that the growth rate of the silicon nanowires exhibits a maximum as a function of PSiCl4 and P H2. Gas phase equilibrium calculations were used in conjunction with a mass transport model to explain the experimental data. The modeling results demonstrate a similar maximum in the mass of solid silicon predicted to form as a function of PSiCl4 and PH2, which results from a change in the gas phase concentration of SiHxCly and SiClx species. This results in a shift in the process from growth to etching with increasing PSiCl4. In general, for the atmospheric pressure conditions employed in this study, growth at higher temperatures >1000°C and higher SiCl4 concentrations gave the best results. The growth of silicon nanowire arrays on anodized alumina (AAO)-coated glass substrates was also investigated. Glass will not hold up to the high temperatures required for Si nanowire growth with SiCl4 so SiH 4 was used as the Si precursor instead. Initial studies were carried out to measure the resistivity of p-type and n-type silicon nanowires grown in freestanding AAO membranes. A series of nanowire samples were grown in which the doping and the nanowire length inside the membrane were varied. Circular metal contacts were deposited on the top surface of the membranes and the resistance of the nanowire arrays was measured. The measured resistance versus nanowire length was plotted and the nanowire resistivity was extracted from the slope. The resistivity of the silicon nanowires grown in the AAO membranes was then compared to the resistivity of silicon nanowires grown on Si and measured using single wire four-point measurements. It was determined that the undoped silicon nanowires grown in AAO have a lower resistivity compared to nanowires grown on Si substrates. This indicates the presence of an unintentional acceptor. The resistivity of the silicon nanowires was found to change as the dopant/SiH4 ratio was varied during growth. The growth and doping conditions developed from this study were then used to fabricate p-type SiNW arrays on the AAO coated glass substrates. The final investigation in this thesis focused on the development of a process for radial coating of an n-type Si layer on the p-type Si nanowires. While prior studies demonstrated the fabrication of polycrystalline n-type Si shell layers on Si nanowires, an epitaxial n-type Si shell layer is ultimately of interest to obtain a high quality p-n interface. Initial n-type Si thin film deposition studies were carried out on sapphire substrates using SiH 4 as the silicon precursor to investigate the effect of growth conditions on thickness uniformity, growth rate and doping level. High growth temperatures (>900°C) are generally desired for achieving epitaxial growth; however, gas phase depletion of the SiH4 source along the length of the reactor resulted in poor thickness uniformity. To improve the uniformity, the substrate was shifted closer to the gas inlet at higher temperatures (950°C) and the total flow of gas through the reactor was increased to 200 sccm. A series of n-type doping experiments were also carried out. Hall measurements indicated n-type behavior and four-point measurements yielded a change in resistivity based on the PH3/SiH4 ratio. Pre-coating sample preparation was determined to be important for achieving a high quality Si shell layer. Since Au can diffuse down the sides of the nanowire during sample cooldown after growth, the Au tips were etched away prior to shell layer deposition. The effect of deposition temperature on the structural properties of the shell layer deposited on the VLS grown SiNWs was investigated. TEM revealed that the n-type Si shells were polycrystalline at low temperatures (650°C) but were single crystal at 950°C. SiNW samples grown on glass were also coated; however, due to the temperature constraints, the maximum temperature used was 650°C and therefore the n-type Si shells were polycrystalline. (Abstract shortened by UMI.)

Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

PubMed Central

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

PubMed

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Off-axis silicon carbide substrates

DOEpatents

Edgar, James; Dudley, Michael; Kuball, Martin; Zhang, Yi; Wang, Guan; Chen, Hui; Zhang, Yu

2014-09-02

A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers.

Process for utilizing low-cost graphite substrates for polycrystalline solar cells

NASA Technical Reports Server (NTRS)

Chu, T. L. (Inventor)

1978-01-01

Low cost polycrystalline silicon solar cells supported on substrates were prepared by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical grade polycrystalline silicon, graphite and steel coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures thereof such that p-n junction devices were formed which effectively convert solar energy to electrical energy. To improve the conversion efficiency of the polycrystalline silicon solar cells, the crystallite size in the silicon was substantially increased by melting and solidifying a base layer of polycrystalline silicon before depositing the layers which form the p-n junction.

Method for Growing Low-Defect Single Crystal Heteroepitaxial Films

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor); Neudeck, Philip G. (Inventor)

2002-01-01

A method is disclosed for growing high-quality low-defect crystal films heteroepitaxially on substrates that are different than the crystal films. The growth of the first two heteroepitaxial bilayers is performed on a first two-dimensional nucleate island before a second growth of two-dimensional nucleation is allowed to start. The method is particularly suited for the growth of 3C-SiC, 2H-AlN, or 2H-GaN on 6H-SiC, 4H-SiC, or silicon substrates.

Silicon based substrate with calcium aluminosilicate/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Miller, Robert Alden (Inventor); Jacobson, Nathan S. (Inventor); Smialek, James L. (Inventor); Opila, Elizabeth J. (Inventor); Lee, Kang N. (Inventor); Nagaraj, Bangalore A. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2001-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a calcium alumino silicate.

Silicon based substrate with environmental/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Jacobson, Nathan S. (Inventor); Bansal, Narottam P. (Inventor); Opila, Elizabeth J. (Inventor); Smialek, James L. (Inventor); Lee, Kang N. (Inventor); Spitsberg, Irene T. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2002-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

Silicon based substrate with environmental/ thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Jacobson, Nathan S. (Inventor); Bansal, Nanottam P. (Inventor); Opila, Elizabeth J. (Inventor); Smialek, James L. (Inventor); Lee, Kang N. (Inventor); Spitsberg, Irene T. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2002-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

Real-time monitoring of surface-initiated atom transfer radical polymerization using silicon photonic microring resonators: implications for combinatorial screening of polymer brush growth conditions.

PubMed

Limpoco, F Ted; Bailey, Ryan C

2011-09-28

We directly monitor in parallel and in real time the temporal profiles of polymer brushes simultaneously grown via multiple ATRP reaction conditions on a single substrate using arrays of silicon photonic microring resonators. In addition to probing relative polymerization rates, we show the ability to evaluate the dynamic properties of the in situ grown polymers. This presents a powerful new platform for studying modified interfaces that may allow for the combinatorial optimization of surface-initiated polymerization conditions.

Pulsed energy synthesis and doping of silicon carbide

DOEpatents

Truher, J.B.; Kaschmitter, J.L.; Thompson, J.B.; Sigmon, T.W.

1995-06-20

A method for producing beta silicon carbide thin films by co-depositing thin films of amorphous silicon and carbon onto a substrate is disclosed, whereafter the films are irradiated by exposure to a pulsed energy source (e.g. excimer laser) to cause formation of the beta-SiC compound. Doped beta-SiC may be produced by introducing dopant gases during irradiation. Single layers up to a thickness of 0.5-1 micron have been produced, with thicker layers being produced by multiple processing steps. Since the electron transport properties of beta silicon carbide over a wide temperature range of 27--730 C is better than these properties of alpha silicon carbide, they have wide application, such as in high temperature semiconductors, including HETEROJUNCTION-junction bipolar transistors and power devices, as well as in high bandgap solar arrays, ultra-hard coatings, light emitting diodes, sensors, etc.

Pulsed energy synthesis and doping of silicon carbide

DOEpatents

Truher, Joel B.; Kaschmitter, James L.; Thompson, Jesse B.; Sigmon, Thomas W.

1995-01-01

A method for producing beta silicon carbide thin films by co-depositing thin films of amorphous silicon and carbon onto a substrate, whereafter the films are irradiated by exposure to a pulsed energy source (e.g. excimer laser) to cause formation of the beta-SiC compound. Doped beta-SiC may be produced by introducing dopant gases during irradiation. Single layers up to a thickness of 0.5-1 micron have been produced, with thicker layers being produced by multiple processing steps. Since the electron transport properties of beta silicon carbide over a wide temperature range of 27.degree.-730.degree. C. is better than these properties of alpha silicon carbide, they have wide application, such as in high temperature semiconductors, including hetero-junction bipolar transistors and power devices, as well as in high bandgap solar arrays, ultra-hard coatings, light emitting diodes, sensors, etc.

Silicon based substrate with calcium aluminosilicate environmental/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Miller, Robert Alden (Inventor); Jacobson, Nathan S. (Inventor); Smialek, James L. (Inventor); Opila, Elizabeth J. (Inventor); Lee, Kang N. (Inventor); Nagaraj, Bangalore A. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2001-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a calcium alumino silicate.

Chemical resistivity of self-assembled monolayer covalently attached to silicon substrate to hydrofluoric acid and ammonium fluoride

NASA Astrophysics Data System (ADS)

Saito, N.; Youda, S.; Hayashi, K.; Sugimura, H.; Takai, O.

2003-06-01

Self-assembled monolayers (SAMs) were prepared on hydrogen-terminated silicon substrates through chemical vapor deposition using 1-hexadecene (HD) as a precursor. The HD-SAMs prepared in an atmosphere under a reduced pressure (≈50 Pa) showed better chemical resistivities to hydrofluoric acid and ammonium fluoride (NH 4F) solutions than that of an organosilane SAM formed on oxide-covered silicon substrates. The surface covered with the HD-SAM was micro-patterned by vacuum ultraviolet photolithography and consequently divided into two areas terminated with HD-SAM or silicon dioxide. This micro-patterned sample was immersed in a 40 vol.% NH 4F aqueous solution. Surface images obtained by an optical microscopy clearly show that the micro-patterns of HD-SAM/silicon dioxide were successfully transferred into the silicon substrate.

Polymer taper bridge for silicon waveguide to single mode waveguide coupling

NASA Astrophysics Data System (ADS)

Kruse, Kevin; Middlebrook, Christopher T.

2016-03-01

Coupling of optical power from high-density silicon waveguides to silica optical fibers for signal routing can incur high losses and often requires complex end-face preparation/processing. Novel coupling device taper structures are proposed for low coupling loss between silicon photonic waveguides and single mode fibers are proposed and devices are fabricated and measured in terms of performance. Theoretical mode conversion models for waveguide tapers are derived for optimal device structure design and performance. Commercially viable vertical and multi-layer taper designs using polymer waveguide materials are proposed as innovative, cost-efficient, and mass-manufacturable optical coupling devices. The coupling efficiency for both designs is determined to evaluate optimal device dimensions and alignment tolerances with both silicon rib waveguides and silicon nanowire waveguides. Propagation loss as a function of waveguide roughness and metallic loss are determined and correlated to waveguide dimensions to obtain total insertion loss for the proposed taper designs. Multi-layer tapers on gold-sputtered substrates are fabricated through photolithography as proof-of-concept devices and evaluated for device loss optimization. Tapered waveguide coupling loss with Si WGs (2.74 dB) was experimentally measured with high correlation to theoretical results.

Surface thiolation of silicon for antifouling application.

PubMed

Zhang, Xiaoning; Gao, Pei; Hollimon, Valerie; Brodus, DaShan; Johnson, Arion; Hu, Hongmei

2018-02-07

Thiol groups grafted silicon surface was prepared as previously described. 1H,1H,2H,2H-perfluorodecanethiol (PFDT) molecules were then immobilized on such a surface through disulfide bonds formation. To investigate the contribution of PFDT coating to antifouling, the adhesion behaviors of Botryococcus braunii (B. braunii) and Escherichia coli (E. coli) were studied through biofouling assays in the laboratory. The representative microscope images suggest reduced B. braunii and E. coli accumulation densities on PFDT integrated silicon substrate. However, the antifouling performance of PFDT integrated silicon substrate decreased over time. By incubating the aged substrate in 10 mM TCEP·HCl solution for 1 h, the fouled PFDT coating could be removed as the disulfide bonds were cleaved, resulting in reduced absorption of algal cells and exposure of non-fouled silicon substrate surface. Our results indicate that the thiol-terminated substrate can be potentially useful for restoring the fouled surface, as well as maximizing the effective usage of the substrate.

Optimization and characterization of biomolecule immobilization on silicon substrates using (3-aminopropyl)triethoxysilane (APTES) and glutaraldehyde linker

NASA Astrophysics Data System (ADS)

Gunda, Naga Siva Kumar; Singh, Minashree; Norman, Lana; Kaur, Kamaljit; Mitra, Sushanta K.

2014-06-01

In the present work, we developed and optimized a technique to produce a thin, stable silane layer on silicon substrate in a controlled environment using (3-aminopropyl)triethoxysilane (APTES). The effect of APTES concentration and silanization time on the formation of silane layer is studied using spectroscopic ellipsometry and Fourier transform infrared spectroscopy (FTIR). Biomolecules of interest are immobilized on optimized silane layer formed silicon substrates using glutaraldehyde linker. Surface analytical techniques such as ellipsometry, FTIR, contact angle measurement system, and atomic force microscopy are employed to characterize the bio-chemically modified silicon surfaces at each step of the biomolecule immobilization process. It is observed that a uniform, homogenous and highly dense layer of biomolecules are immobilized with optimized silane layer on the silicon substrate. The developed immobilization method is successfully implemented on different silicon substrates (flat and pillar). Also, different types of biomolecules such as anti-human IgG (rabbit monoclonal to human IgG), Listeria monocytogenes, myoglobin and dengue capture antibodies were successfully immobilized. Further, standard sandwich immunoassay (antibody-antigen-antibody) is employed on respective capture antibody coated silicon substrates. Fluorescence microscopy is used to detect the respective FITC tagged detection antibodies bound to the surface after immunoassay.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Ceramic with zircon coating

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor)

2003-01-01

An article comprises a silicon-containing substrate and a zircon coating. The article can comprise a silicon carbide/silicon (SiC/Si) substrate, a zircon (ZrSiO.sub.4) intermediate coating and an external environmental/thermal barrier coating.

Superhydrophobic SERS substrates based on silicon hierarchical nanostructures

NASA Astrophysics Data System (ADS)

Chen, Xuexian; Wen, Jinxiu; Zhou, Jianhua; Zheng, Zebo; An, Di; Wang, Hao; Xie, Weiguang; Zhan, Runze; Xu, Ningsheng; Chen, Jun; She, Juncong; Chen, Huanjun; Deng, Shaozhi

2018-02-01

Silicon nanostructures have been cultivated as promising surface enhanced Raman scattering (SERS) substrates in terms of their low-loss optical resonance modes, facile functionalization, and compatibility with today’s state-of-the-art CMOS techniques. However, unlike their plasmonic counterparts, the electromagnetic field enhancements induced by silicon nanostructures are relatively small, which restrict their SERS sensing limit to around 10-7 M. To tackle this problem, we propose here a strategy for improving the SERS performance of silicon nanostructures by constructing silicon hierarchical nanostructures with a superhydrophobic surface. The hierarchical nanostructures are binary structures consisted of silicon nanowires (NWs) grown on micropyramids (MPs). After being modified with perfluorooctyltriethoxysilane (PFOT), the nanostructure surface shows a stable superhydrophobicity with a high contact angle of ˜160°. The substrate can allow for concentrating diluted analyte solutions into a specific area during the evaporation of the liquid droplet, whereby the analytes are aggregated into a small volume and can be easily detected by the silicon nanostructure SERS substrate. The analyte molecules (methylene blue: MB) enriched from an aqueous solution lower than 10-8 M can be readily detected. Such a detection limit is ˜100-fold lower than the conventional SERS substrates made of silicon nanostructures. Additionally, the detection limit can be further improved by functionalizing gold nanoparticles onto silicon hierarchical nanostructures, whereby the superhydrophobic characteristics and plasmonic field enhancements can be combined synergistically to give a detection limit down to ˜10-11 M. A gold nanoparticle-functionalized superhydrophobic substrate was employed to detect the spiked melamine in liquid milk. The results showed that the detection limit can be as low as 10-5 M, highlighting the potential of the proposed superhydrophobic SERS substrate in practical food safety inspection applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

DTIC Science & Technology

2011-11-01

stack between the GaN and Substrate layers. The University of Bristol recently reported that this TBR in commercial devices on Silicon Carbide ( SiC ...Circuit RF Radio Frequency PA Power Amplifier SiC Silicon Carbide FEA Finite Element Analysis heff Effective Heat transfer Coefficient (W/m 2 K...substrate material switched from sapphire to silicon , and by another factor of two from silicon to SiC . TABLE 1: SAMPLE RESULTS FROM DOUGLAS ET AL. FOR

Optimization of single keV ion implantation for the construction of single P-donor devices

NASA Astrophysics Data System (ADS)

Yang, Changyi; Jamieson, David N.; Hopf, Toby; Andresen, Soren E.; Hearne, Sean M.; Hudson, Fay E.; Pakes, Christopher I.; Mitic, Mladen; Gauja, Eric; Tamanyan, Grigori; Dzurak, Andrew S.; Prawer, Steven; Clark, Robert G.

2005-02-01

We report recent progress in single keV ion implantation and online detection for the controlled implantation of single donors in silicon. When integrated with silicon nanofabrication technology this forms the "top down" strategy for the construction of prototype solid state quantum computer devices based on phosphorus donors in silicon. We have developed a method of single ion implantation and online registration that employs detector electrodes adjacent to the area into which the donors are to be implanted. The implantation sites are positioned with nanometer accuracy using an electron beam lithography patterned PMMA mask. Control of the implantation depth of 20 nm is achieved by tuning the phosphorus ion energy to 14 keV. The counting of single ion implantation in each site is achieved by the detection of e-/h+ pairs produced by the implanted phosphorus ion in the substrate. The system is calibrated by use of Mn K-line x-rays (5.9 and 6.4 keV) and we find the ionization energy of the 14 keV phosphorus ions in silicon to be about 3.5-4.0 keV for implants through a 5 nm SiO2 surface layer. This paper describes the development of an improved PIN detector structure that provides more reliable performance of the earlier MOS structure. With the new structure, the energy noise threshold has been minimized to 1 keV or less. Unambiguous detection/counting of single keV ion implantation events were achieved with a confidence level greater than 98% with a reliable and reproducible fabrication process.

Compensated amorphous silicon solar cell

DOEpatents

Devaud, Genevieve

1983-01-01

An amorphous silicon solar cell including an electrically conductive substrate, a layer of glow discharge deposited hydrogenated amorphous silicon over said substrate and having regions of differing conductivity with at least one region of intrinsic hydrogenated amorphous silicon. The layer of hydrogenated amorphous silicon has opposed first and second major surfaces where the first major surface contacts the electrically conductive substrate and an electrode for electrically contacting the second major surface. The intrinsic hydrogenated amorphous silicon region is deposited in a glow discharge with an atmosphere which includes not less than about 0.02 atom percent mono-atomic boron. An improved N.I.P. solar cell is disclosed using a BF.sub.3 doped intrinsic layer.

Energy Levels of Defects Created in Silicon Supersaturated with Transition Metals

NASA Astrophysics Data System (ADS)

García, H.; Castán, H.; Dueñas, S.; García-Hemme, E.; García-Hernansaz, R.; Montero, D.; González-Díaz, G.

2018-03-01

Intermediate-band semiconductors have attracted much attention for use in silicon-based solar cells and infrared detectors. In this work, n-Si substrates have been implanted with very high doses (1013 cm-2 and 1014 cm-2) of vanadium, which gives rise to a supersaturated layer inside the semiconductor. However, the Mott limit was not exceeded. The energy levels created in the supersaturated silicon were studied in detail by means of thermal admittance spectroscopy. We found a single deep center at energy near E C - 200 meV. This value agrees with one of the levels found for vanadium in silicon. The capture cross-section values of the deep levels were also calculated, and we found a relationship between the capture cross-section and the energy position of the deep levels which follows the Meyer-Neldel rule. This process usually appears in processes involving multiple excitations. The Meyer-Neldel energy values agree with those previously obtained for silicon supersaturated with titanium and for silicon contaminated with iron.

RF Sputtering for preparing substantially pure amorphous silicon monohydride

DOEpatents

Jeffrey, Frank R.; Shanks, Howard R.

1982-10-12

A process for controlling the dihydride and monohydride bond densities in hydrogenated amorphous silicon produced by reactive rf sputtering of an amorphous silicon target. There is provided a chamber with an amorphous silicon target and a substrate therein with the substrate and the target positioned such that when rf power is applied to the target the substrate is in contact with the sputtering plasma produced thereby. Hydrogen and argon are fed to the chamber and the pressure is reduced in the chamber to a value sufficient to maintain a sputtering plasma therein, and then rf power is applied to the silicon target to provide a power density in the range of from about 7 watts per square inch to about 22 watts per square inch to sputter an amorphous silicon hydride onto the substrate, the dihydride bond density decreasing with an increase in the rf power density. Substantially pure monohydride films may be produced.

Fully Tunable Silicon Nanowire Arrays Fabricated by Soft Nanoparticle Templating.

PubMed

Rey, By Marcel; Elnathan, Roey; Ditcovski, Ran; Geisel, Karen; Zanini, Michele; Fernandez-Rodriguez, Miguel-Angel; Naik, Vikrant V; Frutiger, Andreas; Richtering, Walter; Ellenbogen, Tal; Voelcker, Nicolas H; Isa, Lucio

2016-01-13

We demonstrate a fabrication breakthrough to produce large-area arrays of vertically aligned silicon nanowires (VA-SiNWs) with full tunability of the geometry of the single nanowires and of the whole array, paving the way toward advanced programmable designs of nanowire platforms. At the core of our fabrication route, termed "Soft Nanoparticle Templating", is the conversion of gradually compressed self-assembled monolayers of soft nanoparticles (microgels) at a water-oil interface into customized lithographical masks to create VA-SiNW arrays by means of metal-assisted chemical etching (MACE). This combination of bottom-up and top-down techniques affords excellent control of nanowire etching site locations, enabling independent control of nanowire spacing, diameter and height in a single fabrication route. We demonstrate the fabrication of centimeter-scale two-dimensional gradient photonic crystals exhibiting continuously varying structural colors across the entire visible spectrum on a single silicon substrate, and the formation of tunable optical cavities supported by the VA-SiNWs, as unambiguously demonstrated through numerical simulations. Finally, Soft Nanoparticle Templating is combined with optical lithography to create hierarchical and programmable VA-SiNW patterns.

Molecular-dynamics simulations of energetic C{sub 60} impacts on (2x1)-(100) silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Xiaoyuan; Albe, Karsten; Averback, Robert S.

2000-07-01

Single impacts of energetic C{sub 60} clusters on (2x1)-(100) silicon substrates are studied by molecular-dynamics simulations. The role of impact energies and internal cluster energy are investigated in detail. Six different energy regimes can be identified at the end of the ballistic phase: At thermal energies below 20 eV the fullerene cages undergo elastic deformation, while impinging on the surface, and are mostly chemisorpted on top of the (2x1)-dimer rows. Between 20 and 100 eV the cage structure is preserved after the collision, but the cluster comes to rest within a few monolayers of the silicon surface. At energies ofmore » 100-500 eV the cluster partially decomposes and small coherent carbon caps are embedded in the surface. At higher energies up to 1.5 keV complete decomposition of the fullerene cluster occurs and an amorphous zone is formed in the subsurface area. At energies greater than approximately 1.5 keV craters form and above 6 keV sputtering becomes significant. In all cases the substrate temperature is of minor influence on the final result, but the projectile temperature is important for impacts at lower energies (<1.5 keV). For high energy impacts the ballistics resemble that of single atom impacts. Nearly 1:1 stoichiometry is obtained for impact energies around 1 keV. These results reveal an interesting possibility for controlled implantation of C in Si at high local concentrations, which might allow the formation of silicon carbide. (c) 2000 American Institute of Physics.« less

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Low temperature deposition of polycrystalline silicon thin films on a flexible polymer substrate by hot wire chemical vapor deposition

NASA Astrophysics Data System (ADS)

Lee, Sang-hoon; Jung, Jae-soo; Lee, Sung-soo; Lee, Sung-bo; Hwang, Nong-moon

2016-11-01

For the applications such as flexible displays and solar cells, the direct deposition of crystalline silicon films on a flexible polymer substrate has been a great issue. Here, we investigated the direct deposition of polycrystalline silicon films on a polyimide film at the substrate temperature of 200 °C. The low temperature deposition of crystalline silicon on a flexible substrate has been successfully made based on two ideas. One is that the Si-Cl-H system has a retrograde solubility of silicon in the gas phase near the substrate temperature. The other is the new concept of non-classical crystallization, where films grow by the building block of nanoparticles formed in the gas phase during hot-wire chemical vapor deposition (HWCVD). The total amount of precipitation of silicon nanoparticles decreased with increasing HCl concentration. By adding HCl, the amount and the size of silicon nanoparticles were reduced remarkably, which is related with the low temperature deposition of silicon films of highly crystalline fraction with a very thin amorphous incubation layer. The dark conductivity of the intrinsic film prepared at the flow rate ratio of RHCl=[HCl]/[SiH4]=3.61 was 1.84×10-6 Scm-1 at room temperature. The Hall mobility of the n-type silicon film prepared at RHCl=3.61 was 5.72 cm2 V-1s-1. These electrical properties of silicon films are high enough and could be used in flexible electric devices.

Visible-blind ultraviolet photodetectors on porous silicon carbide substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naderi, N.; Hashim, M.R., E-mail: roslan@usm.my

2013-06-01

Highlights: • Highly reliable UV detectors are fabricated on porous silicon carbide substrates. • The optical properties of samples are enhanced by increasing the current density. • The optimized sample exhibits enhanced sensitivity to the incident UV radiation. - Abstract: Highly reliable visible-blind ultraviolet (UV) photodetectors were successfully fabricated on porous silicon carbide (PSC) substrates. High responsivity and high photoconductive gain were observed in a metal–semiconductor–metal ultraviolet photodetector that was fabricated on an optimized PSC substrate. The PSC samples were prepared via the UV-assisted photo-electrochemical etching of an n-type hexagonal silicon carbide (6H-SiC) substrate using different etching current densities. Themore » optical results showed that the current density is an outstanding etching parameter that controls the porosity and uniformity of PSC substrates. A highly porous substrate was synthesized using a suitable etching current density to enhance its light absorption, thereby improving the sensitivity of UV detector with this substrate. The electrical characteristics of fabricated devices on optimized PSC substrates exhibited enhanced sensitivity and responsivity to the incident radiation.« less

Laboratory studies of silicon vapor deposition, phase A. [feasibility of producing thin films for photovoltaic applications

NASA Technical Reports Server (NTRS)

Frost, R. T.; Racette, G. W.; Stockhoff, E. H.

1977-01-01

A system is described capable of carrying out silicon vapor deposition experiments in the low 10 to the minus 10th power torr vacuum range. The system was assembled and tested for use in a program aimed at exploration of vacuum heteroepitaxy of silicon on several substrates of potential interest for photovoltaic applications. An experiment is described in which a silicon layer 2.5 microns thick was deposited on a pyrolytically cleaned tungsten substrate held at a temperature of 400 C. Using a resistance heated silicon source, thicker layers can be deposited in periods of hours by utilizing closer source to substrate distances.

Highly stable, protein resistant thin films on SiC-modified silicon substrates.

PubMed

Qin, Guoting; Zhang, Rui; Makarenko, Boris; Kumar, Amit; Rabalais, Wayne; López Romero, J Manuel; Rico, Rodrigo; Cai, Chengzhi

2010-05-21

Thin films terminated with oligo(ethylene glycol) (OEG) could be photochemically grafted onto ultrathin silicon carbide layers that were generated on silicon substrates via carbonization with acetylene at 820 degrees C. The OEG coating reduced the non-specific adsorption of fibrinogen on the substrates by 99.5% and remained resistant after storage in PBS for 4 weeks at 37 degrees C.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Spalling of a Thin Si Layer by Electrodeposit-Assisted Stripping

NASA Astrophysics Data System (ADS)

Kwon, Youngim; Yang, Changyol; Yoon, Sang-Hwa; Um, Han-Don; Lee, Jung-Ho; Yoo, Bongyoung

2013-11-01

A major goal in solar cell research is to reduce the cost of the final module. Reducing the thickness of the crystalline silicon substrate to several tens of micrometers can reduce material costs. In this work, we describe the electrodeposition of a Ni-P alloy, which induces high stress in the silicon substrate at room temperature. The induced stress enables lift-off of the thin-film silicon substrate. After lift-off of the thin Si film, the mother substrate can be reused, reducing material costs. Moreover, the low-temperature process expected to be improved Si substrate quality.

Forming high efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2014-09-09

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Forming high-efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2015-07-07

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process

DOEpatents

McKee, Rodney A.; Walker, Frederick J.

1993-01-01

A process and structure involving a silicon substrate utilizes an ultra high vacuum and molecular beam epitaxy (MBE) methods to grow an epitaxial oxide film upon a surface of the substrate. As the film is grown, the lattice of the compound formed at the silicon interface becomes stabilized, and a base layer comprised of an oxide having a sodium chloride-type lattice structure grows epitaxially upon the compound so as to cover the substrate surface. A perovskite may then be grown epitaxially upon the base layer to render a product which incorporates silicon, with its electronic capabilities, with a perovskite having technologically-significant properties of its own.

MEMS fabrication and frequency sweep for suspending beam and plate electrode in electrostatic capacitor

NASA Astrophysics Data System (ADS)

Zhu, Jianxiong; Song, Weixing

2018-01-01

We report a MEMS fabrication and frequency sweep for a high-order mode suspending beam and plate layer in electrostatic micro-gap semiconductor capacitor. This suspended beam and plate was designed with silicon oxide (SiO2) film which was fabricated using bulk silicon micromachining technology on both side of a silicon substrate. The designed semiconductor capacitors were driven by a bias direct current (DC) and a sweep frequency alternative current (AC) in a room temperature for an electrical response test. Finite element calculating software was used to evaluate the deformation mode around its high-order response frequency. Compared a single capacitor with a high-order response frequency (0.42 MHz) and a 1 × 2 array parallel capacitor, we found that the 1 × 2 array parallel capacitor had a broader high-order response range. And it concluded that a DC bias voltage can be used to modulate a high-order response frequency for both a single and 1 × 2 array parallel capacitors.

Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1993-01-01

The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

Strong Surface Diffusion Mediated Glancing-Angle Deposition: Growth, Recrystallization and Reorientation of Tin Nanorods

NASA Astrophysics Data System (ADS)

Wang, Huan-Hua; Shi, Yi-Jian; William, Chu; Yigal, Blum

2008-01-01

Different from usual glancing-angle deposition where low surface diffusion is necessary to form nanorods, strong surface diffusion mediated glancing-angle deposition is exemplified by growing tin nanorod films on both silicon and glass substrates simultaneously via thermal evaporation. During growth, the nanorods were simultaneously baked by the high-temperature evaporator, and therefore re-crystallized into single crystals in consequence of strong surface diffusion. The monocrystalline tin nanorods have a preferred orientation perpendicular to the substrate surface, which is quite different from the usual uniformly oblique nanorods without recrystallization.

Fabrication of polycrystalline solar cells on low-cost substrates

NASA Technical Reports Server (NTRS)

Chu, T. L. (Inventor)

1976-01-01

A new method of producing p-n junction semiconductors for solar cells was described; the principal objective of this investigation is to reduce production costs significantly by depositing polycrystalline silicon on a relatively cheap substrate such as metallurgical-grade silicon, graphite, or steel. The silicon layer contains appropriate dopants, and the substrates are coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures of these compounds.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

2002-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Increased voltage photovoltaic cell

NASA Technical Reports Server (NTRS)

Ross, B.; Bickler, D. B.; Gallagher, B. D. (Inventor)

1985-01-01

A photovoltaic cell, such as a solar cell, is provided which has a higher output voltage than prior cells. The improved cell includes a substrate of doped silicon, a first layer of silicon disposed on the substrate and having opposite doping, and a second layer of silicon carbide disposed on the first layer. The silicon carbide preferably has the same type of doping as the first layer.

Molybdenum enhanced low-temperature deposition of crystalline silicon nitride

DOEpatents

Lowden, Richard A.

1994-01-01

A process for chemical vapor deposition of crystalline silicon nitride which comprises the steps of: introducing a mixture of a silicon source, a molybdenum source, a nitrogen source, and a hydrogen source into a vessel containing a suitable substrate; and thermally decomposing the mixture to deposit onto the substrate a coating comprising crystalline silicon nitride containing a dispersion of molybdenum silicide.

Theoretical Studies about Adsorption on Silicon Surface

NASA Astrophysics Data System (ADS)

Huang, Yan; Chen, Xiaoshuang; Zhu, Xiao Yan; Duan, He; Zhou, Xiao Hao; Lu, Wei

In this review paper, we address the important research topic of adsorption on the silicon surface. The deposition of single Si ad-species (adatom and ad-dimer) on the p(2×2) reconstructed Si(100) surface has been simulated by the empirical tight-binding method. Using the clean and defective Si surfaces as the deposition substrates, the deposition energies are mapped out around the clean surface, dimer vacancies, steps and kink structures. The binding sites, saddle points and several possible diffusion paths are obtained from the calculated energy. With further analysis of the deposition and diffusion behaviors, the influences of the surface defects can be found. Then, by adopting the first-principle calculations, the adsorptions of the II-VI group elements on the clean and As-passivated Si(211) substrates have been calculated as the example of adsorption on the high-miller-index Si surface.

Role of near-field enhancement in plasmonic laser nanoablation using gold nanorods on a silicon substrate.

PubMed

Harrison, R K; Ben-Yakar, Adela

2010-10-11

We present experimental results for the plasmonic laser ablation of silicon with nanoscale features as small as 22 x 66 nm using single near-infrared, femtosecond laser pulses incident on gold nanorods. Near the ablation threshold, these features are photo-imprints of gold nanorod particles positioned on the surface of the silicon and have feature sizes similar to the nanorods. The single rod-shaped ablation pattern matches the enhancement patterns of the Poynting vector magnitude on the surface of silicon, implying that the ablation is a result of the plasmonic enhancement of the incident electromagnetic waves in the near-field of the particles. Interestingly, the ablation pattern is different from the two separated holes at the ends of the nanorod, as would be expected from the electric field--|E|(2) enhancement pattern. We measured the plasmonic ablation threshold fluence to be almost two orders of magnitude less than the femtosecond laser ablation threshold of silica, present in the thin native oxide layer on the surface of silicon. This value also agrees with the enhancement of the Poynting vector of a nanorod on silicon as calculated with electromagnetic simulations. We thus conclude that plasmonic ablation with plasmonic nanoparticles depends directly on the polarization and the value of the near-field enhancement of the Poynting vector and not the square of the electric field as previously suggested.

Formation of intra-island grain boundaries in pentacene monolayers.

PubMed

Zhang, Jian; Wu, Yu; Duhm, Steffen; Rabe, Jürgen P; Rudolf, Petra; Koch, Norbert

2011-12-21

To assess the formation of intra-island grain boundaries during the early stages of pentacene film growth, we studied sub-monolayers of pentacene on pristine silicon oxide and silicon oxide with high pinning centre density (induced by UV/O(3) treatment). We investigated the influence of the kinetic energy of the impinging molecules on the sub-monolayer growth by comparing organic molecular beam deposition (OMBD) and supersonic molecular beam deposition (SuMBD). For pentacene films fabricated by OMBD, higher pentacene island-density and higher polycrystalline island density were observed on UV/O(3)-treated silicon oxide as compared to pristine silicon oxide. Pentacene films deposited by SuMBD exhibited about one order of magnitude lower island- and polycrystalline island densities compared to OMBD, on both types of substrates. Our results suggest that polycrystalline growth of single islands on amorphous silicon oxide is facilitated by structural/chemical surface pinning centres, which act as nucleation centres for multiple grain formation in a single island. Furthermore, the overall lower intra-island grain boundary density in pentacene films fabricated by SuMBD reduces the number of charge carrier trapping sites specific to grain boundaries and should thus help achieving higher charge carrier mobilities, which are advantageous for their use in organic thin-film transistors.

Enhanced Telecom Emission from Single Group-IV Quantum Dots by Precise CMOS-Compatible Positioning in Photonic Crystal Cavities.

PubMed

Schatzl, Magdalena; Hackl, Florian; Glaser, Martin; Rauter, Patrick; Brehm, Moritz; Spindlberger, Lukas; Simbula, Angelica; Galli, Matteo; Fromherz, Thomas; Schäffler, Friedrich

2017-03-15

Efficient coupling to integrated high-quality-factor cavities is crucial for the employment of germanium quantum dot (QD) emitters in future monolithic silicon-based optoelectronic platforms. We report on strongly enhanced emission from single Ge QDs into L3 photonic crystal resonator (PCR) modes based on precise positioning of these dots at the maximum of the respective mode field energy density. Perfect site control of Ge QDs grown on prepatterned silicon-on-insulator substrates was exploited to fabricate in one processing run almost 300 PCRs containing single QDs in systematically varying positions within the cavities. Extensive photoluminescence studies on this cavity chip enable a direct evaluation of the position-dependent coupling efficiency between single dots and selected cavity modes. The experimental results demonstrate the great potential of the approach allowing CMOS-compatible parallel fabrication of arrays of spatially matched dot/cavity systems for group-IV-based data transfer or quantum optical systems in the telecom regime.

Enhanced Telecom Emission from Single Group-IV Quantum Dots by Precise CMOS-Compatible Positioning in Photonic Crystal Cavities

PubMed Central

2017-01-01

Efficient coupling to integrated high-quality-factor cavities is crucial for the employment of germanium quantum dot (QD) emitters in future monolithic silicon-based optoelectronic platforms. We report on strongly enhanced emission from single Ge QDs into L3 photonic crystal resonator (PCR) modes based on precise positioning of these dots at the maximum of the respective mode field energy density. Perfect site control of Ge QDs grown on prepatterned silicon-on-insulator substrates was exploited to fabricate in one processing run almost 300 PCRs containing single QDs in systematically varying positions within the cavities. Extensive photoluminescence studies on this cavity chip enable a direct evaluation of the position-dependent coupling efficiency between single dots and selected cavity modes. The experimental results demonstrate the great potential of the approach allowing CMOS-compatible parallel fabrication of arrays of spatially matched dot/cavity systems for group-IV-based data transfer or quantum optical systems in the telecom regime. PMID:28345012

Controlled doping by self-assembled dendrimer-like macromolecules

NASA Astrophysics Data System (ADS)

Wu, Haigang; Guan, Bin; Sun, Yingri; Zhu, Yiping; Dan, Yaping

2017-02-01

Doping via self-assembled macromolecules might offer a solution for developing single atom electronics by precisely placing individual dopants at arbitrary location to meet the requirement for circuit design. Here we synthesize dendrimer-like polyglycerol macromolecules with each carrying one phosphorus atom in the core. The macromolecules are immobilized by the coupling reagent onto silicon surfaces that are pre-modified with a monolayer of undecylenic acid. Nuclear magnetic resonance (NMR) and X-ray photoelectron spectroscopy (XPS) are employed to characterize the synthesized macromolecules and the modified silicon surfaces, respectively. After rapid thermal annealing, the phosphorus atoms carried by the macromolecules diffuse into the silicon substrate, forming dopants at a concentration of 1017 cm-3. Low-temperature Hall effect measurements reveal that the ionization process is rather complicated. Unlike the widely reported simple ionization of phosphorus dopants, nitrogen and carbon are also involved in the electronic activities in the monolayer doped silicon.

Dislocation-free strained silicon-on-silicon by in-place bonding

NASA Astrophysics Data System (ADS)

Cohen, G. M.; Mooney, P. M.; Paruchuri, V. K.; Hovel, H. J.

2005-06-01

In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as "bonded in-place". We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained.

Method of deposition of silicon carbide layers on substrates

DOEpatents

Angelini, P.; DeVore, C.E.; Lackey, W.J.; Blanco, R.E.; Stinton, D.P.

1982-03-19

A method for direct chemical vapor deposition of silicon carbide to substrates, especially nuclear waste particles, is provided by the thermal decomposition of methylsilane at 800 to 1050/sup 0/C when the substrates have been confined within a suitable coating environment.

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

DOE PAGES

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio; ...

2017-11-14

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 10 4 cm -2), localized areas with a defect density > 10 5 cm -2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stackingmore » faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. In conclusion, the impact of the defects on material performance and substrate re-use is also discussed.« less

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 10 4 cm -2), localized areas with a defect density > 10 5 cm -2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stackingmore » faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. In conclusion, the impact of the defects on material performance and substrate re-use is also discussed.« less

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

NASA Astrophysics Data System (ADS)

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio; Jensen, Mallory Ann; Morishige, Ashley E.; Lai, Barry; Hao, Ruiying; Ravi, T. S.; Buonassisi, Tonio

2018-02-01

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 104 cm-2), localized areas with a defect density > 105 cm-2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stacking faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. The impact of the defects on material performance and substrate re-use is also discussed.

Evaluation of glass resin coatings for solar cell applications

NASA Technical Reports Server (NTRS)

Field, M. B.

1978-01-01

Using a variety of non-vacuum deposition techniques coatings were implemented on silicon solar cells and arrays of cells interconnected on Kapton substrates. The coatings provide both antireflection optical matching and environmental protection. Reflectance minima near 2% was achieved at a single wavelength in the visible. Reflectance averaging below 5% across the useful collection range was demonstrated. The coatings and methods of deposition were: (1) Ta2O5 spun, dipped or sprayed; (2) Ta2O5.SiO2 spun, dipped or sprayed; (3) GR908 (SiO2) spun, dipped, or sprayed. Total coating thickness were in the range of 18 microns to 25 microns. The coatings and processes are compatible with single cells or cells mounted on Kapton substrates.

Molybdenum enhanced low-temperature deposition of crystalline silicon nitride

DOEpatents

Lowden, R.A.

1994-04-05

A process for chemical vapor deposition of crystalline silicon nitride is described which comprises the steps of: introducing a mixture of a silicon source, a molybdenum source, a nitrogen source, and a hydrogen source into a vessel containing a suitable substrate; and thermally decomposing the mixture to deposit onto the substrate a coating comprising crystalline silicon nitride containing a dispersion of molybdenum silicide. 5 figures.

Electron Beam "Writes" Silicon On Sapphire

NASA Technical Reports Server (NTRS)

Heinemann, Klaus

1988-01-01

Method of growing silicon on sapphire substrate uses beam of electrons to aid growth of semiconductor material. Silicon forms as epitaxial film in precisely localized areas in micron-wide lines. Promising fabrication method for fast, densely-packed integrated circuits. Silicon deposited preferentially in contaminated substrate zones and in clean zone irradiated by electron beam. Electron beam, like surface contamination, appears to stimulate decomposition of silane atmosphere.

Single and multijunction silicon based thin film solar cells on a flexible substrate with absorber layers made by hot-wire CVD

NASA Astrophysics Data System (ADS)

Li, Hongbo

2007-09-01

With the worldwide growing concern about reliable energy supply and the environmental problems of fossil and nuclear energy production, the need for clean and sustainable energy sources is evident. Solar energy conversion, such as in photovoltaic systems, can play a major role in the urgently needed energy transition in electricity production. Solar cells based on thin film silicon and its alloys are a promising candidate that is capable of fulfilling the fast increasing demand of a reliable solar cell supply. The conventional method to deposit silicon thin films is based on plasma enhanced chemical vapour deposition (PECVD) techniques, which have the disadvantage of increasing film inhomogeneity at a high deposition rate when scaling up for the industrial production. In this thesis, we study the possibility of making high efficiency single and multijunction thin film silicon solar cells with the so-called hot-wire CVD technique, in which no strong electromagnetic field is involved in the deposition. Therefore, the up-scaling for industrial production is straightforward. We report and discuss our findings on the correlation of substrate surface rms roughness and the main output parameter of a solar cell, the open circuit voltage Voc of c-Si:H n i p cells. By considering all the possible reasons that could influence the Voc of such cells, we conclude that the near linear correlation of Voc and substrate surface rms roughness is the result the two most probable reasons: the unintentional doping through the cracks originated near the valleys of the substrate surface due to the in-diffusion of impurities, and the high density electrical defects formed by the collision of columnar silicon structures. Both of them relate to the morphology of substrate surface. Therefore, to have the best cell performance on a rough substrate surface, a good control on the substrate surface morphology is necessary. Another issue influencing the performance of c-Si:H solar cells is the change in layer crystallinity during the growth of the c-Si:H i-layer. For PECVD deposited cells, it is often found that the layer crystallinity is enhanced with increasing film thickness. We found for Hot-wire deposited cells, however, the opposite development in material structure: the material becomes amorphous near the end of the deposition. This results in a deterioration of cell performance. We therefore introduce a so-called H2 reverse profiling technique, in which H2 is increased during the c-Si:H i-layer deposition. With this technique, a cell with an efficiency of 8.5% has been reached, which is in line with the best reported PECVD cells deposited on the same type of substrate. In the literature, carrier transport in c-Si:H cells has been a topic for debate. In this thesis, we present our finding of photogating effect on the spectral response of c-Si:H solar cells. When measured under coloured bias light, the apparent quantum efficiency value of a c-Si:H cell can be largely enhanced. This phenomenon is a typical result of trapping induced field modification in the bulk of a drift type solar cell. The discovery of this phenomenon has experimentally proved that field-driven transport to a large extend exist in a c-Si:H solar cell.

Impact of the silicon substrate resistivity and growth condition on the deep levels in Ni-Au/AlN/Si MIS Capacitors

NASA Astrophysics Data System (ADS)

Wang, Chong; Simoen, Eddy; Zhao, Ming; Li, Wei

2017-10-01

Deep levels formed under different growth conditions of a 200 nm AlN buffer layer on B-doped Czochralski Si(111) substrates with different resistivity were investigated by deep-level transient spectroscopy (DLTS) on metal-insulator-semiconductor capacitors. Growth-temperature-dependent Al diffusion in the Si substrate was derived from the free carrier density obtained by capacitance-voltage measurement on samples grown on p- substrates. The DLTS spectra revealed a high concentration of point and extended defects in the p- and p+ silicon substrates, respectively. This indicated a difference in the electrically active defects in the silicon substrate close to the AlN/Si interface, depending on the B doping concentration.

Purified silicon production system

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2004-03-30

Method and apparatus for producing purified bulk silicon from highly impure metallurgical-grade silicon source material at atmospheric pressure. Method involves: (1) initially reacting iodine and metallurgical-grade silicon to create silicon tetraiodide and impurity iodide byproducts in a cold-wall reactor chamber; (2) isolating silicon tetraiodide from the impurity iodide byproducts and purifying it by distillation in a distillation chamber; and (3) transferring the purified silicon tetraiodide back to the cold-wall reactor chamber, reacting it with additional iodine and metallurgical-grade silicon to produce silicon diiodide and depositing the silicon diiodide onto a substrate within the cold-wall reactor chamber. The two chambers are at atmospheric pressure and the system is open to allow the introduction of additional source material and to remove and replace finished substrates.

Silicon induced stability and mobility of indium zinc oxide based bilayer thin film transistors

NASA Astrophysics Data System (ADS)

Chauhan, Ram Narayan; Tiwari, Nidhi; Liu, Po-Tsun; Shieh, Han-Ping D.; Kumar, Jitendra

2016-11-01

Indium zinc oxide (IZO), silicon containing IZO, and IZO/IZO:Si bilayer thin films have been prepared by dual radio frequency magnetron sputtering on glass and SiO2/Si substrates for studying their chemical compositions and electrical characteristics in order to ascertain reliability for thin film transistor (TFT) applications. An attempt is therefore made here to fabricate single IZO and IZO/IZO:Si bilayer TFTs to study the effect of film thickness, silicon incorporation, and bilayer active channel on device performance and negative bias illumination stress (NBIS) stability. TFTs with increasing single active IZO layer thickness exhibit decrease in carrier mobility but steady improvement in NBIS; the best values being μFE ˜ 27.0, 22.0 cm2/Vs and ΔVth ˜ -13.00, -6.75 V for a channel thickness of 7 and 27 nm, respectively. While silicon incorporation is shown to reduce the mobility somewhat, it raises the stability markedly (ΔVth ˜ -1.20 V). Further, IZO (7 nm)/IZO:Si (27 nm) bilayer based TFTs display useful characteristics (field effect mobility, μFE = 15.3 cm2/Vs and NBIS value, ΔVth =-0.75 V) for their application in transparent electronics.

Silicon carbide thyristor

NASA Technical Reports Server (NTRS)

Edmond, John A. (Inventor); Palmour, John W. (Inventor)

1996-01-01

The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.

Bidisperse silica nanoparticles close-packed monolayer on silicon substrate by three step spin method

NASA Astrophysics Data System (ADS)

Khanna, Sakshum; Marathey, Priyanka; Utsav, Chaliawala, Harsh; Mukhopadhyay, Indrajit

2018-05-01

We present the studies on the structural properties of monolayer Bidisperse silica (SiO2) nanoparticles (BDS) on Silicon (Si-100) substrate using spin coating technique. The Bidisperse silica nanoparticle was synthesised by the modified sol-gel process. Nanoparticles on the substrate are generally assembled in non-close/close-packed monolayer (CPM) form. The CPM form is obtained by depositing the colloidal suspension onto the silicon substrate using complex techniques. Here we report an effective method for forming a monolayer of bidisperse silica nanoparticle by three step spin coating technique. The samples were prepared by mixing the monodisperse solutions of different particles size 40 and 100 nm diameters. The bidisperse silica nanoparticles were self-assembled on the silicon substrate forming a close-packed monolayer film. The scanning electron microscope images of bidisperse films provided in-depth film structure of the film. The maximum surface coverage obtained was around 70-80%.

Correlating single-molecule and ensemble-average measurements of peptide adsorption onto different inorganic materials.

PubMed

Kim, Seong-Oh; Jackman, Joshua A; Mochizuki, Masahito; Yoon, Bo Kyeong; Hayashi, Tomohiro; Cho, Nam-Joon

2016-06-07

The coating of solid-binding peptides (SBPs) on inorganic material surfaces holds significant potential for improved surface functionalization at nano-bio interfaces. In most related studies, the goal has been to engineer peptides with selective and high binding affinity for a target material. The role of the material substrate itself in modulating the adsorption behavior of a peptide molecule remains less explored and there are few studies that compare the interaction of one peptide with different inorganic substrates. Herein, using a combination of two experimental techniques, we investigated the adsorption of a 16 amino acid-long random coil peptide to various inorganic substrates - gold, silicon oxide, titanium oxide and aluminum oxide. Quartz crystal microbalance-dissipation (QCM-D) experiments were performed in order to measure the peptide binding affinity for inorganic solid supports at the ensemble average level, and atomic force microscopy (AFM) experiments were conducted in order to determine the adhesion force of a single peptide molecule. A positive trend was observed between the total mass uptake of attached peptide and the single-molecule adhesion force on each substrate. Peptide affinity for gold was appreciably greater than for the oxide substrates. Collectively, the results obtained in this study offer insight into the ways in which inorganic materials can differentially influence and modulate the adhesion of SBPs.

Fabrication of novel plasmonics-active substrates

NASA Astrophysics Data System (ADS)

Dhawan, Anuj; Gerhold, Michael; Du, Yan; Misra, Veena; Vo-Dinh, Tuan

2009-02-01

This paper describes methodologies for fabricating of highly efficient plasmonics-active SERS substrates - having metallic nanowire structures with pointed geometries and sub-5 nm gap between the metallic nanowires enabling concentration of high EM fields in these regions - on a wafer-scale by a reproducible process that is compatible with large-scale development of these substrates. Excitation of surface plasmons in these nanowire structures leads to substantial enhancement in the Raman scattering signal obtained from molecules lying in the vicinity of the nanostructure surface. The methodologies employed included metallic coating of silicon nanowires fabricated by employing deep UV lithography as well as controlled growth of silicon germanium on silicon nanostructures to form diamond-shaped nanowire structures followed by metallic coating. These SERS substrates were employed for detecting chemical and biological molecules of interest. In order to characterize the SERS substrates developed in this work, we obtained SERS signals from molecules such as p-mercaptobenzoic acid (pMBA) and cresyl fast violet (CFV) attached to or adsorbed on the metal-coated SERS substrates. It was observed that both gold-coated triangular shaped nanowire substrates as well as gold-coated diamond shaped nanowire substrates provided very high SERS signals for the nanowires having sub-15 nm gaps and that the SERS signal depends on the closest spacing between the metal-coated silicon and silicon germanium nanowires. SERS substrates developed by the different processes were also employed for detection of biological molecules such as DPA (Dipicolinic Acid), an excellent marker for spores of bacteria such as Anthrax.

Crystalline silicon growth in nickel/a-silicon bilayer

NASA Astrophysics Data System (ADS)

Mohiddon, Md Ahamad; Naidu, K. Lakshun; Dalba, G.; Rocca, F.; Krishna, M. Ghanashyam

2013-02-01

The effect of substrate temperature on amorphous Silicon crystallization, mediated by metal impurity is reported. Bilayers of Ni(200nm)/Si(400nm) are deposited on fused silica substrate by electron beam evaporator at 200 and 500 °C. Raman mapping shows that, 2 to 5 micron size crystalline silicon clusters are distributed over the entire surface of the sample. X-ray diffraction and X-ray absorption spectroscopy studies demonstrate silicon crystallizes over the metal silicide seeds and grow with the annealing temperature.

Solar cell with silicon oxynitride dielectric layer

DOEpatents

Shepherd, Michael; Smith, David D

2015-04-28

Solar cells with silicon oxynitride dielectric layers and methods of forming silicon oxynitride dielectric layers for solar cell fabrication are described. For example, an emitter region of a solar cell includes a portion of a substrate having a back surface opposite a light receiving surface. A silicon oxynitride (SiO.sub.xN.sub.y, 0

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

DOEpatents

Feng, Tom; Ghosh, Amal K.

1980-01-01

Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300.degree. C. to about 400.degree. C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250.degree. C. Preferably the insulating layer is naturally grown silicon oxide layer.

Active pixel sensor array as a detector for electron microscopy.

PubMed

Milazzo, Anna-Clare; Leblanc, Philippe; Duttweiler, Fred; Jin, Liang; Bouwer, James C; Peltier, Steve; Ellisman, Mark; Bieser, Fred; Matis, Howard S; Wieman, Howard; Denes, Peter; Kleinfelder, Stuart; Xuong, Nguyen-Huu

2005-09-01

A new high-resolution recording device for transmission electron microscopy (TEM) is urgently needed. Neither film nor CCD cameras are systems that allow for efficient 3-D high-resolution particle reconstruction. We tested an active pixel sensor (APS) array as a replacement device at 200, 300, and 400 keV using a JEOL JEM-2000 FX II and a JEM-4000 EX electron microscope. For this experiment, we used an APS prototype with an area of 64 x 64 pixels of 20 microm x 20 microm pixel pitch. Single-electron events were measured by using very low beam intensity. The histogram of the incident electron energy deposited in the sensor shows a Landau distribution at low energies, as well as unexpected events at higher absorbed energies. After careful study, we concluded that backscattering in the silicon substrate and re-entering the sensitive epitaxial layer a second time with much lower speed caused the unexpected events. Exhaustive simulation experiments confirmed the existence of these back-scattered electrons. For the APS to be usable, the back-scattered electron events must be eliminated, perhaps by thinning the substrate to less than 30 microm. By using experimental data taken with an APS chip with a standard silicon substrate (300 microm) and adjusting the results to take into account the effect of a thinned silicon substrate (30 microm), we found an estimate of the signal-to-noise ratio for a back-thinned detector in the energy range of 200-400 keV was about 10:1 and an estimate for the spatial resolution was about 10 microm.

Developments toward an 18% efficient silicon solar cell

NASA Technical Reports Server (NTRS)

Meulenberg, A., Jr.

1983-01-01

Limitations to increased open-circuit voltage were identified and experimentally verified for 0.1 ohm-cm solar cells with heavily doped emitters. After major reduction in the dark current contribution from the metal-silicon interface of the grid contacts, the surface recombination velocity of the oxide-silicon interface of shallow junction solar cells is the limiting factor. In deep junction solar cells, where the junction field does not aid surface collection, the emitter bulk is the limiting factor. Singly-diffused, shallow junction cells have been fabricated with open circuit voltages in excess of 645 mV. Double-diffusion shallow and deep junctions cells have displayed voltages above 650 mV. MIS solar cells formed on 0.1 ohm-cm substrates have exibited the lowest dark currents produced in the course of the contract work.

Methods of repairing a substrate

NASA Technical Reports Server (NTRS)

Riedell, James A. (Inventor); Easler, Timothy E. (Inventor)

2011-01-01

A precursor of a ceramic adhesive suitable for use in a vacuum, thermal, and microgravity environment. The precursor of the ceramic adhesive includes a silicon-based, preceramic polymer and at least one ceramic powder selected from the group consisting of aluminum oxide, aluminum nitride, boron carbide, boron oxide, boron nitride, hafnium boride, hafnium carbide, hafnium oxide, lithium aluminate, molybdenum silicide, niobium carbide, niobium nitride, silicon boride, silicon carbide, silicon oxide, silicon nitride, tin oxide, tantalum boride, tantalum carbide, tantalum oxide, tantalum nitride, titanium boride, titanium carbide, titanium oxide, titanium nitride, yttrium oxide, zirconium boride, zirconium carbide, zirconium oxide, and zirconium silicate. Methods of forming the ceramic adhesive and of repairing a substrate in a vacuum and microgravity environment are also disclosed, as is a substrate repaired with the ceramic adhesive.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

1997-01-01

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Terahertz Magnetic Mirror Realized with Dielectric Resonator Antennas.

PubMed

Headland, Daniel; Nirantar, Shruti; Withayachumnankul, Withawat; Gutruf, Philipp; Abbott, Derek; Bhaskaran, Madhu; Fumeaux, Christophe; Sriram, Sharath

2015-11-25

Single-crystal silicon is bonded to a metal-coated substrate and etched in order to form an array of microcylinder passive terahertz dielectric resonator antennas (DRAs). The DRAs exhibit a magnetic response, and hence the array behaves as an efficient artificial magnetic conductor (AMC), with potential for terahertz antenna and sensing applications. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Method of deposition of silicon carbide layers on substrates and product

DOEpatents

Angelini, Peter; DeVore, Charles E.; Lackey, Walter J.; Blanco, Raymond E.; Stinton, David P.

1984-01-01

A method for direct chemical vapor deposition of silicon carbide to substrates, especially nuclear waste particles, is provided by the thermal decomposition of methylsilane at about 800.degree. C. to 1050.degree. C. when the substrates have been confined within a suitable coating environment.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, Stephen M.; Tao, Hongyi; Todd-Copley, Judith A.

1991-01-01

A process for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, S.M.; Tao, H.; Todd-Copley, J.A.

1991-06-11

A process is disclosed for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength. 1 figure.

Improved toughness of silicon carbide

NASA Technical Reports Server (NTRS)

Palm, J. A.

1976-01-01

Impact energy absorbing layers (EALs) comprised of partially densified silicon carbide were formed in situ on fully sinterable silicon carbide substrates. After final sintering, duplex silicon carbide structures resulted which were comprised of a fully sintered, high density silicon carbide substrate or core, overlayed with an EAL of partially sintered silicon carbide integrally bonded to its core member. Thermal cycling tests proved such structures to be moderately resistant to oxidation and highly resistant to thermal shock stresses. The strength of the developed structures in some cases exceeded but essentially it remained the same as the fully sintered silicon carbide without the EAL. Ballistic impact tests indicated that substantial improvements in the toughness of sintered silicon carbide were achieved by the use of the partially densified silicon carbide EALs.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Zook, J. D.; Harrison, W. B.; Scott, M. W.; Hendrickson, G.; Wolner, H. A.; Nelson, L. D.; Schuller, T. L.; Peterson, A. A.

1976-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon by dip-coating one surface of carbonized ceramic substrates with a thin layer of large grain polycrystalline silicon was investigated. The dip-coating methods studied were directed toward a minimum cost process with the ultimate objective of producing solar cells with a conversion efficiency of 10% or greater. The technique shows excellent promise for low cost, labor-saving, scale-up potentialities and would provide an end product of sheet silicon with a rigid and strong supportive backing. An experimental dip-coating facility was designed and constructed, several substrates were successfully dip-coated with areas as large as 25 sq cm and thicknesses of 12 micron to 250 micron. There appears to be no serious limitation on the area of a substrate that could be coated. Of the various substrate materials dip-coated, mullite appears to best satisfy the requirement of the program. An inexpensive process was developed for producing mullite in the desired geometry.

Low-Power RIE of SiO2 in CHF3 To Obtain Steep Sidewalls

NASA Technical Reports Server (NTRS)

Turner, Tasha; Wu, Chi

2003-01-01

A reactive-ion etching (RIE) process has been developed to enable the formation of holes with steep sidewalls in a layer of silicon dioxide that covers a silicon substrate. The holes in question are through the thickness of the SiO2 and are used to define silicon substrate areas to be etched or to be built upon through epitaxial deposition of silicon. The sidewalls of these holes are required to be vertical in order to ensure that the sidewalls of the holes to be etched in the substrate or the sidewalls of the epitaxial deposits, respectively, also turn out to be vertical.

Metal-insulator transition properties of sputtered silicon-doped and un-doped vanadium dioxide films at terahertz range

NASA Astrophysics Data System (ADS)

Zhang, Huafu; Wu, Zhiming; Niu, Ruihua; Wu, Xuefei; he, Qiong; Jiang, Yadong

2015-03-01

Silicon-doped and un-doped vanadium dioxide (VO2) films were synthesized on high-purity single-crystal silicon substrates by means of reactive direct current magnetron sputtering followed by thermal annealing. The structure, morphology and metal-insulator transition properties of silicon-doped VO2 films at terahertz range were measured and compared to those of un-doped VO2 films. X-ray diffraction and scanning electron microscopy indicated that doping the films with silicon significantly affects the preferred crystallographic orientation and surface morphologies (grain size, pores and characteristics of grain boundaries). The temperature dependence of terahertz transmission shows that the transition temperature, hysteresis width and transition sharpness greatly depend on the silicon contents while the transition amplitude was relatively insensitive to the silicon contents. Interestingly, the VO2 film doped with a silicon content of 4.6 at.% shows excellent terahertz switching characteristics, namely a small hysteresis width of 4.5 °C, a giant transmission modulation ratio of about 82% and a relatively low transition temperature of 56.1 °C upon heating. This work experimentally indicates that silicon doping can effectively control not only the surface morphology but also the metal-insulator transition characteristics of VO2 films at terahertz range.

Purification and deposition of silicon by an iodide disproportionation reaction

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2002-01-01

Method and apparatus for producing purified bulk silicon from highly impure metallurgical-grade silicon source material at atmospheric pressure. Method involves: (1) initially reacting iodine and metallurgical-grade silicon to create silicon tetraiodide and impurity iodide byproducts in a cold-wall reactor chamber; (2) isolating silicon tetraiodide from the impurity iodide byproducts and purifying it by distillation in a distillation chamber; and (3) transferring the purified silicon tetraiodide back to the cold-wall reactor chamber, reacting it with additional iodine and metallurgical-grade silicon to produce silicon diiodide and depositing the silicon diiodide onto a substrate within the cold-wall reactor chamber. The two chambers are at atmospheric pressure and the system is open to allow the introduction of additional source material and to remove and replace finished substrates.

Composition Comprising Silicon Carbide

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2012-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Method and apparatus for forming conformal SiN.sub.x films

DOEpatents

Wang, Qi

2007-11-27

A silicon nitride film formation method includes: Heating a substrate to be subjected to film formation to a substrate temperature; heating a wire to a wire temperature; supplying silane, ammonia, and hydrogen gases to the heating member; and forming a silicon nitride film on the substrate.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Zero lattice mismatch and twin-free single crystalline ScN buffer layers for GaN growth on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lupina, L.; Zoellner, M. H.; Dietrich, B.

2015-11-16

We report the growth of thin ScN layers deposited by plasma-assisted molecular beam epitaxy on Sc{sub 2}O{sub 3}/Y{sub 2}O{sub 3}/Si(111) substrates. Using x-ray diffraction, Raman spectroscopy, and transmission electron microscopy, we find that ScN films grown at 600 °C are single crystalline, twin-free with rock-salt crystal structure, and exhibit a direct optical band gap of 2.2 eV. A high degree of crystalline perfection and a very good lattice matching between ScN and GaN (misfit < 0.1%) makes the ScN/Sc{sub 2}O{sub 3}/Y{sub 2}O{sub 3} buffer system a very promising template for the growth of high quality GaN layers on silicon.

Graphite based Schottky diodes formed semiconducting substrates

NASA Astrophysics Data System (ADS)

Schumann, Todd; Tongay, Sefaattin; Hebard, Arthur

2010-03-01

We demonstrate the formation of semimetal graphite/semiconductor Schottky barriers where the semiconductor is either silicon (Si), gallium arsenide (GaAs) or 4H-silicon carbide (4H-SiC). The fabrication can be as easy as allowing a dab of graphite paint to air dry on any one of the investigated semiconductors. Near room temperature, the forward-bias diode characteristics are well described by thermionic emission, and the extracted barrier heights, which are confirmed by capacitance voltage measurements, roughly follow the Schottky-Mott relation. Since the outermost layer of the graphite electrode is a single graphene sheet, we expect that graphene/semiconductor barriers will manifest similar behavior.

Laboratory and testbeam results for thin and epitaxial planar sensors for HL-LHC

DOE PAGES

Bubna, M.; Bolla, G.; Bortoletto, D.; ...

2015-08-03

The High-Luminosity LHC (HL-LHC) upgrade of the CMS pixel detector will require the development of novel pixel sensors which can withstand the increase in instantaneous luminosity to L = 5 × 10 34 cm –2s –1 and collect ~ 3000fb –1 of data. The innermost layer of the pixel detector will be exposed to doses of about 10 16 n eq/ cm 2. Hence, new pixel sensors with improved radiation hardness need to be investigated. A variety of silicon materials (Float-zone, Magnetic Czochralski and Epitaxially grown silicon), with thicknesses from 50 μm to 320 μm in p-type and n-type substrates have beenmore » fabricated using single-sided processing. The effect of reducing the sensor active thickness to improve radiation hardness by using various techniques (deep diffusion, wafer thinning, or growing epitaxial silicon on a handle wafer) has been studied. Furthermore, the results for electrical characterization, charge collection efficiency, and position resolution of various n-on-p pixel sensors with different substrates and different pixel geometries (different bias dot gaps and pixel implant sizes) will be presented.« less

Silicon on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Pickering, C.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon was investigated. It was hoped this could be done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Work was directed towards the solution of unique cell processing/design problems encountered with the silicon-ceramic (SOC) material due to its intimate contact with the ceramic substrate. Significant progress was demonstrated in the following areas; (1) the continuous coater succeeded in producing small-area coatings exhibiting unidirectional solidification and substatial grain size; (2) dip coater succeeded in producing thick (more than 500 micron) dendritic layers at coating speeds of 0.2-0.3 cm/sec; and (3) a standard for producing total area SOC solar cells using slotted ceramic substrates was developed.

Graphene-silicon layered structures on single-crystalline Ir(111) thin films

DOE PAGES

Que, Yande D.; Tao, Jing; Zhang, Yong; ...

2015-01-20

Epitaxial growth of graphene on transition metal crystals, such as Ru,⁽¹⁻³⁾ Ir,⁽⁴⁻⁶⁾ and Ni,⁽⁷⁾ provides large-area, uniform graphene layers with controllable defect density, which is crucial for practical applications in future devices. To decrease the high cost of single-crystalline metal bulks, single-crystalline metal films are strongly suggested as the substrates for epitaxial growth large-scale high-quality graphene.⁽⁸⁻¹⁰⁾ Moreover, in order to weaken the interactions of graphene with its metal host, which may result in a suppression of the intrinsic properties of graphene,⁽¹¹ ¹²⁾ the method of element intercalation of semiconductors at the interface between an epitaxial graphene layer and a transitionmore » metal substrate has been successfully realized.⁽¹³⁻¹⁶⁾« less

Kapitza thermal resistance studied by high-frequency photothermal radiometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horny, Nicolas; Chirtoc, Mihai; Hamaoui, Georges

2016-07-18

Kapitza thermal resistance is determined using high-frequency photothermal radiometry (PTR) extended for modulation up to 10 MHz. Interfaces between 50 nm thick titanium coatings and silicon or stainless steel substrates are studied. In the used configuration, the PTR signal is not sensitive to the thermal conductivity of the film nor to its optical absorption coefficient, thus the Kapitza resistance is directly determined from single thermal parameter fits. Results of thermal resistances show the significant influence of the nature of the substrate, as well as of the presence of free electrons at the interface.

Polycrystalline silicon on tungsten substrates

NASA Technical Reports Server (NTRS)

Bevolo, A. J.; Schmidt, F. A.; Shanks, H. R.; Campisi, G. J.

1979-01-01

Thin films of electron-beam-vaporized silicon were deposited on fine-grained tungsten substrates under a pressure of about 1 x 10 to the -10th torr. Mass spectra from a quadrupole residual-gas analyzer were used to determine the partial pressure of 13 residual gases during each processing step. During separate silicon depositions, the atomically clean substrates were maintained at various temperatures between 400 and 780 C, and deposition rates were between 20 and 630 A min. Surface contamination and interdiffusion were monitored by in situ Auger electron spectrometry before and after cleaning, deposition, and annealing. Auger depth profiling, X-ray analysis, and SEM in the topographic and channeling modes were utilized to characterize the samples with respect to silicon-metal interface, interdiffusion, silicide formation, and grain size of silicon. The onset of silicide formation was found to occur at approximately 625 C. Above this temperature tungsten silicides were formed at a rate faster than the silicon deposition. Fine-grain silicon films were obtained at lower temperatures.

Surface Attachment of Gold Nanoparticles Guided by Block Copolymer Micellar Films and Its Application in Silicon Etching

PubMed Central

Wei, Mingjie; Wang, Yong

2015-01-01

Patterning metallic nanoparticles on substrate surfaces is important in a number of applications. However, it remains challenging to fabricate such patterned nanoparticles with easily controlled structural parameters, including particle sizes and densities, from simple methods. We report on a new route to directly pattern pre-formed gold nanoparticles with different diameters on block copolymer micellar monolayers coated on silicon substrates. Due to the synergetic effect of complexation and electrostatic interactions between the micellar cores and the gold particles, incubating the copolymer-coated silicon in a gold nanoparticles suspension leads to a monolayer of gold particles attached on the coated silicon. The intermediate micellar film was then removed using oxygen plasma treatment, allowing the direct contact of the gold particles with the Si substrate. We further demonstrate that the gold nanoparticles can serve as catalysts for the localized etching of the silicon substrate, resulting in nanoporous Si with a top layer of straight pores. PMID:28793407

RF sputtering for controlling dihydride and monohydride bond densities in amorphous silicon hydride

DOEpatents

Jeffery, F.R.; Shanks, H.R.

1980-08-26

A process is described for controlling the dihydride and monohydride bond densities in hydrogenated amorphous silicone produced by reactive rf sputtering of an amorphous silicon target. There is provided a chamber with an amorphous silicon target and a substrate therein with the substrate and the target positioned such that when rf power is applied to the target the substrate is in contact with the sputtering plasma produced thereby. Hydrogen and argon are fed to the chamber and the pressure is reduced in the chamber to a value sufficient to maintain a sputtering plasma therein, and then rf power is applied to the silicon target to provide a power density in the range of from about 7 watts per square inch to about 22 watts per square inch to sputter an amorphous solicone hydride onto the substrate, the dihydride bond density decreasing with an increase in the rf power density. Substantially pure monohydride films may be produced.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

Method of forming contacts for a back-contact solar cell

DOEpatents

Manning, Jane

2015-10-20

Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.

Method of forming contacts for a back-contact solar cell

DOEpatents

Manning, Jane

2014-07-15

Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.

Nanoscale fabrication using single-ion impacts

NASA Astrophysics Data System (ADS)

Millar, Victoria; Pakes, Chris I.; Cimmino, Alberto; Brett, David; Jamieson, David N.; Prawer, Steven D.; Yang, Changyi; Rout, Bidhudutta; McKinnon, Rita P.; Dzurak, Andrew S.; Clark, Robert G.

2001-11-01

We describe a novel technique for the fabrication of nanoscale structures, based on the development of localized chemical modification caused in a PMMA resist by the implantation of single ions. The implantation of 2 MeV He ions through a thin layer of PMMA into an underlying silicon substrate causes latent damage in the resist. On development of the resist we demonstrate the formation within the PMMA layer of clearly defined etched holes, of typical diameter 30 nm, observed using an atomic force microscope employing a carbon nanotube SPM probe in intermittent-contact mode. This technique has significant potential applications. Used purely to register the passage of an ion, it may be a useful verification of the impact sites in an ion-beam modification process operating at the single-ion level. Furthermore, making use of the hole in the PMMA layer to perform subsequent fabrication steps, it may be applied to the fabrication of self-aligned structures in which surface features are fabricated directly above regions of an underlying substrate that are locally doped by the implanted ion. Our primary interest in single-ion resists relates to the development of a solid-state quantum computer based on an array of 31P atoms (which act as qubits) embedded with nanoscale precision in a silicon matrix. One proposal for the fabrication of such an array is by phosphorous-ion implantation. A single-ion resist would permit an accurate verification of 31P implantation sites. Subsequent metalisation of the latent damage may allow the fabrication of self-aligned metal gates above buried phosphorous atoms.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

Fabrication of high-resolution nanostructures of complex geometry by the single-spot nanolithography method

PubMed Central

Anisimova, Margarita; Samardak, Aleksei; Ognev, Alexey

2015-01-01

Summary The paper presents a method for the high-resolution production of polymer nanopatterns with controllable geometrical parameters by means of a single-spot electron-beam lithography technique. The essence of the method entails the overexposure of a positive-tone resist, spin-coated onto a substrate where nanoscale spots are exposed to an electron beam with a dose greater than 0.1 pC per dot. A single-spot enables the fabrication of a nanoring, while a chain of spots placed at distance of 5–30 nm from each other allows the production of a polymer pattern of complex geometry of sub-10 nm resolution. We demonstrate that in addition to the naturally oxidized silicon substrates, gold-coated substrates can also successfully be used for the single-spot nanopattering technique. An explanation of the results related to the resist overexposure was demonstrated using Monte Carlo simulations. Our nanofabrication method significantly accelerates (up to 10 times) the fabrication rate as compared to conventional lithography on positive-tone resist. This technique can be potentially employed in the electronics industry for the production of nanoprinted lithography molds, etching masks, nanoelectronics, nanophotonics, NEMS and MEMS devices. PMID:25977869

Analysis of single band and dual band graphene based patch antenna for terahertz region

NASA Astrophysics Data System (ADS)

George, Jemima Nissiyah; Madhan, M. Ganesh

2017-10-01

A microstrip patch antenna is designed using a very thin layer of graphene as the radiating patch, which is fed by a microstrip transmission line. The graphene based patch is designed on a silicon substrate having a dielectric constant of 11.9, to radiate at a single frequency of 2.6 THz. Further, this antenna is made to resonate at dual frequencies of 2.48 THz and 3.35 THz, by changing the substrate height, which is reported for the first time. Various antenna parameters such as return loss, VSWR, gain, efficiency and bandwidth are also determined for the single and dual band operation. For the single band operation, a bandwidth of 145.4 GHz and an efficiency of 92% was achieved. For dual band operation, a maximum bandwidth of 140.5 GHz was obtained at 3.35 THz and an efficiency of 87.3% was obtained at the first resonant frequency of 2.48 THz. The absorption cross section of the antenna is also analysed for various substrate heights and has maximum peaks at the corresponding resonating frequencies. The simulation has been carried out by using a full wave electromagnetic simulator based on FDTD method.

High-Performance Ultrathin Organic-Inorganic Hybrid Silicon Solar Cells via Solution-Processed Interface Modification.

PubMed

Zhang, Jie; Zhang, Yinan; Song, Tao; Shen, Xinlei; Yu, Xuegong; Lee, Shuit-Tong; Sun, Baoquan; Jia, Baohua

2017-07-05

Organic-inorganic hybrid solar cells based on n-type crystalline silicon and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) exhibited promising efficiency along with a low-cost fabrication process. In this work, ultrathin flexible silicon substrates, with a thickness as low as tens of micrometers, were employed to fabricate hybrid solar cells to reduce the use of silicon materials. To improve the light-trapping ability, nanostructures were built on the thin silicon substrates by a metal-assisted chemical etching method (MACE). However, nanostructured silicon resulted in a large amount of surface-defect states, causing detrimental charge recombination. Here, the surface was smoothed by solution-processed chemical treatment to reduce the surface/volume ratio of nanostructured silicon. Surface-charge recombination was dramatically suppressed after surface modification with a chemical, associated with improved minority charge-carrier lifetime. As a result, a power conversion efficiency of 9.1% was achieved in the flexible hybrid silicon solar cells, with a substrate thickness as low as ∼14 μm, indicating that interface engineering was essential to improve the hybrid junction quality and photovoltaic characteristics of the hybrid devices.

Circularly polarized Raman study on diamond structure crystals

NASA Astrophysics Data System (ADS)

Lee, Je-Ho; Kim, Sera; Seong, Maeng-Je

2018-01-01

Circularly polarized Raman and/or photoluminescence (PL) analyses have recently been very important in studying physical properties of many layered materials that were either mechanically exfoliated or grown by chemical-vapor-deposition (CVD) on silicon substrates. Since silicon Raman signal is always accompanied by the circularly polarized Raman and/or PL signal from the layered materials, observation of proper circularly polarized Raman selection rules on silicon substrates would be extremely good indicator that the circularly polarized Raman and/or PL measurements on the layered materials were done properly. We have performed circularly polarized Raman measurements on silicon substrates and compared the results with the Raman intensities calculated by using Raman tensors of the diamond crystal structure. Our experimental results were in excellent agreement with the calculation. Similar circularly polarized Raman analysis done on germanium substrate also showed good agreement.

Passivation coating for flexible substrate mirrors

DOEpatents

Tracy, C. Edwin; Benson, David K.

1990-01-01

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate before metal deposition thereon to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors. Also, the silver or other reflective metal layer on mirrors comprising thin, lightweight, flexible substrates of metal or polymer sheets coated with glassy layers can be protected with silicon nitride according to this invention.

Investigations into the impact of various substrates and ZnO ultra thin seed layers prepared by atomic layer deposition on growth of ZnO nanowire array

PubMed Central

2012-01-01

The impact of various substrates and zinc oxide (ZnO) ultra thin seed layers prepared by atomic layer deposition on the geometric morphology of subsequent ZnO nanowire arrays (NWs) fabricated by the hydrothermal method was investigated. The investigated substrates included B-doped ZnO films, indium tin oxide films, single crystal silicon (111), and glass sheets. Scanning electron microscopy and X-ray diffraction measurements revealed that the geometry and aligment of the NWs were controlled by surface topography of the substrates and thickness of the ZnO seed layers, respectively. According to atomic force microscopy data, we suggest that the substrate, fluctuate amplitude and fluctuate frequency of roughness on ZnO seed layers have a great impact on the alignment of the resulting NWs, whereas the influence of the seed layers' texture was negligible. PMID:22759838

Optimization of solar cells for air mass zero operation and a study of solar cells at high temperatures

NASA Technical Reports Server (NTRS)

Hovel, H. J.; Vernon, S. M.

1982-01-01

The power to weight ratio of GaAs cells can be reduced by fabricating devices using thin GaAs films on low density substrate materials (silicon, glass, plastics). A graphoepitaxy technique was developed which uses fine geometric patterns in the substrate to affect growth. Initial substrates were processed by etching 25 microns deep grooves into 100 oriented wafers; fine-grained polycrystalline GaAs layers 25-50 microns thick were then deposited on these and recrystallization was performed, heating the substrates to above the GaAs melting point in ASH3 atmosphere, resulting in large grain regrowth oriented along the groove dimensions. Experiments with smaller groove depths and spacings were initially encouraging; single large GaAs grains would totally cover one and often two groove fields of 14 groove each spanning several hundred microns. Dielectric coatings on the grooved substrates were also used to modify the growth.

Gallium Arsenide Monolithic Optoelectronic Circuits

NASA Astrophysics Data System (ADS)

Bar-Chaim, N.; Katz, J.; Margalit, S.; Ury, I.; Wilt, D.; Yariv, A.

1981-07-01

The optical properties of GaAs make it a very useful material for the fabrication of optical emitters and detectors. GaAs also possesses electronic properties which allow the fabrication of high speed electronic devices which are superior to conventional silicon devices. Monolithic optoelectronic circuits are formed by the integration of optical and electronic devices on a single GaAs substrate. Integration of many devices is most easily accomplished on a semi-insulating (SI) sub-strate. Several laser structures have been fabricated on SI GaAs substrates. Some of these lasers have been integrated with Gunn diodes and with metal semiconductor field effect transistors (MESFETs). An integrated optical repeater has been demonstrated in which MESFETs are used for optical detection and electronic amplification, and a laser is used to regenerate the optical signal. Monolithic optoelectronic circuits have also been constructed on conducting substrates. A heterojunction bipolar transistor driver has been integrated with a laser on an n-type GaAs substrate.

Decal transfer microfabrication

DOEpatents

Nuzzo, Ralph G.; Childs, William Robert

2004-10-19

A method of making a microstructure includes forming a pattern in a surface of a silicon-containing elastomer, oxidizing the pattern, contacting the pattern with a substrate; and bonding the oxidized pattern and the substrate such that the pattern and the substrate are irreversibly attached. The silicon-containing elastomer may be removably attached to a transfer pad.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

NASA Astrophysics Data System (ADS)

Balpande, Suresh S.; Pande, Rajesh S.

2016-04-01

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of harvester and schottky diodes based voltage multiplier.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Balpande, Suresh S., E-mail: balpandes@rknec.edu; Pande, Rajesh S.

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition tomore » this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of harvester and schottky diodes based voltage multiplier.« less

Modification of surface properties of cellulosic substrates by quaternized silicone emulsions.

PubMed

Purohit, Parag S; Somasundaran, P

2014-07-15

The present work describes the effect of quaternization of silicones as well as the relevant treatment parameter pH on the frictional, morphological and relaxation properties of fabric substrates. Due to their unique surface properties, silicone polymers are extensively used to modify surface properties of various materials, although the effects of functionalization of silicones and relevant process conditions on modification of substrates are not well understood. Specifically we show a considerable reduction in fabric friction, roughness and waviness upon treatment with quaternized silicones. The treatment at acidic pH results in better deposition of silicone polymers onto the fabric as confirmed through streaming potential measurements which show charge reversal of the fabric. Interestingly, Raman spectroscopy studies show the band of C-O ring stretching mode at ∼1095 cm(-1) shift towards higher wavenumber indicating lowering of stress in fibers upon appropriate silicone treatment. Thus along with the morphological and frictional properties being altered, silicone treatment can lead to a reduction in fabric strain. It is concluded that the electrostatic interactions play an initial role in modification of the fiber substrate followed by multilayer deposition of polymer. This multi-technique approach to study fiber properties upon treatment by combining macro to molecular level methods has helped in understanding of new functional coating materials. Copyright © 2014 Elsevier Inc. All rights reserved.

Nanoscale Etching and Indentation of Silicon Surfaces with Carbon Nanotubes

NASA Technical Reports Server (NTRS)

Dzegilenko, Fedor N.; Srivastava, Deepak; Saini, Subhash

1998-01-01

The possibility of nanolithography of silicon and germanium surfaces with bare carbon nanotube tips of scanning probe microscopy devices is considered with large scale classical molecular dynamics (MD) simulations employing Tersoff's reactive many-body potential for heteroatomic C/Si/Ge system. Lithography plays a key role in semiconductor manufacturing, and it is expected that future molecular and quantum electronic devices will be fabricated with nanolithographic and nanodeposition techniques. Carbon nanotubes, rolled up sheets of graphene made of carbon, are excellent candidates for use in nanolithography because they are extremely strong along axial direction and yet extremely elastic along radial direction. In the simulations, the interaction of a carbon nanotube tip with silicon surfaces is explored in two regimes. In the first scenario, the nanotubes barely touch the surface, while in the second they are pushed into the surface to make "nano holes". The first - gentle scenario mimics the nanotube-surface chemical reaction induced by the vertical mechanical manipulation of the nanotube. The second -digging - scenario intends to study the indentation profiles. The following results are reported in the two cases. In the first regime, depending on the surface impact site, two major outcomes outcomes are the selective removal of either a single surface atom or a surface dimer off the silicon surface. In the second regime, the indentation of a silicon substrate by the nanotube is observed. Upon the nanotube withdrawal, several surface silicon atoms are adsorbed at the tip of the nanotube causing significant rearrangements of atoms comprising the surface layer of the silicon substrate. The results are explained in terms of relative strength of C-C, C-Si, and Si-Si bonds. The proposed method is very robust and does not require applied voltage between the nanotube tips and the surface. The implications of the reported controllable etching and hole-creating for nanolithography on silicon are discussed in detail.

Modifying Surface Fluctuations of Polymer Melt Films with Substrate Modification

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Yang; He, Qiming; Zhang, Fan

Deposition of a plasma polymerized film on a silicon substrate substantially changes the fluctuations on the surface of a sufficiently thin, melt polystyrene (PS) film atop the substrate. Surface fluctuation relaxation times measured with X-ray photon correlation spectroscopy (XPCS) for ca. 4R g thick melt films of 131 kg/mol linear PS on silicon and on a plasma polymer modified silicon wafer can both be described using a hydrodynamic continuum theory (HCT) that assumes the film is characterized throughout its depth by the bulk viscosity. However, when the film thickness is reduced to ~3R g, confinement effects are evident. The surfacemore » fluctuations are slower than predicted using the HCT, and the confinement effect for the PS on silicon is larger than that for the PS on the plasma polymerized film. This deviation is thus due to a difference in the thicknesses of the strongly adsorbed layers at the substrate which are impacted by the substrate surface energy.« less

Modifying Surface Fluctuations of Polymer Melt Films with Substrate Modification

DOE PAGES

Zhou, Yang; He, Qiming; Zhang, Fan; ...

2017-08-14

Deposition of a plasma polymerized film on a silicon substrate substantially changes the fluctuations on the surface of a sufficiently thin, melt polystyrene (PS) film atop the substrate. Surface fluctuation relaxation times measured with X-ray photon correlation spectroscopy (XPCS) for ca. 4R g thick melt films of 131 kg/mol linear PS on silicon and on a plasma polymer modified silicon wafer can both be described using a hydrodynamic continuum theory (HCT) that assumes the film is characterized throughout its depth by the bulk viscosity. However, when the film thickness is reduced to ~3R g, confinement effects are evident. The surfacemore » fluctuations are slower than predicted using the HCT, and the confinement effect for the PS on silicon is larger than that for the PS on the plasma polymerized film. This deviation is thus due to a difference in the thicknesses of the strongly adsorbed layers at the substrate which are impacted by the substrate surface energy.« less

Extension of the ADC Charge-Collection Model to Include Multiple Junctions

NASA Technical Reports Server (NTRS)

Edmonds, Larry D.

2011-01-01

The ADC model is a charge-collection model derived for simple p-n junction silicon diodes having a single reverse-biased p-n junction at one end and an ideal substrate contact at the other end. The present paper extends the model to include multiple junctions, and the goal is to estimate how collected charge is shared by the different junctions.

Diamond Composite Films for Protective Coatings on Metals and Method of Formation

NASA Technical Reports Server (NTRS)

Ong, Tiong P. (Inventor); Shing, Yuh-Han (Inventor)

1997-01-01

Composite films consisting of diamond crystallites and hard amorphous films such as diamond-like carbon, titanium nitride, and titanium oxide are provided as protective coatings for metal substrates against extremely harsh environments. A composite layer having diamond crystallites and a hard amorphous film is affixed to a metal substrate via an interlayer including a bottom metal silicide film and a top silicon carbide film. The interlayer is formed either by depositing metal silicide and silicon carbide directly onto the metal substrate, or by first depositing an amorphous silicon film, then allowing top and bottom portions of the amorphous silicon to react during deposition of the diamond crystallites, to yield the desired interlayer structure.

Silicon nitride films deposited with an electron beam created plasma

NASA Technical Reports Server (NTRS)

Bishop, D. C.; Emery, K. A.; Rocca, J. J.; Thompson, L. R.; Zamani, H.; Collins, G. J.

1984-01-01

The electron beam assisted chemical vapor deposition (EBCVD) of silicon nitride films using NH3, N2, and SiH4 as the reactant gases is reported. The films have been deposited on aluminum, SiO2, and polysilicon film substrates as well as on crystalline silicon substrates. The range of experimental conditions under which silicon nitrides have been deposited includes substrate temperatures from 50 to 400 C, electron beam currents of 2-40 mA, electron beam energies of 1-5 keV, total ambient pressures of 0.1-0.4 Torr, and NH3/SiH4 mass flow ratios of 1-80. The physical, electrical, and chemical properties of the EBCVD films are discussed.

Broadband angle-independent antireflection coatings on nanostructured light trapping solar cells

NASA Astrophysics Data System (ADS)

Vázquez-Guardado, Abraham; Boroumand, Javaneh; Franklin, Daniel; Chanda, Debashis

2018-03-01

Backscattering from nanostructured surfaces greatly diminishes the efficacy of light trapping solar cells. While the analytical design of broadband, angle-independent antireflection coatings on nanostructured surfaces proved inefficient, numerical optimization proves a viable alternative. Here, we numerically design and experimentally verify the performance of single and bilayer antireflection coatings on a 2D hexagonal diffractive light trapping pattern on crystalline silicon substrates. Three well-known antireflection coatings, aluminum oxide, silicon nitride, and silicon oxide, which also double as high-quality surface passivation materials, are studied in the 400-1000 nm band. By varying thickness and conformity, the optimal parameters that minimize the broadband total reflectance (specular and scattering) from the nanostructured surface are obtained. The design results in a single-layer antireflection coating with normal-angle wavelength-integrated reflectance below 4% and a bilayer antireflection coating demonstrating reflection down to 1.5%. We show experimentally an angle-averaged reflectance of ˜5.2 % up to 60° incident angle from the optimized bilayer antireflection-coated nanostructured surface, paving the path toward practical implementation of the light trapping solar cells.

Silicon Nanowire Growth at Chosen Positions and Orientations

NASA Technical Reports Server (NTRS)

Getty, Stephanie A.

2009-01-01

It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.

Micro-opto-mechanical devices and systems using epitaxial lift off

NASA Technical Reports Server (NTRS)

Camperi-Ginestet, C.; Kim, Young W.; Wilkinson, S.; Allen, M.; Jokerst, N. M.

1993-01-01

The integration of high quality, single crystal thin film gallium arsenide (GaAs) and indium phosphide (InP) based photonic and electronic materials and devices with host microstructures fabricated from materials such as silicon (Si), glass, and polymers will enable the fabrication of the next generation of micro-opto-mechanical systems (MOMS) and optoelectronic integrated circuits. Thin film semiconductor devices deposited onto arbitrary host substrates and structures create hybrid (more than one material) near-monolithic integrated systems which can be interconnected electrically using standard inexpensive microfabrication techniques such as vacuum metallization and photolithography. These integrated systems take advantage of the optical and electronic properties of compound semiconductor devices while still using host substrate materials such as silicon, polysilicon, glass and polymers in the microstructures. This type of materials optimization for specific tasks creates higher performance systems than those systems which must use trade-offs in device performance to integrate all of the function in a single material system. The low weight of these thin film devices also makes them attractive for integration with micromechanical devices which may have difficulty supporting and translating the full weight of a standard device. These thin film devices and integrated systems will be attractive for applications, however, only when the development of low cost, high yield fabrication and integration techniques makes their use economically feasible. In this paper, we discuss methods for alignment, selective deposition, and interconnection of thin film epitaxial GaAs and InP based devices onto host substrates and host microstructures.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

2003-11-04

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D [Fairfield, CA; Theiss, Steven D [Woodbury, MN; Carey, Paul G [Mountain View, CA; Smith, Patrick M [San Ramon, CA; Wickbold, Paul [Walnut Creek, CA

2006-09-26

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Ultra-localized single cell electroporation using silicon nanowires.

PubMed

Jokilaakso, Nima; Salm, Eric; Chen, Aaron; Millet, Larry; Guevara, Carlos Duarte; Dorvel, Brian; Reddy, Bobby; Karlstrom, Amelie Eriksson; Chen, Yu; Ji, Hongmiao; Chen, Yu; Sooryakumar, Ratnasingham; Bashir, Rashid

2013-02-07

Analysis of cell-to-cell variation can further the understanding of intracellular processes and the role of individual cell function within a larger cell population. The ability to precisely lyse single cells can be used to release cellular components to resolve cellular heterogeneity that might be obscured when whole populations are examined. We report a method to position and lyse individual cells on silicon nanowire and nanoribbon biological field effect transistors. In this study, HT-29 cancer cells were positioned on top of transistors by manipulating magnetic beads using external magnetic fields. Ultra-rapid cell lysis was subsequently performed by applying 600-900 mV(pp) at 10 MHz for as little as 2 ms across the transistor channel and the bulk substrate. We show that the fringing electric field at the device surface disrupts the cell membrane, leading to lysis from irreversible electroporation. This methodology allows rapid and simple single cell lysis and analysis with potential applications in medical diagnostics, proteome analysis and developmental biology studies.

Structural and interfacial defects in c-axis oriented LiNbO3 thin films grown by pulsed laser deposition on Si using Al : ZnO conducting layer

NASA Astrophysics Data System (ADS)

Shandilya, Swati; Tomar, Monika; Sreenivas, K.; Gupta, Vinay

2009-05-01

Highly c-axis oriented LiNbO3 films are deposited using pulsed laser deposition on a silicon substrate using a transparent conducting Al doped ZnO layer. X-ray diffraction and Raman spectroscopic analysis show the fabrication of single phase and oriented LiNbO3 films under the optimized deposition condition. An extra peak at 905 cm-1 was observed in the Raman spectra of LiNbO3 film deposited at higher substrate temperature and higher oxygen pressure, and attributed to the presence of niobium antisite defects in the lattice. Dielectric constant and ac conductivity of oriented LiNbO3 films deposited under the static and rotating substrate modes have been studied. Films deposited under the rotating substrate mode exhibit dielectric properties close to the LiNbO3 single crystal. The cause of deviation in the dielectric properties of the film deposited under the static substrate mode, in comparison with the bulk, are discussed in the light of the possible formation of an interdiffusion layer at the interface of the LiNbO3 film and the Al : ZnO layer.

Silicon-Germanium Films Grown on Sapphire for Ka-Band Communications Applications

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Mueller, Carl H.; Croke, Edward T.

2004-01-01

NASA's vision in the space communications area is to develop a broadband data network in which there is a high degree of interconnectivity among the various satellite systems, ground stations, and wired systems. To accomplish this goal, we will need complex electronic circuits integrating analog and digital data handling at the Ka-band (26 to 40 GHz). The purpose of this project is to show the feasibility of a new technology for Ka-band communications applications, namely silicon germanium (SiGe) on sapphire. This new technology will have several advantages in comparison to the existing silicon-substrate- based circuits. The main advantages are extremely low parasitic reactances that enable much higher quality active and passive components, better device isolation, higher radiation tolerance, and the integration of digital and analog circuitry on a single chip.

YBa2Cu307 superconducting microbolometer linear arrays

NASA Astrophysics Data System (ADS)

Johnson, Burgess R.; Ohnstein, Thomas R.; Marsh, Holly A.; Dunham, Scott B.; Kruse, Paul W.

1992-09-01

Single pixels and linear arrays of microbolometers employing the high-T(subscript c) superconductor YBa(subscript 2)Cu(subscript 3)O(subscript 7) have been fabricated by silicon micromachining techniques. The substrates are 3 in. diameter silicon wafers upon which buffer layers of Si(subscript 3)N(subscript 4) and yttria-stabilized zirconia (YSZ) have been deposited. The YBa(subscript 2)Cu(subscript 3)O(subscript 7) was deposited by ion beam sputtering upon the yttria-stabilized zirconia (YSZ), then photolithographically patterned into serpentines 4 micrometers wide. Anisotropic etching in KOH removed the silicon underlying each pixel, thereby providing the necessary thermal isolation. When operated at 70 degree(s)K with 1 (mu) A dc bias, the D(superscript *) is 7.5 X 10(superscript 8) cm Hz(superscript 1/2)/Watt with a thermal response time of 24 msec.

Formation of porous silicon oxide from substrate-bound silicon rich silicon oxide layers by continuous-wave laser irradiation

NASA Astrophysics Data System (ADS)

Wang, Nan; Fricke-Begemann, Th.; Peretzki, P.; Ihlemann, J.; Seibt, M.

2018-03-01

Silicon nanocrystals embedded in silicon oxide that show room temperature photoluminescence (PL) have great potential in silicon light emission applications. Nanocrystalline silicon particle formation by laser irradiation has the unique advantage of spatially controlled heating, which is compatible with modern silicon micro-fabrication technology. In this paper, we employ continuous wave laser irradiation to decompose substrate-bound silicon-rich silicon oxide films into crystalline silicon particles and silicon dioxide. The resulting microstructure is studied using transmission electron microscopy techniques with considerable emphasis on the formation and properties of laser damaged regions which typically quench room temperature PL from the nanoparticles. It is shown that such regions consist of an amorphous matrix with a composition similar to silicon dioxide which contains some nanometric silicon particles in addition to pores. A mechanism referred to as "selective silicon ablation" is proposed which consistently explains the experimental observations. Implications for the damage-free laser decomposition of silicon-rich silicon oxides and also for controlled production of porous silicon dioxide films are discussed.

Galvanic displacement reaction and rapid thermal annealing in size/shape controlling silver nanoparticles on silicon substrate

NASA Astrophysics Data System (ADS)

Ghosh, Tapas; Satpati, Biswarup

2017-05-01

The effect of the thermal annealing on silver nanoparticles deposited on silicon surface has been studied. The silver nanoparticles have been deposited by the galvanic displacement reaction. Rapid thermal annealing (RTA) has been performed on the Si substrate, containing the silver nanoparticles. The scanning transmission electron microscopy (STEM), energy dispersive X-ray (EDX) spectroscopy and scanning electron microscopy (SEM) study show that the galvanic displacement reaction and subsequent rapid thermal annealing could lead to well separated and spherical shaped larger silver nanoparticles on silicon substrate.

Development of refractory armored silicon carbide by infrared transient liquid phase processing

NASA Astrophysics Data System (ADS)

Hinoki, Tatsuya; Snead, Lance L.; Blue, Craig A.

2005-12-01

Tungsten (W) and molybdenum (Mo) were coated on silicon carbide (SiC) for use as a refractory armor using a high power plasma arc lamp at powers up to 23.5 MW/m 2 in an argon flow environment. Both tungsten powder and molybdenum powder melted and formed coating layers on silicon carbide within a few seconds. The effect of substrate pre-treatment (vapor deposition of titanium (Ti) and tungsten, and annealing) and sample heating conditions on microstructure of the coating and coating/substrate interface were investigated. The microstructure was observed by scanning electron microscopy (SEM) and optical microscopy (OM). The mechanical properties of the coated materials were evaluated by four-point flexural tests. A strong tungsten coating was successfully applied to the silicon carbide substrate. Tungsten vapor deposition and pre-heating at 5.2 MW/m 2 made for a refractory layer containing no cracks propagating into the silicon carbide substrate. The tungsten coating was formed without the thick reaction layer. For this study, small tungsten carbide grains were observed adjacent to the interface in all conditions. In addition, relatively large, widely scattered tungsten carbide grains and a eutectic structure of tungsten and silicon were observed through the thickness in the coatings formed at lower powers and longer heating times. The strength of the silicon carbide substrate was somewhat decreased as a result of the processing. Vapor deposition of tungsten prior to powder coating helped prevent this degradation. In contrast, molybdenum coating was more challenging than tungsten coating due to the larger coefficient of thermal expansion (CTE) mismatch as compared to tungsten and silicon carbide. From this work it is concluded that refractory armoring of silicon carbide by Infrared Transient Liquid Phase Processing is possible. The tungsten armored silicon carbide samples proved uniform, strong, and capable of withstanding thermal fatigue testing.

Improving performance of Si/CdS micro-/nanoribbon p-n heterojunction light emitting diodes by trenched structure

NASA Astrophysics Data System (ADS)

Huang, Shiyuan; Wu, Yuanpeng; Ma, Xiangyang; Yang, Zongyin; Liu, Xu; Yang, Qing

2018-05-01

Realizing high performance silicon based light sources has been an unremitting pursuit for researchers. In this letter, we propose a simple structure to enhance electroluminescence emission and reduce the threshold of injected current of silicon/CdS micro-/nanoribbon p-n heterojunction visible light emitting diodes, by fabricating trenched structure on silicon substrate to mount CdS micro-/nanoribbon. A series of experiments and simulation analysis favors the rationality and validity of our mounting design. After mounting the CdS micro-/nanoribbon, the optical field confinement increases, and absorption and losses from high refractive silicon substrate are effectively reduced. Meanwhile the sharp change of silicon substrate near heterojunction also facilitates the balance between electron current and hole current, which substantially conduces to the stable amplification of electroluminescence emission in CdS micro-/nanoribbon.

High spatial resolution mapping of surface plasmon resonance modes in single and aggregated gold nanoparticles assembled on DNA strands

NASA Astrophysics Data System (ADS)

Diaz-Egea, Carlos; Sigle, Wilfried; van Aken, Peter A.; Molina, Sergio I.

2013-07-01

We present the mapping of the full plasmonic mode spectrum for single and aggregated gold nanoparticles linked through DNA strands to a silicon nitride substrate. A comprehensive analysis of the electron energy loss spectroscopy images maps was performed on nanoparticles standing alone, dimers, and clusters of nanoparticles. The experimental results were confirmed by numerical calculations using the Mie theory and Gans-Mie theory for solving Maxwell's equations. Both bright and dark surface plasmon modes have been unveiled.

Influence of residual stress on the adhesion and surface morphology of PECVD-coated polypropylene

NASA Astrophysics Data System (ADS)

Jaritz, Montgomery; Hopmann, Christian; Behm, Henrik; Kirchheim, Dennis; Wilski, Stefan; Grochla, Dario; Banko, Lars; Ludwig, Alfred; Böke, Marc; Winter, Jörg; Bahre, Hendrik; Dahlmann, Rainer

2017-11-01

The properties of plasma-enhanced chemical vapour deposition (PECVD) coatings on polymer materials depend to some extent on the surface and material properties of the substrate. Here, isotactic polypropylene (PP) substrates are coated with silicon oxide (SiO x ) films. Plasmas for the deposition of SiO x are energetic and oxidative due to the high amount of oxygen in the gas mixture. Residual stress measurements using single Si cantilever stress sensors showed that these coatings contain high compressive stress. To investigate the influence of the plasma and the coatings, residual stress, silicon organic (SiOCH) coatings with different thicknesses between the PP and the SiO x coating are used as a means to protect the substrate from the oxidative SiO x coating process. Pull-off tests are performed to analyse differences in the adhesion of these coating systems. It could be shown that the adhesion of the PECVD coatings on PP depends on the coatings’ residual stress. In a PP/SiOCH/SiO x -multilayer system the residual stress can be significantly reduced by increasing the thickness of the SiOCH coating, resulting in enhanced adhesion.

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2007-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Coated silicon comprising material for protection against environmental corrosion

NASA Technical Reports Server (NTRS)

Hazel, Brian Thomas (Inventor)

2009-01-01

In accordance with an embodiment of the invention, an article is disclosed. The article comprises a gas turbine engine component substrate comprising a silicon material; and an environmental barrier coating overlying the substrate, wherein the environmental barrier coating comprises cerium oxide, and the cerium oxide reduces formation of silicate glass on the substrate upon exposure to corrodant sulfates.

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy (Inventor)

2011-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Enhanced optical output power of InGaN/GaN light-emitting diodes grown on a silicon (111) substrate with a nanoporous GaN layer.

PubMed

Lee, Kwang Jae; Chun, Jaeyi; Kim, Sang-Jo; Oh, Semi; Ha, Chang-Soo; Park, Jung-Won; Lee, Seung-Jae; Song, Jae-Chul; Baek, Jong Hyeob; Park, Seong-Ju

2016-03-07

We report the growth of InGaN/GaN multiple quantum wells blue light-emitting diodes (LEDs) on a silicon (111) substrate with an embedded nanoporous (NP) GaN layer. The NP GaN layer is fabricated by electrochemical etching of n-type GaN on the silicon substrate. The crystalline quality of crack-free GaN grown on the NP GaN layer is remarkably improved and the residual tensile stress is also decreased. The optical output power is increased by 120% at an injection current of 20 mA compared with that of conventional LEDs without a NP GaN layer. The large enhancement of optical output power is attributed to the reduction of threading dislocation, effective scattering of light in the LED, and the suppression of light propagation into the silicon substrate by the NP GaN layer.

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, V.K.

1990-08-21

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications is disclosed. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al[sub x]N[sub y]O[sub z] layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al[sub x]N[sub y]O[sub z] layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, Vinod K.

1990-01-01

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al.sub.x N.sub.y O.sub.z layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al.sub.x N.sub.y O.sub.z layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Bio-inspired silicon nanospikes fabricated by metal-assisted chemical etching for antibacterial surfaces

NASA Astrophysics Data System (ADS)

Hu, Huan; Siu, Vince S.; Gifford, Stacey M.; Kim, Sungcheol; Lu, Minhua; Meyer, Pablo; Stolovitzky, Gustavo A.

2017-12-01

The recently discovered bactericidal properties of nanostructures on wings of insects such as cicadas and dragonflies have inspired the development of similar nanostructured surfaces for antibacterial applications. Since most antibacterial applications require nanostructures covering a considerable amount of area, a practical fabrication method needs to be cost-effective and scalable. However, most reported nanofabrication methods require either expensive equipment or a high temperature process, limiting cost efficiency and scalability. Here, we report a simple, fast, low-cost, and scalable antibacterial surface nanofabrication methodology. Our method is based on metal-assisted chemical etching that only requires etching a single crystal silicon substrate in a mixture of silver nitrate and hydrofluoric acid for several minutes. We experimentally studied the effects of etching time on the morphology of the silicon nanospikes and the bactericidal properties of the resulting surface. We discovered that 6 minutes of etching results in a surface containing silicon nanospikes with optimal geometry. The bactericidal properties of the silicon nanospikes were supported by bacterial plating results, fluorescence images, and scanning electron microscopy images.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Formation and investigation of ultrathin layers of Co2FeSi ferromagnetic alloy synthesized on silicon covered with a CaF2 barrier layer

NASA Astrophysics Data System (ADS)

Grebenyuk, G. S.; Gomoyunova, M. V.; Pronin, I. I.; Vyalikh, D. V.; Molodtsov, S. L.

2016-03-01

Ultrathin (∼2 nm) films of Co2FeSi ferromagnetic alloy were formed on silicon by solid-phase epitaxy and studied in situ. Experiments were carried out in an ultrahigh vacuum (UHV) using substrates of Si(1 1 1) single crystals covered with a 5 nm thick CaF2 barrier layer. The elemental and phase composition as well as the magnetic properties of the synthesized films were analyzed by photoelectron spectroscopy using synchrotron radiation and by magnetic linear dichroism in photoemission of Fe 3p and Co 3p electrons. The study shows that the synthesis of the Co2FeSi ferromagnetic alloy occurs in the temperature range of 200-400 °C. At higher temperatures, the films become island-like and lose their ferromagnetic properties, as the CaF2 barrier layer is unable to prevent a mass transfer between the film and the Si substrate, which violates the stoichiometry of the alloy.

Thin-film piezoelectric-on-silicon resonators for high-frequency reference oscillator applications.

PubMed

Abdolvand, Reza; Lavasani, Hossein M; Ho, Gavin K; Ayazi, Farrokh

2008-12-01

This paper studies the application of lateral bulk acoustic thin-film piezoelectric-on-substrate (TPoS) resonators in high-frequency reference oscillators. Low-motional-impedance TPoS resonators are designed and fabricated in 2 classes--high-order and coupled-array. Devices of each class are used to assemble reference oscillators and the performance characteristics of the oscillators are measured and discussed. Since the motional impedance of these devices is small, the transimpedance amplifier (TIA) in the oscillator loop can be reduced to a single transistor and 3 resistors, a format that is very power-efficient. The lowest reported power consumption is approximately 350 microW for an oscillator operating at approximately 106 MHz. A passive temperature compensation method is also utilized by including the buried oxide layer of the silicon-on-insulator (SOI) substrate in the structural resonant body of the device, and a very small (-2.4 ppm/ degrees C) temperature coefficient of frequency is obtained for an 82-MHz oscillator.

Graphene as a Buffer Layer for Silicon Carbide-on-Insulator Structures

PubMed Central

Astuti, Budi; Tanikawa, Masahiro; Rahman, Shaharin Fadzli Abd; Yasui, Kanji; Hashim, Abdul Manaf

2012-01-01

We report an innovative technique for growing the silicon carbide-on-insulator (SiCOI) structure by utilizing polycrystalline single layer graphene (SLG) as a buffer layer. The epitaxial growth was carried out using a hot-mesh chemical vapor deposition (HM-CVD) technique. Cubic SiC (3C-SiC) thin film in (111) domain was realized at relatively low substrate temperature of 750 °C. 3C-SiC energy bandgap of 2.2 eV was confirmed. The Si-O absorption band observed in the grown film can be caused by the out-diffusion of the oxygen atom from SiO2 substrate or oxygen doping during the cleaning process. Further experimental works by optimizing the cleaning process, growth parameters of the present growth method, or by using other growth methods, as well, are expected to realize a high quality SiCOI structure, thereby opening up the way for a breakthrough in the development of advanced ULSIs with multifunctionalities.

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

NASA Astrophysics Data System (ADS)

Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

2018-02-01

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

Thin-film magnetless Faraday rotators for compact heterogeneous integrated optical isolators

NASA Astrophysics Data System (ADS)

Karki, Dolendra; Stenger, Vincent; Pollick, Andrea; Levy, Miguel

2017-06-01

This report describes the fabrication, characterization, and transfer of ultra-compact thin-film magnetless Faraday rotators to silicon photonic substrates. Thin films of magnetization latching bismuth-substituted rare-earth iron garnets were produced from commercially available materials by mechanical lapping, dice polishing, and crystal-ion-slicing. Eleven- μ m -thick films were shown to retain the 45 ° Faraday rotation of the bulk material to within 2 ° at 1.55 μ m wavelength without re-poling. Anti-reflection coated films evince 0.09 dB insertion loses and better than -20 dB extinction ratios. Lower extinction ratios than the bulk are ascribed to multimode propagation. Significantly larger extinction ratios are predicted for single-mode waveguides. Faraday rotation, extinction ratios, and insertion loss tests on He-ion implanted slab waveguides of the same material yielded similar results. The work culminated with bond alignment and transfer of 7 μ m -thick crystal-ion-sliced 50 × 480 μ m 2 films onto silicon photonic substrates.

Study on Silicon Microstructure Processing Technology Based on Porous Silicon

NASA Astrophysics Data System (ADS)

Shang, Yingqi; Zhang, Linchao; Qi, Hong; Wu, Yalin; Zhang, Yan; Chen, Jing

2018-03-01

Aiming at the heterogeneity of micro - sealed cavity in silicon microstructure processing technology, the technique of preparing micro - sealed cavity of porous silicon is proposed. The effects of different solutions, different substrate doping concentrations, different current densities, and different etching times on the rate, porosity, thickness and morphology of the prepared porous silicon were studied. The porous silicon was prepared by different process parameters and the prepared porous silicon was tested and analyzed. For the test results, optimize the process parameters and experiments. The experimental results show that the porous silicon can be controlled by optimizing the parameters of the etching solution and the doping concentration of the substrate, and the preparation of porous silicon with different porosity can be realized by different doping concentration, so as to realize the preparation of silicon micro-sealed cavity, to solve the sensor sensitive micro-sealed cavity structure heterogeneous problem, greatly increasing the application of the sensor.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon.

PubMed

Ben Slama, Sonia; Hajji, Messaoud; Ezzaouia, Hatem

2012-08-17

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon

PubMed Central

2012-01-01

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications. PMID:22901341

Silver-free solar cell interconnection by laser spot welding of thin aluminum layers: analysis of process limits for ns- and μs-lasers

NASA Astrophysics Data System (ADS)

Schulte-Huxel, H.; Blankemeyer, S.; Kajari-Schröder, S.; Brendel, R.

2014-03-01

We investigate a laser welding process for contacting aluminum metallized crystalline silicon solar cells to a 10-μm-thick aluminum layers on a glass substrate. The reduction of the solar cell metallization thickness is analyzed with respect to laser induced damage using SiNx passivated silicon wafers. Additionally, we measure the mechanical stress of the laser welds by perpendicular tear-off as well as the electrical contact resistance. We apply two types of laser processes; one uses one to eight 20-ns-laser pulses at 355 nm with fluences between 12 and 40 J/cm2 and the other single 1.2-μs-laser pulses at 1064 nm with 33 to 73 J/cm2. Ns laser pulses can contact down to 1-μm-thick aluminum layers on silicon without inducing laser damage to the silicon and lead to sufficient strong mechanical contact. In case of μs laser pulses the limiting thickness is 2 μm.

Impacts of Post-metallisation Processes on the Electrical and Photovoltaic Properties of Si Quantum Dot Solar Cells.

PubMed

Di, Dawei; Perez-Wurfl, Ivan; Gentle, Angus; Kim, Dong-Ho; Hao, Xiaojing; Shi, Lei; Conibeer, Gavin; Green, Martin A

2010-08-01

As an important step towards the realisation of silicon-based tandem solar cells using silicon quantum dots embedded in a silicon dioxide (SiO(2)) matrix, single-junction silicon quantum dot (Si QD) solar cells on quartz substrates have been fabricated. The total thickness of the solar cell material is 420 nm. The cells contain 4 nm diameter Si quantum dots. The impacts of post-metallisation treatments such as phosphoric acid (H(3)PO(4)) etching, nitrogen (N(2)) gas anneal and forming gas (Ar: H(2)) anneal on the cells' electrical and photovoltaic properties are investigated. The Si QD solar cells studied in this work have achieved an open circuit voltage of 410 mV after various processes. Parameters extracted from dark I-V, light I-V and circular transfer length measurement (CTLM) suggest limiting mechanism in the Si QD solar cell operation and possible approaches for further improvement.

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

NASA Astrophysics Data System (ADS)

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-09-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage.

Ultracompact bottom-up photonic crystal lasers on silicon-on-insulator.

PubMed

Lee, Wook-Jae; Kim, Hyunseok; You, Jong-Bum; Huffaker, Diana L

2017-08-25

Compact on-chip light sources lie at the heart of practical nanophotonic devices since chip-scale photonic circuits have been regarded as the next generation computing tools. In this work, we demonstrate room-temperature lasing in 7 × 7 InGaAs/InGaP core-shell nanopillar array photonic crystals with an ultracompact footprint of 2300 × 2300 nm 2 , which are monolithically grown on silicon-on-insulator substrates. A strong lateral confinement is achieved by a photonic band-edge mode, which is leading to a strong light-matter interaction in the 7 × 7 nanopillar array, and by choosing an appropriate thickness of a silicon-on-insulator layer the band-edge mode can be trapped vertically in the nanopillars. The nanopillar array band-edge lasers exhibit single-mode operation, where the mode frequency is sensitive to the diameter of the nanopillars. Our demonstration represents an important first step towards developing practical and monolithic III-V photonic components on a silicon platform.

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

PubMed Central

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-01-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage. PMID:27659796

Substrate for thin silicon solar cells

DOEpatents

Ciszek, Theodore F.

1995-01-01

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1.times.10.sup.-3 ohm-cm.

Die singulation method

DOEpatents

Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.

2013-06-11

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Die singulation method

DOEpatents

Swiler, Thomas P [Albuquerque, NM; Garcia, Ernest J [Albuquerque, NM; Francis, Kathryn M [Rio Rancho, NM

2014-01-07

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with a HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon

PubMed Central

Girel, Kseniya V.; Panarin, Andrei; Terekhov, Sergei N.

2018-01-01

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy. PMID:29883382

High-speed and on-chip graphene blackbody emitters for optical communications by remote heat transfer.

PubMed

Miyoshi, Yusuke; Fukazawa, Yusuke; Amasaka, Yuya; Reckmann, Robin; Yokoi, Tomoya; Ishida, Kazuki; Kawahara, Kenji; Ago, Hiroki; Maki, Hideyuki

2018-03-29

High-speed light emitters integrated on silicon chips can enable novel architectures for silicon-based optoelectronics, such as on-chip optical interconnects, and silicon photonics. However, conventional light sources based on compound semiconductors face major challenges for their integration with a silicon-based platform because of their difficulty of direct growth on a silicon substrate. Here we report ultra-high-speed (100-ps response time), highly integrated graphene-based on-silicon-chip blackbody emitters in the near-infrared region including telecommunication wavelength. Their emission responses are strongly affected by the graphene contact with the substrate depending on the number of graphene layers. The ultra-high-speed emission can be understood by remote quantum thermal transport via surface polar phonons of the substrates. We demonstrated real-time optical communications, integrated two-dimensional array emitters, capped emitters operable in air, and the direct coupling of optical fibers to the emitters. These emitters can open new routes to on-Si-chip, small footprint, and high-speed emitters for highly integrated optoelectronics and silicon photonics.

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon.

PubMed

Bandarenka, Hanna V; Girel, Kseniya V; Zavatski, Sergey A; Panarin, Andrei; Terekhov, Sergei N

2018-05-21

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy.

Advances in silicon carbide Chemical Vapor Deposition (CVD) for semiconductor device fabrication

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Petit, Jeremy B.; Matus, Lawrence G.

1991-01-01

Improved SiC chemical vapor deposition films of both 3C and 6H polytypes were grown on vicinal (0001) 6H-SiC wafers cut from single-crystal boules. These films were produced from silane and propane in hydrogen at one atmosphere at a temperature of 1725 K. Among the more important factors which affected the structure and morphology of the grown films were the tilt angle of the substrate, the polarity of the growth surface, and the pregrowth surface treatment of the substrate. With proper pregrowth surface treatment, 6H films were grown on 6H substrates with tilt angles as small as 0.1 degrees. In addition, 3C could be induced to grow within selected regions on a 6H substrate. The polarity of the substrate was a large factor in the incorporation of dopants during epitaxial growth. A new growth model is discussed which explains the control of SiC polytype in epitaxial growth on vicinal (0001) SiC substrates.

Method for providing an arbitrary three-dimensional microstructure in silicon using an anisotropic deep etch

DOEpatents

Morales, Alfredo M.; Gonzales, Marcela

2004-06-15

The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch the silicon substrate and therefore provides the ability etch structures of variable depths.

Self-cleaning poly(dimethylsiloxane) film with functional micro/nano hierarchical structures.

PubMed

Zhang, Xiao-Sheng; Zhu, Fu-Yun; Han, Meng-Di; Sun, Xu-Ming; Peng, Xu-Hua; Zhang, Hai-Xia

2013-08-27

This paper reports a novel single-step wafer-level fabrication of superhydrophobic micro/nano dual-scale (MNDS) poly(dimethylsiloxane) (PDMS) films. The MNDS PDMS films were replicated directly from an ultralow-surface-energy silicon substrate at high temperature without any surfactant coating, achieving high precision. An improved deep reactive ion etching (DRIE) process with enhanced passivation steps was proposed to easily realize the ultralow-surface-energy MNDS silicon substrate and also utilized as a post-treatment process to strengthen the hydrophobicity of the MNDS PDMS film. The chemical modification of this enhanced passivation step to the surface energy has been studied by density functional theory, which is also the first investigation of C4F8 plasma treatment at molecular level by using first-principle calculations. From the results of a systematic study on the effect of key process parameters (i.e., baking temperature and time) on PDMS replication, insight into the interaction of hierarchical multiscale structures of polymeric materials during the micro/nano integrated fabrication process is experimentally obtained for the first time. Finite element simulation has been employed to illustrate this new phenomenon. Additionally, hierarchical PDMS pyramid arrays and V-shaped grooves have been developed and are intended for applications as functional structures for a light-absorption coating layer and directional transport of liquid droplets, respectively. This stable, self-cleaning PDMS film with functional micro/nano hierarchical structures, which is fabricated through a wafer-level single-step fabrication process using a reusable silicon mold, shows attractive potential for future applications in micro/nanodevices, especially in micro/nanofluidics.

Method for enhancing the solubility of dopants in silicon

DOEpatents

Sadigh, Babak; Lenosky, Thomas J.; De La Rubia, Tomas Diaz

2003-09-30

A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility was largely enhanced (more than 100%) by a compressive bi-axial strain, based on a size-mismatch theory since the boron atoms are smaller than the silicon atoms. It has been found that the large enhancement or mixing properties of dopants in silicon and germanium substrates is primarily governed by their, and to second order by their size-mismatch with the substrate. Further, it has been determined that the dopant solubility enhancement with strain is most effective when the charge and the size-mismatch of the impurity favor the same type of strain. Thus, the solid solubility of small p-type (e.g., boron) as well as large n-type (e.g., arsenic) dopants can be raised most dramatically by appropriate bi-axial (compressive) strain, and that solubility of a large p-type dopant (e.g, indium) in silicon will be raised due to size-mismatch with silicon, which favors tensile strain, while its negative charge prefers compressive strain, and thus the two effects counteract each other.

Temperature dependent evolution of wrinkled single-crystal silicon ribbons on shape memory polymers.

PubMed

Wang, Yu; Yu, Kai; Qi, H Jerry; Xiao, Jianliang

2017-10-25

Shape memory polymers (SMPs) can remember two or more distinct shapes, and thus can have a lot of potential applications. This paper presents combined experimental and theoretical studies on the wrinkling of single-crystal Si ribbons on SMPs and the temperature dependent evolution. Using the shape memory effect of heat responsive SMPs, this study provides a method to build wavy forms of single-crystal silicon thin films on top of SMP substrates. Silicon ribbons obtained from a Si-on-insulator (SOI) wafer are released and transferred onto the surface of programmed SMPs. Then such bilayer systems are recovered at different temperatures, yielding well-defined, wavy profiles of Si ribbons. The wavy profiles are shown to evolve with time, and the evolution behavior strongly depends on the recovery temperature. At relatively low recovery temperatures, both wrinkle wavelength and amplitude increase with time as evolution progresses. Finite element analysis (FEA) accounting for the thermomechanical behavior of SMPs is conducted to study the wrinkling of Si ribbons on SMPs, which shows good agreement with experiment. Merging of wrinkles is observed in FEA, which could explain the increase of wrinkle wavelength observed in the experiment. This study can have important implications for smart stretchable electronics, wrinkling mechanics, stimuli-responsive surface engineering, and advanced manufacturing.

Multifunctional epitaxial systems on silicon substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singamaneni, Srinivasa Rao, E-mail: ssingam@ncsu.edu; Materials Science Division, Army Research Office, Research Triangle Park, North Carolina 27709; Department of Physics, The University of Texas at El Paso, El Paso, Texas 79968

2016-09-15

Multifunctional heterostructures can exhibit a wide range of functional properties, including colossal magneto-resistance, magnetocaloric, and multiferroic behavior, and can display interesting physical phenomena including spin and charge ordering and strong spin-orbit coupling. However, putting this functionality to work remains a challenge. To date, most of the work reported in the literature has dealt with heterostructures deposited onto closely lattice matched insulating substrates such as DyScO{sub 3}, SrTiO{sub 3} (STO), or STO buffered Si(100) using concepts of lattice matching epitaxy (LME). However, strain in heterostructures grown by LME is typically not fully relaxed and the layers contain detrimental defects such asmore » threading dislocations that can significantly degrade the physical properties of the films and adversely affect the device characteristics. In addition, most of the substrates are incompatible with existing CMOS-based technology, where Si (100) substrates dominate. This review discusses recent advances in the integration of multifunctional oxide and non-oxide materials onto silicon substrates. An alternative thin film growth approach, called “domain matching epitaxy,” is presented which identifies approaches for minimizing lattice strain and unwanted defects in large misfit systems (7%–25% and higher). This approach broadly allows for the integration of multifunctional materials onto silicon substrates, such that sensing, computation, and response functions can be combined to produce next generation “smart” devices. In general, pulsed laser deposition has been used to epitaxially grow these materials, although the concepts developed here can be extended to other deposition techniques, as well. It will be shown that TiN and yttria-stabilized zirconia template layers provide promising platforms for the integration of new functionality into silicon-based computer chips. This review paper reports on a number of thin-film heterostructure systems that span a variety of ferroelectric, multiferroic, magnetic, photocatalytic, and smart materials. Their properties have been extensively investigated and their functionality found to be comparable to films grown on single-crystal oxide substrates previously reported by researchers in this field. In addition, this review explores the utility of using laser processing to introduce stable defects in a controlled way and induce magnetism and engineer the optical and electrical properties of nonmagnetic oxides such as BaTiO{sub 3}, VO{sub 2}, NiO, and TiO{sub 2} as an alternative for incorporating additional magnetic and conducting layers into the structure. These significant materials advancements herald a flurry of exciting new advances in CMOS-compatible multifunctional devices.« less

Microelectromechanical pump utilizing porous silicon

DOEpatents

Lantz, Jeffrey W [Albuquerque, NM; Stalford, Harold L [Norman, OK

2011-07-19

A microelectromechanical (MEM) pump is disclosed which includes a porous silicon region sandwiched between an inlet chamber and an outlet chamber. The porous silicon region is formed in a silicon substrate and contains a number of pores extending between the inlet and outlet chambers, with each pore having a cross-section dimension about equal to or smaller than a mean free path of a gas being pumped. A thermal gradient is provided along the length of each pore by a heat source which can be an electrical resistance heater or an integrated circuit (IC). A channel can be formed through the silicon substrate so that inlet and outlet ports can be formed on the same side of the substrate, or so that multiple MEM pumps can be connected in series to form a multi-stage MEM pump. The MEM pump has applications for use in gas-phase MEM chemical analysis systems, and can also be used for passive cooling of ICs.

Dual-Input AND Gate From Single-Channel Thin-Film FET

NASA Technical Reports Server (NTRS)

Miranda, F. A.; Pinto, N. J.; Perez, R.; Mueller, C. H.

2008-01-01

A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Polycrystalline silicon ion sensitive field effect transistors

NASA Astrophysics Data System (ADS)

Yan, F.; Estrela, P.; Mo, Y.; Migliorato, P.; Maeda, H.; Inoue, S.; Shimoda, T.

2005-01-01

We report the operation of polycrystalline silicon ion sensitive field effect transistors. These devices can be fabricated on inexpensive disposable substrates such as glass or plastics and are, therefore, promising candidates for low cost single-use intelligent multisensors. In this work we have developed an extended gate structure with a Si3N4 sensing layer. Nearly ideal pH sensitivity (54mV /pH) and stable operation have been achieved. Temperature effects have been characterized. A penicillin sensor has been fabricated by functionalizing the sensing area with penicillinase. The sensitivity to penicillin G is about 10mV/mM, in solutions with concentration lower than the saturation value, which is about 7 mM.

Selective epitaxy using the gild process

DOEpatents

Weiner, Kurt H.

1992-01-01

The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.1-x grown over silicon. Such a process may be used to manufacture small transistors that have a narrow base, heavy doping, and high gain. The narrowness allows a faster transistor, and the heavy doping reduces the resistance of the narrow layer. The process does not require high temperature annealing; therefore materials such as aluminum can be used. Furthermore, the process may be used to fabricate diodes that have a high reverse breakdown voltage and a low reverse leakage current.

Silicon nanomembranes as a means to evaluate stress evolution in deposited thin films

Treesearch

Anna M. Clausen; Deborah M. Paskiewicz; Alireza Sadeghirad; Joseph Jakes; Donald E. Savage; Donald S. Stone; Feng Liu; Max G. Lagally

2014-01-01

Thin-film deposition on ultra-thin substrates poses unique challenges because of the potential for a dynamic response to the film stress during deposition. While theoretical studies have investigated film stress related changes in bulk substrates, little has been done to learn how stress might evolve in a film growing on a compliant substrate. We use silicon...

Indium-bump-free antimonide superlattice membrane detectors on silicon substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zamiri, M., E-mail: mzamiri@chtm.unm.edu, E-mail: skrishna@chtm.unm.edu; Klein, B.; Schuler-Sandy, T.

2016-02-29

We present an approach to realize antimonide superlattices on silicon substrates without using conventional Indium-bump hybridization. In this approach, PIN superlattices are grown on top of a 60 nm Al{sub 0.6}Ga{sub 0.4}Sb sacrificial layer on a GaSb host substrate. Following the growth, the individual pixels are transferred using our epitaxial-lift off technique, which consists of a wet-etch to undercut the pixels followed by a dry-stamp process to transfer the pixels to a silicon substrate prepared with a gold layer. Structural and optical characterization of the transferred pixels was done using an optical microscope, scanning electron microscopy, and photoluminescence. The interface betweenmore » the transferred pixels and the new substrate was abrupt, and no significant degradation in the optical quality was observed. An Indium-bump-free membrane detector was then fabricated using this approach. Spectral response measurements provided a 100% cut-off wavelength of 4.3 μm at 77 K. The performance of the membrane detector was compared to a control detector on the as-grown substrate. The membrane detector was limited by surface leakage current. The proposed approach could pave the way for wafer-level integration of photonic detectors on silicon substrates, which could dramatically reduce the cost of these detectors.« less

Producing Solar Cells By Surface Preparation For Accelerated Nucleation Of Microcrystalline Silicon On Heterogeneous Substrates.

DOEpatents

Yang, Liyou; Chen, Liangfan

1998-03-24

Attractive multi-junction solar cells and single junction solar cells with excellent conversion efficiency can be produced with a microcrystalline tunnel junction, microcrystalline recombination junction or one or more microcrystalline doped layers by special plasma deposition processes which includes plasma etching with only hydrogen or other specified etchants to enhance microcrystalline growth followed by microcrystalline. nucleation with a doped hydrogen-diluted feedstock.

Lateral epitaxy of atomically sharp WSe 2/WS 2 heterojunctions on silicon dioxide substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Jianyi; Zhou, Wu; Tang, Wei

Here, in recent years, 2-D transition-metal dichalcogenides (TMDCs) have received great interests because of the broader possibilities offered by their tunable band gaps, as opposed to gapless graphene which precludes application in digital electronics. TMDCs exhibit an indirect-to-direct band gap transition at the single atomic sheet state as well as optically accessible spin degree of freedom in valleytronics.

Lateral epitaxy of atomically sharp WSe 2/WS 2 heterojunctions on silicon dioxide substrates

DOE PAGES

Chen, Jianyi; Zhou, Wu; Tang, Wei; ...

2016-09-30

Here, in recent years, 2-D transition-metal dichalcogenides (TMDCs) have received great interests because of the broader possibilities offered by their tunable band gaps, as opposed to gapless graphene which precludes application in digital electronics. TMDCs exhibit an indirect-to-direct band gap transition at the single atomic sheet state as well as optically accessible spin degree of freedom in valleytronics.

Towards substrate engineering of graphene-silicon Schottky diode photodetectors.

PubMed

Selvi, Hakan; Unsuree, Nawapong; Whittaker, Eric; Halsall, Matthew P; Hill, Ernie W; Thomas, Andrew; Parkinson, Patrick; Echtermeyer, Tim J

2018-02-15

Graphene-silicon Schottky diode photodetectors possess beneficial properties such as high responsivities and detectivities, broad spectral wavelength operation and high operating speeds. Various routes and architectures have been employed in the past to fabricate devices. Devices are commonly based on the removal of the silicon-oxide layer on the surface of silicon by wet-etching before deposition of graphene on top of silicon to form the graphene-silicon Schottky junction. In this work, we systematically investigate the influence of the interfacial oxide layer, the fabrication technique employed and the silicon substrate on the light detection capabilities of graphene-silicon Schottky diode photodetectors. The properties of devices are investigated over a broad wavelength range from near-UV to short-/mid-infrared radiation, radiation intensities covering over five orders of magnitude as well as the suitability of devices for high speed operation. Results show that the interfacial layer, depending on the required application, is in fact beneficial to enhance the photodetection properties of such devices. Further, we demonstrate the influence of the silicon substrate on the spectral response and operating speed. Fabricated devices operate over a broad spectral wavelength range from the near-UV to the short-/mid-infrared (thermal) wavelength regime, exhibit high photovoltage responses approaching 10 6 V W -1 and short rise- and fall-times of tens of nanoseconds.

Solution and interfacial behavior of modified silicone polymers and their interactions with solid substrates

NASA Astrophysics Data System (ADS)

Purohit, Parag

Surface treatment is very important step in many applications such as fabric finishing, coatings, cosmetics and personal care. Silicone polymers are a class of organic/inorganic materials that show unique properties such as weak intermolecular forces and high flexibility enabling even a very high molecular weight chain to achieve optimal orientation on surfaces. Material properties such as softness, repellency, bounciness and friction can therefore be tailored by using appropriately modified silicone polymers. Despite wide applications, the underlying mechanisms of material modification are unknown and tailoring silicones for applications remains mostly empirical. Thus the objective of this research is to understand the solution and interfacial behavior of functionalized silicone polymers, which govern their performance in material modification. Modified silicones are simultaneously hydrophobic and oleophobic in nature and due to this nearly universal non-compatibility, the studies of these polymers present unusual challenges. Due to this incompatible nature, the functionalized silicone polymers were emulsified into O/W emulsions to study their solution and interfacial properties. The colloidal properties such as electrokinetic and droplet distribution of these emulsions are assumed to play an important role in the observed surface and physical properties of solid substrates (in present study, cellulosic substrates) as well the stability of emulsions itself. To understand the effects of modified silicones on cellulosic substrates a variety of techniques such as frictional analysis, scanning electron microscopy and atomic force microscopy that can probe from macro to nano level were used. It is hypothesized that the size distribution and charge of silicone emulsions as well as the physiochemical conditions such as pH, control silicone conformation which in turn affect the modification of the substrate properties. With bimodal droplet distribution of silicone emulsions, the nano-sized droplets can penetrate deeper into the substrate to provide bounciness, whereas macro-sized droplets can coat the top layer leading to friction reduction. It was observed that at pH 5.5 the silicone treatment resulted in charge reversal of fibers as opposed to treatment at pH 9.5. On a macroscopic scale 20% reduction in frictional coefficient of the fabric was observed after treatment with quaternized (cationically modified) silicones as compared to untreated fibers. It was also observed using AFM that the fibrils treated with quaternized silicones are uniform, well stacked and smoother than the untreated fibers. Spectroscopic analysis of treated fibers using Raman spectroscopy indicated a decrease in fiber stress as a function of modification of silicone polymer and the interaction pH. It is concluded that the protonated amine functional silicone (below pH 7) as well as the quaternized silicone interacts with the negatively charged cellulose fibers primarily through electrostatic interactions. It is proposed that this initial surface coating is a uniform thin film which allows further deposition of polymer from the emulsion. It was observed that at high pH the zetapotential of silicone emulsions decreases drastically and the nano emulsions turn turbid. It is proposed that the observed electrophoretic and nephelometric behavior at high pH is due to flocculation of nanosized droplets to micron size, which eventually leads to droplets coalescing and emulsion destabilization. It is also postulated that the nano emulsion possess a critical dilution concentration (CDC), above which dilution leads to rapid coalescence. This critical dilution phase was further confirmed through polarity parameter and excimer formation studies which show significantly different polymer and surfactant microstructures near the CDC. Hence it is concluded that the observed surface properties of the substrate obtained above the CDC are significantly different than those below the CDC. The results reveal the vital role of physiochemical parameters such as pH, droplet size, and concentration on the emulsion stability as well as the observed physical/chemical properties of the substrates.

Substrate for thin silicon solar cells

DOEpatents

Ciszek, T.F.

1995-03-28

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1{times}10{sup {minus}3} ohm-cm. 4 figures.

Measured Propagation Characteristics of Finite Ground Coplanar Waveguide on Silicon with a Thick Polyimide Interface Layer

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Papapolymerou, John; Tentzeris, Emmanouil M.; Williams, W. O. (Technical Monitor)

2002-01-01

Measured propagation characteristics of Finite Ground Coplanar (FGC) waveguide on silicon substrates with resistivities spanning 3 orders of magnitude (0.1 to 15.5 Ohm cm) and a 20 micron thick polyimide interface layer is presented as a function of the FGC geometry. Results show that there is an optimum FGC geometry for minimum loss, and silicon with a resistivity of 0.1 Ohm cm has greater loss than substrates with higher and lower resistivity. Lastly, substrates with a resistivity of 10 Ohm cm or greater have acceptable loss.

Silicon-integrated thin-film structure for electro-optic applications

DOEpatents

McKee, Rodney A.; Walker, Frederick Joseph

2000-01-01

A crystalline thin-film structure suited for use in any of an number of electro-optic applications, such as a phase modulator or a component of an interferometer, includes a semiconductor substrate of silicon and a ferroelectric, optically-clear thin film of the perovskite BaTiO.sub.3 overlying the surface of the silicon substrate. The BaTiO.sub.3 thin film is characterized in that substantially all of the dipole moments associated with the ferroelectric film are arranged substantially parallel to the surface of the substrate to enhance the electro-optic qualities of the film.

Coated article and method of making

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Lee, Kang Neung (Inventor)

2003-01-01

An article includes a silicon-containing substrate and a modified mullite coating. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating. The article can further comprise a thermal barrier coating applied to the modified mullite coating. The modified mullite coating functions as a bond coating between the external environmental/thermal barrier coating and the silicon-containing substrate. In a method of forming an article, a silicon-containing substrate is formed and a modified mullite coating is applied. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating.

Coated article and method of making

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Lee, Kang Neung (Inventor)

2002-01-01

An article includes a silicon-containing substrate and a modified mullite coating. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating. The article can further comprise a thermal barrier coating applied to the modified mullite coating. The modified mullite coating functions as a bond coating between the external environmental/thermal barrier coating and the silicon-containing substrate. In a method of forming an article, a silicon-containing substrate is formed and a modified mullite coating is applied. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating.

RF Transmission Lines on Silicon Substrates

NASA Technical Reports Server (NTRS)

Ponchak, George E.

1999-01-01

A review of RF transmission lines on silicon substrates is presented. Through measurements and calculated results, it is shown that attenuation is dominated by conductor loss if silicon substrates with a resistivity greater than 2500 Ohm-cm are used. Si passivation layers affect the transmission line attenuation; however, measured results demonstrate that passivation layers do not necessarily increase attenuation. If standard, low resistivity Si wafers must be used, alternative transmission lines such as thin film microstrip and Co-Planar Waveguide (CPW) on thick polyimide layers must be used. Measured results presented here show that low loss per unit length is achievable with these transmission lines.

The processes of formation and epitaxial alignment of SrTiO3 thin films prepared by metallo-organic decomposition

NASA Astrophysics Data System (ADS)

Braunstein, G.; Paz-Pujalt, G. R.; Mason, M. G.; Blanton, T.; Barnes, C. L.; Margevich, D.

1993-01-01

The processes of formation and crystallization of thin films of SrTiO3 prepared by the method of metallo-organic decomposition have been studied with particular emphasis on the relationship between the thermal decomposition of the metallo-organic precursors and the eventual epitaxial alignment of the crystallized films. The films are deposited by spin coating onto single-crystalline silicon and SrTiO3 substrates, pyrolyzed on a hot plate at temperatures ranging from 200 to 450 °C, and subsequently heat treated in a quartz tube furnace at temperatures ranging from 300 to 1200 °C. Heat treatment at temperatures up to 450-500 °C results in the evaporation of solvents and other organic addenda, thermal decomposition of the metallo-organic (primarily metal-carboxylates) precursors, and formation of a carbonate species. This carbonate appears to be an intermediate phase in the reaction of SrCO3 and TiO2 to form SrTiO3. Relevant to this work is the fact that the carbonate species exhibits diffraction lines, indicating the formation of grains that can serve as seeds for the nucleation and growth of randomly oriented SrTiO3 crystallites, thereby leading to a polycrystalline film. Deposition on silicon substrates indeed results in the formation of polycrystalline SrTiO3. However, when the precursor solution is deposited on single-crystalline SrTiO3 substrates, the crystallization process involves a competition between two mechanisms: the random nucleation and growth of crystallites just described, and layer-by-layer solid phase epitaxy. Epitaxial alignment on SrTiO3 substrates can be achieved when the samples are heat treated at temperatures of 1100-1200 °C or at temperatures as low as 600-650 °C when the substrate is heated to about 1100 °C before spin coating.

Charge-coupled device for low background observations

NASA Technical Reports Server (NTRS)

Loh, Edwin D. (Inventor); Cheng, Edward S. (Inventor)

2002-01-01

A charge-coupled device with a low-emissivity metal layer located between a sensing layer and a substrate provides reduction in ghost images. In a typical charge-coupled device of a silicon sensing layer, a silicon dioxide insulating layer, with a glass substrate and a metal carrier layer, a near-infrared photon, not absorbed in the first pass, enters the glass substrate, reflects from the metal carrier, thereby returning far from the original pixel in its entry path. The placement of a low-emissivity metal layer between the glass substrate and the sensing layer reflects near infrared photons before they reach the substrate so that they may be absorbed in the silicon nearer the pixel of their points of entry so that the reflected ghost image is coincident with the primary image for a sharper, brighter image.

Hybrid III-V/silicon lasers

NASA Astrophysics Data System (ADS)

Kaspar, P.; Jany, C.; Le Liepvre, A.; Accard, A.; Lamponi, M.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Shen, A.; Charbonnier, P.; Mallecot, F.; Duan, G.-H.; Gentner, J.-.; Fedeli, J.-M.; Olivier, S.; Descos, A.; Ben Bakir, B.; Messaoudene, S.; Bordel, D.; Malhouitre, S.; Kopp, C.; Menezo, S.

2014-05-01

The lack of potent integrated light emitters is one of the bottlenecks that have so far hindered the silicon photonics platform from revolutionizing the communication market. Photonic circuits with integrated light sources have the potential to address a wide range of applications from short-distance data communication to long-haul optical transmission. Notably, the integration of lasers would allow saving large assembly costs and reduce the footprint of optoelectronic products by combining photonic and microelectronic functionalities on a single chip. Since silicon and germanium-based sources are still in their infancy, hybrid approaches using III-V semiconductor materials are currently pursued by several research laboratories in academia as well as in industry. In this paper we review recent developments of hybrid III-V/silicon lasers and discuss the advantages and drawbacks of several integration schemes. The integration approach followed in our laboratory makes use of wafer-bonded III-V material on structured silicon-on-insulator substrates and is based on adiabatic mode transfers between silicon and III-V waveguides. We will highlight some of the most interesting results from devices such as wavelength-tunable lasers and AWG lasers. The good performance demonstrates that an efficient mode transfer can be achieved between III-V and silicon waveguides and encourages further research efforts in this direction.

Fabrication and characterization of multi-stopband Fabry-Pérot filter array for nanospectrometers in the VIS range using SCIL nanoimprint technology

NASA Astrophysics Data System (ADS)

Shen, Yannan; Istock, André; Zaman, Anik; Woidt, Carsten; Hillmer, Hartmut

2018-05-01

Miniaturization of optical spectrometers can be achieved by Fabry-Pérot (FP) filter arrays. Each FP filter consists of two parallel highly reflecting mirrors and a resonance cavity in between. Originating from different individual cavity heights, each filter transmits a narrow spectral band (transmission line) with different wavelengths. Considering the fabrication efficiency, plasma enhanced chemical vapor deposition (PECVD) technology is applied to implement the high-optical-quality distributed Bragg reflectors (DBRs), while substrate conformal imprint lithography (one type of nanoimprint technology) is utilized to achieve the multiple cavities in just a single step. The FP filter array fabricated by nanoimprint combined with corresponding detector array builds a so-called "nanospectrometer". However, the silicon nitride and silicon dioxide stacks deposited by PECVD result in a limited stopband width of DBR (i.e., < 100 nm), which then limits the sensing range of filter arrays. However, an extension of the spectral range of filter arrays is desired and the topic of this investigation. In this work, multiple DBRs with different central wavelengths (λ c) are structured, deposited, and combined on a single substrate to enlarge the entire stopband. Cavity arrays are successfully aligned and imprinted over such terrace like surface in a single step. With this method, small chip size of filter arrays can be preserved, and the fabrication procedure of multiple resonance cavities is kept efficient as well. The detecting range of filter arrays is increased from roughly 50 nm with single DBR to 163 nm with three different DBRs.

Toward three-dimensional microelectronic systems: directed self-assembly of silicon microcubes via DNA surface functionalization.

PubMed

Lämmerhardt, Nico; Merzsch, Stephan; Ledig, Johannes; Bora, Achyut; Waag, Andreas; Tornow, Marc; Mischnick, Petra

2013-07-02

The huge and intelligent processing power of three-dimensional (3D) biological "processors" like the human brain with clock speeds of only 0.1 kHz is an extremely fascinating property, which is based on a massively parallel interconnect strategy. Artificial silicon microprocessors are 7 orders of magnitude faster. Nevertheless, they do not show any indication of intelligent processing power, mostly due to their very limited interconnectivity. Massively parallel interconnectivity can only be realized in three dimensions. Three-dimensional artificial processors would therefore be at the root of fabricating artificially intelligent systems. A first step in this direction would be the self-assembly of silicon based building blocks into 3D structures. We report on the self-assembly of such building blocks by molecular recognition, and on the electrical characterization of the formed assemblies. First, planar silicon substrates were functionalized with self-assembling monolayers of 3-aminopropyltrimethoxysilane for coupling of oligonucleotides (single stranded DNA) with glutaric aldehyde. The oligonucleotide immobilization was confirmed and quantified by hybridization with fluorescence-labeled complementary oligonucleotides. After the individual processing steps, the samples were analyzed by contact angle measurements, ellipsometry, atomic force microscopy, and fluorescence microscopy. Patterned DNA-functionalized layers were fabricated by microcontact printing (μCP) and photolithography. Silicon microcubes of 3 μm edge length as model objects for first 3D self-assembly experiments were fabricated out of silicon-on-insulator (SOI) wafers by a combination of reactive ion etching (RIE) and selective wet etching. The microcubes were then surface-functionalized using the same protocol as on planar substrates, and their self-assembly was demonstrated both on patterned silicon surfaces (88% correctly placed cubes), and to cube aggregates by complementary DNA functionalization and hybridization. The yield of formed aggregates was found to be about 44%, with a relative fraction of dimers of some 30%. Finally, the electrical properties of the formed dimers were characterized using probe tips inside a scanning electron microscope.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Comparative study of initial stages of copper immersion deposition on bulk and porous silicon

NASA Astrophysics Data System (ADS)

Bandarenka, Hanna; Prischepa, Sergey L.; Fittipaldi, Rosalba; Vecchione, Antonio; Nenzi, Paolo; Balucani, Marco; Bondarenko, Vitaly

2013-02-01

Initial stages of Cu immersion deposition in the presence of hydrofluoric acid on bulk and porous silicon were studied. Cu was found to deposit both on bulk and porous silicon as a layer of nanoparticles which grew according to the Volmer-Weber mechanism. It was revealed that at the initial stages of immersion deposition, Cu nanoparticles consisted of crystals with a maximum size of 10 nm and inherited the orientation of the original silicon substrate. Deposited Cu nanoparticles were found to be partially oxidized to Cu2O while CuO was not detected for all samples. In contrast to porous silicon, the crystal orientation of the original silicon substrate significantly affected the sizes, density, and oxidation level of Cu nanoparticles deposited on bulk silicon.

Process for Polycrystalline film silicon growth

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2001-01-01

A process for depositing polycrystalline silicon on substrates, including foreign substrates, occurs in a chamber at about atmospheric pressure, wherein a temperature gradient is formed, and both the atmospheric pressure and the temperature gradient are maintained throughout the process. Formation of a vapor barrier within the chamber that precludes exit of the constituent chemicals, which include silicon, iodine, silicon diiodide, and silicon tetraiodide. The deposition occurs beneath the vapor barrier. One embodiment of the process also includes the use of a blanketing gas that precludes the entrance of oxygen or other impurities. The process is capable of repetition without the need to reset the deposition zone conditions.

Laser desorption ionization and peptide sequencing on laser induced silicon microcolumn arrays

DOEpatents

Vertes, Akos [Reston, VA; Chen, Yong [San Diego, CA

2011-12-27

The present invention provides a method of producing a laser-patterned silicon surface, especially silicon wafers for use in laser desorption ionization (LDI-MS) (including MALDI-MS and SELDI-MS), devices containing the same, and methods of testing samples employing the same. The surface is prepared by subjecting a silicon substrate to multiple laser shots from a high-power picosecond or femtosecond laser while in a processing environment, e.g., underwater, and generates a remarkable homogenous microcolumn array capable of providing an improved substrate for LDI-MS.

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE PAGES

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff; ...

2015-08-20

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

Fully CMOS-compatible titanium nitride nanoantennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Briggs, Justin A., E-mail: jabriggs@stanford.edu; Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305; Naik, Gururaj V.

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements onmore » plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.« less

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

Detector and energy analyzer for energetic-hydrogen in beams and plasmas

DOEpatents

Bastasz, R.J.; Hughes, R.C.; Wampler, W.R.

1988-11-01

A detector for detecting energetic hydrogen ions and atoms ranging in energy from about 1 eV up to 1 keV in an evacuated environment includes a Schottky diode with a palladium or palladium-alloy gate metal applied to a silicon-dioxide layer on an n-silicon substrate. An array of the energetic-hydrogen detectors having a range of energy sensitivities form a plasma energy analyzer having a rapid response time and a sensitivity for measuring fluxes of energetic hydrogen. The detector is sensitive to hydrogen and its isotopes but is insensitive to non-hydrogenic particles. The array of energetic-hydrogen detectors can be formed on a single silicon chip, with thin-film layers of gold metal applied in various thicknesses to successive detectors in the array. The gold layers serve as particle energy-filters so that each detector is sensitive to a different range of hydrogen energies. 4 figs.

X-ray reflectometry and simulation of the parameters of SiC epitaxial films on Si(111), grown by the atomic substitution method

NASA Astrophysics Data System (ADS)

Kukushkin, S. A.; Nussupov, K. Kh.; Osipov, A. V.; Beisenkhanov, N. B.; Bakranova, D. I.

2017-05-01

The structure and composition of SiC nanolayers are comprehensively studied by X-ray reflectometry, IR-spectroscopy, and atomic-force microscopy (AFM) methods for the first time. SiC films were synthesized by the new method of topochemical substitution of substrate atoms at various temperatures and pressure of CO active gas on the surface of high-resistivity low-dislocation single-crystal n-type silicon (111). Based on an analysis and generalization of experimental data obtained using X-ray reflectometry, IR spectroscopy, and AFM methods, a structural model of SiC films on Si was proposed. According to this model, silicon carbide film consists of a number of layers parallel to the substrate, reminiscent of a layer cake. The composition and thickness of each layer entering the film structure is experimentally determined. It was found that all samples contain superstoichiometric carbon; however, its structure is significantly different for the samples synthesized at temperatures of 1250 and 1330°C, respectively. In the former case, the film surface is saturated with silicon vacancies and carbon in the structurally loose form reminiscent of HOPG carbon. In the films grown at 1330°C, carbon is in a dense structure with a close-to-diamond density.

High-T(sub c) Edge-geometry SNS Weak Links on Silicon-on-sapphire Substrates

NASA Technical Reports Server (NTRS)

Hunt, B.; Foote, M.; Pike, W.; Barner, J.; Vasquez, R.

1994-01-01

High-quality superconductor/normal-metal/superconductor(SNS) edge-geometry weak links have been produced on silicon-on-sapphire (SOS) substrates using a new SrTiO(sub 3)/'seed layer'/cubic-zirconia (YS2) buffer system.

Electron beam recrystallization of amorphous semiconductor materials

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.

1968-01-01

Nucleation and growth of crystalline films of silicon, germanium, and cadmium sulfide on substrates of plastic and glass were investigated. Amorphous films of germanium, silicon, and cadmium sulfide on amorphous substrates of glass and plastic were converted to the crystalline condition by electron bombardment.

Suppression effect of silicon (Si) on Er{sup 3+} 1.54μm excitation in ZnO thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu, Bo; Lu, Fei, E-mail: lufei@sdu.edu.cn; Fan, Ranran

2016-08-15

We have investigated the photoluminescence (PL) characteristics of ZnO:Er thin films on Si (100) single crystal and SiO{sub 2}-on-silicon (SiO{sub 2}) substrates, synthesized by radio frequency magnetron sputtering. Rutherford backscattering/channeling spectrometry (RBS), X-ray diffraction (XRD) and atomic force microscope (AFM) were used to analyze the properties of thin films. The diffusion depth profiles of Si were determined by second ion mass spectrometry (SIMS). Infrared spectra were obtained from the spectrometer and related instruments. Compared with the results at room temperature (RT), PL (1.54μm) intensity increased when samples were annealed at 250°C and decreased when at 550°C. A new peak atmore » 1.15μm from silicon (Si) appeared in 550°C samples. The Si dopants in ZnO film, either through the diffusion of Si from the substrate or ambient, directly absorbed the energy of pumping light and resulted in the suppression of Er{sup 3+} 1.54μm excitation. Furthermore, the energy transmission efficiency between Si and Er{sup 3+} was very low when compared with silicon nanocrystal (Si-NC). Both made the PL (1.54μm) intensity decrease. All the data in experiments proved the negative effects of Si dopants on PL at 1.54μm. And further research is going on.« less

Pulsed laser-induced formation of silica nanogrids

PubMed Central

2014-01-01

Silica grids with micron to sub-micron mesh sizes and wire diameters of 50 nm are fabricated on fused silica substrates. They are formed by single-pulse structured excimer laser irradiation of a UV-absorbing silicon suboxide (SiO x ) coating through the transparent substrate. A polydimethylsiloxane (PDMS) superstrate (cover layer) coated on top of the SiO x film prior to laser exposure serves as confinement for controlled laser-induced structure formation. At sufficiently high laser fluence, this process leads to grids consisting of a periodic loop network connected to the substrate at regular positions. By an additional high-temperature annealing, the residual SiO x is oxidized, and a pure SiO2 grid is obtained. PACS 81.07.-b; 81.07.Gf; 81.65.Cf PMID:24581305

Growth and characterization of β-Ga2O3 crystals

NASA Astrophysics Data System (ADS)

Nikolaev, V. I.; Maslov, V.; Stepanov, S. I.; Pechnikov, A. I.; Krymov, V.; Nikitina, I. P.; Guzilova, L. I.; Bougrov, V. E.; Romanov, A. E.

2017-01-01

Here we report on the growth and characterization of β-Ga2O3 bulk crystals and polycrystalline layer on different substrates. Bulk β-Ga2O3 crystals were produced by free crystallisation of gallium oxide melt in sapphire crucible. Transparent single crystals measuring up to 8 mm across were obtained. Good structural quality was confirmed by x-ray diffraction rocking curve FWHM values of 46″. Young's modulus, shear modulus and hardness of the β-Ga2O3 crystals were measured by nanoindentation and Vickers microindentation techniques. Polycrystalline β-Ga2O3 films were deposited on silicon and sapphire substrates by sublimation method. It was found that structure and morphology of the films were greatly influenced by the material and orientation of the substrates. The best results were achieved on a-plane sapphire substrates where predominantly (111) oriented films were obtained.

Influence of design variables on radiation hardness of silicon MINP solar cells

NASA Technical Reports Server (NTRS)

Anderson, W. A.; Solaun, S.; Rao, B. B.; Banerjee, S.

1985-01-01

Metal-insulator-N/P silicon (MINP) solar cells were fabricated using different substrate resistivity values, different N-layer designs, and different I-layer designs. A shallow junction into an 0.3 ohm-cm substrate gave best efficiency whereas a deeper junction into a 1 to 4 ohm-cm substrate gave improved radiation hardness. I-layer design variation did little to influence radiation hardness.

Environmental barrier coating

DOEpatents

Pujari, Vimal K.; Vartabedian, Ara; Collins, William T.; Woolley, David; Bateman, Charles

2012-12-18

The present invention relates generally to a multi-layered article suitable for service in severe environments. The article may be formed of a substrate, such as silicon carbide and/or silicon nitride. The substrate may have a first layer of a mixture of a rare earth silicate and Cordierite. The substrate may also have a second layer of a rare earth silicate or a mixture of a rare earth silicate and cordierite.

Development of Mullite Substrates and Containers

NASA Technical Reports Server (NTRS)

Sibold, J. D.

1979-01-01

The mullite-molten silicon interaction was evaluated through fabrication of a series of bodies made with variations in density, alumina-silica ratio, and glass-crystalline ratio. The materials were tested in a sessile drop technique. None of the variations stood up to extended exposure to molten silicon sufficiently to be recommended as a container material. However, directional solidification experiments suggest that, under proper conditions, contamination of the silicon by mullite containers can be minimized. To improve an already good thermal expansion match between mullite and silicon, compositional variations were studied. Altering of the alumina-silica ratio was determined to give a continuously varying thermal expansion. A standard mullite composition was selected and substrates 40 x 4 x .040 inches were fabricated. Slotted substrates of various configurations and various compositions were also fabricated.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Vertical group III-V nanowires on si, heterostructures, flexible arrays and fabrication

DOEpatents

Wang, Deli; Soci, Cesare; Bao, Xinyu; Wei, Wei; Jing, Yi; Sun, Ke

2015-01-13

Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer.

Ion irradiation of the native oxide/silicon surface increases the thermal boundary conductance across aluminum/silicon interfaces

NASA Astrophysics Data System (ADS)

Gorham, Caroline S.; Hattar, Khalid; Cheaito, Ramez; Duda, John C.; Gaskins, John T.; Beechem, Thomas E.; Ihlefeld, Jon F.; Biedermann, Laura B.; Piekos, Edward S.; Medlin, Douglas L.; Hopkins, Patrick E.

2014-07-01

The thermal boundary conductance across solid-solid interfaces can be affected by the physical properties of the solid boundary. Atomic composition, disorder, and bonding between materials can result in large deviations in the phonon scattering mechanisms contributing to thermal boundary conductance. Theoretical and computational studies have suggested that the mixing of atoms around an interface can lead to an increase in thermal boundary conductance by creating a region with an average vibrational spectra of the two materials forming the interface. In this paper, we experimentally demonstrate that ion irradiation and subsequent modification of atoms at solid surfaces can increase the thermal boundary conductance across solid interfaces due to a change in the acoustic impedance of the surface. We measure the thermal boundary conductance between thin aluminum films and silicon substrates with native silicon dioxide layers that have been subjected to proton irradiation and post-irradiation surface cleaning procedures. The thermal boundary conductance across the Al/native oxide/Si interfacial region increases with an increase in proton dose. Supported with statistical simulations, we hypothesize that ion beam mixing of the native oxide and silicon substrate within ˜2.2nm of the silicon surface results in the observed increase in thermal boundary conductance. This ion mixing leads to the spatial gradation of the silicon native oxide into the silicon substrate, which alters the acoustic impedance and vibrational characteristics at the interface of the aluminum film and native oxide/silicon substrate. We confirm this assertion with picosecond acoustic analyses. Our results demonstrate that under specific conditions, a "more disordered and defected" interfacial region can have a lower resistance than a more "perfect" interface.

Deposition of hydrogenated silicon clusters for efficient epitaxial growth.

PubMed

Le, Ha-Linh Thi; Jardali, Fatme; Vach, Holger

2018-06-13

Epitaxial silicon thin films grown from the deposition of plasma-born hydrogenated silicon nanoparticles using plasma-enhanced chemical vapor deposition have widely been investigated due to their potential applications in photovoltaic and nanoelectronic device technologies. However, the optimal experimental conditions and the underlying growth mechanisms leading to the high-speed epitaxial growth of thin silicon films from hydrogenated silicon nanoparticles remain far from being understood. In the present work, extensive molecular dynamics simulations were performed to study the epitaxial growth of silicon thin films resulting from the deposition of plasma-born hydrogenated silicon clusters at low substrate temperatures under realistic reactor conditions. There is strong evidence that a temporary phase transition of the substrate area around the cluster impact site to the liquid state is necessary for the epitaxial growth to take place. We predict further that a non-normal incidence angle for the cluster impact significantly facilitates the epitaxial growth of thin crystalline silicon films.

Formation of microchannels from low-temperature plasma-deposited silicon oxynitride

DOEpatents

Matzke, Carolyn M.; Ashby, Carol I. H.; Bridges, Monica M.; Manginell, Ronald P.

2000-01-01

A process for forming one or more fluid microchannels on a substrate is disclosed that is compatible with the formation of integrated circuitry on the substrate. The microchannels can be formed below an upper surface of the substrate, above the upper surface, or both. The microchannels are formed by depositing a covering layer of silicon oxynitride over a mold formed of a sacrificial material such as photoresist which can later be removed. The silicon oxynitride is deposited at a low temperature (.ltoreq.100.degree. C.) and preferably near room temperature using a high-density plasma (e.g. an electron-cyclotron resonance plasma or an inductively-coupled plasma). In some embodiments of the present invention, the microchannels can be completely lined with silicon oxynitride to present a uniform material composition to a fluid therein. The present invention has applications for forming microchannels for use in chromatography and electrophoresis. Additionally, the microchannels can be used for electrokinetic pumping, or for localized or global substrate cooling.

Ablative performance of uncoated silicone-modified and shuttle baseline reinforced carbon composites

NASA Technical Reports Server (NTRS)

Dicus, D. L.; Hopko, R. N.; Brown, R. D.

1976-01-01

The relative ablative performance of uncoated silicone-modified reinforced carbon composite (RCC) and uncoated shuttle baseline RCC substrates was investigated. The test specimens were 13 plies (5.3 to 5.8 millimeters) thick and had a 25-millimeter-diameter test face. Prior to arc tunnel testing, all specimens were subjected to a heat treatment simulating the RCC coating process. During arc tunnel testing, the specimens were exposed to cold wall heating rates of 178 to 529 kilowatts/sq m and stagnation pressures ranging from 0.015 to 0.046 atmosphere at Mach 4.6 in air, with and without preheating in nitrogen. The results show that the ablative performance of uncoated silicone-modified RCC substrates is significantly superior to that of uncoated shuttle baseline RCC substrates over the range of heating conditions used. These results indicate that the silicone-modified RCC substrate would yield a substantially greater safety margin in the event of complete coating loss on the shuttle orbiter.

RF sputtered silicon and hafnium nitrides as applied to 440C steel

NASA Technical Reports Server (NTRS)

Grill, A.; Aron, P. R.

1984-01-01

Silicon nitride and hafnium nitride coatings were deposited on oxidized and unoxidized 440C stainless steel substrates. Sputtering was done in mixtures of argon and nitrogen gases from pressed powder silicon nitride and from hafnium metal targets. The coatings and the interface between the coating and substrate were investigated by X-ray diffractometry, scanning electron microscopy, energy dispersive X-ray analysis and Auger electron spectroscopy. Oxide was found at all interfaces with an interface width of at least 600 A for the oxidized substrates and at least 300 A for the unoxidized substrates. Scratch test results demonstrate that the adhesion of hafnium nitride to both oxidized and unoxidized 440C is superior to that of silicon nitride. Oxidized 440C is found to have increased adhesion, to both nitrides, over that of unoxidized 440C. Coatings of both nitrides deposited at 8 mtorr were found to have increased adhesion to both oxidized and unoxidized 440C over those deposited at 20 mtorr.

Stability of the tungsten diselenide and silicon carbide heterostructure against high energy proton exposure

NASA Astrophysics Data System (ADS)

Walker, Roger C.; Shi, Tan; Jariwala, Bhakti; Jovanovic, Igor; Robinson, Joshua A.

2017-10-01

Single layers of tungsten diselenide (WSe2) can be used to construct ultra-thin, high-performance electronics. Additionally, there has been considerable progress in controlled and direct growth of single layers on various substrates. Based on these results, high-quality WSe2-based devices that approach the limit of physical thickness are now possible. Such devices could be useful for space applications, but understanding how high-energy radiation impacts the properties of WSe2 and the WSe2/substrate interface has been lacking. In this work, we compare the stability against high energy proton radiation of WSe2 and silicon carbide (SiC) heterostructures generated by mechanical exfoliation of WSe2 flakes and by direct growth of WSe2 via metal-organic chemical vapor deposition (MOCVD). These two techniques produce WSe2/SiC heterostructures with distinct differences due to interface states generated during the MOCVD growth process. This difference carries over to differences in band alignment from interface states and the ultra-thin nature of the MOCVD-grown material. Both heterostructures are not susceptible to proton-induced charging up to a dose of 1016 protons/cm2, as measured via shifts in the binding energy of core shell electrons and a decrease in the valence band offset. Furthermore, the MOCVD-grown material is less affected by the proton exposure due to its ultra-thin nature and a greater interaction with the substrate. These combined effects show that the directly grown material is suitable for multi-year use in space, provided that high quality devices can be fabricated from it.

Plasmonic and silicon spherical nanoparticle antireflective coatings

NASA Astrophysics Data System (ADS)

Baryshnikova, K. V.; Petrov, M. I.; Babicheva, V. E.; Belov, P. A.

2016-03-01

Over the last decade, plasmonic antireflecting nanostructures have been extensively studied to be utilized in various optical and optoelectronic systems such as lenses, solar cells, photodetectors, and others. The growing interest to all-dielectric photonics as an alternative optical technology along with plasmonics motivates us to compare antireflective properties of plasmonic and all-dielectric nanoparticle coatings based on silver and crystalline silicon respectively. Our simulation results for spherical nanoparticles array on top of amorphous silicon show that both silicon and silver coatings demonstrate strong antireflective properties in the visible spectral range. For the first time, we show that zero reflectance from the structure with silicon coatings originates from the destructive interference of electric- and magnetic-dipole responses of nanoparticle array with the wave reflected from the substrate, and we refer to this reflection suppression as substrate-mediated Kerker effect. We theoretically compare the silicon and silver coating effectiveness for the thin-film photovoltaic applications. Silver nanoparticles can be more efficient, enabling up to 30% increase of the overall absorbance in semiconductor layer. Nevertheless, silicon coatings allow up to 64% absorbance increase in the narrow band spectral range because of the substrate-mediated Kerker effect, and band position can be effectively tuned by varying the nanoparticles sizes.

Plasmonic and silicon spherical nanoparticle antireflective coatings

PubMed Central

Baryshnikova, K. V.; Petrov, M. I.; Babicheva, V. E.; Belov, P. A.

2016-01-01

Over the last decade, plasmonic antireflecting nanostructures have been extensively studied to be utilized in various optical and optoelectronic systems such as lenses, solar cells, photodetectors, and others. The growing interest to all-dielectric photonics as an alternative optical technology along with plasmonics motivates us to compare antireflective properties of plasmonic and all-dielectric nanoparticle coatings based on silver and crystalline silicon respectively. Our simulation results for spherical nanoparticles array on top of amorphous silicon show that both silicon and silver coatings demonstrate strong antireflective properties in the visible spectral range. For the first time, we show that zero reflectance from the structure with silicon coatings originates from the destructive interference of electric- and magnetic-dipole responses of nanoparticle array with the wave reflected from the substrate, and we refer to this reflection suppression as substrate-mediated Kerker effect. We theoretically compare the silicon and silver coating effectiveness for the thin-film photovoltaic applications. Silver nanoparticles can be more efficient, enabling up to 30% increase of the overall absorbance in semiconductor layer. Nevertheless, silicon coatings allow up to 64% absorbance increase in the narrow band spectral range because of the substrate-mediated Kerker effect, and band position can be effectively tuned by varying the nanoparticles sizes. PMID:26926602

Evaluation of the Effect of Silicone Contamination on Various Bond Systems and the Feasibility of Removing the Contamination

NASA Technical Reports Server (NTRS)

Stanley, Stephanie D.

2008-01-01

Silicone is a contaminant that can cause catastrophic failure of a bond system depending on the materials and processes used to fabricate the bond system, Unfortunately, more and more materials are fabricated using silicone. The purpose of this testing was to evaluate which bond systems are sensitive to silicone contamination and whether or not a cleaning process could be utilized to remove the silicone to bring the bond system performance back to baseline. Due to the extensive nature of the testing attempts will be made to generalize the understanding within classes of substrates, bond systems, and surface preparation and cleaning methods. This study was done by contaminating various meta! (steel, inconel, and aluminum), phenolic (carbon cloth phenolic and glass cloth phenolic), and rubber (natural rubber, asbestos-silicone dioxide filled natural butyldiene rubber, silica-filled ethylene propylenediene monomer, and carbon-filled ethylene propylenediene monomer) substrates which were then bonded using various adhesives and coatings (epoxy-based adhesives, paints, ablative compounds, and Chemlok adhesives) to determine the effect silicone contamination has on a given bond system's performance. The test configurations depended on the bond system being evaluated. The study also evaluated the feasibility of removing the silicone contamination by cleaning the contaminated substrate prior to bonding. The cleaning processes also varied depending on bond system.

In situ micro-Raman analysis and X-ray diffraction of nickel silicide thin films on silicon.

PubMed

Bhaskaran, M; Sriram, S; Perova, T S; Ermakov, V; Thorogood, G J; Short, K T; Holland, A S

2009-01-01

This article reports on the in situ analysis of nickel silicide (NiSi) thin films formed by thermal processing of nickel thin films deposited on silicon substrates. The in situ techniques employed for this study include micro-Raman spectroscopy (microRS) and X-ray diffraction (XRD); in both cases the variations for temperatures up to 350 degrees C has been studied. Nickel silicide thin films formed by vacuum annealing of nickel on silicon were used as a reference for these measurements. In situ analysis was carried out on nickel thin films on silicon, while the samples were heated from room temperature to 350 degrees C. Data was gathered at regular temperature intervals and other specific points of interest (such as 250 degrees C, where the reaction between nickel and silicon to form Ni(2)Si is expected). The transformations from the metallic state, through the intermediate reaction states, until the desired metal-silicon reaction product is attained, are discussed. The evolution of nickel silicide from the nickel film can be observed from both the microRS and XRD in situ studies. Variations in the evolution of silicide from metal for different silicon substrates are discussed, and these include (100) n-type, (100) p-type, and (110) p-type silicon substrates.

Rapid Covalent Modification of Silicon Oxide Surfaces through Microwave-Assisted Reactions with Alcohols.

PubMed

Lee, Austin W H; Gates, Byron D

2016-07-26

We demonstrate the method of a rapid covalent modification of silicon oxide surfaces with alcohol-containing compounds with assistance by microwave reactions. Alcohol-containing compounds are prevalent reagents in the laboratory, which are also relatively easy to handle because of their stability against exposure to atmospheric moisture. The condensation of these alcohols with the surfaces of silicon oxides is often hindered by slow reaction kinetics. Microwave radiation effectively accelerates this condensation reaction by heating the substrates and/or solvents. A variety of substrates were modified in this demonstration, such as silicon oxide films of various thicknesses, glass substrates such as microscope slides (soda lime), and quartz. The monolayers prepared through this strategy demonstrated the successful formation of covalent surface modifications of silicon oxides with water contact angles of up to 110° and typical hysteresis values of 2° or less. An evaluation of the hydrolytic stability of these monolayers demonstrated their excellent stability under acidic conditions. The techniques introduced in this article were successfully applied to tune the surface chemistry of silicon oxides to achieve hydrophobic, oleophobic, and/or charged surfaces.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

2013-05-01

Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

Some material structural properties of SOI substrates produced by SDB technology

NASA Astrophysics Data System (ADS)

Hui, Li; Guo-Liang, Sun; Juan, Zhan; Qin-Yi, Tong

1987-10-01

SOI substrates have been produced by silicon direct bonding (SDB) technology. Thermal oxides ranging in thickness from native oxide to 1 μm or even more, on either or both wafers have been bonded successfully. The fracture strength of the SOI layer is 130-200 kg/cm 2 which is similar to the value of intrinsic bulk silicon. Dislocations have been shown to be concentrated on the backsides of the substrate and no additional defects have been developed within 80 μm of the Si-SiO 2 bonding area. Mobility and minority carrier lifetime similar to that of the original bulk silicon have been obtained after annealing.

Efficient Surface Enhanced Raman Scattering substrates from femtosecond laser based fabrication

NASA Astrophysics Data System (ADS)

Parmar, Vinod; Kanaujia, Pawan K.; Bommali, Ravi Kumar; Vijaya Prakash, G.

2017-10-01

A fast and simple femtosecond laser based methodology for efficient Surface Enhanced Raman Scattering (SERS) substrate fabrication has been proposed. Both nano scaffold silicon (black silicon) and gold nanoparticles (Au-NP) are fabricated by femtosecond laser based technique for mass production. Nano rough silicon scaffold enables large electromagnetic fields for the localized surface plasmons from decorated metallic nanoparticles. Thus giant enhancement (approximately in the order of 104) of Raman signal arises from the mixed effects of electron-photon-phonon coupling, even at nanomolar concentrations of test organic species (Rhodamine 6G). Proposed process demonstrates the low-cost and label-less application ability from these large-area SERS substrates.

Deposition of device quality, low hydrogen content, hydrogenated amorphous silicon at high deposition rates with increased stability using the hot wire filament technique

DOEpatents

Molenbroek, Edith C.; Mahan, Archie Harvin; Gallagher, Alan C.

2000-09-26

A method or producing hydrogenated amorphous silicon on a substrate, comprising the steps of: positioning the substrate in a deposition chamber at a distance of about 0.5 to 3.0 cm from a heatable filament in the deposition chamber; maintaining a pressure in said deposition chamber in the range of about 10 to 100 millitorr and pressure times substrate-filament spacing in the range of about 10 to 100 millitorr-cm, heating the filament to a temperature in the range of about 1,500 to 2,000.degree. C., and heating the substrate to a surface temperature in the range of about 280 to 475.degree. C.; and flowing silicohydride gas into the deposition chamber with said heated filament, decomposing said silicohydride gas into silicon and hydrogen atomic species and allowing products of gas reactions between said atomic species and the silicohydride gas to migrate to and deposit on said substrate while adjusting and maintaining said pressure times substrate-filament spacing in said deposition chamber at a value in said 10 to 100 millitorr range to produce statistically about 3 to 50 atomic collisions between the silicon and hydrogen atomic species migrating to said substrate and undecomposed molecules of the silane or other silicohydride gas in the deposition chamber.

Study of water diffusion on single-supported bilayer lipid membranes by quasielastic neutron scattering

NASA Astrophysics Data System (ADS)

Bai, M.; Miskowiec, A.; Hansen, F. Y.; Taub, H.; Jenkins, T.; Tyagi, M.; Diallo, S. O.; Mamontov, E.; Herwig, K. W.; Wang, S.-K.

2012-05-01

High-energy-resolution quasielastic neutron scattering has been used to elucidate the diffusion of water molecules in proximity to single bilayer lipid membranes supported on a silicon substrate. By varying sample temperature, level of hydration, and deuteration, we identify three different types of diffusive water motion: bulk-like, confined, and bound. The motion of bulk-like and confined water molecules is fast compared to those bound to the lipid head groups (7-10 H2O molecules per lipid), which move on the same nanosecond time scale as H atoms within the lipid molecules.

Rapid epitaxy-free graphene synthesis on silicidated polycrystalline platinum

PubMed Central

Babenko, Vitaliy; Murdock, Adrian T.; Koós, Antal A.; Britton, Jude; Crossley, Alison; Holdway, Philip; Moffat, Jonathan; Huang, Jian; Alexander-Webber, Jack A.; Nicholas, Robin J.; Grobert, Nicole

2015-01-01

Large-area synthesis of high-quality graphene by chemical vapour deposition on metallic substrates requires polishing or substrate grain enlargement followed by a lengthy growth period. Here we demonstrate a novel substrate processing method for facile synthesis of mm-sized, single-crystal graphene by coating polycrystalline platinum foils with a silicon-containing film. The film reacts with platinum on heating, resulting in the formation of a liquid platinum silicide layer that screens the platinum lattice and fills topographic defects. This reduces the dependence on the surface properties of the catalytic substrate, improving the crystallinity, uniformity and size of graphene domains. At elevated temperatures growth rates of more than an order of magnitude higher (120 μm min−1) than typically reported are achieved, allowing savings in costs for consumable materials, energy and time. This generic technique paves the way for using a whole new range of eutectic substrates for the large-area synthesis of 2D materials. PMID:26175062

Innovative Ge Quantum Dot Functional Sensing and Metrology Devices

DTIC Science & Technology

2017-08-21

information latency and power consumption . In contrast, optical interconnects have shown tremendous promise for replacing electrical wires thanks to...single oxidation step of Si0.85Ge0.15 nano-pillars patterned over a buffer layer of Si3N4 on top of the n-Si substrate. During the high- temperature ...exquisitely-controlled dynamic balance between the fluxes of oxygen and silicon interstitials. Results and Discussion: 1. Self-organized, gate

Vacuum die attach for integrated circuits

DOEpatents

Schmitt, E.H.; Tuckerman, D.B.

1991-09-10

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

Vacuum die attach for integrated circuits

DOEpatents

Schmitt, Edward H.; Tuckerman, David B.

1991-01-01

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

Preparation of monolayers of [MnIII 6CrIII]3+ single-molecule magnets on HOPG, mica and silicon surfaces and characterization by means of non-contact AFM

NASA Astrophysics Data System (ADS)

Gryzia, Aaron; Predatsch, Hans; Brechling, Armin; Hoeke, Veronika; Krickemeyer, Erich; Derks, Christine; Neumann, Manfred; Glaser, Thorsten; Heinzmann, Ulrich

2011-08-01

We report on the characterization of various salts of [ Mn III 6 Cr III ] 3+ complexes prepared on substrates such as highly oriented pyrolytic graphite (HOPG), mica, SiO2, and Si3N4. [ Mn III 6 Cr III ] 3+ is a single-molecule magnet, i.e., a superparamagnetic molecule, with a blocking temperature around 2 K. The three positive charges of [ Mn III 6 Cr III ] 3+ were electrically neutralized by use of various anions such as tetraphenylborate (BPh4 -), lactate (C3H5O3 -), or perchlorate (ClO4 -). The molecule was prepared on the substrates out of solution using the droplet technique. The main subject of investigation was how the anions and substrates influence the emerging surface topology during and after the preparation. Regarding HOPG and SiO2, flat island-like and hemispheric-shaped structures were created. We observed a strong correlation between the electronic properties of the substrate and the analyzed structures, especially in the case of mica where we observed a gradient in the analyzed structures across the surface.

Method of making a ceramic with preferential oxygen reactive layer

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Luthra, Krishan Lal (Inventor)

2003-01-01

A method of forming an article. The method comprises forming a silicon-based substrate that is oxidizable by reaction with an oxidant to form at least one gaseous product and applying an intermediate layer/coating onto the substrate, wherein the intermediate layer/coating is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant.

Formation of thin-film resistors on silicon substrates

DOEpatents

Schnable, George L.; Wu, Chung P.

1988-11-01

The formation of thin-film resistors by the ion implantation of a metallic conductive layer in the surface of a layer of phosphosilicate glass or borophosphosilicate glass which is deposited on a silicon substrate. The metallic conductive layer materials comprise one of the group consisting of tantalum, ruthenium, rhodium, platinum and chromium silicide. The resistor is formed and annealed prior to deposition of metal, e.g. aluminum, on the substrate.

IBIC characterisation of novel detectors for single atom doping of quantum computer devices

NASA Astrophysics Data System (ADS)

Yang, Changyi; Jamieson, David N.; Pakes, Chris I.; George, Damien P.; Hearne, Sean M.; Dzurak, Andrew S.; Gauja, Eric; Stanley, F.; Clark, R. G.

2003-09-01

Single ion implantation and online detection is highly desirable for the emerging application, in which single 31P ions need to be inserted in prefabricated silicon cells to construct solid-state quantum bits (qubits). In order to fabricate qubit arrays, we have developed novel detectors that employ detector electrodes adjacent to the prefabricated cells that can detect single keV ion strikes appropriate for the fabrication of shallow phosphorus arrays. The method utilises a high purity silicon substrate with very high resistivity, a thin SiO 2 surface layer, nanometer masks for the lateral positioning single phosphorus implantation, biased electrodes applied to the surface of the silicon and sensitive electronics that can detect the charge transient from single keV ion strikes. A TCAD (Technology Computer Aided Design) software package was applied in the optimisation of the device design and simulation of the detector performance. Here we show the characterisation of these detectors using ion beam induced charge (IBIC) with a focused 2 MeV He ions in a nuclear microprobe. The IBIC imaging method in a nuclear microprobe allowed us to measure the dead-layer thickness of the detector structure (required to be very thin for successful detection of keV ions), and the spatial distribution of the charge collection efficiency around the entire region of the detector. We show that our detectors have near 100% charge collection efficiency for MeV ions, extremely thin dead-layer thickness (about 7 nm) and a wide active region extending laterally from the electrodes (10-20 μm) where qubit arrays can be constructed. We demonstrate that the device can be successfully applied in the detection of keV ionisation energy from single events of keV X-rays and keV 31P ions.

NT-SiC (new-technology silicon carbide) : Φ 650mm optical space mirror substrate of high-strength reaction-sintered silicon carbide

NASA Astrophysics Data System (ADS)

Suyama, Shoko; Itoh, Yoshiyasu; Tsuno, Katsuhiko; Ohno, Kazuhiko

2005-08-01

Silicon carbide (SiC) is the most advantageous as the material of various telescope mirrors, because of high stiffness, low density, low coefficient of thermal expansion, high thermal conductivity and thermal stability. Newly developed high-strength reaction-sintered silicon carbide (NTSIC), which has two times higher strength than sintered SiC, is one of the most promising candidates for lightweight optical mirror substrate, because of fully dense, lightweight, small sintering shrinkage (+/-1 %), good shape capability and low processing temperature. In this study, 650mm in diameter mirror substrate of NTSIC was developed for space telescope applications. Three developed points describe below. The first point was to realize the lightweight to thin the thickness of green bodies. Ribs down to 3mm thickness can be obtained by strengthen the green body. The second point was to enlarge the mirror size. 650mm in diameter of mirror substrate can be fabricated with enlarging the diameter in order. The final point was to realize the homogeneity of mirror substrate. Some properties, such as density, bending strength, coefficient of thermal expansion, Young's modulus, Poisson's ratio, fracture toughness, were measured by the test pieces cutting from the fabricated mirror substrates.

Silicon accumulation and distribution in petunia and sunflower

USDA-ARS?s Scientific Manuscript database

Silicon (Si) is a beneficial element that has been shown to protect plants during periods of abiotic and biotic stress. Plant-available Si can be supplied through substrate components, substrate amendments, liquid fertilization, or foliar sprays. The objective of this study was to compare Si accum...

Microdynamic Devices Fabricated on Silicon-On-Sapphire Substrates.

DTIC Science & Technology

Silicon-on-sapphire substrates are provided for the fabrication of micromechanical devices, such as micromotors . The high voltage stand-off...a consequence, the electrostatically driven devices, micromotors , can be incorporated in the integrated circuits and yet be powered at elevated voltages to increase their work potential.

Method of fabricating germanium and gallium arsenide devices

NASA Technical Reports Server (NTRS)

Jhabvala, Murzban (Inventor)

1990-01-01

A method of semiconductor diode fabrication is disclosed which relies on the epitaxial growth of a precisely doped thickness layer of gallium arsenide or germanium on a semi-insulating or intrinsic substrate, respectively, of gallium arsenide or germanium by either molecular beam epitaxy (MBE) or by metal-organic chemical vapor deposition (MOCVD). The method involves: depositing a layer of doped or undoped silicon dioxide on a germanium or gallium arsenide wafer or substrate, selectively removing the silicon dioxide layer to define one or more surface regions for a device to be fabricated thereon, growing a matched epitaxial layer of doped germanium or gallium arsenide of an appropriate thickness using MBE or MOCVD techniques on both the silicon dioxide layer and the defined one or more regions; and etching the silicon dioxide and the epitaxial material on top of the silicon dioxide to leave a matched epitaxial layer of germanium or gallium arsenide on the germanium or gallium arsenide substrate, respectively, and upon which a field effect device can thereafter be formed.

Deep level transient spectroscopic investigation of phosphorus-doped silicon by self-assembled molecular monolayers.

PubMed

Gao, Xuejiao; Guan, Bin; Mesli, Abdelmadjid; Chen, Kaixiang; Dan, Yaping

2018-01-09

It is known that self-assembled molecular monolayer doping technique has the advantages of forming ultra-shallow junctions and introducing minimal defects in semiconductors. In this paper, we report however the formation of carbon-related defects in the molecular monolayer-doped silicon as detected by deep-level transient spectroscopy and low-temperature Hall measurements. The molecular monolayer doping process is performed by modifying silicon substrate with phosphorus-containing molecules and annealing at high temperature. The subsequent rapid thermal annealing drives phosphorus dopants along with carbon contaminants into the silicon substrate, resulting in a dramatic decrease of sheet resistance for the intrinsic silicon substrate. Low-temperature Hall measurements and secondary ion mass spectrometry indicate that phosphorus is the only electrically active dopant after the molecular monolayer doping. However, during this process, at least 20% of the phosphorus dopants are electrically deactivated. The deep-level transient spectroscopy shows that carbon-related defects are responsible for such deactivation.

Microfabricated instrument for tissue biopsy and analysis

DOEpatents

Krulevitch, Peter A.; Lee, Abraham P.; Northrup, M. Allen; Benett, William J.

2001-01-01

A microfabricated biopsy/histology instrument which has several advantages over the conventional procedures, including minimal specimen handling, smooth cutting edges with atomic sharpness capable of slicing very thin specimens (approximately 2 .mu.m or greater), micro-liter volumes of chemicals for treating the specimens, low cost, disposable, fabrication process which renders sterile parts, and ease of use. The cutter is a "cheese-grater" style design comprising a block or substrate of silicon and which uses anisotropic etching of the silicon to form extremely sharp and precise cutting edges. As a specimen is cut, it passes through the silicon cutter and lies flat on a piece of glass which is bonded to the cutter. Microchannels are etched into the glass or silicon substrates for delivering small volumes of chemicals for treating the specimen. After treatment, the specimens can be examined through the glass substrate.

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors

PubMed Central

Marrs, Michael A.; Raupp, Gregory B.

2016-01-01

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm2 and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate. PMID:27472329

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors.

PubMed

Marrs, Michael A; Raupp, Gregory B

2016-07-26

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm² and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate.

Silicon-based highly-efficient fiber-to-waveguide coupler for high index contrast systems

NASA Astrophysics Data System (ADS)

Nguyen, Victor; Montalbo, Trisha; Manolatou, Christina; Agarwal, Anu; Hong, Ching-yin; Yasaitis, John; Kimerling, L. C.; Michel, Jurgen

2006-02-01

A coupler to efficiently transfer broadband light from a single-mode optical fiber to a single-mode high-index contrast waveguide has been fabricated on a silicon substrate. We utilized a novel coupling scheme, with a vertically asymmetric design consisting of a stepwise parabolic graded index profile combined with a horizontal taper, to simultaneously confine light in both directions. Coupling efficiency has been measured as a function of the device dimensions. The optimal coupling efficiency is achieved for structures whose length equals the focal distance of the graded index and whose input width is close to the mode field diameter of the fiber. The fabricated structure is compact, robust and highly efficient, with an insertion loss of 2.2dB at 1550nm. The coupler exhibits less than 1dB variation in coupling efficiency in the measured spectral range from 1520nmto1620nm. The lowest insertion loss of 1.9dB is measured at 1540nm. The coupler design offers highly efficient coupling for single mode waveguides of core indices up to 2.2.

CMUT Fabrication Based On A Thick Buried Oxide Layer.

PubMed

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O; Khuri-Yakub, Butrus T

2010-10-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required - in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate.

CMUT Fabrication Based On A Thick Buried Oxide Layer

PubMed Central

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O.; Khuri-Yakub, Butrus T.

2010-01-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required – in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate. PMID:22685377

Semiconductor to Metal Transition Characteristics of VO2/NiO Epitaxial Heterostructures Integrated with Si(100)

NASA Astrophysics Data System (ADS)

Molaei, Roya

The novel functionalities of Vanadium dioxide (VO2), such as, several orders of magnitude transition in resistivity and IR transmittance, provide the exciting opportunity for the development of next generation memory, sensor, and field-effect based devices. A critical issue in the development of practical devices based on metal oxides is the integration of high quality epitaxial oxide thin films with the existing silicon technology which is based on silicon (100) substrates. However, silicon is not suitable for epitaxial growth of oxides owing to its tendency to readily form an amorphous oxide layer or silicide at the film-substrate interface. The oxide films deposited directly on silicon exhibit poor crystallinity and are not suitable for device applications. To overcome this challenge, appropriate substrate templates must be developed for the growth of oxide thin films on silicon substrates. The primary objective of this dissertation was to develop an integration methodology of VO2 with Si (100) substrates so they could be used in "smart" sensor type of devices along with other multifunctional devices on the same silicon chip. This was achieved by using a NiO/c- YSZ template layer deposited in situ. It will be shown that if the deposition conditions are controlled properly. This approach was used to integrate VO 2 thin films with Si (100) substrates using pulsed laser deposition (PLD) technique. The deposition methodology of integrating VO2 thin films on silicon using various other template layers will also be discussed. Detailed epitaxial relationship of NiO/c-YSZ/Si(100) heterostructures as a template to growth of VO2 as well as were studied. We also were able to create a p-n junction within a single NiO epilayer through subsequent nanosecond laser annealing, as well as established a structure-property correlation in NiO/c-YSZ/Si(100) thin film epitaxial heterostructures with especial emphasis on the stoichiometry and crystallographic characteristics. NiO/c-YSZ/Si(100) heterostructures were used as template to grow fully relaxed VO2 thin films. The detailed x-ray diffraction, transmission electron microscopy (TEM), electrical characterization results for the deposited films will be presented. In the framework on domain matching epitaxy, epitaxial growth of VO2 (tetragonal crystal structure at growth temperature) on NiO has been explained. Our detailed phi-scan X-ray diffraction measurements corroborate our understanding of the epitaxial growth and in-plane atomic arrangements at the interface. It was observed that the transition characteristics (sharpness, over which electrical property changes are completed, amplitude, transition temperature, and hysteresis) are a strong function of microstructure, strain, and stoichiometry. We have shown that by the choosing the right template layer, strain in the VO2 thin films can be fully relaxed and near-bulk VO2 transition temperatures can be achieved. Finally, I will present my research work on modification of semiconductor-to-metal transition characteristics and effect on room temperature magnetic properties of VO2 thin films upon laser annealing. While the microstructure (epitaxy, crystalline quality etc.) and phase were preserved, we envisage these changes to occur as a result of introduction of oxygen vacancies upon laser treatment.

12-GHz thin-film transistors on transferrable silicon nanomembranes for high-performance flexible electronics.

PubMed

Sun, Lei; Qin, Guoxuan; Seo, Jung-Hun; Celler, George K; Zhou, Weidong; Ma, Zhenqiang

2010-11-22

Multigigahertz flexible electronics are attractive and have broad applications. A gate-after-source/drain fabrication process using preselectively doped single-crystal silicon nanomembranes (SiNM) is an effective approach to realizing high device speed. However, further downscaling this approach has become difficult in lithography alignment. In this full paper, a local alignment scheme in combination with more accurate SiNM transfer measures for minimizing alignment errors is reported. By realizing 1 μm channel alignment for the SiNMs on a soft plastic substrate, thin-film transistors with a record speed of 12 GHz maximum oscillation frequency are demonstrated. These results indicate the great potential of properly processed SiNMs for high-performance flexible electronics.

Grating-assisted coupling to nanophotonic circuits in microcrystalline diamond thin films.

PubMed

Rath, Patrik; Khasminskaya, Svetlana; Nebel, Christoph; Wild, Christoph; Pernice, Wolfram Hp

2013-01-01

Synthetic diamond films can be prepared on a waferscale by using chemical vapour deposition (CVD) on suitable substrates such as silicon or silicon dioxide. While such films find a wealth of applications in thermal management, in X-ray and terahertz window design, and in gyrotron tubes and microwave transmission lines, their use for nanoscale optical components remains largely unexplored. Here we demonstrate that CVD diamond provides a high-quality template for realizing nanophotonic integrated optical circuits. Using efficient grating coupling devices prepared from partially etched diamond thin films, we investigate millimetre-sized optical circuits and achieve single-mode waveguiding at telecoms wavelengths. Our results pave the way towards broadband optical applications for sensing in harsh environments and visible photonic devices.

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Epitaxial regrowth of silicon for the fabrication of radial junction nanowire solar cells

NASA Astrophysics Data System (ADS)

Kendrick, Chito E.; Eichfeld, Sarah M.; Ke, Yue; Weng, Xiaojun; Wang, Xin; Mayer, Theresa S.; Redwing, Joan M.

2010-08-01

Radial p-n silicon nanowire (SiNW) solar cells are of interest as a potential pathway to increase the efficiency of crystalline silicon photovoltaics by reducing the junction length and surface reflectivity. Our studies have focused on the use of vapor-liquid-solid (VLS) growth in combination with chemical vapor deposition (CVD) processing for the fabrication of radial p-n junction SiNW array solar cells. High aspect ratio p-type SiNW arrays were initially grown on gold-coated (111) Si substrates by CVD using SiCl4 as the source gas and B2H6 as the p-type dopant source. The epitaxial re-growth of n-type Si shell layers on the Si nanowires was then investigated using SiH4 as the source gas and PH3 as the dopant. Highly conformal coatings were achieved on nanowires up to 25 μm in length. The microstructure of the Si shell layer changed from polycrystalline to single crystal as the deposition temperature was raised from 650oC to 950oC. Electrical test structures were fabricated by aligning released SiNWs onto pre-patterned substrates via fieldassisted assembly followed by selective removal of the n-type shell layer and contact deposition. Current-voltage measurements of the radial p-n SiNWs diodes fabricated with re-grown Si shell layers at 950°C demonstrate rectifying behavior with an ideality factor of 1.93. Under illumination from an AM1.5g spectrum and efficiency for this single SiNW radial p-n junction was determined to be 1.8%, total wire diameter was 985 nm.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Schwank, James R.; Fleetwood, Daniel M.; Shaneyfelt, Marty R.; Winokur, Peter S.; Devine, Roderick A. B.

1998-01-01

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

High-Performance Flexible Thin-Film Transistors Based on Single-Crystal-like Silicon Epitaxially Grown on Metal Tape by Roll-to-Roll Continuous Deposition Process.

PubMed

Gao, Ying; Asadirad, Mojtaba; Yao, Yao; Dutta, Pavel; Galstyan, Eduard; Shervin, Shahab; Lee, Keon-Hwa; Pouladi, Sara; Sun, Sicong; Li, Yongkuan; Rathi, Monika; Ryou, Jae-Hyun; Selvamanickam, Venkat

2016-11-02

Single-crystal-like silicon (Si) thin films on bendable and scalable substrates via direct deposition are a promising material platform for high-performance and cost-effective devices of flexible electronics. However, due to the thick and unintentionally highly doped semiconductor layer, the operation of transistors has been hampered. We report the first demonstration of high-performance flexible thin-film transistors (TFTs) using single-crystal-like Si thin films with a field-effect mobility of ∼200 cm 2 /V·s and saturation current, I/l W > 50 μA/μm, which are orders-of-magnitude higher than the device characteristics of conventional flexible TFTs. The Si thin films with a (001) plane grown on a metal tape by a "seed and epitaxy" technique show nearly single-crystalline properties characterized by X-ray diffraction, Raman spectroscopy, reflection high-energy electron diffraction, and transmission electron microscopy. The realization of flexible and high-performance Si TFTs can establish a new pathway for extended applications of flexible electronics such as amplification and digital circuits, more than currently dominant display switches.

The Growth of Expitaxial GaAs and GaAlAs on Silicon Substrates by OMVPE

DTIC Science & Technology

1988-08-01

structures have been grown on semi-insulating gallium arsenide substrates, and on high-resistivity silicon substrates using a two stage growth technique...fully in Quarter 9. 2. MATERIALS GROWTH 2.1 DOPING OF GALLIUM ARSENIDE FOR FETs As reported in quarter 7, doping levels for GaAs/SI 4ere found to be a...FET structures on both GaAs and Si substrates. A number of FET layers have been grown to the GAT4 specification on semi-insulating gallium arsenide

Stress stiffened silicon nitride micro bridges array as substrate with tunable stiffness for cell culture.

PubMed

Chen, Jianfeng; Liu, Guangli; Ma, Chengfu; Zhao, Gang; Du, Wenqiang; Zhu, Wulin; Chu, Jiaru

2017-06-01

Recently, interactions between one-dimensional structural stiffness of physical micro environments and cell biological process have been widely studied. However in previous studies, the influence of structural stiffness on biological process was coupled with the influence of micro fiber curvature. Therefore decoupling the influences of fiber curvature and structural stiffness on cell biological process is of prime importance. In this study, we proposed a novel cell culture substrate comprised of silicon nitride bridges whose structure stiffness can be regulated by altering the axial residual stress without changing material and geometry properties. Both theoretical calculations and finite element simulations were performed to study the influence of residual stress on structure stiffness of bridges. Then multi-positions AFM bending tests were implemented to measure local stiffness of a single micro bridge so as to verify our predictions. NIH/3T3 mouse fibroblast cells were cultured on our substrates to examine the feasibility of the substrate application for investigating cellular response to microenvironment with variable stiffness. The results showed that cells on the edge region near bridge ends were more spread, elongated and better aligned along the bridge axial direction than those on the bridge center region. The results suggest that cells can sense and respond to the differences of stiffness and stiffness gradient between the edge and the center region of the bridges, which makes this kind of substrates can be applied in some biomedical fields, such as cell migration and wound healing. Copyright © 2017 Elsevier B.V. All rights reserved.

High speed, mask-less, laser controlled deposition of microscale tungsten tracks using 405 nm wavelength diode laser

NASA Astrophysics Data System (ADS)

Ten, Jyi Sheuan; Sparkes, Martin; O'Neill, William

2017-02-01

A rapid, mask-less deposition technique for the deposition of conductive tracks to nano- and micro-devices has been developed. The process uses a 405 nm wavelength laser diode for the direct deposition of tungsten tracks on silicon substrates via laser assisted chemical vapour deposition. Unlike lithographic processes this technique is single step and does not require chemical masks that may contaminate the substrate. To demonstrate the process, tungsten was deposited from tungsten hexacarbonyl precursors to produce conductive tracks with widths of 1.7-28 μm and heights of 0.05-35 μm at laser scan speeds up to 40 μm/s. The highest volumetric deposition rate achieved is 1×104 μm3/s, three orders of magnitude higher than that of focused ion beam deposition and on par with a 515 nm wavelength argon ion laser previously reported as the laser source. The microstructure and elemental composition of the deposits are comparable to that of largearea chemical vapour deposition methods using the same chemical precursor. The contact resistance and track resistance of the deposits has been measured using the transfer length method to be 205 μΩ cm. The deposition temperature has been estimated at 334 °C from a laser heat transfer model accounting for temperature dependent optical and physical properties of the substrate. The peak temperatures achieved on silicon and other substrates are higher than the thermal dissociation temperature of numerous precursors, indicating that this technique can also be used to deposit other materials such as gold and platinum on various substrates.

Wetting of silicone oil onto a cell-seeded substrate

NASA Astrophysics Data System (ADS)

Lu, Yongjie; Chan, Yau Kei; Chao, Youchuang; Shum, Ho Cheung

2017-11-01

Wetting behavior of solid substrates in three-phase systems containing two immiscible liquids are widely studied. There exist many three-phase systems in biological environments, such as droplet-based microfluidics or tamponade of silicone oil for eye surgery. However, few studies focus on wetting behavior of biological surfaces with cells. Here we investigate wetting of silicone oil onto cell-seeded PMMA sheet immersed in water. Using a simple parallel-plate cell, we show the effect of cell density, viscosity of silicone oil, morphology of silicone oil drops and interfacial tension on the wetting phenomenon. The dynamics of wetting is also observed by squeezing silicone oil drop using two parallel plates. Experimental results are explained based on disjoining pressure which is dependent on the interaction of biological surfaces and liquid used. These findings are useful for explaining emulsification of silicone oil in ophthalmological applications.

Fabrication of resonant patterns using thermal nano-imprint lithography for thin-film photovoltaic applications.

PubMed

Khaleque, Tanzina; Svavarsson, Halldor Gudfinnur; Magnusson, Robert

2013-07-01

A single-step, low-cost fabrication method to generate resonant nano-grating patterns on poly-methyl-methacrylate (PMMA; plexiglas) substrates using thermal nano-imprint lithography is reported. A guided-mode resonant structure is obtained by subsequent deposition of thin films of transparent conductive oxide and amorphous silicon on the imprinted area. Referenced to equivalent planar structures, around 25% and 45% integrated optical absorbance enhancement is observed over the 450-nm to 900-nm wavelength range in one- and two-dimensional patterned samples, respectively. The fabricated elements provided have 300-nm periods. Thermally imprinted thermoplastic substrates hold potential for low-cost fabrication of nano-patterned thin-film solar cells for efficient light management.

Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

NASA Astrophysics Data System (ADS)

Syed Mohammed, Zishan Ali; Puiu, Poenar Daniel; Aditya, Sheel

2018-01-01

Low resistance is an important requirement for microcoils which act as a signal receiver to ensure low thermal noise during signal detection. High-aspect ratio (HAR) planar microcoils entrenched in blind silicon trenches have features that make them more attractive than their traditional counterparts employing electroplating through a patterned thick polymer or achieved through silicon vias. However, challenges met in fabrication of such coils have not been discussed in detail until now. This paper reports the realization of such HAR microcoils embedded in Si blind trenches, fabricated with a single lithography step by first etching blind trenches in the silicon substrate with an aspect ratio of almost 3∶1 and then filling them up using copper electroplating. The electroplating was followed by chemical wet etching as a faster way of removing excess copper than traditional chemical mechanical polishing. Electrical resistance was further reduced by annealing the microcoils. The process steps and challenges faced in the realization of such structures are reported here followed by their electrical characterization. The obtained electrical resistances are then compared with those of other similar microcoils embedded in blind vias.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Residual strain effects on large aspect ratio micro-diaphragms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hijab, R.S.; Muller, R.S.

1988-09-30

Highly compliant, large aspect ratio diaphragms for use in low-pressure, capacitive-readout sensors, have been investigated. In such structures, unrelaxed strain in the diaphragms can radically alter mechanical behavior. Although strain can be reduced by thermal annealing, it usually reaches a remnant irreducible minimum. The purpose of this paper is to describe techniques that result in low-strain materials and that reduce the effects of residual strain in micro-diaphragms. Square polysilicon grilles and perforated diaphragms made from both single and double polysilicon layers and from single-crystal silicon, with aspect ratios (side/thickness) of up to 1000 and very low compressive strain ({approx}6 {times}more » 10{sup {minus}5}), have been fabricated. Strain reduction is achieved by combining thermal annealing with one of two mechanical design techniques. The first technique makes use of a series of cantilever beams to support the diaphragms. In a second procedure, corrugated surfaces in thinned membranes of single-crystal silicon are formed. The corrugations result from the use of boron doping and anisotropic silicon etching. In both of these techniques to produce low-strain diaphragms, an etched cavity is purposely formed in the substrate crystal below them. Only one-sided processing of wafers is employed, thus aiding reproducibility and providing ease of compatibility with an MOS process. A fast-etching sacrificial-support layer (phosphorus-doped CVD oxide) is used. 4 refs., 10 figs.« less

Epitaxial hexagonal materials on IBAD-textured substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Matias, Vladimir; Yung, Christopher

2017-08-15

A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substratesmore » to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer.« less

Microcrystalline silicon growth for heterojunction solar cells

NASA Technical Reports Server (NTRS)

Iles, P. A.; Leung, D. C.; Fang, P. H.

1984-01-01

A single source of evaporation with B mixed with highly doped Si is used instead of the coevaporation of separate Si and B sources to reduce possible carbon contamination. The results of both the heterojunction or heteroface structures, however, are similar when evaporation is used. The best Voc of the heterojunction is about 460mV and no improvement in Voc in the heteroface structure is observed. Slight Voc degradation occurred. A study of the p m-Si/p c-Si structure showed a negative Voc in many cases. The interface properties between the two materials are such that instead of repelling minority carriers from the substrate carrier, collection actually occurred. Another study of cells made in the part of substrates not covered by n-Si results in performance lower than the controls. This indicates possible substrate degradation in the process.

Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector.

PubMed

Putranto, Dedy Septono Catur; Priambodo, Purnomo Sidi; Hartanto, Djoko; Du, Wei; Satoh, Hiroaki; Ono, Atsushi; Inokawa, Hiroshi

2014-09-08

Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation.

A continuous silicon-coating facility

NASA Technical Reports Server (NTRS)

Butter, C.; Heaps, J. D.

1979-01-01

Automatic continuous silicon-coating facility is used to process 100 by 10 cm graphite-coated ceramic substrates for silicon solar cells. Process reduces contamination associated with conventional dip-coating processes, improving material service life.

Gray scale x-ray mask

DOEpatents

Morales, Alfredo M [Livermore, CA; Gonzales, Marcela [Seattle, WA

2006-03-07

The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch the silicon substrate and therefore provides the ability etch structures of variable depths.

Broadly tunable terahertz difference-frequency generation in quantum cascade lasers on silicon

NASA Astrophysics Data System (ADS)

Jung, Seungyong; Kim, Jae Hyun; Jiang, Yifan; Vijayraghavan, Karun; Belkin, Mikhail A.

2018-01-01

We report broadly tunable terahertz (THz) sources based on intracavity Cherenkov difference-frequency generation in quantum cascade lasers transfer-printed on high-resistivity silicon substrates. Spectral tuning from 1.3 to 4.3 THz was obtained from a 2-mm long laser chip using a modified Littrow external cavity setup. The THz power output and the midinfrared-to-THz conversion efficiency of the devices transferred on silicon are dramatically enhanced, compared with the devices on a native semi-insulating InP substrate. Enhancement is particularly significant at higher THz frequencies, where the tail of the Reststrahlen band results in a strong absorption of THz light in the InP substrate.

Designed porosity materials in nuclear reactor components

DOEpatents

Yacout, A. M.; Pellin, Michael J.; Stan, Marius

2016-09-06

A nuclear fuel pellet with a porous substrate, such as a carbon or tungsten aerogel, on which at least one layer of a fuel containing material is deposited via atomic layer deposition, and wherein the layer deposition is controlled to prevent agglomeration of defects. Further, a method of fabricating a nuclear fuel pellet, wherein the method features the steps of selecting a porous substrate, depositing at least one layer of a fuel containing material, and terminating the deposition when the desired porosity is achieved. Also provided is a nuclear reactor fuel cladding made of a porous substrate, such as silicon carbide aerogel or silicon carbide cloth, upon which layers of silicon carbide are deposited.

Near single-crystalline, high-carrier-mobility silicon thin film on a polycrystalline/amorphous substrate

DOEpatents

Findikoglu, Alp T [Los Alamos, NM; Jia, Quanxi [Los Alamos, NM; Arendt, Paul N [Los Alamos, NM; Matias, Vladimir [Santa Fe, NM; Choi, Woong [Los Alamos, NM

2009-10-27

A template article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material; is provided, together with a semiconductor article including a base substrate including: (i) a base material selected from the group consisting of polycrystalline substrates and amorphous substrates, and (ii) at least one layer of a differing material upon the surface of the base material; and, a buffer material layer upon the base substrate, the buffer material layer characterized by: (a) low chemical reactivity with the base substrate, (b) stability at temperatures up to at least about 800.degree. C. under low vacuum conditions, and (c) a lattice crystal structure adapted for subsequent deposition of a semiconductor material, and, a top-layer of semiconductor material upon the buffer material layer.

Monolithically interconnected silicon-film™ module technology

NASA Astrophysics Data System (ADS)

DelleDonne, E. J.; Ford, D. H.; Hall, R. B.; Ingram, A. E.; Rand, J. A.; Barnett, A. M.

1999-03-01

AstroPower is developing an advanced thin-silicon-based, photovoltaic module product. A low-cost monolithic interconnected device is being integrated into a module that combines the design and process features of advanced light trapped, thin-silicon solar cells. This advanced product incorporates a low-cost substrate, a nominally 50-μm thick grown silicon layer with minority carrier diffusion lengths exceeding the active layer thickness, light trapping due to back-surface reflection, and back-surface passivation. The thin silicon layer enables high solar cell performance and can lead to a module conversion efficiency as high as 19%. These performance design features, combined with low-cost manufacturing using relatively low-cost capital equipment, continuous processing and a low-cost substrate, will lead to high-performance, low-cost photovoltaic panels.

Evanescent Microwave Probes on High-Resistivity Silicon and its Application in Characterization of Semiconductors

NASA Technical Reports Server (NTRS)

Tabib-Azar, M.; Akinwande, D.; Ponchak, George E.; LeClair, S. R.

1999-01-01

In this article we report the design, fabrication, and characterization of very high quality factor 10 GHz microstrip resonators on high-resistivity (high-rho) silicon substrates. Our experiments show that an external quality factor of over 13 000 can be achieved on microstripline resonators on high-rho silicon substrates. Such a high Q factor enables integration of arrays of previously reported evanescent microwave probe (EMP) on silicon cantilever beams. We also demonstrate that electron-hole pair recombination and generation lifetimes of silicon can be conveniently measured by illuminating the resonator using a pulsed light. Alternatively, the EMP was also used to nondestructively monitor excess carrier generation and recombination process in a semiconductor placed near the two-dimensional resonator.

Evaluation of the Effect of Silicone Contamination on Various Bond Systems and the Feasibility of Removing the Contamination

NASA Technical Reports Server (NTRS)

Stanley, Stephanie D.

2008-01-01

Silicone is a contaminant that can cause catastrophic failure of a bond system depending on the materials and processes used to fabricate the bond system. Unfortunately, more and more materials are fabricated using silicone. The purpose of this testing was to evaluate which bond systems are sensitive to silicone contamination and whether or not a cleaning process could be utilized to remove the silicone to bring the bond system performance back to baseline. Due to the extensive nature of the testing, attempts will be made to generalize the understanding within classes of substrates, bond systems, and surface preparation and cleaning methods. This study was done by contaminating various metal (steel, Inconel, and aluminum), phenolic (carbon-cloth phenolic [CCP] and glass-cloth phenolic [GCP]), and rubber (natural rubber, asbestos-silicone dioxide filled natural butyldiene rubber [ASNBR]; silica-filled ethylene propylenediene monomer [SFEPDM], and carbon-filled ethylene propylenediene monomer [CFEPDM]) substrates which were then bonded using various adhesives and coatings (epoxy-based adhesives, paints, ablative compounds, and Chemlok adhesives) to determine the effect silicone contamination has on a given bond system's performance. The test configurations depended on the bond system being evaluated. The study also evaluated the feasibility of removing the silicone contamination by cleaning the contaminated substrate prior to bonding. The cleaning processes also varied depending on bond system.

Silicon on ceramic process. Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Zook, J. D.; Heaps, J. D.; Maciolek, R. B.; Koepke, B. G.; Butter, C. D.; Schuldt, S. B.

1977-01-01

The technical and economic feasibility of producing solar-cell-quality sheet silicon was investigated. The sheets were made by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Significant progress was made in all areas of the program.

Effects of varying oxygen partial pressure on molten silicon-ceramic substrate interactions

NASA Technical Reports Server (NTRS)

Ownby, D. P.; Barsoum, M. W.

1980-01-01

The silicon sessile drop contact angle was measured on hot pressed silicon nitride, silicon nitride coated on hot pressed silicon nitride, silicon carbon coated on graphite, and on Sialon to determine the degree to which silicon wets these substances. The post-sessile drop experiment samples were sectioned and photomicrographs were taken of the silicon-substrate interface to observe the degree of surface dissolution and degradation. Of these materials, silicon did not form a true sessile drop on the SiC on graphite due to infiltration of the silicon through the SiC coating, nor on the Sialon due to the formation of a more-or-less rigid coating on the liquid silicon. The most wetting was obtained on the coated Si3N4 with a value of 42 deg. The oxygen concentrations in a silicon ribbon furnace and in a sessile drop furnace were measured using the protable thoria-yttria solid solution electrolyte oxygen sensor. Oxygen partial pressures of 10 to the minus 7 power atm and 10 to the minus 8 power atm were obtained at the two facilities. These measurements are believed to represent nonequilibrium conditions.

Patterned microstructures formed with MeV Au implantation in Si(1 0 0)

NASA Astrophysics Data System (ADS)

Rout, Bibhudutta; Greco, Richard R.; Zachry, Daniel P.; Dymnikov, Alexander D.; Glass, Gary A.

2006-09-01

Energetic (MeV) Au implantation in Si(1 0 0) (n-type) through masked micropatterns has been used to create layers resistant to KOH wet etching. Microscale patterns were produced in PMMA and SU(8) resist coatings on the silicon substrates using P-beam writing and developed. The silicon substrates were subsequently exposed using 1.5 MeV Au 3+ ions with fluences as high as 1 × 10 16 ions/cm 2 and additional patterns were exposed using copper scanning electron microscope calibration grids as masks on the silicon substrates. When wet etched with KOH microstructures were created in the silicon due to the resistance to KOH etching cause by the Au implantation. The process of combining the fabrication of masked patterns with P-beam writing with broad beam Au implantation through the masks can be a promising, cost-effective process for nanostructure engineering with Si.

AES study on the chemical composition of ferroelectric BaTiO3 thin films RF sputter-deposited on silicon

NASA Technical Reports Server (NTRS)

Dharmadhikari, V. S.; Grannemann, W. W.

1983-01-01

AES depth profiling data are presented for thin films of BaTiO3 deposited on silicon by RF sputtering. By profiling the sputtered BaTiO3/silicon structures, it was possible to study the chemical composition and the interface characteristics of thin films deposited on silicon at different substrate temperatures. All the films showed that external surface layers were present, up to a few tens of angstroms thick, the chemical composition of which differed from that of the main layer. The main layer had stable composition, whereas the intermediate film-substrate interface consisted of reduced TiO(2-x) oxides. The thickness of this intermediate layer was a function of substrate temperature. All the films showed an excess of barium at the interface. These results are important in the context of ferroelectric phenomena observed in BaTiO3 thin films.

Optical substrate materials for synchrotron radiation beamlines

DOE Office of Scientific and Technical Information (OSTI.GOV)

Howells, M.R.; Paquin, R.A.

1997-06-01

The authors consider the materials choices available for making optical substrates for synchrotron radiation beam lines. They find that currently the optical surfaces can only be polished to the required finish in fused silica and other glasses, silicon, CVD silicon carbide, electroless nickel and 17-4 PH stainless steel. Substrates must therefore be made of one of these materials or of a metal that can be coated with electroless nickel. In the context of material choices for mirrors they explore the issues of dimensional stability, polishing, bending, cooling, and manufacturing strategy. They conclude that metals are best from an engineering andmore » cost standpoint while the ceramics are best from a polishing standpoint. They then give discussions of specific materials as follows: silicon carbide, silicon, electroless nickel, Glidcop{trademark}, aluminum, precipitation-hardening stainless steel, mild steel, invar and superinvar. Finally they summarize conclusions and propose ideas for further research.« less

Stoichiometry of Silicon Dioxide Films Obtained by Ion-Beam Sputtering

NASA Astrophysics Data System (ADS)

Telesh, E. V.; Dostanko, A. P.; Gurevich, O. V.

2018-03-01

The composition of SiOx films produced by ion-beam sputtering (IBS) of silicon and quartz targets were studied by infrared spectrometry. Films with thicknesses of 150-390 nm were formed on silicon substrates. It was found that increase in the partial pressure of oxygen in the working gas, increase in the temperature of the substrate, and the presence of a positive potential on the target during reactive IBS of silicon shifted the main absorption band νas into the high-frequency region and increased the composition index from 1.41 to 1.85. During IBS of a quartz target the stoichiometry of the films deteriorates with increase of the energy of the sputtering argon ions. This may be due to increase of the deposition rate. Increase in the current of the thermionic compensator, increase of the substrate temperature, and addition of oxygen led to the formation of SiOx films with improved stoichiometry.

Method to fabricate silicon chromatographic column comprising fluid ports

DOEpatents

Manginell, Ronald P.; Frye-Mason, Gregory C.; Heller, Edwin J.; Adkins, Douglas R.

2004-03-02

A new method for fabricating a silicon chromatographic column comprising through-substrate fluid ports has been developed. This new method enables the fabrication of multi-layer interconnected stacks of silicon chromatographic columns.

Curvature Control of Silicon Microlens for THz Dielectric Antenna

NASA Technical Reports Server (NTRS)

Lee, Choonsup; Chattopadhyay, Goutam; Cooper, Ken; Mehdi, Imran

2012-01-01

We have controlled the curvature of silicon microlens by changing the amount of photoresist in order to microfabricate hemispherical silicon microlens which can improve the directivity and reduce substrate mode losses.

Micromachined cutting blade formed from {211}-oriented silicon

DOEpatents

Fleming, James G.; Sniegowski, Jeffry J.; Montague, Stephen

2003-09-09

A cutting blade is disclosed fabricated of micromachined silicon. The cutting blade utilizes a monocrystalline silicon substrate having a {211} crystalline orientation to form one or more cutting edges that are defined by the intersection of {211} crystalline planes of silicon with {111} crystalline planes of silicon. This results in a cutting blade which has a shallow cutting-edge angle .theta. of 19.5.degree.. The micromachined cutting blade can be formed using an anisotropic wet etching process which substantially terminates etching upon reaching the {111} crystalline planes of silicon. This allows multiple blades to be batch fabricated on a common substrate and separated for packaging and use. The micromachined cutting blade, which can be mounted to a handle in tension and optionally coated for increased wear resistance and biocompatibility, has multiple applications including eye surgery (LASIK procedure).

Micromachined cutting blade formed from {211}-oriented silicon

DOEpatents

Fleming, James G [Albuquerque, NM; Fleming, legal representative, Carol; Sniegowski, Jeffry J [Tijeras, NM; Montague, Stephen [Albuquerque, NM

2011-08-09

A cutting blade is disclosed fabricated of micromachined silicon. The cutting blade utilizes a monocrystalline silicon substrate having a {211} crystalline orientation to form one or more cutting edges that are defined by the intersection of {211} crystalline planes of silicon with {111} crystalline planes of silicon. This results in a cutting blade which has a shallow cutting-edge angle .theta. of 19.5.degree.. The micromachined cutting blade can be formed using an anisotropic wet etching process which substantially terminates etching upon reaching the {111} crystalline planes of silicon. This allows multiple blades to be batch fabricated on a common substrate and separated for packaging and use. The micromachined cutting blade, which can be mounted to a handle in tension and optionally coated for increased wear resistance and biocompatibility, has multiple applications including eye surgery (LASIK procedure).

MBE growth and optical properties of GaN layers on SiC/Si(111) hybrid substrate

NASA Astrophysics Data System (ADS)

Reznik, R. R.; Kotlyar, K. P.; Soshnikov, I. P.; Kukushkin, S. A.; Osipov, A. V.; Nikitina, E. V.; Cirlin, G. E.

2017-11-01

The fundamental possibility of the growth of GaN layers by molecular-beam epitaxy on a silicon substrate with nanoscale buffer layer of silicon carbide without any AlN layers has been demonstrated for the first time. Morphological properties of the resulting system have been studied.

Influence of calcium and silicon supplementation into Pleurotus ostreatus substrates on quality of fresh and canned mushrooms.

PubMed

Thongsook, T; Kongbangkerd, T

2011-08-01

Supplements of gypsum (calcium source), pumice (silicon source) and pumice sulfate (silicon and calcium source) into substrates for oyster mushrooms (Pleurotus ostreatus) were searched for their effects on production as well as qualities of fresh and canned mushrooms. The addition of pumice up to 30% had no effect on total yield, size distribution and cap diameters. The supplementation of gypsum at 10% decreased the total yield; and although gypsum at 5% did not affect total yield, the treatment increased the proportion of large-sized caps. High content (>10%) of pumice sulfate resulted in the lower yield. Calcium and silicon contents in the fruit bodies were not influenced by supplementations. The centrifugal drip loss values and solid content of fresh mushrooms, and the percentage of weight gained and firmness of canned mushrooms, cultivated in substrates supplemented with gypsum, pumice and pumice sulfate were significantly (p≤0.05) higher than those of the control. Scanning electron micrographs revealed the more compacted hyphae of mushroom stalks supplemented with silicon and/or calcium after heat treatment, compared to the control. Supplementation of P. ostreatus substrates with 20% pumice was the most practical treatment because it showed no effect on yield and the most cost-effective.

Porous silicon-copper phthalocyanine heterostructure based photoelectrochemical cell

NASA Astrophysics Data System (ADS)

A. Betty, C.; N, Padma; Arora, Shalav; Survaiya, Parth; Bhattacharya, Debarati; Choudhury, Sipra; Roy, Mainak

2018-01-01

A hybrid solar cell consisting of nanostructured p-type porous silicon (PS) deposited with visible light absorbing dye, Copper Phthalocyanine (CuPc) has been prepared in the photoelectrochemical cell configuration. P-type PS with (100) and (111) orientations which have different porous structures were used for studying the effects of the substrate morphology on the cell efficiency. Heterostructures were prepared by depositing three different thicknesses of CuPc for optimizing the cell efficiency. Structural and surface characterizations were studied using XRD, Raman, SEM and AFM on the PS-CuPc heterostructure. XRD spectrum on both plane silicon and porous silicon indicates the π-π stacking of CuPc with increased disorder for CuPc film on porous silicon. Electrochemical characterizations under sun light type radiation have been carried out to evaluate the photosensitivity of the heterostructure. Between the two different substrates, (100) PS gives better photocurrent, possibly due to the higher surface area and lower series resistance of the structure. Among the (100) PS substrates, (100) PS with 15 nm CuPc film gives Voc more than 1 V resulting in higher efficiency for the cell. The study suggests the scope for optimization of solar cell efficiency using various combinations of the substrate structure and thickness of the sensitizing layer.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y.S.

1991-08-20

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used. 5 figures.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y. Simon

1991-01-01

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used.

Silicon nitride protective coatings for silvered glass mirrors

DOEpatents

Tracy, C. Edwin; Benson, David K.

1988-01-01

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate before metal deposition to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors.

Silicon nitride protective coatings for silvered glass mirrors

DOEpatents

Tracy, C.E.; Benson, D.K.

1984-07-20

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate prior to metal deposition thereon to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Silicon nanowires: where mechanics and optics meet at the nanoscale.

PubMed

Ramos, Daniel; Gil-Santos, Eduardo; Malvar, Oscar; Llorens, Jose M; Pini, Valerio; San Paulo, Alvaro; Calleja, Montserrat; Tamayo, Javier

2013-12-06

Mechanical transducers based on nanowires promise revolutionary advances in biological sensing and force microscopy/spectroscopy. A crucial step is the development of simple and non-invasive techniques able to detect displacements with subpicometer sensitivity per unit bandwidth. Here, we design suspended tapered silicon nanowires supporting a range of optical resonances that confine and efficiently scatter light in the visible range. Then, we develop an optical method for efficiently coupling the evanescent field to the regular interference pattern generated by an incoming laser beam and the reflected beam from the substrate underneath the nanowire. This optomechanical coupling is here applied to measure the displacement of 50 nm wide nanowires with sensitivity on the verge of 1 fm/Hz(1/2) at room temperature with a simple laser interferometry set-up. This method opens the door to the measurement of the Brownian motion of ultrashort nanowires for the detection of single biomolecular recognition events in liquids, and single molecule spectroscopy in vacuum.

Progress on micromechanical inertial guidance system

NASA Astrophysics Data System (ADS)

Poth, Tim; Elwell, John

1992-02-01

The development of a lightweight inertial measurement units (IMUs) is described which uses micromechanical gyroscopes and accelerometers. The IMU concept is described in terms of the silicon components of the instrument and the projected size, cost, and accuracies. The gyroscopes and accelerometers are chemically etched from wafers of single-crystal silicon that can yield up to 4000 single instruments from one 4-inch wafer. Particular emphasis is placed on the control-loop analysis, designing the electronics, and increasing the instrument signal. Attention is given to the development of a buffer amplifier that is fabricated on the same substrate as the instrument to minimize readout noise. These advances are important for improving the signal-to-noise ratio, and 12 hrs of testing data show that the control and readout electronics are responsible for most of the residual walk. The IMUs have potential applications in automobile skid detectors and airbags, GPS navigation systems, and in aerospace guidance systems where weight is a primary concern.

Diameter and location control of ZnO nanowires using electrodeposition and sodium citrate

NASA Astrophysics Data System (ADS)

Lifson, Max L.; Levey, Christopher G.; Gibson, Ursula J.

2013-10-01

We report single-step growth of spatially localized ZnO nanowires of controlled diameter to enable improved performance of piezoelectric devices such as nanogenerators. This study is the first to demonstrate the combination of electrodeposition with zinc nitrate and sodium citrate in the growth solution. Electrodeposition through a thermally-grown silicon oxide mask results in localization, while the growth voltage and solution chemistry are tuned to control the nanowire geometry. We observe a competition between lateral (relative to the (0001) axis) citrate-related morphology and voltage-driven vertical growth which enables this control. High aspect ratios result with either pure nitrate or nitrate-citrate mixtures if large voltages are used, but low growth voltages permit the growth of large diameter nanowires in solution with citrate. Measurements of the current density suggest a two-step growth process. An oxide mask blocks the electrodeposition, and suppresses nucleation of thermally driven growth, permitting single-step lithography on low cost p-type silicon substrates.

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, TImothy M.; Jhabvala, Christine A.; Leong, Edward; Costen, Nicholas P.; Sharp, Elmer; Adachi, Tomoko; Benford, Dominic

2012-01-01

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Silicon-on-ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Whitehead, A. B.; Zook, J. D.; Grung, B. L.; Heaps, J. D.; Schmit, F.; Schuldt, S. B.; Chapman, P. W.

1981-01-01

The technical feasibility of producing solar cell quality sheet silicon to meet the DOE 1986 cost goal of 70 cents/watt was investigated. The silicon on ceramic approach is to coat a low cost ceramic substrate with large grain polycrystalline silicon by unidirectional solidification of molten silicon. Results and accomplishments are summarized.

Fabrication of terahertz metamaterials using electrohydrodynamic jet printing for sensitive detection of yeast

NASA Astrophysics Data System (ADS)

Pradhipta Tenggara, Ayodya; Park, S. J.; Teguh Yudistira, Hadi; Ahn, Y. H.; Byun, Doyoung

2017-03-01

We demonstrated the fabrication of terahertz metamaterial sensor for the accurate and on-site detection of yeast using electrohydrodynamic jet printing, which is inexpensive, simple, and environmentally friendly. The very small sized pattern up to 5 µm-width of electrical split ring resonator unit structures could be printed on a large area on both a rigid substrate and flexible substrate, i.e. silicon wafer and polyimide film using the drop on demand technique to eject liquid ink containing silver nanoparticles. Experimental characterization and simulation were performed to study their performances in detecting yeast of different weights. It was shown that the metamaterial sensor fabricated on a flexible polyimide film had higher sensitivity by more than six times than the metamaterial sensor fabricated on a silicon wafer, due to the low refractive index of the PI substrate and due to the extremely thin substrate thickness which lowers the effective index further. The resonance frequency shift saturated when the yeast weights were 145 µg and 215 µg for metamaterial structures with gap size 6.5 µm fabricated on the silicon substrate and on the polyimide substrate, respectively.

Preparation of Mica and Silicon Substrates for DNA Origami Analysis and Experimentation

PubMed Central

Pillers, Michelle A.; Shute, Rebecca; Farchone, Adam; Linder, Keenan P.; Doerfler, Rose; Gavin, Corey; Goss, Valerie; Lieberman, Marya

2015-01-01

The designed nature and controlled, one-pot synthesis of DNA origami provides exciting opportunities in many fields, particularly nanoelectronics. Many of these applications require interaction with and adhesion of DNA nanostructures to a substrate. Due to its atomically flat and easily cleaned nature, mica has been the substrate of choice for DNA origami experiments. However, the practical applications of mica are relatively limited compared to those of semiconductor substrates. For this reason, a straightforward, stable, and repeatable process for DNA origami adhesion on derivatized silicon oxide is presented here. To promote the adhesion of DNA nanostructures to silicon oxide surface, a self-assembled monolayer of 3-aminopropyltriethoxysilane (APTES) is deposited from an aqueous solution that is compatible with many photoresists. The substrate must be cleaned of all organic and metal contaminants using Radio Corporation of America (RCA) cleaning processes and the native oxide layer must be etched to ensure a flat, functionalizable surface. Cleanrooms are equipped with facilities for silicon cleaning, however many components of DNA origami buffers and solutions are often not allowed in them due to contamination concerns. This manuscript describes the set-up and protocol for in-lab, small-scale silicon cleaning for researchers who do not have access to a cleanroom or would like to incorporate processes that could cause contamination of a cleanroom CMOS clean bench. Additionally, variables for regulating coverage are discussed and how to recognize and avoid common sample preparation problems is described. PMID:26274888

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Yu; School of Mechanical and Electrical Engineering, Wuhan Institute of Technology, Wuhan 430073; Guo, Zhiguang, E-mail: zguo@licp.cas.cn

Graphical abstract: A double-metal-assisted chemical etching method is employed to fabricate superhydrophobic surfaces, showing a good superhydrophobicity with the contact angle of about 170°, and the sliding angle of about 0°. Meanwhile, the potential formation mechanism about it is also presented. Highlights: ► A double-metal-assisted chemical etching method is employed to fabricate superhydrophobic surfaces. ► The obtained surfaces show good superhydrophobicity with a high contact angle and low sliding angle. ► The color of the etched substrate dark brown or black and it is so-called black silicon. -- Abstract: Silicon substrates treated by metal-assisted chemical etching have been studied formore » many years since they could be employed in a variety of electronic and optical devices such as integrated circuits, photovoltaics, sensors and detectors. However, to the best of our knowledge, the chemical etching treatment on the same silicon substrate with the assistance of two or more kinds of metals has not been reported. In this paper, we mainly focus on the etching time and finally obtain a series of superhydrophobic silicon surfaces with novel etching structures through two successive etching processes of Cu-assisted and Ag-assisted chemical etching. It is shown that large-scale homogeneous but locally irregular wire-like structures are obtained, and the superhydrophobic surfaces with low hysteresis are prepared after the modifications with low surface energy materials. It is worth noting that the final silicon substrates not only possess high static contact angle and low hysteresis angle, but also show a black color, indicating that the superhydrophobic silicon substrate has an extremely low reflectance in a certain range of wavelengths. In our future work, we will go a step further to discuss the effect of temperature, the size of Cu nanoparticles and solution concentration on the final topography and superhydrophobicity.« less

Silicon Micromachined Microlens Array for THz Antennas

NASA Technical Reports Server (NTRS)

Lee, Choonsup; Chattopadhyay, Goutam; Mehdi, IImran; Gill, John J.; Jung-Kubiak, Cecile D.; Llombart, Nuria

2013-01-01

5 5 silicon microlens array was developed using a silicon micromachining technique for a silicon-based THz antenna array. The feature of the silicon micromachining technique enables one to microfabricate an unlimited number of microlens arrays at one time with good uniformity on a silicon wafer. This technique will resolve one of the key issues in building a THz camera, which is to integrate antennas in a detector array. The conventional approach of building single-pixel receivers and stacking them to form a multi-pixel receiver is not suited at THz because a single-pixel receiver already has difficulty fitting into mass, volume, and power budgets, especially in space applications. In this proposed technique, one has controllability on both diameter and curvature of a silicon microlens. First of all, the diameter of microlens depends on how thick photoresist one could coat and pattern. So far, the diameter of a 6- mm photoresist microlens with 400 m in height has been successfully microfabricated. Based on current researchers experiences, a diameter larger than 1-cm photoresist microlens array would be feasible. In order to control the curvature of the microlens, the following process variables could be used: 1. Amount of photoresist: It determines the curvature of the photoresist microlens. Since the photoresist lens is transferred onto the silicon substrate, it will directly control the curvature of the silicon microlens. 2. Etching selectivity between photoresist and silicon: The photoresist microlens is formed by thermal reflow. In order to transfer the exact photoresist curvature onto silicon, there needs to be etching selectivity of 1:1 between silicon and photoresist. However, by varying the etching selectivity, one could control the curvature of the silicon microlens. The figure shows the microfabricated silicon microlens 5 x5 array. The diameter of the microlens located in the center is about 2.5 mm. The measured 3-D profile of the microlens surface has a smooth curvature. The measured height of the silicon microlens is about 280 microns. In this case, the original height of the photoresist was 210 microns. The change was due to the etching selectivity of 1.33 between photoresist and silicon. The measured surface roughness of the silicon microlens shows the peak-to-peak surface roughness of less than 0.5 microns, which is adequate in THz frequency. For example, the surface roughness should be less than 7 microns at 600 GHz range. The SEM (scanning electron microscope) image of the microlens confirms the smooth surface. The beam pattern at 550 GHz shows good directivity.

High performance and reusable SERS substrates using Ag/ZnO heterostructure on periodic silicon nanotube substrate

NASA Astrophysics Data System (ADS)

Lai, Yi-Chen; Ho, Hsin-Chia; Shih, Bo-Wei; Tsai, Feng-Yu; Hsueh, Chun-Hway

2018-05-01

Surface-enhanced Raman scattering (SERS) substrate with a higher surface area, enhanced light harvesting, multiple hot spots and strong electromagnetic field enhancements would exhibit enhanced Raman signals. Herein, the Ag nanoparticle/ZnO nanowire heterostructure decorated periodic silicon nanotube (Ag@ZnO@SiNT) substrate was proposed and fabricated. The proposed structure employed as SERS-active substrate was examined, and the results showed both the high performance in terms of high sensitivity and good reproducibility. Furthermore, the Ag@ZnO@SiNT substrate demonstrated the self-cleaning performance through the photocatalytic degradation of probed molecules upon UV-irradiation. The results showed that the proposed nanostructure had high performance, good reproducibility and reusability, and it is a promising SERS-active substrate for molecular sensing and cleaning.