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Sample records for solder interconnect integrity

  1. Computational continuum modeling of solder interconnects: Applications

    SciTech Connect

    Burchett, S.N.; Neilsen, M.K.; Frear, D.R.

    1997-04-01

    The most commonly used solder for electrical interconnections in electronic packages is the near eutectic 60Sn-40Fb alloy. This alloy has a number of processing advantages (suitable melting point of 183C and good wetting behavior). However, under conditions of cyclic strain and temperature (thermomechanical fatigue), the microstructure of this alloy undergoes a heterogeneous coarsening and failure process that makes the prediction of solder joint lifetime complex. A viscoplastic, microstructure dependent, constitutive model for solder, which is currently under development, was implemented into a finite element code. With this computational capability, the thermomechanical response of solder interconnects, including microstructural evolution, can be predicted. This capability was applied to predict the thermomechanical response of a mini ball grid array solder interconnect. In this paper, the constitutive model will first be briefly discussed. The results of computational studies to determine the thermomechanical response of a mini ball grid array solder interconnects then will be presented.

  2. Assessment of Solder Interconnect Integrity in Dismantled Electronic Components from N57 and B61 Tube-Type Radars

    SciTech Connect

    Rejent, J.A.; Vianco, P.T.; Woodrum, R.A.

    1999-07-01

    Aging analyses were performed on solder joints from two radar units: (1) a laboratory, N57 tube-type radar unit and (2) a field-returned, B61-0, tube-type radar unit. The cumulative temperature environments experienced by the units during aging were calculated from the intermetallic compound layer thickness and the mean Pb-rich phase particle size metrics for solder joints in the units, assuming an aging time of 35 years for both radars. Baseline aging metrics were obtained from a laboratory test vehicle assembled at AS/FM and T; the aging kinetics of both metrics were calculated from isothermal aging experiments. The N57 radar unit interconnect board solder joints exhibited very little aging. The eyelet solder joints did show cracking that most likely occurred at the time of assembly. The eyelet, SA1126 connector solder joints, showed some delamination between the Cu pad and underlying laminate. The B61 field-returned radar solder joints showed a nominal degree of aging. Cracking of the eyelet solder joints was observed. The Pb-rich phase particle measurements indicated additional aging of the interconnects as a result of residual stresses. Cracking of the terminal pole connector, pin-to-pin solder joint was observed; but it was not believed to jeopardize the electrical functionality of the interconnect. Extending the stockpile lifetime of the B61 tube-type radar by an additional 20 years would not be impacted by the reliability of the solder joints with respect to further growth of the intermetallic compound layer. Additional coarsening of the Pb-rich phase will increase the joints' sensitivity to thermomechanical fatigue.

  3. Computational continuum modeling of solder interconnects

    SciTech Connect

    Burchett, S.N.; Neilsen, M.K.; Frear, D.R.; Stephens, J.J.

    1997-03-01

    The most commonly used solder for electrical interconnections in electronic packages is the near eutectic 60Sn-40Pb alloy. This alloy has a number of processing advantages (suitable melting point of 183 C and good wetting behavior). However, under conditions of cyclic strain and temperature (thermomechanical fatigue), the microstructure of this alloy undergoes a heterogeneous coarsening and failure process that makes prediction of solder joint lifetime complex. A viscoplastic, microstructure dependent, constitutive model for solder which is currently in development was implemented into a finite element code. With this computational capability, the thermomechanical response of solder interconnects, including microstructural evolution, can be predicted. This capability was applied to predict the thermomechanical response of various leadless chip carrier solder interconnects to determine the effects of variations in geometry and loading. In this paper, the constitutive model will first be briefly discussed. The results of computational studies to determine the effect of geometry and loading variations on leadless chip carrier solder interconnects then will be presented.

  4. Life prediction modeling of solder interconnects for electronic systems

    SciTech Connect

    Frear, D.R.; Burchett, S.N.; Neilsen, M.K.

    1997-02-01

    A microstructurally-based computational simulation is presented that predicts the behavior and lifetime of solder interconnects for electronic applications. This finite element simulation is based on an internal state variable constitutive model that captures both creep and plasticity, and accounts for microstructural evolution. The basis of the microstructural evolution is a simple model that captures the grain size and microstructural defects in the solder. The mechanical behavior of the solder is incorporated into the model in the form of time-dependent viscoplastic equations derived from experimental creep tests. The unique aspect of this methodology is that the constants in the constitutive relations of the model are determined from experimental tests. This paper presents the constitutive relations and the experimental means by which the constants in the equations are determined. The fatigue lifetime of the solder interconnects is predicted using a damage parameter (or grain size) that is an output of the computer simulation. This damage parameter methodology is discussed and experimentally validated.

  5. Effect of grain orientation on mechanical properties and thermomechanical response of Sn-based solder interconnects

    SciTech Connect

    Chen, Hongtao; Yan, Bingbing; Yang, Ming; Ma, Xin; Li, Mingyu

    2013-11-15

    The thermomechanical response of Sn-based solder interconnects with differently oriented grains was investigated by electron backscattered diffraction technique under thermal cycling and thermal shock testing in this study. The results showed that deformation and cracking of solder interconnects have a close relationship with the unique characteristics of grain orientation and boundaries in each solder interconnect, and deformation was frequently confined within the high-angle grain boundaries. The micro Vickers hardness testing results showed that the hardness varied significantly depending on the grain orientation and structure, and deformation twins can be induced around the indents by the indentation testing. - Highlights: • Thermomechanical response shows a close relationship with the grain structure. • Deformation was frequently confined within the high-angle grain boundaries. • Different grain orientations exhibit different hardness. • Deformation twins can be induced around the indents in SAC105 solder interconnects.

  6. Evaluating the Impact of Dwell Time on Solder Interconnect Durability Under Bending Loads

    NASA Astrophysics Data System (ADS)

    Menon, Sandeep; Osterman, Michael; Pecht, Michael

    2015-11-01

    With the increasing portability and miniaturization of modern-day electronics, the mechanical robustness of these systems has become more of a concern. Existing standards for conducting mechanical durability tests of electronic assemblies include bend, shock/drop, vibration, and torsion. Although these standards provide insights into both cyclic fatigue and overstress damage incurred in solder interconnects (widely regarded as the primary mode of failure in electronic assemblies), they fail to address the impact of time- dependent (creep) behavior due to sustained mechanical loads on solder interconnect durability. It has been seen in previous studies that solder durability under thermal cycling loads is inversely proportional to the dwell time or hold time at either temperature extreme of the imposed temperature cycle. Fatigue life models, which include dwell time, have been developed for solder interconnects subject to temperature cycling. However, the fatigue life models that have been developed in the literature for solder interconnects under mechanical loads fail to address the influence of the duration of loading. In this study, solder interconnect test vehicles were subjected to cyclic mechanical bending with various dwell times in order to understand the impact of the duration of mechanical loads on solder interconnect durability. The solder interconnects examined in this study were formed with 2512 resistor packages using various solder compositions [tin-lead (Sn-Pb) and 96.5Sn-3Ag-0.5Cu (SAC305)]. To evaluate the impact of dwell time, the boards were tested with 0 s, 60 s, and 300 s of dwell time at both extremes of the loading profile. It was observed that an increase in the dwell time of the loading profile resulted in a decrease in the characteristic life of the solder interconnects. The decrease in fatigue life was attributed to increased creep damage as identified using finite-element simulations. An energy partitioning approach was then used to

  7. Advances in Pb-free solder microstructure control and interconnect design

    SciTech Connect

    Reeve, Kathlene N.; Holaday, John R.; Choquette, Stephanie M.; Anderson, Iver E.; Handwerker, Carol A.

    2016-06-09

    New electronics applications demanding enhanced performance and higher operating temperatures have led to continued research in the field of Pb-free solder designs and interconnect solutions. In this paper, recent advances in the microstructural design of Pb-free solders and interconnect systems were discussed by highlighting two topics: increasing β-Sn nucleation in Sn-based solders, and isothermally solidified interconnects using transient liquid phases. Issues in β-Sn nucleation in Sn-based solders were summarized in the context of Swenson’s 2007 review of the topic. Recent advancements in the areas of alloy composition manipulation, nucleating heterogeneities, and rapid solidification were discussed, and a proposal based on a multi-faceted solidification approach involving the promotion of constitutional undercooling and nucleating heterogeneities was outlined for future research. The second half of the paper analyzed two different approaches to liquid phase diffusion bonding as a replacement for high-Pb solders, one based on the application of the pseudo-binary Cu-Ni-Sn ternary system, and the other on a proposed thermodynamic framework for identifying potential ternary alloys for liquid phase diffusion bonding. Furthermore, all of the concepts reviewed relied upon the fundamentals of thermodynamics, kinetics, and solidification, to which Jack Smith substantially contributed during his scientific career.

  8. Advances in Pb-free solder microstructure control and interconnect design

    DOE PAGES

    Reeve, Kathlene N.; Holaday, John R.; Choquette, Stephanie M.; ...

    2016-06-09

    New electronics applications demanding enhanced performance and higher operating temperatures have led to continued research in the field of Pb-free solder designs and interconnect solutions. In this paper, recent advances in the microstructural design of Pb-free solders and interconnect systems were discussed by highlighting two topics: increasing β-Sn nucleation in Sn-based solders, and isothermally solidified interconnects using transient liquid phases. Issues in β-Sn nucleation in Sn-based solders were summarized in the context of Swenson’s 2007 review of the topic. Recent advancements in the areas of alloy composition manipulation, nucleating heterogeneities, and rapid solidification were discussed, and a proposal based onmore » a multi-faceted solidification approach involving the promotion of constitutional undercooling and nucleating heterogeneities was outlined for future research. The second half of the paper analyzed two different approaches to liquid phase diffusion bonding as a replacement for high-Pb solders, one based on the application of the pseudo-binary Cu-Ni-Sn ternary system, and the other on a proposed thermodynamic framework for identifying potential ternary alloys for liquid phase diffusion bonding. Furthermore, all of the concepts reviewed relied upon the fundamentals of thermodynamics, kinetics, and solidification, to which Jack Smith substantially contributed during his scientific career.« less

  9. Solder Interconnect Predictor (SIP) Software v. 0.5

    SciTech Connect

    VIANCO, PAUL; NEILSEN, MICHAEL; & REJENT, JEROME

    2008-11-19

    This software tool was developed for predicting the fatigue damage in a wide variety of 63Sn-37Pb solder joints used in electronics applications. This tool is based upon the unified creep plasticity damage model CompSIR developed at Sandia National Laboratories. The software can be used as a design tool for predicting the long term reliability of consumer, military and space electronics. Both service as well as accelerated testing environments can be addressed by the user. The mesh generating function provides the user with the greater versatility to explore different package and I/O configurations. For example, different solder joint geometries can be investigated to determine the effects of workmanship quality on reliability. Graphical user interfaces provide the user with easy data input screens as well as results profiles.

  10. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  11. Thermal compression chip interconnection using organic solderability preservative etched substrate by plasma processing.

    PubMed

    Cho, Sung-Won; Choi, JoonYoung; Chung, Chin-Wook

    2014-12-01

    The solderability of copper organic solderbility preservative (CuOSP) finished substrate was enhanced by the plasma etching. To improve the solderability of TC interconnection with the CuOSP finished substrate, the plasma etching process is used. An Oxygen-Hydrogen plasma treatment process is performed to remove OSP material. To prevent the oxidation by oxygen plasma treatment, hydrogen reducing process is also performed before TC interconnection process. The thickness of OSP material after plasma etching is measured by optical reflection method and the component analysis by Auger Electron Spectroscopy is performed. From the lowered thickness, the bonding force of TC interconnection after OSP etching process is lowered. Also the electrical open/short test was performed after assembling the completed semiconductor packaging. The improved yield due to the plasma etching process is achieved.

  12. A statistical mechanics model to predict electromigration induced damage and void growth in solder interconnects

    NASA Astrophysics Data System (ADS)

    Wang, Yuexing; Yao, Yao; Keer, Leon M.

    2017-02-01

    Electromigration is an irreversible mass diffusion process with damage accumulation in microelectronic materials and components under high current density. Based on experimental observations, cotton type voids dominate the electromigration damage accumulation prior to cracking in the solder interconnect. To clarify the damage evolution process corresponding to cotton type void growth, a statistical model is proposed to predict the stochastic characteristic of void growth under high current density. An analytical solution of the cotton type void volume growth over time is obtained. The synchronous electromigration induced damage accumulation is predicted by combining the statistical void growth and the entropy increment. The electromigration induced damage evolution in solder joints is developed and applied to verify the tensile strength deterioration of solder joints due to electromigration. The predictions agree well with the experimental results.

  13. Carboxylate-Passivated Silver Nanoparticles and Their Application to Sintered Interconnection: A Replacement for High Temperature Lead-Rich Solders

    NASA Astrophysics Data System (ADS)

    Ogura, Hiroshi; Maruyama, Minoru; Matsubayashi, Ryo; Ogawa, Tetsuya; Nakamura, Shigeyoshi; Komatsu, Teruo; Nagasawa, Hiroshi; Ichimura, Akio; Isoda, Seiji

    2010-08-01

    Lead-free silver nanoparticle pastes have been tested as a replacement for high temperature lead-rich solders used in electronic manufacturing. The pastes contain a small amount of solvent, and primarily consist of submicron-silver powder and passivated silver nanoparticles. The nanoparticles were synthesized from Ag2CO3 and a long-chain alcohol by a method that produced a passivating layer consisting almost exclusively of the carboxylate of the reactant alcohol. The pastes were used to connect a silicon diode chip to copper bases without applied pressure when sintered at 350°C under nitrogen. Diode packages made with sintered silver interconnects had electrical and thermal properties equal to those with lead-soldered interconnects, even after 3000 thermal cycles between -55°C and +150°C. The mechanical strength was half that of lead-rich solder joints, but still strong enough for practical use.

  14. Investigation Of The Effects Of Reflow Profile Parameters On Lead-free Solder Bump Volumes And Joint Integrity

    NASA Astrophysics Data System (ADS)

    Amalu, E. H.; Lui, Y. T.; Ekere, N. N.; Bhatti, R. S.; Takyi, G.

    2011-01-01

    The electronics manufacturing industry was quick to adopt and use the Surface Mount Technology (SMT) assembly technique on realization of its huge potentials in achieving smaller, lighter and low cost product implementations. Increasing global customer demand for miniaturized electronic products is a key driver in the design, development and wide application of high-density area array package format. Electronic components and their associated solder joints have reduced in size as the miniaturization trend in packaging continues to be challenged by printing through very small stencil apertures required for fine pitch flip-chip applications. At very narrow aperture sizes, solder paste rheology becomes crucial for consistent paste withdrawal. The deposition of consistent volume of solder from pad-to-pad is fundamental to minimizing surface mount assembly defects. This study investigates the relationship between volume of solder paste deposit (VSPD) and the volume of solder bump formed (VSBF) after reflow, and the effect of reflow profile parameters on lead-free solder bump formation and the associated solder joint integrity. The study uses a fractional factorial design (FFD) of 24-1 Ramp-Soak-Spike reflow profile, with all main effects and two-way interactions estimable to determine the optimal factorial combination. The results from the study show that the percentage change in the VSPD depends on the combination of the process parameters and reliability issues could become critical as the size of solder joints soldered on the same board assembly vary greatly. Mathematical models describe the relationships among VSPD, VSBF and theoretical volume of solder paste. Some factors have main effects across the volumes and a number of interactions exist among them. These results would be useful for R&D personnel in designing and implementing newer applications with finer-pitch interconnect.

  15. INTERCONNECTIONS BETWEEN HUMAN HEALTH AND ECOLOGICAL INTEGRITY

    EPA Science Inventory

    Interconnections between Human Health and Ecological Integrity emanates from a June 2000 Pellston Workshop in Snowbird, Utah, USA. Jointly sponsored by the Society of Environmental Toxicology and Chemistry (SETAC) and the Society of Toxicology (SOT), the workshop was motivated by...

  16. Self-assembly of Sn-3Ag-0.5Cu Solder in Thermoplastic Resin Containing Carboxyl Group and its Interconnection

    NASA Astrophysics Data System (ADS)

    Miyauchi, Kazuhiro; Yamashita, Yukihiko; Suzuki, Naoya; Takano, Nozomu

    2014-09-01

    The self-assembly of solder powder on pads is attractive as a novel interconnection method between chips and substrates. However, the solder used in this method is limited to Sn-58Bi and Sn-52In. In contrast, Sn-3Ag-0.5Cu has been relatively less studied despite its wide use as a lead-free solder in assembling semiconductor packages. Hence, here, polymeric materials incorporating Sn-3Ag-0.5Cu solder powder were investigated for the self-assembly of the solder on pads at temperatures up to 260°C in a lead-free reflow process. The self-assembly of the solder was observed with an optical microscope through transparent glass chips placed on substrates covered with the polymeric materials incorporating the solder powder. Differential scanning calorimetry measurements were performed to confirm the behaviors of the reaction of the resins and the melting of the solder. When epoxy resin with a fluxing additive was used as a matrix, self-assembly of the solder was prevented by the cross-linking reaction. Conversely, when thermoplastic resin containing carboxyl groups was used as a matrix, the self-assembly of solder was successfully achieved in the absence of fluxing additives. The shear strength of interconnection using reflowfilm with lamination was sufficient and significantly increased during the reflow process. However, the shear strength of the reflowfilm showed cohesive failure, possibly because of the brittle intermetallic compounds (Ag3Sn, Au4Sn) network in bulk was lower than that of conventional solder paste that showed interfacial failure after the reflow process with a rapid cooling rate.

  17. Microcantilever Fracture Testing of Intermetallic Cu3Sn in Lead-Free Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Philippi, Bastian; Matoy, Kurt; Zechner, Johannes; Kirchlechner, Christoph; Dehm, Gerhard

    2017-01-01

    Driven by legislation and the abolishment of harmful and hazardous lead-containing solders, lead-free replacement materials are in continuous development. Assessment of the mechanical properties of intermetallic phases such as Cu3Sn that evolve at the interface between solder and copper metalization is crucial to predict performance and meet the high reliability demands in typical application fields of microelectronics. While representative material parameters and fracture properties are required to assess mechanical behavior, indentation-based testing produces different results depending on the sample type. In this work, focused ion beam machined cantilevers were used to unravel the impact of microstructure on the fracture behavior of Sn-Ag-Cu lead-free solder joints. Fracture testing on notched cantilevers showed brittle fracture for Cu3Sn. Unnotched samples allowed measurement of the fracture stress, to estimate the critical defect size in unnotched Cu3Sn microcantilevers.

  18. Microcantilever Fracture Testing of Intermetallic Cu3Sn in Lead-Free Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Philippi, Bastian; Matoy, Kurt; Zechner, Johannes; Kirchlechner, Christoph; Dehm, Gerhard

    2017-03-01

    Driven by legislation and the abolishment of harmful and hazardous lead-containing solders, lead-free replacement materials are in continuous development. Assessment of the mechanical properties of intermetallic phases such as Cu3Sn that evolve at the interface between solder and copper metalization is crucial to predict performance and meet the high reliability demands in typical application fields of microelectronics. While representative material parameters and fracture properties are required to assess mechanical behavior, indentation-based testing produces different results depending on the sample type. In this work, focused ion beam machined cantilevers were used to unravel the impact of microstructure on the fracture behavior of Sn-Ag-Cu lead-free solder joints. Fracture testing on notched cantilevers showed brittle fracture for Cu3Sn. Unnotched samples allowed measurement of the fracture stress, to estimate the critical defect size in unnotched Cu3Sn microcantilevers.

  19. Laser soldering of Sn plated brass integrator assembly housings

    NASA Astrophysics Data System (ADS)

    Keicher, D. M.; Poulter, G. A.; Sorensen, N. R.

    1993-09-01

    The high conductivity provided by solder closure joints of component housings is sometimes required to ensure electrical shielding of the components contained within. However, using a soldering iron to produce the solder joints can lead to charring of the insulating materials within the housing. To overcome this problem, the localized heating characteristics of laser soldering can be exploited. The feasibility of laser soldering Sn plated brass housings with a CW Nd:YAG laser has been investigated. It has been determined that laser soldering of these housings using a low solids solder flux is a viable technique and will minimize the amount of heat input to the enclosed electronic components. Metallographic analysis has shown good wetting of the solder on the housing components. Accelerated aging experiments indicate that no significant corrosion potential due to solder flux residues exists. Although a low solids flux was used to make the joints, initial results indicate that a fluxless technique can be developed to eliminate fluxes completely.

  20. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  1. Integrated nanophotonic devices for optical interconnections

    NASA Astrophysics Data System (ADS)

    Huang, Yidong; Feng, Xue; Cui, Kaiyu; Li, Yongzhuo; Wang, Yu

    2016-03-01

    Nanostructure is an effective solution for realizing optoelectronic devices with compact size and high performances simultaneously. This paper reports our research progress on integrated nanophotonic devices for optical interconnections. We proposed a parent-sub micro ring structure for optical add-drop multiplexer (OADM) with compact footprint, large free spectral range, and uniform channel spacing. All eight channels can be multiplexed and de-multiplexed with 2.6 dB drop loss, 0.36 nm bandwidth (>40 GHz), -20 dB channel crosstalk, and high thermal tuning efficiency of 0.15 nm/mW. A novel principle of optical switch was proposed and demonstrated based on the coupling of the defect modes in photonic crystal waveguide. Switching functionality with bandwidth up to 24 nm and extinction ratio in excess of 15 dB over the entire bandwidth was achieved, while the footprint was only 8 μm×17.6 μm. We proposed an optical orbital angular momentum (OAM) coding and decoding method to increase the data-carrying capacity of wireless optical interconnect. An integrated OAM emitter, where the topological charge can be continuously varied from -4 to 4 was realized. Also we studied ultrafast modulated nLED as the integrated light source for optical interconnections using a nanobeam cavity with stagger holes.

  2. Silicon hybrid wafer scale integration interconnect evaluation

    NASA Astrophysics Data System (ADS)

    Lyke, James C.

    1989-12-01

    The electrical characteristics of interconnections that have been proposed for use in silicon hybrid wafer scale integration (WSI) approaches were investigated. The study was based on a set of 5 inch test wafers, containing various interconnection structures previously designed at AFIT. Two test wafers used a special polyimide dielectric, while a third was composed of a benzocyclobutene (BCB). The investigated structures represented 10 cm length aluminum, coupled, stripline-like transmission lines. The metrics used included continuity measurements, ac measurement of the characteristic impedance and coupling levels, and pulsed-signal response measurements. Continuity results indicated transmission and leakage failures in all wafers, although the failure mechanisms were sometimes wafer-specific. The characteristic impedance measurement technique was flawed, but revealed interesting information concerning the driving-point impedances of the structures. Most coupled structures manifested coupling responses which were consistent in shape with theoretical estimates, but higher in magnitude by 10 to 20 dB. All structures revealed coupling levels lower than -25 dB. Despite correlation difficulties, the results implied that transmission line behavior is manifested in WSIC interconnections.

  3. Sn-Ag-Cu Nanosolders: Solder Joints Integrity and Strength

    NASA Astrophysics Data System (ADS)

    Roshanghias, Ali; Khatibi, Golta; Yakymovych, Andriy; Bernardi, Johannes; Ipser, Herbert

    2016-08-01

    Although considerable research has been dedicated to the synthesis and characterization of lead-free nanoparticle solder alloys, only very little has been reported on the reliability of the respective joints. In fact, the merit of nanoparticle solders with depressed melting temperatures close to the Sn-Pb eutectic temperature has always been challenged when compared with conventional solder joints, especially in terms of inferior solderability due to the oxide shell commonly present on the nanoparticles, as well as due to compatibility problems with common fluxing agents. Correspondingly, in the current study, Sn-Ag-Cu (SAC) nanoparticle alloys were combined with a proper fluxing vehicle to produce prototype nanosolder pastes. The reliability of the solder joints was successively investigated by means of electron microscopy and mechanical tests. As a result, the optimized condition for employing nanoparticles as a competent nanopaste and a novel procedure for surface treatment of the SAC nanoparticles to diminish the oxide shell prior to soldering are being proposed.

  4. Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

    DTIC Science & Technology

    1989-12-01

    the assessment of the current state -of-the-art in electromagnetic analyses to determine its applicability to NVSI interconnections. Weak links or... states that transmission line effects are clearly exhibited when the physical length of any component of an electrical system (include interconnections...assumedl for coniduc- tois and dielectrics. Furthermore, all geometric distances arc assuimedl to bie uniform. unless otherwise stated . This assertion

  5. Impact of Cooling Rate-Induced Recrystallization on High G Mechanical Shock and Thermal Cycling in Sn-Ag-Cu Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Lee, Tae-Kyu; Bieler, Thomas R.; Kim, Choong-Un

    2016-01-01

    The mechanical stability and thermo-mechanical fatigue performance of solder joints with low silver content Sn-1.0Ag-0.5Cu (wt.%) (SAC105) alloy based on different cooling rates are investigated in high G level shock environment and thermal cycling conditions. The cooling rate-controlled samples ranging from 1°C/min to 75°C/min cooling rate, not only show differences in microstructure, where a fine poly-granular microstructure develops in the case of fast cooling versus normal cooling, but also show various shock performances based on the microstructure changes. The fast cooling rate improves the high G shock performance by over 90% compared to the normal cooled SAC105 alloy air-cooling environment commonly used after assembly reflow. The microstructure effect on thermal cycling performance is also discussed, which is analyzed based on the Sn grain orientation, interconnect stability, and solder joint bulk microstructure.

  6. Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

    NASA Technical Reports Server (NTRS)

    Mandal, R. P.

    1976-01-01

    Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

  7. Variational Integrators for Interconnected Lagrange-Dirac Systems

    NASA Astrophysics Data System (ADS)

    Parks, Helen; Leok, Melvin

    2017-02-01

    Interconnected systems are an important class of mathematical models, as they allow for the construction of complex, hierarchical, multiphysics, and multiscale models by the interconnection of simpler subsystems. Lagrange-Dirac mechanical systems provide a broad category of mathematical models that are closed under interconnection, and in this paper, we develop a framework for the interconnection of discrete Lagrange-Dirac mechanical systems, with a view toward constructing geometric structure-preserving discretizations of interconnected systems. This work builds on previous work on the interconnection of continuous Lagrange-Dirac systems (Jacobs and Yoshimura in J Geom Mech 6(1):67-98, 2014) and discrete Dirac variational integrators (Leok and Ohsawa in Found Comput Math 11(5), 529-562, 2011). We test our results by simulating some of the continuous examples given in Jacobs and Yoshimura (2014).

  8. Failure Analysis of Board-Level Sn-Ag-Cu Solder Interconnections Under JEDEC Standard Drop Test

    NASA Astrophysics Data System (ADS)

    Zhang, Bo; Xi, Jing Si; Liu, Pin Kuan; Ding, Han

    2013-09-01

    This work investigates the board-level drop reliability of printed circuit boards (PCBs) assembled using three chip-size packages subjected to Joint Electron Device Engineering Council (JEDEC) standard drop test condition B. The acceleration and dynamic strain responses at several locations of the board-level package in the time and frequency domain are comprehensively investigated. The results in the time domain suggest that the dynamic response of the board-level package has two phases: forced vibration and free vibration. The maximum response occurs at the first half free vibration cycle. The acceleration response at the center of the PCB is larger than at the edges, whereas the dynamic strain response is just the opposite. The results in the frequency domain show that the first mode is fundamental. In addition, failure analysis is performed using the dye-and-pry test and cross-section test, suggesting that the brittle cracking occurs at the layer between the integrated circuit (IC) pad and the solder, not only through intermetallic compound (IMC) but also along the surface between the IC pad and IMC.

  9. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2003-11-04

    The present invention is directed to an improved electrochemical energy storage device. The electrochemical energy storage device includes a number of solid-state, thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. Fuses and various electrical and electromechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  10. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2004-09-28

    An electrochemical energy storage device includes a number of solid-state thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. Fuses and various electrical and electro-mechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  11. Metallic Nanowire Interconnections for Integrated Circuit Fabrication

    NASA Technical Reports Server (NTRS)

    Ng, Hou Tee (Inventor); Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

    2007-01-01

    A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

  12. Updating Interconnection Screens for PV System Integration

    SciTech Connect

    Coddington, M.; Mather, B.; Kroposki, B.; Lynn, K.; Razon, A.; Ellis, A.; Hill, R.; Key, T.; Nicole, K.; Smith, J.

    2012-02-01

    This white paper evaluates the origins and usefulness of the capacity penetration screen, offer short-term solutions which could effectively allow fast-track interconnection to many PV system applications, and considers longer-term solutions for increasing PV deployment levels in a safe and reliable manner while reducing or eliminating the emphasis on the penetration screen. Short-term and longer-term alternatives approaches are offered as examples; however, specific modifications to screening procedures should be discussed with stakeholders and must ultimately be adopted by state and federal regulatory bodies.

  13. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  14. Interconnection of thermal parameters, microstructure and mechanical properties in directionally solidified Sn–Sb lead-free solder alloys

    SciTech Connect

    Dias, Marcelino; Costa, Thiago; Rocha, Otávio; Spinelli, José E.; Cheung, Noé; Garcia, Amauri

    2015-08-15

    Considerable effort is being made to develop lead-free solders for assembling in environmental-conscious electronics, due to the inherent toxicity of Pb. The search for substitute alloys of Pb–Sn solders has increased in order to comply with different soldering purposes. The solder must not only meet the expected levels of electrical performance but may also have appropriate mechanical strength, with the absence of cracks in the solder joints. The Sn–Sb alloy system has a range of compositions that can be potentially included in the class of high temperature solders. This study aims to establish interrelations of solidification thermal parameters, microstructure and mechanical properties of Sn–Sb alloys (2 wt.%Sb and 5.5 wt.%Sb) samples, which were directionally solidified under cooling rates similar to those of reflow procedures in industrial practice. A complete high-cooling rate cellular growth is shown to be associated with the Sn–2.0 wt.%Sb alloy and a reverse dendrite-to-cell transition is observed for the Sn–5.5 wt.%Sb alloy. Strength and ductility of the Sn–2.0 wt.%Sb alloy are shown not to be affected by the cellular spacing. On the other hand, a considerable variation in these properties is associated with the cellular region of the Sn–5.5 wt.%Sb alloy casting. - Graphical abstract: Display Omitted - Highlights: • The microstructure of the Sn–2 wt.%Sb alloy is characterized by high-cooling rates cells. • Reverse dendrite > cell transition occurs for Sn–5.5 wt.%Sb alloy: cells prevail for cooling rates > 1.2 K/s. • Sn–5.5 wt.%Sb alloy: the dendritic region occurs for cooling rates < 0.9 K/s. • Sn–5.5 wt.%Sb alloy: tensile properties are improved with decreasing cellular spacing.

  15. Impact of 5% NaCl Salt Spray Pretreatment on the Long-Term Reliability of Wafer-Level Packages with Sn-Pb and Sn-Ag-Cu Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Liu, Bo; Lee, Tae-Kyu; Liu, Kuo-Chuan

    2011-10-01

    Understanding the sensitivity of Pb-free solder joint reliability to various environmental conditions, such as corrosive gases, low temperatures, and high-humidity environments, is a critical topic in the deployment of Pb-free products in various markets and applications. The work reported herein concerns the impact of a marine environment on Sn-Pb and Sn-Ag-Cu interconnects. Both Sn-Pb and Sn-Ag-Cu solder alloy wafer-level packages, with and without pretreatment by 5% NaCl salt spray, were thermally cycled to failure. The salt spray test did not reduce the characteristic lifetime of the Sn-Pb solder joints, but it did reduce the lifetime of the Sn-Ag-Cu solder joints by over 43%. Although both materials showed strong resistance to corrosion, the localized nature of the corroded area at critical locations in the solder joint caused significant degradation in the Sn-Ag-Cu solder joints. The mechanisms leading to these results as well as the extent, microstructural evolution, and dependency of the solder alloy degradation are discussed.

  16. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2000-01-01

    The present invention is directed to an improved electrochemical energy storage device. The electrochemical energy storage device includes a number of solid-state, thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. In one embodiment, a sheet of conductive material is processed by employing a known milling, stamping, or chemical etching technique to include a connection pattern which provides for flexible and selective interconnecting of individual electrochemical cells within the housing, which may be a hermetically sealed housing. Fuses and various electrical and electro-mechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  17. Assessment of circuit board surface finishes for electronic assembly with lead-free solders

    SciTech Connect

    Ray, U.; Artaki, I.; Finley, D.W.; Wenger, G.M.; Pan, T.; Blair, H.D.; Nicholson, J.M.; Vianco, P.T.

    1996-10-01

    The suitability of various metallic printed wiring board surface finishes was assessed for new technology applications that incorporate assembly with Lead-free solders. The manufacture of a lead-free product necessitates elimination of lead (Pb) from the solder, the circuit board as well as the component lead termination. It is critical however for the selected interconnect Pb-free solder and the corresponding printed wiring board (PWB) and component lead finishes to be mutually compatible. Baseline compatibility of select Pb-free solders with Pb containing PWB surface finish and components was assessed. This was followed by examining the compatibility of the commercially available CASTIN{trademark} (SnAgCuSb) Pb-free solder with a series of PWB metallic finishes: Ni/Au, Ni/Pd, and Pd/Cu. The compatibility was assessed with respect to assembly performance, solder joint integrity and long term attachment reliability. Solder joint integrity and mechanical behavior of representative 50 mil pitch 20I/O SOICs was determined before and after thermal stress. Mechanical pull test studies demonstrated that the strength of SnAgCuSb solder interconnections is notably greater than that of SnPb interconnections.

  18. Effect of Isothermal Aging on the Long-Term Reliability of Fine-Pitch Sn-Ag-Cu and Sn-Ag Solder Interconnects With and Without Board-Side Ni Surface Finish

    NASA Astrophysics Data System (ADS)

    Lee, Tae-Kyu; Duh, Jeng-Gong

    2014-11-01

    The combined effects on long-term reliability of isothermal aging and chemically balanced or unbalanced surface finish have been investigated for fine-pitch ball grid array packages with Sn-3.0Ag-0.5Cu (SAC305) (wt.%) and Sn-3.5Ag (SnAg) (wt.%) solder ball interconnects. Two different printed circuit board surface finishes were selected to compare the effects of chemically balanced and unbalanced structure interconnects with and without board-side Ni surface finish. NiAu/solder/Cu and NiAu/solder/NiAu interconnects were isothermally aged and thermally cycled to evaluate long-term thermal fatigue reliability. Weibull plots of the combined effects of each aging condition and each surface finish revealed lifetime for NiAu/SAC305/Cu was reduced by approximately 40% by aging at 150°C; less degradation was observed for NiAu/SAC305/NiAu. Further reduction of characteristic life-cycle number was observed for NiAu/SnAg/NiAu joints. Microstructure was studied, focusing on its evolution near the board and package-side interfaces. Different mechanisms of aging were apparent under the different joint configurations. Their effects on the fatigue life of solder joints are discussed.

  19. A Novel and Facile Method to Prepare Integrated Electrospun Nanofibrous Membrane with Soldered Junctions.

    PubMed

    Shen, Lingdi; Chen, Jiajia; Hong, Guishan; Wang, Xuefen

    2016-01-01

    Integrated electrospun nanofibrous membrane was prepared by creating soldered junctions between nanofibers via a facile strategy. Polyacrylonitrile (PAN) mixed with poly(vinylidene fluoride) (PVDF) at different ratios of PVDF were prepared in N,N'-dimethyl formamide (DMF), then electrospun to fabricate PAN/PVDF membranes. PVDF can form microgels in DMF which slows down volatile speed of DMF and affects the solidification of PAN/PVDF nanofibers. The resulting membranes were investigated by Fourier transform infrared spectroscopy, scanning electron microscopy, dynamic water contact angle and tensile testing to confirm the morphology and mechanical properties. Soldered junctions were observed between nanofibers with the increase of PVDF content. These junctions made the membrane integrated and greatly enhanced tensile strength from 5.1 to 8.1 MPa (increased by ~60%) and tensile modulus from 49.4 to 117.9 MPa (increased by ~139%) without compromising porosity when the content of PVDF increased from 0 to 60 wt%.

  20. Use of Fiber Optic Interconnects for Signal Integrity

    NASA Astrophysics Data System (ADS)

    Phal, Yamuna D.; Phal, Deovrat D.

    2016-05-01

    Signal integrity (SI) is always a concern when it comes to high-speed data transmission. Even in space, there is a need for high-speed data transmission such as in the communication systems, monitoring various sub- systems and for other on-board experiments and applications.From Electromagneticperspective, using fiber-optic interconnect is highly recommended to avoid interference issues. This field has been explored for quite some time now, but mostly limited to applications that are on earth. Using these interconnects for harsh and extreme environments i.e. in space, requires reliability and ruggedness of interconnects and the system.This study suggests methods for optical fiber based communication systems for internal unit communication, communication within various instruments, as well as inter-board communication. A conclusion in terms of what areas need to be explored for enabling high-speed data transmission for space applications would be discussed in details. This study also explores and compares the existing technologies in the fiber-optic interconnects for space applications.

  1. Time And Temperature Dependent Micromechanical Properties Of Solder Joints For 3D-Package Integration

    NASA Astrophysics Data System (ADS)

    Roellig, Mike; Meier, Karsten; Metasch, Rene

    2010-11-01

    The recent development of 3D-integrated electronic packages is characterized by the need to increase the diversity of functions and to miniaturize. Currently many 3D-integration concepts are being developed and all of them demand new materials, new designs and new processing technologies. The combination of simulation and experimental investigation becomes increasingly accepted since simulations help to shorten the R&D cycle time and reduce costs. Numerical calculations like the Finite-Element-Method are strong tools to calculate stress conditions in electronic packages resulting from thermal strains due to the manufacturing process and environmental loads. It is essential for the application of numerical calculations that the material data is accurate and describes sufficiently the physical behaviour. The developed machine allows the measurement of time and temperature dependent micromechanical properties of solder joints. Solder joints, which are used to mechanically and electrically connect different packages, are physically measured as they leave the process. This allows accounting for process influences, which may change material properties. Additionally, joint sizes and metallurgical interactions between solder and under bump metallization can be respected by this particular measurement. The measurement allows the determination of material properties within a temperature range of 20° C-200° C. Further, the time dependent creep deformation can be measured within a strain-rate range of 10-31/s-10-81/s. Solder alloys based on Sn-Ag/Sn-Ag-Cu with additionally impurities and joint sizes down to O/ 200 μm were investigated. To finish the material characterization process the material model coefficient were extracted by FEM-Simulation to increase the accuracy of data.

  2. Heat Lamps Solder Solar Array Quickly

    NASA Technical Reports Server (NTRS)

    Coyle, P. J.; Crouthamel, M. S.

    1982-01-01

    Interconnection tabs in a nine-solar-cell array have been soldered simultaneously with radiant heat. Cells and tabs are held in position for soldering by sandwiching them between compliant silicone-rubber vacuum platen and transparent polyimide sealing membrane. Heat lamps warm cells, producing smooth, flat solder joints of high quality.

  3. Integration of a waveguide self-electrooptic effect device and a vertically coupled interconnect waveguide

    DOEpatents

    Vawter, G. Allen

    2008-02-26

    A self-electrooptic effect device ("SEED") is integrated with waveguide interconnects through the use of vertical directional couplers. Light initially propagating in the interconnect waveguide is vertically coupled to the active waveguide layer of the SEED and, if the SEED is in the transparent state, the light is coupled back to the interconnect waveguide.

  4. Development of the Regimes of Semiautomatic Contact Soldering

    NASA Astrophysics Data System (ADS)

    Shtennikov, V. N.

    2015-01-01

    The influence of the soldering rod length on the contact soldering temperature has been studied. The results of investigations were taken as a basis for incorporating a high-speed semiautomatic regime of soldering integrated circuits with planar leads to multilayer printed circuit boards. It has been established that to ensure an optimum soldering temperature it is necessary to take account of the temperature of the soldering rod before soldering, its length and diameter, and the soldering time when the rod is short.

  5. Solar cell array interconnects

    DOEpatents

    Carey, P.G.; Thompson, J.B.; Colella, N.J.; Williams, K.A.

    1995-11-14

    Electrical interconnects are disclosed for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb-Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value. 4 figs.

  6. Solar cell array interconnects

    DOEpatents

    Carey, Paul G.; Thompson, Jesse B.; Colella, Nicolas J.; Williams, Kenneth A.

    1995-01-01

    Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb-Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value.

  7. Characterization of the Effect of thermal Cycling on the Signal Integrity of Interconnect Structures used in 3D Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Kandel, Binayak

    2012-03-01

    The performance and reliability of the microelectronic devices are significantly influenced by the condition of interconnects in Integrated Circuits (IC). These interconnects serve primarily as signal transmission pathways in IC. Good interconnects enable free flow of electrical signals with low impedance. However, microelectronic devices are continuously subjected to fluctuating temperature conditions during their lifetime, which affect the signal integrity of interconnects. Therefore, this project takes a look at the effect of repeated temperature cycling on the reliability and performance of interconnects. Two types of interconnects: Back-End-of-Line (BEOL) and Through-Si-Via (TSV) were studied. We simulate the real world conditions by applying repeated temperature cycling, and use an RF network analyzer to extract the reflection and transmission signal characteristics of the interconnects. The mean-time-to-failure is determined upon their breakdown which is followed by the failure analysis to determine the root cause of failure.

  8. Environmental toxicology: Interconnections between human health and ecological integrity

    EPA Science Inventory

    This presentation will discuss what has made a career in environmental toxicology rewarding, environmental and scientific challenges for the 21st century, paradigm shift in regulatory toxicology, adverse outcome framework, interconnections between human health and ecological inte...

  9. Solder Mounting Technologies for Electronic Packaging

    SciTech Connect

    VIANCO, PAUL T.

    1999-09-23

    Soldering provides a cost-effective means for attaching electronic packages to circuit boards using both small scale and large scale manufacturing processes. Soldering processes accommodate through-hole leaded components as well as surface mount packages, including the newer area array packages such as the Ball Grid Arrays (BGA), Chip Scale Packages (CSP), and Flip Chip Technology. The versatility of soldering is attributed to the variety of available solder alloy compositions, substrate material methodologies, and different manufacturing processes. For example, low melting temperature solders are used with temperature sensitive materials and components. On the other hand, higher melting temperature solders provide reliable interconnects for electronics used in high temperature service. Automated soldering techniques can support large-volume manufacturing processes, while providing high reliability electronic products at a reasonable cost.

  10. Induction soldering of photovoltaic system components

    SciTech Connect

    Kumaria, Shashwat; de Leon, Briccio

    2015-11-17

    A method comprises positioning a pair of photovoltaic wafers in a side-by-side arrangement. An interconnect is placed on the pair of wafers such that the interconnect overlaps both wafers of the pair, solder material being provided between the interconnect and the respective wafers. A solder head is then located adjacent the interconnect, and the coil is energized to effect inductive heating of the solder material. The solder head comprises an induction coil shaped to define an eye, and a magnetic field concentrator located at least partially in the eye of the coil. The magnetic field concentrator defines a passage extending axially through the eye of the coil, and may be of a material with a high magnetic permeability.

  11. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

    PubMed

    Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

    2008-02-01

    Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

  12. Electromigration-induced back stress in critical solder length for three-dimensional integrated circuits

    SciTech Connect

    Huang, Y. T.; Hsu, H. H.; Wu, Albert T.

    2014-01-21

    Because of the miniaturization of electronic devices, the reliability of electromigration has become a major concern when shrinking the solder dimensions in flip-chip joints. Fast reaction between solders and electrodes causes intermetallic compounds (IMCs) to form, which grow rapidly and occupy entire joints when solder volumes decrease. In this study, U-grooves were fabricated on Si chips as test vehicles. An electrode-solder-electrode sandwich structure was fabricated by using lithography and electroplating. Gaps exhibiting well-defined dimensions were filled with Sn3.5Ag solders. The gaps between the copper electrodes in the test sample were limited to less than 15 μm to simulate microbumps. The samples were stressed at various current densities at 100 °C, 125 °C, and 150 °C. The morphological changes of the IMCs were observed, and the dimensions of the IMCs were measured to determine the kinetic growth of IMCs. Therefore, this study focused on the influence of back stress caused by microstructural evolution in microbumps.

  13. Stability of Flip-Chip Interconnects Assembled with Al/Ni(V)/Cu-UBM and Eutectic Pb-Sn Solder During Exposure to High-Temperature Storage

    NASA Astrophysics Data System (ADS)

    Osenbach, J.; Amin, A.; Bachman, M.; Baiocchi, F.; Bitting, D.; Crouthamel, D.; Delucca, J.; Gerlach, D.; Goodell, J.; Peridier, C.; Stahley, M.; Weachock, R.

    2009-02-01

    The thermal stability of flip-chip solder joints made with trilayer Al/Ni(V)/Cu underbump metalization (UBM) and eutectic Pb-Sn solder connected to substrates with either electroless Ni(P)-immersion gold (ENIG) or Pb-Sn solder on Cu pad (Cu-SOP) surface finish was determined. The ENIG devices degraded more than 50 times faster than the Cu-SOP devices. Microstructural characterization of these joints using scanning and transmission electron microscopy and ion beam microscopy showed that electrical degradation of the ENIG devices was a direct result of the conversion of the as-deposited Ni(V) barrier UBM layer into a porous fine-grained V3Sn-intermetallic compound (IMC). This conversion was driven by the Au layer in the ENIG surface finish. No such conversion was observed for the devices assembled on Cu-SOP surface finish substrates. A resistance degradation model is proposed. The model captures changes from a combination of phenomena including increased (1) intrinsic resistivity, (2) porosity, and (3) electron scattering at grain boundaries and surfaces. Finally, the results from this study were compared with results found in a number of published electromigration studies. This comparison indicates that degradation during current stressing in the Pb-Sn bump/ENIG system is in part due to current-crowding-induced Joule heating and the thermal gradients that result from localized Joule heating.

  14. Fully-integrated, bezel-less transistor arrays using reversibly foldable interconnects and stretchable origami substrates

    NASA Astrophysics Data System (ADS)

    Kim, Mijung; Park, Jihun; Ji, Sangyoon; Shin, Sung-Ho; Kim, So-Yun; Kim, Young-Cheon; Kim, Ju-Young; Park, Jang-Ung

    2016-05-01

    Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints.Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02041k

  15. Silicon-hybrid wafer-scale integration achieved with multilevel aluminum interconnects

    NASA Astrophysics Data System (ADS)

    Takahashi, Grant L.; Kolesar, Edward S.

    A silicon-hybrid wafer-scale integration (WSI) technique has been developed to interconnect complementary metal-oxide semiconductor (CMOS) circuits. Electrical performance tests and processing diagnostics reveal that the interconnect design is very promising. The wafer-scale integrated circuit was fabricated by mounting two CMOS integrated circuit dies into etched wells and then planarizing the surface of the silicon wafer substrate. Next the wafer's surface was coated with a photosensitive polyimide and patterned with vias to accommodate the interconnecting conductors. The CMOS dies were two-bit shift registers and were electrically interconnected with aluminum conductors using conventional silicon processing techniques. A diagnostic evaluation was accomplished to determine the electrical continuity of the conductors and via contacts. When compared to a complementary wire-bonded interconnect scheme, the silicon WSI technology was found to be the superior performer at 1-MHz operating frequencies. Discontinuous interconnects were evaluated, and the failures were identified to occur at the severe topographical steps encountered on the substrate wafer's surface.

  16. Process for electrically interconnecting electrodes

    DOEpatents

    Carey, Paul G.; Thompson, Jesse B.; Colella, Nicolas J.; Williams, Kenneth A.

    2002-01-01

    Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb--Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb--Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value.

  17. Silicon hybrid wafer scale integration interconnect performance evaluation at RF frequencies

    NASA Astrophysics Data System (ADS)

    Lyke, James C., Jr.; Kolesar, Edward S., Jr.

    The RF electrical characteristics of hybrid wafer scale integration (WSI) interconnections on silicon-polyimide-aluminum and silicon-benzocyclobutene-aluminum substrates have been evaluated. The silicon wafer substrates were five in in diameter, and each contained an identical set of 200 photolithographically patterned dielectric and aluminum interconnect test structures. The aluminum conductors were 2.5-microns thick, and half of the test structure conductors were 10-microns wide, while the remainder were 25-microns wide. Measurements between 5 kHz and 220 MHz confirmed the expected transmission line behavior manifested by the longer interconnections. The coupling levels in the 400 line/cm density structures are low, but nevertheless significant, especially when digital logic applications requiring low-noise margins are anticipated. More important were the attenuation effects manifested by the longer aluminum interconnections when they were combined with low-impedence matched terminations.

  18. Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

    SciTech Connect

    Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q.; Enquist, P.M.

    1995-12-31

    Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

  19. Wafer-Level 3D Integration for ULSI Interconnects

    NASA Astrophysics Data System (ADS)

    Gutmann, Ronald J.; Lu, Jian-Qiang

    Three-dimensional (3D) integration in a system-in-a-package (SiP) implementation (packaging-based 3D) is becoming increasingly used in consumer, computer, and communication applications where form factor is critical. In particular, the hand-held market for a growing myriad of voice, data, messaging, and imaging products is enabled by packaging-based 3D integration (i.e., stacking and connecting individual chips). The key drivers are for increased memory capacity and for heterogeneous integration of different IC technologies and functions.

  20. Parametric study on the solderability of etched PWB copper

    SciTech Connect

    Hosking, F.M.; Stevenson, J.O.; Hernandez, C.L.

    1996-10-01

    The rapid advancement of interconnect technology has resulted in a more engineered approach to designing and fabricating printed wiring board (PWB) surface features. Recent research at Sandia National Laboratories has demonstrated the importance of surface roughness on solder flow. This paper describes how chemical etching was used to enhance the solderability of surfaces that were normally difficult to wet. The effects of circuit geometry, etch concentration, and etching time on solder flow are discussed. Surface roughness and solder flow data are presented. The results clearly demonstrate the importance of surface roughness on the solderability of fine PWB surface mount features.

  1. Wave soldering with Pb-free solders

    SciTech Connect

    Artaki, I.; Finley, D.W.; Jackson, A.M.; Ray, U.; Vianco, P.T.

    1995-07-01

    The manufacturing feasibility and attachment reliability of a series of newly developed lead-free solders were investigated for wave soldering applications. Some of the key assembly aspects addressed included: wettability as a function of board surface finish, flux activation and surface tension of the molten solder, solder joint fillet quality and optimization of soldering thermal profiles. Generally, all new solder formulations exhibited adequate wave soldering performance and can be considered as possible alternatives to eutectic SnPb for wave soldering applications. Further process optimization and flux development is necessary to achieve the defect levels associated with the conventional SnPb process.

  2. Inter-connections between human health and ecological integrity: An organizational framework for research and development

    EPA Science Inventory

    A Pellston workshop entitled, Interconnections between Human Health and Ecological Integrity, was held in 2000. Jointly sponsored by the Society of Environmental Toxicology and Chemistry (SETAC) and the Society of Toxicology (SOT), the workshop was motivated by the concern of hum...

  3. On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

    NASA Astrophysics Data System (ADS)

    Hornak, L. A.; Tewksbury, S. K.

    1987-07-01

    A method, compatible with VLSI processing, is described which makes it possible to fabricate vertical through-wafer optical interconnects for hybrid multiwafer wafer-scale-integrated (WSI) architectures. Using optical devices operating at wavelengths beyond the Si absorption cutoff, a low-loss through-the-wafer propagation between WSI circuit planes can be achieved over the distances of about 1 mm with the interstitial Si wafers as part of the interconnect 'free-space' transmission medium. VLSI-process-compatible SiO2 Fresnel phase-reversal zone plate arrays were fabricated. Initial results show that a 400-percent improvement in optical power coupling through the wafer was obtained.

  4. Silicon nanophotonic integrated devices enabling multiplexed on-chip optical interconnects

    NASA Astrophysics Data System (ADS)

    Dai, Daoxin; Wang, Jian; Chen, Sitao

    2015-05-01

    Advanced multiplexing technologies including wavelength-division-multiplexing (WDM), polarization-division multiplexing (PDM), and mode-division multiplexing (MDM) have been utilized as a cost-effective solution to enhance the capacity of an optical-interconnect link. The on-chip (de)multiplexers, including WDM filters, PDM devices, and MDM devices, are the most important key components in a multi-channel multiplexed optical interconnect system. Hybrid (de)multiplexer to enable various multiplexing technologies simultaneously are becoming more and more important to achieve many channels. In this paper we give a review for our recent work on silicon photonic integrated devices for realizing multi-channel multiplexed on-chip optical interconnects.

  5. Requirements for soldered electrical connections

    NASA Technical Reports Server (NTRS)

    1992-01-01

    This publication is applicable to NASA programs involving solder connections for flight hardware, mission essential support equipment, and elements thereof. This publication sets forth hand and wave soldering requirements for reliable electrical connections. The prime consideration is the physical integrity of solder connections. Special requirements may exist which are not in conformance with the requirements of this publication. Design documentation contains the detail for these requirements, and they take precedence over conflicting portions of this publication when they are approved in writing by the procuring NASA installation.

  6. Integrating silicon photonic interconnects with CMOS: Fabrication to architecture

    NASA Astrophysics Data System (ADS)

    Sherwood, Nicholas Ramsey

    While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

  7. Welded solar cell interconnection

    NASA Technical Reports Server (NTRS)

    Stofel, E. J.; Browne, E. R.; Meese, R. A.; Vendura, G. J.

    1982-01-01

    The efficiency of the welding of solar-cell interconnects is compared with the efficiency of soldering such interconnects, and the cases in which welding may be superior are examined. Emphasis is placed on ultrasonic welding; attention is given to the solar-cell welding machine, the application of the welding process to different solar-cell configurations, producibility, and long-life performance of welded interconnects. Much of the present work has been directed toward providing increased confidence in the reliability of welding using conditions approximating those that would occur with large-scale array production. It is concluded that there is as yet insufficient data to determine which of three methods (soldering, parallel gap welding, and ultrasonic welding) provides the longest-duration solar panel life.

  8. Solder flow over fine line PWB surface finishes

    SciTech Connect

    Hosking, F.M.; Hernandez, C.L.

    1998-08-01

    The rapid advancement of interconnect technology has stimulated the development of alternative printed wiring board (PWB) surface finishes to enhance the solderability of standard copper and solder-coated surfaces. These new finishes are based on either metallic or organic chemistries. As part of an ongoing solderability study, Sandia National Laboratories has investigated the solder flow behavior of two azole-based organic solderability preservations, immersion Au, immersion Ag, electroless Pd, and electroless Pd/Ni on fine line copper features. The coated substrates were solder tested in the as-fabricated and environmentally-stressed conditions. Samples were processed through an inerted reflow machine. The azole-based coatings generally provided the most effective protection after aging. Thin Pd over Cu yielded the best wetting results of the metallic coatings, with complete dissolution of the Pd overcoat and wetting of the underlying Cu by the flowing solder. Limited wetting was measured on the thicker Pd and Pd over Ni finishes, which were not completely dissolved by the molten solder. The immersion Au and Ag finishes yielded the lowest wetted lengths, respectively. These general differences in solderability were directly attributed to the type of surface finish which the solder came in contact with. The effects of circuit geometry, surface finish, stressing, and solder processing conditions are discussed.

  9. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    PubMed

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

  10. [Interface interconnection and data integration in implementing of digital operating room].

    PubMed

    Feng, Jingyi; Chen, Hua; Liu, Jiquan

    2011-10-01

    The digital operating-room, with highly integrated clinical information, is very important for rescuing lives of patients and improving quality of operations. Since equipments in domestic operating-rooms have diversified interface and nonstandard communication protocols, designing and implementing an integrated data sharing program for different kinds of diagnosing, monitoring, and treatment equipments become a key point in construction of digital operating room. This paper addresses interface interconnection and data integration for commonly used clinical equipments from aspects of hardware interface, interface connection and communication protocol, and offers a solution for interconnection and integration of clinical equipments in heterogeneous environment. Based on the solution, a case of an optimal digital operating-room is presented in this paper. Comparing with the international solution for digital operating-room, the solution proposed in this paper is more economical and effective. And finally, this paper provides a proposal for the platform construction of digital perating-room as well as a viewpoint for standardization of domestic clinical equipments.

  11. Delay modeling of high-speed distributed interconnect for the signal integrity prediction

    NASA Astrophysics Data System (ADS)

    Raveloa, B.

    2012-02-01

    A relevant modeling-method of distributed interconnect line for the high-speed signal integrity (SI) application is introduced in this paper. By using the microwave and transmission line (TL) theory, the interconnect lines are assumed as its distributed RLC-model. Then, based on the transfer matrix analysis, the second-order global transfer function of the interconnect network comprised of the TL driven by voltage source including its internal resistance and the impedance load is expressed. Thus, mathematical analysis enabling the physical SI-parameters' extraction was established by using the transient response of the loaded line. To verify the relevance of the developed model, RC- and RLC-lines excited by square-wavepulse with 10-Gbits/s-rate were investigated. So, comparisons with SPICE-computations were performed. As results, transient responses perfectly well correlated to the reference SPICE-models were evidenced. As application of the introduced model, evaluations of rise-/fall-times, propagation delays, signal attenuations and even the settling times were realized for different values of TL-parameters. Compared to other methods, the computation execution time and data memory consumed by the program implementing the proposed delay modeling-method algorithm are much better.

  12. In Situ Electromigration in Cu-Sn and Ni-Sn Critical Solder Length for Three-Dimensional Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huang, Y. T.; Chen, C. H.; Lee, B. H.; Chen, H. C.; Wang, C. M.; Wu, Albert T.

    2016-12-01

    An in situ electromigration study has been conducted on U-groove Cu/Sn-3.5Ag/Cu and Ni/Sn-3.5Ag/Ni sandwich structures; the results were used to simulate microsolder joints passing current density of 1 × 104 A/cm2 at 150°C. The solder gap was only 15 μm, shorter than the critical length of Sn-3.5Ag solder. Backstress was proved to exist at critical solder lengths and to influence the electromigration mechanism. Theoretical calculations of the diffusivity of Cu and Ni in Sn solder indicated that the degree to which the dominant diffusion species (Cu or Ni atoms) diffused through the solder line is retarded by the backstress effect. The morphologies of intermetallic compounds (IMCs) were observed, and the grain boundaries in Sn solder were measured using electron backscatter diffraction to determine the kinetics of intermetallic growth. The results reveal that the unique electromigration characteristics of microbump joints, including the diffusivity, morphology, and backstress, can be determined. The retardation of atomic migration improves the reliability against electromigration.

  13. Integration of optoelectronic technologies for chip-to- chip interconnections and parallel pipeline processing

    NASA Astrophysics Data System (ADS)

    Wu, Jenming

    Digital information services such as multimedia systems and data communications require the processing and transfer of tremendous amount of data. These data need to be stored, accessed and delivered efficiently and reliably at high speed for various user applications. This represents a great challenge for current electronic systems. Electronics is effective in providing high performance processing and computation, but its input/outputs (I/Os) bandwidth is unable to scale with its processing power. The signal I/Os or interconnections are needed between processors and input devices, between processors for multiprocessor systems, and between processors and storage devices. Novel chip-to-chip interconnect technologies are needed to meet this challenge. This work integrates optoelectronic technologies for chip-to-chip interconnects and parallel pipeline processing. Photonic and electronic technologies are complementary to each other in the sense that electronics is more suitable for high-speed, low cost computation, and photonics is more suitable for high-bandwidth information transmission. Smart pixel technology uses electronics for logic switching and optics for chip-to- chip interconnects, thus combining the abilities of photonics and electronics nicely. This work describes both vertical and horizontal integration of smart pixel technologies for chip-to-chip optical interconnects and its applications. We present smart pixel VLSI designs in both hybrid CMOS/MQW smart pixel and monolithic GaAs smart pixel technologies. We use the CMOS/MQW technology for smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing. We have tested the chip and constructed a prototype system for device characterization and system demonstration. We have verified the functionality of the system and characterized the electrical functions of the chip and the optoelectronic properties of the MQW devices. We have developed algorithms that utilize SPARCL for various

  14. Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

    2001-01-01

    In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

  15. Integrated Energy-Water Planning in the Western and Texas Interconnections

    SciTech Connect

    Vincent Tidwell; John Gasper; Robert Goldstein; Jordan Macknick; Gerald Sehlke; Michael Webber; Mark Wigmosta

    2013-07-01

    While long-term regional electricity transmission planning has traditionally focused on cost, infrastructure utilization, and reliability, issues concerning the availability of water represent an emerging issue. Thermoelectric expansion must be considered in the context of competing demands from other water use sectors balanced with fresh and non-fresh water supplies subject to climate variability. An integrated Energy-Water Decision Support System (DSS) is being developed that will enable planners in the Western and Texas Interconnections to analyze the potential implications of water availability and cost for long-range transmission planning. The project brings together electric transmission planners (Western Electricity Coordinating Council and Electric Reliability Council of Texas) with western water planners (Western Governors’ Association and the Western States Water Council). This paper lays out the basic framework for this integrated Energy-Water DSS.

  16. Laser forward transfer of solder paste for microelectronics fabrication

    NASA Astrophysics Data System (ADS)

    Mathews, Scott A.; Charipar, Nicholas A.; Auyeung, Ray C.; Kim, Heungsoo; Piqué, Alberto

    2015-03-01

    The progressive miniaturization of electronic devices requires an ever-increasing density of interconnects attached via solder joints. As a consequence, the overall size and spacing (or pitch) of these solder joint interconnects keeps shrinking. When the pitch between interconnects decreases below 200 μm, current technologies, such as stencil printing, find themselves reaching their resolution limit. Laser direct-write (LDW) techniques based on laser-induced forward transfer (LIFT) of functional materials offer unique advantages and capabilities for the printing of solder pastes. At NRL, we have demonstrated the successful transfer, patterning, and subsequent reflow of commercial Pb-free solder pastes using LIFT. Transfers were achieved both with the donor substrate in contact with the receiving substrate and across a 25 μm gap, such that the donor substrate does not make contact with the receiving substrate. We demonstrate the transfer of solder paste features down to 25 μm in diameter and as large as a few hundred microns, although neither represents the ultimate limit of the LIFT process in terms of spatial dimensions. Solder paste was transferred onto circular copper pads as small as 30 μm and subsequently reflowed, in order to demonstrate that the solder and flux were not adversely affected by the LIFT process.

  17. Mechanical Solder Characterisation Under High Strain Rate Conditions

    NASA Astrophysics Data System (ADS)

    Meier, Karsten; Roellig, Mike; Wiese, Steffen; Wolter, Klaus-Juergen

    2010-11-01

    Using a setup for high strain rate tensile experiments the mechanical behavior of two lead-free tin based solders is investigated. The first alloy is SnAg1.3Cu0.5Ni. The second alloy has a higher silver content but no addition of Ni. Solder joints are the main electrical, thermal and mechanical interconnection technology on the first and second interconnection level. With the recent rise of 3D packaging technologies many novel interconnection ideas are proposed with innovative or visionary nature. Copper pillar, stud bump, intermetallic (SLID) and even spring like joints are presented in a number of projects. However, soldering will remain one of the important interconnect technologies. Knowing the mechanical properties of solder joints is important for any reliability assessment, especially when it comes to vibration and mechanical shock associated with mobile applications. Taking the ongoing miniaturization and linked changes in solder joint microstructure and mechanical behavior into account the need for experimental work on that issue is not satisfied. The tests are accomplished utilizing miniature bulk specimens to match the microstructure of real solder joints as close as possible. The dogbone shaped bulk specimens have a crucial diameter of 1 mm, which is close to BGA solder joints. Experiments were done in the strain rate range from 20 s-1 to 600 s-1. Solder strengthening has been observed with increased strain rate for both SAC solder alloys. The yield stress increases by about 100% in the investigated strain rate range. The yield level differs strongly. A high speed camera system was used to assist the evaluation process of the stress and strain data. Besides the stress and strain data extracted from the experiment the ultimate fracture strain is determined and the fracture surfaces are evaluated using SEM technique considering rate dependency.

  18. Soldering instrument safety improvements

    DOEpatents

    Kosslow, William J.; Giron, Ronald W.

    1996-01-01

    A safe soldering device includes a retractable heat shield which can be moved between a first position in which the solder tip of the device is exposed for soldering operation and a second position in which the solder tip is covered by the heat shield. Preferably, the heat shield is biased towards the second position and may be locked in the first position for ease of use. When the soldering device is equipped with a vacuum system, the heat shield may serve to guide the flow of gases and heat from the solder tip away from the work area. The heat shield is preferably made of non-heatsinking plastic.

  19. Electroplated solder alloys for flip chip interconnections

    NASA Astrophysics Data System (ADS)

    Annala, P.; Kaitila, J.; Salonen, J.

    1997-01-01

    Flip chip mounting of bare dice is gaining widespread use in microelectronics packaging. The main drivers for this technology are high packaging density, improved performance at high frequency, low parasitic effects and potentially high reliability and low cost. Many companies have made significant efforts to develop a technology for bump processing, bare die testing and underfill encapsulation to gain the benefit of all potential advantages. We have focussed on low cost bumping of fully processed silicon wafers to develop a flexible scheme for various reflow requirements. The bumping process is based on galvanic plating from an alloy solution or, alternatively, from several elemental plating baths. Sputtered Mo/Cu or Cr/Cu is used as a wettable base for electroplating. Excess base metal is removed by using the bumps as an etching mask. Variation of the alloy composition or the layer structure, allows the adjustment of the bump reflow temperature for the specific requirements of the assembly. Using binary tin-lead and ternary tin-lead-bismuth alloys, reflow temperatures from 100 °C (bismuth rich alloys) to above 300 °C (lead rich alloys) can be covered. The influence of the plating current density on the final alloy composition has been established by ion beam analysis of the plated layers and a series of reflow experiments. To control the plating uniformity and the alloy composition, a new cup plating system has been built with a random flow pattern and continuous adjustment of the current density. A well-controlled reflow of the bumps has been achieved in hot glycerol up to the eutectic point of tin-lead alloys. For high temperature alloys, high molecular weight organic liquids have been used. A tensile pull strength of 20 g per bump and resistance of 5 mΩ per bump have been measured for typical eutectic tin-lead bumps of 100 μm in diameter.

  20. Microstructural evolution during the thermomechanical fatigue of solder joints

    SciTech Connect

    Frear, D R

    1991-01-01

    Solder joints in electronic packages are electrical interconnections that also function as mechanical bonds. The solder often constrains materials of different coefficients of thermal expansion that, when thermal fluctuations are encountered, causes the solder joint to experience cyclical deformation. Due to the catastrophic consequences of electrical or mechanical failure of solder joints, a great deal of work has been performed to develop a better understanding of the metallurgical response of solder joints subjected to thermomechanical fatigue. This work reviews the microstructural and mechanical evolution that occurs in solder joints during thermomechanical fatigue. The eutectic Sn-Pb solder alloy is highlighted. Unlike most materials that experience thermomechanical fatigue, solder is commonly used at temperatures of up to nine-tenths of its melting point. Therefore extensive creep, solid state diffusion, recrystallization and grain growth occur in this alloy resulting in the evolution of a heterogeneous coarsened band through which failure eventually takes place. Two other solder alloys are compared with the Sn-Pb eutectic, a Pb-rich Sn-Pb alloy and a ternary near eutectic (40In-40Sn-20Pb, all alloys are given in wt. %). The Pb-rich alloy is a precipitated single phase matrix that does not evolve during thermomechanical fatigue and subsequently has a shorter lifetime. Conversely, the 40In-40Sn-20Pb solder is a two phase eutectic in which the microstructures refines during thermomechanical fatigue giving it a longer lifetime than the eutectic Sn-Pb solder. The microstructural processes that occur during thermomechanical fatigue and final fracture behavior are discussed for the three solder alloys. 47 refs., 14 figs.

  1. Hybrid microcircuit board assembly with lead-free solders

    SciTech Connect

    Vianco, P.T.; Hernandez, C.L.; Rejent, J.A.

    2000-01-11

    An assessment was made of the manufacturability of hybrid microcircuit test vehicles assembled using three Pb-free solder compositions 96.5Sn--3.5Ag (wt.%), 91.84Sn--3.33Ag--4.83Bi, and 86.85Sn--3.15Ag--5.0Bi--5.0Au. The test vehicle substrate was 96% alumina; the thick film conductor composition was 76Au--21Pt--3Pd. Excellent registration between the LCCC or chip capacitor packages and the thick film solder pads was observed. Reduced wetting of bare (Au-coated) LCCC castellations was eliminated by hot solder dipping the I/Os prior to assembly of the circuit card. The Pb-free solders were slightly more susceptible to void formation, but not to a degree that would significantly impact joint functionality. Microstructural damage, while noted in the Sn-Pb solder joints, was not observed in the Pb-free interconnects.

  2. Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

    NASA Astrophysics Data System (ADS)

    Aggarwal, Ankur

    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is

  3. Integration Process Development for Improved Compatibility with Organic Non-Porous Ultralow-k Dielectric Fluorocarbon on Advanced Cu Interconnects

    NASA Astrophysics Data System (ADS)

    Gu, Xun; Tomita, Yugo; Nemoto, Takenao; Miyatani, Kotaro; Saito, Akane; Kobayashi, Yasuo; Teramoto, Akinobu; Kuroda, Rihito; Kuroki, Shin-Ichiro; Kawase, Kazumasa; Nozawa, Toshihisa; Matsuoka, Takaaki; Sugawa, Shigetoshi; Ohmi, Tadahiro

    2012-05-01

    Integration of an organic non-porous ultralow-k dielectric, fluorocarbon (k= 2.2), into advanced Cu interconnects was demonstrated. The challenges of process-induced damage, such as delamination and variances of both the structure and electrical properties of the fluorocarbon during fabrication, were investigated on Cu/fluorocarbon damascene interconnects. A titanium-based barrier layer, instead of a tantalum-based barrier layer, was used to avoid delamination between Cu and fluorocarbon in Cu/fluorocarbon interconnects. A moisture-hermetic dielectric protective layer was also effective to avoid damage induced by wet chemical cleaning. On the other hand, a post-etching nitrogen plasma treatment to form a stable protective layer on the surface of the fluorocarbon was proposed for the practical minimization of damage introduction to fluorocarbon in the following damascene process, such as post-etching cleaning.

  4. Ensuring Fully Soldered Through Holes

    NASA Technical Reports Server (NTRS)

    Blow, Raymond K.

    1987-01-01

    Simple differential-pressure soldering method provides visual evidence that hidden joints are fully soldered. Intended for soldering connector pins in plated through holes in circuit boards. Molten solder flows into plated through holes, drawn by vacuum in manifold over circuit board. Differential-pressure process ensures solder wets entire through hole around connector pin.

  5. An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.

    SciTech Connect

    Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark; Vianco, Paul Thomas; Zender, Gary L.; Hlava, Paul Frank; Rejent, Jerome Andrew

    2008-09-01

    The assembly of the BDYE detector requires the attachment of sixteen silicon (Si) processor dice (eight on the top side; eight on the bottom side) onto a low-temperature, co-fired ceramic (LTCC) substrate using 63Sn-37Pb (wt.%, Sn-Pb) in a double-reflow soldering process (nitrogen). There are 132 solder joints per die. The bond pads were gold-platinum-palladium (71Au-26Pt-3Pd, wt.%) thick film layers fired onto the LTCC in a post-process sequence. The pull strength and failure modes provided the quality metrics for the Sn-Pb solder joints. Pull strengths were measured in both the as-fabricated condition and after exposure to thermal cycling (-55/125 C; 15 min hold times; 20 cycles). Extremely low pull strengths--referred to as the low pull strength phenomenon--were observed intermittently throughout the product build, resulting in added program costs, schedule delays, and a long-term reliability concern for the detector. There was no statistically significant correlation between the low pull strength phenomenon and (1) the LTCC 'sub-floor' lot; (2) grit blasting the LTCC surfaces prior to the post-process steps; (3) the post-process parameters; (4) the conductor pad height (thickness); (5) the dice soldering assembly sequence; or (5) the dice pull test sequence. Formation of an intermetallic compound (IMC)/LTCC interface caused by thick film consumption during either the soldering process or by solid-state IMC formation was not directly responsible for the low-strength phenomenon. Metallographic cross sections of solder joints from dice that exhibited the low pull strength behavior, revealed the presence of a reaction layer resulting from an interaction between Sn from the molten Sn-Pb and the glassy phase at the TKN/LTCC interface. The thick film porosity did not contribute, explicitly, to the occurrence of reaction layer. Rather, the process of printing the very thin conductor pads was too sensitive to minor thixotropic changes to ink, which resulted in

  6. Multichannel Integrated Acoustooptic Device Modules for Signal Processing, Computing and Optical Interconnect.

    NASA Astrophysics Data System (ADS)

    Le, Phat Duc

    A variety of lithium niobate (LiNbO_3 )-based multichannel integrated optic (IO) device modules for applications in signal processing, computing, and optical interconnect have been realized. The key to the realization of these device modules is the titanium -indiffusion proton-exchange (TIPE) technique developed recently at our laboratory for fabrication of microlenses and microlens arrays. First, two ten-channel IO device modules have been constructed and tested. These two high -packing density devices modules represent the highest degree of integration and the largest number of components that have been accomplished thus far. The architecture common to both modules consists of a composite waveguide 1.0 x 2.0 cm^2 in size in which a channel -waveguide array, a planar waveguide, a linear microlens array, an electrooptic Bragg modulator array or an acoustooptic and electrooptic Bragg modulator array, and a large-aperture lens are integrated. These device modules have been used to perform matrix-matrix multiplications and digital correlations with encouraging results. In performing these computations, a convenient scheme that utilizes a linear ion-milled planar microlens array, devised specifically for these multichannel device modules, has been employed for simultaneous and efficient excitation of the entire channel-waveguide array. Secondly, a new type of strictly nonblocking IO switching network has been conceived and realized in LiNbO_3 . In this new optical switching network module two arrays of channel waveguides, a pair of large-aperture TIPE lenses, and a set of surface-acoustic-wave (SAW) transducers are configured such that the acoustooptic Bragg diffraction serves as a means to activate the connection between any input and any output channels. The working principle of this guided-wave acoustooptic switching network has been verified by using a 4 x 4 switching network module with encouraging performance such as a typical crosstalk level of -16 dB.

  7. The parylene-aluminum multilayer interconnection system for wafer scale integration and wafer scale hybrid packaging

    NASA Astrophysics Data System (ADS)

    Majid, N.; Dabral, S.; McDonald, J. F.

    1989-03-01

    Polyimides have been considered as interlayer dielectrics for wafer scale integration (WSI) and wafer scale hybrid packaging (WSHP). However, high temperature curing steps for polyimide lead to large stresses in polyimide films. This is due to differing thermal expansion coefficients of the metal conductor, insulator and substrate materials causing yield and reliability problems. Polyimides also require the use of solvents, and tend to outgas during subsequent processing. They tend to absorb moisture with resulting degradation of dielectric constants. Also, the spin on method used to apply and planarize polyimide layers exhibits nonuniformity of thickness on large wafers. In this paper we examine parylene (Poly-p-xylylene) and some of its derivatives as possible interlayer dielectrics due to some of their attractive features. Parylene has a low dielectric constant. It can be vapor deposited at low temperatures and in vacuum. It is also highly resistant to corrosion and is a clear, transparent material with possible use for optical interconnections. This paper studies the reactive ion etching properties for polyimides and parylenes in an oxygen containing plasma under identical conditions. The etching rates of the parylenes and polyimides have been compared. The surface properties of these polymers are examined. Further, the film growth properties of aluminum deposited on the etched surfaces using the ionized cluster beam are investigated.

  8. Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

    NASA Astrophysics Data System (ADS)

    Apostolopoulos, Dimitrios; Bakopoulos, Paraskevas; Kalavrouziotis, Dimitrios; Giannoulis, Giannis; Kanakis, Giannis; Iliadis, Nikos; Spatharakis, Christos; Bauwelinck, Johan; Avramopoulos, Hercules

    2014-03-01

    New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of opticalinterconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies.

  9. Oahu Wind Integration and Transmission Study (OWITS): Hawaiian Islands Transmission Interconnection Project

    SciTech Connect

    Woodford, D.

    2011-02-01

    This report provides an independent review included an initial evaluation of the technical configuration and capital costs of establishing an undersea cable system and examining impacts to the existing electric transmission systems as a result of interconnecting the islands.

  10. Phase 2 Report: Oahu Wind Integration and Transmission Study (OWITS); Hawaiian Islands Transmission Interconnection Project

    SciTech Connect

    Woodford, D.

    2011-02-01

    This report provides an independent review including an initial evaluation of the technical configuration and capital costs of establishing an undersea cable system and examining impacts to the existing electric transmission systems as a result of interconnecting the islands

  11. Solderability test system

    DOEpatents

    Yost, F.; Hosking, F.M.; Jellison, J.L.; Short, B.; Giversen, T.; Reed, J.R.

    1998-10-27

    A new test method to quantify capillary flow solderability on a printed wiring board surface finish. The test is based on solder flow from a pad onto narrow strips or lines. A test procedure and video image analysis technique were developed for conducting the test and evaluating the data. Feasibility tests revealed that the wetted distance was sensitive to the ratio of pad radius to line width (l/r), solder volume, and flux predry time. 11 figs.

  12. Solderability test system

    DOEpatents

    Yost, Fred; Hosking, Floyd M.; Jellison, James L.; Short, Bruce; Giversen, Terri; Reed, Jimmy R.

    1998-01-01

    A new test method to quantify capillary flow solderability on a printed wiring board surface finish. The test is based on solder flow from a pad onto narrow strips or lines. A test procedure and video image analysis technique were developed for conducting the test and evaluating the data. Feasibility tests revealed that the wetted distance was sensitive to the ratio of pad radius to line width (l/r), solder volume, and flux predry time.

  13. Operating Reserve Implication of Alternative Implementations of an Energy Imbalance Service on Wind Integration in the Western Interconnection: Preprint

    SciTech Connect

    Milligan, M.; Kirby, B.; King, J.; Beuning, S.

    2011-07-01

    During the past few years, there has been significant interest in alternative ways to manage power systems over a larger effective electrical footprint. Large regional transmission organizations in the Eastern Interconnection have effectively consolidated balancing areas, achieving significant economies of scale that result in a reduction in required reserves. Conversely, in the Western Interconnection there are many balancing areas, which will result in challenges if there is significant wind and solar energy development in the region. A recent proposal to the Western Electricity Coordinating Council suggests a regional energy imbalance service (EIS). To evaluate this EIS, a number of analyses are in process or are planned. This paper describes one part of an analysis of the EIS's implication on operating reserves under several alternative scenarios of the market footprint and participation. We improve on the operating reserves method utilized in the Eastern Wind Integration and Transmission Study and apply this modified approach to data from the Western Wind and Solar Integration Study.

  14. Integrating III-V, Si, and polymer waveguides for optical interconnects: RAPIDO

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Harjanne, Mikko; Offrein, Bert-Jan; Caër, Charles; Neumeyr, Christian; Malacarne, Antonio; Guina, Mircea; Sheehan, Robert N.; Peters, Frank H.; Melanen, Petri

    2016-03-01

    We present a vision for the hybrid integration of advanced transceivers at 1.3 μm wavelength, and the progress done towards this vision in the EU-funded RAPIDO project. The final goal of the project is to make five demonstrators that show the feasibility of the proposed concepts to make optical interconnects and packet-switched optical networks that are scalable to Pb/s systems in data centers and high performance computing. Simplest transceivers are to be made by combining directly modulated InP VCSELs with 12 μm SOI multiplexers to launch, for example, 200 Gbps data into a single polymer waveguide with 4 channels to connect processors on a single line card. For more advanced transceivers we develop novel dilute nitride amplifiers and modulators that are expected to be more power-efficient and temperatureinsensitive than InP devices. These edge-emitting III-V chips are flip-chip bonded on 3 μm SOI chips that also have polarization and temperature independent multiplexers and low-loss coupling to the 12 μm SOI interposers, enabling to launch up to 640 Gbps data into a standard single mode (SM) fiber. In this paper we present a number of experimental results, including low-loss multiplexers on SOI, zero-birefringence Si waveguides, micron-scale mirrors and bends with 0.1 dB loss, direct modulation of VCSELs up to 40 Gbps, +/-0.25μm length control for dilute nitride SOA, strong band edge shifts in dilute nitride EAMs and SM polymer waveguides with 0.4 dB/cm loss.

  15. Microstructural characterization and thermal cycling reliability of solders under isothermal aging and electrical current

    NASA Astrophysics Data System (ADS)

    Chauhan, Preeti Singh

    Solder joints on printed circuit boards provide electrical and mechanical connections between electronic devices and metallized patterns on boards. These solder joints are often the cause of failure in electronic packages. Solders age under storage and operational life conditions, which can include temperature, mechanical loads, and electrical current. Aging occurring at a constant temperature is called isothermal aging. Isothermal aging leads to coarsening of the bulk microstructure and increased interfacial intermetallic compounds at the solder-pad interface. The coarsening of the solder bulk degrades the creep properties of solders, whereas the voiding and brittleness of interfacial intermetallic compounds leads to mechanical weakness of the solder joint. Industry guidelines on solder interconnect reliability test methods recommend preconditioning the solder assemblies by isothermal aging before conducting reliability tests. The guidelines assume that isothermal aging simulates a "reasonable use period," but do not relate the isothermal aging levels with specific use conditions. Studies on the effect of isothermal aging on the thermal cycling reliability of tin-lead and tin-silver-copper solders are limited in scope, and results have been contradictory. The effect of electrical current on solder joints has been has mostly focused on current densities above 104A/cm2 with high ambient temperature (≥100oC), where electromigration, thermomigration, and Joule heating are the dominant failure mechanisms. The effect of current density below 104A/cm2 on temperature cycling fatigue of solders has not been established. This research provides the relation between isothermal aging and the thermal cycling reliability of select Sn-based solders. The Sn-based solders with 3%, 1%, and 0% silver content that have replaced tin-lead are studied and compared against tin-lead solder. The activation energy and growth exponents of the Arrhenius model for the intermetallic growth in

  16. SNL initiatives in electronic fluxless soldering

    SciTech Connect

    Hosking, F.M.; Frear, D.R.; Vianco, P.T.; Keicher, D.M.

    1991-01-01

    Conventional soldering of electronic components generally requires the application of a chemical flux to promote solder wetting and flow. Chlorofluorocarbons (CFC) and halogenated solvents are normally used to remove the resulting flux residues. While such practice has been routinely accepted throughout the electronics industry, the environmental impact of hazardous solvents on ozone depletion will eventually limit or prevent their use. Solvent substitution or alternative technologies must be developed to meet these goals. Sandia National Laboratories, Albuquerque has a comprehensive environmentally conscious electronics manufacturing program underway that is funded by the DOE Office of Technology Development. Primary elements of the integrated task are the characterization and development of alternative fluxless soldering technologies that would eliminate circuit board cleaning associated with flux residue removal. Storage and handling of hazardous solvents and mixed solvent-flux waste would be consequently reduced during electronics soldering. This paper will report on the progress of the SNL fluxless soldering initiative. Emphasis is placed on the use of controlled atmospheres, laser heating, and ultrasonic soldering.

  17. Reduced oxide soldering activation (ROSA) PWB solderability testing

    SciTech Connect

    Hernandez, C.L.; Hosking, F.M.; Reed, J.; Tench, D.M.; White, J.

    1996-02-01

    The effect of ROSA pretreatment on the solderability of environmentally stressed PWB test coupons was investigated. The PWB surface finish was an electroplated, reflowed solder. Test results demonstrated the ability to recover plated-through-hole fill of steam aged samples with solder after ROSA processing. ROSA offers an alternative method for restoring the solderability of aged PWB surfaces.

  18. Microstructurally based finite element simulation of solder joint behavior

    SciTech Connect

    Frear, D.R.; Burchett, S.N.; Neilsen, M.K.; Stephens, J.J.

    1996-01-01

    The most commonly used solder for electrical interconnects in electronic packages is the near eutectic 60Sn-40Pb alloy. This alloy has a number of processing advantages (suitable melting point of 183C and good wetting behavior). However, under conditions of cyclic strain and temperature (thermomechanical fatigue) the microstructure of this alloy undergoes a heterogeneous coarsening and failure process that makes the prediction of solder joint lifetime complex. A finite element simulation methodology to predict solder joint mechanical behavior, that includes microstructural evolution, has been developed. The mechanical constitutive behavior was incorporated into the time dependent internal state variable viscoplastic model through experimental creep tests. The microstructural evolution is incorporated through a series of mathematical relations that describe mass flow in a temperature/strain environment. The model has been found to simulate observed thermomechanical fatigue behavior in solder joints.

  19. Reliability Evaluation of Bga Solder Joints during Accelerated Life Test

    NASA Astrophysics Data System (ADS)

    Lee, Ouk Sub; Myoung, No Hoon; Kim, Dong Hyeok; Hur, Man Jae; Hwang, Si Woon

    The use of BGA (Ball Grid Array) interconnects utilizing the lead-free solder joint has grown rapidly because of its small volume and diversity of application. Thus, it requires the continuous quantification and refinement of lead-free solder joint reliability. The lead-free solder creep and cyclically applied mechanical loads cause metal fatigue on the lead-free solder joint which inevitably leads to an electrical discontinuity. In the field application, BGA solder joints experience mechanical loads during temperature changes caused by power up/down events as the result of the CTE (Coefficient of Thermal Expansion) mismatch between the substrate and the Si die. In this paper, extremely small resistance changes at joint area corresponding to through-cracks generated by thermal fatigue were measured. In this way, the failure was defined in terms of anomalous changes in electrical resistance of the joint. Furthermore the reliability of BGA solder joints in thermal cycling is evaluated by using the modified coffin-Manson criterion which may define and distinguish failure. Any change in circuit resistance according to the accumulated damage induced by the thermal cycling in the joint was recorded and evaluated in order to quantitate reliability of solder joint.

  20. Solder Reflow Failures in Electronic Components During Manual Soldering

    NASA Technical Reports Server (NTRS)

    Teverovsky, Alexander; Greenwell, Chris; Felt, Frederick

    2008-01-01

    This viewgraph presentation reviews the solder reflow failures in electronic components that occur during manual soldering. It discusses the specifics of manual-soldering-induced failures in plastic devices with internal solder joints. The failure analysis turned up that molten solder had squeezed up to the die surface along the die molding compound interface, and the dice were not protected with glassivation allowing solder to short gate and source to the drain contact. The failure analysis concluded that the parts failed due to overheating during manual soldering.

  1. Simple integration technique to realize parallel optical interconnects: implementation of a pluggable two-dimensional optical data link

    NASA Astrophysics Data System (ADS)

    Goulet, Alain; Naruse, Makoto; Ishikawa, Masatoshi

    2002-09-01

    An assembly technique is presented to realize pluggable or fully integrated optoelectronic systems based on image relays. A method to visually align and assemble optoelectronic chips or fiber bundles to half of a relay is explained. To validate this technique, two-dimensional arrays of vertical-cavity surface-emitting lasers and photodetectors and a fiber image guide have been integrated to gradient index lenses with simple optomechanical parts. Although the connection of these modules was realized with +/-0.5 mm lateral tolerances, parallel optical interconnects were successfully achieved at 10 MHz. The lateral misalignment between chips was on average 20 μm and at worst 60 μm.

  2. Kinetics of Au-containing ternary intermetallic redeposition at solder/UBM interface

    NASA Astrophysics Data System (ADS)

    Lee, Jong-Hyun; Park, Jong-Hwan; Shin, Dong-Hyuk; Lee, Yong-Ho; Kim, Yong-Seog

    2001-09-01

    In this study, the effects of the under bump metallurgy (UBM) structure and Cu content in solders on the redeposition rate of Au-containing ternary intermetallics at the solder/UBM interface were investigated. A UBM structure with a Ni diffusion barrier, Au/Ni/Cu, appeared to promote the redeposition of ternary Au-containing intermetallics at the solder/UBM interface of the ternary during the solid-state aging treatment and the Au-embrittlement of the solder interconnections. Copper added to the eutectic Sn-Pb and Sn-Ag solders was observed to be very effective in retarding the redeposition by forming the ternary intermetallics in solder matrices and preventing the Au-embrittlement. These phenomena were discussed with the microstructures observed.

  3. Root Cause Investigation of Lead-Free Solder Joint Interfacial Failures After Multiple Reflows

    NASA Astrophysics Data System (ADS)

    Li, Yan; Hatch, Olen; Liu, Pilin; Goyal, Deepak

    2016-12-01

    Solder joint interconnects in three-dimensional (3D) packages with package stacking configurations typically must undergo multiple reflow cycles during the assembly process. In this work, interfacial open joint failures between the bulk solder and the intermetallic compound (IMC) layer were found in Sn-Ag-Cu (SAC) solder joints connecting a small package to a large package after multiple reflow reliability tests. Systematic progressive 3D x-ray computed tomography experiments were performed on both incoming and assembled parts to reveal the initiation and evolution of the open failures in the same solder joints before and after the reliability tests. Characterization studies, including focused ion beam cross-sections, scanning electron microscopy, and energy-dispersive x-ray spectroscopy, were conducted to determine the correlation between IMC phase transformation and failure initiation in the solder joints. A comprehensive failure mechanism, along with solution paths for the solder joint interfacial failures after multiple reflow cycles, is discussed in detail.

  4. Root Cause Investigation of Lead-Free Solder Joint Interfacial Failures After Multiple Reflows

    NASA Astrophysics Data System (ADS)

    Li, Yan; Hatch, Olen; Liu, Pilin; Goyal, Deepak

    2017-03-01

    Solder joint interconnects in three-dimensional (3D) packages with package stacking configurations typically must undergo multiple reflow cycles during the assembly process. In this work, interfacial open joint failures between the bulk solder and the intermetallic compound (IMC) layer were found in Sn-Ag-Cu (SAC) solder joints connecting a small package to a large package after multiple reflow reliability tests. Systematic progressive 3D x-ray computed tomography experiments were performed on both incoming and assembled parts to reveal the initiation and evolution of the open failures in the same solder joints before and after the reliability tests. Characterization studies, including focused ion beam cross-sections, scanning electron microscopy, and energy-dispersive x-ray spectroscopy, were conducted to determine the correlation between IMC phase transformation and failure initiation in the solder joints. A comprehensive failure mechanism, along with solution paths for the solder joint interfacial failures after multiple reflow cycles, is discussed in detail.

  5. Lead-free solder

    DOEpatents

    Anderson, Iver E.; Terpstra, Robert L.

    2001-05-15

    A Sn--Ag--Cu eutectic alloy is modified with one or more low level and low cost alloy additions to enhance high temperature microstructural stability and thermal-mechanical fatigue strength without decreasing solderability. Purposeful fourth or fifth element additions in the collective amount not exceeding about 1 weight % (wt. %) are added to Sn--Ag--Cu eutectic solder alloy based on the ternary eutectic Sn--4.7%Ag--1.7%Cu (wt. %) and are selected from the group consisting essentially of Ni, Fe, and like-acting elements as modifiers of the intermetallic interface between the solder and substrate to improve high temperature solder joint microstructural stability and solder joint thermal-mechanical fatigue strength.

  6. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, D.B.

    1988-06-06

    Integrated circuit chips are electrically connected to a silicon wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability. 6 figs.

  7. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, David B.

    1991-01-01

    Integrated circuit chips are electrically connected to a silica wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin metal lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability.

  8. Solder Bonding for Power Transistors

    NASA Technical Reports Server (NTRS)

    Snytsheuvel, H. A.; Mandel, H.

    1985-01-01

    Indium solder boosts power rating and facilitates circuit changes. Efficient heat conduction from power transistor to heat sink provided by layer of indium solder. Low melting point of indium solder (141 degrees C) allows power transistor to be removed, if circuit must be reworked, without disturbing other components mounted with ordinary solder that melts at 181 degrees C. Solder allows devices operated at higher power levels than does conventional attachment by screws.

  9. Interconnection, Integration, and Interactive Impact Analysis of Microgrids and Distribution Systems

    SciTech Connect

    Kang, Ning; Wang, Jianhui; Singh, Ravindra; Lu, Xiaonan

    2017-01-01

    Distribution management systems (DMSs) are increasingly used by distribution system operators (DSOs) to manage the distribution grid and to monitor the status of both power imported from the transmission grid and power generated locally by a distributed energy resource (DER), to ensure that power flows and voltages along the feeders are maintained within designed limits and that appropriate measures are taken to guarantee service continuity and energy security. When microgrids are deployed and interconnected to the distribution grids, they will have an impact on the operation of the distribution grid. The challenge is to design this interconnection in such a way that it enhances the reliability and security of the distribution grid and the loads embedded in the microgrid, while providing economic benefits to all stakeholders, including the microgrid owner and operator and the distribution system operator.

  10. A Comprehensive Surface Mount Technology Solution for Integrated Circuits onto Flexible Screen Printed Electrical Interconnects

    DTIC Science & Technology

    2014-05-19

    Wei Lin, Josh C. Agar, Ching-Ping Wong, (2011, Feb.), “A simple low-cost approach to prepare flexible highly conductive polymer composited by in...Dragonova, (1993, Oct.), “Biocompatible and biodegradable polyurethane polymers ”, in Biomaterials, 14(13), pp. 1024-1029. Available: http://www.ncbi.nlm.nih.gov/pubmed/8286669 ...10 B. Screen-printed interconnects onto flexible polymer film .................................................................... 11 III

  11. LTCC interconnects in microsystems

    NASA Astrophysics Data System (ADS)

    Rusu, Cristina; Persson, Katrin; Ottosson, Britta; Billger, Dag

    2006-06-01

    Different microelectromechanical system (MEMS) packaging strategies towards high packaging density of MEMS devices and lower expenditure exist both in the market and in research. For example, electrical interconnections and low stress wafer level packaging are essential for improving device performance. Hybrid integration of low temperature co-fired ceramics (LTCC) with Si can be a way for an easier packaging system with integrated electrical interconnection, and as well towards lower costs. Our research on LTCC-Si integration is reported in this paper.

  12. Performance evaluation of multi-stratum resources integrated resilience for software defined inter-data center interconnect.

    PubMed

    Yang, Hui; Zhang, Jie; Zhao, Yongli; Ji, Yuefeng; Wu, Jialin; Lin, Yi; Han, Jianrui; Lee, Young

    2015-05-18

    Inter-data center interconnect with IP over elastic optical network (EON) is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resources integration among IP networks, optical networks and application stratums resources that allows to accommodate data center services. In view of this, this study extends to consider the service resilience in case of edge optical node failure. We propose a novel multi-stratum resources integrated resilience (MSRIR) architecture for the services in software defined inter-data center interconnect based on IP over EON. A global resources integrated resilience (GRIR) algorithm is introduced based on the proposed architecture. The MSRIR can enable cross stratum optimization and provide resilience using the multiple stratums resources, and enhance the data center service resilience responsiveness to the dynamic end-to-end service demands. The overall feasibility and efficiency of the proposed architecture is experimentally verified on the control plane of our OpenFlow-based enhanced SDN (eSDN) testbed. The performance of GRIR algorithm under heavy traffic load scenario is also quantitatively evaluated based on MSRIR architecture in terms of path blocking probability, resilience latency and resource utilization, compared with other resilience algorithms.

  13. Interconnection Guidelines

    EPA Pesticide Factsheets

    The Interconnection Guidelines provide general guidance on the steps involved with connecting biogas recovery systems to the utility electrical power grid. Interconnection best practices including time and cost estimates are discussed.

  14. Acid soldering flux poisoning

    MedlinePlus

    The harmful substances in soldering fluxes are called hydrocarbons. They include: Ammonium chloride Rosin Hydrochloric acid Zinc ... Lee DC. Hydrocarbons. In: Marx JA, Hockberger RS, Walls RM, et ... Rosen's Emergency Medicine: Concepts and Clinical Practice . 8th ...

  15. Soldering of Thin Film-Metallized Glass Substrates

    SciTech Connect

    Hosking, F.M.; Hernandez, C.L.; Glass, S.J.

    1999-03-31

    The ability to produce reliable electrical and structural interconnections between glass and metals by soldering was investigated. Soldering generally requires premetallization of the glass. As a solderable surface finish over soda-lime-silicate glass, two thin films coatings, Cr-Pd-Au and NiCr-Sn, were evaluated. Solder nettability and joint strengths were determined. Test samples were processed with Sn60-Pb40 solder alloy at a reflow temperature of 210 C. Glass-to-cold rolled steel single lap samples yielded an average shear strength of 12 MPa. Solder fill was good. Control of the Au thickness was critical in minimizing the formation of AuSn{sub 4} intermetallic in the joint, with a resulting joint shear strength of 15 MPa. Similar glass-to-glass specimens with the Cr-Pd-Au finish failed at 16.5 MPa. The NiCr-Sn thin film gave even higher shear strengths of 20-22.5 MPa, with failures primarily in the glass.

  16. SOLDERING OF ALUMINUM BASE METALS

    DOEpatents

    Erickson, G.F.

    1958-02-25

    This patent deals with the soldering of aluminum to metals of different types, such as copper, brass, and iron. This is accomplished by heating the aluminum metal to be soldered to slightly above 30 deg C, rubbing a small amount of metallic gallium into the part of the surface to be soldered, whereby an aluminum--gallium alloy forms on the surface, and then heating the aluminum piece to the melting point of lead--tin soft solder, applying lead--tin soft solder to this alloyed surface, and combining the aluminum with the other metal to which it is to be soldered.

  17. Materials, processes, and characterization of extended air-gaps for the intra-level interconnection of integrated circuits

    NASA Astrophysics Data System (ADS)

    Park, Seongho

    The integration of an air-gap as an ultra low dielectric constant material in an infra-metal dielectric region of interconnect structure in integrated circuits was investigated in terms of material properties of a thermally decomposable sacrificial polymer, fabrication processes and electrical performance. Extension of the air-gap into the inter-layer dielectric region reduces the interconnect capacitance. In order to enhance the hardness of a polymer for the better process reliabilities, a conventional norbornene-based sacrificial polymer was electron-beam irradiated. Although the hardness of the polymer increased, the thermal properties degraded. A new high modulus tetracyclododecene-based sacrificial polymer was characterized and compared to the norbornene-based polymer in terms of hardness, process reliability and thermal properties. The tetracyclododecene-based polymer was harder and showed better process reliability than the norbomene-based sacrificial polymer. Using the tetracyclododecene-based sacrificial polymer, a single layer Cu/air-gap and extended Culair-gap structures were fabricated. The effective dielectric constant of the air-gap and extended air-gap structures were 2.42 and 2.17, respectively. This meets the requirements for the 32 nm node. Moisture uptake of the extended Cu/air-gap structure increased the effective dielectric constant. The exposure of the structure to hexamethyldisilazane vapor removed the absorbed moisture and changed the structure hydrophobic, improving the integration reliability. The integration processes of the air-gap and the extended air-gap into a dual damascene Cu metallization process has been proposed and compared to state-of-the-art integration approaches.

  18. Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

    DOEpatents

    Jansen, Kai W.; Maley, Nagi

    2001-01-01

    High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

  19. Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

    DOEpatents

    Jansen, Kai W.; Maley, Nagi

    2000-01-01

    High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

  20. High integrity interconnection of silver submicron/nanoparticles on silicon wafer by femtosecond laser irradiation

    NASA Astrophysics Data System (ADS)

    Huang, H.; Sivayoganathan, M.; Duley, W. W.; Zhou, Y.

    2015-01-01

    Welding of nanomaterials is a promising technique for constructing nanodevices with robust mechanical properties. To date, fabrication of these devices is limited because of difficulties in restricting damage to the nanomaterials during the welding process. In this work, by utilizing very low fluence (˜900 μJ cm-2) femtosecond (fs) laser irradiation, we have produced a metallic interconnection between two adjacent silver (Ag) submicron/nanoparticles which were fixed on a silicon (Si) wafer after fs laser deposition. No additional filler material was used, and the connected particles remain almost damage free. Observation of the morphology before and after joining and finite difference time domain simulations indicate that the interconnection can be attributed to plasmonic excitation in the Ag submicron/nanoparticles. Concentration of energy between the particles leads to local ablation followed by re-deposition of the ablated material to form a bridging link that joins the two particles. This welding technique shows potential applications in the fabrication of nanodevices.

  1. High integrity interconnection of silver submicron/nanoparticles on silicon wafer by femtosecond laser irradiation.

    PubMed

    Huang, H; Sivayoganathan, M; Duley, W W; Zhou, Y

    2015-01-16

    Welding of nanomaterials is a promising technique for constructing nanodevices with robust mechanical properties. To date, fabrication of these devices is limited because of difficulties in restricting damage to the nanomaterials during the welding process. In this work, by utilizing very low fluence (∼900 μJ cm(-2)) femtosecond (fs) laser irradiation, we have produced a metallic interconnection between two adjacent silver (Ag) submicron/nanoparticles which were fixed on a silicon (Si) wafer after fs laser deposition. No additional filler material was used, and the connected particles remain almost damage free. Observation of the morphology before and after joining and finite difference time domain simulations indicate that the interconnection can be attributed to plasmonic excitation in the Ag submicron/nanoparticles. Concentration of energy between the particles leads to local ablation followed by re-deposition of the ablated material to form a bridging link that joins the two particles. This welding technique shows potential applications in the fabrication of nanodevices.

  2. A new active solder for joining electronic components

    SciTech Connect

    SMITH,RONALD W.; VIANCO,PAUL T.; HERNANDEZ,CYNTHIA L.; LUGSCHEIDER,E.; RASS,I.; HILLEN,F.

    2000-05-11

    Electronic components and micro-sensors utilize ceramic substrates, copper and aluminum interconnect and silicon. The joining of these combinations require pre-metallization such that solders with fluxes can wet such combinations of metals and ceramics. The paper will present a new solder alloy that can bond metals, ceramics and composites. The alloy directly wets and bonds in air without the use flux or premetallized layers. The paper will present typical processing steps and joint microstructures in copper, aluminum, aluminum oxide, aluminum nitride, and silicon joints.

  3. Novel interconnect deposition technology

    NASA Astrophysics Data System (ADS)

    Speckman, D. M.; Wendt, J. P.

    1991-12-01

    A new series of experiments was initiated to improve current interconnect deposition technology for integrated circuits. Preliminary aluminum deposition experiments were carried out using trimethylamine(alane) as the precursor, and some mildly reflective, uniform aluminum films were successfully deposited on glass slides, suggesting that chemical vapor deposition (CVD) will be a practicable deposition technique for advanced integrated circuit interconnect films. CVD studies of aluminum and zirconium- and hafnium-diboride thin films are continuing.

  4. Interfacial Reactions Between ZnAl(Ge) Solders on Cu and Ni Substrates

    NASA Astrophysics Data System (ADS)

    Rautiainen, Antti; Vuorinen, Vesa; Paulasto-Kröckel, Mervi

    2017-04-01

    Reactions between zinc-aluminum-germanium solder and copper/nickel substrates were investigated after 30 min of soldering at 420°C that simulates a wafer-level bonding process, and the results were compared to a eutectic zinc-aluminum solder. The ZnAlGe system (81.4 at.% Zn, 13.1 at.% Al, 5.5 at.% Ge) was selected in order to decrease the eutectic temperature of the ZnAleut (88.7 at.% Zn, 11.3 at.% Al) for high-temperature lead-free solder applications. In addition, a standard high temperature storage test at 150°C was performed up to 3000 h in order to investigate the evolution of the interconnection microstructures. Extensive copper dissolution was discovered during the soldering process. Germanium did not participate in any of the interfacial reactions on a copper substrate. On a nickel substrate, rapid formation of intermetallic compounds was discovered with both solders, and all the aluminum from the 500 μm thick solder was consumed by the formation of the Al3Ni2 phase during bonding. Germanium was observed to dissolve in the Al3Ni2 phase, but the addition of germanium to the solder was not found to affect markedly the interfacial microstructure. Based on the results, isothermal sections at 150°C of Al-Cu-Zn and Al-Ni-Zn systems are presented with superimposed diffusion paths.

  5. Method and apparatus for jetting, manufacturing and attaching uniform solder balls

    DOEpatents

    Yost, Frederick G.; Frear, Darrel R.; Schmale, David T.

    1999-01-01

    An apparatus and process for jetting molten solder in the form of balls directly onto all the metallized interconnects lands for a ball grid array package in one step with no solder paste required. Molten solder is jetted out of a grid of holes using a piston attached to a piezoelectric crystal. When voltage is applied to the crystal it expands forcing the piston to extrude a desired volume of solder through holes in the aperture plate. When the voltage is decreased the piston reverses motion creating an instability in the molten solder at the aperture plate surface and thereby forming spherical solder balls that fall onto a metallized substrate. The molten solder balls land on the substrate and form a metallurgical bond with the metallized lands. The size of the solder balls is determined by a combination of the size of the holes in the aperture plate, the duration of the piston pulse, and the displacement of the piston. The layout of the balls is dictated by the location of the hooks in the grid. Changes in ball size and layout can be easily accomplished by changing the grid plate. This invention also allows simple preparation of uniform balls for subsequent supply to BGA users.

  6. Method and apparatus for jetting, manufacturing and attaching uniform solder balls

    DOEpatents

    Yost, F.G.; Frear, D.R.; Schmale, D.T.

    1999-01-05

    An apparatus and process are disclosed for jetting molten solder in the form of balls directly onto all the metallized interconnects lands for a ball grid array package in one step with no solder paste required. Molten solder is jetted out of a grid of holes using a piston attached to a piezoelectric crystal. When voltage is applied to the crystal it expands forcing the piston to extrude a desired volume of solder through holes in the aperture plate. When the voltage is decreased the piston reverses motion creating an instability in the molten solder at the aperture plate surface and thereby forming spherical solder balls that fall onto a metallized substrate. The molten solder balls land on the substrate and form a metallurgical bond with the metallized lands. The size of the solder balls is determined by a combination of the size of the holes in the aperture plate, the duration of the piston pulse, and the displacement of the piston. The layout of the balls is dictated by the location of the hooks in the grid. Changes in ball size and layout can be easily accomplished by changing the grid plate. This invention also allows simple preparation of uniform balls for subsequent supply to BGA users. 7 figs.

  7. A microstructural analysis of solder joints from the electronic assemblies of dismantled nuclear weapons

    SciTech Connect

    Vianco, P.T.; Rejent, J.A.

    1997-05-01

    MC1814 Interconnection Boxes from dismantled B57 bombs, and MC2839 firing Sets from retired W70-1 warheads were obtained from the Pantex facility. Printed circuit boards were selected from these components for microstructural analysis of their solder joints. The analysis included a qualitative examination of the solder joints and quantitative assessments of (1) the thickness of the intermetallic compound layer that formed between the solder and circuit board Cu features, and (2) the Pb-rich phase particle distribution within the solder joint microstructure. The MC2839 solder joints had very good workmanship qualities. The intermetallic compound layer stoichiometry was determined to be that of Cu6Sn5. The mean intermetallic compound layer thickness for all solder joints was 0.885 mm. The magnitude of these values did not indicate significant growth over the weapon lifetime. The size distribution of the Pb-rich phase particles for each of the joints were represented by the mean of 9.85 {times} 10{sup {minus}6} mm{sup 2}. Assuming a spherical geometry, the mean particle diameter would be 3.54 mm. The joint-to-joint difference of intermetallic compound layer thickness and Pb-rich particle size distribution was not caused by varying thermal environments, but rather, was a result of natural variations in the joint microstructure that probably existed at the time of manufacture. The microstructural evaluation of the through-hole solder joints form the MC2839 and MC1814 components indicated that the environmental conditions to which these electronic units were exposed in the stockpile, were benign regarding solder joint aging. There was an absence of thermal fatigue damage in MC2839 circuit board, through-hole solder joints. The damage to the eyelet solder joints of the MC1814 more likely represented infant mortality failures at or very near the time of manufacture, resulting from a marginal design status of this type of solder joint design.

  8. Modeling the Rate-Dependent Durability of Reduced-Ag SAC Interconnects for Area Array Packages Under Torsion Loads

    NASA Astrophysics Data System (ADS)

    Srinivas, Vikram; Menon, Sandeep; Osterman, Michael; Pecht, Michael G.

    2013-08-01

    Solder durability models frequently focus on the applied strain range; however, the rate of applied loading, or strain rate, is also important. In this study, an approach to incorporate strain rate dependency into durability estimation for solder interconnects is examined. Failure data were collected for SAC105 solder ball grid arrays assembled with SAC305 solder that were subjected to displacement-controlled torsion loads. Strain-rate-dependent (Johnson-Cook model) and strain-rate-independent elastic-plastic properties were used to model the solders in finite-element simulation. Test data were then used to extract damage model constants for the reduced-Ag SAC solder. A generalized Coffin-Manson damage model was used to estimate the durability. The mechanical fatigue durability curve for reduced-silver SAC solder was generated and compared with durability curves for SAC305 and Sn-Pb from the literature.

  9. Optical Interconnections For WSI

    NASA Astrophysics Data System (ADS)

    Friedrich, E.; Valette, S.; Gidon, P.

    1989-02-01

    Optical interconnections may be an alternative to metallic lines in very large and fast circuits. In this field, integrated optics could be very attractive because the basic approach is similar to the one of microelectronics. From this point of view, the silicon based integrated optics technology developed at LETI is described and expected performances are analysed.

  10. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

  11. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  12. Integrated multilayer microfluidic device with a nanoporous membrane interconnect for online coupling of solid-phase extraction to microchip electrophoresis.

    PubMed

    Long, Zhicheng; Shen, Zheng; Wu, Dapeng; Qin, Jianhua; Lin, Bingcheng

    2007-12-01

    An integrated microfluidic device was developed for online coupling of solid-phase extraction to microchip electrophoresis (chip SPE-CE). With a nanoporous membrane sandwiched between two PDMS substrates, SPE preconcentration and electrophoretic separation can be carried out in upper and lower fluidic layers, separately and sequentially. During the SPE process, the thin membrane can act as a fluid isolator to prevent intermixing between two fluidic channels. However, when a pulse voltage is applied, the membrane becomes a gateable interconnect so that a small plug of concentrated analytes can be online injected into the lower channel for subsequent separations. This multilayer design provides a universal solution to online SPE-CE hyphenation. Both electroosmotic flow and hydrodynamic pumps have been adopted for SPE operation. SPE was performed on a 2.5 mm long microcolumn, with two weirs on both sides to retain the C(18)-coated silica beads. Rhodamine 123 and FITC-labelled ephedrine were used to test the operational performance of the hyphenation system. High separation efficiency and thousand-fold signal enhancement were achieved.

  13. Integrated Energy-Water Planning in the Western and Texas Interconnections (Invited)

    NASA Astrophysics Data System (ADS)

    Tidwell, V. C.

    2013-12-01

    While thermoelectric power generation accounts for less than one percent of total water consumption in the western U.S, steady growth in demand is projected for this sector. Complexities and heterogeneity in water supply, water demand, and institutional controls make water development a challenging proposition throughout the West. A consortium of National Laboratories, the University of Texas and the Electric Power Research Institute are working with the Western Governors' Association and Western States Water Council to assist the Western Electricity Coordinating Council and the Electric Reliability Council of Texas to integrate water related issues into long-term transmission planning. Specifically, water withdrawal and consumption have been estimated for each western power plant and their susceptibility to climate impacts assessed. To assist with transmission planning, water availability and cost data have been mapped at the 8-digit Hydrologic Unit Code level for the conterminous western U.S. (1208 watersheds). Five water sources were individually considered, including unappropriated surface water, unappropriated groundwater, appropriated water, municipal wastewater and brackish groundwater. Also mapped is projected growth in consumptive water demand to 2030. The relative costs (capital and O&M) to secure, convey, and treat the water as necessary have also been estimated for each source of water. These data configured into watershed level supply curves were subsequently used to constrain West-wide transmission planning. Results across a range of alternative energy futures indicate the impact of water availability and cost on the makeup and siting of future power generation. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. Water budgets at a 8

  14. Intermetallics Characterization of Lead-Free Solder Joints under Isothermal Aging

    NASA Astrophysics Data System (ADS)

    Choubey, Anupam; Yu, Hao; Osterman, Michael; Pecht, Michael; Yun, Fu; Yonghong, Li; Ming, Xu

    2008-08-01

    Solder interconnect reliability is influenced by environmentally imposed loads, solder material properties, and the intermetallics formed within the solder and the metal surfaces to which the solder is bonded. Several lead-free metallurgies are being used for component terminal plating, board pad plating, and solder materials. These metallurgies react together and form intermetallic compounds (IMCs) that affect the metallurgical bond strength and the reliability of solder joint connections. This study evaluates the composition and extent of intermetallic growth in solder joints of ball grid array components for several printed circuit board pad finishes and solder materials. Intermetallic growth during solid state aging at 100°C and 125°C up to 1000 h for two solder alloys, Sn-3.5Ag and Sn-3.0Ag-0.5Cu, was investigated. For Sn-3.5Ag solder, the electroless nickel immersion gold (ENIG) pad finish was found to result in the lowest IMC thickness compared to immersion tin (ImSn), immersion silver (ImAg), and organic solderability preservative (OSP). Due to the brittle nature of the IMC, a lower IMC thickness is generally preferred for optimal solder joint reliability. A lower IMC thickness may make ENIG a desirable finish for long-life applications. Activation energies of IMC growth in solid-state aging were found to be 0.54 ± 0.1 eV for ENIG, 0.91 ± 0.12 eV for ImSn, and 1.03 ± 0.1 eV for ImAg. Cu3Sn and Cu6Sn5 IMCs were found between the solder and the copper pad on boards with the ImSn and ImAg pad finishes. Ternary (Cu,Ni)6Sn5 intermetallics were found for the ENIG pad finish on the board side. On the component side, a ternary IMC layer composed of Ni-Cu-Sn was found. Along with intermetallics, microvoids were observed at the interface between the copper pad and solder, which presents some concern if devices are subject to shock and vibration loading.

  15. Thermomechanical fatigue behavior of Sn-Ag solder joints

    NASA Astrophysics Data System (ADS)

    Choi, S.; Subramanian, K. N.; Lucas, J. P.; Bieler, T. R.

    2000-10-01

    Microstructural studies of thermomechanically fatigued actual electronic components consisting of metallized alumina substrate and tinned copper lead, soldered with Sn-Ag or 95.5Ag/4Ag/0.5Cu solder were carried out with an optical microscope and environmental scanning electron microscope (ESEM). Damage characterization was made on samples that underwent 250 and 1000 thermal shock cycles between -40°C and 125°C, with a 20 min hold time at each extreme. Surface roughening and grain boundary cracking were evident even in samples thermally cycled for 250 times. The cracks were found to originate on the free surface of the solder joint. With increased thermal cycles these cracks grew by grain boundary decohesion. The crack that will affect the integrity of the solder joint was found to originate from the free surface of the solder very near the alumina substrate and progress towards and continue along the solder region adjacent to the Ag3Sn intermetallic layer formed with the metallized alumina substrate. Re-examination of these thermally fatigued samples that were stored at room temperature after ten months revealed the effects of significant residual stress due to such thermal cycles. Such observations include enhanced surface relief effects delineating the grain boundaries and crack growth in regions inside the joint.

  16. Simulation of Grain Growth in a Near-Eutectic Solder Alloy

    SciTech Connect

    TIKARE,VEENA; VIANCO,PAUL T.

    1999-12-16

    Microstructural evolution due to aging of solder alloys determines their long-term reliability as electrical, mechanical and thermal interconnects in electronics packages. The ability to accurately determine the reliability of existing electronic components as well as to predict the performance of proposed designs depends upon the development of reliable material models. A kinetic Monte Carlo simulation was used to simulate microstructural evolution in solder-class materials. The grain growth model simulated many of the microstructural features observed experimentally in 63Sn-37Pb, a popular near-eutectic solder alloy. The model was validated by comparing simulation results to new experimental data on coarsening of Sn-Pb solder. The computational and experimental grain growth exponent for two-phase solder was found to be much lower than that for normal, single phase grain growth. The grain size distributions of solders obtained from simulations were narrower than that of normal grain growth. It was found that the phase composition of solder is important in determining grain growth behavior.

  17. In-situ study of electromigration-induced grain rotation in Pb-free solder joint by synchrotron microdiffraction

    SciTech Connect

    Chen, Kai; Tamura, Nobumichi; Tu, King-Ning

    2008-10-31

    The rotation of Sn grains in Pb-free flip chip solder joints hasn't been reported in literature so far although it has been observed in Sn strips. In this letter, we report the detailed study of the grain orientation evolution induced by electromigration by synchrotron based white beam X-ray microdiffraction. It is found that the grains in solder joint rotate more slowly than in Sn strip even under higher current density. On the other hand, based on our estimation, the reorientation of the grains in solder joints also results in the reduction of electric resistivity, similar to the case of Sn strip. We will also discuss the reason why the electric resistance decreases much more in strips than in the Sn-based solders, and the different driving force for the grain growth in solder joint and in thin film interconnect lines.

  18. Wetting in Soldering and Microelectronics

    NASA Astrophysics Data System (ADS)

    Matsumoto, T.; Nogi, K.

    2008-08-01

    Wettability of solid metals by molten solders is reviewed. The contact angle and wetting force are tabulated for various combinations of solid metals and molten solders such as Sn-Pb base alloys, Sn-Ag base alloys, Sn-Zn base alloys, Sn-Cu base alloys, and Sn-Bi base alloys. Studies on the wetting rate are also discussed.

  19. Breakthrough: Lead-free Solder

    SciTech Connect

    Anderson, Iver

    2012-01-01

    Ames Laboratory senior metallurgist Iver Anderson explains the importance of lead-free solder in taking hazardous lead out of the environment by eliminating it from discarded computers and electronics that wind up in landfills. Anderson led a team that developed a tin-silver-copper replacement for traditional lead-tin solder that has been adopted by more than 50 companies worldwide.

  20. Breakthrough: Lead-free Solder

    ScienceCinema

    Anderson, Iver

    2016-07-12

    Ames Laboratory senior metallurgist Iver Anderson explains the importance of lead-free solder in taking hazardous lead out of the environment by eliminating it from discarded computers and electronics that wind up in landfills. Anderson led a team that developed a tin-silver-copper replacement for traditional lead-tin solder that has been adopted by more than 50 companies worldwide.

  1. An Evaluation of Prototype Circuit Boards Assembled with a Sn-Ag Bi Solder

    SciTech Connect

    ARTAKI,I.; RAY,U.; REJENT,JEROME A.; VIANCO,PAUL T.

    1999-09-01

    An evaluation was performed which examined the aging of surface mount solder joints assembled with 91.84Sn-3.33Ag-4.83Bi solder. Defect analysis of the as-fabricated test vehicles revealed excellent solderability, good package alignment, and a minimum number of voids. Continuous DC electrical monitoring of the solder joints did not reveal opens during as many as 10,000 thermal cycles (0 C, 100 C). The solder joints exhibited no significant degradation through 2500 cycles, based upon an absence of microstructural damage and sustained shear and pull strengths of chip capacitors and J-leaded solder joints, respectively. Thermal cycles of 5000 and 10,000 resulted in some surface cracking of the solder fillets and coatings. In a few cases, deeper cracks were observed in the thinner reaches of several solder fillets. There was no deformation or cracking in the solder located in the gap between the package I/O and the circuit board pad nor in the interior of the fillets, both locations that would raise concerns of joint mechanical integrity. A drop in the chip capacitor shear strength was attributed to crack growth near the top of the fillet.

  2. A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization

    SciTech Connect

    He, Yugui; Liu, Chaoyang; Feng, Jiwen; Wang, Dong; Chen, Fang; Liu, Maili; Zhang, Zhi; Wang, Chao

    2015-08-15

    High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately −170 for {sup 1}H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo {sup 1}H MRI at 0.35 T.

  3. A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization

    NASA Astrophysics Data System (ADS)

    He, Yugui; Feng, Jiwen; Zhang, Zhi; Wang, Chao; Wang, Dong; Chen, Fang; Liu, Maili; Liu, Chaoyang

    2015-08-01

    High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately -170 for 1H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo 1H MRI at 0.35 T.

  4. Interconnect mechanisms in microelectronic packaging

    NASA Astrophysics Data System (ADS)

    Roma, Maria Penafrancia C.

    alloy showed differences in adhesion strength and IMC formation. Bond strength by wire pull testing showed the 95Ag alloy with higher values while shear bond testing showed the 88Ag higher bond strength. Use of Cu pillars in flip chips and eutectic bonding in wafer level chip scale packages are direct consequences of diminishing interconnect dimension as a result of the drive for miniaturization. The combination of Cu-Sn interdiffusion, Kirkendall mechanism and heterogeneous vacancy precipitation are the main causes of IMC and void formation in Cu pillar - Sn solder - Cu lead frame sandwich structure. However, adding a Ni barrier agent showed less porous IMC layer as well as void formation as a result of the modified Cu and Sn movement well as the void formation. Direct die to die bonding using Al-Ge eutectic bonds is necessary when 3D integration is needed to reduce the footprint of a package. Hermeticity and adhesion strength are a function of the Al/Ge thickness ratio, bonding pressure, temperature and time. Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) allowed imaging of interfacial microstructures, porosity, grain morphology while Scanning Transmission Electron microscope (STEM) provided diffusion profile and confirmed interdiffusion. Ion polishing technique provided information on porosity and when imaged using backscattered mode, grain structure confirmed mechanical deformation of the bonds. Measurements of the interfacial bond strength are made by wire pull tests and ball shear tests based on existing industry standard tests. However, for the Al-Ge eutectic bonds, no standard strength is available so a test is developed using the stud pull test method using the Dage 4000 Plus to yield consistent results. Adhesion strengths of 30-40 MPa are found for eutectic bonded packages however, as low as 20MPa was measured in low temperature bonded areas.

  5. Metal-interconnection-free integration of InGaN/GaN light emitting diodes with AlGaN/GaN high electron mobility transistors

    SciTech Connect

    Liu, Chao; Cai, Yuefei; Liu, Zhaojun; Ma, Jun; Lau, Kei May

    2015-05-04

    We report a metal-interconnection-free integration scheme for InGaN/GaN light emitting diodes (LEDs) and AlGaN/GaN high electron mobility transistors (HEMTs) by combining selective epi removal (SER) and selective epitaxial growth (SEG) techniques. SER of HEMT epi was carried out first to expose the bottom unintentionally doped GaN buffer and the sidewall GaN channel. A LED structure was regrown in the SER region with the bottom n-type GaN layer (n-electrode of the LED) connected to the HEMTs laterally, enabling monolithic integration of the HEMTs and LEDs (HEMT-LED) without metal-interconnection. In addition to saving substrate real estate, minimal interface resistance between the regrown n-type GaN and the HEMT channel is a significant improvement over metal-interconnection. Furthermore, excellent off-state leakage characteristics of the driving transistor can also be guaranteed in such an integration scheme.

  6. Metal-interconnection-free integration of InGaN/GaN light emitting diodes with AlGaN/GaN high electron mobility transistors

    NASA Astrophysics Data System (ADS)

    Liu, Chao; Cai, Yuefei; Liu, Zhaojun; Ma, Jun; Lau, Kei May

    2015-05-01

    We report a metal-interconnection-free integration scheme for InGaN/GaN light emitting diodes (LEDs) and AlGaN/GaN high electron mobility transistors (HEMTs) by combining selective epi removal (SER) and selective epitaxial growth (SEG) techniques. SER of HEMT epi was carried out first to expose the bottom unintentionally doped GaN buffer and the sidewall GaN channel. A LED structure was regrown in the SER region with the bottom n-type GaN layer (n-electrode of the LED) connected to the HEMTs laterally, enabling monolithic integration of the HEMTs and LEDs (HEMT-LED) without metal-interconnection. In addition to saving substrate real estate, minimal interface resistance between the regrown n-type GaN and the HEMT channel is a significant improvement over metal-interconnection. Furthermore, excellent off-state leakage characteristics of the driving transistor can also be guaranteed in such an integration scheme.

  7. Optically interconnected phased arrays

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Kunath, Richard R.

    1988-01-01

    Phased-array antennas are required for many future NASA missions. They will provide agile electronic beam forming for communications and tracking in the range of 1 to 100 GHz. Such phased arrays are expected to use several hundred GaAs monolithic integrated circuits (MMICs) as transmitting and receiving elements. However, the interconnections of these elements by conventional coaxial cables and waveguides add weight, reduce flexibility, and increase electrical interference. Alternative interconnections based on optical fibers, optical processing, and holography are under evaluation as possible solutions. In this paper, the current status of these techniques is described. Since high-frequency optical components such as photodetectors, lasers, and modulators are key elements in these interconnections, their performance and limitations are discussed.

  8. Investigation and analysis on the solder ball shear strength of plastic ball grid array, chip scale, and flip chip packages with eutectic lead-tin and lead-free solders

    NASA Astrophysics Data System (ADS)

    Huang, Xingjia

    Area array technology is one of the main themes for IC packaging in the past decade. Ball grid array (BGA), chip scale package (CSP) and flip chip (FC) packages utilize solder ball (bumps) for interconnection overwhelmingly. Nowadays, the solder ball shear test has been widely used as a standard qualification test to evaluate the solder ball attachment strength for BGA, CSP and FC packages. In this thesis, experimental observations of failure mechanisms in the solder ball shear test were performed on PBGA packages with 30-mil eutectic Pb-Sn solder balls at a fixed test condition. Three typical failure modes were identified. During the ball shear test, the solder ball undergoes substantial rigid-body rotation. For Mode I failure (the dominant mode), no crack is observed when the shear force starts to descend. For Mode II failure (the less dominant mode), a crack is initiated at the root of the solder ball at an early stage of the ball shear test. Finite element simulation on the ball shear test shows that Failure Modes I is closely related to the high regions of von Mises stress contours inside the solder. The experimental investigation on effects of shear test conditions on solder ball shear strength for PBGA, CSP and FC packages were performed. A higher shear speed and lower ram height result in a higher solder ball shear strength. The shear strength of Sn-Ag-Cu solder balls is more sensitive to the shear speed than that of eutectic Pb-Sn solder balls. Finite element models were then constructed to simulate the effect of the shear test conditions on the solder ball shear strength for PBGA with 30-mil eutectic Pb-Sn solder balls. With a scale factor (effective thickness), it is feasible to study a 3-D problem with a 2-D finite element model. The results from 2-D modeling are in agreement with the experimental data. For BGA, CSP and FC, the ideal solder ball shear test conditions are recommended to be the cases with a ram height of 10 to 20% of the ball height and a

  9. METHOD FOR SOLDERING NORMALLY NON-SOLDERABLE ARTICLES

    DOEpatents

    McGuire, J.C.

    1959-11-24

    Methods are presented for coating and joining materials which are considered difficult to solder by utilizing an abrasive wheel and applying a bar of a suitable coating material, such as Wood's metal, to the rotating wheel to fill the cavities of the abrasive wheel and load the wheel with the coating material. The surface of the base material is then rubbed against the loaded rotating wheel, thereby coating the surface with the soft coating metal. The coating is a cohesive bonded layer and holds the base metal as tenaciously as a solder holds to easily solderable metals.

  10. Fuel cell system with interconnect

    DOEpatents

    Liu, Zhien; Goettler, Richard

    2016-12-20

    The present invention includes an integrated planar, series connected fuel cell system having electrochemical cells electrically connected via interconnects, wherein the anodes of the electrochemical cells are protected against Ni loss and migration via an engineered porous anode barrier layer.

  11. Soldering ceramic-metal restorations.

    PubMed

    Presswood, R G

    1975-09-01

    This is a technique for soldering ceramic-metal restorations in a vacuum-fired furnace. Care must be exercised to prevent adherence of the flux to the porcelain surfaces. Low-heat solders have been used, but they do not flow any better and may result in a weak union. The various colors of impression plaster to form the key for removal of the assembly are used to prevent softening and distortion of the individual units. There are several techniques described in assembling and soldering ceramic-metal restorations. This technique is direct, accurate, and easily accomplished.

  12. Research study: Device technology STAR router user's guide. [automated layout of large scale integration discretionary interconnection masks

    NASA Technical Reports Server (NTRS)

    Wright, R. A.

    1979-01-01

    The STAR Router program developed to perform automated layout of LSI discretionary interconnection masks is described. The input and output for the router are standard PR2D data files. A state-of-the-art cellular path-finding procedure, based on Lee's algorithm, which produces fast, shortest distance routing of microcircuit net data is included.

  13. Performance evaluation of multi-stratum resources integration based on network function virtualization in software defined elastic data center optical interconnect.

    PubMed

    Yang, Hui; Zhang, Jie; Ji, Yuefeng; Tian, Rui; Han, Jianrui; Lee, Young

    2015-11-30

    Data center interconnect with elastic optical network is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resilience between IP and elastic optical networks that allows to accommodate data center services. In view of this, this study extends to consider the resource integration by breaking the limit of network device, which can enhance the resource utilization. We propose a novel multi-stratum resources integration (MSRI) architecture based on network function virtualization in software defined elastic data center optical interconnect. A resource integrated mapping (RIM) scheme for MSRI is introduced in the proposed architecture. The MSRI can accommodate the data center services with resources integration when the single function or resource is relatively scarce to provision the services, and enhance globally integrated optimization of optical network and application resources. The overall feasibility and efficiency of the proposed architecture are experimentally verified on the control plane of OpenFlow-based enhanced software defined networking (eSDN) testbed. The performance of RIM scheme under heavy traffic load scenario is also quantitatively evaluated based on MSRI architecture in terms of path blocking probability, provisioning latency and resource utilization, compared with other provisioning schemes.

  14. Some Observations of Solder Joint Failure Under Tensile-Compressive Stress

    NASA Technical Reports Server (NTRS)

    Winslow, J. W.

    1993-01-01

    It has long been known that solder joints under mechanical stress are subject to failure. In early electronic systems, such failures were avoided primarily by avoiding the use of solder as a mechanical structural component. The rule was to first make sound wire connections that did not depend mechanically on solder, and only then to solder them. Careful design and miniaturization in modern electronic systems limits the mechanical stresses exerted on solder joints to values less than their yield points, and these joints have become integral parts of the mechanical structures. Unfortunately, while these joints are strong enough when new, they have proven vulnerable to fatigue failures as they age.Details of the fatigue process are poorly understood, making predictions of expected lifetimes difficult.

  15. Study on Dynamic Failure Model of Lead-Free Solders Using Shpb Techniques

    NASA Astrophysics Data System (ADS)

    Niu, Xiaoyan; Yuan, Guozheng; Li, Zhigang; Shu, Xuefeng

    The dynamic compressive properties of 96.3Sn3Ag0.7Cu and 99.3Sn0.7Cu solders were studied by means of a split Hopkinson pressure bar at strain rates ranging from 500 to 2000 s-1. Tests were conducted at room temperature and under uniaxial compressive conditions. Eutectic SnPb solders were used as the reference. From the data of tests, it was found that yield strength and flow stress increased remarkably with the increase of strain rate. On logarithmic scales, the yield strength increased linearly with strain rate. These lead-free solders revealed certain visco-plastic behavior and strain rate sensitivity, which predicted using Johnson-Cook material model. Related parameters in the model were determined from the experiment. Compared with the typical Pb-containing solder Sn63Pb37, these lead-free solders showed some fine properties and could substitute some Pb-containing solder alloys in microelectronic components packaging and interconnects.

  16. Comparative shear tests of some low temperature lead-free solder pastes

    NASA Astrophysics Data System (ADS)

    Branzei, Mihai; Plotog, Ioan; Varzaru, Gaudentiu; Cucu, Traian C.

    2016-12-01

    The range of electronic components and as a consequence, all parts of automotive electronic equipment operating temperatures in a vehicle is given by the location of that equipment, so the maximum temperature can vary between 358K and 478K1. The solder joints could be defined as passive parts of the interconnection structure of automotive electronic equipment, at a different level, from boards of electronic modules to systems. The manufacturing costs reduction necessity and the RoHS EU Directive3, 7 consequences generate the trend to create new Low-Temperature Lead-Free (LTLF) solder pastes family9. In the paper, the mechanical strength of solder joints and samples having the same transversal section as resistor 1206 case type made using the same LTLF alloys into Vapour Phase Soldering (VPS) process characterized by different cooling rates (slow and rapid) and two types of test PCBs pads finish, were benchmarked at room temperature. The presented work extends the theoretical studies and experiments upon heat transfer in VPSP in order to optimize the technology for soldering process (SP) of automotive electronic modules and could be extended for home and modern agriculture appliances industry. The shear forces (SF) values of the LTLF alloy samples having the same transversal section as resistor 1206 case type will be considered as references values of a database useful in the new solder alloy creation processes and their qualification for automotive electronics domain.

  17. High density interconnection technology - Surface mount technology

    NASA Astrophysics Data System (ADS)

    Menozzi, G.

    The design features of surface mount technology (SMT) circuits for data transmission, engineering and aerospace applications are examined. Details of pin out, dual face, and interconnection techniques employed for SMT circuits mounted on plastic or ceramic leadless chip carriers are explored. The industrial processes applied to obtain the SMT boards are discussed, along with methods for quality assurance, especially for the soldered connections. SMT installations in the form of 4 Mbit multilayer circuits for an ESA project and a 32-bit mainframe computer are described.

  18. Repairable chip bonding/interconnect process

    DOEpatents

    Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

    1997-01-01

    A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

  19. Repairable chip bonding/interconnect process

    DOEpatents

    Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

    1997-08-05

    A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

  20. Electrical interconnect

    SciTech Connect

    Frost, John S.; Brandt, Randolph J.; Hebert, Peter; Al Taher, Omar

    2015-10-06

    An interconnect includes a first set of connector pads, a second set of connector pads, and a continuous central portion. A first plurality of legs extends at a first angle from the continuous central portion. Each leg of the first plurality of legs is connected to a connector pad of a first set of connector pads. A second plurality of legs extends at a second angle from the continuous central portion. Each leg of the second plurality of legs is connected to a connector pad of the second set of connector pads. Gaps are defined between legs. The gaps enable movement of the first set of connector pads relative to the second set of connector pads.

  1. Development of Readout Interconnections for the Si-W Calorimeter of SiD

    SciTech Connect

    Woods, M.; Fields, R.G.; Holbrook, B.; Lander, R.L.; Moskaleva, A.; Neher, C.; Pasner, J.; Tripathi, M.; Brau, J.E.; Frey, R.E.; Strom, D.; Breidenbach, M.; Freytag, D.; Haller, G.; Herbst, R.; Nelson, T.; Schier, S.; Schumm, B.; /UC, Santa Cruz

    2012-09-14

    The SiD collaboration is developing a Si-W sampling electromagnetic calorimeter, with anticipated application for the International Linear Collider. Assembling the modules for such a detector will involve special bonding technologies for the interconnections, especially for attaching a silicon detector wafer to a flex cable readout bus. We review the interconnect technologies involved, including oxidation removal processes, pad surface preparation, solder ball selection and placement, and bond quality assurance. Our results show that solder ball bonding is a promising technique for the Si-W ECAL, and unresolved issues are being addressed.

  2. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  3. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  4. Interconnecting heterogeneous database management systems

    NASA Technical Reports Server (NTRS)

    Gligor, V. D.; Luckenbaugh, G. L.

    1984-01-01

    It is pointed out that there is still a great need for the development of improved communication between remote, heterogeneous database management systems (DBMS). Problems regarding the effective communication between distributed DBMSs are primarily related to significant differences between local data managers, local data models and representations, and local transaction managers. A system of interconnected DBMSs which exhibit such differences is called a network of distributed, heterogeneous DBMSs. In order to achieve effective interconnection of remote, heterogeneous DBMSs, the users must have uniform, integrated access to the different DBMs. The present investigation is mainly concerned with an analysis of the existing approaches to interconnecting heterogeneous DBMSs, taking into account four experimental DBMS projects.

  5. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ...-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in any container that makes use of...

  6. Investigation of welded interconnection of large area wraparound contacted silicon solar cells

    NASA Technical Reports Server (NTRS)

    Lott, D. R.

    1984-01-01

    An investigation was conducted to evaluate the welding and temperature cycle testing of large area 5.9 x 5.9 wraparound silicon solar cells utilizing printed circuit substrates with SSC-155 interconnect copper metals and the LMSC Infrared Controlled weld station. An initial group of 5 welded modules containing Phase 2 developmental 5.9 x 5.9 cm cells were subjected to cyclical temperatures of + or 80 C at a rate of 120 cycles per day. Anomalies were noted in the adhesion of the cell contact metallization; therefore, 5 additional modules were fabricated and tested using available Phase I cells with demonstrated contact integrity. Cycling of the later module type through 12,000 cycles indicated the viability of this type of lightweight flexible array concept. This project demonstrated acceptable use of an alternate interconnect copper in combination with large area wraparound cells and emphasized the necessity to implement weld pull as opposed to solder pull procedures at the cell vendors for cells that will be interconnected by welding.

  7. Interconnects, Transmitters, and Receivers

    NASA Astrophysics Data System (ADS)

    Hoefflinger, Bernd

    Interconnects on-chip between transistors and between functions like processors and memories, between chips on carriers or in stacks, and the communication with the outside world have become a highly complex performance, reliability, cost, and energy challenge. Twelve layers of metal interconnects, produced by lithography, require, including the contact vias, 24 mask and process cycles on top of the process front-end. The resulting lines are associated with resistance, capacitance and inductance parasitics as well as with ageing due to high current densities. Large savings in wiring lengths are achieved with 3D integration: transistor stacking, chip stacking and TSV's, a direction, which has exploded since 2005 because of many other benefits and, at the same time, with sensitive reliability and cost issues. On top of this or as an alternative, non-contact interconnects are possible with capacitive or inductive coupling. Inductive in particular has proven to be attractive because its transmission range is large enough for communication in chip stacks and yet not too large to cause interference.Optical transmitters based on integrated III-V compound-semiconductor lasers and THz power amplifiers compete with ascending low-cost, parallel-wire transmitters based on BiCMOS technologies. Parallel mm-wave and THz transceiver arrays enable mm-wave radar for traffic safety and THz computed-tomography. In spite of all these technology advances, the power efficiency of data communication will only improve 100× in a decade. New compression and architectural techniques are in high demand.

  8. Post-soldering of nonprecious alloys.

    PubMed

    Saxton, P L

    1980-05-01

    A repeatable post-soldering technique for a nonprecious alloy has been described. With proper metal design, nonprecious alloy crowns can be soldered in a standard vacuum porcelain furnace. Scanning electron micrographs and EDXA confirm that a good union has taken place between the gold solder and nickel alloy.

  9. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 3 2010-04-01 2009-04-01 true Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  10. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 3 2012-04-01 2012-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  11. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 3 2011-04-01 2011-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  12. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 3 2013-04-01 2013-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  13. Solders in Real Electronic Joints

    NASA Astrophysics Data System (ADS)

    Rudajevová, A.; Dušek, K.

    2014-07-01

    Undercooling and recalescence were studied using the differential scanning calorimetry (DSC) method on real electronic systems. Two solder pastes, Sn62.5Pb36.5Ag1 and Sn96.5Ag3Cu0.5, were used for preparation of electronic joints. Various combinations of these solders and soldering pads with different surface finishes such as Cu, Cu-Ni-Au, Cu-Sn, and Cu-Sn99Cu1 were used. During melting of both pastes, the Sn and Sn99Cu1 surface finishes immediately dissolved in the solder and the Cu surface coating was exposed to the melt. Therefore, practically the same undercooling was found for the Cu, Cu-Sn, and Cu-Sn99Cu1 coatings. The lowest undercooling was found for the Cu-Ni-Au surface finish for both solder pastes. If two separated electronic joints were made on the sample, two separate peaks were found in the DSC signal during solidification. In the sample with only one joint, only one exothermic peak was found. These findings were observed for all paste/surface finish combinations. These data were analyzed, showing that this effect is a consequence of undercooling and recalescence: Latent heat released during solidification of the joint increases the surrounding temperature and influences all the processes taking place.

  14. Release Resistant Electrical Interconnections For Mems Devices

    DOEpatents

    Peterson, Kenneth A.; Garrett, Stephen E.; Reber, Cathleen A.

    2005-02-22

    A release resistant electrical interconnection comprising a gold-based electrical conductor compression bonded directly to a highly-doped polysilicon bonding pad in a MEMS, IMEMS, or MOEMS device, without using any intermediate layers of aluminum, titanium, solder, or conductive adhesive disposed in-between the conductor and polysilicon pad. After the initial compression bond has been formed, subsequent heat treatment of the joint above 363 C creates a liquid eutectic phase at the bondline comprising gold plus approximately 3 wt % silicon, which, upon re-solidification, significantly improves the bond strength by reforming and enhancing the initial bond. This type of electrical interconnection is resistant to chemical attack from acids used for releasing MEMS elements (HF, HCL), thereby enabling the use of a "package-first, release-second" sequence for fabricating MEMS devices. Likewise, the bond strength of an Au--Ge compression bond may be increased by forming a transient liquid eutectic phase comprising Au-12 wt % Ge.

  15. Advanced Interconnect Development

    SciTech Connect

    Yang, Z.G.; Maupin, G.; Simner, S.; Singh, P.; Stevenson, J.; Xia, G.

    2005-01-27

    The objectives of this project are to develop cost-effective, optimized materials for intermediate temperature SOFC interconnect and interconnect/electrode interface applications and identify and understand degradation processes in interconnects and at their interfaces with electrodes.

  16. Interconnection networks

    DOEpatents

    Faber, V.; Moore, J.W.

    1988-06-20

    A network of interconnected processors is formed from a vertex symmetric graph selected from graphs GAMMA/sub d/(k) with degree d, diameter k, and (d + 1)exclamation/ (d /minus/ k + 1)exclamation processors for each d greater than or equal to k and GAMMA/sub d/(k, /minus/1) with degree d /minus/ 1, diameter k + 1, and (d + 1)exclamation/(d /minus/ k + 1)exclamation processors for each d greater than or equal to k greater than or equal to 4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network GAMMA/sub d/(k, /minus/1) is provided, no processor has a channel connected to form an edge in a direction delta/sub 1/. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations. 9 figs.

  17. Undercooling Behavior and Intermetallic Compound Coalescence in Microscale Sn-3.0Ag-0.5Cu Solder Balls and Sn-3.0Ag-0.5Cu/Cu Joints

    NASA Astrophysics Data System (ADS)

    Zhou, M. B.; Ma, X.; Zhang, X. P.

    2012-11-01

    The microstructure of microscale solder interconnects and soldering defects have long been known to have a significant influence on the reliability of electronic packaging, and both are directly related to the solidification behavior of the undercooled solder. In this study, the undercooling behavior and solidification microstructural evolution of Sn-3.0Ag-0.5Cu solder balls with different diameters (0.76 mm, 0.50 mm, and 0.30 mm) and the joints formed by soldering these balls on Cu open pads of two diameters (0.48 mm and 0.32 mm) on a printed circuit board (PCB) substrate were characterized by differential scanning calorimetry (DSC) incorporated into the reflow process. Results show that the decrease in diameter of the solder balls leads to an obvious increase in the undercooling of the balls, while the undercooling of the solder joints shows a dependence on both the diameter of the solder balls and the diameter ratio of solder ball to Cu pad (i.e., D s/ D p), and the diameter of the solder balls has a stronger influence on the undercooling of the joints than the dimension of the Cu pad. Coarse primary intermetallic compound (IMC) solidification phases were formed in the smaller solder balls and joints. The bulk Ag3Sn IMC is the primary solidification phase in the as-reflowed solder balls. Due to the interfacial reaction and dissolution of Cu atoms into the solder matrix, the primary Ag3Sn phase can be suppressed and the bulk Cu6Sn5 IMC is the only primary solidification phase in the as-reflowed solder joints.

  18. Interconnected semiconductor devices

    DOEpatents

    Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

    1990-10-23

    Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

  19. Solder Joint Health Monitoring Testbed

    NASA Technical Reports Server (NTRS)

    Delaney, Michael M.; Flynn, James G.; Browder, Mark E.

    2009-01-01

    A method of monitoring the health of selected solder joints, called SJ-BIST, has been developed by Ridgetop Group Inc. under a Small Business Innovative Research (SBIR) contract. The primary goal of this research program is to test and validate this method in a flight environment using realistically seeded faults in selected solder joints. An additional objective is to gather environmental data for future development of physics-based and data-driven prognostics algorithms. A test board is being designed using a Xilinx FPGA. These boards will be tested both in flight and on the ground using a shaker table and an altitude chamber.

  20. Self assembled structures for 3D integration

    NASA Astrophysics Data System (ADS)

    Rao, Madhav

    Three dimensional (3D) micro-scale structures attached to a silicon substrate have various applications in microelectronics. However, formation of 3D structures using conventional micro-fabrication techniques are not efficient and require precise control of processing parameters. Self assembly is a method for creating 3D structures that takes advantage of surface area minimization phenomena. Solder based self assembly (SBSA), the subject of this dissertation, uses solder as a facilitator in the formation of 3D structures from 2D patterns. Etching a sacrificial layer underneath a portion of the 2D pattern allows the solder reflow step to pull those areas out of the substrate plane resulting in a folded 3D structure. Initial studies using the SBSA method demonstrated low yields in the formation of five different polyhedra. The failures in folding were primarily attributed to nonuniform solder deposition on the underlying metal pads. The dip soldering method was analyzed and subsequently refined. A modified dip soldering process provided improved yield among the polyhedra. Solder bridging referred as joining of solder deposited on different metal patterns in an entity influenced the folding mechanism. In general, design parameters such as small gap-spacings and thick metal pads were found to favor solder bridging for all patterns studied. Two types of soldering: face and edge soldering were analyzed. Face soldering refers to the application of solder on the entire metal face. Edge soldering indicates application of solder only on the edges of the metal face. Mechanical grinding showed that face soldered SBSA structures were void free and robust in nature. In addition, the face soldered 3D structures provide a consistent heat resistant solder standoff height that serve as attachments in the integration of dissimilar electronic technologies. Face soldered 3D structures were developed on the underlying conducting channel to determine the thermo-electric reliability of

  1. Soldering Technology (4th) Proceedings of Annual Seminar, 20-21 February 1980.

    DTIC Science & Technology

    1980-02-01

    es- temperature. The size of the solder 3lobule to be used is related r to wire diameter under test. Time may be measured automatically via electrical ...mo=ed on a rocating arm which carried them ino tangential contac with a dross free solder surface. An electrical contact probe allows measur mez of the...both sheet or wtre specimens but not printed circuit boards. Being the most recently inovated test it has not yet been fully integrated into

  2. Creep-Fatigue Crack Growth Behavior of Pb-Containing and Pb-Free Solders at Room and Elevated Temperatures

    NASA Astrophysics Data System (ADS)

    Fakpan, Kittichai; Otsuka, Yuichi; Mutoh, Yoshiharu; Inoue, Shunsuke; Nagata, Kohsoku; Kodani, Kazuya

    2012-09-01

    Fatigue crack growth tests of lead-containing (Sn-37Pb) and lead-free (Sn-3.0Ag-0.5Cu) solders were conducted at frequencies ranging from 0.1 Hz to 10 Hz at stress ratio of 0.1, at room temperature and at 70°C. The J-integral range (Δ J) and the modified J-integral ( C *) were used in assessing the cycle-dependent and time-dependent crack growth behavior for both solders. The experimental results showed that the crack growth behavior of both solders at the lower frequency and higher temperature was predominantly time dependent, whereas the crack growth behavior of both solders at the higher frequency and lower temperature was predominantly cycle dependent, with the transition in fatigue crack growth behavior from cycle dependent to time dependent expressed as f + 6500exp(1/ T) = 6520. In both the cycle-dependent and time-dependent regions, the crack growth resistance of the lead-free solder was higher than that of lead-containing solder. Fracture surface observations showed that, as the frequency decreased and/or the temperature increased, the fracture path changed from transgranular to intergranular for Sn-37Pb solder, and from transgranular to mixed transgranular-intergranular for Sn-3.0Ag-0.5Cu solder.

  3. Microstructure of lead-free solder bumps using laser reflow soldering

    NASA Astrophysics Data System (ADS)

    Nishikawa, Hiroshi; Iwata, Noriya; Kubota, Shinya

    2014-08-01

    Compared with conventional reflow soldering using a furnace, laser reflow soldering brings advantages such as localized heating, rapid rise and fall in temperature, non-contact soldering and the fact that it is an easily automated process. In this study, to elucidate the characteristics of laser reflow soldering, we investigated the microstructures of a Sn-Ag-Cu solder bump and a Sn-Bi solder bump on a Cu pad after reflow and aging. In the as-soldered condition, we found obvious microstructural refinement and a thin intermetallic compound (IMC) layer at the interface for both the Sn-Ag-Cu solder bump and the Sn-Bi solder bump using laser reflow soldering. Also, during isothermal aging, the total thickness of the IMC layer increased, and a distinct second layer was observed at the interface between the Cu pad and the first layer, regardless of the soldering method. In particular, the growth of the IMC layer was faster in the case of the laser reflow soldering than in the case of the conventional reflow soldering.

  4. NTF: Soldering Technology Development for Cryogenics

    NASA Technical Reports Server (NTRS)

    Hall, E. T., Jr.

    1985-01-01

    The advent of the National Transonic Facility (NTF) brought about a new application for an old joining method, soldering. Soldering for use at cryogenic temperatures requires that solders remain ductile and free from tin-pest (grey tin), have toughness to withstand aerodynamic loads associated with flight research, and maintain their surface finishes. Solders are used to attach 347 Stainless-Steel tubing in surface grooves of models. The solder must fill up the gap and metallurgically bound to the tubing and model. Cryogenic temperatures require that only specific materials for models can be used, including: Vasco Max 200 CVM, lescalloy A-286 Vac Arc, pH 13-8 Mo. Solders identified for testing at this time are: 50% Sn - 49.5% Pb - 0.5% Sb, 95% Sn - 5% Sb, 50% In 50% Pb, and 37.5% Sn - 37.5% Pb - 25% In. With these materials and solders, it is necessary to determine their solderability. After solderability is determined, tube/groove specimens are fabricated and stressed under cryogenic temperatures. Compatible solders are then used for acutual models.

  5. Polymeric optoelectronic interconnects

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.

    2000-04-01

    Electrical interconnects are reaching their fundamental limits and are becoming the speed bottleneck as processor speeds are increasing. A polymer-based interconnect technology was developed for affordable integrated optical circuits that address the optical signal processing needs in the telecom, datacom, and performance computing industries. We engineered organic polymers that can be readily made into single-mode, multimode, and micro-optical waveguide structures of controlled numerical apertures and geometries. These materials are formed from highly-crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, robustness, optical loss, thermal stability, and humidity resistance. These monomers are intermiscible, providing for precise continuous adjustment of the refractive index over a wide range. In polymer form, they exhibit state-of-the-art loss values and exceptional environmental stability, enabling use in a variety of demanding applications. A wide range of rigid and flexible substrates can be used, including glass, quartz, silicon, glass-filled epoxy printed circuit board substrates, and flexible plastic films. The devices we describe include a variety of routing elements that can be sued as part of a massively parallel photonic integrated circuit on the MCM, board, or backplane level.

  6. Microstructurally based thermomechanical fatigue lifetime model of solder joints for electronic applications

    SciTech Connect

    Frear, D.R.; Rashid, M.M.; Burchett, S.N.

    1993-07-01

    We present a new methodology for predicting the fatigue life of solder joints for electronics applications. This approach involves integration of experimental and computational techniques. The first stage involves correlating the manufacturing and processing parameters with the starting microstructure of the solder joint. The second stage involves a series of experiments that characterize the evolution of the microstructure during thermal cycling. The third stage consists of a computer modeling and simulation effort that utilizes the starting microstructure and experimental data to produce a reliability prediction of the solder joint. This approach is an improvement over current methodologies because it incorporates the microstructure and properties of the solder directly into the model and allows these properties to evolve as the microstructure changes during fatigue.

  7. Microstructurally based thermomechanical fatigue lifetime model of solder joints for electronic applications

    NASA Astrophysics Data System (ADS)

    Frear, D. R.; Rashid, M. M.; Burchett, S. N.

    We present a new methodology for predicting the fatigue life of solder joints for electronics applications. This approach involves integration of experimental and computational techniques. The first stage involves correlating the manufacturing and processing parameters with the starting microstructure of the solder joint. The second stage involves a series of experiments that characterize the evolution of the microstructure during thermal cycling. The third stage consists of a computer modeling and simulation effort that utilizes the starting microstructure and experimental data to produce a reliability prediction of the solder joint. This approach is an improvement over current methodologies because it incorporates the microstructure and properties of the solder directly into the model and allows these properties to evolve as the microstructure changes during fatigue.

  8. Use of optoelectronic tweezers in manufacturing—accurate solder bead positioning

    NASA Astrophysics Data System (ADS)

    Zhang, Shuailong; Liu, Yongpeng; Juvert, Joan; Tian, Pengfei; Navarro, Jean-Claude; Cooper, Jonathan M.; Neale, Steven L.

    2016-11-01

    In this work, we analyze the use of optoelectronic tweezers (OETs) to manipulate 45 μm diameter Sn62Pb36Ag2 solder beads with light-induced dielectrophoresis force and we demonstrate high positioning accuracy. It was found that the positional deviation of the solder beads increases with the increase of the trap size. To clarify the underlying mechanism, simulations based on the integration of the Maxwell stress tensor were used to study the force profiles of OET traps with different sizes. It was found that the solder beads felt a 0.1 nN static friction or stiction force due to electrical forces pulling them towards the surface and that this force is not dependent on the size of the trap. The stiction limits the positioning accuracy; however, we show that by choosing a trap that is just larger than the solder bead sub-micron positional accuracy can be achieved.

  9. Thermal Cycling Fatigue in DIPs Mounted with Eutectic Tin-Lead Solder Joints in Stub and Gullwing Geometries

    NASA Technical Reports Server (NTRS)

    Winslow, J. W.; Silveira, C. de

    1993-01-01

    It has long been known that solder joints under mechanical stress are subject to failure. In early electronic systems, such failures were avoided primarily by avoiding the use of solder as a mechanical structural component. The rule was first to make sound wire connections that did not depend mechanically on solder, and only then to solder them. Careful design and miniaturization in modern electronic systems limits the mechanical stresses exerted on solder joints to values less than their yield points, and these joints have become integral parts of the mechanical structures. Unfortunately, while these joints are strong enough when new, they have proven vulnerable to fatigue failures as they age. Details of the fatigue process are poorly understood, making predictions of expected lifetimes difficult.

  10. Silver flip chip interconnect technology and solid state bonding

    NASA Astrophysics Data System (ADS)

    Sha, Chu-Hsuan

    -section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active

  11. Tin soldering of aluminum and its alloys

    NASA Technical Reports Server (NTRS)

    Gallo, Gino

    1921-01-01

    A method is presented for soldering aluminum to other metals. The method adopted consists of a galvanic application to the surface of the light-metal parts to be soldered, of a layer of another metal, which, without reacting electrolytically on the aluminum, adheres strongly to the surface to which it is applied, and is, on the other hand, adapted to receive the soft solder. The metal found to meet the criteria best was iron.

  12. Role of W and Mn for reliable 1X nanometer-node ultra-large-scale integration Cu interconnects proved by atom probe tomography

    SciTech Connect

    Shima, K.; Shimizu, H.; Momose, T.; Shimogaki, Y.; Tu, Y.; Takamizawa, H.; Shimizu, Y.; Inoue, K.; Nagai, Y.

    2014-09-29

    We used atom probe tomography (APT) to study the use of a Cu(Mn) as a seed layer of Cu, and a Co(W) single-layer as reliable Cu diffusion barriers for future interconnects in ultra-large-scale integration. The use of Co(W) layer enhances adhesion of Cu to prevent electromigration and stress-induced voiding failures. The use of Cu(Mn) as seed layer may enhance the diffusion barrier performance of Co(W) by stuffing the Cu diffusion pass with Mn. APT was used to visualize the distribution of W and Mn in three dimensions with sub-nanometer resolution. W was found to segregate at the grain boundaries of Co, which prevents diffusion of Cu via the grain boundaries. Mn was found to diffuse from the Cu(Mn) layer to Co(W) layer and selectively segregate at the Co(W) grain boundaries with W, reinforcing the barrier properties of Co(W) layer. Hence, a Co(W) barrier coupled with a Cu(Mn) seed layer can form a sufficient diffusion barrier with film that is less than 2.0-nm-thick. The diffusion barrier behavior was preserved following a 1-h annealing at 400 °C. The underlayer of the Cu interconnects requires a large adhesion strength with the Cu, as well as low electrical resistivity. The use of Co(W) has previously been shown to satisfy these requirements, and addition of Mn is not expected to deteriorate these properties.

  13. Die Soldering in Aluminium Die Casting

    SciTech Connect

    Han, Q.; Kenik, E.A.; Viswanathan, S.

    2000-03-15

    Two types of tests, dipping tests and dip-coating tests were carried out on small steel cylinders using pure aluminum and 380 alloy to investigate the mechanism of die soldering during aluminum die casting. Optical and scanning electron microscopy were used to study the morphology and composition of the phases formed during soldering. A soldering mechanism is postulated based on experimental observations. A soldering critical temperature is postulated at which iron begins to react with aluminum to form an aluminum-rich liquid phase and solid intermetallic compounds. When the temperature at the die surface is higher than this critical temperature, the aluminum-rich phase is liquid and joins the die with the casting during the subsequent solidification. The paper discusses the mechanism of soldering for the case of pure aluminum and 380 alloy casting in a steel mold, the factors that promote soldering, and the strength of the bond formed when soldering occurs. conditions, an aluminum-rich soldering layer may also form over the intermetallic layer. Although a significant amount of research has been conducted on the nature of these intermetallics, little is known about the conditions under which soldering occurs.

  14. Fatigue failure kinetics and structural changes in lead-free interconnects due to mechanical and thermal cycling

    NASA Astrophysics Data System (ADS)

    Fiedler, Brent Alan

    Environmental and human health concerns drove European parliament to mandate the Reduction of Hazardous Substances (RoHS) for electronics. This was enacted in July 2006 and has practically eliminated lead in solder interconnects. There is concern in the electronics packaging community because modern lead-free solder is rich in tin. Presently, near-eutectic tin-silver-copper solders are favored by industry. These solders are stiffer than the lead-tin near-eutectic alloys, have a higher melting temperature, fewer slip systems, and form intermetallic compounds (IMC) with Cu, Ni and Ag, each of which tend to have a negative effect on lifetime. In order to design more reliable interconnects, the experimental observation of cracking mechanisms is necessary for the correct application of existing theories. The goal of this research is to observe the failure modes resulting from mode II strain and to determine the damage mechanisms which describe fatigue failures in 95.5 Sn- 4.0 Ag - 0.5 Cu wt% (SAC405) lead-free solder interconnects. In this work the initiation sites and crack paths were characterized for SAC405 ball-grid array (BGA) interconnects with electroless-nickel immersion-gold (ENIG) pad-finish. The interconnects were arranged in a perimeter array and tested in fully assembled packages. Evaluation methods included monotonic and displacement controlled mechanical shear fatigue tests, and temperature cycling. The specimens were characterized using metallogaphy, including optical and electron microscopy as well as energy dispersive spectroscopy (EDS) and precise real-time electrical resistance structural health monitoring (SHM). In mechanical shear fatigue tests, strain was applied by the substrates, simulating dissimilar coefficients of thermal expansion (CTE) between the board and chip-carrier. This type of strain caused cracks to initiate in the soft Sn-rich solder and grow near the interface between the solder and intermetallic compounds (IMC). The growth near

  15. Printed Module Interconnects

    SciTech Connect

    Stockert, Talysa R.; Fields, Jeremy D.; Pach, Gregory F.; Mauger, Scott A.; van Hest, Maikel F. A. M.

    2015-06-14

    Monolithic interconnects in photovoltaic modules connect adjacent cells in series, and are typically formed sequentially involving multiple deposition and scribing steps. Interconnect widths of 500 um every 10 mm result in 5% dead area, which does not contribute to power generation in an interconnected solar panel. This work expands on previous work that introduced an alternative interconnection method capable of producing interconnect widths less than 100 um. The interconnect is added to the module in a single step after deposition of the photovoltaic stack, eliminating the need for scribe alignment. This alternative method can be used for all types of thin film photovoltaic modules. Voltage addition with copper-indium-gallium-diselenide (CIGS) solar cells using a 2-scribe printed interconnect approach is demonstrated. Additionally, interconnect widths of 250 um are shown.

  16. Design and analysis of tilt integral derivative controller with filter for load frequency control of multi-area interconnected power systems.

    PubMed

    Kumar Sahu, Rabindra; Panda, Sidhartha; Biswal, Ashutosh; Chandra Sekhar, G T

    2016-03-01

    In this paper, a novel Tilt Integral Derivative controller with Filter (TIDF) is proposed for Load Frequency Control (LFC) of multi-area power systems. Initially, a two-area power system is considered and the parameters of the TIDF controller are optimized using Differential Evolution (DE) algorithm employing an Integral of Time multiplied Absolute Error (ITAE) criterion. The superiority of the proposed approach is demonstrated by comparing the results with some recently published heuristic approaches such as Firefly Algorithm (FA), Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) optimized PID controllers for the same interconnected power system. Investigations reveal that proposed TIDF controllers provide better dynamic response compared to PID controller in terms of minimum undershoots and settling times of frequency as well as tie-line power deviations following a disturbance. The proposed approach is also extended to two widely used three area test systems considering nonlinearities such as Generation Rate Constraint (GRC) and Governor Dead Band (GDB). To improve the performance of the system, a Thyristor Controlled Series Compensator (TCSC) is also considered and the performance of TIDF controller in presence of TCSC is investigated. It is observed that system performance improves with the inclusion of TCSC. Finally, sensitivity analysis is carried out to test the robustness of the proposed controller by varying the system parameters, operating condition and load pattern. It is observed that the proposed controllers are robust and perform satisfactorily with variations in operating condition, system parameters and load pattern.

  17. Laser soldering of enameled wires

    NASA Astrophysics Data System (ADS)

    Böhm, S.; Hemken, G.; Noack, K.

    2009-02-01

    In electrical connections with enameled copper wires, isolation material residue can be found in the solder area when the coating is not stripped. This residue can lead to mechanical and electrical problems. In electronic devices and MEMS, quality requirements increase with rising thermal requirements for electrical contacts made from enameled copper wire. Examples for this exist in the area of automotive electronics, consumer electronics and in the field of machine design. Typical products with electrical connecting which use enameled wires include: micro-phones and speakers (especially for mobile phones), coil forms, small transformers, relays, clock coils, and so on. Due to increasing thermal and electrical requirements, the manufacturer of enameled wires continuously develops new isolating materials for the improvement of isolation classes, thermal resistance, etc. When using current bonding and solder processes, there exist problems for contacting enameled copper wire with these insulation layers. Therefore the Institute of Joining and Welding, Department Micro Joining developed a laser based solder process with which enamels copper wires can enable high quality electrical connections without a preceding stripping process.

  18. Effects of hydration on laser soldering

    NASA Astrophysics Data System (ADS)

    Chan, Eric K.; Brown, Dennis T.; Kovach, Ian S.; Welch, Ashley J.

    1997-05-01

    Laser welding with albumin-based tissue solder has been investigated as an alternative to surgical suturing. Many surgical procedures require the soldered tissues to be in a hydrated environment. We have studied the effects of hydration on laser soldered rat dermis and baboon articular cartilage in vitro. The solder is composed of human serum albumin, sodium hyaluronate and indocyanine green. We used a micro-pipette to deposit 2 (mu) l of solder on each tissue specimen. An 808 nm cw laser beam with irradiance of 27 W/cm2 was scanned 4 times over the same solder area at a constant speed of 0.84 mm/sec. After photo-coagulation, each tissue specimen was cut into two halves at the center of the solder, perpendicular to the direction of the scanning laser beam. One half was reserved as control while the other half was soaked in phosphate buffered saline for a designated hydration period. The hydration periods were 1 hr, 1, 2, and 7 days. All tissue specimens were fixed in glutaraldahyde, then prepared for scanning electron microcopy analysis. For most of the specimens, there was non-uniform coagulation across the thickness of the solder. Closer to the laser beam, the upper solder region formed a more dense coagulum. While the region closer to solder-tissue interface, the solder aggregated into small globules. This non-uniform coagulation was likely caused by non-uniform energy distribution during photocoagulation. The protein globules and coagulum seem to be responsible for the solder attachment from the specimen surface. However, we have noted that the solder detached from the cartilage substrate as early as after 1 hr of hydration. On the other hand, the solder attached to the dermis much better than to cartilage. This may be explained by the difference in surface roughness of the two tissue types. The dermal layer of the skin is composed of collagen matrix which may provide a better entrapment of the solder than the smooth surface of articular cartilage.

  19. Effect of ashing conditions and optimization of nano process integration in copper/porous low-k nano-interconnects.

    PubMed

    Pyo, Sung Gyu; Kim, Soo Won

    2012-11-01

    We report the optimization of ashing conditions and the process integration of a chemical vapor deposition (CVD) ultra low-k (k = 2.2) organosilicate (OSG) dielectric in a top hard mask damascene structure. The N2/H2 ash showed the lowest resistance-capacitance (RC) product and a dual top hard mask approach for dual damascene processing was built, using 200 nm SiC/50 nm SiO2 as the hard mask. This CVD low-k material had no low-k voiding, unlike other spin-on dielectric (SOD) low-k materials. The presence of the densified layer around the trench during the ashing process could improve the precursor penetration during the CVD barrier metal deposition process.

  20. Cartan's soldered spaces and conservation laws in physics

    NASA Astrophysics Data System (ADS)

    Kouneiher, Joseph; Barbachoux, Cécile

    2015-06-01

    In this paper, we will introduce a generalized soldering p-forms geometry, which can be the right framework to describe many new approaches and concepts in modern physics. Here we will treat some aspects of the theory of local cohomology in fields theory or more precisely the theory of soldering-form conservation laws in physics. We provide some illustrative applications, primarily taken from the Einstein equations of general theory of relativity and Yang-Mills theory. This theory can be considered to be a generalization of Noether's theory of conserved current to differential forms of any degree. An essential result of this, is that the conservation of the energy-momentum in general relativity, is linked to the fact that the vacuum field equations are equivalent to the integrability conditions of a first-order system of differential equations. We also apply the idea of the soldered space and the integrability conditions to the case of Yang-Mills theory. The mathematical framework, where these intuitive considerations would fit naturally, can be used to describe also the dynamics of changing manifolds.

  1. Nano-soldering to single atomic layer

    DOEpatents

    Girit, Caglar O.; Zettl, Alexander K.

    2011-10-11

    A simple technique to solder submicron sized, ohmic contacts to nanostructures has been disclosed. The technique has several advantages over standard electron beam lithography methods, which are complex, costly, and can contaminate samples. To demonstrate the soldering technique graphene, a single atomic layer of carbon, has been contacted, and low- and high-field electronic transport properties have been measured.

  2. Experiments and Demonstrations with Soldering Guns.

    ERIC Educational Resources Information Center

    Henry, Dennis C.; Danielson, Sarah A.

    1993-01-01

    Discusses the essential electrical characteristics of a particular model of soldering gun. Presents four classroom demonstrations that utilize the soldering gun to test the following geometrics of wire loops as electromagnets: (1) the original tip; (2) a single circular loop; (3) a Helmholtz coil; and (4) the solenoid. (MDH)

  3. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  4. Evaluation of Bulk Mechanical Properties of Selected Lead-Free Solders in Tension and in Shear

    NASA Astrophysics Data System (ADS)

    Devaki Rani, S.; Murthy, G. S.

    2013-08-01

    Lead-free solders are fast emerging as better alternatives to Sn-Pb solders. The reliability of a soldered joint to withstand imposed stresses in an assembly is decided by its mechanical properties. The present work is about the investigation of tensile and shear properties of four binary eutectic alloys Sn-3.5Ag, Sn-58Bi, Sn-0.7Cu, Sn-9Zn and a ternary alloy Sn-57Bi-1.3Zn in comparison with conventional Sn-38Pb alloy. It is observed that the lead-free solders have better mechanical properties than the latter. SEM studies of tensile and shear fracture show ductile dimples circular in tension and parabolic in shear modes supporting the mechanical behavior of the alloys investigated. Eutectic alloys Sn-Ag, Sn-Zn, and Sn-Cu form potential substitutes for Sn-Pb for electronic interconnects exposed to high temperatures, while Sn-Bi and Sn-Bi-Zn are attractive alternatives in addressing the need of lower processing temperatures in printed circuit boards and other applications.

  5. Comparison of Extensive Thermal Cycling Effects on Microstructure Development in Micro-alloyed Sn-Ag-Cu Solder Joints

    SciTech Connect

    Anderson, Iver E.; Boesenberg, Adam; Harringa, Joel; Riegner, David; Steinmetz, Andrew; Hillman, David

    2011-09-28

    Pb-free solder alloys based on the Sn-Ag-Cu (SAC) ternary eutectic have promise for widespread adoption across assembly conditions and operating environments, but enhanced microstructural control is needed. Micro-alloying with elements such as Zn was demonstrated for promoting a preferred solidification path and joint microstructure earlier in simple (Cu/Cu) solder joints studies for different cooling rates. This beneficial behavior now has been verified in reworked ball grid array (BGA) joints, using dissimilar SAC305 (Sn-3.0Ag-0.5Cu, wt.%) solder paste. After industrial assembly, BGA components joined with Sn-3.5Ag-0.74Cu-0.21Zn solder were tested in thermal cycling (-55 C/+125 C) along with baseline SAC305 BGA joints beyond 3000 cycles with continuous failure monitoring. Weibull analysis of the results demonstrated that BGA components joined with SAC + Zn/SAC305 have less joint integrity than SAC305 joints, but their lifetime is sufficient for severe applications in consumer, defense, and avionics electronic product field environments. Failure analysis of the BGA joints revealed that cracking did not deviate from the typical top area (BGA component side) of each joint, in spite of different Ag3Sn blade content. Thus, SAC + Zn solder has not shown any advantage over SAC305 solder in these thermal cycling trials, but other characteristics of SAC + Zn solder may make it more attractive for use across the full range of harsh conditions of avionics or defense applications.

  6. Laser soldering of flip-chips

    NASA Astrophysics Data System (ADS)

    Kordás, K.; Pap, A. E.; Tóth, G.; Pudas, M.; Jääskeläinen, J.; Uusimäki, A.; Vähäkangas, J.

    2006-02-01

    A novel process for laser soldering of flip-chips on transparent printed circuit board assemblies is presented. The experiments were carried out on silver test patterns printed on glass wafers using a roller-type gravure offset printing method. The contact pads, where the bumps of the flip-chips are positioned, were covered with a thin layer of additional solder paste. The aligned samples (solder pad—solder paste—chip bump) were illuminated through the glass substrate using an Ar + laser beam ( λ=488 nm, P=0.6-3.0 W, d=100 μm at 1/e) to heat the printed pad and melt the solder paste, thus forming a joint between the printed pad and the chip bump. The heat-affected zone was modeled using computer-assisted finite element method. The solder joint cross-sections were analyzed using optical and electron microscopy as well as energy dispersive X-ray element analyses. The laser-soldered joints were of good mechanical and electrical quality and the process proved to be suitable for manufacturing customized circuit prototypes.

  7. Perforation patterned electrical interconnects

    SciTech Connect

    Frey, Jonathan

    2014-01-28

    This disclosure describes systems and methods for increasing the usable surface area of electrical contacts within a device, such as a thin film solid state device, through the implementation of electrically conductive interconnects. Embodiments described herein include the use of a plurality of electrically conductive interconnects that penetrate through a top contact layer, through one or more multiple layers, and into a bottom contact layer. The plurality of conductive interconnects may form horizontal and vertical cross-sectional patterns. The use of lasers to form the plurality of electrically conductive interconnects from reflowed layer material further aids in the manufacturing process of a device.

  8. A study of thermal cycling and radiation effects on indium and solder bump bonding

    SciTech Connect

    Selcuk Cihangir et al.

    2001-09-12

    The BTeV hybrid pixel detector is constructed of readout chips and sensor arrays which are developed separately. The detector is assembled by flip-chip mating of the two parts. This method requires the availability of highly reliable, reasonably low cost fine-pitch flip-chip attachment technology. We have tested the quality of two bump-bonding technologies; indium bumps (by Advanced Interconnect Technology Ltd. (AIT) of Hong Kong) and fluxless solder bumps (by MCNC in North Carolina, USA). The results have been presented elsewhere[1]. In this paper we describe tests we performed to further evaluate these technologies. We subjected 15 indium bump-bonded and 15 fluxless solder bump-bonded dummy detectors through a thermal cycle and then a dose of radiation to observe the effects of cooling, heating and radiation on bump-bonds.

  9. Electromigration kinetics and critical current of Pb-free interconnects

    SciTech Connect

    Lu, Minhua; Rosenberg, Robert

    2014-04-07

    Electromigration kinetics of Pb-free solder bump interconnects have been studied using a single bump parameter sweep technique. By removing bump to bump variations in structure, texture, and composition, the single bump sweep technique has provided both activation energy and power exponents that reflect atomic migration and interface reactions with fewer samples, shorter stress time, and better statistics than standard failure testing procedures. Contact metallurgies based on Cu and Ni have been studied. Critical current, which corresponds to the Blech limit, was found to exist in the Ni metallurgy, but not in the Cu metallurgy. A temperature dependence of critical current was also observed.

  10. Roles of service parameters on the mechanical behavior of lead-free solder joints

    NASA Astrophysics Data System (ADS)

    Rhee, Hongjoo

    2005-07-01

    Lead-based solders have been extensively used as interconnects in various electronic applications due to their low cost and suitable material properties. However, in view of environmental and health concerns, the electronics industry is forced to develop lead-free alternative solders. Eutectic Sn-3.5Ag based solders are being considered as suitable substitutes due to their non-toxicity, tolerable melting temperatures, and comparable mechanical as well as electrical properties. Smaller electronic packaging and emerging new technologies impose several constraints on the solder interconnect that require better inherent properties in the solder to resist failure during operation. Hence, it is important to develop a clear understanding of the deformation behavior of eutectic Sn-Ag solder joints. Mechanical characterization was performed to investigate the behavior of eutectic Sn-Ag solder joints. Peak shear stress and flow stress decreased with increasing testing temperature and with decreasing simple shear-strain rate. The effect of simple shear-strain rate on the peak shear stress was found to be more significant at temperature regimes less than 125°C. The deformation structure of specimens deformed at higher temperatures was dominated by grain boundary deformation, while at lower temperatures it was dominated by shear banding. Stress relaxation studies on eutectic Sn-Ag solder joints were carried out to provide a better understanding of various parameters contributing to thermomechanical damage accumulation. Monotonic stress relaxation tests at various pre-strain conditions and testing temperatures can provide information relevant to the effects of ramp rates during heating and cooling excursions experienced during thermomechanical fatigue. Peak shear stress and residual shear stress, resulting from stress relaxation period, decreased with increasing testing temperature for a given pre-strain condition. A faster ramp rate was found to cause higher resultant residual

  11. Laser Assisted Soldering: Effects of Hydration on Solder-Tissue Adhesion

    SciTech Connect

    Chan, E.K.; Welch, A.J.; Brown, D.T.; Kovach, I.S.

    1998-10-01

    Wound stabilization is critical in early wound healing. Other than superficial skin wounds, most tissue repair is exposed to a hydrated environment postoperatively. To simulate the stability of laser-soldered tissue in a wet environment, we studied the effects of hydration on laser soldered rat dermis and baboon articular cartilage. In this {ital in vitro} study, we used a solder composed of human serum albumin, sodium hyaluronate, and Indocyanine Green. A 2 {mu}L solder droplet was deposited on each tissue specimen and then the solder was irradiated with a scanning laser beam (808 nm and 27thinspW/cm{sup 2}). After photocoagulation, each tissue specimen was cut into two halves dividing the solder. One half was reserved as control while the other half was soaked in saline for a designated period before fixation (1 h, 1, 2, and 7 days). All tissue specimens were prepared for scanning electron microscopy (SEM). SEM examinations revealed nonuniform coagulation across the solder thickness for most of the specimens, likely a result of the temperature gradient generated by laser heating. Closer to the laser beam, the uppermost region of the solder formed a dense coagulum. The solder aggregated into small globules in the region anterior to the solder-tissue interface. All cartilage specimens soaked in saline suffered coagulum detachment from tissue surface. We noted a high concentration of the protein globules in the detached coagulum. These globules were likely responsible for solder detachment from the cartilage surface. Solder adhered better to the dermis than to cartilage. The dermal layer of the skin, composed of collagen matrix, provided a better entrapment of the solder than the smooth surface of articular cartilage. Insufficient laser heating of solder formed protein globules. Unstable solder-tissue fusion was likely a result of these globules being detached from tissue substrate when the specimen was submerged in a hydrated environment. The solder-tissue bonding

  12. Mechanical and thermomechanical stability issues of 96.5SN-3.5AG solder joints in microelectronic packages

    NASA Astrophysics Data System (ADS)

    Yang, Hong

    Flip chip technology is the ultimate solution for high performance and high density chip level interconnection. This thesis describes the investigation of using eutectic 96.5Sn-3.5Ag solder for flip chip applications. The principal components of the research include mechanical characterization, bumping process development, and finite element simulation for solder joint reliability. A novel solder bumping process was developed for wafer level fabrication of 96.5Sn-3.5Ag solder bumps. As a baseline process, an electroplating method was applied to fabricate the micro-scale solder bumps with 125-mum diameter, 250-mum pitch and approximately 80-mum height. Pre-deposition of solder bumps was carried out by electroplating over a fine-pattern photoresist mask. Rapid dissolution of Ag into Sn was accomplished during reflow and chip joining process. Nickel was selected as the diffusion barrier and wetting layer in the under-the-bump metallurgy (UBM). Microstructural and compositional analyses were performed using SEM and EDS. Three different mechanical testing techniques including tensile creep, lap shear creep, and automated ball indentation tests were used to characterize the mechanical deformation behavior of 96.5Sn-3.5Ag solder and solder joints. Constant-load creep tests on bulk specimens revealed a dislocation climb mechanism with a relatively large stress exponent of n = 10 for creep strain rates ranging from 10sp{-9} to 10sp{-3} and at temperatures ranging from 298K to 453K. The apparent activation energy for creep was found to be 0.57 ev. Lap shear creep tests on 96.5Sn-7.5Ag solder bumps also revealed a dislocation climb mechanism with a stress exponent of n = 10 for creep strain rates ranging from 10sp{-7} to 10sp{-4} at room temperature. In general, the solder joints are more creep resistant than the bulk specimen due to the inclusion of solder/base metal intermetallics. The intermetallic compounds may form precipitates or dispersoids in the solder matrix and

  13. Organic solderability preservation evaluation. Topical report

    SciTech Connect

    Becka, G.A.; McHenry, M.R.; Slanina, J.T.

    1997-03-01

    An evaluation was conducted to determine the possible replacement of the hot air solder leveling (HASL) process used in the Allied Signal Federal Manufacturing & Technologies (FM&T) Printed Wiring Board Facility with an organic solderability preservative (OSP). The drivers for replacing HASL include (1) Eliminating lead from PWB fabrication processes; (2) Potential legislation restricting use of lead, (3) Less expensive processing utilizing OSP rather than HASL processing; (4) Avoiding solder dross disposal inherent with HASL processing, (5) OSP provides flat, planar surface required for surface mount technology product, and (6) Trend to thinner PWB designs. A reduction in the cost of nonconformance (CONC) due to HASL defects (exposed copper, solderability, dewetting and non-wetting) would be realized with the incorporation of the OSP process. Several supplier HASL replacement candidates were initially evaluated. One supplier chemistry was chosen for potential use in the FM&T PWB and assembly areas.

  14. Shrink-Fit Solderable Inserts Seal Hermetically

    NASA Technical Reports Server (NTRS)

    Croucher, William C.

    1992-01-01

    Shrink-fit stainless-steel insert in aluminum equipment housing allows electrical connectors to be replaced by soldering, without degrading hermeticity of housing or connector. Welding could destroy electrostatic-sensitive components and harm housing and internal cables. Steel insert avoids problems because connector soldered directly to it rather than welded to housing. Seals between flange and housing, and between connector and flange resistant to leaks, even after mechanical overloading and thermal shocking.

  15. Microstructural influences on the mechanical properties of solder

    SciTech Connect

    Morris, J.W. Jr.; Goldstein, J.L.F.; Mei, Z.

    1993-04-01

    Intent of this book is to review analytic methods for predicting behavior of solder joints, based on continuum mechanics. The solder is treated as a continuous, homogeneous body, or composite of such bodies, whose mechanical behavior is uniform and governed by simple constitutive equations. The microstructure of a solder joint influences its mechanical properties in 3 ways: it governs deformation and failure; common solders deform inhomogeneously; and common solders are microstructurally unstable. The variety of microstructures often found in solder joints are briefly reviewed, and some of the ways are discussed in which the microstructure influences the common types of high-temperature mechanical behavior. 25 figs, 40 refs.

  16. Sensitivity of Solder Joint Fatigue to Sources of Variation in Advanced Vehicular Power Electronics Cooling

    SciTech Connect

    Vlahinos, A.; O'Keefe, M.

    2010-06-01

    This paper demonstrates a methodology for taking variation into account in thermal and fatigue analyses of the die attach for an inverter of an electric traction drive vehicle. This method can be used to understand how variation and mission profile affect parameters of interest in a design. Three parameters are varied to represent manufacturing, material, and loading variation: solder joint voiding, aluminum nitride substrate thermal conductivity, and heat generation at the integrated gate bipolar transistor. The influence of these parameters on temperature and solder fatigue life is presented. The heat generation loading variation shows the largest influence on the results for the assumptions used in this problem setup.

  17. Soldering Technology. Proceedings of Annual Seminar (8th) Held on 22-23 February 1984

    DTIC Science & Technology

    1984-02-01

    new MIL-STD-883C with water white rosin flux. The internal system within TI is policed by a corrective action loop that was formalized after the...EFFECTEVENESS OF THE TI SYSTEM : rhe cost sivings associated with a reject rate at the solder 2aohioe of 4 parts per 10,000 can only be compared to what it...system does not seem to be a large cause of solderability problems with components other than integrated circuits. The internal documentation system

  18. A systems approach to solder joint fatigue in spacecraft electronic packaging

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.

    1991-01-01

    Differential expansion induced fatigue resulting from temperature cycling is a leading cause of solder joint failures in spacecraft. Achieving high reliability flight hardware requires that each element of the fatigue issue be addressed carefully. This includes defining the complete thermal-cycle environment to be experienced by the hardware, developing electronic packaging concepts that are consistent with the defined environments, and validating the completed designs with a thorough qualification and acceptance test program. This paper describes a useful systems approach to solder fatigue based principally on the fundamental log-strain versus log-cycles-to-failure behavior of fatigue. This fundamental behavior has been useful to integrate diverse ground test and flight operational thermal-cycle environments into a unified electronics design approach. Each element of the approach reflects both the mechanism physics that control solder fatigue, as well as the practical realities of the hardware build, test, delivery, and application cycle.

  19. Use of organic solderability preservatives on solderability retention of copper after accelerated aging

    SciTech Connect

    Hernandez, C.L.; Sorensen, N.R.; Lucero, S.J.

    1997-02-01

    Organic solderability preservatives (OSP`s) have been used by the electronics industry for some time to maintain the solderability of circuit boards and components. Since solderability affects both manufacturing efficiency and product reliability, there is significant interest in maintaining good solder wettability. There is often a considerable time interval between the initial fabrication of a circuit board or component and its use at the assembly level. Parts are often stored under a variety of conditions, in many cases not well controlled. Solder wettability can deteriorate during storage, especially in harsh environments. This paper describes the ongoing efforts at Sandia National Laboratories to quantify solder watability on bare and aged copper surfaces. Benzotriazole and imidazole were applied to electronic grade copper to retard aging effects on solderability. The coupons were introduced into Sandia`s Facility for Atmospheric Corrosion Testing (FACT) to simulate aging in a typical indoor industrial environment. H{sub 2}S, NO{sub 2} and Cl{sub 2} mixed gas was introduced into the test cell and maintained at 35{degrees}C and 70% relative humidity for test periods of one day to two weeks. The OSP`s generally performed better than bare Cu, although solderability diminished with increasing exposure times.

  20. Corrosion resistance of the soldering joint of post-soldering of palladium-based metal-ceramic alloys.

    PubMed

    Kawada, E; Sakurai, Y; Oda, Y

    1997-05-01

    To evaluate the corrosion resistance of post soldering of metal-ceramic alloys, four commercially available palladium-system metal-ceramic alloys (Pd-Cu, Pd-Ni, Pd-Ag, and Pd-Sb systems) and two types of solder (12 k gold solder and 16 k gold solder) with different compositions and melting points were used. The corrosion resistance of the soldered joint was evaluated by anodic polarization. The electrochemical characteristics of soldered surface were measured using electrochemical equipment. Declines in corrosion resistance were not detectable with Pd-Cu, Pd-Ag and Pd-Sb types, but break down at low potential occurred with Pd-Ni type.

  1. Polymer Gelatin Waveguide In Conjuction With Integrated Holographic Optical Elements On GaAs, LiNb03, Glass, And Aluminum Substrates For Optical Interconnects, Signal Processing, And Computing

    NASA Astrophysics Data System (ADS)

    Chen, Ray T.

    1990-02-01

    We have observed waveguiding in thin films of polymer gelatin on GaAs, LiNb03, glass and aluminum substrates. A graded index profile can be induced in the gelatin layer and tuned by wet processing. This makes it possible to form waveguides on any smooth surface. Locally sensitizing the gelatin waveguide with ammonium dichromate allows us to integrate single and multiplexed gratings on the same substrate to perform various functions for optical interconnects and signal processing. A waveguide grating coupler that converts free space TEM00 laser light to a two dimensional spherical guided wave with 50° angle of divergence has also demonstrated. A passive broadcasting network can be formed using this new technology. Further plausible applications such as WD(D)M local area network, optical interconnection, and optical computing are also presented.

  2. Micro-fluidic interconnect

    DOEpatents

    Okandan, Murat; Galambos, Paul C.; Benavides, Gilbert L.; Hetherington, Dale L.

    2006-02-28

    An apparatus for simultaneously aligning and interconnecting microfluidic ports is presented. Such interconnections are required to utilize microfluidic devices fabricated in Micro-Electromechanical-Systems (MEMS) technologies, that have multiple fluidic access ports (e.g. 100 micron diameter) within a small footprint, (e.g. 3 mm.times.6 mm). Fanout of the small ports of a microfluidic device to a larger diameter (e.g. 500 microns) facilitates packaging and interconnection of the microfluidic device to printed wiring boards, electronics packages, fluidic manifolds etc.

  3. Electronic interconnects and devices with topological surface states and methods for fabricating same

    DOEpatents

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2017-04-04

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

  4. Electronic interconnects and devices with topological surface states and methods for fabricating same

    SciTech Connect

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2016-05-03

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

  5. Thermomechanical fatigue life prediction for several solders

    NASA Astrophysics Data System (ADS)

    Wen, Shengmin

    Since solder connections operate at high homologous temperature, solders are high temperature materials. This feature makes their mechanical behavior and fatigue phenomena unique. Based on experimental findings, a physical damage mechanism is introduced for solders. The mechanism views the damage process as a series of independent local damage events characterized by the failure of individual grains, while the structural damage is the eventual percolation result of such local events. Fine's dislocation energy density concept and Mura's microcrack initiation theory are adopted to derive the fatigue formula for an individual grain. A physical damage metric is introduced to describe the material with damage. A unified creep and plasticity constitutive model is adopted to simulate the mechanical behavior of solders. The model is cast into a continuum damage mechanics framework to simulate material with damage. The model gives good agreement with the experimental results of 96.5Pb-3.5Sn and 96.5Sn-3.5Ag solders under uniaxial strain-controlled cyclic loading. The model is convenient for implementation into commercial computational packages. Also presented is a fatigue theory with its failure criterion for solders based on physical damage mechanism. By introducing grain orientation into the fatigue formula, an m-N curve (m is Schmid factor) at constant loading condition is suggested for fatigue of grains with different orientations. A solder structure is defined as fatigued when the damage metric reaches a critical threshold, since at this threshold the failed grains may form a cluster and percolate through the structure according to percolation theory. Fatigue data of 96.5Pb-3.5Sn solder bulk specimens under various uniaxial tension tests were analyzed. Results show that the theory gives consistent predictions under broad conditions, while inelastic strain theory does not. The theory is anisotropic with no size limitation to its application, which could be suitable for

  6. Age-aware solder performance models : level 2 milestone completion.

    SciTech Connect

    Neilsen, Michael K.; Vianco, Paul Thomas; Neidigk, Matthew Aaron; Holm, Elizabeth Ann

    2010-09-01

    Legislated requirements and industry standards are replacing eutectic lead-tin (Pb-Sn) solders with lead-free (Pb-free) solders in future component designs and in replacements and retrofits. Since Pb-free solders have not yet seen service for long periods, their long-term behavior is poorly characterized. Because understanding the reliability of Pb-free solders is critical to supporting the next generation of circuit board designs, it is imperative that we develop, validate and exercise a solder lifetime model that can capture the thermomechanical response of Pb-free solder joints in stockpile components. To this end, an ASC Level 2 milestone was identified for fiscal year 2010: Milestone 3605: Utilize experimentally validated constitutive model for lead-free solder to simulate aging and reliability of solder joints in stockpile components. This report documents the completion of this milestone, including evidence that the milestone completion criteria were met and a summary of the milestone Program Review.

  7. Immortality of Cu damascene interconnects

    NASA Astrophysics Data System (ADS)

    Hau-Riege, Stefan P.

    2002-04-01

    We have studied short-line effects in fully-integrated Cu damascene interconnects through electromigration experiments on lines of various lengths and embedded in different dielectric materials. We compare these results with results from analogous experiments on subtractively-etched Al-based interconnects. It is known that Al-based interconnects exhibit three different behaviors, depending on the magnitude of the product of current density, j, and line length, L: For small values of (jL), no void nucleation occurs, and the line is immortal. For intermediate values, voids nucleate, but the line does not fail because the current can flow through the higher-resistivity refractory-metal-based shunt layers. Here, the resistance of the line increases but eventually saturates, and the relative resistance increase is proportional to (jL/B), where B is the effective elastic modulus of the metallization system. For large values of (jL/B), voiding leads to an unacceptably high resistance increase, and the line is considered failed. By contrast, we observed only two regimes for Cu-based interconnects: Either the resistance of the line stays constant during the duration of the experiment, and the line is considered immortal, or the line fails due to an abrupt open-circuit failure. The absence of an intermediate regime in which the resistance saturates is due to the absence of a shunt layer that is able to support a large amount of current once voiding occurs. Since voids nucleate much more easily in Cu- than in Al-based interconnects, a small fraction of short Cu lines fails even at low current densities. It is therefore more appropriate to consider the probability of immortality in the case of Cu rather than assuming a sharp boundary between mortality and immortality. The probability of immortality decreases with increasing amount of material depleted from the cathode, which is proportional to (jL2/B) at steady state. By contrast, the immortality of Al-based interconnects is

  8. Computer simulation of solder joint failure

    SciTech Connect

    Burchett, S.N.; Frear, D.R.; Rashid, M.M.

    1997-04-01

    The thermomechanical fatigue failure of solder joints is increasingly becoming an important reliability issue for electronic packages. The purpose of this Laboratory Directed Research and Development (LDRD) project was to develop computational tools for simulating the behavior of solder joints under strain and temperature cycling, taking into account the microstructural heterogeneities that exist in as-solidified near eutectic Sn-Pb joints, as well as subsequent microstructural evolution. The authors present two computational constitutive models, a two-phase model and a single-phase model, that were developed to predict the behavior of near eutectic Sn-Pb solder joints under fatigue conditions. Unique metallurgical tests provide the fundamental input for the constitutive relations. The two-phase model mathematically predicts the heterogeneous coarsening behavior of near eutectic Sn-Pb solder. The finite element simulations with this model agree qualitatively with experimental thermomechanical fatigue tests. The simulations show that the presence of an initial heterogeneity in the solder microstructure could significantly degrade the fatigue lifetime. The single-phase model was developed to predict solder joint behavior using materials data for constitutive relation constants that could be determined through straightforward metallurgical experiments. Special thermomechanical fatigue tests were developed to give fundamental materials input to the models, and an in situ SEM thermomechanical fatigue test system was developed to characterize microstructural evolution and the mechanical behavior of solder joints during the test. A shear/torsion test sample was developed to impose strain in two different orientations. Materials constants were derived from these tests. The simulation results from the two-phase model showed good fit to the experimental test results.

  9. Zee electrical interconnect

    NASA Technical Reports Server (NTRS)

    Rust, Thomas M. (Inventor); Gaddy, Edward M. (Inventor); Herriage, Michael J. (Inventor); Patterson, Robert E. (Inventor); Partin, Richard D. (Inventor)

    2001-01-01

    An interconnect, having some length, that reliably connects two conductors separated by the length of the interconnect when the connection is made but in which one length if unstressed would change relative to the other in operation. The interconnect comprises a base element an intermediate element and a top element. Each element is rectangular and formed of a conducting material and has opposed ends. The elements are arranged in a generally Z-shape with the base element having one end adapted to be connected to one conductor. The top element has one end adapted to be connected to another conductor and the intermediate element has its ends disposed against the other end of the base and the top element. Brazes mechanically and electrically interconnect the intermediate element to the base and the top elements proximate the corresponding ends of the elements. When the respective ends of the base and the top elements are connected to the conductors, an electrical connection is formed therebetween, and when the conductors are relatively moved or the interconnect elements change length the elements accommodate the changes and the associated compression and tension forces in such a way that the interconnect does not mechanically fatigue.

  10. Dynamic Response of Soldered Electronic Components under Impact Loading

    DTIC Science & Technology

    2011-12-01

    2   2.   Varying Strain Rates and Solder Joint Failure .................................3   3.   Drop Impact Analysis on Sn - Ag -Cu...absence of significant internal grain rotation, and that it consistent at all strain-rates. 4 3. Drop Impact Analysis on Sn - Ag -Cu Solder Joints...Pang and Che [4] discuss the complexities of drop test analysis and the dangers of over simplifying Sn - Ag -Cu solder joint deformation response. Solder

  11. Testing of printed circuit board solder joints by optical correlation

    NASA Technical Reports Server (NTRS)

    Espy, P. N.

    1975-01-01

    An optical correlation technique for the nondestructive evaluation of printed circuit board solder joints was evaluated. Reliable indications of induced stress levels in solder joint lead wires are achievable. Definite relations between the inherent strength of a solder joint, with its associated ability to survive stress, are demonstrable.

  12. Microstructural evolution of eutectic Au-Sn solder joints

    SciTech Connect

    Song, Ho Geon

    2002-05-01

    Current trends toward miniaturization and the use of lead(Pb)-free solder in electronic packaging present new problems in the reliability of solder joints. This study was performed in order to understand the microstructure and microstructural evolution of small volumes of nominally eutectic Au-Sn solder joints (80Au-20Sn by weight), which gives insight into properties and reliability.

  13. Efforts to Develop a 300°C Solder

    SciTech Connect

    Norann, Randy A

    2015-01-25

    This paper covers the efforts made to find a 300°C electrical solder solution for geothermal well monitoring and logging tools by Perma Works LLC. This paper covers: why a high temperature solder is needed, what makes for a good solder, testing flux, testing conductive epoxy and testing intermetallic bonds. Future areas of research are suggested.

  14. Fluxless laser soldering for electronic packaging

    SciTech Connect

    Hosking, F.M.; Keicher, D.M.

    1991-12-31

    Conventional soldering typically requires the use of reactive fluxes to promote wetting. The resulting flux residues are removed primarily with halogenated or chlorofluorocarbon (CFC) solvents. With the mandated phaseout of CFCs by the year 2000, there has been a concentrated effort to develop alternative, environmentally compatible manufacturing and cleaning technologies that will satisfy the restrictions placed on CFCs, but still yield high quality product. Sandia National Laboratories is currently evaluating a variety of alternative fluxless soldering technologies which can be applied to electronic packaging. Laser soldering in a controlled atmosphere has shown great potential as an environmentally compatible process. The effects of laser heating with a 100 watt CW Nd:YAG laser, joint design, and base/filler metal reactions on achieving fluxless wetting with good metallurgical bonds were examined. Satisfactory Ni-Au plated Kovar{reg_sign} solder joints were made with 80In-15Pb-5Ag and 63Sn-37Pb (wt. %) solder alloys in a slightly reducing cover gas. Wetting generally increased with increasing laser power, decreasing laser beam spot size, and decreasing part travel speed. The materials and processing interaction effects are identified and discussed.

  15. Environmental toxicology: Interconnections between human ...

    EPA Pesticide Factsheets

    This presentation will discuss what has made a career in environmental toxicology rewarding, environmental and scientific challenges for the 21st century, paradigm shift in regulatory toxicology, adverse outcome framework, interconnections between human health and ecological integrity, SOT-SETAC Pellston Workshop findings, concepts for systems thinking in environmental toxicology The Eminent Toxicologist Lectures are historically relevant, high-quality presentations appropriate for senior undergraduate students, graduate students, or the scientifically oriented general public. This series of lectures is produced by the SOT Undergraduate Subcommittee of the Education Committee in conjunction with the Eminent Toxicologist Working Group.

  16. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1989-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  17. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1987-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  18. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-06-24

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  19. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1989-03-21

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration. 6 figs.

  20. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-08-23

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  1. A novel method for direct solder bump pull testing using lead-free solders

    NASA Astrophysics Data System (ADS)

    Turner, Gregory Alan

    This thesis focuses on the design, fabrication, and evaluation of a new method for testing the adhesion strength of lead-free solders, named the Isotraction Bump Pull method (IBP). In order to develop a direct solder joint-strength testing method that did not require customization for different solder types, bump sizes, specific equipment, or trial-and-error, a combination of two widely used and accepted standards was created. First, solder bumps were made from three types of lead free solder were generated on untreated copper PCB substrates using an in-house fabricated solder bump-on-demand generator, Following this, the newly developed method made use of a polymer epoxy to encapsulate the solder bumps that could then be tested under tension using a high precision universal vertical load machine. The tests produced repeatable and predictable results for each of the three alloys tested that were in agreement with the relative behavior of the same alloys using other testing methods in the literature. The median peak stress at failure for the three solders tested were 2020.52 psi, 940.57 psi, and 2781.0 psi, and were within one standard deviation of the of all data collected for each solder. The assumptions in this work that brittle fracture occurred through the Intermetallic Compound layer (IMC) were validated with the use of Energy-Dispersive X-Ray Spectrometry and high magnification of the fractured surface of both newly exposed sides of the test specimens. Following this, an examination of the process to apply the results from the tensile tests into standard material science equations for the fracture of the systems was performed..

  2. Voiding in lead-free soldering of components with large solder pads

    NASA Astrophysics Data System (ADS)

    Dziurdzia, Barbara; Mikołajek, Janusz

    2016-12-01

    The paper presents the quantification of void formation in lead-free solder joints underneath bottom terminated components (BTCs) through X-ray inspection. Experiments were designed to investigate how void formation is affected by using vacuum in reflow soldering on the example of light emitted diode (LED) packages on metal core printed circuit boards (PCBs). Convection and vapour phase reflow soldering were used for LED assembly. X-ray inspection system analyzed the statistical distribution, mean value, standard deviation and process capability value Cpk of thermal pads coverage for various technological versions of LEDs.

  3. SOFC INTERCONNECT DEVELOPMENT

    SciTech Connect

    Diane M. England

    2004-03-16

    An interconnect for an SOFC stack is used to connect fuel cells into a stack. SOFC stacks are expected to run for 40,000 hours and 10 thermal cycles for the stationary application and 10,000 hours and 7000 thermal cycles for the transportation application. The interconnect of a stack must be economical and robust enough to survive the SOFC stack operation temperature of 750 C and must maintain the electrical connection to the fuel cells throughout the lifetime and under thermal cycling conditions. Ferritic and austenitic stainless steels, and nickel-based superalloys were investigated as possible interconnect materials for solid oxide fuel cell (SOFC) stacks. The alloys were thermally cycled in air and in a wet nitrogen-argon-hydrogen (N2-Ar-H2-H2O) atmosphere. Thermogravimetry was used to determine the parabolic oxidation rate constants of the alloys in both atmospheres. The area-specific resistance of the oxide scale and metal substrates were measured using a two-probe technique with platinum contacts. The study identifies two new interconnect designs which can be used with both bonded and compressive stack sealing mechanisms. The new interconnect designs offer a solution to chromium vaporization, which can lead to degradation of some (chromium-sensitive) SOFC cathodes.

  4. Nanocopper Based Solder-Free Electronic Assembly

    NASA Astrophysics Data System (ADS)

    Schnabl, K.; Wentlent, L.; Mootoo, K.; Khasawneh, S.; Zinn, A. A.; Beddow, J.; Hauptfleisch, E.; Blass, D.; Borgesen, P.

    2014-12-01

    CuantumFuse nano copper material has been used to assemble functional LED test boards and a small camera board with a 48 pad CMOS sensor quad-flat no-lead chip and a 10 in flexible electronics demo. Drop-in replacement of solder, by use of stencil printing and standard surface mount technology equipment, has been demonstrated. Applications in space and commercial systems are currently under consideration. The stable copper-nanoparticle paste has been examined and characterized by scanning electron microscopy and high-resolution transmission electron microscopy; this has shown that the joints are nanocrystalline but with substantial porosity. Assessment of reliability is expected to be complicated by this and by the effects of thermal and strain-enhanced coarsening of pores. Strength, creep, and fatigue properties were measured and results are discussed with reference to our understanding of solder reliability to assess the potential of this nano-copper based solder alternative.

  5. Solder Joint Health Monitoring Testbed System

    NASA Technical Reports Server (NTRS)

    Delaney, Michael M.

    2009-01-01

    The density and pin count for Field Programmable Gate Arrays (FPGAs) has been increasing, and has exceeded current methods of solder joint inspection, making early detection of failures more problematic. These failures are a concern for both flight safety and maintenance in commercial aviation. Ridgetop Group, Inc. has developed a method for detecting solder joint failures in real time. The NASA Dryden Flight Research Center is developing a set of boards to test this method in ground environmental and accelerated testing as well as flight test on a Dryden F-15 or F-18 research aircraft. In addition to detecting intermittent and total solder joint failures, environmental data on the boards, such as temperature and vibration, will be collected and time-correlated to aircraft state data. This paper details the technical approach involved in the detection process, and describes the design process and products to date for Dryden s FPGA failure detection boards.

  6. Scalable IP switching based on optical interconnect

    NASA Astrophysics Data System (ADS)

    Luo, Zhixiang; Cao, Mingcui; Liu, Erwu

    2000-10-01

    IP traffic on the Internet and enterprise networks has been growing exponentially in the last several years, and much attention is being focused on the use of IP multicast for real-time multimedia applications. The current soft and general-purpose CPU-based routers face great stress since they have great latency and low forwarding speeds. Based on the ASICs, layer 2 switching provides high-speed packet forwarding. Integrating high-speed of Layer 2 switching with the flexibility of Layer 3 routing, Layer 3 switching (IP switching) has been put forward in order to avoid the performance bottleneck associated with Layer 3 forwarding. In this paper, we present a prototype system of a scalable IP switching based on scalable ATM switching fabric and optical interconnect. The IP switching system mainly consists of the input/output interface unit, scalable ATM switching fabric and IP control component. Optical interconnects between the input fan-out stage and the interconnect stage, also the interconnect stage and the output concentration stage provide high-speed data paths. And the interconnect stage is composed of 16 X 16 CMOS-SEED ATM switching modules. With 64 ports of OC-12 interface, the maximum throughput of the prototype system is about 20 million packets per second (MPPS) for 256 bytes average packet length, and the packet loss ratio is less than 10e-9. Benefiting from the scalable architecture and the optical interconnect, this IP switching system can easily scale to very large network size.

  7. Application of optical interconnect technology at Lawrence Livermore National Laboratory

    SciTech Connect

    Haigh, R.E.; Lowry, M.E.; McCammon, K.; Hills, R.; Mitchell, R.; Sweider, D.

    1995-08-10

    Optical interconnects will be required to meet the information bandwidth requirements of future communication and computing applications. At Lawrence Livermore National Laboratory, the authors are involved in applying optical interconnect technologies in two distinct application areas: Multi-Gigabit/sec Computer Backplanes and Gigabit/sec Wide Area Networking using Wavelength Division Multiplexing. In this paper, the authors discuss their efforts to integrate optical interconnect technologies into prototype computing and communication systems.

  8. Lead (Pb)-Free Solder Applications

    SciTech Connect

    VIANCO,PAUL T.

    2000-08-15

    Legislative and marketing forces both abroad and in the US are causing the electronics industry to consider the use of Pb-free solders in place of traditional Sn-Pb alloys. Previous case studies have demonstrated the satisfactory manufacturability and reliability of several Pb-free compositions for printed circuit board applications. Those data, together with the results of fundamental studies on Pb-free solder materials, have indicated the general feasibility of their use in the broader range of present-day, electrical and electronic components.

  9. ESD Test Apparatus for Soldering Irons

    NASA Technical Reports Server (NTRS)

    Sancho, Jose; Esser, Robert

    2013-01-01

    ESDA (Electrostatic Discharge Association) ESD STM 13.1-2000 requires frequent testing of the voltage leakage from the tip of a soldering iron and the resistance from the tip of the soldering iron to the common point ground. Without this test apparatus, the process is time-consuming and requires several wires, alligator clips, or test probes, as well as additional equipment. Soldering iron tips must be tested for electrostatic discharge risks frequently, and this typically takes a lot of time in setup and testing. This device enables the operator to execute the full test in one minute or less. This innovation is a simple apparatus that plugs into a digital multimeter (DMM) and the Common Point Ground (CPG) reference. It enables the user to perform two of the electrostatic discharge tests required in ESD STM 13.1-2000. The device consists of a small black box with two prongs sticking out of one end, two inputs on the opposite end (one of the inputs is used to connect the reference CPG to the DMM), and a metal tab on one side. Inside the box are wires, several washers of various materials, and assembly hardware (nuts and screws/bolts). The device is a passive electronic component that is plugged into a DMM. The operator sets the DMM to read voltage. The operator places the heated tip of the soldering iron onto the metal tab with a small amount of solder to ensure a complete connection. The voltage is read and recorded. The operator switches the DMM to read resistance. The operator places the heated tip of the soldering iron onto the metal tab with a small amount of solder to ensure a complete connection. The resistance is recorded. If the recorded voltage and resistance are below a number stated in ESDA ESD STM 13.1-2000, the test is considered to pass. The device includes all the necessary wiring internal to its body so the operator does not need to do any independent wiring, except for grounding. It uses a stack of high-thermal-resistance washers to minimize the

  10. Microwave Tissue Soldering for Immediate Wound Closure

    NASA Technical Reports Server (NTRS)

    Arndt, G. Dickey; Ngo, Phong H.; Plan, Chau T.; Byerly, Diane; Dusl, John; Sognier, Marguerite A.

    2011-01-01

    A novel approach for the immediate sealing of traumatic wounds is under development. A portable microwave generator and handheld antenna are used to seal wounds, binding the edges of the wound together using a biodegradable protein sealant or solder. This method could be used for repairing wounds in emergency settings, by restoring the wound surface to its original strength within minutes. This technique could also be utilized for surgical purposes involving solid visceral organs (i.e., liver, spleen, and kidney) that currently do not respond well to ordinary surgical procedures. A miniaturized microwave generator and a handheld antenna are used to deliver microwave energy to the protein solder, which is applied to the wound. The antenna can be of several alternative designs optimized for placement either in contact with or proximity to the protein solder covering the wound. In either case, optimization of the design includes the matching of impedances to maximize the energy delivered to the protein solder and wound at a chosen frequency. For certain applications, an antenna could be designed that would emit power only when it is in direct contact with the wound. The optimum frequency or frequencies for a specific application would depend on the required depth of penetration of the microwave energy. In fact, a computational simulation for each specific application could be performed, which would then match the characteristics of the antenna with the protein solder and tissue to best effect wound closure. An additional area of interest with potential benefit that remains to be validated is whether microwave energy can effectively kill bacteria in and around the wound. Thus, this may be an efficient method for simultaneously sterilizing and closing wounds. Using microwave energy to seal wounds has a number of advantages over lasers, which are currently in experimental use in some hospitals. Laser tissue welding is unsuitable for emergency use because its large, bulky

  11. Reliability issues in Pb-free solder joint miniaturization

    NASA Astrophysics Data System (ADS)

    Huang, Zhiheng; Conway, Paul P.; Jung, Erik; Thomson, Rachel C.; Liu, Changqing; Loeher, Thomas; Minkus, Mathias

    2006-09-01

    As solder joints become increasingly miniaturized to meet the severe demands of future electronic packaging, it is vitally important to consider whether the solder joint size and geometry could become reliability issues and thereby affect implementation of the Pb-free solders. In this study, three bumping techniques, i.e., solder dipping, stencil printing followed by solder reflow, and electroplating of solders with subsequent reflow, were used to investigate the interfacial interactions of molten Sn-3.5Ag, Sn-3.8Ag-0.7Cu, and pure Sn solders on a copper pad at 240°C. The resultant interfacial microstructures, coming from a variety of Cu pads, with sizes ranging from 1 mm to 25 µm, and representing different solder bump geometries, have been investigated. In addition, a two-dimensional thermodynamic/kinetic model has been developed to assist the understanding of the kinetics of interdiffusion and the formation of interfacial intermetallic compounds. Experimental results and theoretical predictions both suggest that the solder bump size and geometry can influence the as-soldered microstructure; therefore, this factor should be taken into consideration for the design of future reliable ultrafine Pb-free solder joints.

  12. SOFC INTERCONNECT DEVELOPMENT

    SciTech Connect

    Diane M. England

    2003-06-06

    This report summarizes the interconnect work being performed at Delphi. Materials were chosen for this interconnect project were chosen from ferritic and austenitic stainless steels, and nickel-based superalloys. The alloys are thermally cycled in air and a wet hydrogen atmosphere. The oxide scale adherence, electrical resistance and oxidation resistance are determined after long-term oxidation of each alloy. The oxide scale adherence will be observed using a scanning electron microscope. The electrical resistance of the oxidized alloys will be determined using an electrical resistance measurement apparatus which has been designed and is currently being built. Data from the electrical resistance measurement is expected to be provided in the second quarter.

  13. Solder for oxide layer-building metals and alloys

    DOEpatents

    Kronberg, J.W.

    1992-09-15

    A low temperature solder and method for soldering an oxide layer-building metal such as aluminum, titanium, tantalum or stainless steel is disclosed. The composition comprises tin and zinc; germanium as a wetting agent; preferably small amounts of copper and antimony; and a grit, such as silicon carbide. The grit abrades any oxide layer formed on the surface of the metal as the germanium penetrates beneath and loosens the oxide layer to provide good metal-to-metal contact. The germanium comprises less than approximately 10% by weight of the solder composition so that it provides sufficient wetting action but does not result in a melting temperature above approximately 300 C. The method comprises the steps rubbing the solder against the metal surface so the grit in the solder abrades the surface while heating the surface until the solder begins to melt and the germanium penetrates the oxide layer, then brushing aside any oxide layer loosened by the solder.

  14. Solder for oxide layer-building metals and alloys

    DOEpatents

    Kronberg, James W.

    1992-01-01

    A low temperature solder and method for soldering an oxide layer-building metal such as aluminum, titanium, tantalum or stainless steel. The comosition comprises tin and zinc; germanium as a wetting agent; preferably small amounts of copper and antimony; and a grit, such as silicon carbide. The grit abrades any oxide layer formed on the surface of the metal as the germanium penetrates beneath and loosens the oxide layer to provide good metal-to-metal contact. The germanium comprises less than aproximatley 10% by weight of the solder composition so that it provides sufficient wetting action but does not result in a melting temperature above approximately 300.degree. C. The method comprises the steps rubbing the solder against the metal surface so the grit in the solder abrades the surface while heating the surface until the solder begins to melt and the germanium penetrates the oxide layer, then brushing aside any oxide layer loosened by the solder.

  15. Novel Three-Dimensional Vertical Interconnect Technology for Microwave and RF Applications

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.

    1999-01-01

    In this paper, novel 3D interconnects suitable for applications in microwave and RF integrated circuit technology have been presented. The interconnect fabrication process and design details are presented. In addition, measured and numerically modeled results of the performance of the interconnects have been shown. The results indicate that the proposed technology has tremendous potential applications in integrated circuit technology. C,

  16. Thermal cycling life prediction of Sn-3.0Ag-0.5Cu solder joint using type-I censored data.

    PubMed

    Mi, Jinhua; Li, Yan-Feng; Yang, Yuan-Jian; Peng, Weiwen; Huang, Hong-Zhong

    2014-01-01

    Because solder joint interconnections are the weaknesses of microelectronic packaging, their reliability has great influence on the reliability of the entire packaging structure. Based on an accelerated life test the reliability assessment and life prediction of lead-free solder joints using Weibull distribution are investigated. The type-I interval censored lifetime data were collected from a thermal cycling test, which was implemented on microelectronic packaging with lead-free ball grid array (BGA) and fine-pitch ball grid array (FBGA) interconnection structures. The number of cycles to failure of lead-free solder joints is predicted by using a modified Engelmaier fatigue life model and a type-I censored data processing method. Then, the Pan model is employed to calculate the acceleration factor of this test. A comparison of life predictions between the proposed method and the ones calculated directly by Matlab and Minitab is conducted to demonstrate the practicability and effectiveness of the proposed method. At last, failure analysis and microstructure evolution of lead-free solders are carried out to provide useful guidance for the regular maintenance, replacement of substructure, and subsequent processing of electronic products.

  17. Thermal Cycling Life Prediction of Sn-3.0Ag-0.5Cu Solder Joint Using Type-I Censored Data

    PubMed Central

    Mi, Jinhua; Yang, Yuan-Jian; Huang, Hong-Zhong

    2014-01-01

    Because solder joint interconnections are the weaknesses of microelectronic packaging, their reliability has great influence on the reliability of the entire packaging structure. Based on an accelerated life test the reliability assessment and life prediction of lead-free solder joints using Weibull distribution are investigated. The type-I interval censored lifetime data were collected from a thermal cycling test, which was implemented on microelectronic packaging with lead-free ball grid array (BGA) and fine-pitch ball grid array (FBGA) interconnection structures. The number of cycles to failure of lead-free solder joints is predicted by using a modified Engelmaier fatigue life model and a type-I censored data processing method. Then, the Pan model is employed to calculate the acceleration factor of this test. A comparison of life predictions between the proposed method and the ones calculated directly by Matlab and Minitab is conducted to demonstrate the practicability and effectiveness of the proposed method. At last, failure analysis and microstructure evolution of lead-free solders are carried out to provide useful guidance for the regular maintenance, replacement of substructure, and subsequent processing of electronic products. PMID:25121138

  18. Quantifying Electromigration Processes in Sn-0.7Cu Solder with Lab-Scale X-Ray Computed Micro-Tomography

    NASA Astrophysics Data System (ADS)

    Mertens, James Charles Edwin

    For decades, microelectronics manufacturing has been concerned with failures related to electromigration phenomena in conductors experiencing high current densities. The influence of interconnect microstructure on device failures related to electromigration in BGA and flip chip solder interconnects has become a significant interest with reduced individual solder interconnect volumes. A survey indicates that x-ray computed micro-tomography (muXCT) is an emerging, novel means for characterizing the microstructures' role in governing electromigration failures. This work details the design and construction of a lab-scale muXCT system to characterize electromigration in the Sn-0.7Cu lead-free solder system by leveraging in situ imaging. In order to enhance the attenuation contrast observed in multi-phase material systems, a modeling approach has been developed to predict settings for the controllable imaging parameters which yield relatively high detection rates over the range of x-ray energies for which maximum attenuation contrast is expected in the polychromatic x-ray imaging system. In order to develop this predictive tool, a model has been constructed for the Bremsstrahlung spectrum of an x-ray tube, and calculations for the detector's efficiency over the relevant range of x-ray energies have been made, and the product of emitted and detected spectra has been used to calculate the effective x-ray imaging spectrum. An approach has also been established for filtering 'zinger' noise in x-ray radiographs, which has proven problematic at high x-ray energies used for solder imaging. The performance of this filter has been compared with a known existing method and the results indicate a significant increase in the accuracy of zinger filtered radiographs. The obtained results indicate the conception of a powerful means for the study of failure causing processes in solder systems used as interconnects in microelectronic packaging devices. These results include the

  19. Interconnecting with VIPs

    ERIC Educational Resources Information Center

    Collins, Robert

    2013-01-01

    Interconnectedness changes lives. It can even save lives. Recently the author got to witness and be part of something in his role as a teacher of primary science that has changed lives: it may even have saved lives. It involved primary science teaching--and the climate. Robert Collins describes how it is all interconnected. The "Toilet…

  20. Capillary interconnect device

    DOEpatents

    Renzi, Ronald F

    2013-11-19

    An interconnecting device for connecting a plurality of first fluid-bearing conduits to a corresponding plurality of second fluid-bearing conduits thereby providing fluid communication between the first fluid-bearing conduits and the second fluid-bearing conduits. The device includes a manifold and one or two ferrule plates that are held by compressive axial forces.

  1. CAISSON: Interconnect Network Simulator

    NASA Technical Reports Server (NTRS)

    Springer, Paul L.

    2006-01-01

    Cray response to HPCS initiative. Model future petaflop computer interconnect. Parallel discrete event simulation techniques for large scale network simulation. Built on WarpIV engine. Run on laptop and Altix 3000. Can be sized up to 1000 simulated nodes per host node. Good parallel scaling characteristics. Flexible: multiple injectors, arbitration strategies, queue iterators, network topologies.

  2. Open Systems Interconnection.

    ERIC Educational Resources Information Center

    Denenberg, Ray

    1985-01-01

    Discusses the need for standards allowing computer-to-computer communication and gives examples of technical issues. The seven-layer framework of the Open Systems Interconnection (OSI) Reference Model is explained and illustrated. Sidebars feature public data networks and Recommendation X.25, OSI standards, OSI layer functions, and a glossary.…

  3. Coplanar interconnection module

    NASA Technical Reports Server (NTRS)

    Steward, R. D.; Windsor, H. F.

    1970-01-01

    Module for interconnecting a semiconductor array to external leads or components incorporates a metal external heat sink for cooling the array. Heat sink, extending down from the molded block that supports the array, is immersed in a liquid nitrogen bath which is designed to maintain the desired array temperature.

  4. Free-electron laser tissue-soldering in vitro with an albumin solder

    NASA Astrophysics Data System (ADS)

    Sorg, Brian S.; Choi, Bernard; McNally-Heintzelman, Karen M.; Jansen, E. Duco; Welch, Ashley J.

    2000-04-01

    The purpose of this study was to explore the feasibility of using a free-electron laser (FEL) to photothermally coagulate an albumin solder for laser-assisted incision closure. A 50%(w/v) bovine serum albumin solder was used to repair an incision in bovine aorta. The solder was coagulated by targeting absorption peaks in the solder infrared absorption spectrum using the FEL. Acute breaking strengths of repaired incisions were measured and the data analyzed by one-way ANOVA (P < 0.05). Multiple comparisons of means were performed using the Newman-Keuls test. The solder absorption spectrum from 2 - 10 microns was similar to water with an additional peak at 6.45 microns (amide II) due to the albumin. Preliminary results indicated that wavelengths at or very close to the absorption peaks were excessively absorbed, resulting in only the top surface of the solder being coagulated. Using wavelengths at points of weak absorption on the water absorption curve yielded better results.

  5. Large data centers interconnect bottlenecks.

    PubMed

    Ghiasi, Ali

    2015-02-09

    Large data centers interconnect bottlenecks are dominated by the switch I/O BW and the front panel BW as a result of pluggable modules. To overcome the front panel BW and the switch ASIC BW limitation one approach is to either move the optics onto the mid-plan or integrate the optics into the switch ASIC. Over the last 4 years, VCSEL based optical engines have been integrated into the packages of large-scale HPC routers, moderate size Ethernet switches, and even FPGA's. Competing solutions based on Silicon Photonics (SiP) have also been proposed for integration into HPC and Ethernet switch packages but with better integration path through the use of TSV (Through Silicon Via) stack dies. Integrating either VCSEL or SiP based optical engines into complex ASIC package that operates at high temperatures, where the required reliability is not trivial, one should ask what is the technical or the economic advantage before embarking on such a complex integration. High density Ethernet switches addressing data centers currently in development are based on 25G NRZ signaling and QSFP28 optical module that can support up to 3.6 Tb of front panel bandwidth.

  6. Prediction of Solder Joint Fatigue Life

    DTIC Science & Technology

    1988-04-01

    strains are in turn used to calculate Nf via a Coffin - Manson LCF curve developed from the tests on simple solder joints. This life is compared to...correlation with a = 0.52 (the Coffin - Manson LCF exponent) has been discussed previously [2]. The slope was determined from a least squares fit with a

  7. Multilead, Vaporization-Cooled Soldering Heat Sink

    NASA Technical Reports Server (NTRS)

    Rice, John

    1995-01-01

    Vaporization-cooled heat sink proposed for use during soldering of multiple electrical leads of packaged electronic devices to circuit boards. Heat sink includes compliant wicks held in grooves on edges of metal fixture. Wicks saturated with water. Prevents excessive increases in temperature at entrances of leads into package.

  8. Damage mechanics characterization on fatigue behavior of a solder joint material

    SciTech Connect

    Chow, C.L.; Yang, F.; Fang, H.E.

    1998-08-01

    This paper presents the first part of a comprehensive mechanics approach capable of predicting the integrity and reliability of solder joint material under fatigue loading without viscoplastic damage considerations. A separate report will be made to present a comprehensive damage model describing life prediction of the solder material under thermomechanical fatigue loading. The method is based on a theory of damage mechanics which makes possible a macroscopic description of the successive material deterioration caused by the presence of microcracks/voids in engineering materials. A damage mechanics model based on the thermodynamic theory of irreversible processes with internal state variables is proposed and used to provide a unified approach in characterizing the cyclic behavior of a typical solder material. With the introduction of a damage effect tensor, the constitutive equations are derived to enable the formulation of a fatigue damage dissipative potential function and a fatigue damage criterion. The fatigue evolution is subsequently developed based on the hypothesis that the overall damage is induced by the accumulation of fatigue and plastic damage. This damage mechanics approach offers a systematic and versatile means that is effective in modeling the entire process of material failure ranging from damage initiation and propagation leading eventually to macro-crack initiation and growth. As the model takes into account the load history effect and the interaction between plasticity damage and fatigue damage, with the aid of a modified general purpose finite element program, the method can readily be applied to estimate the fatigue life of solder joints under different loading conditions.

  9. Cross-border impacts of the restriction of hazardous substances: a perspective based on Japanese solders.

    PubMed

    Fuse, Masaaki; Tsunemi, Kiyotaka

    2013-08-20

    Despite the relevance of the global economy, Regulatory Impact Assessments of the restriction of hazardous substances (RoHS) in the European Union (EU) are based only on domestic impacts. This paper explores the cross-border environmental impacts of the RoHS by focusing on the shifts to lead-free solders in Japan, which exports many electronics to the EU. The regulatory impacts are quantified by integrating a material flow analysis for metals constituting a solder with a scenario analysis with and without the RoHS. The results indicate that the EU regulation, the RoHS, has triggered shifts in Japan to lead-free solders, not only for electronics subject to this regulation, but for other products as well. We also find that the RoHS leads to a slow reduction in environmental emissions of the target, lead, but results in a rapid increase in the use of tin and silver in lead-free solders. This indicates the importance of assessing potential alternative substances, the use of which may increase as a result of adhering to the RoHS. The latter constitutes a negative impact because of recent concerns regarding resource criticality.

  10. A Thermal Model for Carbon Nanotube Interconnects

    PubMed Central

    Mohsin, Kaji Muhammad; Srivastava, Ashok; Sharma, Ashwani K.; Mayberry, Clay

    2013-01-01

    In this work, we have studied Joule heating in carbon nanotube based very large scale integration (VLSI) interconnects and incorporated Joule heating influenced scattering in our previously developed current transport model. The theoretical model explains breakdown in carbon nanotube resistance which limits the current density. We have also studied scattering parameters of carbon nanotube (CNT) interconnects and compared with the earlier work. For 1 µm length single-wall carbon nanotube, 3 dB frequency in S12 parameter reduces to ~120 GHz from 1 THz considering Joule heating. It has been found that bias voltage has little effect on scattering parameters, while length has very strong effect on scattering parameters.

  11. Graphene Nanoribbons (GNRs) for Future Interconnect

    NASA Astrophysics Data System (ADS)

    Saptono Duryat, Rahmat

    2016-05-01

    Selecting and developing materials for the future devices require a sound understanding of design requirements. Miniaturization of electronic devices, as commonly expressed by Moore Law, has involved the integration level. Increase of the level has caused some consequences in the design and selection of materials for interconnection. The present paper deals with the challenge of materials design and selection beyond the nanoscale limit and the ability of traditional materials to cope with. One of the emerging materials, i.e. Graphene, will be reviewed with particular reference to its characteristics and potentials for future interconnection.

  12. Microwave Tissue Soldering for Immediate Wound Closure

    NASA Technical Reports Server (NTRS)

    Arndt, G. Dickey; Ngo, Phong H.; Phan, Chau T.; Byerly, Diane; Dusl, John; Sognier, Marguerite A.; Carl, James

    2011-01-01

    A novel approach for the immediate sealing of traumatic wounds is under development. A portable microwave generator and handheld antenna are used to seal wounds, binding the edges of the wound together using a biodegradable protein sealant or solder. This method could be used for repairing wounds in emergency settings by restoring the wound surface to its original strength within minutes. This technique could also be utilized for surgical purposes involving solid visceral organs (i.e., liver, spleen, and kidney) that currently do not respond well to ordinary surgical procedures. A miniaturized microwave generator and a handheld antenna are used to deliver microwave energy to the protein solder, which is applied to the wound. The antenna can be of several alternative designs optimized for placement either in contact with or in proximity to the protein solder covering the wound. In either case, optimization of the design includes the matching of impedances to maximize the energy delivered to the protein solder and wound at a chosen frequency. For certain applications, an antenna could be designed that would emit power only when it is in direct contact with the wound. The optimum frequency or frequencies for a specific application would depend on the required depth of penetration of the microwave energy. In fact, a computational simulation for each specific application could be performed, which would then match the characteristics of the antenna with the protein solder and tissue to best effect wound closure. An additional area of interest with potential benefit that remains to be validated is whether microwave energy can effectively kill bacteria in and around the wound. Thus, this may be an efficient method for simultaneously sterilizing and closing wounds.

  13. Impact of an Elevated Temperature Environment on Sn-Ag-Cu Interconnect Board Level High-G Mechanical Shock Performance

    NASA Astrophysics Data System (ADS)

    Lee, Tae-Kyu; Chen, Zhiqiang; Baty, Greg; Bieler, Thomas R.; Kim, Choong-Un

    2016-12-01

    The mechanical stability of Sn-Ag-Cu interconnects with low and high silver content against mechanical shock at room and elevated temperatures was investigated. With a heating element-embedded printed circuit board design, a test temperature from room temperature to 80°C was established. High impact shock tests were applied to isothermally pre-conditioned ball-grid array interconnects. Under cyclic shock testing, degradation and improved shock performances were identified associated with test temperature variation and non-solder mask defined and solder-mask defined pad design configuration differences. Different crack propagation paths were observed, induced by the effect of the elevated temperature test conditions and isothermal aging pre-conditions.

  14. Fuel cell system with interconnect

    DOEpatents

    Liu, Zhien; Goettler, Richard; Delaforce, Philip Mark

    2016-03-08

    The present invention includes a fuel cell system having an interconnect that reduces or eliminates diffusion (leakage) of fuel and oxidant by providing an increased densification, by forming the interconnect as a ceramic/metal composite.

  15. Optical transceivers for interconnections in satellite payloads

    NASA Astrophysics Data System (ADS)

    Karppinen, Mikko; Heikkinen, Veli; Juntunen, Eveliina; Kautio, Kari; Ollila, Jyrki; Sitomaniemi, Aila; Tanskanen, Antti

    2013-02-01

    The increasing data rates and processing on board satellites call for the use of photonic interconnects providing high-bitrate performance as well as valuable savings in mass and volume. Therefore, optical transmitter and receiver technology is developed for aerospace applications. The metal-ceramic-packaging with hermetic fiber pigtails enables robustness for the harsh spacecraft environment, while the 850-nm VCSEL-based transceiver technology meets the high bit-rate and low power requirements. The developed components include 6 Gbps SpaceFibre duplex transceivers for intra-satellite data links and 40 Gbps parallel optical transceivers for board-to-board interconnects. Also, integration concept of interchip optical interconnects for onboard processor ICs is presented.

  16. Effect of the Soldering Process on the Microstructure and Mechanical Properties of Sn-9Zn/Al Solder Joints

    NASA Astrophysics Data System (ADS)

    Yao, Yao; Feng, Xue; Jian, Zhou; Zhanying, Feng; Xu, Chen

    2015-08-01

    Tin-zinc solder alloys are considered to be appropriate for soldering of aluminum alloys at low-temperature in electronics and radiators applications. In this paper, the effects of different soldering parameters on the microstructure and interfacial reaction behaviors of 1070Al/Sn-9Zn/1070Al joints were investigated. The results show that the Al substrate was dissolved by the liquid solder, but Al-related intermetallic was not observed in the interface. Two kinds of Al-rich phases formed in the solder matrix. Large butterfly-shaped solid solution (Al)″ phases (about 10 μm) were formed in the liquid alloys, and compact-shaped precipitations (nano-size) were dissolved out from solders during solidification process. With increasing of the soldering time, Al″ phases were migrated upwards in the solders and the amount of this phase increased. In addition, with the increase of the soldering temperature, the dissolution rate of Al into the solder increased and the formation time of (Al)″ phases was reduced. Shear test results indicate when soldered at 250 °C, the shear strength increased from 48.6 MPa to a maximum 60.5 MPa and then decreased to a stable value (about 55 MPa) with increasing of the soldering time. Similar trends were also observed at 300 and 350 °C, while the soldering time needed to obtain maximum shear strength was shortened. The formation of these Al-rich phases improves the shear strength but deteriorates the ductility.

  17. Characterization of eutectic Sn-Bi solder joints

    NASA Astrophysics Data System (ADS)

    Mei, Z.; Morris, J. W.

    1992-06-01

    This report presents experimental results on 58Bi-42Sn solder joints, optical and SEM microstructures of their matrix and of their interface with copper, solidification behavior studied by differential scanning calorimetry, wettability to copper, creep, and low cycle fatigue. These results are discussed in comparison with 60Sn-40Pb solder, and with three low temperature solders, 52In-48Sn, 43Sn-43Pb-14Bi, and 40In-40Sn-20Pb. The 58Bi-42Sn solder paste with RMA flux wets Cu matrix with a wetting angle of 35° and had a 15° C undercooling during solidification. The constitutive equation of the steady state shear strain rate, and the Coffin-Manson relation constants for the low cycle shear fatigue life at 65° C have been determined. The test results show that this solder has the best creep resistance but the poorest fatigue strength compared with the other four solders.

  18. Issues in the replacement of lead-bearing solders

    NASA Astrophysics Data System (ADS)

    Vianco, Paul T.; Frear, Darrel R.

    1993-07-01

    The use of soft solders, particularly those containing lead, dates back nearly 5,000 years. Solders similar to the materials used to seal the aqueducts of ancient Rome are now an important building block in the manufacture of high-speed computer assemblies. This history attests to the technological versatility of soft solders and, in particular, the solder alloys that contain lead. However, the health effects of prolonged exposure to lead have also been documented; measures to limit human exposure—at the work place and indirectly through the environment—are being considered. The successful introduction of lead-free solders into future electronic products will rely heavily upon their solderability, which can be evaluated by test procedures such as the meniscometer/wetting balance technique and the capillary flow test.

  19. Microstructural Evolution and Mechanical Properties of Au-20wt.%Sn|Ni Interconnection

    NASA Astrophysics Data System (ADS)

    Dong, H. Q.; Vuorinen, V.; Liu, X. W.; Laurila, T.; Li, J.; Paulasto-Kröckel, M.

    2016-01-01

    In this paper, the microstructural evolution and properties of Au-20wt.%Sn|Ni reaction couples were investigated from two perspectives: (1) by analyzing the microstructure of the as-soldered and aged samples, as well as (2) by measuring the mechanical properties of the intermetallic compounds formed within the reaction zone. The evolution of interfacial reaction products for both the as-soldered and aged interconnections was rationalized by using the experimental results in combination with assessed thermodynamic data from the Au-Ni-Sn system. Moreover, nanoindentation tests were implemented to measure the indentation modulus and hardness of the compounds formed at the interface. It was found that aging had a negligible influence on the elastic modulus and hardness of AuSn and Au5Sn, while the solubility of the third element significantly changed the indentation modulus and hardness of the intermetallic compounds.

  20. Fatigue of Advanced In-Situ Composite Solders

    DTIC Science & Technology

    2007-11-02

    ABSTRACT (Maximum 200 words) " ~~" Solder joints used in surface mount technology experience thermomechanical fatigue due to the mismatches in...solder joint to undergo shear strains. The purpose of this study was to examine and explain the thermomechanical fatigue damage mechanisms of various...types of solder compositions. Shear, creep, low cycle fatigue , and thermomechanical fatigue tests were conducted in this research. The development

  1. Anomalous creep in Sn-rich solder joints

    SciTech Connect

    Song, Ho Geon; Morris Jr., John W.; Hua, Fay

    2002-03-15

    This paper discusses the creep behavior of example Sn-rich solders that have become candidates for use in Pb-free solder joints. The specific solders discussed are Sn-3.5Ag, Sn-3Ag-0.5Cu, Sn-0.7Cu and Sn-10In-3.1Ag, used in thin joints between Cu and Ni-Au metallized pads.

  2. Transient Crack Growth Behavior Under Cycle/Time-Dependent Step Loading for Pb-Containing and Pb-Free Solders

    NASA Astrophysics Data System (ADS)

    Fakpan, Kittichai; Otsuka, Yuichi; Miyashita, Yukio; Mutoh, Yoshiharu; Nagata, Kohsoku

    2013-12-01

    In the present study, fatigue crack growth tests of Pb-containing [Sn-37Pb (wt.%)] and Pb-free [Sn-3.0Ag-0.5Cu (wt.%)] solders were performed under cycle/time-dependent step loading at a constant J-integral range (Δ J). The C * parameter was also estimated for discussing time-dependent crack growth behavior. The experimental results indicated that acceleration of the crack growth rate at the beginning of the second loading step was induced when the C * value for the first loading step was high, regardless of time- or cycle-dependent crack growth and for both Sn-37Pb and Sn-3.0Ag-0.5Cu solders. The length of the acceleration region of the crack growth rate for both solders was in good agreement with the creep damage zone size estimated by the creep zone model proposed by Riedel and Rice.

  3. Magellan/Galileo solder joint failure analysis and recommendations

    NASA Technical Reports Server (NTRS)

    Ross, Ronald G., Jr.

    1989-01-01

    On or about November 10, 1988 an open circuit solder joint was discovered in the Magellan Radar digital unit (DFU) during integration testing at Kennedy Space Center (KSC). A detailed analysis of the cause of the failure was conducted at the Jet Propulsion Laboratory leading to the successful repair of many pieces of affected electronic hardware on both the Magellan and Galileo spacecraft. The problem was caused by the presence of high thermal coefficient of expansion heat sink and conformal coating materials located in the large (0.055 inch) gap between Dual Inline Packages (DIPS) and the printed wiring board. The details of the observed problems are described and recommendations are made for improved design and testing activities in the future.

  4. Object-oriented graphical tool for automated laser soldering

    NASA Astrophysics Data System (ADS)

    Fidan, Ismail

    1995-10-01

    Object-oriented interfaces (OOIs) have become an important component of automation activity. Object-oriented software techniques have provided some hope to cope with the complexity of modern software development tasks. Object orientation is expressed by many researchers as an important direction in designing and implementing software in the 1990s and beyond. In today's electronics industry, there are several different types of interfaces used for different pieces of manufacturing equipment. It is now possible to create a general, OOI for most manufacturing equipment that is easy to use, easy to learn how to use, and easy to modify. Such an interface can benefit the user in terms of savings in time and money. The laser soldering interface, designed and implemented in the Center for Integrated Electronics and Electronics Manufacturing (CIEEM) at Rensselaer, is one of the 'flexible' user interfaces described above. This paper describes the object-oriented graphical tool (OOGT) development and its final structure.

  5. Coarsening of the Sn-Pb Solder Microstructure in Constitutive Model-Based Predictions of Solder Joint Thermal Mechanical Fatigue

    SciTech Connect

    Vianco, P.T.; Burchett, S.N.; Neilsen, M.K.; Rejent, J.A.; Frear, D.R.

    1999-04-12

    Thermal mechanical fatigue (TMF) is an important damage mechanism for solder joints exposed to cyclic temperature environments. Predicting the service reliability of solder joints exposed to such conditions requires two knowledge bases: first, the extent of fatigue damage incurred by the solder microstructure leading up to fatigue crack initiation, must be quantified in both time and space domains. Secondly, fatigue crack initiation and growth must be predicted since this metric determines, explicitly, the loss of solder joint functionality as it pertains to its mechanical fastening as well as electrical continuity roles. This paper will describe recent progress in a research effort to establish a microstructurally-based, constitutive model that predicts TMF deformation to 63Sn-37Pb solder in electronic solder joints up to the crack initiation step. The model is implemented using a finite element setting; therefore, the effects of both global and local thermal expansion mismatch conditions in the joint that would arise from temperature cycling.

  6. Solderability preservation through the use of organic inhibitors

    SciTech Connect

    Sorensen, N.R.; Hosking, F.M.

    1994-12-01

    Organic inhibitors can be used to prevent corrosion of metals and have application in the electronics industry as solderability preservatives. We have developed a model to describe the action of two inhibitors (benzotriazole and imidazole) during the environmental aging and soldering process. The inhibitors bond with the metal surface and form a barrier that prevents or retards oxidation. At soldering temperatures, the metal-organic complex breaks down leaving an oxide-free metal surface that allows excellent wetting by molten solder. The presence of the inhibitor retards the wetting rate relative to clean copper, but provides a vast improvement relative to oxidized copper.

  7. Aging, stressing and solderability of electroplated and electroless copper

    SciTech Connect

    Sorensen, N.R.; Hosking, F.M.

    1995-08-01

    Organic inhibitors can be used to prevent corrosion of metals have application in the electronics industry as solderability preservatives. We have developed a model to describe the action of two inhibitors (benzotriazole and imidazole) during the environmental aging and soldering process. The inhibitors bond with the metal surface and form a barrier that prevents or retards oxidation. At soldering temperatures, the metal-organic complex breaks down leaving an oxide-free metal surface that allows excellent wetting by the molten solder. The presence of the inhibitor retards the wetting rate relative to clean copper but provides a vast improvement relative to oxidized copper.

  8. Shaping Transistor Leads for Better Solder Joints

    NASA Technical Reports Server (NTRS)

    Mandel, H.; Dillon, J. D.

    1982-01-01

    Special lead-forming tool puts step in leads of microwave power transistors without damaging braze joints that fasten leads to package. Stepped leads are soldered to circuit boards more reliably than straight leads, and stress on brazes is relieved. Lead-forming hand-tool has two parts: a forming die and an actuator. Spring-loaded saddle is adjusted so that when transistor package is placed on it, leads rest on forming rails.

  9. Carbon Nanotube Interconnect

    NASA Technical Reports Server (NTRS)

    Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

    2006-01-01

    Method and system for fabricating an electrical interconnect capable of supporting very high current densities ( 10(exp 6)-10(exp 10) Amps/sq cm), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOw, or SiuNv is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

  10. Optical backplane interconnect switch for data processors and computers

    NASA Technical Reports Server (NTRS)

    Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

    1989-01-01

    An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

  11. Controlling microstructure and mechanical properties of the new microelectronic interconnect alloys

    NASA Astrophysics Data System (ADS)

    Mutuku, Francis M.

    An in-depth understanding of the physics of solidification could lead to the optimization of the properties of micro-electronic interconnects. Sn is the base material in the billions of interconnects in devices such as smart phones. These interconnects are formed by melting and solidifying a solder alloy (e.g. SnAgCu) in situ. But Sn has a low symmetry structure, Sn nucleation from the solder melt is complex and the morphology of the Sn and Sn alloys precipitates that form during solidification can vary tremendously (along with resultant mechanical properties). The effect of processing parameters on the solidification behavior, microstructure, and properties must be carefully addressed. Strong evidence adduced in this study shows that under many conditions, when cooling near eutectic SnAgCu from the melt, Ag3Sn nucleates before beta-Sn. The difficulty in the nucleation of beta-Sn provides a window of time between the nucleation of Ag3Sn precipitates and of beta-Sn solidification within which the Ag3Sn precipitate morphology can be manipulated. Thus distinct variations in precipitate number density, and inter-particle spacing were observed for different thermal histories, e.g. for different cooling rates. The average number density of Ag3Sn particles and the area of the pseudo-eutectic phase were observed to increase with increase in the Ag concentration, and with increase in the cooling rate. The shear strength and shear fatigue life increased with increase in the area fraction of the pseudo-eutectic phase. Upon aging of SnAgCu solder joints at an elevated temperature, the Ag3Sn particles coarsened, and became less effective in impeding dislocation motion. Consequently, the shear strength and shear fatigue performance degraded. On the other hand, alloys with constituents that formed solid solutions in Sn, such as small concentrations of Bi or Sb registered less degradation in both shear strength and shear fatigue life upon aging.

  12. Policy issues in interconnecting networks

    NASA Technical Reports Server (NTRS)

    Leiner, Barry M.

    1989-01-01

    To support the activities of the Federal Research Coordinating Committee (FRICC) in creating an interconnected set of networks to serve the research community, two workshops were held to address the technical support of policy issues that arise when interconnecting such networks. The workshops addressed the required and feasible technologies and architectures that could be used to satisfy the desired policies for interconnection. The results of the workshop are documented.

  13. Fuel cell system with interconnect

    DOEpatents

    Liu, Zhien; Goettler, Richard

    2015-09-29

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  14. Optical interconnection of optical modules

    NASA Astrophysics Data System (ADS)

    Schamschula, Marius P.; Caulfield, H. J.; Shamir, Joseph

    1990-12-01

    The most plausible possible uses of nonlinear optics as the bases for interconnections among complex optical modules are evaluated, with a view to such applications as neural networks that entail large numbers of interconnections and numerous stages. Optical interconnection allows such a system to be composed of many modules as well as to incorporate switching- and amplification-function optical nonlinearities. While it is possible to achieve a pixel-by-pixel, diffraction-limited flat-field relay with nonlinearity, where the interconnect allows for cascadability, the wave-particle duality is destroyed between stages.

  15. Characterization of Solder Joint Reliability Using Cyclic Mechanical Fatigue Testing

    NASA Astrophysics Data System (ADS)

    Kim, Choong-Un; Bang, Woong-Ho; Xu, Huili; Lee, Tae-Kyu

    2013-10-01

    This article summarizes the mechanics of two mechanical fatigue methods, cyclic bending fatigue and shear fatigue, in inducing failure in solder joints in package assemblies, and it presents the characteristics of fatigue failures resulting from these methods using example cases of Sn-Pb eutectic and Sn-rich Pb-free solder alloys. Numerical simulation suggests that both testing configurations induce fatigue failure by the crack-opening mode. In the case of bending fatigue, the strain induced by the bending displacement is found to be sensitive to chip geometry, and it induces fatigue cracks mainly at the solder matrix adjacent to the printed circuit board interface. In case of shear fatigue, the failure location is firmly fixed at the solder neck, created by solder mask, where an abrupt change in the solder geometry occurs. Both methods conclude that the Coffin-Manson model is the most appropriate model for the isothermal mechanical fatigue of solder alloys. An analysis of fatigue characteristics using the frame of the Coffin-Manson model produces several insightful results, such as the reason why Pb-free alloys show higher fatigue resistance than Sn-Pb alloys even if they are generally more brittle. Our analysis suggests that it is related to higher work hardening. All these results indicate that mechanical fatigue can be an extremely useful method for fast screening of defective package structures and also in gaining a better understanding of fatigue failure mechanism and prediction of reliability in solder joints.

  16. Local and Global Properties of a Lead-Free Solder

    NASA Astrophysics Data System (ADS)

    Ma, Z.; Chalon, F.; Leroy, R.; Ranganathan, N.; Beake, B. D.

    2013-07-01

    Elastic and viscous properties including Young's modulus, hardness, creep rate sensitivity, and fatigue resistance of Sn-1.2Ag-0.5Cu-0.05Ni lead-free solder have been investigated. The properties of bulk specimens and in situ solder balls are compared. Experiments show good correlations of Young's modulus and creep rate sensitivity between conventional measurements and nanoindentation results on bulk specimens. Further mechanical properties of the beach-ball microstructure in solder balls are characterized by nanoindentation. The load-partial unload technique has been used to determine the variation in mechanical properties with increasing depth of penetration into the intermetallic inclusions in the in situ solder. The fatigue resistances of the bulk specimens and solder balls are compared by using the novel nanoimpact method. In comparison with bulk specimens, it is found that in situ solder has higher Young's modulus, lower creep strain rate sensitivity, and better fatigue resistance. The effects of soldering and the scale differences strongly affect the mechanical and fatigue properties of in situ solder.

  17. Handling fixture for soldering round wires to FCC

    NASA Technical Reports Server (NTRS)

    Loggins, R.; Martineck, H. G.

    1971-01-01

    Fixture holds flat conductor cable and wires in position until after soldering of contacting conductor ends and potting of junctions. Device provides for proper spacing of wires and adequate access for soldered joints during fabrication, and positions mold halves during potting operation.

  18. Direct-soldering 6061 aluminum alloys with ultrasonic coating.

    PubMed

    Ding, Min; Zhang, Pei-lei; Zhang, Zhen-yu; Yao, Shun

    2010-02-01

    In this study, the authors applied furnace soldering with ultrasonic coating method to solder 6061 aluminum alloy and investigated the effects of both coating time and soldering temperature on its properties. The following results were obtained: firstly, the solder region mainly composed of four kinds of microstructure zones: rich Sn zone, rich-Pb zone, Sn-Pb eutectic phase and rich Al zone. Meanwhile, the microanalysis identified a continuous reaction product at the alumina-solder interface as a rich-Pb zone. Therefore, the joint strength changed with soldering time and soldering temperature. Secondly, the tensile data had significantly greater variability, with values ranging from 13.99MPa to 24.74MPa. The highest value was obtained for the samples coated with Sn-Pb-Zn alloy for 45s. Fractures occurred along the solder-alumina interface for the 6061 aluminum alloy with its surface including hybrid tough fracture of dimple and tear ridge. The interface could initially strip at the rich Bi zone with the effect of shear stress.

  19. A study of thermal cycling and radiation effects on indium and solder bump bonds

    SciTech Connect

    Simon Kwan et al.

    2001-12-11

    The BTeV hybrid pixel detector is constructed of readout chips and sensor arrays which are developed separately. The detector is assembled by flip-chip mating of the two parts. This method requires the availability of highly reliable, reasonably low cost fine-pitch flip-chip attachment technology. We have tested the quality of two bump-bonding technologies; indium bumps (by Advanced Interconnect Technology Ltd. (AIT) of Hong Kong) and fluxless solder bumps (by MCNC in North Carolina, USA). The results have been presented elsewhere [1]. In this paper we describe tests we performed to further evaluate these technologies. We subjected 15 indium bump-bonded and 15 fluxless solder bump-bonded dummy detectors through a thermal cycle and then a dose of radiation to observe the effects of cooling, heating and radiation on bump-bonds. We also exercised the processes of HDI mounting and wire bonding to some of the dummy detectors to see the effect of these processes on bump bonds.

  20. Evaluation of soldered connectors of two base metal ceramic alloys.

    PubMed

    Lima Verde, M A; Stein, R S

    1994-04-01

    Soldered connectors for two base metal ceramic alloys (nickel-chromium and cobalt-chromium) were compared by use of four different techniques: (1) infrared preceramic soldering, (2) gas and oxygen preceramic soldering, (3) porcelain furnace postsoldering under vacuum, and (4) porcelain furnace postsoldering without vacuum. A control group was established with solid cast specimens of each alloy. No statistically significant difference was noted between infrared and torch preceramic soldering techniques for either of the two alloys. However, the joints postsoldered under vacuum were significantly superior to postsoldered connectors without vacuum (p < 0.0001). No significant differences were observed among techniques 1, 2, and 3, although the three groups were substantially superior to technique 4 for both alloys (p = 0.05). The control group for both alloys was appreciably stronger than the soldered groups (p < 0.0001), and the nickel-chromium samples within the control group were significantly stronger than the Co-Cr samples.

  1. Dry soldering with hot filament produced atomic hydrogen

    DOEpatents

    Panitz, Janda K. G.; Jellison, James L.; Staley, David J.

    1995-01-01

    A system for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs.

  2. Dry soldering with hot filament produced atomic hydrogen

    DOEpatents

    Panitz, J.K.G.; Jellison, J.L.; Staley, D.J.

    1995-04-25

    A system is disclosed for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs. 1 fig.

  3. A Study of Solder Alloy Ductility for Cryogenic Applications

    NASA Technical Reports Server (NTRS)

    Lupinacci, A.; Shapiro, A. A.; Suh, J-O.; Minor, A. M.

    2013-01-01

    For aerospace applications it is important to understand the mechanical performance of components at the extreme temperature conditions seen in service. For solder alloys used in microelectronics, cryogenic temperatures can prove problematic. At low temperatures Sn-based solders undergo a ductile to brittle transition that leads to brittle cracks, which can result in catastrophic failure of electronic components, assemblies and spacecraft payloads. As industrial processes begin to move away from Pb-Sn solder, it is even more critical to characterize the behavior of alternative Sn-based solders. Here we report on initial investigations using a modified Charpy test apparatus to characterize the ductile to brittle transformation temperature of nine different solder systems.

  4. Epidemics on interconnected networks

    NASA Astrophysics Data System (ADS)

    Dickison, Mark; Havlin, S.; Stanley, H. E.

    2012-06-01

    Populations are seldom completely isolated from their environment. Individuals in a particular geographic or social region may be considered a distinct network due to strong local ties but will also interact with individuals in other networks. We study the susceptible-infected-recovered process on interconnected network systems and find two distinct regimes. In strongly coupled network systems, epidemics occur simultaneously across the entire system at a critical infection strength βc, below which the disease does not spread. In contrast, in weakly coupled network systems, a mixed phase exists below βc of the coupled network system, where an epidemic occurs in one network but does not spread to the coupled network. We derive an expression for the network and disease parameters that allow this mixed phase and verify it numerically. Public health implications of communities comprising these two classes of network systems are also mentioned.

  5. Soldering-based easy packaging of thin polyimide multichannel electrodes for neuro-signal recording

    NASA Astrophysics Data System (ADS)

    Baek, Dong-Hyun; Han, Chang-Hee; Jung, Ha-Chul; Kim, Seon Min; Im, Chang-Hwan; Oh, Hyun-Jik; Jungho Pak, James; Lee, Sang-Hoon

    2012-11-01

    We propose a novel packaging method for preparing thin polyimide (PI) multichannel microelectrodes. The electrodes were connected simply by making a via-hole at the interconnection pad of a thin PI electrode, and a nickel (Ni) ring was constructed by electroplating through the via-hole to permit stable soldering with strong adhesion to the electrode and the printed circuit board. The electroplating conditions were optimized for the construction of a well-organized Ni ring. The electrical properties of the packaged electrode were evaluated by fabricating and packaging a 40-channel thin PI electrode. Animal experiments were performed using the packaged electrode for high-resolution recording of somatosensory evoked potential from the skull of a rat. The in vivo and in vitro tests demonstrated that the packaged PI electrode may be used broadly for the continuous measurement of bio-signals or for neural prosthetics.

  6. Printed interconnects for photovoltaic modules

    SciTech Connect

    Fields, J. D.; Pach, G.; Horowitz, K. A. W.; Stockert, T. R.; Woodhouse, M.; van Hest, M. F. A. M.

    2017-01-01

    Film-based photovoltaic modules employ monolithic interconnects to minimize resistance loss and enhance module voltage via series connection. Conventional interconnect construction occurs sequentially, with a scribing step following deposition of the bottom electrode, a second scribe after deposition of absorber and intermediate layers, and a third following deposition of the top electrode. This method produces interconnect widths of about 300 um, and the area comprised by interconnects within a module (generally about 3%) does not contribute to power generation. The present work reports on an increasingly popular strategy capable of reducing the interconnect width to less than 100 um: printing interconnects. Cost modeling projects a savings of about $0.02/watt for CdTe module production through the use of printed interconnects, with savings coming from both reduced capital expense and increased module power output. Printed interconnect demonstrations with copper-indium-gallium-diselenide and cadmium-telluride solar cells show successful voltage addition and miniaturization down to 250 um. Material selection guidelines and considerations for commercialization are discussed.

  7. Printability Optimization For Fine Pitch Solder Bonding

    SciTech Connect

    Kwon, Sang-Hyun; Lee, Chang-Woo; Yoo, Sehoon

    2011-01-17

    Effect of metal mask and pad design on solder printability was evaluated by DOE in this study. The process parameters were stencil thickness, squeegee angle, squeegee speed, mask separating speed, and pad angle of PCB. The main process parameters for printability were stencil thickness and squeegee angle. The response surface showed that maximum printability of 1005 chip was achieved at the stencil thickness of 0.12 mm while the maximum printability of 0603 and 0402 chip was obtained at the stencil thickness of 0.05 mm. The bonding strength of the MLCC chips was also directly related with the printability.

  8. Printability Optimization For Fine Pitch Solder Bonding

    NASA Astrophysics Data System (ADS)

    Kwon, Sang-Hyun; Lee, Chang-Woo; Yoo, Sehoon

    2011-01-01

    Effect of metal mask and pad design on solder printability was evaluated by DOE in this study. The process parameters were stencil thickness, squeegee angle, squeegee speed, mask separating speed, and pad angle of PCB. The main process parameters for printability were stencil thickness and squeegee angle. The response surface showed that maximum printability of 1005 chip was achieved at the stencil thickness of 0.12 mm while the maximum printability of 0603 and 0402 chip was obtained at the stencil thickness of 0.05 mm. The bonding strength of the MLCC chips was also directly related with the printability.

  9. Fatigue life prediction of solder joints

    SciTech Connect

    Jones, W.B.

    1991-09-10

    The current status of lifetime prediction under conditions of thermomechanical creep/fatigue is reviewed. Each method is summarized and the results of the application to solder joints is shown. While each method has been applied with some success, a predictive, phenomenological approach has not been developed and validated. A method which captures the response of a crack to steady-state and cycling environments appears to hold most the most promise to provide a useful design tool. 42 refs., 14 figs., 1 tab.

  10. Electromigration of composite Sn-Ag-Cu solder bumps

    NASA Astrophysics Data System (ADS)

    Sharma, Ashutosh; Xu, Di Erick; Chow, Jasper; Mayer, Michael; Sohn, Heung-Rak; Jung, Jae Pil

    2015-11-01

    This study investigates the electromigration (EM) behavior of lead free Sn-Ag-Cu (SAC) solder alloys that were reinforced with different types of nanoparticles [Copper-coated carbon nanotubes (Cu/CNT), La2O3, Graphene, SiC, and ZrO2]. The composite solders were bumped on a Cu substrate at 220°C, and the resistance of the bumped solders was measured using a four wire setup. Current aging was carried out for 4 hours at a temperature of 160°C, and an increase in resistance was noted during this time. Of all the composite solders that were studied, La2O3 and SiC reinforced SAC solders exhibited the smallest resistances after current aging. However, the rate of change in the resistance at room temperature was lower for the SiC-reinforced SAC solder. The SAC and Graphene reinforced SAC solder bumps completely failed within 15 - 20 min of these tests. The SiC nanoparticles were reported to possibly entrap the SAC atoms better than other nanoparticles with a lower rate of EM. [Figure not available: see fulltext.

  11. Advanced silicon device technologies for optical interconnects

    NASA Astrophysics Data System (ADS)

    Wosinski, Lech; Wang, Zhechao; Lou, Fei; Dai, Daoxin; Lourdudoss, Sebastian; Thylen, Lars

    2012-01-01

    Silicon photonics is an emerging technology offering novel solutions in different areas requiring highly integrated communication systems for optical networking, sensing, bio-applications and computer interconnects. Silicon photonicsbased communication has many advantages over electric wires for multiprocessor and multicore macro-chip architectures including high bandwidth data transmission, high speed and low power consumption. Following the INTEL's concept to "siliconize" photonics, silicon device technologies should be able to solve the fabrication problems for six main building blocks for realization of optical interconnects: light generation, guiding of light including wavelength selectivity, light modulation for signal encoding, detection, low cost assembly including optical connecting of the devices to the real world and finally the electronic control systems.

  12. Simulation of thermomechanical fatigue in solder joints

    SciTech Connect

    Fang, H.E.; Porter, V.L.; Fye, R.M.; Holm, E.A.

    1997-12-31

    Thermomechanical fatigue (TMF) is a very complex phenomenon in electronic component systems and has been identified as one prominent degradation mechanism for surface mount solder joints in the stockpile. In order to precisely predict the TMF-related effects on the reliability of electronic components in weapons, a multi-level simulation methodology is being developed at Sandia National Laboratories. This methodology links simulation codes of continuum mechanics (JAS3D), microstructural mechanics (GLAD), and microstructural evolution (PARGRAIN) to treat the disparate length scales that exist between the macroscopic response of the component and the microstructural changes occurring in its constituent materials. JAS3D is used to predict strain/temperature distributions in the component due to environmental variable fluctuations. GLAD identifies damage initiation and accumulation in detail based on the spatial information provided by JAS3D. PARGRAIN simulates the changes of material microstructure, such as the heterogeneous coarsening in Sn-Pb solder, when the component`s service environment varies.

  13. Hydraulically interconnected vehicle suspension: background and modelling

    NASA Astrophysics Data System (ADS)

    Zhang, Nong; Smith, Wade A.; Jeyakumaran, Jeku

    2010-01-01

    This paper presents a novel approach for the frequency domain analysis of a vehicle fitted with a general hydraulically interconnected suspension (HIS) system. Ideally, interconnected suspensions have the capability, unique among passive systems, to provide stiffness and damping characteristics dependent on the all-wheel suspension mode in operation. A basic, lumped-mass, four-degree-of-freedom half-car model is used to illustrate the proposed methodology. The mechanical-fluid boundary condition in the double-acting cylinders is modelled as an external force on the mechanical system and a moving boundary on the fluid system. The fluid system itself is modelled using the hydraulic impedance method, in which the relationships between the dynamic fluid states, i.e. pressures and flows, at the extremities of a single fluid circuit are determined by the transfer matrix method. A set of coupled, frequency-dependent equations, which govern the dynamics of the integrated half-car system, are then derived and the application of these equations to both free and forced vibration analysis is explained. The fluid system impedance matrix for the two general wheel-pair interconnection types-anti-synchronous and anti-oppositional-is also given. To further outline the application of the proposed methodology, the paper finishes with an example using a typical anti-roll HIS system. The integrated half-car system's free vibration solutions and frequency response functions are then obtained and discussed in some detail. The presented approach provides a scientific basis for investigating the dynamic characteristics of HIS-equipped vehicles, and the results offer further confirmation that interconnected suspension schemes can provide, at least to some extent, individual control of modal stiffness and damping characteristics.

  14. Teaching minority middle-school students to solder

    NASA Astrophysics Data System (ADS)

    Reardon, James; Gates, Billy J., Jr.

    2014-03-01

    We aspired to teach minority middle school students to solder. We found that important variables affecting our ability to do so included: student-to-teacher ratio, venue of instruction, relationships with community partners, and understanding of the structure of the student's worldview. Once the effects of these variables had been understood, we found the students readily learned to solder. We now want to see whether the acquisition of the skill of soldering leads the students to be more interested in technical careers and in going to college. Supported by an APS Outreach Mini-grant.

  15. Solder extrusion pressure bonding process and bonded products produced thereby

    DOEpatents

    Beavis, Leonard C.; Karnowsky, Maurice M.; Yost, Frederick G.

    1992-01-01

    Production of soldered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about -40.degree. C. and 110.degree. C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  16. Solder extrusion pressure bonding process and bonded products produced thereby

    DOEpatents

    Beavis, L.C.; Karnowsky, M.M.; Yost, F.G.

    1992-06-16

    Disclosed is a process for production of soldered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about [minus]40 C and 110 C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  17. Solder technology in the manufacturing of electronic products

    SciTech Connect

    Vianco, P.T.

    1993-08-01

    The electronics industry has relied heavily upon the use of soldering for both package construction and circuit assembly. The solder attachment of devices onto printed circuit boards and ceramic microcircuits has supported the high volume manufacturing processes responsible for low cost, high quality consumer products and military hardware. Defects incurred during the manufacturing process are minimized by the proper selection of solder alloys, substrate materials and process parameters. Prototyping efforts are then used to evaluate the manufacturability of the chosen material systems. Once manufacturing feasibility has been established, service reliability of the final product is evaluated through accelerated testing procedures.

  18. Oblique incidence of semi-guided waves on step-like folds in planar dielectric slabs: Lossless vertical interconnects in 3D integrated photonic circuits

    NASA Astrophysics Data System (ADS)

    Hildebrandt, Andre; Alhaddad, Samer; Hammer, Manfred; Förstner, Jens

    2016-02-01

    Semi-guided light propagation across linear folds of slab waveguides is being considered. Radiation losses vanish beyond certain critical angles of incidence, as can be understood by arguments resembling Snell's law. One thus realizes lossless propagation through 90-degree corner configurations, where the remaining guided waves are still subject to pronounced reflection and polarization conversion. A step-like system of two of these sharp corners can then be viewed as a system akin to a Fabry-Perot interferometer, with two partial reflectors at a distance given by the vertical separation of the slab cores. The respective resonance effect enables full transmission of semiguided, laterally plane waves through the step structures. One obtains a configuration that optically connects guiding layers at different elevation levels in a 3-D integrated optical chip, without radiation losses, over large distances, and reasonably broadband. We show rigorous quasi-analytical results for typical high-contrast Si/SiO2 structures. Although the full-transmission effect requires a symmetric system, here realized by slab waveguides with a silicon core sandwiched between thick silica substrate and cover layers, simulations for configurations with air cover show that a certain asymmetry can well be afforded.

  19. Interconnect resistance of photovoltaic submodules

    NASA Technical Reports Server (NTRS)

    Volltrauer, H.; Eser, E.; Delahoy, A. E.

    1985-01-01

    Small area amorphous silicon solar cells generally have higher efficiencies than large interconnected submodules. Among the reasons for the differences in performance are the lack of large area uniformity, the effect of nonzero tin oxide sheet resistance, and possibly pinholes in the various layers. Another and usually small effect that can contribute to reduced performance of interconnected cells is the resistance of the interconnection i.e., the series resistance introduced by the metal to tin oxide contact through silicon. Proper processing problems to avoid poor contacts are discussed.

  20. Material design of plasma-enhanced chemical vapour deposition SiCH films for low-k cap layers in the further scaling of ultra-large-scale integrated devices-Cu interconnects.

    PubMed

    Shimizu, Hideharu; Nagano, Shuji; Uedono, Akira; Tajima, Nobuo; Momose, Takeshi; Shimogaki, Yukihiro

    2013-10-01

    Cap layers for Cu interconnects in ultra-large-scale integrated devices (ULSIs), with a low dielectric constant (k-value) and strong barrier properties against Cu and moisture diffusion, are required for the future further scaling of ULSIs. There is a trade-off, however, between reducing the k-value and maintaining strong barrier properties. Using quantum mechanical simulations and other theoretical computations, we have designed ideal dielectrics: SiCH films with Si-C2H4-Si networks. Such films were estimated to have low porosity and low k; thus they are the key to realizing a cap layer with a low k and strong barrier properties against diffusion. For fabricating these ideal SiCH films, we designed four novel precursors: isobutyl trimethylsilane, diisobutyl dimethylsilane, 1, 1-divinylsilacyclopentane and 5-silaspiro [4,4] noname, based on quantum chemical calculations, because such fabrication is difficult by controlling only the process conditions in plasma-enhanced chemical vapor deposition (PECVD) using conventional precursors. We demonstrated that SiCH films prepared using these newly designed precursors had large amounts of Si-C2H4-Si networks and strong barrier properties. The pore structure of these films was then analyzed by positron annihilation spectroscopy, revealing that these SiCH films actually had low porosity, as we designed. These results validate our material and precursor design concepts for developing a PECVD process capable of fabricating a low-k cap layer.

  1. Effect of soldering techniques and gap distance on tensile strength of soldered Ni-Cr alloy joint

    PubMed Central

    Lee, Sang-Yeob

    2010-01-01

    PURPOSE The present study was intended to evaluate the effect of soldering techniques with infrared ray and gas torch under different gap distances (0.3 mm and 0.5 mm) on the tensile strength and surface porosity formation in Ni-Cr base metal alloy. MATERIALS AND METHODS Thirty five dumbbell shaped Ni-Cr alloy specimens were prepared and assigned to 5 groups according to the soldering method and the gap distance. For the soldering methods, gas torch (G group) and infrared ray (IR group) were compared and each group was subdivided by corresponding gap distance (0.3 mm: G3 and IR3, 0.5 mm: G5, IR5). Specimens of the experimental groups were sectioned in the middle with a diamond disk and embedded in solder blocks according to the predetermined distance. As a control group, 7 specimens were prepared without sectioning or soldering. After the soldering procedure, a tensile strength test was performed using universal testing machine at a crosshead speed 1 mm/min. The proportions of porosity on the fractured surface were calculated on the images acquired through the scanning electronic microscope. RESULTS Every specimen of G3, G5, IR3 and IR5 was fractured on the solder joint area. However, there was no significant difference between the test groups (P > .05). There was a negative correlation between porosity formation and tensile strength in all the specimens in the test groups (P < .05). CONCLUSION There was no significant difference in ultimate tensile strength of joints and porosity formations between the gas-oxygen torch soldering and infrared ray soldering technique or between the gap distance of 0.3 mm and 0.5 mm. PMID:21264189

  2. Universal Interconnection Technology Workshop Proceedings

    SciTech Connect

    Sheaffer, P.; Lemar, P.; Honton, E. J.; Kime, E.; Friedman, N. R.; Kroposki, B.; Galdo, J.

    2002-10-01

    The Universal Interconnection Technology (UIT) Workshop - sponsored by the U.S. Department of Energy, Distributed Energy and Electric Reliability (DEER) Program, and Distribution and Interconnection R&D - was held July 25-26, 2002, in Chicago, Ill., to: (1) Examine the need for a modular universal interconnection technology; (2) Identify UIT functional and technical requirements; (3) Assess the feasibility of and potential roadblocks to UIT; (4) Create an action plan for UIT development. These proceedings begin with an overview of the workshop. The body of the proceedings provides a series of industry representative-prepared papers on UIT functions and features, present interconnection technology, approaches to modularization and expandability, and technical issues in UIT development as well as detailed summaries of group discussions. Presentations, a list of participants, a copy of the agenda, and contact information are provided in the appendices of this document.

  3. IEEE P1547 Series of Standards for Interconnection: Preprint

    SciTech Connect

    Basso, T. S.; DeBlasio, R.

    2003-05-01

    The IEEE P1547 Standard For Interconnecting Distributed Resources With Electric Power Systems is the first in the P1547 series of planned interconnection standards, and additional standards are needed. There are major issues and obstacles to an orderly transition to the use and integration of distributed power resources with electric power systems (grid or utility grid). The lack of uniform national interconnection standards and tests for interconnection operation and certification-as well as the lack of uniform national building, electrical, and safety codes-is understood, and resolving this needs reasonable lead time to develop and promulgate consensus. The P1547 standard is a benchmark milestone for the IEEE standards consensus process and successfully demonstrates a model for ongoing success in the development of further national standards and for moving forward in modernizing our nation's electric power system.

  4. Solder fatigue reduction in point focus photovoltaic concentrator modules

    SciTech Connect

    Hund, T.D.; Burchett, S.N.

    1991-01-01

    Solder fatigue tests have been conducted on point focus photovoltaic concentration cell assemblies to identify a baseline fatigue life and to quantify the fatigue life improvements that result using a copper-molybdenum-copper low-expansion insert between the solar cell and copper heat spreader. Solder microstructural changes and fatigue crack growth were identified using cross sections and ultrasonic scans of the fatigue solder joints. The Coffin-Manson and Total Strain fatigue models for low-cycle fatigue were evaluated for use in fatigue life predictions. Since both of these models require strain calculations, two strain calculation methods were compared: hand-calculated shear strain and a finite element method shear strain. At present, the available theoretical models for low-cycle solder fatigue are limited in their ability to predict failure; consequently, extensive thermal cycling is continuing to define the fatigue life for point focus photovoltaic cell assemblies. 9 refs., 9 figs., 2 tabs.

  5. Investigation of gold embrittlement in connector solder joints

    NASA Technical Reports Server (NTRS)

    Lane, F. L.

    1972-01-01

    An investigation was performed to determine to what extent typical flight connector solder joints may be embrittled by the presence of gold. In addition to mapping of gold content in connector solder joints by an electron microprobe analyzer, metallographic examinations and mechanical tests (thermal shock, vibration, impact and tensile strength) were also conducted. A description of the specimens and tests, a discussion of the data, and some conclusions are presented.

  6. An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

    NASA Astrophysics Data System (ADS)

    Zhu, Zhang-Ming; Hao, Bao-Tian; En, Yun-Fei; Yang, Yin-Tang; Li, Yue-Jin

    2011-06-01

    On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.

  7. [Study on postsoldering of Ni-Cr ceramic alloys. Effect of soldering temperature and atmosphere].

    PubMed

    Ishigure, K

    1990-03-01

    The effects of soldering temperatures and atmospheres on tensile strength of solder joints were investigated for two types of Ni-Cr ceramic alloys and one type of gold solder for postsoldering. Each alloy and the gold solder were soldered with fluoride flux in an electric furnace in three different temperatures and four different atmospheres. Of the three different temperatures, one was just over the liquidus point of the solder, another 50 degrees C higher than the liquidus point and the other 100 degrees C higher than the liquidus point. Of the four different atmospheres, one was under vacuum, another under vacuum with a 6 l/h argon gas flow, another under vacuum with a 12 l/h argon gas flow and the other under vacuum with a 24 l/h argon gas flow. Tensile strength testing was performed at the solder joints. The fracture surface was observed by EPMA. Wettability of the liquid solder on each alloy was performed by the sessile drop method in high-purity argon gas. The surface tension and the contact angle of the liquid solder on MgO were determined by the sessile drop method in high-purity argon gas. The soldering was performed in the furnace used for the sessile drop method in high-purity argon gas. The results are summarized as follows. The tensile strength of UNI METAL-solder joints was significantly affected by the soldering temperature (p less than 0.01). However, the effect of the soldering atmosphere on the tensile strength was small. The effect of the soldering temperature and atmosphere on the tensile strength of Victory II-solder joints was small. Each alloy had a different adequate soldering temperature. With the increase in the soldering temperature, the diffusion layer of the solder joint interface increased, but no correlationship between the atmosphere and the diffusion layer thickness was observed. Fracture patterns of UNI METAL-solder joints were mixed adhesive-cohesive fractures with a large cohesive area. Fracture patterns of Victory II-solder

  8. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

    1989-05-09

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

  9. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, Timothy J.; Ginley, David S.; Zipperian, Thomas E.

    1989-01-01

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

  10. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

    1987-10-23

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In molecular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating. 1 tab.

  11. Characterization of eutectic Sn-Bi solder joints

    SciTech Connect

    Mei, Z.; Morris, J.W. Jr. )

    1992-06-01

    This report presents experimental results on 58Bi-42Sn solder joints, optical and SEM microstructures of their matrix and of their interface with copper, solidification behavior studied by differential scanning calorimetry, wettability to copper, creep, and low cycle fatigue. These results are discussed in comparison with 60Sn-40Pb solder, and with three low temperature solders, 52In-48Sn, 42Sn-43Pb-14Bi, and 40In-40Sn-20Pb. The 58Bi-42Sn solder paste with RMA flux wets Cu matrix with a wetting angle of 35[degree] and had a 15[degree] C undercooling during solidification. The constitutive equation of the steady state shear strain rate, and the Coffin-Manson relation constants for the low cycle shear fatigue life at 65[degree] C have been determined. The test results show that this solder has the best creep resistance but the poorest fatigue strength compared with the other four solders. 27 refs., 11 figs., 1 tab.

  12. Creep properties of Pb-free solder joints

    SciTech Connect

    Song, H.G.; Morris Jr., J.W.; Hua, F.

    2002-04-01

    Describes the creep behavior of three Sn-rich solders that have become candidates for use in Pb-free solder joints: Sn-3.5Ag, Sn-3Ag-0.5Cu and Sn-0.7Cu. The three solders show the same general behavior when tested in thin joints between Cu and Ni/Au metallized pads at temperatures between 60 and 130 C. Their steady-state creep rates are separated into two regimes with different stress exponents(n). The low-stress exponents range from {approx}3-6, while the high-stress exponents are anomalously high (7-12). Strikingly, the high-stress exponent has a strong temperature dependence near room temperature, increasing significantly as the temperature drops from 95 to 60 C. The anomalous creep behavior of the solders appears to be due to the dominant Sn constituent. Joints of pure Sn have stress exponents, n, that change with stress and temperature almost exactly like those of the Sn-rich solder joints. Research on creep in bulk samples of pure Sn suggests that the anomalous temperature dependence of the stress exponent may show a change in the dominant mechanism of creep. Whatever its source, it has the consequence that conventional constitutive relations for steady-state creep must be used with caution in treating Sn-rich solder joints, and qualification tests that are intended to verify performance should be carefully designed.

  13. Microsurgical anastomosis of sperm duct by laser tissue soldering

    NASA Astrophysics Data System (ADS)

    Wehner, Martin M.; Teutu-Kengne, Alain-Fleury; Brkovic, Drasko; Henning, Thomas; Klee, Doris; Poprawe, Reinhart; Jakse, Gerhard

    2005-04-01

    Connection of small vessels is usually done by suturing which is very cumbersome. Laser tissue soldering can circumvent that obstacle if a handy procedure can be defined. Our principle approach consists of a bioresorbable hollow stent with an expected degradation time of 3 weeks in combination with laser soldering. The stent is to be fed into the vessel to stabilize both ends and should allow percolation immediately after joining. The stents are made of Poly(D,L-lactid-co-glycolid) and solder is prepared from bovine serum albumin (BSA) doped with Indocyanine green (ICG) as chromophore to increase the absorption of laser light. After insertion, solder is applied onto the outer surface of the vessel and coagulated by laser radiation. The wavelength of 810 nm of a diode laser fits favorably to absorption properties of tissue and solder such that heating up of tissue is limited to prevent from necrosis and wound healing complications. In our study the preparation of stents, the consistency and doping of solder, a beam delivery instrument and the irradiation conditions are worked out. In-vitro tests are carried out on sperm ducts of Sprague-Dowlae (SD) rats. Different irradiation conditions are investigated and a micro-optical system consisting of a lens and a reflecting prism to ensure simultaneous irradiation of front and back side of the vessels tested. Under these conditions, the short-term rupture strength of laser anastomosis revealed as high as those achieved by suturing.

  14. Misalignment corrections in optical interconnects

    NASA Astrophysics Data System (ADS)

    Song, Deqiang

    Optical interconnects are considered a promising solution for long distance and high bitrate data transmissions, outperforming electrical interconnects in terms of loss and dispersion. Due to the bandwidth and distance advantage of optical interconnects, longer links have been implemented with optics. Recent studies show that optical interconnects have clear advantages even at very short distances---intra system interconnects. The biggest challenge for such optical interconnects is the alignment tolerance. Many free space optical components require very precise assembly and installation, and therefore the overall cost could be increased. This thesis studied the misalignment tolerance and possible alignment correction solutions for optical interconnects at backplane or board level. First the alignment tolerance for free space couplers was simulated and the result indicated the most critical alignments occur between the VCSEL, waveguide and microlens arrays. An in-situ microlens array fabrication method was designed and experimentally demonstrated, with no observable misalignment with the waveguide array. At the receiver side, conical lens arrays were proposed to replace simple microlens arrays for a larger angular alignment tolerance. Multilayer simulation models in CodeV were built to optimized the refractive index and shape profiles of the conical lens arrays. Conical lenses fabricated with micro injection molding machine and fiber etching were characterized. Active component VCSOA was used to correct misalignment in optical connectors between the board and backplane. The alignment correction capability were characterized for both DC and AC (1GHz) optical signal. The speed and bandwidth of the VCSOA was measured and compared with a same structure VCSEL. Based on the optical inverter being studied in our lab, an all-optical flip-flop was demonstrated using a pair of VCSOAs. This memory cell with random access ability can store one bit optical signal with set or

  15. Lead-free solder technology transfer from ASE Americas

    SciTech Connect

    FTHENAKIS,V.

    1999-10-19

    To safeguard the environmental friendliness of photovoltaics, the PV industry follows a proactive, long-term environmental strategy involving a life-of-cycle approach to prevent environmental damage by its processes and products from cradle to grave. Part of this strategy is to examine substituting lead-based solder on PV modules with other solder alloys. Lead is a toxic metal that, if ingested, can damage the brain, nervous system, liver and kidneys. Lead from solder in electronic products has been found to leach out from municipal waste landfills and municipal incinerator ash was found to be high in lead also because of disposed consumer electronics and batteries. Consequently, there is a movement in Europe and Japan to ban lead altogether from use in electronic products and to restrict the movement across geographical boundaries of waste containing lead. Photovoltaic modules may contain small amounts of regulated materials, which vary from one technology to another. Environmental regulations impact the cost and complexity of dealing with end-of-life PV modules. If they were classified as hazardous according to Federal or State criteria, then special requirements for material handling, disposal, record-keeping and reporting would escalate the cost of decommissioning the modules. Fthenakis showed that several of today's x-Si modules failed the US-EPA Toxicity Characteristic Leaching Procedure (TCLP) for potential leaching of Pb in landfills and also California's standard on Total Threshold Limit Concentration (TTLC) for Pb. Consequently, such modules may be classified as hazardous waste. He highlighted potential legislation in Europe and Japan which could ban or restrict the use of lead and the efforts of the printed-circuit industries in developing Pb-free solder technologies in response to such expected legislation. Japanese firms already have introduced electronic products with Pb-free solder, and one PV manufacturer in the US, ASE Americas has used a Pb

  16. Average interconnection length and interconnection distribution for rectangular arrays

    NASA Astrophysics Data System (ADS)

    Gura, Carol; Abraham, Jacob A.

    1989-05-01

    It is shown that it is necessary to utilize different partitioning coefficients in interconnection length analyses which are based on Rent's rule, depending on whether one- or two-dimensional placement strategies are used. Beta is the partitioning coefficient in the power-law relationship Alpha Beta which provides a measure of the number of interconnection that cross a boundary which encloses Beta blocks. The partitioning coefficients are Beta = p/2 and Beta = p for two- and one-dimensional arrays, respectively, where p is the experimental coefficient, of the Rent relationship. Based on these separate partitioning coefficients, an average interconnection length prediction is presented for rectangular arrays that out performs existing predictions. Examples are given to support this theory.

  17. Characterization of Low-Melting-Point Sn-Bi-In Lead-Free Solders

    NASA Astrophysics Data System (ADS)

    Li, Qin; Ma, Ninshu; Lei, YongPing; Lin, Jian; Fu, HanGuang; Gu, Jian

    2016-11-01

    Development of lead-free solders with low melting temperature is important for substitution of Pb-based solders to reduce direct risks to human health and the environment. In the present work, Sn-Bi-In solders were studied for different ratios of Bi and Sn to obtain solders with low melting temperature. The microstructure, thermal properties, wettability, mechanical properties, and reliability of joints with Cu have been investigated. The results show that the microstructures of the Sn-Bi-In solders were composed of β-Sn, Bi, and InBi phases. The intermetallic compound (IMC) layer was mainly composed of Cu6Sn5, and its thickness increased slightly as the Bi content was increased. The melting temperature of the solders was around 100°C to 104°C. However, when the Sn content exceeded 50 wt.%, the melting range became larger and the wettability became worse. The tensile strength of the solder alloys and solder joints declined with increasing Bi content. Two fracture modes (IMC layer fracture and solder/IMC mixed fracture) were found in solder joints. The fracture mechanism of solder joints was brittle fracture. In addition, cleavage steps on the fracture surface and coarse grains in the fracture structure were comparatively apparent for higher Bi content, resulting in decreased elongation for both solder alloys and solder joints.

  18. Polyhedral integrated and free space optical interconnection

    DOEpatents

    Erteza, Ireena A.

    1998-01-01

    An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment.

  19. Polyhedral integrated and free space optical interconnection

    DOEpatents

    Erteza, I.A.

    1998-01-06

    An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment. 7 figs.

  20. Scaling of Metal Interconnects: Challenges to Functionality and Reliability

    SciTech Connect

    Engelhardt, M.; Schindler, G.; Traving, M.; Stich, A.; Gabric, Z.; Pamler, W.; Hoenlein, W.

    2006-02-07

    Copper-based nano interconnects featuring CDs well beyond today's chip generations and air gap structures were fabricated and subjected to electrical characterization and tests to get already today insight on functionality and reliability aspects of metallization schemes in future semiconductor products. Size effects observed already in today's advanced products will definitely limit the resistivity in future interconnects. Copper diffusion barrier layers were scaled down to the 1nm regime of thicknesses without observable degradation effects regarding adhesion properties and functionality. Interconnect reliability was found to decrease with decreasing barrier thickness. Worst results regarding adhesion properties and interconnect reliability were obtained for vanishing barrier thickness which promotes unrestricted mass flow of copper along the interconnect line. Air gaps were developed and characterized as an alternative approach to porous ultra low-k materials. They allowed the realization of effective k-values of the insulation of 2.4, which meet requirements of chip generations far in the future, while avoiding the integration issues associated with these soft materials. First reliability results obtained with air gaps are comparable with those obtained on full structures. Whereas leakage current behavior with electrical field strength expected to be present between neighboring lines in chip generations during the next 10 years were similar for air gaps and oxide, interconnects insulated by air gaps displayed lower breakdown fields than those insulated by oxide.

  1. Scaling of Metal Interconnects: Challenges to Functionality and Reliability

    NASA Astrophysics Data System (ADS)

    Engelhardt, M.; Schindler, G.; Traving, M.; Stich, A.; Gabric, Z.; Pamler, W.; Hönlein, W.

    2006-02-01

    Copper-based nano interconnects featuring CDs well beyond today's chip generations and air gap structures were fabricated and subjected to electrical characterization and tests to get already today insight on functionality and reliability aspects of metallization schemes in future semiconductor products. Size effects observed already in today's advanced products will definitely limit the resistivity in future interconnects. Copper diffusion barrier layers were scaled down to the 1nm regime of thicknesses without observable degradation effects regarding adhesion properties and functionality. Interconnect reliability was found to decrease with decreasing barrier thickness. Worst results regarding adhesion properties and interconnect reliability were obtained for vanishing barrier thickness which promotes unrestricted mass flow of copper along the interconnect line. Air gaps were developed and characterized as an alternative approach to porous ultra low-k materials. They allowed the realization of effective k-values of the insulation of 2.4, which meet requirements of chip generations far in the future, while avoiding the integration issues associated with these soft materials. First reliability results obtained with air gaps are comparable with those obtained on full structures. Whereas leakage current behavior with electrical field strength expected to be present between neighboring lines in chip generations during the next 10 years were similar for air gaps and oxide, interconnects insulated by air gaps displayed lower breakdown fields than those insulated by oxide.

  2. Finite width coplanar waveguide patch antenna with vertical fed through interconnect

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.; Lee, Richard Q.; Shalkhauser, Kurt A.; Owens, Jonathan; Demarco, James; Leen, Joan; Sturzebecher, Dana

    1996-01-01

    The paper presents the design, fabrication and characterization of a finite width Coplanar waveguide (FCPW) patch antenna and a FCPW-to-FCPW vertical interconnect. The experimental results demonstrate the antenna and interconnect performance. A scheme to integrate an eight element FCPW patch array with MMIC phase shifters and amplifiers using vertical interconnects is described. The antenna module has potential applications in an advanced satellite to ground transmit phased array at K-Band.

  3. Development of a new Pb-free solder: Sn-Ag-Cu

    SciTech Connect

    Miller, Chad M.

    1995-02-10

    With the ever increasing awareness of the toxicity of Pb, significant pressure has been put on the electronics industry to get the Pb out of solder. This work pertains to the development and characterization of an alloy which is Pb-free, yet retains the proven positive qualities of current Sn-Pb solders while enhancing the shortcomings of Sn-Pb solder. The solder studied is the Sn-4.7Ag-1.7Cu wt% alloy. By utilizing a variety of experimental techniques the alloy was characterized. The alloy has a melting temperature of 217°C and exhibits eutectic melting behavior. The solder was examined by subjecting to different annealing schedules and examining the microstructural stability. The effect of cooling rate on the microstructure of the solder was also examined. Overall, this solder alloy shows great promise as a viable alternative to Pb-bearing solders and, as such, an application for a patent has been filed.

  4. Solder wetting behavior enhancement via laser-textured surface microcosmic topography

    NASA Astrophysics Data System (ADS)

    Chen, Haiyan; Peng, Jianke; Fu, Li; Wang, Xincheng; Xie, Yan

    2016-04-01

    In order to reduce or even replace the use of Sn-Pb solder in electronics industry, the laser-textured surface microstructures were used to enhance the wetting behavior of lead free solder during soldering. According to wetting theory and Sn-Ag-Cu lead free solder performance, we calculated and designed four microcosmic structures with the similar shape and different sizes to control the wetting behavior of lead free solder. The micro-structured surfaces with different dimensions were processed on copper plates by fiber femtosecond laser, and the effect of microstructures on wetting behavior was verified experimentally. The results showed that the wetting angle of Sn-Ag-Cu solder on the copper plate with microstructures decreased effectively compared with that on the smooth copper plate. The wetting angles had a sound fit with the theoretical values calculated by wetting model. The novel method provided a feasible route for adjusting the wetting behavior of solders and optimizing solders system.

  5. Manufacturing of planar ceramic interconnects

    SciTech Connect

    Armstrong, B.L.; Coffey, G.W.; Meinhardt, K.D.; Armstrong, T.R.

    1996-12-31

    The fabrication of ceramic interconnects for solid oxide fuel cells (SOFC) and separator plates for electrochemical separation devices has been a perennial challenge facing developers. Electrochemical vapor deposition (EVD), plasma spraying, pressing, tape casting and tape calendering are processes that are typically utilized to fabricate separator plates or interconnects for the various SOFC designs and electrochemical separation devices. For sake of brevity and the selection of a planar fuel cell or gas separation device design, pressing will be the only fabrication technique discussed here. This paper reports on the effect of the characteristics of two doped lanthanum manganite powders used in the initial studies as a planar porous separator for a fuel cell cathode and as a dense interconnect for an oxygen generator.

  6. 3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

    NASA Astrophysics Data System (ADS)

    Le, Fuliang; Lee, Shi-Wei Ricky; Zhang, Qiming

    2017-04-01

    3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

  7. Microbial leaching of waste solder for recovery of metal.

    PubMed

    Hocheng, H; Hong, T; Jadhav, U

    2014-05-01

    This study proposes an environment-friendly bioleaching process for recovery of metals from solders. Tin-copper (Sn-Cu), tin-copper-silver (Sn-Cu-Ag), and tin-lead (Sn-Pb) solders were used in the current study. The culture supernatant of Aspergillus niger removed metals faster than the culture supernatant of Acidithiobacillus ferrooxidans. Also, the metal removal by A. niger culture supernatant is faster for Sn-Cu-Ag solder as compared to other solder types. The effect of various process parameters such as shaking speed, temperature, volume of culture supernatant, and increased solder weight on bioleaching of metals was studied. About 99 (±1.75) % metal dissolution was achieved in 60 h, at 200-rpm shaking speed, 30 °C temperature, and by using 100-ml A. niger culture supernatant. An optimum solder weight for bioleaching was found to be 5 g/l. Addition of sodium hydroxide (NaOH) and sodium chloride (NaCl) in the bioleached solution from Sn-Cu-Ag precipitated tin (85 ± 0.35 %) and silver (80 ± 0.08 %), respectively. Passing of hydrogen sulfide (H2S) gas at pH 8.1 selectively precipitated lead (57.18 ± 0.13 %) from the Sn-Pb bioleached solution. The proposed innovative bioleaching process provides an alternative technology for recycling waste solders to conserve resources and protect environment.

  8. Effect of Ag, Ni and Bi Additions on Solderability of Lead-Free Solders

    NASA Astrophysics Data System (ADS)

    Nobari, Amir Hossein; Maalekian, Mehran; Seelig, Karl; Pekguleryuz, Mihriban

    2017-01-01

    In this study, the effects of Ag, Ni and Bi additions on the melting, solidification, fluidity and wetting behavior of Sn-0.7Cu base solder alloy are studied. The addition of a small amount of Ni reduces the undercooling and improves the feeding distance (fluidity length); however, Ni does not improve the wetting and the spreading performance. The effect of Ni on the fluidity length of Ag-containing Sn-0.7Cu (SAC alloy) is marginal. Bi and Ag both improve wetting performance and also lower the melting temperature; however, they do not improve the fluidity; instead, they reduce the maximum length of fluidity.

  9. Si photonics technology for future optical interconnection

    NASA Astrophysics Data System (ADS)

    Zheng, Xuezhe; Krishnamoorthy, Ashok V.

    2011-12-01

    Scaling of computing systems require ultra-efficient interconnects with large bandwidth density. Silicon photonics offers a disruptive solution with advantages in reach, energy efficiency and bandwidth density. We review our progress in developing building blocks for ultra-efficient WDM silicon photonic links. Employing microsolder based hybrid integration with low parasitics and high density, we optimize photonic devices on SOI platforms and VLSI circuits on more advanced bulk CMOS technology nodes independently. Progressively, we successfully demonstrated single channel hybrid silicon photonic transceivers at 5 Gbps and 10 Gbps, and 80 Gbps arrayed WDM silicon photonic transceiver using reverse biased depletion ring modulators and Ge waveguide photo detectors. Record-high energy efficiency of less than 100fJ/bit and 385 fJ/bit were achieved for the hybrid integrated transmitter and receiver, respectively. Waveguide grating based optical proximity couplers were developed with low loss and large optical bandwidth to enable multi-layer intra/inter-chip optical interconnects. Thermal engineering of WDM devices by selective substrate removal, together with WDM link using synthetic wavelength comb, we significantly improved the device tuning efficiency and reduced the tuning range. Using these innovative techniques, two orders of magnitude tuning power reduction was achieved. And tuning cost of only a few 10s of fJ/bit is expected for high data rate WDM silicon photonic links.

  10. Aspects of short-range interconnect packaging

    NASA Astrophysics Data System (ADS)

    Wohlfeld, Denis; Brenner, Karl-Heinz

    2012-01-01

    In short-range interconnect applications, one question arises frequently: When should optical solutions be chosen over electrical wiring? The answer to this question of course depends on several factors like costs, performance, reliability, availability of testing equipment and knowledge about optical technologies, and last but not least, it strongly depends on the application itself. Networking in high performance computing (HPC) is one such example. With bit rates around 10 Gbit/s per channel and cable length above 2 m, the high attenuation of electrical cables leads to a clear preference of optical or active optical cables (AOC) for most planned HPC systems. For AOCs, the electro-optical conversion is realized inside the connector housing, while for purely optical cables, the conversion is done at the edge of the board. Proceeding to 25 Gbit/s and higher, attenuation and loss of signal quality become critical. Therefore, either significantly more effort has to be spent on the electrical side, or the package for conversion has to be integrated closer to the chip, thus requiring new packaging technologies. The paper provides a state of the art overview of packaging concepts for short range interconnects, it describes the main challenges of optical package integration and illustrates new concepts and trends in this research area.

  11. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  12. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  13. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  14. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  15. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  16. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  17. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  18. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  19. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  20. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  1. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  2. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  3. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  4. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  5. Methylene blue solder re-absorption in microvascular anastomoses

    NASA Astrophysics Data System (ADS)

    Birch, Jeremy F.; Hepplewhite, J.; Frier, Malcolm; Bell, Peter R. F.

    2003-06-01

    Soldered vascular anastomoses have been reported using several chromophores but little is known of the optimal conditions for microvascular anastomosis. There are some indications of the optimal protein contents of a solder, and the effects of methylene blue on anastomotic strength. The effects of varying laser power density in vivo have also been described, showing a high rate of thrombosis with laser power over 22.9Wcm-2. However no evidence exists to describe how long the solder remains at the site of the anastomosis. Oz et al reported that the fibrin used in their study had been almost completely removed by 90 days but without objective evidence of solder removal. In order to address the issue of solder re-absorption from the site of an anastomosis we used radio-labelled albumin (I-125) incorporated into methylene blue based solder. This was investigated in both the situation of the patent and thrombosed anastomosis with anastomoses formed at high and low power. Iodine-125 (half life: 60.2 days) was covalently bonded to porcine albumin and mixed with the solder solution. Radio-iodine has been used over many years to determine protein turnover using either I-125 or I-131. Iodine-125 labelled human albumin is regularly used as a radiopharmaceutical tool for the determination of plasma volume. Radio-iodine has the advantages of not affecting protein metabolism and the label is rapidly excreted after metabolic breakdown. Labelling with chromium (Cr-51) causes protein denaturation and is lost from the protein with time. Labelled albumin has been reported in human studies over a 21-day period, with similar results reported by Matthews. Most significantly McFarlane reported a different rate of catabolism of I-131 and I-125 over a 22-day period. The conclusion from this is that the rate of iodine clearance is a good indicator of protein catabolism. In parallel with the surgery a series of blank standards were prepared with a known mass of solder to correct for isotope

  6. Microstructural evolution of eutectic gold-tin solder joints

    NASA Astrophysics Data System (ADS)

    Song, Ho Geon

    Current trends toward miniaturization and the use of lead (Pb)-free solders in electronic packaging present new problems in the reliability of solder joints. This study was performed in order to understand the microstructure and microstructural evolution of small volumes of nominally eutectic Au-Sn solder joints (80Au-20Sn by weight), which gives insight into properties and reliability. The study particularly concentrated on the effects that the joint size and the type of substrate metallization have on both the bulk and interface microstructures of the joints. The systems studied were eutectic Au-Sn on Cu and Cu/electroless Ni/Au and for each system, two sets of sample geometries were used. Eutectic Au-Sn solder joints on Cu have microstructures that are very coarse on the scale of the joint, where the microstructure is strongly affected by the amount of Cu dissolution during reflow process. During aging, steady diffusion of Cu leads to the growth of Cu-rich interfacial intermetallic layers, significant consumption of substrate Cu, and formation of Kirkendall pores along the interface. Thermal cycling of the joints caused decomposition of the thick zeta(Cu)-phase into a fine-grained multiphase microstructure. The microstructures of eutectic Au-Sn solder joints on Cu/electroless Ni/Au are also very coarse due to the dissolution of Au used as a protective layer during soldering. Electroless Ni is shown to effectively act as a diffusion barrier for Cu. The electroless Ni near the interface evolves into a complicated structure due to the interfacial reaction. The solubility characteristics and diffusional behavior of substrate metals into eutectic Au-Sn solder determines the detailed microstructure and microstructural evolution of the ultrafine eutectic Au-Sn joints. Two important things to be noted from the results are as follows: First, the overall microstructures of these joints are very coarse with respect to the size of joint, and hence the properties of the

  7. Experimental Methods in Reduced-gravity Soldering Research

    NASA Technical Reports Server (NTRS)

    Pettegrew, Richard D.; Struk, Peter M.; Watson, John K.; Haylett, Daniel R.

    2002-01-01

    The National Center for Microgravity Research, NASA Glenn Research Center, and NASA Johnson Space Center are conducting an experimental program to explore the influence of reduced gravity environments on the soldering process. An improved understanding of the effects of the acceleration environment is important to application of soldering during current and future human space missions. Solder joint characteristics that are being considered include solder fillet geometry, porosity, and microstructural features. Both through-hole and surface mounted devices are being investigated. This paper focuses on the experimental methodology employed in this project and the results of macroscopic sample examination. The specific soldering process, sample configurations, materials, and equipment were selected to be consistent with those currently on-orbit. Other apparatus was incorporated to meet requirements imposed by operation onboard NASA's KC-135 research aircraft and instrumentation was provided to monitor both the atmospheric and acceleration environments. The contingent of test operators was selected to include both highly skilled technicians and less skilled individuals to provide a population cross-section that would be representative of the skill mix that might be encountered in space mission crews.

  8. Solder creep-fatigue interactions with flexible leaded parts

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.; Wen, L. C.; Mon, G. R.; Jetter, E.

    1992-01-01

    With flexible leaded parts, the solder-joint failure process involves a complex interplay of creep and fatigue mechanisms. To better understand the role of creep in typical multi-hour cyclic loading conditions, a specialized non-linear finite-element creep simulation computer program has been formulated. The numerical algorithm includes the complete part-lead-solder-PWB system, accounting for strain-rate dependence of creep on applied stress and temperature, and the role of the part-lead dimensions and flexibility that determine the total creep deflection (solder strain range) during stress relaxation. The computer program has been used to explore the effects of various solder creep-fatigue parameters such as lead height and stiffness, thermal-cycle test profile, and part/board differential thermal expansion properties. One of the most interesting findings is the strong presence of unidirectional creep-ratcheting that occurs during thermal cycling due to temperature dominated strain-rate effects. To corroborate the solder fatigue model predictions, a number of carefully controlled thermal-cycle tests have been conducted using special bimetallic test boards.

  9. Optical interconnection techniques for Hypercube

    NASA Technical Reports Server (NTRS)

    Johnston, A. R.; Bergman, L. A.; Wu, W. H.

    1988-01-01

    Direct free-space optical interconnection techniques are described for the Hypercube concurrent processor machine using a holographic optical element. Computational requirements and optical constraints on implementation are briefly summarized with regard to topology, power consumption, and available technologies. A hybrid lens/HOE approach is described that can support an eight-dimensional cube of 256 nodes.

  10. Effect of Hold Time on Crack Growth Behavior of Pb-Containing and Pb-Free Solders

    NASA Astrophysics Data System (ADS)

    Fakpan, Kittichai; Otsuka, Yuichi; Mutoh, Yoshiharu; Nagata, Kohsoku

    2012-11-01

    Four types of loading waveforms were adopted to investigate the effect of hold time on crack growth behavior of Sn-37Pb and Sn-3.0Ag-0.5Cu solders: a sinusoidal waveform, triangular waveform, and trapezoidal waveform with hold times of 1 s, 5 s, and 10 s, and a triangular waveform with hold time of 10 s at maximum tensile load. The experimental results showed that the crack growth behavior of both solders tested under sinusoidal and triangular waveforms without any hold time was predominantly cycle dependent. On the other hand, the crack growth behavior of both solders tested under trapezoidal waveforms with hold times of 1 s, 5 s, and 10 s and triangular waveforms with hold time of 10 s was predominantly time dependent. Under cycle-dependent conditions the crack growth data were a function of J-integral range, while under time-dependent conditions the crack growth data were not a function of the creep J-integral range but rather of the C * parameter.

  11. Nano copper based high temperature solder alternative

    NASA Astrophysics Data System (ADS)

    Sharma, Akshay

    Nano Cu an alternative to high temperature solder is developed by the Advance Technological Center at the Lockheed Martin Corporation. A printable paste of Cu nano particles is developed with an ability to fuse at 200°C in reflow oven. After reflow the deposited material has nano crystalline and nano porous structure which affects its properties. Accelerated test are performed on nano Cu deposition having nano porous and nano crystalline structure for assessment and prediction of reliability. Nano Cu assemblies with different bond layer thickness are sheared to calculate the strength of the material and are correlated with the porous and crystalline structure of nano Cu. Thermal and isothermal fatigue test are performed on nano Cu to see the dependency of life on stress and further surface of failed assemblies were observed to determine the type of failure. Creep test at RT are performed to find the type of creep mechanism and how they are affected when subjected to high temperature. TEM, SEM, X-ray, C-SAM and optical microscopy is done on the nano Cu sample for structure and surface analysis.

  12. Creep characterization of solder bumps using nanoindentation

    NASA Astrophysics Data System (ADS)

    Du, Yingjie; Liu, Xiao Hu; Fu, Boshen; Shaw, Thomas M.; Lu, Minhua; Wassick, Thomas A.; Bonilla, Griselda; Lu, Hongbing

    2016-10-01

    Current nanoindentation techniques for the measurement of creep properties are applicable to viscoplastic materials with negligible elastic deformations. A new technique for characterization of creep behavior is needed for situations where the elastic deformation plays a significant role. In this paper, the effect of elastic deformation on the determination of creep parameters using nanoindentation with a self-similar nanoindenter tip is evaluated using finite element analysis (FEA). It is found that the creep exponent measured from nanoindentation without taking into account of the contribution of elastic deformation tends to be higher than the actual value. An effective correction method is developed to consider the elastic deformation in the calculation of creep parameters. FEA shows that this method provides accurate creep exponent. The creep parameters, namely the creep exponent and activation energy, were measured for three types of reflowed solder bumps using the nanoindentation method. The measured parameters were verified using FEA. The results show that the new correction approach allows extraction of creep parameters with precision from nanoindentation data.

  13. Optical interconnections and networks; Proceedings of the Meeting, The Hague, Netherlands, Mar. 14, 15, 1990

    NASA Technical Reports Server (NTRS)

    Bartelt, Hartmut (Editor)

    1990-01-01

    The conference presents papers on interconnections, clock distribution, neural networks, and components and materials. Particular attention is given to a comparison of optical and electrical data interconnections at the board and backplane levels, a wafer-level optical interconnection network layout, an analysis and simulation of photonic switch networks, and the integration of picosecond GaAs photoconductive devices with silicon circuits for optical clocking and interconnects. Consideration is also given to the optical implementation of neural networks, invariance in an optoelectronic implementation of neural networks, and the recording of reversible patterns in polymer lightguides.

  14. An Overview of Surface Finishes and Their Role in Printed Circuit Board Solderability and Solder Joint Performance

    SciTech Connect

    Vianco, P.T.

    1998-10-15

    A overview has been presented on the topic of alternative surface finishes for package I/Os and circuit board features. Aspects of processability and solder joint reliability were described for the following coatings: baseline hot-dipped, plated, and plated-and-fused 100Sn and Sn-Pb coatings; Ni/Au; Pd, Ni/Pd, and Ni/Pd/Au finishes; and the recently marketed immersion Ag coatings. The Ni/Au coatings appear to provide the all-around best option in terms of solderability protection and wire bondability. Nickel/Pal ftishes offer a slightly reduced level of performance in these areas that is most likely due to variable Pd surface conditions. It is necessmy to minimize dissolved Au or Pd contents in the solder material to prevent solder joint embrittlement. Ancillary aspects that included thickness measurement techniques; the importance of finish compatibility with conformal coatings and conductive adhesives; and the need for alternative finishes for the processing of non-Pb bearing solders were discussed.

  15. Effects of Solder Temperature on Pin Through-Hole during Wave Soldering: Thermal-Fluid Structure Interaction Analysis

    PubMed Central

    Abdul Aziz, M. S.; Abdullah, M. Z.; Khor, C. Y.

    2014-01-01

    An efficient simulation technique was proposed to examine the thermal-fluid structure interaction in the effects of solder temperature on pin through-hole during wave soldering. This study investigated the capillary flow behavior as well as the displacement, temperature distribution, and von Mises stress of a pin passed through a solder material. A single pin through-hole connector mounted on a printed circuit board (PCB) was simulated using a 3D model solved by FLUENT. The ABAQUS solver was employed to analyze the pin structure at solder temperatures of 456.15 K (183°C) < T < 643.15 K (370°C). Both solvers were coupled by the real time coupling software and mesh-based parallel code coupling interface during analysis. In addition, an experiment was conducted to measure the temperature difference (ΔT) between the top and the bottom of the pin. Analysis results showed that an increase in temperature increased the structural displacement and the von Mises stress. Filling time exhibited a quadratic relationship to the increment of temperature. The deformation of pin showed a linear correlation to the temperature. The ΔT obtained from the simulation and the experimental method were validated. This study elucidates and clearly illustrates wave soldering for engineers in the PCB assembly industry. PMID:25225638

  16. An Interconnect Sheet Resistance Model Considering CMP Pattern Effects in 45 nm Process

    NASA Astrophysics Data System (ADS)

    Ma, Tianyu; Chen, Lan; Ruan, Wenbiao

    Side effects in Cu interconnect chemical mechanical polishing (CMP) process - dishing and erosion - will both influence chip surface topography and deteriorate interconnect electrical characteristics such as interconnect resistance. In this paper, test chip was designed for measurement of both surface topography and electrical characteristics of Cu interconnect after CMP process. An interconnect sheet resistance model considering dishing and erosion effects is proposed and verified by experimental results. For most test structures, difference between prediction results and measurement results are less than 4%. This model is applicable to other CMP processes in which dishing and erosion are positive or negative, and it can also be easily integrated into state-of-art CMP simulators for accurate interconnect resistance prediction.

  17. Isothermal fatigue of low tin lead based solder

    NASA Astrophysics Data System (ADS)

    Vayman, Semyon; Fine, Morris E.; Jeannotte, Dexter A.

    1988-04-01

    Low tin lead based solder fails by intergranular and/or transgranular modes depending upon experimental conditions. At low frequency and in tests with hold times separation of grains is the main mode of fracture. In the 5 to 100 °C temperature range at high frequency (> 10-2 Hz) and at high total strain range (0.75 pct) the failure mode is mixed transgranular-intergranular; at a low total strain range (0.3 pct) the mode of failure is intergranular. Change in failure mode leads to a bend in the Coffin-Manson plot. Tensile hold time and combined tensile and compressive hold times are found to reduce dramatically the fatigue cycles to failure of this solder. A simple mathematical relation between the fatigue life of the solder and ramp time, tensile, and compressive hold times is developed.

  18. Corrosion Issues in Solder Joint Design and Service

    SciTech Connect

    VIANCO,PAUL T.

    1999-11-24

    Corrosion is an important consideration in the design of a solder joint. It must be addressed with respect to the service environment or, as in the case of soldered conduit, as the nature of the medium being transported within piping or tubing. Galvanic-assisted corrosion is of particular concern, given the fact that solder joints are comprised of different metals or alloy compositions that are in contact with one-another. The (thermodynamic) potential for corrosion to take place in a particular environment requires the availability of the galvanic series for those conditions and which includes the metals or alloys in question. However, the corrosion kinetics, which actually determine the rate of material loss under the specified service conditions, are only available through laboratory evaluations or field data that are found in the existing literature or must be obtained by in-house testing.

  19. Development of alternatives to lead-bearing solders

    SciTech Connect

    Vianco, P.T.

    1993-07-01

    Soldering technology, using tin-lead alloys has had a significant role in the packaging of highly functional, low cost electronic devices. The elimination of lead from all manufactured products, whether through legislation or tax incentives, will impact the electronics community which uses lead-containing solders. In response to these proposed measures, the National Center for Manufacturing Sciences has established a multi-year program involving participants from industry, academia, and the national laboratories with the objective to identify potential replacements for lead-bearing solders. Selection of candidate alloys is based upon the analysis of materials properties, manufacturability, modeling codes for reliability prediction, as well as toxicological properties and resource availability, data developed in the program.

  20. Optical Path Difference Evaluation of Laser-Soldered Optical Components

    NASA Astrophysics Data System (ADS)

    Burkhardt, T.; Hornaff, M.; Burkhardt, D.; Beckert, E.

    2015-12-01

    We present Solderjet Bumping, a laser-based soldering process, as an all inorganic joining technique for optical materials and mechanical support structures. The adhesive-free bonding process enables the low-stress assembly of fragile and sensitive components for advanced optical systems. Our process addresses high demanding applications, e.g. under high energetic radiation (short wavelengths of 280 nm and below and/or high intensities), for vacuum operation, and for harsh environmental conditions. Laser-based soldering allows the low stress assembly of aligned sub-cells as key components for high quality optical systems. The evaluation of the optical path difference in fused silica and the radiation resistant LAK9G15 glass components after soldering and environmental testing shows the potential of the technique.

  1. Process characterization and control of hand-soldered printed wiring assemblies

    SciTech Connect

    Cheray, D.L.; Mandl, R.G.

    1993-09-01

    A designed experiment was conducted to characterize the hand soldering process parameters for manufacturing printed wiring assemblies (PWAs). Component tinning was identified as the most important parameter in hand soldering. After tinning, the soldering iron tip temperature of 700{degrees}F and the choice of operators influence solder joint quality more than any other parameters. Cleaning and flux/flux core have little impact on the quality of the solder joint. The need for component cleaning prior to assembly must be evaluated for each component.

  2. Drinking Water Contamination Due To Lead-based Solder

    NASA Astrophysics Data System (ADS)

    Garcia, N.; Bartelt, E.; Cuff, K. E.

    2004-12-01

    The presence of lead in drinking water creates many health hazards. Exposure to lead-contaminated water can affect the brain, the central nervous system, blood cells, and kidneys, causing such problems as mental retardation, kidney disease, heart disease, stroke, and death. One way in which lead can contaminate our water supply is through the use of lead solder to join pipes. Lead solder was widely used in the past because of its ease of application as well as its low cost. Lead contamination in residential areas has previously been found to be a particularly serious problem in first-draw samples, of water that has sat stagnant in pipes overnight. To investigate the time-dependence of drinking water lead contamination, we analyzed samples taken hourly of water exposed to lead solder. While our preliminary data was insufficient to show more than a rough correlation between time of exposure and lead concentration over short periods (1-3 hours), we were able to confirm that overnight exposure of water to lead-based solder results in the presence high levels of lead. We also investigated other, external factors that previous research has indicated contribute to increased concentrations of lead. Our analysis of samples of lead-exposed water at various pH and temperatures suggests that these factors can be equally significant in terms of their contribution to elevated lead concentration levels. In particular, water that is slightly corrosive appears to severely impact the solubility of lead. As this type of water is common in much of the Northeast United States, the presence of lead-based solder in residential areas there is especially problematic. Although lead-based solder has been banned since the 1980s, it remains a serious concern, and a practical solution still requires further research.

  3. Process for making a multilayer interconnect system

    NASA Technical Reports Server (NTRS)

    Zachry, Clyde L. (Inventor); Niedzwiecke, Andrew J. (Inventor)

    1976-01-01

    A process for making an interconnect system for a multilayer circuit pattern. The interconnect system is formed having minimized through-hole space consumption so as to be suitable for high density, closely meshed circuit patterns.

  4. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  5. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  6. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  7. National Offshore Wind Energy Grid Interconnection Study

    SciTech Connect

    Daniel, John P.; Liu, Shu; Ibanez, Eduardo; Pennock, Ken; Reed, Greg; Hanes, Spencer

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States. A total of 54GW of offshore wind was assumed to be the target for the analyses conducted. A variety of issues are considered including: the anticipated staging of offshore wind; the offshore wind resource availability; offshore wind energy power production profiles; offshore wind variability; present and potential technologies for collection and delivery of offshore wind energy to the onshore grid; potential impacts to existing utility systems most likely to receive large amounts of offshore wind; and regulatory influences on offshore wind development. The technologies considered the reliability of various high-voltage ac (HVAC) and high-voltage dc (HVDC) technology options and configurations. The utility system impacts of GW-scale integration of offshore wind are considered from an operational steady-state perspective and from a regional and national production cost perspective.

  8. Formation of interconnections to microfluidic devices

    DOEpatents

    Matzke, Carolyn M.; Ashby, Carol I. H.; Griego, Leonardo

    2003-07-29

    A method is disclosed to form external interconnections to a microfluidic device for coupling of a fluid or light or both into a microchannel of the device. This method can be used to form optical or fluidic interconnections to microchannels previously formed on a substrate, or to form both the interconnections and microchannels during the same process steps. The optical and fluidic interconnections are formed parallel to the plane of the substrate, and are fluid tight.

  9. Morphology and Pull Strength of Sn-Ag(-Co) Solder Joint with Copper Pad

    NASA Astrophysics Data System (ADS)

    Nishikawa, Hiroshi; Komatsu, Akira; Takemoto, Tadashi

    2007-09-01

    In order to clarify the effect of the addition of Co to the Sn-Ag solder, the formation and growth of an intermetallic compound (IMC) at the interface between Sn-Ag(-Co) solders and a Cu pad were investigated, and the joint strength of the solder with a Cu pad was also evaluated by a bump pull test. Binary Sn-3.5mass%Ag solder was used as the basic solder, and Sn-3.5mass%Ag-xCo solders (x = 0.1 mass%, 0.3 mass%, and 0.5 mass%) were specially prepared as Co-added solders. For the reflow process, specimens were heated in a radiation furnace at 523 K for 60 s. For the aging process, some specimens were then heat-treated in an oil bath at 423 K for 168 h, 504 h, and 1008 h. The results show that the addition of Co to the Sn-Ag solder strongly affected the formation and growth of the IMC at the interface. The results of the pull test clearly show that all solders had similar pull strengths, regardless of the Co addition, although the IMC morphology at the interface of the Sn-Ag-Co solder was quite different from that of the binary Sn-3.5Ag solder.

  10. Creep deformation behavior in eutectic Sn-Ag solder joints using a novel mapping technique

    SciTech Connect

    Lucas, J.P.; Guo, F.; McDougall, J.; Bieler, T.R.; Subramanian, K.N.; Park, J.K.

    1999-11-01

    Creep deformation behavior was measured for 60--100 {micro}m thick solder joints. The solder joints investigated consisted of: (1) non-composite solder joints made with eutectic Sn-Ag solder, and (2) composite solder joints with eutectic Sn-Ag solder containing 20 vol.%, 5 {micro}m diameter in-situ Cu{sub 6}Sn{sub 5} intermetallic reinforcements. All creep testing in this study was carried out at room temperature. Qualitative and quantitative assessment of creep deformation was characterized on the solder joints. Creep deformation was analyzed using a novel mapping technique where a geometrical-regular line pattern was etched over the entire solder joint using excimer laser ablation. During creep, the laser-ablation (LA) pattern becomes distorted due to deformation in the solder joint. By imaging the distortion of laser-ablation patterns using the SEM, actual deformation mapping for the entire solder joint is revealed. The technique involves sequential optical/digital imaging of the deformation versus time history during creep. By tracing and recording the deformation of the LA patterns on the solder over intervals of time, local creep data are obtained in many locations in the joint. This analysis enables global and localized creep shear strains and strain rate to be determined.

  11. Influence of microstructure on fatigue crack growth behavior of Sn-Ag solder interfaces

    NASA Astrophysics Data System (ADS)

    Liu, Pi Lin; Shang, Jian Ku

    2000-05-01

    The relationship between microstructure and fatigue crack growth behavior was examined at Sn-Ag solder interfaces on copper and electroless-nickel metallizations. On copper metallization, the solder interface was lined with a coarse Ag3Sn intermetallic phase in addition to the Cu6Sn5 intermetallic and the adjacent solder alloy contained nodular Ag3Sn phase. This interfacial microstructure was shown to result in inferior fatigue resistance, with the fatigue crack path following the interfacial Ag3Sn intermetallic phase. In contrast, the solder interface on the electroless-nickel metallization was covered with a thin layer of Ni3Sn4 intermetallic phase, and the solder microstructure was composed of fine needles of Ag3Sn phase dispersed in the Sn-rich matrix. This solder interface was found to be significantly more resistant to fatigue than the copper/Sn-Ag solder interface.

  12. 18 CFR 292.306 - Interconnection costs.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 18 Conservation of Power and Water Resources 1 2010-04-01 2010-04-01 false Interconnection costs... § 292.306 Interconnection costs. (a) Obligation to pay. Each qualifying facility shall be obligated to pay any interconnection costs which the State regulatory authority (with respect to any...

  13. Avioptic plug-in interconnection

    NASA Astrophysics Data System (ADS)

    Caserta, Anthony L.; Lijoi, Bruno

    1989-05-01

    A secure interconnection is claimed for optical and avioptic cables located in exposed positions, which often occur on aircraft communications circuits, for connecting those cables into equipment such as circuit boards. In this invention the interconnection for optical fiber cables comprises a connector which is engaged in a receptacle in a mother board provided with optical circuitry. The connector comprises a cuplike body or plug containing a metal sleeve which encases the optical fiber cable such that the cable end is exposed. The mating receptacle comprises a cylindrical shell having its lower end embedded in the mother board. A hole in the receptacle shell wall receives the end of an optical fiber on the optical circuitry of the mother board. The end of the sleeve of the connector fits over the end of the receptacle shell protruding from the mother board. Beam deflection means in the receptacle or on the connector directs light between the fiber optic cable and the optical circuit element of the mother board. Electrical coupling can be incorporated into the interconnection such that the termination can accommodate electrical as well as optical functions.

  14. Neural network Z-plane implementation with very high interconnection rates

    NASA Astrophysics Data System (ADS)

    Carson, John C.

    1990-11-01

    Neural networks offer the potential for a quantum leap in the capabilities of imaging sensor systems. The critical neural network implementation factors are: weighted interconnect between all detector outputs; parallel, linear processing of each detector output; fan-out to multiple (thousands) processing nodes per detector output and the ability to independently change interconnect weights and processor node connections within the detector integration times. For a 128 x 128 pixel detector array, the number of desirable interconnects could be as high as iO per second, compared to the approximately iO rates achieved presently with off-focal plane digital processors. Irvine Sensors Corporation (ISC) has conceived a new way of interconnecting 3-D focal plane readout modules and of laying out their component integrated circuits that appears to fulfill the very high interconnect rate requirements. This concept is described and mterconnectivity and other performance attributes are discussed.

  15. Soldering and brazing safety guide: A handbook on space practice for those involved in soldering and brazing

    NASA Astrophysics Data System (ADS)

    This manual provides those involved in welding and brazing with effective safety procedures for use in performance of their jobs. Hazards exist in four types of general soldering and brazing processes: (1) cleaning; (2) application of flux; (3) application of heat and filler metal; and (4) residue cleaning. Most hazards during those operations can be avoided by using care, proper ventilation, protective clothing and equipment. Specific process hazards for various methods of brazing and soldering are treated. Methods to check ventilation are presented as well as a check of personal hygiene and good maintenance practices are stressed. Several emergency first aid treatments are described.

  16. Studies on in situ particulate reinforced tin-silver composite solders relevant to thermomechanical fatigue issues

    NASA Astrophysics Data System (ADS)

    Choi, Sunglak

    2001-07-01

    Global pressure based on environmental and health concerns regarding the use of Pb-bearing solder has forced the electronics industry to develop Pb-free alternative solders. Eutectic Sn-Ag solder has received much attention as a potential Pb-free candidate to replace Sn-Pb solder. Since introduction of surface mount technology, packaging density increased and the electronic devices became smaller. As a result, solders in electronic modules are forced to function as a mechanical connection as well as electrical contact. Solders are also exposed to very harsh service conditions such as automotive under-the-hood and aerospace applications. Solder joints experience thermomechanical fatigue, i.e. interaction of fatigue and creep, during thermal cycling due to temperature fluctuation in service conditions. Microstructural study on thermomechanical fatigue of the actual eutectic Sn-Ag and Sn-4Ag-0.5Cu solder joints was performed to better understand deformation and damage accumulation occurring during service. Incorporation of reinforcements has been pursued to improve the mechanical and particularly thermomechanical behavior of solders, and their service temperature capability. In-situ Sn-Ag composite solders were developed by incorporating Cu 6Sn5, Ni3Sn4, and FeSn2 particulate reinforcements in the eutectic Sn-Ag solder in an effort to enhance thermomechanical fatigue resistance. In-situ composite solders were investigated on the growth of interfacial intermetallic layer between solder and Cu substrate growth and creep properties. Solder joints exhibited significant deformation and damage on free surface and interior regions during thermomechanical fatigue. Cracks initiated on the free surface of the solder joints and propagated toward interior regions near the substrate of the solder joint. Crack grew along Sn grain boundaries by grain boundary sliding. There was significant residual stress within the solder joint causing more damage. Presence of small amount of Cu

  17. Microstructural Evolution and Mechanical Properties in (AuSn)eut-Cu Interconnections

    NASA Astrophysics Data System (ADS)

    Dong, Hongqun; Vuorinen, Vesa; Laurila, Tomi; Paulasto-Kröckel, Mervi

    2016-10-01

    The interfacial reactions between the widely employed solder Au-20wt.%Sn and the common contact metallizations (e.g. Ni, Cu and Pt) are normally complex and not well determined. In order to identify the proper contactor for Au-20wt.%Sn solder, the present study focuses on (1) rationalizing the interfacial reaction mechanisms of Au-20wt.%Sn|Cu as well as (2) measuring the mechanical properties of individual intermetallics formed at the interface. The evolution of interfacial reaction products were rationalized by using the experimental results in combination with the calculated Au-Cu-Sn phase diagram information. It was found that the growth of the AuCu interfacial intermetallic layer was diffusion-controlled. The diffusion path of Au-20wt.%Sn|Cu at 150°C was proposed. The hardness and indentation modulus of the interfacial reaction products were measured using nanoindentation tests. The results revealed a significant influence of the Cu solubility on the mechanical properties of (Au,Cu)Sn and (Au,Cu)5Sn, i.e. their hardness and contact modulus increased with the increase in the amount of Cu. Furthermore, results obtained here for the Au-20wt.%Sn|Cu joints were compared to those from Au-20wt.%Sn|Ni in order to assess the similarities and differences between these widely used interconnection metallization systems.

  18. Flexible interconnects for fuel cell stacks

    DOEpatents

    Lenz, David J.; Chung, Brandon W.; Pham, Ai Quoc

    2004-11-09

    An interconnect that facilitates electrical connection and mechanical support with minimal mechanical stress for fuel cell stacks. The interconnects are flexible and provide mechanically robust fuel cell stacks with higher stack performance at lower cost. The flexible interconnects replace the prior rigid rib interconnects with flexible "fingers" or contact pads which will accommodate the imperfect flatness of the ceramic fuel cells. Also, the mechanical stress of stacked fuel cells will be smaller due to the flexibility of the fingers. The interconnects can be one-sided or double-sided.

  19. Interconnects for nanoscale MOSFET technology: a review

    NASA Astrophysics Data System (ADS)

    Chaudhry, Amit

    2013-06-01

    In this paper, a review of Cu/low-k, carbon nanotube (CNT), graphene nanoribbon (GNR) and optical based interconnect technologies has been done. Interconnect models, challenges and solutions have also been discussed. Of all the four technologies, CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies, despite some minor drawbacks. It is concluded that beyond 32 nm technology, a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.

  20. Microfabricated structures with electrical isolation and interconnections

    NASA Technical Reports Server (NTRS)

    Clark, William A. (Inventor); Juneau, Thor N. (Inventor); Roessig, Allen W. (Inventor); Lemkin, Mark A. (Inventor)

    2001-01-01

    The invention is directed to a microfabricated device. The device includes a substrate that is etched to define mechanical structures at least some of which are anchored laterally to the remainder of the substrate. Electrical isolation at points where mechanical structures are attached to the substrate is provided by filled isolation trenches. Filled trenches may also be used to electrically isolate structure elements from each other at points where mechanical attachment of structure elements is desired. The performance of microelectromechanical devices is improved by 1) having a high-aspect-ratio between vertical and lateral dimensions of the mechanical elements, 2) integrating electronics on the same substrate as the mechanical elements, 3) good electrical isolation among mechanical elements and circuits except where electrical interconnection is desired.

  1. 28. VIEW OF THE SOLDERING NICHE FORMED WITH BRICKS. THE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    28. VIEW OF THE SOLDERING NICHE FORMED WITH BRICKS. THE BACK OF THE NICHE IS CEMENT FINISHED. THE BOTTOM HAS A 1 INCH THICK ASBESTOS SHELF. THIS PHOTO WAS TAKEN AT THE 3RD FLOOR. - Pacific Telephone & Telegraph Company Building, 1519 Franklin Street, Oakland, Alameda County, CA

  2. A method of damage mechanics analysis for solder material

    SciTech Connect

    Fang, H.E.; Chow, C.L.; Yang, Fan

    1997-06-01

    This paper presents as a method of damage mechanics analysis for solder joint material stressed to extensive plastic deformation. The material chosen for the current work is the 60Sn-40Pb eutectic alloy due to its wide use. The analysis is based on the thermodynamic theory of irreversible processes. With the introduction of a set of internal state variables, known as damage variables, and a damage effect tensor, a damage dissipative potential function is proposed to enable the formulation of the constitutive equations of elasticity and plasticity coupled with damage. The equations of damage evolution are also derived to monitor damage initiation and growth. Before a damage analysis can be performed with a finite element analysis, the mechanical properties of the chosen solder joint material and its damage variables must first be determined. A method of experimental analysis was developed and used to successfully measure the highly strain sensitive 60Sn-40Pb solder material. The measured properties are presented and various characteristics of the solder material are examined and discussed. 7 refs., 8 figs.

  3. A constitutive model for Sn-Pb solder.

    SciTech Connect

    Neilsen, Michael K.; Vianco, Paul Thomas; Boyce, Brad Lee

    2010-10-01

    A unified creep plasticity damage (UCPD) model for Sn-Pb solder is developed in this paper. Stephens and Frear (1999) studied the creep behavior of near-eutectic 60Sn-40Pb solder subjected to low strain rates and found that the inelastic (creep and plastic) strain rate could be accurately described using a hyperbolic Sine function of the applied effective stress. A recently developed high-rate servo-hydraulic method was employed to characterize the temperature and strain-rate dependent stress-strain behavior of eutectic Sn-Pb solder over a wide range of strain rates (10{sup -4} to 10{sup 2} per second). The steady state inelastic strain rate data from these latest experiments were also accurately captured by the hyperbolic Sine equation developed by Stephens and Frear. Thus, this equation was used as the basis for the UCPD model for Sn-Pb solder developed in this paper. Stephens, J.J., and Frear, D.R., Metallurgical and Materials Transactions A, Volume 30A, pp. 1301-1313, May 1999.

  4. Fundamentals of wetting and spreading with emphasis on soldering

    SciTech Connect

    Yost, F.G.

    1991-01-01

    Soldering is often referred to as a mature technology whose fundamentals were established long ago. Yet a multitude of soldering problems persist, not the least of which are related to the wetting and spreading of solder. The Buff-Goodrich approach to thermodynamics of capillarity is utilized in a review of basic wetting principles. These thermodynamics allow a very compact formulation of capillary phenomena which is used to calculate various meniscus shapes and wetting forces. These shapes and forces lend themselves to experimental techniques, such as the sessile drop and the Wilhelmy plate, for measuring useful surface and interfacial energies. The familiar equations of Young, Wilhelmy, and Neumann are all derived with this approach. The force-energy duality of surface energy is discussed and the force method is developed and used to derive the Herring relations for anisotropic surfaces. The importance of contact angle hysteresis which results from surface roughness and chemical inhomogeneity is presented and Young's equation is modified to reflect these ever present effects. Finally, an analysis of wetting with simultaneous metallurigical reaction is given and used to discuss solder wetting phenomena. 60 refs., 13 figs.

  5. Inelastic Strain Analysis of Solder Joint in NASA Fatigue Specimen

    NASA Technical Reports Server (NTRS)

    Dasgupta, Abhijit; Oyan, Chen

    1991-01-01

    The solder fatigue specimen designed by NASA-GSFC/UNISYS is analyzed in order to obtain the inelastic strain history during two different representative temperature cycles specified by UNISYS. In previous reports (dated July 25, 1990, and November 15, 1990), results were presented of the elastic-plastic and creep analysis for delta T = 31 C cycle, respectively. Subsequent results obtained during the current phase, from viscoplastic finite element analysis of the solder fatigue specimen for delta T = 113 C cycle are summarized. Some common information is repeated for self-completeness. Large-deformation continuum formulations in conjunction with a standard linear solid model is utilized for modeling the solder constitutive creep-plasticity behavior. Relevant material properties are obtained from the literature. Strain amplitudes, mean strains, and residual strains (as well as stresses) accumulated due to a representative complete temperature cycle are obtained as a result of this analysis. The partitioning between elastic strains, time-independent inelastic (plastic) strains, and time-dependent inelastic (creep) strains is also explicitly obtained for two representative cycles. Detailed plots are presented for two representative temperature cycles. This information forms an important input for fatigue damage models, when predicting the fatigue life of solder joints under thermal cycling

  6. Recycling of lead solder dross, Generated from PCB manufacturing

    NASA Astrophysics Data System (ADS)

    Lucheva, Biserka; Tsonev, Tsonio; Iliev, Peter

    2011-08-01

    The main purpose of this work is to analyze lead solder dross, a waste product from manufacturing of printed circuit boards by wave soldering, and to develop an effective and environmentally sound technology for its recycling. A methodology for determination of the content and chemical composition of the metal and oxide phases of the dross is developed. Two methods for recycling of lead solder dross were examined—carbothermal reduction and recycling using boron-containing substances. The influence of various factors on the metal yield was studied and the optimal parameters of the recycling process are defined. The comparison between them under the same parameters-temperature and retention time, showed that recycling of dross with a mixture of borax and boric acid in a 1:2 ratio provides higher metal yield (93%). The recycling of this hazardous waste under developed technology gets glassy slag and solder, which after correction of the chemical composition can be used again for production of PCB.

  7. Aqueous cleaning of flux residue from solder joints. Final report

    SciTech Connect

    Krska, C.M.

    1992-08-01

    Solder joints have traditionally been cleaned using chlorinated or fluorinated solvents. This study addressed alternate processing. One process involved using a saponifier/water solution to remove rosin flux residues; the other process involved using a water-soluble flux and water to remove the residues. Although both processes were satisfactory, the water-soluble flux with water cleaning proved to be the best.

  8. Aqueous cleaning of flux residue from solder joints

    SciTech Connect

    Krska, C.M.

    1992-08-01

    Solder joints have traditionally been cleaned using chlorinated or fluorinated solvents. This study addressed alternate processing. One process involved using a saponifier/water solution to remove rosin flux residues; the other process involved using a water-soluble flux and water to remove the residues. Although both processes were satisfactory, the water-soluble flux with water cleaning proved to be the best.

  9. End-to-end small bowel anastomosis by temperature controlled CO2 laser soldering and an albumin stent: a feasibility study

    NASA Astrophysics Data System (ADS)

    Simhon, David; Kopelman, Doron; Hashmonai, Moshe; Vasserman, Irena; Dror, Michael; Vasilyev, Tamar; Halpern, Marissa; Kariv, Naam; Katzir, Abraham

    2004-07-01

    Introduction: A feasibility study of small intestinal end to end anastomosis was performed in a rabbit model using temperature controlled CO2 laser system and an albumin stent. Compared with standard suturing or clipping, this method does not introduce foreign materials to the repaired wound and therefore, may lead to better and faster wound healing of the anastomotic site. Methods: Transected rabbits small intestines were either laser soldered using 47% bovine serum albumin and intraluminal albumin stent or served as controls in which conventional continuous two-layer end to end anastomosis was performed manually. The integrity of the anastomosis was investigated at the 14th postoperative day. Results: Postoperative course in both treatments was uneventful. The sutured group presented signs of partial bowel obstruction. Macroscopically, no signs of intraluminal fluid leakage were observed in both treatments. Yet, laser soldered intestinal anastomoses demonstrated significant superiority with respect to adhesions and narrowing of the intestinal lumen. Serial histological examinations revealed better wound healing characteristics of the laser soldered anastomotic site. Conclusion: Laser soldering of intestinal end to end anastomosis provide a faster surgical procedure, compared to standard suture technique, with better wound healing results. It is expected that this technique may be adopted in the future for minimal invasive surgeries.

  10. Electromigration Behaviors of Cu Reinforced Sn-3.5Ag Composite Solder Joints

    NASA Astrophysics Data System (ADS)

    Wang, Yan; Han, Jing; Ma, Limin; Zuo, Yong; Guo, Fu

    2016-12-01

    The composite approach, by incorporating small amounts of reinforcement particles in the solder matrix, has proven to be one of the effective ways to improve the reliability of solder joints. The effects of Cu addition on electromigration were investigated in this study by incorporating 2% volume fraction Cu particles into Sn-3.5Ag eutectic solder paste by the in situ process. The one-dimensional solder joints, designed to prevent the current crowding effect, were stressed under a constant current density of 104 A/cm2 at room temperature, and the temperature of the sample could reach 105 ± 5°C due to the Joule heating effect. Doping 2 vol.% Cu was found to retard the electromigration phenomenon effectively. After electric current stressing for 528 h, the growth rate of an interfacial intermetallic compound (IMC) layer at the anode decreased 73% in contrast to that of Sn-3.5Ag solder joints, and the IMC layer at the cathode was almost unchanged. The polarization effect of Cu reinforced composite solder joints was also apparently mitigated. In addition, the surface damage of the composite solder joints was relieved by incorporating 2 vol.% Cu particles. Compared to Sn-3.5Ag solder joints, which had protruded Cu6Sn5 and wrinkles of Sn-solder matrix on the surface, the solder joints with Cu addition had a more even surface.

  11. Analysis of vertical interconnection measurements

    NASA Astrophysics Data System (ADS)

    Karner, F. A.

    The paper examines the predominance of the effects that measurement points, geometries, and alignment have on the interpretation of measured values of contact resistance of vertical interconnections in multilayer electronic packages. It is concluded that: (1) four-terminal measurements for contact resistance are misleading; (2) measured values are mostly a function of structural geometry; (3) simulation in two dimensions and subsequent synthesis is a good predictor in three-dimensional simulations; (4) the dual-contact site is a good alignment aid and contact-resistance indicator; and (5) the measured resistance value should only be used as a reference, and not as an indicator of good or bad.

  12. Double interconnection fuel cell array

    DOEpatents

    Draper, Robert; Zymboly, Gregory E.

    1993-01-01

    A fuel cell array (10) is made, containing number of tubular, elongated fuel cells (12) which are placed next to each other in rows (A, B, C, D), where each cell contains inner electrodes (14) and outer electrodes (18 and 18'), with solid electrolyte (16 and 16') between the electrodes, where the electrolyte and outer electrode are discontinuous, having two portions, and providing at least two opposed discontinuities which contain at least two oppositely opposed interconnections (20 and 20') contacting the inner electrode (14), each cell (12) having only three metallic felt electrical connectors (22) which contact surrounding cells, where each row is electrically connected to the other.

  13. Effect of ultrasonic vibration time on the Cu/Sn-Ag-Cu/Cu joint soldered by low-power-high-frequency ultrasonic-assisted reflow soldering.

    PubMed

    Tan, Ai Ting; Tan, Ai Wen; Yusof, Farazila

    2017-01-01

    Techniques to improve solder joint reliability have been the recent research focus in the electronic packaging industry. In this study, Cu/SAC305/Cu solder joints were fabricated using a low-power high-frequency ultrasonic-assisted reflow soldering approach where non-ultrasonic-treated samples were served as control sample. The effect of ultrasonic vibration (USV) time (within 6s) on the solder joint properties was characterized systematically. Results showed that the solder matrix microstructure was refined at 1.5s of USV, but coarsen when the USV time reached 3s and above. The solder matrix hardness increased when the solder matrix was refined, but decreased when the solder matrix coarsened. The interfacial intermetallic compound (IMC) layer thickness was found to decrease with increasing USV time, except for the USV-treated sample with 1.5s. This is attributed to the insufficient USV time during the reflow stage and consequently accelerated the Cu dissolution at the joint interface during the post-ultrasonic reflow stage. All the USV-treated samples possessed higher shear strength than the control sample due to the USV-induced-degassing effect. The shear strength of the USV-treated sample with 6s was the lowest among the USV-treated samples due to the formation of plate-like Ag3Sn that may act as the crack initiation site.

  14. Reflow soldering and isothermal solid-state aging of Sn-Ag eutectic solder on Au/Ni surface finish

    NASA Astrophysics Data System (ADS)

    Liu, C. M.; Ho, C. E.; Chen, W. T.; Kao, C. R.

    2001-09-01

    The reaction between the eutectic Sn-3.5Ag solder and the Au/Ni surface finish during reflow as well as during isothermal aging was studied. The Au layer was electroplated and had a thickness of the one μm. The peak reflow temperature was fixed at 250 C while the reflow time was varied between 10 sec and one h. Samples that went through 90 sec reflow time were then subjected to 160 C isothermal aging for up to 875 h. It was found that during reflow the Au layer reacted very quickly with the solder to form AuSn4. One μm of Au layer was consumed in less than 10 sec. As the aging time increased, AuSn4 grains began to separate themselves from the Ni layer at the roots of the grains and started to fall into the solder. When, the reflow time reached 30 sec, all the Au intermetallic head left the interface, and Ni3Sn4 started, to form at the interface. The Ni3Sn4 growth rate followed linear kinetics initially (<240 sec), but the growth rate slowed down afterward. During the isothermal aging, only a small amount of (AuxNi1-x)Sn4 resettled back to the interface, and a continuous (Au0.45Ni0.55)Sn4 layer did not form at the interface, unlike the case for the Sn-37Pb solder. This is an important advantage for Sn-3.5 Ag over Sn-37Pb because a continuous (Au0.45Ni0.55)Sn4 layer inevitably will weaken a solder joint. Our observation indicated that many (AuxNi1-x)Sn4 particles were trapped by the Ag3Sn particles, and were hindered from resettling back to the interface.

  15. Estimation of relative rate of copper dissolution in wave soldering and through-hole rework process by designing an experiment for soldering parameters and PCB features

    NASA Astrophysics Data System (ADS)

    Nair, Vineethkumar R.

    The thesis details the study of influence of factors such as surface finish of PCB, copper content in PCB barrel, PCB thickness, type of solder alloy, type and process parameters of through-hole soldering process in determining the rates of copper dissolution in different through-hole soldering processes. The research was designed to conduct experiment in two phases. The first phase was to measure the copper dissolution that occurs during machine-based wave soldering processes and analyze the factors influencing it. The second phase was to measure the copper dissolution that occurs during a solder pot rework process and analyze the factors influencing it. The results from the experiment are used to identify the significance and magnitude of influence that each of the factors has on the rate of copper dissolution. These measurements are further used to estimate the rates of copper dissolution during through-hole rework process.

  16. Compact Interconnection Networks Based on Quantum Dots

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

    2003-01-01

    Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary

  17. 3D FEM Simulations of Drop Test Reliability on 3D-WLP: Effects of Solder Reflow Residual Stress and Molding Resin Parameters

    NASA Astrophysics Data System (ADS)

    Belhenini, Soufyane; Tougui, Abdellah; Bouchou, Abdelhake; Mohan, Ranganathan; Dosseul, Franck

    2014-01-01

    Numerous three-dimensional (3D) packaging technologies are currently used for 3D integration. 3D-wafer level package (3D-WLP) appears to be a way to keep increasing the density of the microelectronic components. The reliability of 3D components has to be evaluated on mechanical demonstrators with daisy chains before real production. Numerical modeling is acknowledged as a very efficient tool for design optimization. In this paper, 3D finite-elements calculations are carried out to analyze the effects of molding resin's mechanical properties and thickness on the 3D component's dynamic response under drop loading conditions. Residual stress generated by solder reflow is also discussed. The influences of residual stresses on the numerical estimation of the component behavior during drop loading are studied. Solder reflow residual stresses have an impact on solder plastic strain and die equivalent stress calculations. We have compared the result of two numerical drop test models. Stress-free initial conduction is introduced for the first model. Solder reflow residual stresses are considered as the initial condition for the second drop test model. Quantitative and qualitative comparisons are carried out to show the effect of residual stress in drop test calculations. For the effect of molding resin thickness on the component behavior under drop loading, the stress-free initial condition is considered. The effect of the molding resin's thickness on critical area location is discussed. The solder bump maximum plastic shear strain and the silicon die maximum equivalent stress are used as reliability criteria. Numerical submodeling techniques are used to increase calculation accuracy. Numerical results have contributed to the design optimization of the 3D-WLP component.

  18. Pre-tinning and flux considerations on the reliability of solder surface

    SciTech Connect

    Sunwoo, A.J. ); Morris, J.W. Jr. ); Lucey, G.K. )

    1991-07-01

    The kinetics of wetting were studied on several different prepared surfaces of copper (Cu) to simulate the microstructure observed in pre-tinned Cu-clad printed circuit boards. The results illustrate the effectiveness of pre-tinning in maintaining the solderability of Cu surfaces. Pre-tinning with Pb-rich solder (95Pb-5Sn) is particularly effective since solderability is preserved even after a relatively long aging treatment. On the other hand, pre-tinning with eutectic solder risks the loss of solderability during aging or baking due to surface exposure of an {var epsilon}-phase intermetallic with poor wetting properties. The results also confirm the presence of carbon in pre-tinned specimens due to the use of flux. The effect of carbon on solderability is not yet known. 13 refs., 8 figs., 1 tab.

  19. Interconnect fatigue design for terrestrial photovoltaic modules

    NASA Technical Reports Server (NTRS)

    Mon, G. R.; Moore, D. M.; Ross, R. G., Jr.

    1982-01-01

    The results of comprehensive investigation of interconnect fatigue that has led to the definition of useful reliability-design and life-prediction algorithms are presented. Experimental data indicate that the classical strain-cycle (fatigue) curve for the interconnect material is a good model of mean interconnect fatigue performance, but it fails to account for the broad statistical scatter, which is critical to reliability prediction. To fill this shortcoming the classical fatigue curve is combined with experimental cumulative interconnect failure rate data to yield statistical fatigue curves (having failure probability as a parameter) which enable (1) the prediction of cumulative interconnect failures during the design life of an array field, and (2) the unambiguous--ie., quantitative--interpretation of data from field-service qualification (accelerated thermal cycling) tests. Optimal interconnect cost-reliability design algorithms are derived based on minimizing the cost of energy over the design life of the array field.

  20. Cascade solar cell having conductive interconnects

    DOEpatents

    Borden, Peter G.; Saxena, Ram R.

    1982-10-26

    Direct ohmic contact between the cells in an epitaxially grown cascade solar cell is obtained by means of conductive interconnects formed through grooves etched intermittently in the upper cell. The base of the upper cell is directly connected by the conductive interconnects to the emitter of the bottom cell. The conductive interconnects preferably terminate on a ledge formed in the base of the upper cell.

  1. Alternating-current induced thermal fatigue of gold interconnects with nanometer-scale thickness and width

    NASA Astrophysics Data System (ADS)

    Sun, Lijuan; Ling, Xue; Li, Xide

    2011-10-01

    With dramatic reduction in sizes of microelectronic devices, the characteristic width and thickness of interconnects in large-scale integrated circuits have reached nanometer scale. Thermal fatigue damage of so small interconnects has attracted more and more attentions. In this work, thermal fatigue of Au interconnects, 35 nm thick and 0.1-5 μm wide, is investigated by applying various alternating current densities to generate cycling temperature and strain in them. A multi-probe measuring system is installed in a scanning electron microscope and a probe-type temperature sensor is for the first time introduced into the system for real-time measuring the temperatures on the pads of the tested interconnects. A one-dimensional heat conduction equation, which uses measured temperatures on the pads as boundary conditions and includes a term of heat dissipation through the interface between the interconnect and the oxidized silicon substrate, is proposed to calculate the time-resolved temperature distribution along the Au interconnects. The measured fatigue lifetimes are presented versus current density and thermal cyclic strain, and the results show that narrower Au lines are more reliable. The failure mechanism of those Au interconnects differs from what is observed in thick interconnects with relatively larger grain size. Topography change caused by localized plasticity on the less-constrained surfaces of the interconnects have not been observed. Instead, grain growing and reorienting due to local temperature varying appear, and grain boundary migration and mergence take place during high temperature fatigue in such thin and narrow interconnects. These results seem to reflect a strain-induced boundary migration mechanism, and the damage morphology also suggests that fatigue of the interconnects with decreased grain size and film thickness is controlled by diffusive mechanisms and interface properties rather than by dislocation glide. Open circuit eventually took

  2. A study on the reliability of indium solder die bonding of high power semiconductor lasers

    NASA Astrophysics Data System (ADS)

    Liu, Xingsheng; Davis, Ronald W.; Hughes, Lawrence C.; Rasmussen, Michael H.; Bhat, Rajaram; Zah, Chung-En; Stradling, Jim

    2006-07-01

    High power semiconductor lasers have found increased applications. Indium solder is one of the most widely used solders in high power laser die bonding. Indium solder has some advantages in laser die bonding. It also has some concerns, however, especially in terms of reliability. In this paper, the reliability of indium solder die bonding of high power broad area semiconductor lasers was studied. It was found that indium solder bonded lasers have much shorter lifetime than AuSn solder bonded devices. Catastrophic degradation was observed in indium solder bonded lasers. Nondestructive optical and acoustic microscopy was conducted during the lifetime testing to monitor the failure process and destructive failure analysis was performed after the lasers failed. It was found that the sudden failure was caused by electromigration of indium solder at the high testing current of up to 7A. It was shown that voids were created and gradually enlarged by indium solder electromigration, which caused local heating near the facets of the laser. The local heating induced catastrophic optical mirror damage (COMD) of the lasers. It was discussed that current crowding, localized high temperature, and large temperature gradient contributed to the fast indium solder electromigration. It was observed that some bright pattern structures appeared on the front facet of the indium solder bonded lasers after the devices failed and the bright patterns grew and spread upon further testing. Failure analysis showed that the bright pattern structure apparent on the front facet was due to crystallization of the TiOx material of the front facet coating as a result of overheating during lifetime testing. It was concluded that indium solder is not suitable for high power laser applications due to electromigration at high current densities and high temperatures.

  3. Detecting nonuniformity in small welds and solder seams using optical correlation and electronic processing.

    PubMed

    Wagner, J W

    1981-10-15

    Using holographic matched filtering and electronic processing, small variations in surface displacement along the seam of a hermetic microcircuit package can be detected when the seam is stressed. Destructive analysis of a solder-sealed package reveals a strong correlation between optical signal variations and nonuniformity of solder adhesion and wetting along the seam. The technique promises potential application as a means of nondestructively inspecting for flaws in small welded or soldered seams.

  4. Interfacial reaction of Sn-based solder joint in the package system

    NASA Astrophysics Data System (ADS)

    Gu, Huandi

    In this thesis, I report a study on the effect of the solder size on intermetallic layer formation by comparing the morphology change and growth rate of two different size solder joint aged at a same temperature for different aging time. The layer thickness and microstructure were analyzed using scanning electron microscopy (SEM). Photoshop was used to measure the thickness of intermetallic compound. Two different size of solder joints with composition of Sn-Ag-Cu (305) were used.

  5. Compact models for nanophotonic structures and on-chip interconnects

    NASA Astrophysics Data System (ADS)

    Alam, Mehboob

    Over the last few years, scaling in deep submicron technologies has shifted the paradigm from device-dominated to interconnect-dominated design methodology. Consequently, there is an increasing interest towards the miniaturization of the guiding medium in nanoscale integrated circuits by exploring plasmon-based waveguides to alleviate the scaling issues associated with today's copper interconnect. In this thesis, we seek short and long-term solutions of on-chip interconnect by developing accurate compact models of on-chip interconnects and impedance characterization of nanophotonic structures. The developed system models are compact and accurate over the operating frequency range and the adopted approach have provided many critical insights and produced many important results. This thesis first presents a new modeling strategy that represents the nanostructure by its equivalent impedance. By applying either quasistatic approximation or separately solving for voltage and current for dominant mode, we reduce the field problem to a circuit problem. The impedance expressed in terms of circuit components is dependent on the material constant as well as the operating frequency. The modeling methodology is successfully applied to nanoparticles and oscillating nanosphere. The proposed model characterizes plasmon resonance in these nanostructures, thereby providing basic building block to develop spice models of complex plasmon-based waveguide for sub-wavelength propagation. We also presented several techniques to develop compact models of on-chip interconnects and passive components for accurate estimation of power, noise and delay of high speed integrated circuits. The automated method generates reduced order models that are accurate across either a narrow or a wide-range of frequencies. The proposed methods are based on Krylov subspace method with interpolation points dynamically selected using either spline based algorithm or discrete wavelet transform. Narrow and

  6. Visualizing interconnections among climate risks

    NASA Astrophysics Data System (ADS)

    Tanaka, K.; Yokohata, T.; Nishina, K.; Takahashi, K.; Emori, S.; Kiguchi, M.; Iseri, Y.; Honda, Y.; Okada, M.; Masaki, Y.; Yamamoto, A.; Shigemitsu, M.; Yoshimori, M.; Sueyoshi, T.; Hanasaki, N.; Ito, A.; Sakurai, G.; Iizumi, T.; Nishimori, M.; Lim, W. H.; Miyazaki, C.; Kanae, S.; Oki, T.

    2015-12-01

    It is now widely recognized that climate change is affecting various sectors of the world. Climate change impact on one sector may spread out to other sectors including those seemingly remote, which we call "interconnections of climate risks". While a number of climate risks have been identified in the Intergovernmental Panel on Climate Change (IPCC) Fifth Assessment Report (AR5), there has been no attempt to explore their interconnections comprehensively. Here we present a first and most exhaustive visualization of climate risks drawn based on a systematic literature survey. Our risk network diagrams depict that changes in the climate system impact natural capitals (terrestrial water, crop, and agricultural land) as well as social infrastructures, influencing the socio-economic system and ultimately our access to food, water, and energy. Our findings suggest the importance of incorporating climate risk interconnections into impact and vulnerability assessments and call into question the widely used damage function approaches, which address a limited number of climate change impacts in isolation. Furthermore, the diagram is useful to educate decision makers, stakeholders, and general public about cascading risks that can be triggered by the climate change. Socio-economic activities today are becoming increasingly more inter-dependent because of the rapid technological progress, urbanization, and the globalization among others. Equally complex is the ecosystem that is susceptible to climate change, which comprises interwoven processes affecting one another. In the context of climate change, a number of climate risks have been identified and classified according to regions and sectors. These reports, however, did not fully address the inter-relations among risks because of the complexity inherent in this issue. Climate risks may ripple through sectors in the present inter-dependent world, posing a challenge ahead of us to maintain the resilience of the system. It is

  7. Modeling and experimental characterization of electromigration in interconnect trees

    NASA Astrophysics Data System (ADS)

    Thompson, C. V.; Hau-Riege, S. P.; Andleigh, V. K.

    1999-11-01

    Most modeling and experimental characterization of interconnect reliability is focussed on simple straight lines terminating at pads or vias. However, laid-out integrated circuits often have interconnects with junctions and wide-to-narrow transitions. In carrying out circuit-level reliability assessments it is important to be able to assess the reliability of these more complex shapes, generally referred to as `trees.' An interconnect tree consists of continuously connected high-conductivity metal within one layer of metallization. Trees terminate at diffusion barriers at vias and contacts, and, in the general case, can have more than one terminating branch when they include junctions. We have extended the understanding of `immortality' demonstrated and analyzed for straight stud-to-stud lines, to trees of arbitrary complexity. This leads to a hierarchical approach for identifying immortal trees for specific circuit layouts and models for operation. To complete a circuit-level-reliability analysis, it is also necessary to estimate the lifetimes of the mortal trees. We have developed simulation tools that allow modeling of stress evolution and failure in arbitrarily complex trees. We are testing our models and simulations through comparisons with experiments on simple trees, such as lines broken into two segments with different currents in each segment. Models, simulations and early experimental results on the reliability of interconnect trees are shown to be consistent.

  8. Interdiffusion analysis of the soldering reactions in Sn-3.5Ag/Cu couples

    NASA Astrophysics Data System (ADS)

    Bae, K. S.; Kim, S. J.

    2001-11-01

    Extensive microstructural and kinetic studies on the formation and growth of the intermetallics of Sn-rich solder/Cu couples have been reported. However, experimental data on the interdiffusion mechanisms during soldering reactions are limited and in conflict. The interdiffusion processes for soldering of Sn-3.5Ag alloy/Cu couples were investigated by using the Cr-evaporated surface as a reference line. At the beginning of soldering, Cu was observed to outdiffuse to the molten Sn-3.5Ag alloy until saturation, and the Sn-Ag solder dissolved with Cu collapsed below the reference line. As a result, the scallop-shaped Cu6Sn5 intermetallic compound was formed at the newly-formed Sn-Ag-Cu solder/Cu interface below the original Cu surface. When the soldered joint was reflowed at the lower temperature to suppress the Cu dissolution, the Cu6Sn5/Cu interface moved into the Cu substrate. Therefore, Sn is the dominant diffusing species for the intermetallic formation during the soldering process, although the extensive Cu dissolution occurs at the early stage of soldering.

  9. Wettability of electroless Ni in the under bump metallurgy with lead free solder

    NASA Astrophysics Data System (ADS)

    Young, Bi-Lian; Duh, Jenq-Gong; Chiou, Bi-Shiou

    2001-05-01

    This study investigates the wettability of several lead-free solders, including Sn, Sn-Ag, and Sn-Bi, on electroless Ni (EN) with various phosphorus content. The role of phosphorus on solder wettability is studied. Microstructure evolution in the lead-free solder/EN joint is investigated with the aid of electron probe microanalyzer (EPMA) to relate metallurgical reactions between the solder and the EN. The SN solder exhibits better wettability on EN, while the Si-Bi solder has a larger contact angle. Wettability degrades as the phosphorus content in EN decreases. The dependence of wetting angle on the phosphorous content can be attributed to the surface roughness and density of EN, along with the interfacial reaction between the solders and EN. An EPMA analysis reveals the presence of a Sn-Bi-Ni-P solid solution at the interface of solder/EN joints due to the interdiffusion of major constituent Ni and Sn. The interaction zone of the solid solution increases with increasing temperature. Wettability of Pb-free solders on EN degrades with the presence of NiO due to oxidation or the existence of Ni3P due to precipitation after annealing. For an adequate wetting behavior in the Sn (Sn-Bi, Sn-Ag)/EN joint, EN deposited with phosphorus contents in the range of 9 to 12 wt% is suggested.

  10. High-power semiconductor laser array packaged on microchannel cooler using gold-tin soldering technology

    NASA Astrophysics Data System (ADS)

    Wang, Jingwei; Kang, Lijun; Zhang, Pu; Nie, Zhiqiang; Li, Xiaoning; Xiong, Lingling; Liu, Xingsheng

    2012-03-01

    High power semiconductor laser arrays have found increased applications in many fields. In this work, a hard soldering microchannel cooler (HSMCC) technology was developed for packaging high power diode laser array. Numerical simulations of the thermal behavior characteristics of hard solder and indium solder MCC-packaged diode lasers were conducted and analyzed. Based on the simulated results, a series of high power HSMCC packaged diode laser arrays were fabricated and characterized. The test and statistical results indicated that under the same output power the HSMCC packaged laser bar has lower smile and high reliability in comparison with the conventional copper MCC packaged laser bar using indium soldering technology.

  11. Backplane photonic interconnect modules with optical jumpers

    NASA Astrophysics Data System (ADS)

    Glebov, Alexei L.; Lee, Michael G.; Yokouchi, Kishio

    2005-03-01

    Prototypes of optical interconnect (OI) modules for backplane applications are presented. The transceivers attached to the linecards E/O convert the signals that are passed to and from the backplane by optical jumpers terminated with MTP-type connectors. The connectors plug into adaptors attached to the backplane and the microlens arrays mounted in the adaptors couple the light between the fibers and waveguides. Planar polymer channel waveguides with 30-50 μm cross-sections route the optical signals across the board with propagation losses as low as 0.05 dB/cm @ 850 nm. The 45¦-tapered integrated micromirrors reflect the light in and out of the waveguide plane with the loss of 0.8 dB per mirror. The connector displacement measurements indicate that the adaptor lateral assembly accuracy can be at least +/-10 μm for the excess loss not exceeding 1 dB. Insertion losses of the test modules with integrated waveguides, 45¦ mirrors, and pluggable optical jumper connectors are about 5 dB. Eye diagrams at 10.7 Gb/s have typical width and height of 70 ps and 400 mV, respectively, and jitter of about 20 ps.

  12. A solder sealing method for paraffin-filled microcavities

    NASA Astrophysics Data System (ADS)

    Nguyen, Hugo; Bejhed, Johan; Köhler, Johan; Thornell, Greger

    2006-11-01

    Demonstrated and investigated here is a method to seal microfluidic systems by soldering. As a particularly difficult case of growing importance, the sealing of openings contaminated with paraffin wax was studied. Solder paste, screen printed on a metallized silicon substrate, was melted locally through application of 6.5-10 V to a 5 Ω copper film resistor for a few seconds and was found able to drive an intermediate layer of paraffin away and seal a 0.2 mm diameter circular via by wetting a surrounding copper pad. Although verified to be robust, the process did result in failing seals on excessive heating because of consumption of the pads. Correctly performed, the technique provided a seal at least withstanding a pressure of 8 bar for 8 h at 85 °C.

  13. Automated inspection of solder joints for surface mount technology

    NASA Technical Reports Server (NTRS)

    Savage, Robert M.; Park, Hyun Soo; Fan, Mark S.

    1993-01-01

    Researchers at NASA/GSFC evaluated various automated inspection systems (AIS) technologies using test boards with known defects in surface mount solder joints. These boards were complex and included almost every type of surface mount device typical of critical assemblies used for space flight applications: X-ray radiography; X-ray laminography; Ultrasonic Imaging; Optical Imaging; Laser Imaging; and Infrared Inspection. Vendors, representative of the different technologies, inspected the test boards with their particular machine. The results of the evaluation showed limitations of AIS. Furthermore, none of the AIS technologies evaluated proved to meet all of the inspection criteria for use in high-reliability applications. It was found that certain inspection systems could supplement but not replace manual inspection for low-volume, high-reliability, surface mount solder joints.

  14. Constitutive modeling of viscoplastic damage in solder material

    SciTech Connect

    WEI,YONG; CHOW,C.L.; NEILSEN,MICHAEL K.; FANG,HUEI ELIOT

    2000-04-17

    This paper presents a constitutive modeling of viscoplastic damage in 63Sn-37Pb solder material taking into account the effects of microstructural change in grain coarsening. Based on the theory of damage mechanics, a two-scalar damage model is developed by introducing the damage variables and the free energy equivalence principle. An inelastic potential function based on the concept of inelastic damage energy release rate is proposed and used to derive an inelastic damage evolution equation. The validation of the model is carried out for the viscoplastic material by predicting monotonic tensile behavior and tensile creep curves at different temperatures. The softening behavior of the material under monotonic tension loading can be characterized with the model. The results demonstrate adequately the validity of the proposed viscoplastic constitutive modeling for the solder material.

  15. Solder joint fatigue analysis under low temperature Martian conditions

    NASA Technical Reports Server (NTRS)

    Tudryn, Carissa

    2006-01-01

    Electronics, without requiring heater power or enclosure in a centralized 'warm electronics box,' will need to survive mean surface temperatures of -120 degrees Celsius to +20 degrees Celsius for an extended Martian mission and an operational temperature up to 85 degrees Celsisus. Since these electronics will need to survive extended cycles under these conditions, fatigue is a significant concern. The solder joint reliability of connectors on a printed wiring board was investigated.

  16. Lead poisoning from lead-soldered electric kettles.

    PubMed Central

    Ng, R.; Martin, D. J.

    1977-01-01

    Lead poisoning occurred in two infants, causing lead encephalopathy in one but no symptoms in the other. Both infants had been fed a formula prepared with water boiled in a lead-soldered electric kettle. The diagnosis was suggested by dense metaphyseal bands in radiographs, illustrating the importance of careful examination of "routine" radiographs, particularly in asymptomatic infants. Images FIG. 1A FIG. 1B FIG. 1C FIG. 2 FIG. 3 PMID:837317

  17. Infrared Detection of Faulty Solder Joints. Phase 2.2.

    DTIC Science & Technology

    1982-03-01

    Determinations 18 3.1.6 Softening Point Determinations 24 3.2 Damage Prevention on Laminates 26 - 3.3 Laser/thermal Testing Through Conformal Coatings...possibility was conceived and implemented. The feasibility of testing solder joints covered by a conformal coat- ing was confirmed. Several...efficacy of the testing method if it had to be carried out in the presence of a conformal coating. Approximately 1,000 feed-through and lap-joints were

  18. Morphology and Shear Strength of Lead-Free Solder Joints with Sn3.0Ag0.5Cu Solder Paste Reinforced with Ceramic Nanoparticles

    NASA Astrophysics Data System (ADS)

    Yakymovych, A.; Plevachuk, Yu.; Švec, P.; Švec, P.; Janičkovič, D.; Šebo, P.; Beronská, N.; Roshanghias, A.; Ipser, H.

    2016-12-01

    To date, additions of different oxide nanoparticles is one of the most widespread procedures to improve the mechanical properties of metals and metal alloys. This research deals with the effect of minor ceramic nanoparticle additions (SiO2, TiO2 and ZrO2) on the microstructure and mechanical properties of Cu/solder/Cu joints. The reinforced Sn3.0Ag0.5Cu (SAC305) solder alloy with 0.5 wt.% and 1.0 wt.% of ceramic nanoparticles was prepared through mechanically stirring. The microstructure of as-solidified Cu/solder/Cu joints was studied using scanning electron microscopy. The additions of ceramic nanoparticles suppressed the growth of the intermetallic compound layer Cu6Sn5 at the interface solder/Cu and improved the microstructure of the joints. Furthermore, measurements of mechanical properties showed improved shear strength of Cu/composite solder/Cu joints compared to joints with unreinforced solder. This fact related to all investigated ceramic nanoinclusions and should be attributed to the adsorption of nanoparticles on the grain surface during solidification. However, this effect is less pronounced on increasing the nanoinclusion content from 0.5 wt.% to 1.0 wt.% due to agglomeration of nanoparticles. Moreover, a comparison analysis showed that the most beneficial influence was obtained by minor additions of SiO2 nanoparticles into the SAC305 solder alloy.

  19. Laser-assisted solder closure of bronchial stumps

    NASA Astrophysics Data System (ADS)

    Oz, Mehmet C.; Williams, Matthew R.; Moscarelli, Richard D.; Kaynar, Murat; Fras, Christian I.; Libutti, Steven K.; Smith, Hillary; Setton, Adrianne J.; Treat, Michael R.; Nowygrod, Roman

    1992-06-01

    Broncho-pleural fistula is a difficult clinical problem without a simple solution. Laser-assisted solder techniques potentially offer a means to precisely fix tissue glues into the fistulae through a bronchoscopic approach. Using a canine model, secondary bronchi were sealed with cryoprecipitate made from solvent/detergent treated plasma (treated to inactivate membrane enveloped virus) mixed with indocyanine green (absorption 805 nm). Diode laser energy (emission 808 nm, 7.3 W/cm2) was applied to the solder until desiccation was observed. Leakage pressures ranged between 18 - 86 mmHg with a mean of 46 +/- 24 mmHg. Laser-assisted solder techniques provide a reliably strong seal over leaking bronchial stumps and use of dye enhancement prevents undesired collateral thermal injury to surrounding bronchial tissue. Solvent/detergent plasma, prepared by methods shown to inactivate large quantities of HIV, HBV, and HCV, is an effective source of cyroprecipitate and should allow widespread use of pooled human material in a clinical setting.

  20. Laser Direct Routing for High Density Interconnects

    NASA Astrophysics Data System (ADS)

    Moreno, Wilfrido Alejandro

    The laser restructuring of electronic circuits fabricated using standard Very Large Scale Integration (VLSI) process techniques, is an excellent alternative that allows low-cost quick turnaround production with full circuit similarity between the Laser Restructured prototype and the customized product for mass production. Laser Restructurable VLSI (LRVLSI) would allow design engineers the capability to interconnect cells that implement generic logic functions and signal processing schemes to achieve a higher level of design complexity. LRVLSI of a particular circuit at the wafer or packaged chip level is accomplished using an integrated computer controlled laser system to create low electrical resistance links between conductors and to cut conductor lines. An infrastructure for rapid prototyping and quick turnaround using Laser Restructuring of VLSI circuits was developed to meet three main parallel objectives: to pursue research on novel interconnect technologies using LRVLSI, to develop the capability of operating in a quick turnaround mode, and to maintain standardization and compatibility with commercially available equipment for feasible technology transfer. The system is to possess a high degree of flexibility, high data quality, total controllability, full documentation, short downtime, a user-friendly operator interface, automation, historical record keeping, and error indication and logging. A specially designed chip "SLINKY" was used as the test vehicle for the complete characterization of the Laser Restructuring system. With the use of Design of Experiment techniques the Lateral Diffused Link (LDL), developed originally at MIT Lincoln Laboratories, was completely characterized and for the first time a set of optimum process parameters was obtained. With the designed infrastructure fully operational, the priority objective was the search for a substitute for the high resistance, high current leakage to substrate, and relatively low density Lateral

  1. Interconnect fatigue design for terrestrial photovoltaic modules

    SciTech Connect

    Mon, G. R.; Moore, D. M.; Ross, Jr., R. G.

    1982-03-01

    Fatigue of solar cell electrical interconnects due to thermal cycling has historically been a major failure mechanism in photovoltaic arrays; the results of a comprehensive investigation of interconnect fatigue that has led to the definition of useful reliability-design and life-prediction algorithms are presented. Experimental data gathered in this study indicate that the classical strain-cycle (fatigue) curve for the interconnect material is a good model of mean interconnect fatigue performance, but it fails to account for the broad statistical scatter, which is critical to reliability prediction. To fill this shortcoming the classical fatigue curve is combined with experimental cumulative interconnect failure rate data to yield statistical fatigue curves (having failure probability as a parameter) which enable: (1) the prediction of cumulative interconnect failures during the design life of an array field; and (2) the unambiguous - i.e., quantitative - interpretation of data from field-service qualification (accelerated thermal cycling) tests. Optimal interconnect cost-reliability design algorithms are derived based on minimizing the cost of energy over the design life of the array field. This procedure yields not only the minimum break-even cost of delivered energy, but also the required degree of interconnect redundancy and an estimate of array power degradation during the design life of the array field. The usefulness of the design algorithms is demonstrated with realistic examples of design optimization, prediction, and service qualification testing.

  2. 14 CFR 29.674 - Interconnected controls.

    Code of Federal Regulations, 2012 CFR

    2012-01-01

    ... 14 Aeronautics and Space 1 2012-01-01 2012-01-01 false Interconnected controls. 29.674 Section 29... AIRWORTHINESS STANDARDS: TRANSPORT CATEGORY ROTORCRAFT Design and Construction Control Systems § 29.674 Interconnected controls. Each primary flight control system must provide for safe flight and landing and...

  3. 14 CFR 27.674 - Interconnected controls.

    Code of Federal Regulations, 2012 CFR

    2012-01-01

    ... 14 Aeronautics and Space 1 2012-01-01 2012-01-01 false Interconnected controls. 27.674 Section 27... AIRWORTHINESS STANDARDS: NORMAL CATEGORY ROTORCRAFT Design and Construction Control Systems § 27.674 Interconnected controls. Each primary flight control system must provide for safe flight and landing and...

  4. 47 CFR 101.519 - Interconnection.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 47 Telecommunication 5 2010-10-01 2010-10-01 false Interconnection. 101.519 Section 101.519 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) SAFETY AND SPECIAL RADIO SERVICES FIXED MICROWAVE SERVICES 24 GHz Service and Digital Electronic Message Service § 101.519 Interconnection. (a) All...

  5. 14 CFR 23.701 - Flap interconnection.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Flap interconnection. 23.701 Section 23.701 Aeronautics and Space FEDERAL AVIATION ADMINISTRATION, DEPARTMENT OF TRANSPORTATION AIRCRAFT AIRWORTHINESS... Systems § 23.701 Flap interconnection. (a) The main wing flaps and related movable surfaces as a...

  6. Government Open Systems Interconnection: Profile in Progress.

    ERIC Educational Resources Information Center

    Mills, Kevin L.

    1990-01-01

    Describes the emergence of Open Systems Interconnection (OSI) as it relates to the U.S. Government Open Systems Interconnection Profile (GOSIP); defines GOSIP; and speculates about its future. Challenges facing GOSIP that are related to test policies and procedures, strategic and tactical planning, additional functionality, and international…

  7. 47 CFR 90.477 - Interconnected systems.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ...) Applicants for new land stations to be interconnected with the public switched telephone network must... switched telephone network only after modifying their license. See § 1.929 of this chapter. In all cases a..., 896-901 MHz, and 935-940 MHz, interconnection with the public switched telephone network is...

  8. 47 CFR 90.477 - Interconnected systems.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ...) Applicants for new land stations to be interconnected with the public switched telephone network must... operation. This restriction will not apply to trunked systems or on any channel assigned exclusively to one... interconnection device. When land stations subject to this part are multiple licensed or shared by...

  9. 47 CFR 101.519 - Interconnection.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 47 Telecommunication 5 2014-10-01 2014-10-01 false Interconnection. 101.519 Section 101.519 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) SAFETY AND SPECIAL RADIO SERVICES FIXED MICROWAVE SERVICES 24 GHz Service and Digital Electronic Message Service § 101.519 Interconnection. (a) All...

  10. 47 CFR 101.519 - Interconnection.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 47 Telecommunication 5 2011-10-01 2011-10-01 false Interconnection. 101.519 Section 101.519 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) SAFETY AND SPECIAL RADIO SERVICES FIXED MICROWAVE SERVICES 24 GHz Service and Digital Electronic Message Service § 101.519 Interconnection. (a) All...

  11. 47 CFR 101.519 - Interconnection.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 47 Telecommunication 5 2013-10-01 2013-10-01 false Interconnection. 101.519 Section 101.519 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) SAFETY AND SPECIAL RADIO SERVICES FIXED MICROWAVE SERVICES 24 GHz Service and Digital Electronic Message Service § 101.519 Interconnection. (a) All...

  12. 47 CFR 101.519 - Interconnection.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 47 Telecommunication 5 2012-10-01 2012-10-01 false Interconnection. 101.519 Section 101.519 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) SAFETY AND SPECIAL RADIO SERVICES FIXED MICROWAVE SERVICES 24 GHz Service and Digital Electronic Message Service § 101.519 Interconnection. (a) All...

  13. Updating Technical Screens for PV Interconnection: Preprint

    SciTech Connect

    Coddington, M.; Ellis, A.; Lynn, K.; Razon, A.; Key, T.; Kroposki, B.; Mather, B.; Hill, R.; Nicole, K.; Smith, J.

    2012-08-01

    Solar photovoltaics (PV) is the dominant type of distributed generation (DG) technology interconnected to electric distribution systems in the United States, and deployment of PV systems continues to increase rapidly. Considering the rapid growth and widespread deployment of PV systems in United States electric distribution grids, it is important that interconnection procedures be as streamlined as possible to avoid unnecessary interconnection studies, costs, and delays. Because many PV interconnection applications involve high penetration scenarios, the process needs to allow for a sufficiently rigorous technical evaluation to identify and address possible system impacts. Existing interconnection procedures are designed to balance the need for efficiency and technical rigor for all DG. However, there is an implicit expectation that those procedures will be updated over time in order to remain relevant with respect to evolving standards, technology, and practical experience. Modifications to interconnection screens and procedures must focus on maintaining or improving safety and reliability, as well as accurately allocating costs and improving expediency of the interconnection process. This paper evaluates the origins and usefulness of the capacity penetration screen, offers potential short-term solutions which could effectively allow fast-track interconnection to many PV system applications, and considers longer-term solutions for increasing PV deployment levels in a safe and reliable manner while reducing or eliminating the emphasis on the penetration screen.

  14. Durability of Metallic Interconnects and Protective Coatings

    SciTech Connect

    Yang, Zhenguo; Stevenson, Jeffry W.

    2009-12-15

    To build up a useful voltage, a number of solid oxide fuel cells (SOFCs) are electrically connected into series in a stack via interconnects, which are placed between adjacent cells. In addition to functioning as a bi-polar electrical connector, the interconnect also acts as a separator plate that separates the fuel at the anode side of one cell from the air at the cathode side on an adjacent cell. During SOFC operation at the high temperatures, the interconnects are thus simultaneously exposed to the oxidizing air at one side and a reducing fuel that can be either hydrogen or hydrocarbon at the other. Besides, they are in contact with adjacent components, such as electrodes or electrical contacts, seals, etc. With steady reduction in SOFC operating temperatures into the low or intermediate range 600-850oC, oxidation resistant alloys are often used to construct interconnects. However, the metallic interconnects may degrade via interactions at their interfaces with surrounding environments or adjacent components, potentially affecting the stability and performance of interconnects and the SOFC stacks. Thus protection layers are applied to metallic interconnects that also intend to mitigate or prevent chromium migration into cells and the cell poisoning. This chapter provides a comprehensive review of materials for metallic interconnects, their degradation and coating protection.

  15. High density interconnects for aerospace applications

    NASA Astrophysics Data System (ADS)

    Menozzi, Gaetan

    1988-08-01

    The technologies of large scale interconnectors were evaluated for chip and wire or leadless ceramic chip carriers. The packaging and interconnecting structures are either ceramic multilayer with multilayer thick film and cofired multilayer ceramic. Test results are given, technology status and next generation interconnects are described, and aerospace applications are presented.

  16. Lateral buckling and mechanical stretchability of fractal interconnects partially bonded onto an elastomeric substrate

    SciTech Connect

    Fu, Haoran; Xu, Sheng; Rogers, John A. E-mail: jrogers@illinois.edu; Xu, Renxiao; Huang, Yonggang E-mail: jrogers@illinois.edu; Jiang, Jianqun; Zhang, Yihui

    2015-03-02

    Fractal-inspired designs for interconnects that join rigid, functional devices can ensure mechanical integrity in stretchable electronic systems under extreme deformations. The bonding configuration of such interconnects with the elastomer substrate is crucial to the resulting deformation modes, and therefore the stretchability of the entire system. In this study, both theoretical and experimental analyses are performed for postbuckling of fractal serpentine interconnects partially bonded to the substrate. The deformation behaviors and the elastic stretchability of such systems are systematically explored, and compared to counterparts that are not bonded at all to the substrate.

  17. Modeling interconnect corners under double patterning misalignment

    NASA Astrophysics Data System (ADS)

    Hyun, Daijoon; Shin, Youngsoo

    2016-03-01

    Publisher's Note: This paper, originally published on March 16th, was replaced with a corrected/revised version on March 28th. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance. Interconnect corners should accurately reflect the effect of misalingment in LELE double patterning process. Misalignment is usually considered separately from interconnect structure variations; this incurs too much pessimism and fails to reflect a large increase in total capacitance for asymmetric interconnect structure. We model interconnect corners by taking account of misalignment in conjunction with interconnect structure variations; we also characterize misalignment effect more accurately by handling metal pitch at both sides of a target metal independently. Identifying metal space at both sides of a target metal.

  18. Soldered contact and current risetime effects on negative polarity wire array Z pinches

    NASA Astrophysics Data System (ADS)

    Chalenski, D. A.; Kusse, B. R.; Greenly, J. B.

    2009-08-01

    The experimental results described in this paper were motivated by earlier, low current, single wire experiments. In these experiments, single 10-25 μm diameter wires were driven by 1-5 kA current pulses with variable dI /dt from 5 to 60 A/ns. The amount of energy deposited in the wires, the expansion rate, and expansion uniformity that occurred before a plasma induced voltage collapse were found to depend on the polarity, dI /dt, and the quality of the contacts between the wires and the electrodes. This paper reports the results of experiments with cylindrical wire arrays driven by Cornell Beam Research Accelerator (COBRA) [J. B. Greenly, J. D. Douglas, D. A. Hammer et al., Rev. Sci. Instrum. 79, 073501 (2008)] current pulses that reached 1 MA. The pulse lengths were varied from 100 to 200 ns. These larger current pulses drove the wires of the array through the initiation phase studied in the single wire experiments and through ablation and Z-pinch implosion to stagnation on the cylindrical axis of the array. Regardless of the current pulse length, the COBRA dI /dt per wire during initiation reached approximately 175 A/ns and resistive voltage breakdown occurred at ˜13 ns. Wire-electrode contacts were modified by soldering the cathode ends of the wires to the brass electrode. With the 100 ns COBRA pulse, voltage monitor data suggested that soldering produced a smaller radius pinch, but bolometer data showed that this did not affect the total energy emitted from the array compared to nonsoldered contacts. With the 200 ns COBRA pulse and soldered contacts, the bolometer data showed an average of 69% increase in time integrated x-ray emission and the photoconducting detector data showed an increase in x-ray power and yield compared with nonsoldered contacts. Under these same conditions the four-frame extreme ultraviolet images showed a more pronounced "Christmas tree" effect at the cathode.

  19. Analysis of a short beam with application to solder joints: could larger stand-off heights relieve stress?

    NASA Astrophysics Data System (ADS)

    Suhir, Ephraim

    2015-08-01

    Physically meaningful and easy-to-use analytical (mathematical) stress model is developed for a short beam with clamped and known-in-advance offset ends. The analysis is limited to elastic deformations. While the classical Timoshenko short-beam theory seeks the beam's deflection caused by the combined bending and shear deformations for the given loading, an inverse problem is considered here: the lateral force is sought for the given ends offset. In short beams this force is larger than in long beams, since, in order to achieve the given displacement (offset), the applied force has to overcome both bending and shear resistance of the beam. It is envisioned that short beams could adequately mimic the state of stress in solder joint interconnections, including ball-grid-array (BGA) systems, with large, compared to conventional joints, stand-off heights. When the package/printed-circuit-board (PCB) assembly is subjected to the change in temperature, the thermal expansion (contraction) mismatch of the package and the PCB results in an easily predictable relative displacement (offset) of the ends of the solder joint. This offset can be determined from the known external thermal mismatch strain (determined as the product of the difference in the coefficients of thermal expansion and the change in temperature) and the position of the joint with respect to the mid-cross-section of the assembly. The maximum normal and shearing stresses could be viewed as suitable criteria of the beam's (joint's) material long-term reliability. It is shown that these stresses can be brought down by employing beam-like joints, i.e., joints with an increased stand-off height compared to conventional joints. It is imperative, of course, that, if such joints are employed, there is still enough interfacial real estate, so that the BGA bonding strength is not compromised. On the other hand, owing to the lower stress level, reliability assurance might be much less of a challenge than in the case of

  20. Reliability of High I/O High Density CCGA Interconnect Electronic Packages under Extreme Thermal Environment

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni

    2012-01-01

    This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions. Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performances, compatibility with standard surface-mount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, payload electronics, and flight avionics. As these packages tend to have less solder joint strain relief than leaded packages or more strain relief over lead-less chip carrier packages, the reliability of CCGA packages is very important for short-term and long-term deep space missions. We have employed high density CCGA 1152 and 1272 daisy chained electronic packages in this preliminary reliability study. Each package is divided into several daisy-chained sections. The physical dimensions of CCGA1152 package is 35 mm x 35 mm with a 34 x 34 array of columns with a 1 mm pitch. The dimension of the CCGA1272 package is 37.5 mm x 37.5 mm with a 36 x 36 array with a 1 mm pitch. The columns are made up of 80% Pb/20%Sn material. CCGA interconnect electronic package printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging techniques. The assembled CCGA boards were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space missions. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling. This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non

  1. Reusable, adhesiveless and arrayed in-plane microfluidic interconnects

    NASA Astrophysics Data System (ADS)

    Lo, R.; Meng, E.

    2011-05-01

    A reusable, arrayed interconnect capable of providing multiple simultaneous connections to and from a microfluidic device in an in-plane manner without the use of adhesives is presented. This method uses a 'pin-and-socket' design in which an SU-8 anchor houses multiple polydimethysiloxane septa (the socket) that each receive a syringe needle (the pin). A needle array containing multiple commercially available 33G (203 µm outer diameter) needles (up to eight) spaced either 2.54 or 1 mm (center-to-center) pierces the septa to access the microfluidic device interior. Finite element modeling and photoelastic stress experiments were used to determine the stress distribution during needle insertion; these results guided the SU-8 septa housing and septa design. The impact of needle diameter, needle tip style, insertion rate and number of needles on pre-puncture, post-puncture and removal forces was characterized. Pressurized connections to SU-8 channel systems withstood up to 62 kPa of pressurized water and maintained 25 kPa of pressurized water for over 24 h. The successful integration and functionality of the interconnect design with surface micromachined Parylene C microchannels was verified using Rhodamine B dye. Dual septa systems to access a single microchannel were demonstrated. Arrayed interconnects were compatible with integrated microfluidic systems featuring electrochemical sensors and actuators.

  2. Multimode siloxane polymer components for optical interconnects

    NASA Astrophysics Data System (ADS)

    Bamiedakis, Nikolaos; Beals, Joseph, IV; Penty, Richard V.; White, Ian H.; DeGroot, Jon v., Jr.; Clapp, Terry V.; De Shazer, David

    2009-02-01

    This paper presents an overview of multimode waveguides and waveguide components formed from siloxane polymer materials which are suitable for use in optical interconnection applications. The components can be cost-effectively integrated onto conventional PCBs and offer increased functionality in optical transmission. The multimode waveguides exhibit low loss (0.04 dB/cm at 850 nm) and low crosstalk (< -30 dB) performance, large alignment tolerances and negligible mode mixing for short waveguide lengths. Error-free data transmission at 10 Gb/s over 1.4 m long waveguides has been successfully demonstrated. Waveguide crossings exhibit very low excess losses, below 0.01 dB/crossing, and excellent crosstalk performance. Low loss is obtained for waveguide bends with radii of curvature larger than 8 mm and 6 mm for 90° and S-shaped bends respectively. High-uniformity splitting is achieved with multimode Y-splitters even in the presence of input misalignments. Y-combiners are shown to benefit from the multimode nature of the waveguides allowing low loss combining (4 dB for an 8×1 device). A large range of power splitting ratios between 30% and 75% is achieved with multimode coupler devices. Examples of system applications benefiting from the use of these components are briefly presented including a terabit capacity optical backplane, a radio-over-fibre multicasting system and a SCM passive optical network.

  3. Interconnected Cavernous Structure of Bacterial Fruiting Bodies

    PubMed Central

    Harvey, Cameron W.; Du, Huijing; Xu, Zhiliang; Kaiser, Dale; Aranson, Igor; Alber, Mark

    2012-01-01

    The formation of spore-filled fruiting bodies by myxobacteria is a fascinating case of multicellular self-organization by bacteria. The organization of Myxococcus xanthus into fruiting bodies has long been studied not only as an important example of collective motion of bacteria, but also as a simplified model for developmental morphogenesis. Sporulation within the nascent fruiting body requires signaling between moving cells in order that the rod-shaped self-propelled cells differentiate into spores at the appropriate time. Probing the three-dimensional structure of myxobacteria fruiting bodies has previously presented a challenge due to limitations of different imaging methods. A new technique using Infrared Optical Coherence Tomography (OCT) revealed previously unknown details of the internal structure of M. xanthus fruiting bodies consisting of interconnected pockets of relative high and low spore density regions. To make sense of the experimentally observed structure, modeling and computer simulations were used to test a hypothesized mechanism that could produce high-density pockets of spores. The mechanism consists of self-propelled cells aligning with each other and signaling by end-to-end contact to coordinate the process of differentiation resulting in a pattern of clusters observed in the experiment. The integration of novel OCT experimental techniques with computational simulations can provide new insight into the mechanisms that can give rise to the pattern formation seen in other biological systems such as dictyostelids, social amoeba known to form multicellular aggregates observed as slugs under starvation conditions. PMID:23300427

  4. Adaptive optical interconnects: the ADDAPT project

    NASA Astrophysics Data System (ADS)

    Henker, Ronny; Pliva, Jan; Khafaji, Mahdi; Ellinger, Frank; Toifl, Thomas; Offrein, Bert; Cevrero, Alessandro; Oezkaya, Ilter; Seifried, Marc; Ledentsov, Nikolay; Kropp, Joerg-R.; Shchukin, Vitaly; Zoldak, Martin; Halmo, Leos; Turkiewicz, Jaroslaw; Meredith, Wyn; Eddie, Iain; Georgiades, Michael; Charalambides, Savvas; Duis, Jeroen; van Leeuwen, Pieter

    2015-09-01

    Existing optical networks are driven by dynamic user and application demands but operate statically at their maximum performance. Thus, optical links do not offer much adaptability and are not very energy-efficient. In this paper a novel approach of implementing performance and power adaptivity from system down to optical device, electrical circuit and transistor level is proposed. Depending on the actual data load, the number of activated link paths and individual device parameters like bandwidth, clock rate, modulation format and gain are adapted to enable lowering the components supply power. This enables flexible energy-efficient optical transmission links which pave the way for massive reductions of CO2 emission and operating costs in data center and high performance computing applications. Within the FP7 research project Adaptive Data and Power Aware Transceivers for Optical Communications (ADDAPT) dynamic high-speed energy-efficient transceiver subsystems are developed for short-range optical interconnects taking up new adaptive technologies and methods. The research of eight partners from industry, research and education spanning seven European countries includes the investigation of several adaptive control types and algorithms, the development of a full transceiver system, the design and fabrication of optical components and integrated circuits as well as the development of high-speed, low loss packaging solutions. This paper describes and discusses the idea of ADDAPT and provides an overview about the latest research results in this field.

  5. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  6. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  7. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  8. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  9. The automated system for technological process of spacecraft's waveguide paths soldering

    NASA Astrophysics Data System (ADS)

    Tynchenko, V. S.; Murygin, A. V.; Emilova, O. A.; Bocharov, A. N.; Laptenok, V. D.

    2016-11-01

    The paper solves the problem of automated process control of space vehicles waveguide paths soldering by means of induction heating. The peculiarities of the induction soldering process are analyzed and necessity of information-control system automation is identified. The developed automated system makes the control of the product heating process, by varying the power supplied to the inductor, on the basis of information about the soldering zone temperature, and stabilizing the temperature in a narrow range above the melting point of the solder but below the melting point of the waveguide. This allows the soldering process automating to improve the quality of the waveguides and eliminate burn-troughs. The article shows a block diagram of a software system consisting of five modules, and describes the main algorithm of its work. Also there is a description of the waveguide paths automated soldering system operation, for explaining the basic functions and limitations of the system. The developed software allows setting of the measurement equipment, setting and changing parameters of the soldering process, as well as view graphs of temperatures recorded by the system. There is shown the results of experimental studies that prove high quality of soldering process control and the system applicability to the tasks of automation.

  10. New multicomponent solder alloys of low melting pointfor low-cost commercial electronic assembly

    NASA Astrophysics Data System (ADS)

    Al-Ganainy, G. S.; Sakr, M. S.

    2003-09-01

    The requirements of the telecommunications, automobile, electronics and aircraft industries for non-toxic solders with melting points close to that of near-eutectic Pb-Sn alloys has led to the development of new Sn-Zn-In solder alloys. Differential thermal analysis (DTA) shows melting points of 198, 195, 190 and 185 +/- 2 °C for the alloys Sn-9Zn, Sn-9Zn-2In, Sn-9Zn-4In and Sn-9Zn-6In, respectively. An equation that fits the data relating the melting point to the In content in the solders is derived. The X-ray diffraction patterns are analyzed to determine the phases that exist in each solder. The stress-strain curves are studied in the temperature range from 90 to 130 °C for all the solders except for those that contain 4 wt% of In, where the temperature range continues to 150 °C. The work-hardening parameters, y (the yield stress), f (the fracture stress), and the parabolic work-hardening coefficient X, increase with increasing indium content in the solders at all working temperatures. They decrease with increasing working temperature for each solder, and show two relaxation stages only for the Sn-9Zn-4In solder around a temperature of 120 °C. (

  11. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  12. Dural reconstruction by fascia using a temperature-controlled CO2 laser soldering system

    NASA Astrophysics Data System (ADS)

    Forer, Boaz; Vasilyev, Tamar; Brosh, Tamar; Kariv, Naam; Gil, Ziv; Fliss, Dan M.; Katzir, Abraham

    2005-04-01

    Conventional methods for dura repair are normally based on sutures or stitches. These methods have several disadvantages: (1) The dura is often brittle, and the standard procedures are difficult and time consuming. (2) The seal is leaky. (3) The introduction of a foreign body (e.g. sutures) may cause an inflammatory response. In order to overcome these difficulties we used a temperature controlled fiber optic based CO2 laser soldering system. In a set of in vitro experiments we generated a hole of diameter 10 mm in the dura of a pig corpse, covered the hole with a segment of fascia, and soldered the fascia to the edges of the hole, using 47% bovine albumin as a solder. The soldering was carried out spot by spot, and each spot was heated to 65° C for 3-6 seconds. The soldered dura was removed and the burst pressure of the soldered patch was measured. The average value for microscopic muscular side soldering was 194 mm Hg. This is much higher than the maximal physiological pressure of the CSF fluid in the brain, which is 15 mm Hg. In a set of in vivo experiments, fascia patches were soldered on holes in five farm pigs. The long term results of these experiments were very promising. In conclusion, we have developed an advanced technique for dural reconstruction, which will find important clinical applications.

  13. EPRI PEAC Corp.: Certification Model Program and Interconnection Agreement Tools

    SciTech Connect

    Not Available

    2003-10-01

    Summarizes the work of EPRI PEAC Corp., under contract to DOE's Distribution and Interconnection R&D, to develop a certification model program and interconnection agreement tools to support the interconnection of distributed energy resources.

  14. 78 FR 29672 - Small Generator Interconnection Agreements and Procedures

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-05-21

    ... Energy Regulatory Commission 18 CFR Part 35 Small Generator Interconnection Agreements and Procedures... Generator Interconnection Procedures (SGIP) and pro forma Small Generator Interconnection Agreement (SGIA..., 2013, the Commission issued an order in the above- referenced docket. Small Generator...

  15. Modeling and Simulation - The Effects of Grain Coarsening on Local Stresses and Strains in Solder Microstructure

    SciTech Connect

    Chanchani, R.

    1999-01-21

    A critical issue in the long-term reliability of solder connections used in electronic packages is the joint failure during thermal cycling. Presently in most finite element analysis to predict the solder joint fatigue failures, solder is assumed as a homogeneous single-phase metal. However in the last decade, several metallurgical studies have shown that solder microstructure may have a role in early solder joint failures (ref 1). Investigators have observed (ref 1) that solder microstructure coarsens in local bands during aging and during thermal cycle fatigue. In a failed solder joint, the fatigue cracks are found in these bands of coarse grains. It is speculated that the grain coarsening increases the local strains within the microstructure, thereby increasing the likelihood for a crack to initiate. The objective of this study is to model and simulate the effect of grain coarsening on local stresses and strains. During solidification of eutectic Pb/Sn solder, two types of microstructure form, namely lamellar and equiaxed. In this study, I have developed a computer code to generate both types of microstructures of varying grain coarseness. This code is incorporated into the finite element (FE) code that analyzes the local stresses and strains within the computer-generated microstructure. The FE code, specifically developed for this study, uses an algorithm involving the sparse matrix and iterative solver. This code on a typical single-processor machine will allow the analyst to use over 1 million degrees of freedom. For higher number of degrees of freedom, we have also developed a code to run on a parallel machine using message passing interface. The data reported in this paper were obtained using the single-processor code. The solder microstructure, if assumed to be homogeneous single phase, has gradual variation in local stresses and strains. In 2-phase solder, von mises stresses and strains are heterogeneously distributed. In general, the maximum von mises

  16. Mapping of interconnection of climate risks

    NASA Astrophysics Data System (ADS)

    Yokohata, Tokuta; Tanaka, Katsumasa; Nishina, Kazuya; Takanashi, Kiyoshi; Emori, Seita; Kiguchi, Masashi; Iseri, Yoshihiko; Honda, Yasushi; Okada, Masashi; Masaki, Yoshimitsu; Yamamoto, Akitomo; Shigemitsu, Masahito; Yoshimori, Masakazu; Sueyoshi, Tetsuo; Iwase, Kenta; Hanasaki, Naota; Ito, Akihiko; Sakurai, Gen; Iizumi, Toshichika; Oki, Taikan

    2015-04-01

    Anthropogenic climate change possibly causes various impacts on human society and ecosystem. Here, we call possible damages or benefits caused by the future climate change as "climate risks". Many climate risks are closely interconnected with each other by direct cause-effect relationship. In this study, the major climate risks are comprehensively summarized based on the survey of studies in the literature using IPCC AR5 etc, and their cause-effect relationship are visualized by a "network diagram". This research is conducted by the collaboration between the experts of various fields, such as water, energy, agriculture, health, society, and eco-system under the project called ICA-RUS (Integrated Climate Assessment - Risks, Uncertainties and Society). First, the climate risks are classified into 9 categories (water, energy, food, health, disaster, industry, society, ecosystem, and tipping elements). Second, researchers of these fields in our project survey the research articles, and pick up items of climate risks, and possible cause-effect relationship between the risk items. A long list of the climate risks is summarized into ~130, and that of possible cause-effect relationship between the risk items is summarized into ~300, because the network diagram would be illegible if the number of the risk items and cause-effect relationship is too large. Here, we only consider the risks that could occur if climate mitigation policies are not conducted. Finally, the chain of climate risks is visualized by creating a "network diagram" based on a network graph theory (Fruchtman & Reingold algorithm). Through the analysis of network diagram, we find that climate risks at various sectors are closely related. For example, the decrease in the precipitation under the global climate change possibly causes the decrease in river runoff and the decrease in soil moisture, which causes the changes in crop production. The changes in crop production can have an impact on society by

  17. The effects of long-term storage on the solderability of immersion silver coatings.

    SciTech Connect

    Buttry, R. Wayne; Lopez, Edwin Paul; Martin, Joseph; Vianco, Paul Thomas; Lucero, Samuel J.; Rejent, Jerome Andrew

    2006-04-01

    The solderability of an immersion Ag finish was evaluated after the exposure of test specimens to a Battelle Class II environment, which accelerates the storage conditions of light industrial surroundings. The solderability metric was the contact angle, (?C), as determined by the meniscometer/wetting balance technique. Auger surface and depth profile analyses were utilized to identify changes in the coating chemistry. The solderability test results indicate that there was no appreciable loss in solderability when the immersion Ag coated coupons were packaged in vapor phase corrosion (VPC) inhibitor bags and/or inhibitor bags with VPC inhibitor paper and aged for 8 hours, 1 week or 2 weeks in the Battelle Class II environment. An increase in surface carbon concentration after aging did not appear to significantly affect solderability.

  18. Bonding nature of rare-earth-containing lead-free solders

    NASA Astrophysics Data System (ADS)

    Ramirez, Ainissa G.; Mavoori, Hareesh; Jin, Sungho

    2002-01-01

    The ability of rare-earth-containing lead-free solders to wet and bond to silica was investigated. Small additions of Lu (0.5-2 wt. %) added to eutectic Sn-Ag or Au-Sn solder render it directly solderable to a silicon oxide surface. The bonding is attributed to the migration of the rare-earth element to the solder-silica interface for chemical reaction and the creation of an interfacial layer that contains a rare-earth oxide. It was found that additions of rare-earth materials did not significantly modify the solidification microstructure or the melting point. Such oxide-bondable solders can be useful for assembly of various optical communication devices.

  19. Complex of automated equipment and technologies for waveguides soldering using induction heating

    NASA Astrophysics Data System (ADS)

    Murygin, A. V.; Tynchenko, V. S.; Laptenok, V. D.; Emilova, O. A.; Bocharov, A. N.

    2017-02-01

    The article deals with the problem of designing complex automated equipment for soldering waveguides based on induction heating technology. A theoretical analysis of the problem, allowing to form a model of the «inductor-waveguide» system and to carry out studies to determine the form of inducing wire, creating a narrow and concentrated heat zone in the area of the solder joint. Also solves the problem of the choice of the temperature control means, the information from which is used later to generate the effective management of induction soldering process. Designed hardware complex in conjunction with the developed software system is a system of automatic control, allowing to manage the process of induction heating, to prevent overheating and destruction of the soldered products, improve the stability of induction soldering process, to improve the quality of products, thereby reducing time and material costs for the production.

  20. The Resistance and Strength of Soft Solder Splices between Conductors in MICE Coils

    SciTech Connect

    Wu, Hong; Pan, Heng; Green, Michael A; Dietderich, Dan; Gartner, T. E.; Higley, Hugh C; Mentink, M.; Xu, FengYu; Trillaud, F.; Liu, X. K.; Wang, Li; Zheng, S. X.; Tam, D.G.

    2010-08-03

    Two of the three types of MICE magnets will have splices within their coils. The MICE coupling coils may have as many as fifteen one-meter long splices within them. Each of the MICE focusing coils may have a couple of 0.25-meter long conductor splices. Equations for the calculation of resistance of soldered lap splices of various types are presented. This paper presents resistance measurements of soldered lap splices of various lengths. Measured splice resistance is shown for one-meter long splices as a function of the fabrication method. Another important consideration is the strength of the splices. The measured breaking stress of splices of various lengths is presented in this paper. Tin-lead solders and tin-silver solders were used for the splices that were tested. From the data given in this report, the authors recommend that the use of lead free solders be avoided for low temperature coils.

  1. Robust solder joint attachment of coaxial cable leads to piezoelectric ceramic electrodes

    NASA Astrophysics Data System (ADS)

    Vianco, P. T.

    A technique was developed for the solder attachment of coaxial cable leads to the silver-bearing thick film electrodes on piezoelectric ceramics. Soldering the cable leads directly to the thick film caused bonds with low mechanical strength due to poor solder joint geometry. A barrier coating of 1.5 micron Cu/1.5 micron Ni/1.0 micron Sn deposited on the thick film layer improved the strength of the solder joints by eliminating the absorption of Ag from the thick film which was responsible for the improper solder joint geometry. The procedure does not require special preparation of the electrode surface and is cost effective due to the use of non-precious metal films and the batch processing capabilities of the electron beam deposition technique.

  2. Tensile properties and thermal shock reliability of Sn-Ag-Cu solder joint with indium addition.

    PubMed

    Yu, A-Mi; Jang, Jae-Won; Lee, Jong-Hyun; Kim, Jun-Ki; Kim, Mok-Soon

    2012-04-01

    The thermal shock reliability and tensile properties of a newly developed quaternary Sn-1.2Ag-0.5Cu-0.4In (wt%) solder alloy were investigated and compared to those of ternary Sn-Ag-Cu based Pb-free solder alloys. It was revealed that the Sn-1.2Ag-0.5Cu-0.4In solder alloy shows better thermal shock reliability compared to the Sn-1.0Ag-0.5Cu and Sn-3.0Ag-0.5Cu solder alloys. The quaternary alloy has higher strength than Sn-1.0Ag-0.5Cu alloy, and higher elongation than Sn-3.0Ag-0.5Cu alloy. It was also revealed that the addition of indium promotes the formation of Ag3(Sn, In) phase in the solder joint during reflow process.

  3. The Influence of Processing on Strengthening Mechanisms in Pb-Free Solder Joints

    NASA Astrophysics Data System (ADS)

    Mutuku, Francis; Arfaei, Babak; Cotts, Eric J.

    2017-04-01

    The number, and the spacing, of Ag3Sn precipitates in Sn-Ag-Cu/Cu solder joints were related to separate processing parameters. The mechanical properties of an individual solder joint were directly related to the resulting distribution of different dispersoids in the joint. As the number of Ag3Sn precipitates increased, so did solder joint strength and shear fatigue lifetime. The room-temperature shear fatigue lifetime was inversely correlated with the separation between Ag3Sn precipitates. Bi and Sb solid solution strengthening was found to result in significantly larger values of shear strength and shear fatigue lifetime for one Pb-free solder. Room-temperature shear fatigue lifetime tests were identified as a relatively straightforward, yet sensitive means to gain insight into the reliability of Sn-Ag-Cu (SAC) solder joints.

  4. Partial Synchronization of Interconnected Boolean Networks.

    PubMed

    Chen, Hongwei; Liang, Jinling; Lu, Jianquan

    2017-01-01

    This paper addresses the partial synchronization problem for the interconnected Boolean networks (BNs) via the semi-tensor product (STP) of matrices. First, based on an algebraic state space representation of BNs, a necessary and sufficient criterion is presented to ensure the partial synchronization of the interconnected BNs. Second, by defining an induced digraph of the partial synchronized states set, an equivalent graphical description for the partial synchronization of the interconnected BNs is established. Consequently, the second partial synchronization criterion is derived in terms of adjacency matrix of the induced digraph. Finally, two examples (including an epigenetic model) are provided to illustrate the efficiency of the obtained results.

  5. Reliability of high I/O high density CCGA interconnect electronic packages under extreme thermal environments

    NASA Astrophysics Data System (ADS)

    Ramesham, Rajeshuni

    2012-03-01

    Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performances, compatibility with standard surfacemount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, payload electronics, and flight avionics. As these packages tend to have less solder joint strain relief than leaded packages or more strain relief over lead-less chip carrier packages, the reliability of CCGA packages is very important for short-term and long-term deep space missions. We have employed high density CCGA 1152 and 1272 daisy chained electronic packages in this preliminary reliability study. Each package is divided into several daisy-chained sections. The physical dimensions of CCGA1152 package is 35 mm x 35 mm with a 34 x 34 array of columns with a 1 mm pitch. The dimension of the CCGA1272 package is 37.5 mm x 37.5 mm with a 36 x 36 array with a 1 mm pitch. The columns are made up of 80% Pb/20%Sn material. CCGA interconnect electronic package printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging techniques. The assembled CCGA boards were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space missions. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling. This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions.

  6. Reliability of CCGA 1152 and CCGA 1272 Interconnect Packages for Extreme Thermal Environments

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni

    2013-01-01

    Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages of high interconnect density, very good thermal and electrical performance, and compatibility with standard surface-mount packaging assembly processes. CCGA packages are used in space applications such as in logics and microprocessor functions, telecommunications, flight avionics, and payload electronics. As these packages tend to have less solder joint strain relief than leaded packages, the reliability of CCGA packages is very important for short- and long-term space missions. Certain planetary satellites require operations of thermally uncontrolled hardware under extremely cold and hot temperatures with large diurnal temperature change from day to night. The planetary protection requires the hardware to be baked at +125 C for 72 hours to kill microbugs to avoid any biological contamination, especially for sample return missions. Therefore, the present CCGA package reliability research study has encompassed the temperature range of 185 to +125 C to cover various NASA deep space missions. Advanced 1152 and 1272 CCGA packaging interconnects technology test hardware objects have been subjected to ex treme temperature thermal cycles from 185 to +125 C. X-ray inspections of CCGA packages have been made before thermal cycling. No anomalous behavior and process problems were observed in the x-ray images. The change in resistance of the daisy-chained CCGA interconnects was measured as a function of increasing number of thermal cycles. Electrical continuity measurements of daisy chains have shown no anomalies, even until 596 thermal cycles. Optical inspections of hardware have shown a significant fatigue for CCGA 1152 packages over CCGA 1272 packages. No catastrophic failures have been observed yet in the results. Process qualification and assembly are required to optimize the CCGA assembly processes. Optical inspections of CCGA boards have been made after 258 and 596 thermal

  7. Method for fabricating an interconnected array of semiconductor devices

    DOEpatents

    Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

    1989-10-10

    Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

  8. Fast formation and growth of high-density Sn whiskers in Mg/Sn-based solder/Mg joints by ultrasonic-assisted soldering: Phenomena, mechanism and prevention

    NASA Astrophysics Data System (ADS)

    Li, M. Y.; Yang, H. F.; Zhang, Z. H.; Gu, J. H.; Yang, S. H.

    2016-06-01

    A universally applicable method for promoting the fast formation and growth of high-density Sn whiskers on solders was developed by fabricating Mg/Sn-based solder/Mg joints using ultrasonic-assisted soldering at 250 °C for 6 s and then subjected to thermal aging at 25 °C for 7 d. The results showed that the use of the ultrasonic-assisted soldering could produce the supersaturated dissolution of Mg in the liquid Sn and lead to the existence of two forms of Mg in Sn after solidification. Moreover, the formation and growth of the high-density whiskers were facilitated by the specific contributions of both of the Mg forms in the solid Sn. Specifically, interstitial Mg can provide the persistent driving force for Sn whisker growth, whereas the Mg2Sn phase can increase the formation probability of Sn whiskers. In addition, we presented that the formation and growth of Sn whiskers in the Sn-based solders can be significantly restricted by a small amount of Zn addition (≥3 wt.%), and the prevention mechanisms are attributed to the segregation of Zn atoms at grain or phase boundaries and the formation of the lamellar-type Zn-rich structures in the solder.

  9. Fast formation and growth of high-density Sn whiskers in Mg/Sn-based solder/Mg joints by ultrasonic-assisted soldering: Phenomena, mechanism and prevention

    PubMed Central

    Li, M. Y.; Yang, H. F.; Zhang, Z. H.; Gu, J. H.; Yang, S. H.

    2016-01-01

    A universally applicable method for promoting the fast formation and growth of high-density Sn whiskers on solders was developed by fabricating Mg/Sn-based solder/Mg joints using ultrasonic-assisted soldering at 250 °C for 6 s and then subjected to thermal aging at 25 °C for 7 d. The results showed that the use of the ultrasonic-assisted soldering could produce the supersaturated dissolution of Mg in the liquid Sn and lead to the existence of two forms of Mg in Sn after solidification. Moreover, the formation and growth of the high-density whiskers were facilitated by the specific contributions of both of the Mg forms in the solid Sn. Specifically, interstitial Mg can provide the persistent driving force for Sn whisker growth, whereas the Mg2Sn phase can increase the formation probability of Sn whiskers. In addition, we presented that the formation and growth of Sn whiskers in the Sn-based solders can be significantly restricted by a small amount of Zn addition (≥3 wt.%), and the prevention mechanisms are attributed to the segregation of Zn atoms at grain or phase boundaries and the formation of the lamellar-type Zn-rich structures in the solder. PMID:27273421

  10. Technology, science, and environtmental impact of a novel Cu-Ag core-shell solderless interconnect system

    NASA Astrophysics Data System (ADS)

    Kammer, Milea Joy

    Tin-based solder is ubiquitous in microelectronics manufacturing and plays a critical role in electronic packaging and attachment. While manufacturers of consumer electronics have made the transition to the use of lead-free solder, there are still a variety of reliability issues associated with these lead-free alternatives, particularly for high performance, high reliability applications. Because of these performance short-comings, researchers are still searching for a material, an alloy, or a unique alternative that can meet the thermal, mechanical, and electrical requirements for conventional reflow solder applications. In an effort to produce a more reliable alternative, Kim et al. proposed the low-temperature (200°C) sintering of copper-silver core-shell particles as a viable solderless interconnect technology. This technology is based on the silver atoms from the shell diffusing by surface diffusion to form sintered necks between copper particles, and therefore dewetting most of the copper surfaces. This study presents a 3-fold, in-depth evaluation of this Cu-Ag core-shell lead-free solderless interconnect technology focusing on solder paste development and prototyping, silver thin film stress relaxation and dewetting kinetics, and the environmental impacts associated with this new technology. First, an evaluation of the starting particle consistency and sintered compact mechanical properties determined that a specific core-shell particle geometry (1microm average core diameter and 10nm shell thickness) outperformed other combinations, exhibiting the highest modulus and yield strengths in sintered compacts, of 620 MPa and 40-60 MPa respectively. In particular, yield strengths for sintered compacts are similar to those reported for Sn-3.5Ag-0.75Cu (a commonly used lead-free solder) for the same strain rate. Following particle evaluations, the development of a functioning flux formulation was a key factor in the creation of a viable drop-in replacement. The

  11. Traffic congestion in interconnected complex networks

    NASA Astrophysics Data System (ADS)

    Tan, Fei; Wu, Jiajing; Xia, Yongxiang; Tse, Chi K.

    2014-06-01

    Traffic congestion in isolated complex networks has been investigated extensively over the last decade. Coupled network models have recently been developed to facilitate further understanding of real complex systems. Analysis of traffic congestion in coupled complex networks, however, is still relatively unexplored. In this paper, we try to explore the effect of interconnections on traffic congestion in interconnected Barabási-Albert scale-free networks. We find that assortative coupling can alleviate traffic congestion more readily than disassortative and random coupling when the node processing capacity is allocated based on node usage probability. Furthermore, the optimal coupling probability can be found for assortative coupling. However, three types of coupling preferences achieve similar traffic performance if all nodes share the same processing capacity. We analyze interconnected Internet autonomous-system-level graphs of South Korea and Japan and obtain similar results. Some practical suggestions are presented to optimize such real-world interconnected networks accordingly.

  12. Epidemics in Interconnected Small-World Networks

    PubMed Central

    Liu, Meng; Li, Daqing; Qin, Pengju; Liu, Chaoran; Wang, Huijuan; Wang, Feilong

    2015-01-01

    Networks can be used to describe the interconnections among individuals, which play an important role in the spread of disease. Although the small-world effect has been found to have a significant impact on epidemics in single networks, the small-world effect on epidemics in interconnected networks has rarely been considered. Here, we study the susceptible-infected-susceptible (SIS) model of epidemic spreading in a system comprising two interconnected small-world networks. We find that the epidemic threshold in such networks decreases when the rewiring probability of the component small-world networks increases. When the infection rate is low, the rewiring probability affects the global steady-state infection density, whereas when the infection rate is high, the infection density is insensitive to the rewiring probability. Moreover, epidemics in interconnected small-world networks are found to spread at different velocities that depend on the rewiring probability. PMID:25799143

  13. Recent Development of SOFC Metallic Interconnect

    SciTech Connect

    Wu JW, Liu XB

    2010-04-01

    Interest in solid oxide fuel cells (SOFC) stems from their higher e±ciencies and lower levels of emitted pollu- tants, compared to traditional power production methods. Interconnects are a critical part in SOFC stacks, which connect cells in series electrically, and also separate air or oxygen at the cathode side from fuel at the anode side. Therefore, the requirements of interconnects are the most demanding, i:e:, to maintain high elec- trical conductivity, good stability in both reducing and oxidizing atmospheres, and close coe±cient of thermal expansion (CTE) match and good compatibility with other SOFC ceramic components. The paper reviewed the interconnect materials, and coatings for metallic interconnect materials.

  14. Implementation of optical interconnections for VLSI

    NASA Technical Reports Server (NTRS)

    Wu, Wennie H.; Bergman, Larry A.; Johnston, Alan R.; Guest, Clark C.; Esener, Sadik C.

    1987-01-01

    This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

  15. Traffic congestion in interconnected complex networks.

    PubMed

    Tan, Fei; Wu, Jiajing; Xia, Yongxiang; Tse, Chi K

    2014-06-01

    Traffic congestion in isolated complex networks has been investigated extensively over the last decade. Coupled network models have recently been developed to facilitate further understanding of real complex systems. Analysis of traffic congestion in coupled complex networks, however, is still relatively unexplored. In this paper, we try to explore the effect of interconnections on traffic congestion in interconnected Barabási-Albert scale-free networks. We find that assortative coupling can alleviate traffic congestion more readily than disassortative and random coupling when the node processing capacity is allocated based on node usage probability. Furthermore, the optimal coupling probability can be found for assortative coupling. However, three types of coupling preferences achieve similar traffic performance if all nodes share the same processing capacity. We analyze interconnected Internet autonomous-system-level graphs of South Korea and Japan and obtain similar results. Some practical suggestions are presented to optimize such real-world interconnected networks accordingly.

  16. An Approach for Impression Creep of Lead Free Microelectronic Solders

    NASA Astrophysics Data System (ADS)

    Anastasio, Onofrio A.

    2002-06-01

    Currently, the microelectronics industry is transitioning from lead-containing to lead-free solders in response to legislation in the EU and Japan. Before an alternative alloy can be designated as a replacement for current Pb-Sn extensive testing must be accomplished. One major characteristic of the alloy that must be considered is creep. Traditionally, creep testing requires numerous samples and a long tin, which thwarts the generation of comprehensive creep databases for difficult to prepare samples such as microelectronic solder joints. However, a relatively new technique, impression creep enables us to rapidly generate creep data. This test uses a cylindrical punch with a flat end to make an impression on the surface of a specimen under constant load. The steady state velocity of the indenter is found to have the same stress and temperature dependence as the conventional unidirectional creep test using bulk specimens. This thesis examines impression creep tests of eutectic Sn-Ag. A testing program and apparatus was developed constructed based on a servo hydraulic test frame. The apparatus is capable of a load resolution of 0.01N with a stability of plus/minus 0.1N, and a displacement resolution of 0.05 microns with a stability of plus/minus 0.1 microns. Samples of eutectic Sn-Ag solder were reflowed to develop the microstructure used in microelectronic packaging. Creep tests were conducted at various stresses and temperatures and showed that coarse microstructures creep more rapidly than the microstructures in the tested regime.

  17. Assessment of Solder Joint Fatigue Life Under Realistic Service Conditions

    NASA Astrophysics Data System (ADS)

    Hamasha, Sa'd.; Jaradat, Younis; Qasaimeh, Awni; Obaidat, Mazin; Borgesen, Peter

    2014-12-01

    The behavior of lead-free solder alloys under complex loading scenarios is still not well understood. Common damage accumulation rules fail to account for strong effects of variations in cycling amplitude, and random vibration test results cannot be interpreted in terms of performance under realistic service conditions. This is a result of the effects of cycling parameters on materials properties. These effects are not yet fully understood or quantitatively predictable, preventing modeling based on parameters such as strain, work, or entropy. Depending on the actual spectrum of amplitudes, Miner's rule of linear damage accumulation has been shown to overestimate life by more than an order of magnitude, and greater errors are predicted for other combinations. Consequences may be particularly critical for so-called environmental stress screening. Damage accumulation has, however, been shown to scale with the inelastic work done, even if amplitudes vary. This and the observation of effects of loading history on subsequent work per cycle provide for a modified damage accumulation rule which allows for the prediction of life. Individual joints of four different Sn-Ag-Cu-based solder alloys (SAC305, SAC105, SAC-Ni, and SACXplus) were cycled in shear at room temperature, alternating between two different amplitudes while monitoring the evolution of the effective stiffness and work per cycle. This helped elucidate general trends and behaviors that are expected to occur in vibrations of microelectronics assemblies. Deviations from Miner's rule varied systematically with the combination of amplitudes, the sequences of cycles, and the strain rates in each. The severity of deviations also varied systematically with Ag content in the solder, but major effects were observed for all the alloys. A systematic analysis was conducted to assess whether scenarios might exist in which the more fatigue-resistant high-Ag alloys would fail sooner than the lower-Ag ones.

  18. Role of Stress-Driven Interfacial Instability in the Failure of Confined Electric Interconnects

    NASA Astrophysics Data System (ADS)

    Wang, Nan; Provatas, Nikolas

    2017-02-01

    We examine the possible role of stress-driven surface instability in the failure of electric interconnects found in large-scale integrated circuits. While electromigration is commonly known as the main reason behind interconnect failure, the complex interplay of electromigration-induced mass transport and stress-induced transport has also been studied extensively since the discovery of the Blech effect due to its importance in integrated-circuit design. However, the role of the dielectric medium confining the interconnect has not been properly included in previous analysis of this phenomenon. Here, we examine the classic ATG instability in the presence of dielectric confinement. We propose that thermal stress and surface transport, typically active in all metal interconnects, may trigger a surface instability at the metal-dielectric interface. In particular, we show that there exists a critical thermal stress level below which the stress-driven surface instability cannot be responsible for the failure of interconnects of any length. However, for an interconnect confined by soft low-k dielectric materials, thermal stresses can still be large enough that such stress-driven instability may break the metal conductor even if its length is below the Blech limit.

  19. Imaging and Analysis of Void-defects in Solder Joints Formed in Reduced Gravity using High-Resolution Computed Tomography

    NASA Technical Reports Server (NTRS)

    Easton, John W.; Struk, Peter M.; Rotella, Anthony

    2008-01-01

    As a part of efforts to develop an electronics repair capability for long duration space missions, techniques and materials for soldering components on a circuit board in reduced gravity must be developed. This paper presents results from testing solder joint formation in low gravity on a NASA Reduced Gravity Research Aircraft. The results presented include joints formed using eutectic tin-lead solder and one of the following fluxes: (1) a no-clean flux core, (2) a rosin flux core, and (3) a solid solder wire with external liquid no-clean flux. The solder joints are analyzed with a computed tomography (CT) technique which imaged the interior of the entire solder joint. This replaced an earlier technique that required the solder joint to be destructively ground down revealing a single plane which was subsequently analyzed. The CT analysis technique is described and results presented with implications for future testing as well as implications for the overall electronics repair effort discussed.

  20. Determination of Interfacial Adhesion Strength between Oxide Scale and Substrate for Metallic SOFC Interconnects

    SciTech Connect

    Sun, Xin; Liu, Wenning N.; Stephens, Elizabeth V.; Khaleel, Mohammad A.

    2008-01-21

    The interfacial adhesion strength between the oxide scale and the substrate is crucial to the reliability and durability of metallic interconnects in SOFC operating environments. It is necessary, therefore, to establish a methodology to quantify the interfacial adhesion strength between the oxide scale and the metallic interconnect substrate, and furthermore to design and optimize the interconnect material as well as the coating materials to meet the design life of an SOFC system. In this paper, we present an integrated experimental/analytical methodology for quantifying the interfacial adhesion strength between oxide scale and a ferritic stainless steel interconnect. Stair-stepping indentation tests are used in conjunction with subsequent finite element analyses to predict the interfacial strength between the oxide scale and Crofer 22 APU substrate.