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Sample records for solder interconnect integrity

  1. Assessment of Solder Interconnect Integrity in Dismantled Electronic Components from N57 and B61 Tube-Type Radars

    SciTech Connect

    Rejent, J.A.; Vianco, P.T.; Woodrum, R.A.

    1999-07-01

    Aging analyses were performed on solder joints from two radar units: (1) a laboratory, N57 tube-type radar unit and (2) a field-returned, B61-0, tube-type radar unit. The cumulative temperature environments experienced by the units during aging were calculated from the intermetallic compound layer thickness and the mean Pb-rich phase particle size metrics for solder joints in the units, assuming an aging time of 35 years for both radars. Baseline aging metrics were obtained from a laboratory test vehicle assembled at AS/FM and T; the aging kinetics of both metrics were calculated from isothermal aging experiments. The N57 radar unit interconnect board solder joints exhibited very little aging. The eyelet solder joints did show cracking that most likely occurred at the time of assembly. The eyelet, SA1126 connector solder joints, showed some delamination between the Cu pad and underlying laminate. The B61 field-returned radar solder joints showed a nominal degree of aging. Cracking of the eyelet solder joints was observed. The Pb-rich phase particle measurements indicated additional aging of the interconnects as a result of residual stresses. Cracking of the terminal pole connector, pin-to-pin solder joint was observed; but it was not believed to jeopardize the electrical functionality of the interconnect. Extending the stockpile lifetime of the B61 tube-type radar by an additional 20 years would not be impacted by the reliability of the solder joints with respect to further growth of the intermetallic compound layer. Additional coarsening of the Pb-rich phase will increase the joints' sensitivity to thermomechanical fatigue.

  2. Demonstrated results of welded and soldered interconnections

    NASA Technical Reports Server (NTRS)

    Hart, R. E., Jr.

    1985-01-01

    Solar cell modules with welded and soldered interconnections were constructed using a flexible substrate material. These modules were thermally cycled between approx. 80 deg C at rates 100 cycles/day to demonstrate survivability under simulated low Earth orbit (LEO) temperature conditions. The modules, cycled in an inert atmosphere, show durability for 36,000 cycles.

  3. Effect of grain orientation on mechanical properties and thermomechanical response of Sn-based solder interconnects

    SciTech Connect

    Chen, Hongtao; Yan, Bingbing; Yang, Ming; Ma, Xin; Li, Mingyu

    2013-11-15

    The thermomechanical response of Sn-based solder interconnects with differently oriented grains was investigated by electron backscattered diffraction technique under thermal cycling and thermal shock testing in this study. The results showed that deformation and cracking of solder interconnects have a close relationship with the unique characteristics of grain orientation and boundaries in each solder interconnect, and deformation was frequently confined within the high-angle grain boundaries. The micro Vickers hardness testing results showed that the hardness varied significantly depending on the grain orientation and structure, and deformation twins can be induced around the indents by the indentation testing. - Highlights: • Thermomechanical response shows a close relationship with the grain structure. • Deformation was frequently confined within the high-angle grain boundaries. • Different grain orientations exhibit different hardness. • Deformation twins can be induced around the indents in SAC105 solder interconnects.

  4. Integrated environmentally compatible soldering technologies. Final report

    SciTech Connect

    Hosking, F.M.; Frear, D.R.; Iman, R.L.; Keicher, D.M.; Lopez, E.P.; Peebles, H.C.; Sorensen, N.R.; Vianco, P.T.

    1994-05-01

    Chemical fluxes are typically used during conventional electronic soldering to enhance solder wettability. Most fluxes contain very reactive, hazardous constituents that require special storage and handling. Corrosive flux residues that remain on soldered parts can severely degrade product reliability. The residues are removed with chlorofluorocarbon (CFC), hydrochlorofluorocarbon (HCFC), or other hazardous solvents that contribute to ozone depletion, release volatile organic compounds into the atmosphere, or add to the solvent waste stream. Alternative materials and processes that offer the potential for the reduction or elimination of cleaning are being developed to address these environmental issues. Timing of the effort is critical, since the targeted chemicals will soon be heavily taxed or banned. DOE`s Office of Environmental Restoration and Waste Management (DOE/EM) has supported Sandia National Laboratories` Environmentally Conscious Manufacturing Integrated Demonstration (ECMID). Part of the ECM program involves the integration of several environmentally compatible soldering technologies for assembling electronics devices. Fluxless or {open_quotes}low-residue/no clean{close_quotes} soldering technologies (conventional and ablative laser processing, controlled atmospheres, ultrasonic tinning, protective coatings, and environmentally compatible fluxes) have been demonstrated at Sandia (SNL/NM), the University of California at Berkeley, and Allied Signal Aerospace-Kansas City Division (AS-KCD). The university demonstrations were directed under the guidance of Sandia staff. Results of the FY93 Soldering ID are presented in this report.

  5. Evaluating the Impact of Dwell Time on Solder Interconnect Durability Under Bending Loads

    NASA Astrophysics Data System (ADS)

    Menon, Sandeep; Osterman, Michael; Pecht, Michael

    2015-11-01

    With the increasing portability and miniaturization of modern-day electronics, the mechanical robustness of these systems has become more of a concern. Existing standards for conducting mechanical durability tests of electronic assemblies include bend, shock/drop, vibration, and torsion. Although these standards provide insights into both cyclic fatigue and overstress damage incurred in solder interconnects (widely regarded as the primary mode of failure in electronic assemblies), they fail to address the impact of time- dependent (creep) behavior due to sustained mechanical loads on solder interconnect durability. It has been seen in previous studies that solder durability under thermal cycling loads is inversely proportional to the dwell time or hold time at either temperature extreme of the imposed temperature cycle. Fatigue life models, which include dwell time, have been developed for solder interconnects subject to temperature cycling. However, the fatigue life models that have been developed in the literature for solder interconnects under mechanical loads fail to address the influence of the duration of loading. In this study, solder interconnect test vehicles were subjected to cyclic mechanical bending with various dwell times in order to understand the impact of the duration of mechanical loads on solder interconnect durability. The solder interconnects examined in this study were formed with 2512 resistor packages using various solder compositions [tin-lead (Sn-Pb) and 96.5Sn-3Ag-0.5Cu (SAC305)]. To evaluate the impact of dwell time, the boards were tested with 0 s, 60 s, and 300 s of dwell time at both extremes of the loading profile. It was observed that an increase in the dwell time of the loading profile resulted in a decrease in the characteristic life of the solder interconnects. The decrease in fatigue life was attributed to increased creep damage as identified using finite-element simulations. An energy partitioning approach was then used to

  6. Solder Interconnect Predictor (SIP) Software v. 0.5

    2008-11-19

    This software tool was developed for predicting the fatigue damage in a wide variety of 63Sn-37Pb solder joints used in electronics applications. This tool is based upon the unified creep plasticity damage model CompSIR developed at Sandia National Laboratories. The software can be used as a design tool for predicting the long term reliability of consumer, military and space electronics. Both service as well as accelerated testing environments can be addressed by the user. Themore » mesh generating function provides the user with the greater versatility to explore different package and I/O configurations. For example, different solder joint geometries can be investigated to determine the effects of workmanship quality on reliability. Graphical user interfaces provide the user with easy data input screens as well as results profiles.« less

  7. Solder Interconnect Predictor (SIP) Software v. 0.5

    SciTech Connect

    VIANCO, PAUL; NEILSEN, MICHAEL; & REJENT, JEROME

    2008-11-19

    This software tool was developed for predicting the fatigue damage in a wide variety of 63Sn-37Pb solder joints used in electronics applications. This tool is based upon the unified creep plasticity damage model CompSIR developed at Sandia National Laboratories. The software can be used as a design tool for predicting the long term reliability of consumer, military and space electronics. Both service as well as accelerated testing environments can be addressed by the user. The mesh generating function provides the user with the greater versatility to explore different package and I/O configurations. For example, different solder joint geometries can be investigated to determine the effects of workmanship quality on reliability. Graphical user interfaces provide the user with easy data input screens as well as results profiles.

  8. Thermal compression chip interconnection using organic solderability preservative etched substrate by plasma processing.

    PubMed

    Cho, Sung-Won; Choi, JoonYoung; Chung, Chin-Wook

    2014-12-01

    The solderability of copper organic solderbility preservative (CuOSP) finished substrate was enhanced by the plasma etching. To improve the solderability of TC interconnection with the CuOSP finished substrate, the plasma etching process is used. An Oxygen-Hydrogen plasma treatment process is performed to remove OSP material. To prevent the oxidation by oxygen plasma treatment, hydrogen reducing process is also performed before TC interconnection process. The thickness of OSP material after plasma etching is measured by optical reflection method and the component analysis by Auger Electron Spectroscopy is performed. From the lowered thickness, the bonding force of TC interconnection after OSP etching process is lowered. Also the electrical open/short test was performed after assembling the completed semiconductor packaging. The improved yield due to the plasma etching process is achieved.

  9. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  10. Cell interconnection without glueing or soldering for crystalline Si photovoltaic modules

    NASA Astrophysics Data System (ADS)

    Summhammer, Johann; Halavani, Zahra

    2016-05-01

    In order to maximize the power output of polycrystalline silicon PV-modules, in previous work we have already tested rectangular cells of 39 × 156 mm which are overlapped along the long sides. The low current density at the cell overlap allows interconnections which need neither soldering nor glueing, but use metallic strips inserted between the cells in the overlap region. The contact is established by the pressure applied to the module during lamination and is retained by the slightly bent cells in the solidified encapsulant. Here we report on the long term stability of different contact materials and contact cross sections applied in eight modules of the 240 W class monitored for up to 24 months of outdoor operation and in a variety of small 5-cell modules exposed to rapid ageing tests with up to 1000 thermal cycles. Cells with three different electrode designs were tested and the contact materials were Cu, Ag, SnPbAg and Sn. Focussing especially on series resistance, fill factor and peak power, it is found that Ag-coated contact strips perform equally well and have practically the same stability as soldered cell interconnections. Due to 70-90% savings in copper and simpler manufacturing the cost of PV-modules may thus be reduced further.

  11. Investigation Of The Effects Of Reflow Profile Parameters On Lead-free Solder Bump Volumes And Joint Integrity

    NASA Astrophysics Data System (ADS)

    Amalu, E. H.; Lui, Y. T.; Ekere, N. N.; Bhatti, R. S.; Takyi, G.

    2011-01-01

    The electronics manufacturing industry was quick to adopt and use the Surface Mount Technology (SMT) assembly technique on realization of its huge potentials in achieving smaller, lighter and low cost product implementations. Increasing global customer demand for miniaturized electronic products is a key driver in the design, development and wide application of high-density area array package format. Electronic components and their associated solder joints have reduced in size as the miniaturization trend in packaging continues to be challenged by printing through very small stencil apertures required for fine pitch flip-chip applications. At very narrow aperture sizes, solder paste rheology becomes crucial for consistent paste withdrawal. The deposition of consistent volume of solder from pad-to-pad is fundamental to minimizing surface mount assembly defects. This study investigates the relationship between volume of solder paste deposit (VSPD) and the volume of solder bump formed (VSBF) after reflow, and the effect of reflow profile parameters on lead-free solder bump formation and the associated solder joint integrity. The study uses a fractional factorial design (FFD) of 24-1 Ramp-Soak-Spike reflow profile, with all main effects and two-way interactions estimable to determine the optimal factorial combination. The results from the study show that the percentage change in the VSPD depends on the combination of the process parameters and reliability issues could become critical as the size of solder joints soldered on the same board assembly vary greatly. Mathematical models describe the relationships among VSPD, VSBF and theoretical volume of solder paste. Some factors have main effects across the volumes and a number of interactions exist among them. These results would be useful for R&D personnel in designing and implementing newer applications with finer-pitch interconnect.

  12. INTERCONNECTIONS BETWEEN HUMAN HEALTH AND ECOLOGICAL INTEGRITY

    EPA Science Inventory

    Interconnections between Human Health and Ecological Integrity emanates from a June 2000 Pellston Workshop in Snowbird, Utah, USA. Jointly sponsored by the Society of Environmental Toxicology and Chemistry (SETAC) and the Society of Toxicology (SOT), the workshop was motivated by...

  13. Microstructure and Grain Orientation Evolution in Sn-3.0Ag-0.5Cu Solder Interconnects Under Electrical Current Stressing

    NASA Astrophysics Data System (ADS)

    Chen, Hongtao; Hang, Chunjin; Fu, Xing; Li, Mingyu

    2015-10-01

    In situ observation was performed on cross-sections of Sn-3.0Ag-0.5Cu solder interconnects to track the evolution of microstructure and grain orientation under electrical current stressing. Cross-sections of Cu/Ni-Sn-3.0Ag-0.5Cu-Ni/Cu sandwich-structured solder interconnects were prepared by the standard metallographic method and subjected to electrical current stressing for different times. The electron backscatter diffraction technique was adopted to characterize the grain orientation and structure of the solder interconnects. The results show that metallization dissolution and intermetallic compound (IMC) migration have close relationships with the grain orientation and structure of the solder interconnects. Ni metallization dissolution at the cathode interface and IMC migration in the solder bulk can be accelerated when the c-axis of the grain is parallel to the electron flow direction, while no observable change was found when the c-axis of the grain was perpendicular to the electron flow direction. IMC can migrate along or be blocked at the grain boundary, depending on the misorientation between the current flow direction and grain boundary.

  14. Healing Voids In Interconnections In Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

    1989-01-01

    Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

  15. Sn-Ag-Cu Nanosolders: Solder Joints Integrity and Strength

    NASA Astrophysics Data System (ADS)

    Roshanghias, Ali; Khatibi, Golta; Yakymovych, Andriy; Bernardi, Johannes; Ipser, Herbert

    2016-08-01

    Although considerable research has been dedicated to the synthesis and characterization of lead-free nanoparticle solder alloys, only very little has been reported on the reliability of the respective joints. In fact, the merit of nanoparticle solders with depressed melting temperatures close to the Sn-Pb eutectic temperature has always been challenged when compared with conventional solder joints, especially in terms of inferior solderability due to the oxide shell commonly present on the nanoparticles, as well as due to compatibility problems with common fluxing agents. Correspondingly, in the current study, Sn-Ag-Cu (SAC) nanoparticle alloys were combined with a proper fluxing vehicle to produce prototype nanosolder pastes. The reliability of the solder joints was successively investigated by means of electron microscopy and mechanical tests. As a result, the optimized condition for employing nanoparticles as a competent nanopaste and a novel procedure for surface treatment of the SAC nanoparticles to diminish the oxide shell prior to soldering are being proposed.

  16. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  17. Integrated nanophotonic devices for optical interconnections

    NASA Astrophysics Data System (ADS)

    Huang, Yidong; Feng, Xue; Cui, Kaiyu; Li, Yongzhuo; Wang, Yu

    2016-03-01

    Nanostructure is an effective solution for realizing optoelectronic devices with compact size and high performances simultaneously. This paper reports our research progress on integrated nanophotonic devices for optical interconnections. We proposed a parent-sub micro ring structure for optical add-drop multiplexer (OADM) with compact footprint, large free spectral range, and uniform channel spacing. All eight channels can be multiplexed and de-multiplexed with 2.6 dB drop loss, 0.36 nm bandwidth (>40 GHz), -20 dB channel crosstalk, and high thermal tuning efficiency of 0.15 nm/mW. A novel principle of optical switch was proposed and demonstrated based on the coupling of the defect modes in photonic crystal waveguide. Switching functionality with bandwidth up to 24 nm and extinction ratio in excess of 15 dB over the entire bandwidth was achieved, while the footprint was only 8 μm×17.6 μm. We proposed an optical orbital angular momentum (OAM) coding and decoding method to increase the data-carrying capacity of wireless optical interconnect. An integrated OAM emitter, where the topological charge can be continuously varied from -4 to 4 was realized. Also we studied ultrafast modulated nLED as the integrated light source for optical interconnections using a nanobeam cavity with stagger holes.

  18. Integrated silicon photonic interconnect with surface-normal optical interface

    NASA Astrophysics Data System (ADS)

    Zhang, Zanyun; Huang, Beiju; Zhang, Zan; Cheng, Chuantong; Liu, Hongwei; Li, Hongqiang; Chen, Hongda

    2016-05-01

    An integrated silicon photonic interconnect with surface-normal optical interface is demonstrated by connecting a bidirectional grating based E-O modulator and a germanium waveguide photodetector. To investigate this photonic interconnect, both static and dynamic performance of the discrete devices are characterized respectively. Based on the characterization work, data transmission experiment is carried out for the photonic interconnect. Eye diagram results indicate the photonic interconnect can operate up to 7 Gb/s.

  19. Soldered solar arrays

    NASA Astrophysics Data System (ADS)

    Allen, H. C.

    1982-06-01

    The ability of soldered interconnects to withstand a combination of long life and severe environmental conditions was investigated. Improvements in joint life from the use of solder mixes appropriate to low temperature conditons were studied. Solder samples were placed in a 150 C oven for 5 weeks (= 12 yr at 80 C, or 24 at 70 C according to Arrhenius's rule). Conventional and high solder melting point array samples underwent 1000 thermal cycles between -186 and 100 C. Results show that conventional and lead rich soldered arrays can survive 10 yr geostationary orbit missions.

  20. PCB with fully integrated optical interconnects

    NASA Astrophysics Data System (ADS)

    Langer, Gregor; Satzinger, Valentin; Schmidt, Volker; Schmid, Gerhard; Leeb, Walter R.

    2011-01-01

    The increasing demand for miniaturization and design flexibility of polymer optical waveguides integrated into electrical printed circuit boards (PCB) calls for new coupling and integration concepts. We report on a method that allows the coupling of optical waveguides to electro-optical components as well as the integration of an entire optical link into the PCB. The electro-optical devices such as lasers and photodiodes are assembled on the PCB and then embedded in an optically transparent material. A focused femtosecond laser beam stimulates a polymerization reaction based on a two-photon absorption effect in the optical material and locally increases the refractive index of the material. In this way waveguide cores can be realized and the embedded components can be connected optically. This approach does not only allow a precise alignment of the waveguide end faces to the components but also offers a truly 3-dimensional routing capability of the waveguides. Using this technology we were able to realize butt-coupling and mirror-coupling interface solutions in several demonstrators. We were also manufacturing demonstrator boards with fully integrated driver and preamplifier chips, which show very low power consumption of down to 10 mW for about 2.5 Gbit/s. Furthermore, demonstrators with interconnects at two different optical layers were realized.

  1. Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

    NASA Technical Reports Server (NTRS)

    Mandal, R. P.

    1976-01-01

    Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

  2. Impact of Cooling Rate-Induced Recrystallization on High G Mechanical Shock and Thermal Cycling in Sn-Ag-Cu Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Lee, Tae-Kyu; Bieler, Thomas R.; Kim, Choong-Un

    2016-01-01

    The mechanical stability and thermo-mechanical fatigue performance of solder joints with low silver content Sn-1.0Ag-0.5Cu (wt.%) (SAC105) alloy based on different cooling rates are investigated in high G level shock environment and thermal cycling conditions. The cooling rate-controlled samples ranging from 1°C/min to 75°C/min cooling rate, not only show differences in microstructure, where a fine poly-granular microstructure develops in the case of fast cooling versus normal cooling, but also show various shock performances based on the microstructure changes. The fast cooling rate improves the high G shock performance by over 90% compared to the normal cooled SAC105 alloy air-cooling environment commonly used after assembly reflow. The microstructure effect on thermal cycling performance is also discussed, which is analyzed based on the Sn grain orientation, interconnect stability, and solder joint bulk microstructure.

  3. Interconnection of thermal parameters, microstructure and mechanical properties in directionally solidified Sn–Sb lead-free solder alloys

    SciTech Connect

    Dias, Marcelino; Costa, Thiago; Rocha, Otávio; Spinelli, José E.; Cheung, Noé; Garcia, Amauri

    2015-08-15

    Considerable effort is being made to develop lead-free solders for assembling in environmental-conscious electronics, due to the inherent toxicity of Pb. The search for substitute alloys of Pb–Sn solders has increased in order to comply with different soldering purposes. The solder must not only meet the expected levels of electrical performance but may also have appropriate mechanical strength, with the absence of cracks in the solder joints. The Sn–Sb alloy system has a range of compositions that can be potentially included in the class of high temperature solders. This study aims to establish interrelations of solidification thermal parameters, microstructure and mechanical properties of Sn–Sb alloys (2 wt.%Sb and 5.5 wt.%Sb) samples, which were directionally solidified under cooling rates similar to those of reflow procedures in industrial practice. A complete high-cooling rate cellular growth is shown to be associated with the Sn–2.0 wt.%Sb alloy and a reverse dendrite-to-cell transition is observed for the Sn–5.5 wt.%Sb alloy. Strength and ductility of the Sn–2.0 wt.%Sb alloy are shown not to be affected by the cellular spacing. On the other hand, a considerable variation in these properties is associated with the cellular region of the Sn–5.5 wt.%Sb alloy casting. - Graphical abstract: Display Omitted - Highlights: • The microstructure of the Sn–2 wt.%Sb alloy is characterized by high-cooling rates cells. • Reverse dendrite > cell transition occurs for Sn–5.5 wt.%Sb alloy: cells prevail for cooling rates > 1.2 K/s. • Sn–5.5 wt.%Sb alloy: the dendritic region occurs for cooling rates < 0.9 K/s. • Sn–5.5 wt.%Sb alloy: tensile properties are improved with decreasing cellular spacing.

  4. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2004-09-28

    An electrochemical energy storage device includes a number of solid-state thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. Fuses and various electrical and electro-mechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  5. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2003-11-04

    The present invention is directed to an improved electrochemical energy storage device. The electrochemical energy storage device includes a number of solid-state, thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. Fuses and various electrical and electromechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  6. Stress-induced voiding study in integrated circuit interconnects

    NASA Astrophysics Data System (ADS)

    Hou, Yuejin; Tan, Cher Ming

    2008-07-01

    An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

  7. A Novel and Facile Method to Prepare Integrated Electrospun Nanofibrous Membrane with Soldered Junctions.

    PubMed

    Shen, Lingdi; Chen, Jiajia; Hong, Guishan; Wang, Xuefen

    2016-01-01

    Integrated electrospun nanofibrous membrane was prepared by creating soldered junctions between nanofibers via a facile strategy. Polyacrylonitrile (PAN) mixed with poly(vinylidene fluoride) (PVDF) at different ratios of PVDF were prepared in N,N'-dimethyl formamide (DMF), then electrospun to fabricate PAN/PVDF membranes. PVDF can form microgels in DMF which slows down volatile speed of DMF and affects the solidification of PAN/PVDF nanofibers. The resulting membranes were investigated by Fourier transform infrared spectroscopy, scanning electron microscopy, dynamic water contact angle and tensile testing to confirm the morphology and mechanical properties. Soldered junctions were observed between nanofibers with the increase of PVDF content. These junctions made the membrane integrated and greatly enhanced tensile strength from 5.1 to 8.1 MPa (increased by ~60%) and tensile modulus from 49.4 to 117.9 MPa (increased by ~139%) without compromising porosity when the content of PVDF increased from 0 to 60 wt%. PMID:27398532

  8. Updating Interconnection Screens for PV System Integration

    SciTech Connect

    Coddington, M.; Mather, B.; Kroposki, B.; Lynn, K.; Razon, A.; Ellis, A.; Hill, R.; Key, T.; Nicole, K.; Smith, J.

    2012-02-01

    This white paper evaluates the origins and usefulness of the capacity penetration screen, offer short-term solutions which could effectively allow fast-track interconnection to many PV system applications, and considers longer-term solutions for increasing PV deployment levels in a safe and reliable manner while reducing or eliminating the emphasis on the penetration screen. Short-term and longer-term alternatives approaches are offered as examples; however, specific modifications to screening procedures should be discussed with stakeholders and must ultimately be adopted by state and federal regulatory bodies.

  9. Metallic Nanowire Interconnections for Integrated Circuit Fabrication

    NASA Technical Reports Server (NTRS)

    Ng, Hou Tee (Inventor); Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

    2007-01-01

    A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

  10. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  11. An application of carbon nanotubes for integrated circuit interconnects

    NASA Astrophysics Data System (ADS)

    Coiffic, J. C.; Foa Torres, L. E.; Le Poche, H.; Fayolle, M.; Roche, S.; Maitrejean, S.; Roualdes, S.; Ayral, A.

    2008-08-01

    Integrated circuits fabrication is soon reaching strong limitations. Help could come from using carbon nanotubes as conducting wires for interconnects. Although this solution was proposed six years ago, researchers still come up with many obstacles such as localization, low temperature growth on copper, contacting and reproducibility. The integration processes exposed here intend to meet the industrial requirements. Two approaches are then possibly followed. Either using densely packed single wall (SWCNT) (or very tiny multiwall) nanotubes, or filling up the whole interconnect diameter with a single large multiwall (MWCNT) nanotube. In this work, we focus on the integration of multiwall vertical interconnects. Densely packed MWCNTs are grown in via holes by CVD. Alternatively, we have developed a method to obtain a single large nanofibre grown by PECVD (MWCNF) in each via hole. Electrical measurements are performed on CVD and PECVD grown carbon nanotubes. The role of electron-phonon interaction in these devices is also briefly discussed.

  12. Time And Temperature Dependent Micromechanical Properties Of Solder Joints For 3D-Package Integration

    NASA Astrophysics Data System (ADS)

    Roellig, Mike; Meier, Karsten; Metasch, Rene

    2010-11-01

    The recent development of 3D-integrated electronic packages is characterized by the need to increase the diversity of functions and to miniaturize. Currently many 3D-integration concepts are being developed and all of them demand new materials, new designs and new processing technologies. The combination of simulation and experimental investigation becomes increasingly accepted since simulations help to shorten the R&D cycle time and reduce costs. Numerical calculations like the Finite-Element-Method are strong tools to calculate stress conditions in electronic packages resulting from thermal strains due to the manufacturing process and environmental loads. It is essential for the application of numerical calculations that the material data is accurate and describes sufficiently the physical behaviour. The developed machine allows the measurement of time and temperature dependent micromechanical properties of solder joints. Solder joints, which are used to mechanically and electrically connect different packages, are physically measured as they leave the process. This allows accounting for process influences, which may change material properties. Additionally, joint sizes and metallurgical interactions between solder and under bump metallization can be respected by this particular measurement. The measurement allows the determination of material properties within a temperature range of 20° C-200° C. Further, the time dependent creep deformation can be measured within a strain-rate range of 10-31/s-10-81/s. Solder alloys based on Sn-Ag/Sn-Ag-Cu with additionally impurities and joint sizes down to O/ 200 μm were investigated. To finish the material characterization process the material model coefficient were extracted by FEM-Simulation to increase the accuracy of data.

  13. Solid-state energy storage module employing integrated interconnect board

    DOEpatents

    Rouillard, Jean; Comte, Christophe; Daigle, Dominik; Hagen, Ronald A.; Knudson, Orlin B.; Morin, Andre; Ranger, Michel; Ross, Guy; Rouillard, Roger; St-Germain, Philippe; Sudano, Anthony; Turgeon, Thomas A.

    2000-01-01

    The present invention is directed to an improved electrochemical energy storage device. The electrochemical energy storage device includes a number of solid-state, thin-film electrochemical cells which are selectively interconnected in series or parallel through use of an integrated interconnect board. The interconnect board is typically disposed within a sealed housing which also houses the electrochemical cells, and includes a first contact and a second contact respectively coupled to first and second power terminals of the energy storage device. The interconnect board advantageously provides for selective series or parallel connectivity with the electrochemical cells, irrespective of electrochemical cell position within the housing. In one embodiment, a sheet of conductive material is processed by employing a known milling, stamping, or chemical etching technique to include a connection pattern which provides for flexible and selective interconnecting of individual electrochemical cells within the housing, which may be a hermetically sealed housing. Fuses and various electrical and electro-mechanical devices, such as bypass, equalization, and communication devices for example, may also be mounted to the interconnect board and selectively connected to the electrochemical cells.

  14. Heat Lamps Solder Solar Array Quickly

    NASA Technical Reports Server (NTRS)

    Coyle, P. J.; Crouthamel, M. S.

    1982-01-01

    Interconnection tabs in a nine-solar-cell array have been soldered simultaneously with radiant heat. Cells and tabs are held in position for soldering by sandwiching them between compliant silicone-rubber vacuum platen and transparent polyimide sealing membrane. Heat lamps warm cells, producing smooth, flat solder joints of high quality.

  15. Formation of solid-solution Cu-to-Cu joints using Ga solder and Pt under bump metallurgy for three-dimensional integrated circuits

    NASA Astrophysics Data System (ADS)

    Lin, Shih-kang; Chang, Hao-miao; Cho, Cheng-liang; Liu, Yu-chen; Kuo, Yi-kai

    2015-07-01

    Three-dimensional (3D) integrated circuits (ICs) are the most important packaging technology for next-generation semiconductors. Cu-to-Cu throughsilicon via interconnections with micro-bumps are key components in the fabrication of 3D ICs. However, significant reliability concerns have been raised due to the formation of brittle intermetallic compounds in the entire 3D IC joints. This study proposes a Ga-based Cu-to-Cu bonding technology with Pt under bump metallurgy (UBM). A systematic analysis of reactive wetting between Ga solders and polycrystalline, single-crystalline, and Ptcoated Cu substrates was conducted. Pt UBM as a wetting layer was identified to be a key component for Ga-based Cu-to-Cu bonding. Pt-coated Cu substrates were bonded using Ga solders with various Ga-to-Pt ratios ( n) at 300℃. When n ≥ 4, the Cu/Pt/Ga/Pt/Cu interface evolves to Cu/facecentered cubic (fcc)/γ1-Cu9Ga4/fcc/Cu, Cu/fcc/γ1-Cu9Ga4 + Ga7Pt3/fcc/Cu, and finally Cu/fcc + Ga7Pt3/Cu structures. The desired ductile solid solution joint formed with discrete Ga7Pt3 precipitates. When n ≤ 1, a Cu/Ga7Pt3/Cu joint formed without Cu actively participating in the reactions. The reaction mechanism and microstructure evolution were elaborated with the aid of CALPHAD thermodynamic modeling. [Figure not available: see fulltext.

  16. Solder poisoning

    MedlinePlus

    ... when someone swallows solder in large amounts. Skin burns can occur if solder touches the skin. This ... urine output EYES, EARS, NOSE, MOUTH, AND THROAT Burns in mouth and throat Yellow eyes (jaundice) STOMACH ...

  17. Integration of a waveguide self-electrooptic effect device and a vertically coupled interconnect waveguide

    DOEpatents

    Vawter, G. Allen

    2008-02-26

    A self-electrooptic effect device ("SEED") is integrated with waveguide interconnects through the use of vertical directional couplers. Light initially propagating in the interconnect waveguide is vertically coupled to the active waveguide layer of the SEED and, if the SEED is in the transparent state, the light is coupled back to the interconnect waveguide.

  18. Solder Mounting Technologies for Electronic Packaging

    SciTech Connect

    VIANCO, PAUL T.

    1999-09-23

    Soldering provides a cost-effective means for attaching electronic packages to circuit boards using both small scale and large scale manufacturing processes. Soldering processes accommodate through-hole leaded components as well as surface mount packages, including the newer area array packages such as the Ball Grid Arrays (BGA), Chip Scale Packages (CSP), and Flip Chip Technology. The versatility of soldering is attributed to the variety of available solder alloy compositions, substrate material methodologies, and different manufacturing processes. For example, low melting temperature solders are used with temperature sensitive materials and components. On the other hand, higher melting temperature solders provide reliable interconnects for electronics used in high temperature service. Automated soldering techniques can support large-volume manufacturing processes, while providing high reliability electronic products at a reasonable cost.

  19. Solar cell array interconnects

    DOEpatents

    Carey, Paul G.; Thompson, Jesse B.; Colella, Nicolas J.; Williams, Kenneth A.

    1995-01-01

    Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb-Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value.

  20. Solar cell array interconnects

    DOEpatents

    Carey, P.G.; Thompson, J.B.; Colella, N.J.; Williams, K.A.

    1995-11-14

    Electrical interconnects are disclosed for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb-Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb-Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value. 4 figs.

  1. Induction soldering of photovoltaic system components

    SciTech Connect

    Kumaria, Shashwat; de Leon, Briccio

    2015-11-17

    A method comprises positioning a pair of photovoltaic wafers in a side-by-side arrangement. An interconnect is placed on the pair of wafers such that the interconnect overlaps both wafers of the pair, solder material being provided between the interconnect and the respective wafers. A solder head is then located adjacent the interconnect, and the coil is energized to effect inductive heating of the solder material. The solder head comprises an induction coil shaped to define an eye, and a magnetic field concentrator located at least partially in the eye of the coil. The magnetic field concentrator defines a passage extending axially through the eye of the coil, and may be of a material with a high magnetic permeability.

  2. Electromigration-induced back stress in critical solder length for three-dimensional integrated circuits

    SciTech Connect

    Huang, Y. T.; Hsu, H. H.; Wu, Albert T.

    2014-01-21

    Because of the miniaturization of electronic devices, the reliability of electromigration has become a major concern when shrinking the solder dimensions in flip-chip joints. Fast reaction between solders and electrodes causes intermetallic compounds (IMCs) to form, which grow rapidly and occupy entire joints when solder volumes decrease. In this study, U-grooves were fabricated on Si chips as test vehicles. An electrode-solder-electrode sandwich structure was fabricated by using lithography and electroplating. Gaps exhibiting well-defined dimensions were filled with Sn3.5Ag solders. The gaps between the copper electrodes in the test sample were limited to less than 15 μm to simulate microbumps. The samples were stressed at various current densities at 100 °C, 125 °C, and 150 °C. The morphological changes of the IMCs were observed, and the dimensions of the IMCs were measured to determine the kinetic growth of IMCs. Therefore, this study focused on the influence of back stress caused by microstructural evolution in microbumps.

  3. Solder Contamination

    SciTech Connect

    Vianco, P.T.

    1999-02-22

    There are two sources of contamination in solder alloys. The first source is trace elements from the primary metals used in the as-manufactured product, be that product in ingot, wire, or powder form. Their levels in the primary metal are determined by the refining process. While some of these trace elements are naturally occurring materials, additional contamination can result from the refining and/or forming processes. Sources include: furnace pot liners, debris on the cutting edges of shears, rolling mill rollers, etc. The types and levels of contaminants per solder alloy are set by recognized industrial, federal, military, and international specifications. For example, the 63Sn-37Pb solder purchased to the ASTM B 32 standard can have maximum levels of contamination for the following metals: 0.08(wt.)%Cu, 0.001 %Cd, 0.005%Al, 0.25%Bi, 0.03%As, 0.02%Fe, and 0.005 %Zn. A second cause of contamination in solders, and solder baths in particular, is their actual use in soldering operations. Each time a workpiece is introduced into the bath, some dissolution of the joint base metal(s), protective or solderable coatings, and fixture metal takes place which adds to contamination levels in the solder. The potential impurities include Cu; Ni; Au or other noble metals used as protective finishes and Al; Fe; and Zn to name a few. Even dissolution of the pot wall or liner is a source of impurities, typically Fe.

  4. Perpendicular Growth Characteristics of Cu-Sn Intermetallic Compounds at the Surface of 99Sn-1Cu/Cu Solder Interconnects

    NASA Astrophysics Data System (ADS)

    Chen, Zhiwen; Liu, Changqing; Wu, Yiping; An, Bing

    2015-12-01

    The growth of intermetallic compounds (IMCs) on the free surface of 99Sn-1Cu solder joints perpendicular to the interdiffusion direction has been investigated in this work. The specimens were specifically designed and polished to reveal a flat free surface at the solder/Cu interface for investigation. After aging at 175°C for progressively increased durations, the height of the perpendicular IMCs was examined and found to follow a parabolic law with aging duration that could be expressed as y = 0.11√ t, where t is the aging duration in hours and y is the height of the perpendicular IMCs in μm. For comparison, the planar growth of IMCs along the interdiffusion direction was also investigated in 99Sn-1Cu/Cu solder joints. After prolonged aging at 175°C, the thickness of the planar interfacial IMC layers also increased parabolically with aging duration and could be expressed as h_{{IMC}} = 0.27√ t + 4.6, where h is the thickness in μm and t is the time in hours. It was found that both the planar and perpendicular growth of the IMCs were diffusion-controlled processes, but the perpendicular growth of the IMCs was much slower than their planar growth due to the longer diffusion distance. It is proposed that Cu3Sn forms prior to the formation of Cu6Sn5 in the perpendicular IMCs, being the reverse order compared with the planar IMC growth.

  5. Modeling and extraction of interconnect parameters in very-large-scale integrated circuits

    NASA Astrophysics Data System (ADS)

    Yuan, C. P.

    1983-08-01

    The increased complexity of the very large scale integrated circuits (VLSI) has greatly impacted the field of computer-aided design (CAD). One of the problems brought about is the interconnection problem. In this research, the goal is two fold. First of all, a more accurate numerical method to evaluate the interconnect capacitance, including the coupling capacitance between interconnects and the fringing field capacitance, was investigated, and the integral method was employed. Two FORTRAN programs "CAP2D' and "CAP3D' based on this method were developed. Second, a PASCAL extraction program emphasizing the extraction of interconnect parameters was developed. It employs the cylindrical approximation formula for the self-capacitance of a single interconnect and other simple formulas for the coupling capacitances derived by a least square method. The extractor assumes only Manhattan geometry and NMOS technology. Four-dimensional binary search trees are used as the basic data structure.

  6. Wave soldering with Pb-free solders

    SciTech Connect

    Artaki, I.; Finley, D.W.; Jackson, A.M.; Ray, U.; Vianco, P.T.

    1995-07-01

    The manufacturing feasibility and attachment reliability of a series of newly developed lead-free solders were investigated for wave soldering applications. Some of the key assembly aspects addressed included: wettability as a function of board surface finish, flux activation and surface tension of the molten solder, solder joint fillet quality and optimization of soldering thermal profiles. Generally, all new solder formulations exhibited adequate wave soldering performance and can be considered as possible alternatives to eutectic SnPb for wave soldering applications. Further process optimization and flux development is necessary to achieve the defect levels associated with the conventional SnPb process.

  7. Fully-integrated, bezel-less transistor arrays using reversibly foldable interconnects and stretchable origami substrates

    NASA Astrophysics Data System (ADS)

    Kim, Mijung; Park, Jihun; Ji, Sangyoon; Shin, Sung-Ho; Kim, So-Yun; Kim, Young-Cheon; Kim, Ju-Young; Park, Jang-Ung

    2016-05-01

    Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints.Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02041k

  8. Requirements for soldered electrical connections

    NASA Technical Reports Server (NTRS)

    1992-01-01

    This publication is applicable to NASA programs involving solder connections for flight hardware, mission essential support equipment, and elements thereof. This publication sets forth hand and wave soldering requirements for reliable electrical connections. The prime consideration is the physical integrity of solder connections. Special requirements may exist which are not in conformance with the requirements of this publication. Design documentation contains the detail for these requirements, and they take precedence over conflicting portions of this publication when they are approved in writing by the procuring NASA installation.

  9. Process for electrically interconnecting electrodes

    DOEpatents

    Carey, Paul G.; Thompson, Jesse B.; Colella, Nicolas J.; Williams, Kenneth A.

    2002-01-01

    Electrical interconnects for solar cells or other electronic components using a silver-silicone paste or a lead-tin (Pb--Sn) no-clean fluxless solder cream, whereby the high breakage of thin (<6 mil thick) solar cells using conventional solder interconnect is eliminated. The interconnects of this invention employs copper strips which are secured to the solar cells by a silver-silicone conductive paste which can be used at room temperature, or by a Pb--Sn solder cream which eliminates undesired residue on the active surfaces of the solar cells. Electrical testing using the interconnects of this invention has shown that no degradation of the interconnects developed under high current testing, while providing a very low contact resistance value.

  10. Automatic computer-aided system of simulating solder joint formation

    NASA Astrophysics Data System (ADS)

    Zhao, Xiujuan; Wang, Chunqing; Zheng, Guanqun; Wang, Gouzhong; Yang, Shiqin

    1999-08-01

    One critical aspect in electronic packaging is the fatigue/creep-induced failure in solder interconnections, which is found to be highly dependent on the shape of solder joints. Thus predicting and analyzing the solder joint shape is warranted. In this paper, an automatic computer-aided system is developed to simulate the formation of solder joint and analyze the influence of the different process parameters on the solder joint shape. The developed system is capable of visually designing the process parameters and calculating the solder joint shape automatically without any intervention from the user. The automation achieved will enable fast shape estimation with the variation of process parameters without time consuming experiments, and the simulating system provides the design and manufacturing engineers an efficient software tools to design soldering process in design environment. Moreover, a program developed from the system can serve as the preprocessor for subsequent finite element joint analysis program.

  11. Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

    SciTech Connect

    Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q.; Enquist, P.M.

    1995-12-31

    Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

  12. Wafer-Level 3D Integration for ULSI Interconnects

    NASA Astrophysics Data System (ADS)

    Gutmann, Ronald J.; Lu, Jian-Qiang

    Three-dimensional (3D) integration in a system-in-a-package (SiP) implementation (packaging-based 3D) is becoming increasingly used in consumer, computer, and communication applications where form factor is critical. In particular, the hand-held market for a growing myriad of voice, data, messaging, and imaging products is enabled by packaging-based 3D integration (i.e., stacking and connecting individual chips). The key drivers are for increased memory capacity and for heterogeneous integration of different IC technologies and functions.

  13. Inter-connections between human health and ecological integrity: An organizational framework for research and development

    EPA Science Inventory

    A Pellston workshop entitled, Interconnections between Human Health and Ecological Integrity, was held in 2000. Jointly sponsored by the Society of Environmental Toxicology and Chemistry (SETAC) and the Society of Toxicology (SOT), the workshop was motivated by the concern of hum...

  14. Prototype circuit boards assembled with non-lead bearing solders

    SciTech Connect

    Vianco, P.T.; Rejent, J.A.

    1998-04-01

    The 91.84Sn-3.33Ag-4.83Bi and 96.5Sn-3.5Ag Pb-free solders were evaluated for surface mount circuit board interconnects. The 63Sn-37Pb solder provided the baseline data. All three solders exhibited suitable manufacturability per a defect analyses of circuit board test vehicles. Thermal cycling had no significant effect on the 91.84Sn-3.33Ag-4.83Bi solder joints. Some degradation in the form of grain boundary sliding was observed in 96.5Sn-3.5Ag and 63Sn-37Pb solder joints. The quality of the solder joint microstructures showed a slight degree of degradation under thermal shock exposure for all of the solders tested. Trends in the solder joint shear strengths could be traced to the presence of Pd in the solder, the source of which was the Pd/Ni finish on the circuit board conductor features. The higher, intrinsic strengths of the Pb-free solders encouraged the failure path to be located in proximity to the solder/substrate interface where Pd combined with Sn to form brittle PdSn{sub 4} particles, resulting in reduced shear strengths.

  15. Solder flow over fine line PWB surface finishes

    SciTech Connect

    Hosking, F.M.; Hernandez, C.L.

    1998-08-01

    The rapid advancement of interconnect technology has stimulated the development of alternative printed wiring board (PWB) surface finishes to enhance the solderability of standard copper and solder-coated surfaces. These new finishes are based on either metallic or organic chemistries. As part of an ongoing solderability study, Sandia National Laboratories has investigated the solder flow behavior of two azole-based organic solderability preservations, immersion Au, immersion Ag, electroless Pd, and electroless Pd/Ni on fine line copper features. The coated substrates were solder tested in the as-fabricated and environmentally-stressed conditions. Samples were processed through an inerted reflow machine. The azole-based coatings generally provided the most effective protection after aging. Thin Pd over Cu yielded the best wetting results of the metallic coatings, with complete dissolution of the Pd overcoat and wetting of the underlying Cu by the flowing solder. Limited wetting was measured on the thicker Pd and Pd over Ni finishes, which were not completely dissolved by the molten solder. The immersion Au and Ag finishes yielded the lowest wetted lengths, respectively. These general differences in solderability were directly attributed to the type of surface finish which the solder came in contact with. The effects of circuit geometry, surface finish, stressing, and solder processing conditions are discussed.

  16. Advances in integrated photonic circuits for packet-switched interconnection

    NASA Astrophysics Data System (ADS)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  17. In Situ Electromigration in Cu-Sn and Ni-Sn Critical Solder Length for Three-Dimensional Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huang, Y. T.; Chen, C. H.; Lee, B. H.; Chen, H. C.; Wang, C. M.; Wu, Albert T.

    2016-09-01

    An in situ electromigration study has been conducted on U-groove Cu/Sn-3.5Ag/Cu and Ni/Sn-3.5Ag/Ni sandwich structures; the results were used to simulate microsolder joints passing current density of 1 × 104 A/cm2 at 150°C. The solder gap was only 15 μm, shorter than the critical length of Sn-3.5Ag solder. Backstress was proved to exist at critical solder lengths and to influence the electromigration mechanism. Theoretical calculations of the diffusivity of Cu and Ni in Sn solder indicated that the degree to which the dominant diffusion species (Cu or Ni atoms) diffused through the solder line is retarded by the backstress effect. The morphologies of intermetallic compounds (IMCs) were observed, and the grain boundaries in Sn solder were measured using electron backscatter diffraction to determine the kinetics of intermetallic growth. The results reveal that the unique electromigration characteristics of microbump joints, including the diffusivity, morphology, and backstress, can be determined. The retardation of atomic migration improves the reliability against electromigration.

  18. Welded solar cell interconnection

    NASA Technical Reports Server (NTRS)

    Stofel, E. J.; Browne, E. R.; Meese, R. A.; Vendura, G. J.

    1982-01-01

    The efficiency of the welding of solar-cell interconnects is compared with the efficiency of soldering such interconnects, and the cases in which welding may be superior are examined. Emphasis is placed on ultrasonic welding; attention is given to the solar-cell welding machine, the application of the welding process to different solar-cell configurations, producibility, and long-life performance of welded interconnects. Much of the present work has been directed toward providing increased confidence in the reliability of welding using conditions approximating those that would occur with large-scale array production. It is concluded that there is as yet insufficient data to determine which of three methods (soldering, parallel gap welding, and ultrasonic welding) provides the longest-duration solar panel life.

  19. Soldering tool heats workpieces and applies solder in one operation

    NASA Technical Reports Server (NTRS)

    Gudkese, V. W.

    1966-01-01

    Fountain-pen type soldering iron heats workpieces and applies solder to joints in densely packed electronics assemblies. The basic soldering tool is used with different-sized orifice tips, eliminating the need for an assortment of conventional soldering guns.

  20. Advanced soldering processes

    SciTech Connect

    Jellison, J.L.; Golden, J.; Frear, D.R.; Hosking, F.M.; Keicher, D.M.; Yost, F.G.

    1993-02-20

    Advanced soldering processes are discussed in a complete manner. The ability to meet the needs of electronic manufacturing, while addressing the environmental issues are challenging goals. Government regulations mandate the elimination of most solvents in solder flux removal. Alternative approaches to promoting wetting are discussed. Inert atmosphere soldering, acid vapor fluxless soldering, atomic and ionic hydrogen as reactive atmospheres, fluxless laser soldering in a controlled atmosphere are offered as soldering mechanisms for the future. Laser are discussed as alternate heat sources. Various types of lasers, advantages of lasers, and fiber optic beam delivery are considered.

  1. Soldering instrument safety improvements

    DOEpatents

    Kosslow, William J.; Giron, Ronald W.

    1996-01-01

    A safe soldering device includes a retractable heat shield which can be moved between a first position in which the solder tip of the device is exposed for soldering operation and a second position in which the solder tip is covered by the heat shield. Preferably, the heat shield is biased towards the second position and may be locked in the first position for ease of use. When the soldering device is equipped with a vacuum system, the heat shield may serve to guide the flow of gases and heat from the solder tip away from the work area. The heat shield is preferably made of non-heatsinking plastic.

  2. Laser forward transfer of solder paste for microelectronics fabrication

    NASA Astrophysics Data System (ADS)

    Mathews, Scott A.; Charipar, Nicholas A.; Auyeung, Ray C.; Kim, Heungsoo; Piqué, Alberto

    2015-03-01

    The progressive miniaturization of electronic devices requires an ever-increasing density of interconnects attached via solder joints. As a consequence, the overall size and spacing (or pitch) of these solder joint interconnects keeps shrinking. When the pitch between interconnects decreases below 200 μm, current technologies, such as stencil printing, find themselves reaching their resolution limit. Laser direct-write (LDW) techniques based on laser-induced forward transfer (LIFT) of functional materials offer unique advantages and capabilities for the printing of solder pastes. At NRL, we have demonstrated the successful transfer, patterning, and subsequent reflow of commercial Pb-free solder pastes using LIFT. Transfers were achieved both with the donor substrate in contact with the receiving substrate and across a 25 μm gap, such that the donor substrate does not make contact with the receiving substrate. We demonstrate the transfer of solder paste features down to 25 μm in diameter and as large as a few hundred microns, although neither represents the ultimate limit of the LIFT process in terms of spatial dimensions. Solder paste was transferred onto circular copper pads as small as 30 μm and subsequently reflowed, in order to demonstrate that the solder and flux were not adversely affected by the LIFT process.

  3. PWB solder wettability after simulated storage

    SciTech Connect

    Hernandez, C.L.; Hosking, F.M.

    1996-03-01

    A new solderability test method has been developed at Sandia National Laboratories that simulates the capillary flow physics of solders on circuit board surfaces. The solderability test geometry was incorporated on a circuit board prototype that was developed for a National Center for Manufacturing Sciences (NCMS) program. The work was conducted under a cooperative research and development agreement between Sandia National Laboratories, NCMS, and several PWB fabricators (AT&T, IBM, Texas Instruments, United Technologies/Hamilton Standard and Hughes Aircraft) to advance PWB interconnect technology. The test was used to investigate the effects of environmental prestressing on the solderability of printed wiring board (PWB) copper finishes. Aging was performed in a controlled chamber representing a typical indoor industrial environment. Solderability testing on as-fabricated and exposed copper samples was performed with the Sn-Pb eutectic solder at four different reflow temperatures (215, 230, 245 and 260{degrees}C). Rosin mildly activated (RMA), low solids (LS), and citric acid-based (CA) fluxes were included in the evaluation. Under baseline conditions, capillary flow was minimal at the lowest temperatures with all fluxes. Wetting increased with temperature at both baseline and prestressing conditions. Poor wetting, however, was observed at all temperatures with the LS flux. Capillary flow is effectively restored with the CA flux.

  4. Demonstration of heterogeneous III-V/Si integration with a compact optical vertical interconnect access.

    PubMed

    Ng, Doris Keh Ting; Wang, Qian; Pu, Jing; Lim, Kim Peng; Wei, Yongqiang; Wang, Yadong; Lai, Yicheng; Ho, Seng Tiong

    2013-12-15

    Heterogeneous III-V/Si integration with a compact optical vertical interconnect access is fabricated and the light coupling efficiency between the III-V/Si waveguide and the silicon nanophotonic waveguide is characterized. The III-V semiconductor material is directly bonded to the silicon-on-insulator (SOI) substrate and etched to form the III-V/Si waveguide for a higher light confinement in the active region. The compact optical vertical interconnect access is formed through tapering a III-V and an SOI layer in the same direction. The measured III-V/Si waveguide has a light coupling efficiency above ~90% to the silicon photonic layer with the tapering structure. This heterogeneous and light coupling structure can provide an efficient platform for photonic systems on chip, including passive and active devices.

  5. Exabits/s integrated photonic interconnection technology for flexible data-centric optical networks

    NASA Astrophysics Data System (ADS)

    Binh, Le N.; Tao, Thomas W.; Ning, Gordon L.

    2016-03-01

    Optical networking is evolving from classical service-provider base data-center centric (DCC) internetworking environment with massive capacity, hence demanding novel optical switching and interconnecting technologies. The traditional telecom networks are under a flattening transformation to meet challenges from DCC networks for massive capacity serving in order of multi-Pb/s. We present proposed distributed and concentric data center based networks and the essential optical interconnection technologies, from the photonic kernels to electronic and optoelectronic server clusters, in both passive and active structures. Optical switching devices and integrated matrices are proposed composing of tunable (bandwidth and center wavelength) optical filters and switches as well as resonant microring modulators (μRM)(switching and spectral demux/mux) for multi-wavelength flexible-bandwidth optical channels of aggregate capacity reaching Ebps. The design principles and some experimental results are also reported.

  6. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    PubMed

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

  7. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    PubMed

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers. PMID:27472614

  8. Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

    PubMed

    Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

    2016-06-22

    We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals. PMID:27250997

  9. Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

    PubMed

    Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

    2016-06-22

    We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals.

  10. [Interface interconnection and data integration in implementing of digital operating room].

    PubMed

    Feng, Jingyi; Chen, Hua; Liu, Jiquan

    2011-10-01

    The digital operating-room, with highly integrated clinical information, is very important for rescuing lives of patients and improving quality of operations. Since equipments in domestic operating-rooms have diversified interface and nonstandard communication protocols, designing and implementing an integrated data sharing program for different kinds of diagnosing, monitoring, and treatment equipments become a key point in construction of digital operating room. This paper addresses interface interconnection and data integration for commonly used clinical equipments from aspects of hardware interface, interface connection and communication protocol, and offers a solution for interconnection and integration of clinical equipments in heterogeneous environment. Based on the solution, a case of an optimal digital operating-room is presented in this paper. Comparing with the international solution for digital operating-room, the solution proposed in this paper is more economical and effective. And finally, this paper provides a proposal for the platform construction of digital perating-room as well as a viewpoint for standardization of domestic clinical equipments.

  11. Numerical simulation of CTE mismatch and thermal-structural stresses in the design of interconnects

    NASA Astrophysics Data System (ADS)

    Peter, Geoffrey John M.

    With the ever-increasing chip complexity, interconnects have to be designed to meet the new challenges. Advances in optical lithography have made chip feature sizes available today at 70 nm dimensions. With advances in Extreme Ultraviolet Lithography, X-ray Lithography, and Ion Projection Lithography it is expected that the line width will further decrease to 20 nm or less. With the decrease in feature size, the number of active devices on the chip increases. With higher levels of circuit integration, the challenge is to dissipate the increased heat flux from the chip surface area. Thermal management considerations include coefficient of thermal expansion (CTE) matching to prevent failure between the chip and the board. This in turn calls for improved system performance and reliability of the electronic structural systems. Experience has shown that in most electronic systems, failures are mostly due to CTE mismatch between the chip, board, and the solder joint (solder interconnect). The resulting high thermal-structural stress and strain due to CTE mismatch produces cracks in the solder joints with eventual failure of the electronic component. In order to reduce the thermal stress between the chip, board, and the solder joint, this dissertation examines the effect of inserting wire bundle (wire interconnect) between the chip and the board. The flexibility of the wires or fibers would reduce the stress at the rigid joints. Numerical simulations of two, and three-dimensional models of the solder and wire interconnects are examined. The numerical simulation is linear in nature and is based on linear isotropic material properties. The effect of different wire material properties is examined. The effect of varying the wire diameter is studied by changing the wire diameter. A major cause of electronic equipment failure is due to fatigue failure caused by thermal cycling, and vibrations. A two-dimensional modal and harmonic analysis was simulated for the wire interconnect

  12. Integrated receiver architectures for board-to-board free-space optical interconnects

    NASA Astrophysics Data System (ADS)

    Wu, Feiyang; Vj, Logeeswaran; Islam, M. Saif; Horsley, David A.; Walmsley, Robert G.; Mathai, Sagi; Houng, Denny; Tan, Michael R. T.; Wang, Shih-Yuan

    2009-06-01

    In many computer and server communications copper cables and wires are currently being used for data transmission and interconnects. However, due to significant shortcomings, such as long transmission time, high noise level, unstable electrical properties, and high power consumption for cooling, researchers are increasingly turning their research interests toward alternatives, such as fiber optic interconnects and free-space optical communication technologies. In this paper, we present design considerations for an integrated receiver for high-speed free-space line-of-sight optical interconnects for distortion-free data transmission in an environment with mechanical vibrations and air turbulences. The receiver consists of an array of high-speed photodiodes for data communication and an array of quadrant photodiodes for real-time beam tracking in order to compensate for the beam misalignment caused by vibrations in servers. Different configurations for spatially positioning the quadrant and data photodiodes are discussed for 4×4 and 9×9 multielement optical detector arrays. We also introduce a new beam tracking device, termed the strip quadrant photodiodes, in order to accurately track highly focused optical beams with very small beam diameter.

  13. Microstructural evolution during the thermomechanical fatigue of solder joints

    SciTech Connect

    Frear, D R

    1991-01-01

    Solder joints in electronic packages are electrical interconnections that also function as mechanical bonds. The solder often constrains materials of different coefficients of thermal expansion that, when thermal fluctuations are encountered, causes the solder joint to experience cyclical deformation. Due to the catastrophic consequences of electrical or mechanical failure of solder joints, a great deal of work has been performed to develop a better understanding of the metallurgical response of solder joints subjected to thermomechanical fatigue. This work reviews the microstructural and mechanical evolution that occurs in solder joints during thermomechanical fatigue. The eutectic Sn-Pb solder alloy is highlighted. Unlike most materials that experience thermomechanical fatigue, solder is commonly used at temperatures of up to nine-tenths of its melting point. Therefore extensive creep, solid state diffusion, recrystallization and grain growth occur in this alloy resulting in the evolution of a heterogeneous coarsened band through which failure eventually takes place. Two other solder alloys are compared with the Sn-Pb eutectic, a Pb-rich Sn-Pb alloy and a ternary near eutectic (40In-40Sn-20Pb, all alloys are given in wt. %). The Pb-rich alloy is a precipitated single phase matrix that does not evolve during thermomechanical fatigue and subsequently has a shorter lifetime. Conversely, the 40In-40Sn-20Pb solder is a two phase eutectic in which the microstructures refines during thermomechanical fatigue giving it a longer lifetime than the eutectic Sn-Pb solder. The microstructural processes that occur during thermomechanical fatigue and final fracture behavior are discussed for the three solder alloys. 47 refs., 14 figs.

  14. Integration of optoelectronic technologies for chip-to- chip interconnections and parallel pipeline processing

    NASA Astrophysics Data System (ADS)

    Wu, Jenming

    Digital information services such as multimedia systems and data communications require the processing and transfer of tremendous amount of data. These data need to be stored, accessed and delivered efficiently and reliably at high speed for various user applications. This represents a great challenge for current electronic systems. Electronics is effective in providing high performance processing and computation, but its input/outputs (I/Os) bandwidth is unable to scale with its processing power. The signal I/Os or interconnections are needed between processors and input devices, between processors for multiprocessor systems, and between processors and storage devices. Novel chip-to-chip interconnect technologies are needed to meet this challenge. This work integrates optoelectronic technologies for chip-to-chip interconnects and parallel pipeline processing. Photonic and electronic technologies are complementary to each other in the sense that electronics is more suitable for high-speed, low cost computation, and photonics is more suitable for high-bandwidth information transmission. Smart pixel technology uses electronics for logic switching and optics for chip-to- chip interconnects, thus combining the abilities of photonics and electronics nicely. This work describes both vertical and horizontal integration of smart pixel technologies for chip-to-chip optical interconnects and its applications. We present smart pixel VLSI designs in both hybrid CMOS/MQW smart pixel and monolithic GaAs smart pixel technologies. We use the CMOS/MQW technology for smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing. We have tested the chip and constructed a prototype system for device characterization and system demonstration. We have verified the functionality of the system and characterized the electrical functions of the chip and the optoelectronic properties of the MQW devices. We have developed algorithms that utilize SPARCL for various

  15. Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

    2001-01-01

    In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

  16. Hybrid microcircuit board assembly with lead-free solders

    SciTech Connect

    Vianco, P.T.; Hernandez, C.L.; Rejent, J.A.

    2000-01-11

    An assessment was made of the manufacturability of hybrid microcircuit test vehicles assembled using three Pb-free solder compositions 96.5Sn--3.5Ag (wt.%), 91.84Sn--3.33Ag--4.83Bi, and 86.85Sn--3.15Ag--5.0Bi--5.0Au. The test vehicle substrate was 96% alumina; the thick film conductor composition was 76Au--21Pt--3Pd. Excellent registration between the LCCC or chip capacitor packages and the thick film solder pads was observed. Reduced wetting of bare (Au-coated) LCCC castellations was eliminated by hot solder dipping the I/Os prior to assembly of the circuit card. The Pb-free solders were slightly more susceptible to void formation, but not to a degree that would significantly impact joint functionality. Microstructural damage, while noted in the Sn-Pb solder joints, was not observed in the Pb-free interconnects.

  17. Integrated optical interconnection for polymeric planar lightwave circuit device using roll-to-roll ultraviolet imprint

    NASA Astrophysics Data System (ADS)

    Cho, Sang Uk; Kang, Ho Ju; Chang, Sunghwan; Choi, Doo-sun; Kim, Chang-Seok; Jeong, Myung Yung

    2014-08-01

    We propose an integrated structure that combines chip and fiber array blocks for optical interconnection with a polymeric planar lightwave circuit (PLC) device using the roll-to-roll imprint process. The fiber array blocks and PLC chip of the integrated structure are fabricated on the same substrate, and the alignments in the three spatial directions were established with the insertion of an optical fiber. The characteristics of the integrated structure were evaluated by fabricating a 1×2 optical splitter device. The structure had an insertion loss of 3.9 dB, and the optical uniformity of the channel was 0.1 dB, indicating that the same performance for an active alignment can be expected.

  18. Soldering instrument safety improvements

    SciTech Connect

    Kosslow, W.J.; Giron, R.W.

    1994-12-31

    It is an object of the present invention to make soldering instruments safer and easier to use. According to one aspect of the present invention, a non-heatsinking, protective shield is provided around the soldering tip of the solder iron. This heat shield covers the iron`s hot tip throughout the soldering process with the exception of the time needed to perform an actual solder connection using the tip. The shield protects the user or nearby personnel from harm when the soldering iron is at elevated temperatures (500{degrees}F to 800{degrees}F).Moreover, the shield is capable of preventing fires which might result if the iron`s tip inadvertently comes into contact with an object that can be easily ignited, e.g. paper. In addition, an air vacuum system is incorporated into the shield to remove the solder smoke.

  19. Integration of robust fluidic interconnects using metal to glass anodic bonding

    NASA Astrophysics Data System (ADS)

    Briand, Danick; Weber, Patrick; de Rooij, Nicolaas F.

    2005-09-01

    This paper reports on the encapsulation of a piezoresistive silicon/Pyrex liquid flow sensor using metal to glass anodic bonding. The bonding technique allowed integrating robust metallic microfluidic interconnects and eliminating the use of glue and O-rings. The bonding parameters of a silicon/Pyrex/metal triple stack were chosen to minimize the residual stress and to obtain a strong and liquid tight bonding interface. The silicon/Pyrex liquid flow sensor was successfully bonded to metallic plates of Kovar and Alloy 42, on which tubes were fixed and a printed circuit board (PCB) was integrated. A post-bonding annealing procedure was developed to reduce the residual bonding stress. The characteristics of the encapsulated liquid flow sensor, such as the temperature coefficient of sensitivity, fulfilled the specifications. Wafer level packaging using metal to glass anodic bonding was considered to reduce the packaging size and cost.

  20. Integrated Energy-Water Planning in the Western and Texas Interconnections

    SciTech Connect

    Vincent Tidwell; John Gasper; Robert Goldstein; Jordan Macknick; Gerald Sehlke; Michael Webber; Mark Wigmosta

    2013-07-01

    While long-term regional electricity transmission planning has traditionally focused on cost, infrastructure utilization, and reliability, issues concerning the availability of water represent an emerging issue. Thermoelectric expansion must be considered in the context of competing demands from other water use sectors balanced with fresh and non-fresh water supplies subject to climate variability. An integrated Energy-Water Decision Support System (DSS) is being developed that will enable planners in the Western and Texas Interconnections to analyze the potential implications of water availability and cost for long-range transmission planning. The project brings together electric transmission planners (Western Electricity Coordinating Council and Electric Reliability Council of Texas) with western water planners (Western Governors’ Association and the Western States Water Council). This paper lays out the basic framework for this integrated Energy-Water DSS.

  1. Solderability test system

    DOEpatents

    Yost, Fred; Hosking, Floyd M.; Jellison, James L.; Short, Bruce; Giversen, Terri; Reed, Jimmy R.

    1998-01-01

    A new test method to quantify capillary flow solderability on a printed wiring board surface finish. The test is based on solder flow from a pad onto narrow strips or lines. A test procedure and video image analysis technique were developed for conducting the test and evaluating the data. Feasibility tests revealed that the wetted distance was sensitive to the ratio of pad radius to line width (l/r), solder volume, and flux predry time.

  2. Solderability test system

    DOEpatents

    Yost, F.; Hosking, F.M.; Jellison, J.L.; Short, B.; Giversen, T.; Reed, J.R.

    1998-10-27

    A new test method to quantify capillary flow solderability on a printed wiring board surface finish. The test is based on solder flow from a pad onto narrow strips or lines. A test procedure and video image analysis technique were developed for conducting the test and evaluating the data. Feasibility tests revealed that the wetted distance was sensitive to the ratio of pad radius to line width (l/r), solder volume, and flux predry time. 11 figs.

  3. Soldering In Space Investigation

    NASA Technical Reports Server (NTRS)

    2004-01-01

    This video captures Mike Fincke melting solder during the first set of planned In-Space Soldering Investigation (ISSI) experiments onboard the International Space Station (ISS). In the video, Fincke touches the tip of the soldering iron to a wire wrapped with rosin-core solder.Review of the experiment video revealed melting kinetics, wetting characteristics, and equilibrium shape attainment of the solder charge. The main photograph shows the results of feeding solder wire onto a heated surface. Here the solder is still attached with the spool seen floating in the foreground of the image. The inset photograph at right, shows a set of three simple melting experiments in which the solder, not affected by gravity, achieved an unexpected equilibrium football shape on the wire. Samples returned to Earth were examined for porosity and flux distribution as well as micro structural development. ISSI's purpose was to find out how solder behaves in a weightless environment and promote our knowledge of fabrication and repair techniques that might be employed during extended space exploration missions.

  4. Soldering In Space Investigation

    NASA Technical Reports Server (NTRS)

    2004-01-01

    This video captures Mike Fincke melting solder during the first set of planned In-Space Soldering Investigation (ISSI) experiments onboard the International Space Station (ISS). In the video, Fincke touches the tip of the soldering iron to a wire wrapped with rosin-core solder. Review of the experiment video revealed melting kinetics, wetting characteristics, and equilibrium shape attainment of the solder charge. The main photograph shows the results of feeding solder wire onto a heated surface. Here the solder is still attached with the spool seen floating in the foreground of the image. The inset photograph at right, shows a set of three simple melting experiments in which the solder, not affected by gravity, achieved an unexpected equilibrium football shape on the wire. Samples returned to Earth were examined for porosity and flux distribution as well as micro structural development. ISSI's purpose was to find out how solder behaves in a weightless environment and promote our knowledge of fabrication and repair techniques that might be employed during extended space exploration missions.

  5. An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.

    SciTech Connect

    Uribe, Fernando R.; Kilgo, Alice C.; Grazier, John Mark; Vianco, Paul Thomas; Zender, Gary L.; Hlava, Paul Frank; Rejent, Jerome Andrew

    2008-09-01

    The assembly of the BDYE detector requires the attachment of sixteen silicon (Si) processor dice (eight on the top side; eight on the bottom side) onto a low-temperature, co-fired ceramic (LTCC) substrate using 63Sn-37Pb (wt.%, Sn-Pb) in a double-reflow soldering process (nitrogen). There are 132 solder joints per die. The bond pads were gold-platinum-palladium (71Au-26Pt-3Pd, wt.%) thick film layers fired onto the LTCC in a post-process sequence. The pull strength and failure modes provided the quality metrics for the Sn-Pb solder joints. Pull strengths were measured in both the as-fabricated condition and after exposure to thermal cycling (-55/125 C; 15 min hold times; 20 cycles). Extremely low pull strengths--referred to as the low pull strength phenomenon--were observed intermittently throughout the product build, resulting in added program costs, schedule delays, and a long-term reliability concern for the detector. There was no statistically significant correlation between the low pull strength phenomenon and (1) the LTCC 'sub-floor' lot; (2) grit blasting the LTCC surfaces prior to the post-process steps; (3) the post-process parameters; (4) the conductor pad height (thickness); (5) the dice soldering assembly sequence; or (5) the dice pull test sequence. Formation of an intermetallic compound (IMC)/LTCC interface caused by thick film consumption during either the soldering process or by solid-state IMC formation was not directly responsible for the low-strength phenomenon. Metallographic cross sections of solder joints from dice that exhibited the low pull strength behavior, revealed the presence of a reaction layer resulting from an interaction between Sn from the molten Sn-Pb and the glassy phase at the TKN/LTCC interface. The thick film porosity did not contribute, explicitly, to the occurrence of reaction layer. Rather, the process of printing the very thin conductor pads was too sensitive to minor thixotropic changes to ink, which resulted in

  6. Intra-Chip Free-Space Optical Interconnect: System, Device, Integration and Prototyping

    NASA Astrophysics Data System (ADS)

    Ciftcioglu, Berkehan

    Currently, on-chip optical interconnect schemes already proposed utilize circuit switching using wavelength division multiplexing (WDM) or all-optical packet switching, all based on planar optical waveguides and related photonic devices such as microrings. These proposed approaches pose significant challenges in latency, energy efficiency, integration, and scalability. This thesis presents a new alternative approach by utilizing free-space optics. This 3-D integrated intra-chip free-space optical interconnect (FSOI) leverages mature photonic devices such as integrated lasers, photodiodes, microlenses and mirrors. It takes full advantages of the latest developments in 3-D integration technologies. This interconnect system provides point-to-point free-space optical links between any two communication nodes to construct an all-to-all intra-chip communication network with little or no arbitration. Therefore, it has significant networking advantages over conventional electrical and waveguide-based optical interconnects. An FSOI system is evaluated based on the real device parameters, predictive technology models and International Roadmap of Semiconductor's predictions. A single FSOI link achieves 10-Gbps data rate with 0.5-pJ/bit energy efficiency and less than 10--12 bit-error-rate (BER). A system using this individual link can provide scalability up to 36 nodes, providing 10-Tbps aggregate bandwidth. A comparison analysis performed between a WDM-based waveguide interconnect system and the proposed FSOI system shows that FSOI achieves better energy efficiency than the WDM one as the technology scales. Similarly, network simulation on a 16-core microprocessor using the proposed FSOI system instead of mesh networks has been shown to speed up the system by 12% and reduce the energy consumption by 33%. As a part of the development of a 3-D integrated FSOI system, operating at 850 nm with a 10-Gbps data rate per optical link, the photonics devices and optical components are

  7. Intra-Chip Free-Space Optical Interconnect: System, Device, Integration and Prototyping

    NASA Astrophysics Data System (ADS)

    Ciftcioglu, Berkehan

    Currently, on-chip optical interconnect schemes already proposed utilize circuit switching using wavelength division multiplexing (WDM) or all-optical packet switching, all based on planar optical waveguides and related photonic devices such as microrings. These proposed approaches pose significant challenges in latency, energy efficiency, integration, and scalability. This thesis presents a new alternative approach by utilizing free-space optics. This 3-D integrated intra-chip free-space optical interconnect (FSOI) leverages mature photonic devices such as integrated lasers, photodiodes, microlenses and mirrors. It takes full advantages of the latest developments in 3-D integration technologies. This interconnect system provides point-to-point free-space optical links between any two communication nodes to construct an all-to-all intra-chip communication network with little or no arbitration. Therefore, it has significant networking advantages over conventional electrical and waveguide-based optical interconnects. An FSOI system is evaluated based on the real device parameters, predictive technology models and International Roadmap of Semiconductor's predictions. A single FSOI link achieves 10-Gbps data rate with 0.5-pJ/bit energy efficiency and less than 10--12 bit-error-rate (BER). A system using this individual link can provide scalability up to 36 nodes, providing 10-Tbps aggregate bandwidth. A comparison analysis performed between a WDM-based waveguide interconnect system and the proposed FSOI system shows that FSOI achieves better energy efficiency than the WDM one as the technology scales. Similarly, network simulation on a 16-core microprocessor using the proposed FSOI system instead of mesh networks has been shown to speed up the system by 12% and reduce the energy consumption by 33%. As a part of the development of a 3-D integrated FSOI system, operating at 850 nm with a 10-Gbps data rate per optical link, the photonics devices and optical components are

  8. Reduced oxide soldering activation (ROSA) PWB solderability testing

    SciTech Connect

    Hernandez, C.L.; Hosking, F.M.; Reed, J.; Tench, D.M.; White, J.

    1996-02-01

    The effect of ROSA pretreatment on the solderability of environmentally stressed PWB test coupons was investigated. The PWB surface finish was an electroplated, reflowed solder. Test results demonstrated the ability to recover plated-through-hole fill of steam aged samples with solder after ROSA processing. ROSA offers an alternative method for restoring the solderability of aged PWB surfaces.

  9. Compound solder joints

    NASA Technical Reports Server (NTRS)

    Batista, R. I.; Simonson, R. B.

    1976-01-01

    Joining technique prevents contamination, may be used to join dissimilar metal tubes, minimizes fluid and gas entrapment, expedites repairs, and can yield joints having leakage rates less than 0.000001 standard cubic cm He/min. Components of joint are solder sleeve, two solder rings, Teflon sleeve, and tubing to be joined.

  10. Solder Reflow Failures in Electronic Components During Manual Soldering

    NASA Technical Reports Server (NTRS)

    Teverovsky, Alexander; Greenwell, Chris; Felt, Frederick

    2008-01-01

    This viewgraph presentation reviews the solder reflow failures in electronic components that occur during manual soldering. It discusses the specifics of manual-soldering-induced failures in plastic devices with internal solder joints. The failure analysis turned up that molten solder had squeezed up to the die surface along the die molding compound interface, and the dice were not protected with glassivation allowing solder to short gate and source to the drain contact. The failure analysis concluded that the parts failed due to overheating during manual soldering.

  11. Lead-free solder

    DOEpatents

    Anderson, Iver E.; Terpstra, Robert L.

    2001-05-15

    A Sn--Ag--Cu eutectic alloy is modified with one or more low level and low cost alloy additions to enhance high temperature microstructural stability and thermal-mechanical fatigue strength without decreasing solderability. Purposeful fourth or fifth element additions in the collective amount not exceeding about 1 weight % (wt. %) are added to Sn--Ag--Cu eutectic solder alloy based on the ternary eutectic Sn--4.7%Ag--1.7%Cu (wt. %) and are selected from the group consisting essentially of Ni, Fe, and like-acting elements as modifiers of the intermetallic interface between the solder and substrate to improve high temperature solder joint microstructural stability and solder joint thermal-mechanical fatigue strength.

  12. Removing Dross From Molten Solder

    NASA Technical Reports Server (NTRS)

    Webb, Winston S.

    1990-01-01

    Automatic device helps to assure good solder connections. Machine wipes dross away from area on surface of molten solder in pot. Sweeps across surface of molten solder somewhat in manner of windshield wiper. Each cycle of operation triggered by pulse from external robot. Equipment used wherever precise, automated soldering must be done to military specifications.

  13. Stress-relieved solder joints

    NASA Technical Reports Server (NTRS)

    Zemenick, C. J.

    1980-01-01

    Mechanical stress on solder joints is reduced by procedure for soldering electronic components to circuit boards. Procedure was developed for radio-frequency (RF) strip-line circuits, for which dimensions must be carefully controlled to minimize parasitic capacitance and inductance. Procedure consists of loosening component from its mounting after each lead is soldered relieving induced stresses before next soldering step.

  14. Solder Bonding for Power Transistors

    NASA Technical Reports Server (NTRS)

    Snytsheuvel, H. A.; Mandel, H.

    1985-01-01

    Indium solder boosts power rating and facilitates circuit changes. Efficient heat conduction from power transistor to heat sink provided by layer of indium solder. Low melting point of indium solder (141 degrees C) allows power transistor to be removed, if circuit must be reworked, without disturbing other components mounted with ordinary solder that melts at 181 degrees C. Solder allows devices operated at higher power levels than does conventional attachment by screws.

  15. Effects of pre-stressing and flux on the flow of solder on PWB copper surfaces

    SciTech Connect

    Hernandez, C.L.; Hosking, F.M.

    1994-12-31

    A variety of test methods are available to evaluate the solderability of printed wiring board [PWB] surface finishes. A new test has been developed which better simulates the capillary flow physics of typical solder assembly processing, especially surface mount soldering. The work was conducted under a cooperative research and development agreement between Sandia National Laboratories, the National Center for Manufacturing Sciences, and several PWB fabricators (AT&T, IBM, Texas Instruments, and United Technologies Corporation/Hamilton Standard) to advance PWB interconnect systems technology. Particular attention has been given at Sandia to characterizing the effects of accelerated aging in a simulated indoor industrial environment on subsequent PWB solderability. The program`s baseline surface finish was copper. Solderability testing on ``as-fabricated`` and ``pre-stressed copper`` pad-strip geometries was performed with Sn-Pb eutectic solder and three different fluxes at four different reflow temperatures.

  16. Thermal Stress of Surface Oxide Layer on Micro Solder Bumps During Reflow

    NASA Astrophysics Data System (ADS)

    Key Chung, C.; Zhu, Z. X.; Kao, C. R.

    2015-02-01

    Micro-bumps are now being developed with diameters smaller than 10 μm. At these dimensions, only very small amounts of solder are used to form the interconnections. Surface oxidation of such small micro-bumps is a critical issue. The key question is whether the oxide film on the solder bumps acts as a barrier to formation of solder joints. In this work, the mechanical stability of the oxide layer on solder bumps was investigated. Solder bumps with 35- μm radii were heated for different times. Auger electron spectroscopy was used to determine the thickness of the oxide layer on the solder bumps. Solder bumps with known oxide layer thicknesses were then heated in a low-oxygen environment (<50 ppm) until they melted. The mechanical stability of the oxide layer was observed by use of a high-speed camera. Results showed that a 14-nm-thick oxide layer on a solder bump of radius 35 μm was able to withstand the molten solder without cracking, leading to a non-wetting solder joint. A thermal stress model of the surface oxide layer revealed that the stress varied substantially with bump size and temperature, and increased almost linearly with temperature. Upon melting, the thermal stress on the oxide increased abruptly, because of the higher thermal expansion of molten solder compared with its solid state. On the basis of the experimental results and the thermal stress model of the oxide film, the maximum oxide thickness that can be tolerated to form a solder joint was determined, e.g. 14 nm oxide can support liquid solder, and thus lead to a non-wetting condition. This work provided a new method of determination of the maximum stress of oxide film for solder joint formation.

  17. Embrittlement of surface mount solder joints by hot solder-dipped, gold-plated leads

    SciTech Connect

    Vianco, P.T.

    1993-07-01

    The detachment of beam-leaded transistors from several surface mount circuit boards following modest thermal cycling was examined. Microstructural analysis of the package leads and bonding pads from the failed units indicated that gold embrittlement was responsible for a loss of solder joint mechanical integrity that caused detachment of transistors from the circuit boards. An analysis of the hot dipping process used to remove gold from the leads prior to assembly demonstrated that the gold, although dissolved from the lead, remained in the nearby solder and was subsequently retained in the coating formed on the lead upon withdrawal from the bath. This scenario allowed gold to enter the circuit board solder joints. It was hypothesized, and later confirmed by experimental trials, that increasing the number of dips prevented gold from entering the solder coatings.

  18. Solder dross removal apparatus

    NASA Technical Reports Server (NTRS)

    Webb, Winston S. (Inventor)

    1990-01-01

    An automatic dross removal apparatus is disclosed for removing dross from the surface of a solder bath in an automated electric component handling system. A rotatable wiper blade is positioned adjacent the solder bath which skims the dross off of the surface prior to the dipping of a robot conveyed component into the bath. An electronic control circuit causes a motor to rotate the wiper arm one full rotational cycle each time a pulse is received from a robot controller as a component approaches the solder bath.

  19. Solder dross removal apparatus

    NASA Technical Reports Server (NTRS)

    Webb, Winston S. (Inventor)

    1992-01-01

    An automatic dross removal apparatus (10) is disclosed for removing dross from the surface of a solder bath (22) in an automated electric component handling system. A rotatable wiper blade (14) is positioned adjacent the solder bath (22) which skims the dross off of the surface prior to the dipping of a robot conveyed component into the bath. An electronic control circuit (34) causes a motor (32) to rotate the wiper arm (14) one full rotational cycle each time a pulse is received from a robot controller (44) as a component approaches the solder bath (22).

  20. Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

    NASA Astrophysics Data System (ADS)

    Apostolopoulos, Dimitrios; Bakopoulos, Paraskevas; Kalavrouziotis, Dimitrios; Giannoulis, Giannis; Kanakis, Giannis; Iliadis, Nikos; Spatharakis, Christos; Bauwelinck, Johan; Avramopoulos, Hercules

    2014-03-01

    New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of opticalinterconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies.

  1. Detecting Defective Solder Bonds

    NASA Technical Reports Server (NTRS)

    Paulson, R.; Barney, J.; Decker, H. J.

    1984-01-01

    Method is noncontact and nondestructive. Technique detects solder bonds in solar array of other large circuit board, using thermal-imaging camera. Board placed between heat lamp and camera. Poor joints indiated by "cold" spots on the infrared image.

  2. Oahu Wind Integration and Transmission Study (OWITS): Hawaiian Islands Transmission Interconnection Project

    SciTech Connect

    Woodford, D.

    2011-02-01

    This report provides an independent review included an initial evaluation of the technical configuration and capital costs of establishing an undersea cable system and examining impacts to the existing electric transmission systems as a result of interconnecting the islands.

  3. Phase 2 Report: Oahu Wind Integration and Transmission Study (OWITS); Hawaiian Islands Transmission Interconnection Project

    SciTech Connect

    Woodford, D.

    2011-02-01

    This report provides an independent review including an initial evaluation of the technical configuration and capital costs of establishing an undersea cable system and examining impacts to the existing electric transmission systems as a result of interconnecting the islands

  4. SOLDERING OF ALUMINUM BASE METALS

    DOEpatents

    Erickson, G.F.

    1958-02-25

    This patent deals with the soldering of aluminum to metals of different types, such as copper, brass, and iron. This is accomplished by heating the aluminum metal to be soldered to slightly above 30 deg C, rubbing a small amount of metallic gallium into the part of the surface to be soldered, whereby an aluminum--gallium alloy forms on the surface, and then heating the aluminum piece to the melting point of lead--tin soft solder, applying lead--tin soft solder to this alloyed surface, and combining the aluminum with the other metal to which it is to be soldered.

  5. Standards in process: Foundation and profiles of ISDN (Integrated Services Digital Network) and OSI (Open Systems Interconnection) studies

    NASA Astrophysics Data System (ADS)

    Cerni, D. M.

    1984-12-01

    Telecommunication and computer technologies are merging, stimulating such global communication projects as the Integrated Services Digital Network (ISDN) and the Open Systems Interconnection (OSI) Reference Model. The systems of standards needed to ensure worldwide success of these projects are being developed. These efforts, of unprecedented complexity, are demanding an increase in knowledgeable dedicated standards workers. This report offers background material on the meaning, significance, and changing nature of standards and their development, both in the United States and internationally.

  6. Integrating III-V, Si, and polymer waveguides for optical interconnects: RAPIDO

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Harjanne, Mikko; Offrein, Bert-Jan; Caër, Charles; Neumeyr, Christian; Malacarne, Antonio; Guina, Mircea; Sheehan, Robert N.; Peters, Frank H.; Melanen, Petri

    2016-03-01

    We present a vision for the hybrid integration of advanced transceivers at 1.3 μm wavelength, and the progress done towards this vision in the EU-funded RAPIDO project. The final goal of the project is to make five demonstrators that show the feasibility of the proposed concepts to make optical interconnects and packet-switched optical networks that are scalable to Pb/s systems in data centers and high performance computing. Simplest transceivers are to be made by combining directly modulated InP VCSELs with 12 μm SOI multiplexers to launch, for example, 200 Gbps data into a single polymer waveguide with 4 channels to connect processors on a single line card. For more advanced transceivers we develop novel dilute nitride amplifiers and modulators that are expected to be more power-efficient and temperatureinsensitive than InP devices. These edge-emitting III-V chips are flip-chip bonded on 3 μm SOI chips that also have polarization and temperature independent multiplexers and low-loss coupling to the 12 μm SOI interposers, enabling to launch up to 640 Gbps data into a standard single mode (SM) fiber. In this paper we present a number of experimental results, including low-loss multiplexers on SOI, zero-birefringence Si waveguides, micron-scale mirrors and bends with 0.1 dB loss, direct modulation of VCSELs up to 40 Gbps, +/-0.25μm length control for dilute nitride SOA, strong band edge shifts in dilute nitride EAMs and SM polymer waveguides with 0.4 dB/cm loss.

  7. Soldering of Thin Film-Metallized Glass Substrates

    SciTech Connect

    Hosking, F.M.; Hernandez, C.L.; Glass, S.J.

    1999-03-31

    The ability to produce reliable electrical and structural interconnections between glass and metals by soldering was investigated. Soldering generally requires premetallization of the glass. As a solderable surface finish over soda-lime-silicate glass, two thin films coatings, Cr-Pd-Au and NiCr-Sn, were evaluated. Solder nettability and joint strengths were determined. Test samples were processed with Sn60-Pb40 solder alloy at a reflow temperature of 210 C. Glass-to-cold rolled steel single lap samples yielded an average shear strength of 12 MPa. Solder fill was good. Control of the Au thickness was critical in minimizing the formation of AuSn{sub 4} intermetallic in the joint, with a resulting joint shear strength of 15 MPa. Similar glass-to-glass specimens with the Cr-Pd-Au finish failed at 16.5 MPa. The NiCr-Sn thin film gave even higher shear strengths of 20-22.5 MPa, with failures primarily in the glass.

  8. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, D.B.

    1988-06-06

    Integrated circuit chips are electrically connected to a silicon wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability. 6 figs.

  9. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, David B.

    1991-01-01

    Integrated circuit chips are electrically connected to a silica wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin metal lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability.

  10. A new active solder for joining electronic components

    SciTech Connect

    SMITH,RONALD W.; VIANCO,PAUL T.; HERNANDEZ,CYNTHIA L.; LUGSCHEIDER,E.; RASS,I.; HILLEN,F.

    2000-05-11

    Electronic components and micro-sensors utilize ceramic substrates, copper and aluminum interconnect and silicon. The joining of these combinations require pre-metallization such that solders with fluxes can wet such combinations of metals and ceramics. The paper will present a new solder alloy that can bond metals, ceramics and composites. The alloy directly wets and bonds in air without the use flux or premetallized layers. The paper will present typical processing steps and joint microstructures in copper, aluminum, aluminum oxide, aluminum nitride, and silicon joints.

  11. Optical Backplane Interconnection

    NASA Technical Reports Server (NTRS)

    Hendricks, Herbert D.

    1991-01-01

    Optical backplane interconnection (OBIT), method of optically interconnecting many parallel outputs from data processor to many parallel inputs of other data processors by optically changing wavelength of output optical beam. Requires only one command: exact wavelength necessary to make connection between two desired processors. Many features, including smallness advantageous to incorporate OBIT into integrated optical device. Simplifies or eliminates wiring and speeds transfer of data over existing electrical or optical interconnections. Computer hookups and fiber-optical communication networks benefit from concept.

  12. Inconsistencies in the Understanding of Solder Joint Reliability Physics

    NASA Technical Reports Server (NTRS)

    Wen, L.; Mon, G. R.; Ross, R. G., Jr.

    1997-01-01

    Over the years, many analytical and experimental research studies have aimed to improve the state-of-the-art assessment of solder joint integrity from a physics-of-failure perspective. Although much progress has been made, there still exist many inconsistent and even contradictory correlations and conclusions. Before discussing some of the prominent inconsistencies found in the literature, this paper reviews the fundamental physics underlying the nature of solder failure...Using the complex constitutive properties of solder, fundamental mechanical and thermomechanical proccesses can be modeled to demonstrate some of the inconsistencies in the literature.

  13. Silver flip chip interconnect technology and solid state bonding

    NASA Astrophysics Data System (ADS)

    Sha, Chu-Hsuan

    -section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active

  14. Roles of interfacial reaction on mechanical properties of solder interfaces

    NASA Astrophysics Data System (ADS)

    Liu, Pilin

    This study investigated roles of interfacial reaction in fracture and fatigue of solder interconnects. The interfacial reaction phases in the as-reflowed and after aging were examined by cross-sectional transmission electron microscopy (TEM) while interfacial mechanical properties were determined from a flexural peel fracture mechanics technique. Because of their widespread uses in microelectronic packaging, SnPb solder interfaces, and Bi-containing Pb-free solder interfaces were chosen as the subjects of this study. In the interfacial reaction study, we observed a complicated micro structural evolution during solid-state aging of electroless-Ni(P)/SnPb solder interconnects. In as-reflowed condition, the interfacial reaction produced Ni3Sn 4 and P-rich layers. Following overaging, the interfacial microstructure degenerated into a complex multilayer structure consisting of multiple layers of Ni-Sn compounds and transformed Ni-P phases. In SnPb solder interfacial system, fatigue study showed that the overaging of the high P electroless Ni-P/SnPb interconnects resulted in a sharp reduction in the fatigue resistance of the interface in the high crack growth rate regime. Fracture mechanism analysis indicated that the sharp drop in fatigue resistance was triggered by the brittle fracture of the Ni3Sn2 intermetallic phase developed at the overaged interface. The fatigue behavior was strongly dependent on P concentration in electroless Ni. Kirkendall voids were found in the interfacial region after aging, but they did not cause premature fracture of the solder interfaces. In Bi-containing solder interfacial system, we found that Bi segregated to the Cu-intermetallic interface during aging in SnBi/Cu interconnect. This caused serious embrittlement of Sn-Bi/Cu interface. Further aging induced numerous voids along the Cu3Sn/Cu interface. These interfacial voids were different from Kirkendall voids. Their formation was explained on basis of vacancy condensation at the

  15. Heterogeneously integrated photonic-crystal lasers on silicon for on/off chip optical interconnects.

    PubMed

    Takeda, Koji; Sato, Tomonari; Fujii, Takuro; Kuramochi, Eiichi; Notomi, Masaya; Hasebe, Koichi; Kakitsuka, Takaaki; Matsuo, Shinji

    2015-01-26

    We demonstrate the continuous-wave operation of lambda-scale embedded active-region photonic-crystal (LEAP) lasers at room temperature, which we fabricated on a Si wafer. The on-Si LEAP lasers exhibit a threshold current of 31 μA, which is the lowest reported value for any type of semiconductor laser on Si. This reveals the great potential of LEAP lasers as light sources for on- or off-chip optical interconnects with ultra-low power consumption in future information communication technology devices including CMOS processors.

  16. A microstructural analysis of solder joints from the electronic assemblies of dismantled nuclear weapons

    SciTech Connect

    Vianco, P.T.; Rejent, J.A.

    1997-05-01

    MC1814 Interconnection Boxes from dismantled B57 bombs, and MC2839 firing Sets from retired W70-1 warheads were obtained from the Pantex facility. Printed circuit boards were selected from these components for microstructural analysis of their solder joints. The analysis included a qualitative examination of the solder joints and quantitative assessments of (1) the thickness of the intermetallic compound layer that formed between the solder and circuit board Cu features, and (2) the Pb-rich phase particle distribution within the solder joint microstructure. The MC2839 solder joints had very good workmanship qualities. The intermetallic compound layer stoichiometry was determined to be that of Cu6Sn5. The mean intermetallic compound layer thickness for all solder joints was 0.885 mm. The magnitude of these values did not indicate significant growth over the weapon lifetime. The size distribution of the Pb-rich phase particles for each of the joints were represented by the mean of 9.85 {times} 10{sup {minus}6} mm{sup 2}. Assuming a spherical geometry, the mean particle diameter would be 3.54 mm. The joint-to-joint difference of intermetallic compound layer thickness and Pb-rich particle size distribution was not caused by varying thermal environments, but rather, was a result of natural variations in the joint microstructure that probably existed at the time of manufacture. The microstructural evaluation of the through-hole solder joints form the MC2839 and MC1814 components indicated that the environmental conditions to which these electronic units were exposed in the stockpile, were benign regarding solder joint aging. There was an absence of thermal fatigue damage in MC2839 circuit board, through-hole solder joints. The damage to the eyelet solder joints of the MC1814 more likely represented infant mortality failures at or very near the time of manufacture, resulting from a marginal design status of this type of solder joint design.

  17. Method and apparatus for jetting, manufacturing and attaching uniform solder balls

    SciTech Connect

    Yost, Frederick G.; Frear, Darrel R.; Schmale, David T.

    1999-01-01

    An apparatus and process for jetting molten solder in the form of balls directly onto all the metallized interconnects lands for a ball grid array package in one step with no solder paste required. Molten solder is jetted out of a grid of holes using a piston attached to a piezoelectric crystal. When voltage is applied to the crystal it expands forcing the piston to extrude a desired volume of solder through holes in the aperture plate. When the voltage is decreased the piston reverses motion creating an instability in the molten solder at the aperture plate surface and thereby forming spherical solder balls that fall onto a metallized substrate. The molten solder balls land on the substrate and form a metallurgical bond with the metallized lands. The size of the solder balls is determined by a combination of the size of the holes in the aperture plate, the duration of the piston pulse, and the displacement of the piston. The layout of the balls is dictated by the location of the hooks in the grid. Changes in ball size and layout can be easily accomplished by changing the grid plate. This invention also allows simple preparation of uniform balls for subsequent supply to BGA users.

  18. Method and apparatus for jetting, manufacturing and attaching uniform solder balls

    DOEpatents

    Yost, F.G.; Frear, D.R.; Schmale, D.T.

    1999-01-05

    An apparatus and process are disclosed for jetting molten solder in the form of balls directly onto all the metallized interconnects lands for a ball grid array package in one step with no solder paste required. Molten solder is jetted out of a grid of holes using a piston attached to a piezoelectric crystal. When voltage is applied to the crystal it expands forcing the piston to extrude a desired volume of solder through holes in the aperture plate. When the voltage is decreased the piston reverses motion creating an instability in the molten solder at the aperture plate surface and thereby forming spherical solder balls that fall onto a metallized substrate. The molten solder balls land on the substrate and form a metallurgical bond with the metallized lands. The size of the solder balls is determined by a combination of the size of the holes in the aperture plate, the duration of the piston pulse, and the displacement of the piston. The layout of the balls is dictated by the location of the hooks in the grid. Changes in ball size and layout can be easily accomplished by changing the grid plate. This invention also allows simple preparation of uniform balls for subsequent supply to BGA users. 7 figs.

  19. Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

    DOEpatents

    Jansen, Kai W.; Maley, Nagi

    2000-01-01

    High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

  20. Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts

    DOEpatents

    Jansen, Kai W.; Maley, Nagi

    2001-01-01

    High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate. During production, the transparent conductive oxide layer of the front contact is scribed by a laser, then the amorphous silicon-containing semiconductors and inner layer of the dual layer back contact are simultaneously scribed and trenched (drilled) by the laser and the trench is subsequently filled with the same metal as the outer layer of the dual layer back contact to provide a superb mechanical and electrical interconnect between the front contact and the outer layer of the dual layer back contact. The outer layer of the dual layer back contact can then be scribed by the laser. For enhanced environmental protection, the photovoltaic modules can be encapsulated.

  1. High integrity interconnection of silver submicron/nanoparticles on silicon wafer by femtosecond laser irradiation.

    PubMed

    Huang, H; Sivayoganathan, M; Duley, W W; Zhou, Y

    2015-01-16

    Welding of nanomaterials is a promising technique for constructing nanodevices with robust mechanical properties. To date, fabrication of these devices is limited because of difficulties in restricting damage to the nanomaterials during the welding process. In this work, by utilizing very low fluence (∼900 μJ cm(-2)) femtosecond (fs) laser irradiation, we have produced a metallic interconnection between two adjacent silver (Ag) submicron/nanoparticles which were fixed on a silicon (Si) wafer after fs laser deposition. No additional filler material was used, and the connected particles remain almost damage free. Observation of the morphology before and after joining and finite difference time domain simulations indicate that the interconnection can be attributed to plasmonic excitation in the Ag submicron/nanoparticles. Concentration of energy between the particles leads to local ablation followed by re-deposition of the ablated material to form a bridging link that joins the two particles. This welding technique shows potential applications in the fabrication of nanodevices.

  2. High integrity interconnection of silver submicron/nanoparticles on silicon wafer by femtosecond laser irradiation

    NASA Astrophysics Data System (ADS)

    Huang, H.; Sivayoganathan, M.; Duley, W. W.; Zhou, Y.

    2015-01-01

    Welding of nanomaterials is a promising technique for constructing nanodevices with robust mechanical properties. To date, fabrication of these devices is limited because of difficulties in restricting damage to the nanomaterials during the welding process. In this work, by utilizing very low fluence (˜900 μJ cm-2) femtosecond (fs) laser irradiation, we have produced a metallic interconnection between two adjacent silver (Ag) submicron/nanoparticles which were fixed on a silicon (Si) wafer after fs laser deposition. No additional filler material was used, and the connected particles remain almost damage free. Observation of the morphology before and after joining and finite difference time domain simulations indicate that the interconnection can be attributed to plasmonic excitation in the Ag submicron/nanoparticles. Concentration of energy between the particles leads to local ablation followed by re-deposition of the ablated material to form a bridging link that joins the two particles. This welding technique shows potential applications in the fabrication of nanodevices.

  3. Capillary flow solder wettability test

    SciTech Connect

    Vianco, P.T.; Rejent, J.A.

    1996-01-01

    A test procedure was developed to assess the capillary flow wettability of solders inside of a confined geometry. The test geometry was comprised of two parallel plates with a controlled gap of constant thickness (0.008 cm, 0.018 cm, 0.025 cm, and 0.038 cm). Capillary flow was assessed by: (1) the meniscus or capillary rise of the solder within the gap, (2) the extent of void formation in the gap, and (3) the time-dependence of the risen solder film. Tests were performed with the lead-free solders.

  4. Alignability of Optical Interconnects

    NASA Astrophysics Data System (ADS)

    Beech, Russell Scott

    With the continuing drive towards higher speed, density, and functionality in electronics, electrical interconnects become inadequate. Due to optics' high speed and bandwidth, freedom from capacitive loading effects, and freedom from crosstalk, optical interconnects can meet more stringent interconnect requirements. But, an optical interconnect requires additional components, such as an optical source and detector, lenses, holographic elements, etc. Fabrication and assembly of an optical interconnect requires precise alignment of these components. The successful development and deployment of optical interconnects depend on how easily the interconnect components can be aligned and/or how tolerant the interconnect is to misalignments. In this thesis, a method of quantitatively specifying the relative difficulty of properly aligning an optical interconnect is described. Ways of using this theory of alignment to obtain design and packaging guidelines for optical interconnects are examined. The measure of the ease with which an optical interconnect can be aligned, called the alignability, uses the efficiency of power transfer as a measure of alignment quality. The alignability is related to interconnect package design through the overall cost measure, which depends upon various physical parameters of the interconnect, such as the cost of the components and the time required for fabrication and alignment. Through a mutual dependence on detector size, the relationship between an interconnect's alignability and its bandwidth, signal-to-noise ratio, and bit-error -rate is examined. The results indicate that a range of device sizes exists for which given performance threshold values are satisfied. Next, the alignability of integrated planar-optic backplanes is analyzed in detail. The resulting data show that the alignability can be optimized by varying the substrate thickness or the angle of reflection. By including the effects of crosstalk, in a multi-channel backplane, the

  5. Damage Produced in Solder Alloys during Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Liu, X. W.; Plumbridge, W. J.

    2007-09-01

    The anisotropy of tin is associated with significant variations in its coefficient of thermal expansion and elastic modulus, with crystallographic direction. Under pure thermal cycling (with no externally applied stress or strain), substantial strains, in excess of 100%, may develop locally, and for very small structures, such as soldered interconnections comprising a few grains, structural integrity may be adversely affected. To examine this possibility, freestanding samples of tin, Sn-3.5wt.%Ag, Sn-0.5wt.%Cu, and Sn-3.8wt.%Ag-0.7wt.%Cu, have been subjected to thermal cycling. Temperature cycles from 30°C to 125°C or from -40°C to 55°C initially caused surface cracking, with openings up to several tens of microns after 3,000 cycles. Subsequently, the surface cracks grew into the interior of the specimens, with the maximum penetration ranging from a few microns after 100 cycles to more than 200 μm after 3,000 cycles. The cracks initiated from damage accumulated along grain boundaries. For the same temperature range, less damage resulted after the lower maximum (or mean) temperature cycle, and there appears to be a thermally activated component of cracking. The microstructure produced by rapid cooling (water quenching) was slightly more resistant than that formed by air, or furnace, cooling. Apart from microstructural coarsening, no damage accrues from isothermal exposure alone.

  6. Modeling the Rate-Dependent Durability of Reduced-Ag SAC Interconnects for Area Array Packages Under Torsion Loads

    NASA Astrophysics Data System (ADS)

    Srinivas, Vikram; Menon, Sandeep; Osterman, Michael; Pecht, Michael G.

    2013-08-01

    Solder durability models frequently focus on the applied strain range; however, the rate of applied loading, or strain rate, is also important. In this study, an approach to incorporate strain rate dependency into durability estimation for solder interconnects is examined. Failure data were collected for SAC105 solder ball grid arrays assembled with SAC305 solder that were subjected to displacement-controlled torsion loads. Strain-rate-dependent (Johnson-Cook model) and strain-rate-independent elastic-plastic properties were used to model the solders in finite-element simulation. Test data were then used to extract damage model constants for the reduced-Ag SAC solder. A generalized Coffin-Manson damage model was used to estimate the durability. The mechanical fatigue durability curve for reduced-silver SAC solder was generated and compared with durability curves for SAC305 and Sn-Pb from the literature.

  7. Breakthrough: Lead-free Solder

    ScienceCinema

    Anderson, Iver

    2016-07-12

    Ames Laboratory senior metallurgist Iver Anderson explains the importance of lead-free solder in taking hazardous lead out of the environment by eliminating it from discarded computers and electronics that wind up in landfills. Anderson led a team that developed a tin-silver-copper replacement for traditional lead-tin solder that has been adopted by more than 50 companies worldwide.

  8. Breakthrough: Lead-free Solder

    SciTech Connect

    Anderson, Iver

    2012-01-01

    Ames Laboratory senior metallurgist Iver Anderson explains the importance of lead-free solder in taking hazardous lead out of the environment by eliminating it from discarded computers and electronics that wind up in landfills. Anderson led a team that developed a tin-silver-copper replacement for traditional lead-tin solder that has been adopted by more than 50 companies worldwide.

  9. Intermetallics Characterization of Lead-Free Solder Joints under Isothermal Aging

    NASA Astrophysics Data System (ADS)

    Choubey, Anupam; Yu, Hao; Osterman, Michael; Pecht, Michael; Yun, Fu; Yonghong, Li; Ming, Xu

    2008-08-01

    Solder interconnect reliability is influenced by environmentally imposed loads, solder material properties, and the intermetallics formed within the solder and the metal surfaces to which the solder is bonded. Several lead-free metallurgies are being used for component terminal plating, board pad plating, and solder materials. These metallurgies react together and form intermetallic compounds (IMCs) that affect the metallurgical bond strength and the reliability of solder joint connections. This study evaluates the composition and extent of intermetallic growth in solder joints of ball grid array components for several printed circuit board pad finishes and solder materials. Intermetallic growth during solid state aging at 100°C and 125°C up to 1000 h for two solder alloys, Sn-3.5Ag and Sn-3.0Ag-0.5Cu, was investigated. For Sn-3.5Ag solder, the electroless nickel immersion gold (ENIG) pad finish was found to result in the lowest IMC thickness compared to immersion tin (ImSn), immersion silver (ImAg), and organic solderability preservative (OSP). Due to the brittle nature of the IMC, a lower IMC thickness is generally preferred for optimal solder joint reliability. A lower IMC thickness may make ENIG a desirable finish for long-life applications. Activation energies of IMC growth in solid-state aging were found to be 0.54 ± 0.1 eV for ENIG, 0.91 ± 0.12 eV for ImSn, and 1.03 ± 0.1 eV for ImAg. Cu3Sn and Cu6Sn5 IMCs were found between the solder and the copper pad on boards with the ImSn and ImAg pad finishes. Ternary (Cu,Ni)6Sn5 intermetallics were found for the ENIG pad finish on the board side. On the component side, a ternary IMC layer composed of Ni-Cu-Sn was found. Along with intermetallics, microvoids were observed at the interface between the copper pad and solder, which presents some concern if devices are subject to shock and vibration loading.

  10. Simulation of Grain Growth in a Near-Eutectic Solder Alloy

    SciTech Connect

    TIKARE,VEENA; VIANCO,PAUL T.

    1999-12-16

    Microstructural evolution due to aging of solder alloys determines their long-term reliability as electrical, mechanical and thermal interconnects in electronics packages. The ability to accurately determine the reliability of existing electronic components as well as to predict the performance of proposed designs depends upon the development of reliable material models. A kinetic Monte Carlo simulation was used to simulate microstructural evolution in solder-class materials. The grain growth model simulated many of the microstructural features observed experimentally in 63Sn-37Pb, a popular near-eutectic solder alloy. The model was validated by comparing simulation results to new experimental data on coarsening of Sn-Pb solder. The computational and experimental grain growth exponent for two-phase solder was found to be much lower than that for normal, single phase grain growth. The grain size distributions of solders obtained from simulations were narrower than that of normal grain growth. It was found that the phase composition of solder is important in determining grain growth behavior.

  11. Leads integral with the internal interconnection that penetrate the molded wall of a package

    NASA Technical Reports Server (NTRS)

    Marley, J.

    1969-01-01

    Multiplicity of external ribbon leads makes possible connections to a sealed or encapsulated microassembly. The leads are integral with the internal connections on a single part that can be fabricated economically by fine-detail electroplating.

  12. In-situ study of electromigration-induced grain rotation in Pb-free solder joint by synchrotron microdiffraction

    SciTech Connect

    Chen, Kai; Tamura, Nobumichi; Tu, King-Ning

    2008-10-31

    The rotation of Sn grains in Pb-free flip chip solder joints hasn't been reported in literature so far although it has been observed in Sn strips. In this letter, we report the detailed study of the grain orientation evolution induced by electromigration by synchrotron based white beam X-ray microdiffraction. It is found that the grains in solder joint rotate more slowly than in Sn strip even under higher current density. On the other hand, based on our estimation, the reorientation of the grains in solder joints also results in the reduction of electric resistivity, similar to the case of Sn strip. We will also discuss the reason why the electric resistance decreases much more in strips than in the Sn-based solders, and the different driving force for the grain growth in solder joint and in thin film interconnect lines.

  13. An Evaluation of Prototype Circuit Boards Assembled with a Sn-Ag Bi Solder

    SciTech Connect

    ARTAKI,I.; RAY,U.; REJENT,JEROME A.; VIANCO,PAUL T.

    1999-09-01

    An evaluation was performed which examined the aging of surface mount solder joints assembled with 91.84Sn-3.33Ag-4.83Bi solder. Defect analysis of the as-fabricated test vehicles revealed excellent solderability, good package alignment, and a minimum number of voids. Continuous DC electrical monitoring of the solder joints did not reveal opens during as many as 10,000 thermal cycles (0 C, 100 C). The solder joints exhibited no significant degradation through 2500 cycles, based upon an absence of microstructural damage and sustained shear and pull strengths of chip capacitors and J-leaded solder joints, respectively. Thermal cycles of 5000 and 10,000 resulted in some surface cracking of the solder fillets and coatings. In a few cases, deeper cracks were observed in the thinner reaches of several solder fillets. There was no deformation or cracking in the solder located in the gap between the package I/O and the circuit board pad nor in the interior of the fillets, both locations that would raise concerns of joint mechanical integrity. A drop in the chip capacitor shear strength was attributed to crack growth near the top of the fillet.

  14. Porosity in collapsible Ball Grid Array solder joints

    SciTech Connect

    Gonzalez, C.A. |

    1998-05-01

    Ball Grid Array (BGA) technology has taken off in recent years due to the increased need for high interconnect density. Opposite to all the advantages BGA packages offer, porosity in collapsible BGA solder joints is often a major concern in the reliability of such packages. The effect of pores on the strength of collapsible BGA solder-joints was studied by manufacturing samples with different degrees of porosity and testing them under a shear load. It was found that the shear strength of the solder joints decreased in a linear fashion with increasing porosity. Failure occurred by internal necking of the interpore matrix. It was confirmed that entrapment of flux residues leads to porosity by manufacturing fluxless samples in a specially made furnace, and comparing them with samples assembled using flux. Also, contamination of Au electrodeposits (in substrate metallization) was determined to cause significant porosity. It was found that hard-Au (Co hardened Au) electrodeposits produce high degrees of porosity even in the absence of flux. Finally, increasing the time the solder spends in the molten state was proven to successfully decrease porosity.

  15. METHOD FOR SOLDERING NORMALLY NON-SOLDERABLE ARTICLES

    DOEpatents

    McGuire, J.C.

    1959-11-24

    Methods are presented for coating and joining materials which are considered difficult to solder by utilizing an abrasive wheel and applying a bar of a suitable coating material, such as Wood's metal, to the rotating wheel to fill the cavities of the abrasive wheel and load the wheel with the coating material. The surface of the base material is then rubbed against the loaded rotating wheel, thereby coating the surface with the soft coating metal. The coating is a cohesive bonded layer and holds the base metal as tenaciously as a solder holds to easily solderable metals.

  16. Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks.

    PubMed

    Jones, Adam M; DeRose, Christopher T; Lentine, Anthony L; Trotter, Douglas C; Starbuck, Andrew L; Norwood, Robert A

    2013-05-20

    We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap. PMID:23736422

  17. Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks.

    PubMed

    Jones, Adam M; DeRose, Christopher T; Lentine, Anthony L; Trotter, Douglas C; Starbuck, Andrew L; Norwood, Robert A

    2013-05-20

    We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap.

  18. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  19. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

  20. Integrated reconfigurable microring based silicon WDM receiver for on-chip optical interconnect

    NASA Astrophysics Data System (ADS)

    Shen, Ao; Qiu, Chen; Yang, Long-Zhi; Dai, Ting-Ge; Hao, Yin-Lei; Jiang, Xiao-Qing; Yang, Jian-Yi

    2015-05-01

    We demonstrate an integrated reconfigurable wavelength division multiplexing receiver on the silicon-on-insulator (SOI) platform. The receiver is composed of a 1 × 8 thermally tunable microring resonator filter and Ge-Si photodetectors. With low thermal tuning powers the channel allocation of the receiver can be reconfigured with high accuracy and flexibility. The thermal tuning efficiency is approximately 8 mW nm-1. We show eight-channel configurations with channel spacing of 100 GHz and 50 GHz and a configuration in which all eight channels cover an entire free spectral range of the ring with uniform channel spacing of 1.2 nm. Each channel can receive high-quality signals with a data rate of up to 13.5 Gb s-1 thus an aggregate data rate higher than 100 Gb s-1 can be achieved.

  1. 24-ch microlens-integrated no-polish connector for optical interconnection with polymer waveguides

    NASA Astrophysics Data System (ADS)

    Shiraishi, Takashi; Yagisawa, Takatoshi; Ikeuchi, Tadashi; Daikuhara, Osamu; Tanaka, Kazuhiro

    2013-02-01

    We successfully developed a new 24-ch optical connector for polymer waveguides. The connector consists of a transparent thermoplastic resin that has two rectangular slits on one side for alignment of the waveguide films and integrated microlens arrays on the other side for coupling to the MT connector. Two 12-ch waveguide films were cut to a 3-mm width. The thickness of each waveguide film was controlled at 100 μm. The waveguide films were inserted into the slits until they touched the bottom face of the slit. Ultraviolet curing adhesive was used to achieve a short hardening process. The expanded beam in the transparent material is focused by the microlens arrays formed on the connector surface. This lens structure enables assembly without the need for a polishing process. We designed the lens for coupling between a step-index 40-μm rectangular waveguide and a graded-index 50-μm fiber. We achieved low-loss optical coupling by designing a method of providing asymmetric magnification between the horizontal and vertical directions in order to compensate for the asymmetric numerical aperture of the waveguide. The typical measured coupling losses from/to the waveguide to/from the fiber were 1.2 dB and 0.6 dB, respectively. The total coupling loss was as small as that of a physical contact connection.

  2. Integration of new alignment mark designs in dual inlaid-copper interconnect processes

    NASA Astrophysics Data System (ADS)

    Warrick, Scott P.; Hinnen, Paul C.; van Haren, Richard J. F.; Smith, Chris J.; Megens, Henry J. L.; Fu, Chong-Cheng

    2002-07-01

    In a joint development program between ASML and Motorola a new set of alignment marks have been designed and tested using the ATHENA off-axis alignment system on the ASML scanner. The new marks were analyzed for improved robustness against varying wafer-processing conditions to verify improved overlay capability and stability. These new marks have been evaluated on a set of dual inlaid-copper short flow wafers, with layer stacks consisting of 180 nm technology generation dielectric materials. Typical process variation has been deliberately introduced as part of the designed experiment to study the performance robustness of the new alignment marks. This paper discusses the new mark design and the theoretical reasons for mark design and/or integration change. Results shown in this paper provide initial feedback as to the viability of new variations of ATHENA alignment marks, specifically the SSPM and VSPM. Included in the results is the investigation to further stabilization of alignment signal strength. New ideas that are currently under development, to increase alignment mark signal strength stability, are discussed.

  3. Characteristics of Al substituted nanowires fabricated by self-aligned growth for future large scale integration interconnects

    NASA Astrophysics Data System (ADS)

    Kudo, Hiroshi; Kurahashi, Teruo

    2011-06-01

    Substituted Al nanowires for use in future large scale integration interconnects were fabricated by self-aligned growth. The resistivity of an Al substituted nanowire 80 nm in width, 100 nm in height, and 20 μm in length was 4.7 μΩ cm, which is 48% lower than that of an Al nanowire with the same dimensions fabricated using a bottom-up approach. The variation in the resistivity was in a narrow range (14%) over a Si wafer. The TEM imaging revealed that the Al substituted nanowire had a bamboo-like structure with grains larger than 1.6 μm. The electromigration activation energy was 0.72 eV, which is comparable to that of a pure Al wire with a bamboo-like structure. The product of the critical current density and wire length was 1.3 × 103 A/cm at 250 °C; 2.1 times higher than that of a pure Al wire with a polycrystalline structure. The acceleration of electromigration due to current density was 2.0, indicating that incubation time dominates electromigration lifetime. The prolonged incubation time observed in the electromigration test is attributed to the reduction in electromigration-induced mass transport due to the microstructure of the Al substituted nanowire. Even the formation of a small void immediately after incubation may be a fatal defect for nanoscale Al wires.

  4. Integrated Energy-Water Planning in the Western and Texas Interconnections (Invited)

    NASA Astrophysics Data System (ADS)

    Tidwell, V. C.

    2013-12-01

    While thermoelectric power generation accounts for less than one percent of total water consumption in the western U.S, steady growth in demand is projected for this sector. Complexities and heterogeneity in water supply, water demand, and institutional controls make water development a challenging proposition throughout the West. A consortium of National Laboratories, the University of Texas and the Electric Power Research Institute are working with the Western Governors' Association and Western States Water Council to assist the Western Electricity Coordinating Council and the Electric Reliability Council of Texas to integrate water related issues into long-term transmission planning. Specifically, water withdrawal and consumption have been estimated for each western power plant and their susceptibility to climate impacts assessed. To assist with transmission planning, water availability and cost data have been mapped at the 8-digit Hydrologic Unit Code level for the conterminous western U.S. (1208 watersheds). Five water sources were individually considered, including unappropriated surface water, unappropriated groundwater, appropriated water, municipal wastewater and brackish groundwater. Also mapped is projected growth in consumptive water demand to 2030. The relative costs (capital and O&M) to secure, convey, and treat the water as necessary have also been estimated for each source of water. These data configured into watershed level supply curves were subsequently used to constrain West-wide transmission planning. Results across a range of alternative energy futures indicate the impact of water availability and cost on the makeup and siting of future power generation. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. Water budgets at a 8

  5. Some Observations of Solder Joint Failure Under Tensile-Compressive Stress

    NASA Technical Reports Server (NTRS)

    Winslow, J. W.

    1993-01-01

    It has long been known that solder joints under mechanical stress are subject to failure. In early electronic systems, such failures were avoided primarily by avoiding the use of solder as a mechanical structural component. The rule was to first make sound wire connections that did not depend mechanically on solder, and only then to solder them. Careful design and miniaturization in modern electronic systems limits the mechanical stresses exerted on solder joints to values less than their yield points, and these joints have become integral parts of the mechanical structures. Unfortunately, while these joints are strong enough when new, they have proven vulnerable to fatigue failures as they age.Details of the fatigue process are poorly understood, making predictions of expected lifetimes difficult.

  6. Refinement of the Microstructure of Sn-Ag-Bi-In Solder, by Addition of SiC Nanoparticles, to Reduce Electromigration Damage Under High Electric Current

    NASA Astrophysics Data System (ADS)

    Kim, Youngseok; Nagao, Shijo; Sugahara, Tohru; Suganuma, Katsuaki; Ueshima, Minoru; Albrecht, Hans-Juergen; Wilke, Klaus; Strogies, Joerg

    2014-12-01

    The trends of miniaturization, multi-functionality, and high performance in advanced electronic devices require higher densities of I/O gates and reduced area of soldering of interconnections. This increases the electric current density flowing through the interconnections, increasing the risk of interconnection failure caused by electromigration (EM). Accelerated directional atomic diffusion in solder materials under high current induces substantial growth of intermetallic compounds (IMCs) at the anode, and also void and crack formation at the cathode. In the work discussed in this paper, addition of SiC nanoparticles to Sn-Ag-Bi-In (SABI) lead-free solder refined its microstructure and improved its EM reliability under high current stress. Electron backscattering diffraction analysis revealed that the added SiC nanoparticles refined solder grain size after typical reflow. Under current stress, SABI joints with added nano-SiC had lifetimes almost twice as long as those without. Comparison of results from high-temperature aging revealed direct current affected evolution of the microstructure. Observations of IMC growth indicated that diffusion of Cu in the SiC composite solder may not have been reduced. During current flow, however, only narrow voids were formed in solder containing SiC, thus preventing the current crowding caused by bulky voids in the solder without SiC.

  7. Description of a solder pulse generator for the single step formation of ball grid arrays

    SciTech Connect

    Schmale, D.T.; Frear, D.R.; Yost, F.G.; Essien, M.

    1997-02-01

    The traditional geometry for surface mount devices is the peripheral array where the leads are on the edges of the device. As the technology drives towards high input/output (I/O) count (increasing number of leads) and smaller packages with finer pitch (less distance between peripheral leads), limitations on peripheral surface mount devices arise. The leads on these fine pitch devices are fragile and can be easily bent. It becomes increasingly difficult to deliver solder past to leads spaced as little as 0.012 inch apart. Too much solder mass can result in bridging between leads while too little solder can contribute to the loss of mechanical and electrical continuity. A solution is to shift the leads from the periphery of the device to the area under the device. This scheme is called areal array packaging and is exemplified by the ball grid array (BGA) package. A system has been designed and constructed to deposit an entire array of several hundred uniform solder droplets onto a printed circuit board in a fraction of a second. The solder droplets wet to the interconnect lands on a pc board and forms a basis for later application of a BGA device. The system consists of a piezoelectric solder pulse unit, heater controls, an inert gas chamber and an analog power supply/pulse unit.

  8. Wetting behavior of alternative solder alloys

    SciTech Connect

    Hosking, F.M.; Vianco, P.T.; Hernandez, C.L.; Rejent, J.A.

    1993-07-01

    Recent economic and environmental issues have stimulated interest in solder alloys other than the traditional Sn-Pb eutectic or near eutectic composition. Preliminary evaluations suggest that several of these alloys approach the baseline properties (wetting, mechanical, thermal, and electrical) of the Sn-Pb solders. Final alloy acceptance will require major revisions to existing industrial and military soldering specifications. Bulk alloy and solder joint properties are consequently being investigated to validate their producibility and reliability. The work reported in this paper examines the wetting behavior of several of the more promising commercial alloys on copper substrates. Solder wettability was determined by the meniscometer and wetting balance techniques. The wetting results suggest that several of the alternative solders would satisfy pretinning and surface mount soldering applications. Their use on plated through hole technology might be more difficult since the alloys generally did not spread or flow as well as the 60Sn-40Pb solder.

  9. Economical solder connections to thin films

    NASA Technical Reports Server (NTRS)

    Bass, J. A.; Gaddy, E. M.

    1979-01-01

    Soldering procedure, successfully tested for attaching leads to silicon solar cells, cover-glasses, is simple, inexpensive, and very effective in forming stable connection. Procedure uses solder of indium alloyed with either silver or tin.

  10. A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization

    SciTech Connect

    He, Yugui; Liu, Chaoyang; Feng, Jiwen; Wang, Dong; Chen, Fang; Liu, Maili; Zhang, Zhi; Wang, Chao

    2015-08-15

    High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately −170 for {sup 1}H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo {sup 1}H MRI at 0.35 T.

  11. A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization.

    PubMed

    He, Yugui; Feng, Jiwen; Zhang, Zhi; Wang, Chao; Wang, Dong; Chen, Fang; Liu, Maili; Liu, Chaoyang

    2015-08-01

    High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately -170 for (1)H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo (1)H MRI at 0.35 T. PMID:26329168

  12. A peripheral component interconnect express-based scalable and highly integrated pulsed spectrometer for solution state dynamic nuclear polarization

    NASA Astrophysics Data System (ADS)

    He, Yugui; Feng, Jiwen; Zhang, Zhi; Wang, Chao; Wang, Dong; Chen, Fang; Liu, Maili; Liu, Chaoyang

    2015-08-01

    High sensitivity, high data rates, fast pulses, and accurate synchronization all represent challenges for modern nuclear magnetic resonance spectrometers, which make any expansion or adaptation of these devices to new techniques and experiments difficult. Here, we present a Peripheral Component Interconnect Express (PCIe)-based highly integrated distributed digital architecture pulsed spectrometer that is implemented with electron and nucleus double resonances and is scalable specifically for broad dynamic nuclear polarization (DNP) enhancement applications, including DNP-magnetic resonance spectroscopy/imaging (DNP-MRS/MRI). The distributed modularized architecture can implement more transceiver channels flexibly to meet a variety of MRS/MRI instrumentation needs. The proposed PCIe bus with high data rates can significantly improve data transmission efficiency and communication reliability and allow precise control of pulse sequences. An external high speed double data rate memory chip is used to store acquired data and pulse sequence elements, which greatly accelerates the execution of the pulse sequence, reduces the TR (time of repetition) interval, and improves the accuracy of TR in imaging sequences. Using clock phase-shift technology, we can produce digital pulses accurately with high timing resolution of 1 ns and narrow widths of 4 ns to control the microwave pulses required by pulsed DNP and ensure overall system synchronization. The proposed spectrometer is proved to be both feasible and reliable by observation of a maximum signal enhancement factor of approximately -170 for 1H, and a high quality water image was successfully obtained by DNP-enhanced spin-echo 1H MRI at 0.35 T.

  13. Modified Spot Welder Solders Flat Cables

    NASA Technical Reports Server (NTRS)

    Haehner, Carl L.

    1992-01-01

    Soldering device, essentially modified spot welder, melts high-melting-temperature solders without damaging plastic insulation on flat electrical cables. Solder preform rests on exposed conductor of cable, under connector pin. Electrodes press pin/preform/conductor sandwich together and supply pulse of current to melt preform, bonding pin to conductor. Anvil acts as support and heat sink. Device used to solder flexible ribbon cables to subminiature pin connectors.

  14. Metal-interconnection-free integration of InGaN/GaN light emitting diodes with AlGaN/GaN high electron mobility transistors

    SciTech Connect

    Liu, Chao; Cai, Yuefei; Liu, Zhaojun; Ma, Jun; Lau, Kei May

    2015-05-04

    We report a metal-interconnection-free integration scheme for InGaN/GaN light emitting diodes (LEDs) and AlGaN/GaN high electron mobility transistors (HEMTs) by combining selective epi removal (SER) and selective epitaxial growth (SEG) techniques. SER of HEMT epi was carried out first to expose the bottom unintentionally doped GaN buffer and the sidewall GaN channel. A LED structure was regrown in the SER region with the bottom n-type GaN layer (n-electrode of the LED) connected to the HEMTs laterally, enabling monolithic integration of the HEMTs and LEDs (HEMT-LED) without metal-interconnection. In addition to saving substrate real estate, minimal interface resistance between the regrown n-type GaN and the HEMT channel is a significant improvement over metal-interconnection. Furthermore, excellent off-state leakage characteristics of the driving transistor can also be guaranteed in such an integration scheme.

  15. Metal-interconnection-free integration of InGaN/GaN light emitting diodes with AlGaN/GaN high electron mobility transistors

    NASA Astrophysics Data System (ADS)

    Liu, Chao; Cai, Yuefei; Liu, Zhaojun; Ma, Jun; Lau, Kei May

    2015-05-01

    We report a metal-interconnection-free integration scheme for InGaN/GaN light emitting diodes (LEDs) and AlGaN/GaN high electron mobility transistors (HEMTs) by combining selective epi removal (SER) and selective epitaxial growth (SEG) techniques. SER of HEMT epi was carried out first to expose the bottom unintentionally doped GaN buffer and the sidewall GaN channel. A LED structure was regrown in the SER region with the bottom n-type GaN layer (n-electrode of the LED) connected to the HEMTs laterally, enabling monolithic integration of the HEMTs and LEDs (HEMT-LED) without metal-interconnection. In addition to saving substrate real estate, minimal interface resistance between the regrown n-type GaN and the HEMT channel is a significant improvement over metal-interconnection. Furthermore, excellent off-state leakage characteristics of the driving transistor can also be guaranteed in such an integration scheme.

  16. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2013 CFR

    2013-01-01

    ... 16 Commercial Practices 1 2013-01-01 2013-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  17. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 16 Commercial Practices 1 2011-01-01 2011-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  18. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2012 CFR

    2012-01-01

    ... 16 Commercial Practices 1 2012-01-01 2012-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  19. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 16 Commercial Practices 1 2010-01-01 2010-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  20. 16 CFR 501.8 - Solder.

    Code of Federal Regulations, 2014 CFR

    2014-01-01

    ... 16 Commercial Practices 1 2014-01-01 2014-01-01 false Solder. 501.8 Section 501.8 Commercial Practices FEDERAL TRADE COMMISSION RULES, REGULATIONS, STATEMENT OF GENERAL POLICY OR INTERPRETATION AND... 500 § 501.8 Solder. Solder and brazing alloys containing precious metals when packaged and labeled...

  1. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ... 21 Food and Drugs 3 2013-04-01 2013-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  2. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ... 21 Food and Drugs 3 2011-04-01 2011-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  3. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 3 2010-04-01 2009-04-01 true Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  4. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2014 CFR

    2014-04-01

    ... 21 Food and Drugs 3 2014-04-01 2014-04-01 false Lead solders. 189.240 Section 189.240 Food and...-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in any container that makes use of...

  5. 21 CFR 189.240 - Lead solders.

    Code of Federal Regulations, 2012 CFR

    2012-04-01

    ... 21 Food and Drugs 3 2012-04-01 2012-04-01 false Lead solders. 189.240 Section 189.240 Food and... Addition to Human Food Through Food-Contact Surfaces § 189.240 Lead solders. (a) Lead solders are alloys of metals that include lead and are used in the construction of metal food cans. (b) Food packaged in...

  6. Laser micromachining of through via interconnects in active die for 3-D multichip module

    NASA Astrophysics Data System (ADS)

    Chu, D.; Miller, W. D.

    One method to increase density in integrated circuits (IC) is to stack die to create a 3-D multichip module (MCM). In the past, special post wafer processing was done to bring interconnects out to the edge of the die. The die were sawed, glued, and stacked. Special processing was done to create interconnects on the edge to provide for interconnects to each of the die. These processes require an IC type fabrication facility (fab) and special processing equipment. In contrast, we have developed packaging assembly methods to create vertical through vias in bond pads of active silicon die, isolate these vias, and metal fill these vias without the use of a special IC fab. These die with through vias can then be joined and stacked to create a 3-D MCM. Vertical through vias in active die are created by laser micromachining using a Nd:YAG laser. Besides the fundamental 1064 nm (infrared) laser wavelength of a Nd:YAG laser, modifications to our Nd:YAG laser allowed us to generate the second harmonic 532 nm (green) laser wavelength and fourth harmonic 266 nm (ultraviolet) laser wavelength in laser micromachining for these vias. Experiments were conducted to determine the best laser wavelengths to use for laser micromachining of vertical through vias in order to minimize damage to the active die. Via isolation experiments were done in order to determine the best method in isolating the bond pads of the die. Die thinning techniques were developed to allow for die thickness as thin as 50 microns. This would allow for high 3-D density when the die are stacked. A method was developed to metal fill the vias with solder using a wire bonder with solder wire.

  7. Laser micromachining of through via interconnects in active die for 3-D multichip module

    SciTech Connect

    Chu, D.; Miller, W.D.

    1995-09-01

    One method to increase density in integrated circuits (IC) is to stack die to create a 3-D multichip module (MCM). In the past, special post wafer processing was done to bring interconnects out to the edge of the die. The die were sawed, glued, and stacked. Special processing was done to create interconnects on the edge to provide for interconnects to each of the die. These processes require an IC type fabrication facility (fab) and special processing equipment. In contrast, we have developed packaging assembly methods to created vertical through vias in bond pads of active silicon die, isolate these vias, and metal fill these vias without the use of a special IC fab. These die with through vias can then be joined and stacked to create a 3-D MCM. Vertical through vias in active die are created by laser micromachining using a Nd:YAG laser. Besides the fundamental 1064 nm (infra-red) laser wavelength of a Nd:YAG laser, modifications to our Nd:YAG laser allowed us to generate the second harmonic 532 nm (green) laser wavelength and fourth harmonic 266nm (ultra violet) laser wavelength in laser micromachining for these vias. Experiments were conducted to determine the best laser wavelengths to use for laser micromachining of vertical through vias in order to minimize damage to the active die. Via isolation experiments were done in order to determine the best method in isolating the bond pads of the die. Die thinning techniques were developed to allow for die thickness as thin as 50 {mu}m. This would allow for high 3-D density when the die are stacked. A method was developed to metal fill the vias with solder using a wire bonder with solder wire.

  8. Solder Joint Health Monitoring Testbed

    NASA Technical Reports Server (NTRS)

    Delaney, Michael M.; Flynn, James G.; Browder, Mark E.

    2009-01-01

    A method of monitoring the health of selected solder joints, called SJ-BIST, has been developed by Ridgetop Group Inc. under a Small Business Innovative Research (SBIR) contract. The primary goal of this research program is to test and validate this method in a flight environment using realistically seeded faults in selected solder joints. An additional objective is to gather environmental data for future development of physics-based and data-driven prognostics algorithms. A test board is being designed using a Xilinx FPGA. These boards will be tested both in flight and on the ground using a shaker table and an altitude chamber.

  9. Low-temperature solder for joining large cryogenic structures. [cooling cools for the National Transonic Facility

    NASA Technical Reports Server (NTRS)

    Buckley, J. D.; Sandefur, P. G., Jr.

    1980-01-01

    Three joining methods were considered for use in fabricating cooling coils for the National Transonic Facility. After analysis and preliminary testing, soldering was chosen as the cooling coil joining technique over mechanical force fit and brazing techniques. Charpy V-Notch tests, cyclic thermal tests (ambient to 77.8 K) and tensile tests at cryogenic temperatures were performed on solder joints to evaluate their structural integrity. It was determined that low temperature solder can be used to ensure good fin-to-tube contact for cooling-coil applications.

  10. Universal solders for direct and powerful bonding on semiconductors, diamond, and optical materials

    NASA Astrophysics Data System (ADS)

    Mavoori, Hareesh; Ramirez, Ainissa G.; Jin, Sungho

    2001-05-01

    The surfaces of electronic and optical materials such as nitrides, carbides, oxides, sulfides, fluorides, selenides, diamond, silicon, and GaAs are known to be very difficult to bond with low melting point solders (<300 °C). We have achieved a direct and powerful bonding on these surfaces by using low temperature solders doped with rare-earth elements. The rare earth is stored in micron-scale, finely-dispersed intermetallic islands (Sn3Lu or Au4Lu), and when released, causes chemical reactions at the interface producing strong bonds. These solders directly bond to semiconductor surfaces and provide ohmic contacts. They can be useful for providing direct electrical contacts and interconnects in a variety of electronic assemblies, dimensionally stable and reliable bonding in optical fiber, laser, or thermal management assemblies.

  11. Research study: Device technology STAR router user's guide. [automated layout of large scale integration discretionary interconnection masks

    NASA Technical Reports Server (NTRS)

    Wright, R. A.

    1979-01-01

    The STAR Router program developed to perform automated layout of LSI discretionary interconnection masks is described. The input and output for the router are standard PR2D data files. A state-of-the-art cellular path-finding procedure, based on Lee's algorithm, which produces fast, shortest distance routing of microcircuit net data is included.

  12. Development of Readout Interconnections for the Si-W Calorimeter of SiD

    SciTech Connect

    Woods, M.; Fields, R.G.; Holbrook, B.; Lander, R.L.; Moskaleva, A.; Neher, C.; Pasner, J.; Tripathi, M.; Brau, J.E.; Frey, R.E.; Strom, D.; Breidenbach, M.; Freytag, D.; Haller, G.; Herbst, R.; Nelson, T.; Schier, S.; Schumm, B.; /UC, Santa Cruz

    2012-09-14

    The SiD collaboration is developing a Si-W sampling electromagnetic calorimeter, with anticipated application for the International Linear Collider. Assembling the modules for such a detector will involve special bonding technologies for the interconnections, especially for attaching a silicon detector wafer to a flex cable readout bus. We review the interconnect technologies involved, including oxidation removal processes, pad surface preparation, solder ball selection and placement, and bond quality assurance. Our results show that solder ball bonding is a promising technique for the Si-W ECAL, and unresolved issues are being addressed.

  13. Repairable chip bonding/interconnect process

    DOEpatents

    Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

    1997-01-01

    A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

  14. Repairable chip bonding/interconnect process

    DOEpatents

    Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

    1997-08-05

    A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

  15. Self assembled structures for 3D integration

    NASA Astrophysics Data System (ADS)

    Rao, Madhav

    Three dimensional (3D) micro-scale structures attached to a silicon substrate have various applications in microelectronics. However, formation of 3D structures using conventional micro-fabrication techniques are not efficient and require precise control of processing parameters. Self assembly is a method for creating 3D structures that takes advantage of surface area minimization phenomena. Solder based self assembly (SBSA), the subject of this dissertation, uses solder as a facilitator in the formation of 3D structures from 2D patterns. Etching a sacrificial layer underneath a portion of the 2D pattern allows the solder reflow step to pull those areas out of the substrate plane resulting in a folded 3D structure. Initial studies using the SBSA method demonstrated low yields in the formation of five different polyhedra. The failures in folding were primarily attributed to nonuniform solder deposition on the underlying metal pads. The dip soldering method was analyzed and subsequently refined. A modified dip soldering process provided improved yield among the polyhedra. Solder bridging referred as joining of solder deposited on different metal patterns in an entity influenced the folding mechanism. In general, design parameters such as small gap-spacings and thick metal pads were found to favor solder bridging for all patterns studied. Two types of soldering: face and edge soldering were analyzed. Face soldering refers to the application of solder on the entire metal face. Edge soldering indicates application of solder only on the edges of the metal face. Mechanical grinding showed that face soldered SBSA structures were void free and robust in nature. In addition, the face soldered 3D structures provide a consistent heat resistant solder standoff height that serve as attachments in the integration of dissimilar electronic technologies. Face soldered 3D structures were developed on the underlying conducting channel to determine the thermo-electric reliability of

  16. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  17. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  18. Investigation of welded interconnection of large area wraparound contacted silicon solar cells

    NASA Technical Reports Server (NTRS)

    Lott, D. R.

    1984-01-01

    An investigation was conducted to evaluate the welding and temperature cycle testing of large area 5.9 x 5.9 wraparound silicon solar cells utilizing printed circuit substrates with SSC-155 interconnect copper metals and the LMSC Infrared Controlled weld station. An initial group of 5 welded modules containing Phase 2 developmental 5.9 x 5.9 cm cells were subjected to cyclical temperatures of + or 80 C at a rate of 120 cycles per day. Anomalies were noted in the adhesion of the cell contact metallization; therefore, 5 additional modules were fabricated and tested using available Phase I cells with demonstrated contact integrity. Cycling of the later module type through 12,000 cycles indicated the viability of this type of lightweight flexible array concept. This project demonstrated acceptable use of an alternate interconnect copper in combination with large area wraparound cells and emphasized the necessity to implement weld pull as opposed to solder pull procedures at the cell vendors for cells that will be interconnected by welding.

  19. Characterization of solder flow on PWB surfaces

    SciTech Connect

    Hosking, F.M.; Yost, F.G.

    1995-07-01

    Different solderability tests have been developed to determine the wetting behavior of solder on metallic surfaces. None offer an exact measure of capillary flow associated with conventional mixed technology soldering. With shrinking package designs, increasing reliability requirements, and the emergence of new soldering technologies, there is a growing need to better understand and predict the flow of solder on printed wiring board (PWB) surfaces. Sandia National Laboratories has developed a capillary flow solderability test, through a joint effort with the National Center for Manufacturing Sciences, that considers this fundamental wetting issue for surface mount technology. The test geometry consists of a metal strip (width, {delta}) connected to a circular metal pad (radius, r{sub c}). Test methodology, experimental results, and validation of a flow model are presented in this paper.

  20. Microstructurally based thermomechanical fatigue lifetime model of solder joints for electronic applications

    SciTech Connect

    Frear, D.R.; Rashid, M.M.; Burchett, S.N.

    1993-07-01

    We present a new methodology for predicting the fatigue life of solder joints for electronics applications. This approach involves integration of experimental and computational techniques. The first stage involves correlating the manufacturing and processing parameters with the starting microstructure of the solder joint. The second stage involves a series of experiments that characterize the evolution of the microstructure during thermal cycling. The third stage consists of a computer modeling and simulation effort that utilizes the starting microstructure and experimental data to produce a reliability prediction of the solder joint. This approach is an improvement over current methodologies because it incorporates the microstructure and properties of the solder directly into the model and allows these properties to evolve as the microstructure changes during fatigue.

  1. Tin soldering of aluminum and its alloys

    NASA Technical Reports Server (NTRS)

    Gallo, Gino

    1921-01-01

    A method is presented for soldering aluminum to other metals. The method adopted consists of a galvanic application to the surface of the light-metal parts to be soldered, of a layer of another metal, which, without reacting electrolytically on the aluminum, adheres strongly to the surface to which it is applied, and is, on the other hand, adapted to receive the soft solder. The metal found to meet the criteria best was iron.

  2. Electrical interconnect

    DOEpatents

    Frost, John S.; Brandt, Randolph J.; Hebert, Peter; Al Taher, Omar

    2015-10-06

    An interconnect includes a first set of connector pads, a second set of connector pads, and a continuous central portion. A first plurality of legs extends at a first angle from the continuous central portion. Each leg of the first plurality of legs is connected to a connector pad of a first set of connector pads. A second plurality of legs extends at a second angle from the continuous central portion. Each leg of the second plurality of legs is connected to a connector pad of the second set of connector pads. Gaps are defined between legs. The gaps enable movement of the first set of connector pads relative to the second set of connector pads.

  3. Thermal Cycling Fatigue in DIPs Mounted with Eutectic Tin-Lead Solder Joints in Stub and Gullwing Geometries

    NASA Technical Reports Server (NTRS)

    Winslow, J. W.; Silveira, C. de

    1993-01-01

    It has long been known that solder joints under mechanical stress are subject to failure. In early electronic systems, such failures were avoided primarily by avoiding the use of solder as a mechanical structural component. The rule was first to make sound wire connections that did not depend mechanically on solder, and only then to solder them. Careful design and miniaturization in modern electronic systems limits the mechanical stresses exerted on solder joints to values less than their yield points, and these joints have become integral parts of the mechanical structures. Unfortunately, while these joints are strong enough when new, they have proven vulnerable to fatigue failures as they age. Details of the fatigue process are poorly understood, making predictions of expected lifetimes difficult.

  4. Release Resistant Electrical Interconnections For Mems Devices

    DOEpatents

    Peterson, Kenneth A.; Garrett, Stephen E.; Reber, Cathleen A.

    2005-02-22

    A release resistant electrical interconnection comprising a gold-based electrical conductor compression bonded directly to a highly-doped polysilicon bonding pad in a MEMS, IMEMS, or MOEMS device, without using any intermediate layers of aluminum, titanium, solder, or conductive adhesive disposed in-between the conductor and polysilicon pad. After the initial compression bond has been formed, subsequent heat treatment of the joint above 363 C creates a liquid eutectic phase at the bondline comprising gold plus approximately 3 wt % silicon, which, upon re-solidification, significantly improves the bond strength by reforming and enhancing the initial bond. This type of electrical interconnection is resistant to chemical attack from acids used for releasing MEMS elements (HF, HCL), thereby enabling the use of a "package-first, release-second" sequence for fabricating MEMS devices. Likewise, the bond strength of an Au--Ge compression bond may be increased by forming a transient liquid eutectic phase comprising Au-12 wt % Ge.

  5. Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices

    PubMed Central

    Sutanto, Jemmy; Anand, Sindhu; Patel, Chetan; Muthuswamy, Jit

    2013-01-01

    Flip-chip packaging is desirable for microelectro-mechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTVTM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking. PMID:24504168

  6. Intermetallic Layers in Soldered Joints

    1998-12-10

    ILAG solves the one-dimensional partial differential equations describing the multiphase, multicomponent, solid-state diffusion-controlled growth of intermetallic layers in soldered joints. This software provides an analysis capability for materials researchers to examine intermetallic growth mechanisms in a wide variety of defense and commercial applications involving both traditional and advanced materials. ILAG calculates the interface positions of the layers, as well as the spatial distribution of constituent mass fractions, and outputs the results at user-prescribed simulation times.

  7. Polarity effect of electromigration on mechanical properties of lead-free solder joints

    NASA Astrophysics Data System (ADS)

    Ren, Fei

    The trend of electronic packaging is to package the chips and the associated interconnections in a compact way that allows high speed operation; that allows for sufficient heat removal; that can withstand the thermal cycling associated with the turning on and turning off of the circuits; and that protects the circuits from environmental attack. These goals require that flip chip solder joints have higher resistance to electromigration, stronger mechanical property to sustain thermal mechanical stress, and are lead-free materials to satisfy environment and health concern. With lots of work on chemical reaction, electromigration and mechanical study in flip chip solder joints, however, the interaction between different driving forces is still little known. As a matter of fact, the combination study of chemical, electrical and mechanical is more and more significant to the understanding of the behavior of flip chip solder joints. In this dissertation, I developed one dimensional Cu (wire)-eutectic SnAgCu(ball)-Cu(wire) structure to investigate the interaction between electrical and mechanical force in lead-free solder joints. Electromigration was first conducted. The mechanical behaviors of solder joints before, after, and during electromigration were examined. Electrical current and mechanical stress were applied either in serial or in parallel to the solder joints. Tensile, creep, and drop tests, combined with different electrical current densities (1˜5x10 3A/cm2) and different stressing time (3˜144 hours), have been performed to study the effect of electromigration on the mechanical behavior of solder joints. Nano-indentation test was conducted to study the localized mechanical property of IMC at both interfaces in nanometer scale. Fracture images help analyze the failure mechanism of solder joints driven by both electrical and mechanical forces. The combination study shows a strain build-up during electromigration. Furthermore, a ductile-to-brittle transition in

  8. Liquid phase sintered composite solders for next generation thermal interface applications

    NASA Astrophysics Data System (ADS)

    Liu, Jia

    It is undeniable that electronics are becoming increasingly powerful and that there is continual effort towards miniaturization of these devices and thus increasing heat generation requires a new paradigm in thermal interface materials (TIM) design. This work was aimed at optimizing the processing parameters and characterizing the performance of Cu-In composite solders produced by liquid phase sintering (LPS). These composites comprise a high-melting phase (HMP) such as Cu embedded in a matrix of a low-melting phase (LMP) such as In. Copper contributes to high thermal and electrical conductivity of composites, whereas the soft In matrix helps maintain high shear compliance. This combination of high electrical/thermal conductivities and high shear compliance makes these solders suitable for a range of next-generation thermal interface material (TIM) and interconnect (IC) applications. After considering a range of compositions, a solder with 60 volume percent In was found to possess the requisite combination of high compliance and high conductivity. During the study, interfacial engineering was introduced to slow down the reaction between Cu and In, and hence further improve the performance of composite solders. A dual interfacial layer consisting of Al 2O3 and Au was used to mitigate the reaction between Cu and In. A 1 nm Al2O3 layer was used as a diffusion barrier to prohibit the inter-diffusion between Cu and In, while a 20 nm Au layer was coated on top of the ceramic Al2O3 for wetting enhancement. The dual layer increased the thermal conductivity of the solder by a factor of ˜2 while reducing the yield strength to make the solder more compliant. The effects of particle size, shape and volume fraction was also studied, and a simple model was utilized to explain the trends in the mechanical and the thermal properties. The optimized Cu-In composite solders were further used to study the performance of solder joints. Mechanical properties under shear and joint

  9. Advanced Interconnect Development

    SciTech Connect

    Yang, Z.G.; Maupin, G.; Simner, S.; Singh, P.; Stevenson, J.; Xia, G.

    2005-01-27

    The objectives of this project are to develop cost-effective, optimized materials for intermediate temperature SOFC interconnect and interconnect/electrode interface applications and identify and understand degradation processes in interconnects and at their interfaces with electrodes.

  10. Numerical and experimental study of residual stresses and thermal fatigue in soldered electronic assemblies

    NASA Astrophysics Data System (ADS)

    Bourcier, R. J.; Stephens, J. J.

    The assembly examined consists of thin plates of alumina, Kovar, 410 stainless steel and 6061 aluminum bonded together using layers of three different solder alloys: 63% Sn - 37% Pb, 50% Pb - 50% In and 40% In - 40% Sn - 20% Pb. Numerical simulation of the fabrication process was performed using a simplified axisymmetric finite element microcell model of the actual assembly. The alumina, Kovar, 410 stainless steel and 6061 aluminum layers were modeled as temperature-dependent elastic-plastic materials while the solder alloys were treated as creeping solids following solidification. Experimental testing of the solder alloys was used to generate input for the finite element code constitutive models. The numerical results of this study have provided guidelines for the successful fabrication of the subject assembly. In particular, slower cooling rates following solidification of the solders have been shown to dramatically lower bending stresses generated in the alumina plate. The experimental portion of the program has provided data on the degration of solder bond integrity used to thermal cycling and has identified possible important factors in the mechanical response of thin solder layers.

  11. Stretchable Si Logic Devices with Graphene Interconnects.

    PubMed

    Lee, Wonho; Jang, Houk; Jang, Bongkyun; Kim, Jae-Hyun; Ahn, Jong-Hyun

    2015-12-16

    Stretchable integrated circuits consisting of ultrathin Si transistors connected by multilayer graphene are demonstrated. Graphene interconnects act as an effective countervailing component to maintain the electrical performance of Si integrated circuits against external strain. Concentration of the applied strain on the graphene interconnect parts can stably protect the Si active devices against applied strains over 10%.

  12. Nano-soldering to single atomic layer

    DOEpatents

    Girit, Caglar O.; Zettl, Alexander K.

    2011-10-11

    A simple technique to solder submicron sized, ohmic contacts to nanostructures has been disclosed. The technique has several advantages over standard electron beam lithography methods, which are complex, costly, and can contaminate samples. To demonstrate the soldering technique graphene, a single atomic layer of carbon, has been contacted, and low- and high-field electronic transport properties have been measured.

  13. Experiments and Demonstrations with Soldering Guns.

    ERIC Educational Resources Information Center

    Henry, Dennis C.; Danielson, Sarah A.

    1993-01-01

    Discusses the essential electrical characteristics of a particular model of soldering gun. Presents four classroom demonstrations that utilize the soldering gun to test the following geometrics of wire loops as electromagnets: (1) the original tip; (2) a single circular loop; (3) a Helmholtz coil; and (4) the solenoid. (MDH)

  14. Interconnected semiconductor devices

    DOEpatents

    Grimmer, Derrick P.; Paulson, Kenneth R.; Gilbert, James R.

    1990-10-23

    Semiconductor layer and conductive layer formed on a flexible substrate, divided into individual devices and interconnected with one another in series by interconnection layers and penetrating terminals.

  15. Interconnection networks

    DOEpatents

    Faber, V.; Moore, J.W.

    1988-06-20

    A network of interconnected processors is formed from a vertex symmetric graph selected from graphs GAMMA/sub d/(k) with degree d, diameter k, and (d + 1)exclamation/ (d /minus/ k + 1)exclamation processors for each d greater than or equal to k and GAMMA/sub d/(k, /minus/1) with degree d /minus/ 1, diameter k + 1, and (d + 1)exclamation/(d /minus/ k + 1)exclamation processors for each d greater than or equal to k greater than or equal to 4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network GAMMA/sub d/(k, /minus/1) is provided, no processor has a channel connected to form an edge in a direction delta/sub 1/. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations. 9 figs.

  16. Solderability enhancement of copper through chemical etching

    SciTech Connect

    Stevenson, J.O.; Guilinger, T.R.; Hosking, F.M.; Yost, F.G.; Sorensen, N.R.

    1995-05-01

    Sandia National Laboratories has established a Cooperative Research and Development Agreement with consortium members of the National Center for Manufacturing Sciences (NCMS) to develop fundamental generic technology in the area of printed wiring board materials and surface finishes. Improved solderability of copper substrates is an important component of the Sandia-NCMS program. The authors are investigating the effects of surface roughness on the wettability and solderability behavior of several different types of copper board finishes. In this paper, the authors present roughness and solderability characterizations for a variety of chemically-etched copper substrates. Initial testing on six chemical etches demonstrate that surface roughness can be greatly enhanced through chemical etching. Noticeable improvements in solder wettability were observed to accompany increases in roughness. A number of different algorithms and measures of roughness were used to gain insight into surface morphologies that lead to improved solderability.

  17. Development of a Robust and Integrated Methodology for Predicting the Reliability of Microelectronic Packaging Systems

    NASA Astrophysics Data System (ADS)

    Fallah-Adl, Ali

    Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material, manufacturing process, use condition, as well as, the inherent variabilities present in the system, greatly influence product reliability. Accurate reliability analysis requires an integrated approach to concurrently account for all these factors and their synergistic effects. Such an integrated and robust methodology can be used in design and development of new and advanced microelectronics systems and can provide significant improvement in cycle-time, cost, and reliability. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks of (1) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, (2) Finite Element analysis (FEM) to predict system response needed for life prediction, and (3) development of a probabilistic methodology to predict the reliability, as well as, the sensitivity of the system to various parameters and the variabilities. These tasks and the predictive capabilities of IMPRPK in microelectronic reliability analysis are discussed.

  18. Solder flow on narrow copper strips

    SciTech Connect

    Hosking, F.M.; Yost, F.G.; Holm, E.A.; Michael, J.R.

    1996-07-01

    Various solderability tests have been developed over the years to quantify the wetting behavior of solder on metallic surfaces. None offer an exact measure of capillary flow normally associated with conventional plated-through-hole and surface mount soldering. With shrinking package designs, increasing reliability requirements, and the emergence of new soldering technologies, there is a growing need to better understand and predict the flow of solder on printed wiring board (PWB) surfaces. Sandia National Laboratories has developed a capillary flow solderability test, through a joint effort with the National Center for Manufacturing Sciences, that considers this fundamental wetting issue for surface mount technology. The test geometry consists of a metal strip (width, {delta}) connected to a circular metal pad (radius, r{sub c}). Solder flow from the pad onto the strip depends on the geometric relationship between {delta} and r{sub c}. Test methodology, experimental results, and validation of a flow model are presented in this paper. 17 refs., 11 figs., 4 tabs.

  19. Fatigue failure kinetics and structural changes in lead-free interconnects due to mechanical and thermal cycling

    NASA Astrophysics Data System (ADS)

    Fiedler, Brent Alan

    Environmental and human health concerns drove European parliament to mandate the Reduction of Hazardous Substances (RoHS) for electronics. This was enacted in July 2006 and has practically eliminated lead in solder interconnects. There is concern in the electronics packaging community because modern lead-free solder is rich in tin. Presently, near-eutectic tin-silver-copper solders are favored by industry. These solders are stiffer than the lead-tin near-eutectic alloys, have a higher melting temperature, fewer slip systems, and form intermetallic compounds (IMC) with Cu, Ni and Ag, each of which tend to have a negative effect on lifetime. In order to design more reliable interconnects, the experimental observation of cracking mechanisms is necessary for the correct application of existing theories. The goal of this research is to observe the failure modes resulting from mode II strain and to determine the damage mechanisms which describe fatigue failures in 95.5 Sn- 4.0 Ag - 0.5 Cu wt% (SAC405) lead-free solder interconnects. In this work the initiation sites and crack paths were characterized for SAC405 ball-grid array (BGA) interconnects with electroless-nickel immersion-gold (ENIG) pad-finish. The interconnects were arranged in a perimeter array and tested in fully assembled packages. Evaluation methods included monotonic and displacement controlled mechanical shear fatigue tests, and temperature cycling. The specimens were characterized using metallogaphy, including optical and electron microscopy as well as energy dispersive spectroscopy (EDS) and precise real-time electrical resistance structural health monitoring (SHM). In mechanical shear fatigue tests, strain was applied by the substrates, simulating dissimilar coefficients of thermal expansion (CTE) between the board and chip-carrier. This type of strain caused cracks to initiate in the soft Sn-rich solder and grow near the interface between the solder and intermetallic compounds (IMC). The growth near

  20. Comparison of Extensive Thermal Cycling Effects on Microstructure Development in Micro-alloyed Sn-Ag-Cu Solder Joints

    SciTech Connect

    Anderson, Iver E.; Boesenberg, Adam; Harringa, Joel; Riegner, David; Steinmetz, Andrew; Hillman, David

    2011-09-28

    Pb-free solder alloys based on the Sn-Ag-Cu (SAC) ternary eutectic have promise for widespread adoption across assembly conditions and operating environments, but enhanced microstructural control is needed. Micro-alloying with elements such as Zn was demonstrated for promoting a preferred solidification path and joint microstructure earlier in simple (Cu/Cu) solder joints studies for different cooling rates. This beneficial behavior now has been verified in reworked ball grid array (BGA) joints, using dissimilar SAC305 (Sn-3.0Ag-0.5Cu, wt.%) solder paste. After industrial assembly, BGA components joined with Sn-3.5Ag-0.74Cu-0.21Zn solder were tested in thermal cycling (-55 C/+125 C) along with baseline SAC305 BGA joints beyond 3000 cycles with continuous failure monitoring. Weibull analysis of the results demonstrated that BGA components joined with SAC + Zn/SAC305 have less joint integrity than SAC305 joints, but their lifetime is sufficient for severe applications in consumer, defense, and avionics electronic product field environments. Failure analysis of the BGA joints revealed that cracking did not deviate from the typical top area (BGA component side) of each joint, in spite of different Ag3Sn blade content. Thus, SAC + Zn solder has not shown any advantage over SAC305 solder in these thermal cycling trials, but other characteristics of SAC + Zn solder may make it more attractive for use across the full range of harsh conditions of avionics or defense applications.

  1. Improving student comprehension of the interconnectivity of the hydrologic cycle with a novel 'hydrology toolbox', integrated watershed model, and companion textbook

    NASA Astrophysics Data System (ADS)

    Huning, L. S.; Margulis, S. A.

    2013-12-01

    Concepts in introductory hydrology courses are often taught in the context of process-based modeling that ultimately is integrated into a watershed model. In an effort to reduce the learning curve associated with applying hydrologic concepts to real-world applications, we developed and incorporated a 'hydrology toolbox' that complements a new, companion textbook into introductory undergraduate hydrology courses. The hydrology toolbox contains the basic building blocks (functions coded in MATLAB) for an integrated spatially-distributed watershed model that makes hydrologic topics (e.g. precipitation, snow, radiation, evaporation, unsaturated flow, infiltration, groundwater, and runoff) more user-friendly and accessible for students. The toolbox functions can be used in a modular format so that students can study individual hydrologic processes and become familiar with the hydrology toolbox. This approach allows such courses to emphasize understanding and application of hydrologic concepts rather than computer coding or programming. While topics in introductory hydrology courses are often introduced and taught independently or semi-independently, they are inherently interconnected. These toolbox functions are therefore linked together at the end of the course to reinforce a holistic understanding of how these hydrologic processes are measured, interconnected, and modeled. They are integrated into a spatially-distributed watershed model or numerical laboratory where students can explore a range of topics such as rainfall-runoff modeling, urbanization, deforestation, watershed response to changes in parameters or forcings, etc. Model output can readily be visualized and analyzed by students to understand watershed response in a real river basin or a simple 'toy' basin. These tools complement the textbook, each of which has been well received by students in multiple hydrology courses with various disciplinary backgrounds. The same governing equations that students have

  2. Laser Assisted Soldering: Effects of Hydration on Solder-Tissue Adhesion

    SciTech Connect

    Chan, E.K.; Welch, A.J.; Brown, D.T.; Kovach, I.S.

    1998-10-01

    Wound stabilization is critical in early wound healing. Other than superficial skin wounds, most tissue repair is exposed to a hydrated environment postoperatively. To simulate the stability of laser-soldered tissue in a wet environment, we studied the effects of hydration on laser soldered rat dermis and baboon articular cartilage. In this {ital in vitro} study, we used a solder composed of human serum albumin, sodium hyaluronate, and Indocyanine Green. A 2 {mu}L solder droplet was deposited on each tissue specimen and then the solder was irradiated with a scanning laser beam (808 nm and 27thinspW/cm{sup 2}). After photocoagulation, each tissue specimen was cut into two halves dividing the solder. One half was reserved as control while the other half was soaked in saline for a designated period before fixation (1 h, 1, 2, and 7 days). All tissue specimens were prepared for scanning electron microscopy (SEM). SEM examinations revealed nonuniform coagulation across the solder thickness for most of the specimens, likely a result of the temperature gradient generated by laser heating. Closer to the laser beam, the uppermost region of the solder formed a dense coagulum. The solder aggregated into small globules in the region anterior to the solder-tissue interface. All cartilage specimens soaked in saline suffered coagulum detachment from tissue surface. We noted a high concentration of the protein globules in the detached coagulum. These globules were likely responsible for solder detachment from the cartilage surface. Solder adhered better to the dermis than to cartilage. The dermal layer of the skin, composed of collagen matrix, provided a better entrapment of the solder than the smooth surface of articular cartilage. Insufficient laser heating of solder formed protein globules. Unstable solder-tissue fusion was likely a result of these globules being detached from tissue substrate when the specimen was submerged in a hydrated environment. The solder-tissue bonding

  3. Role of W and Mn for reliable 1X nanometer-node ultra-large-scale integration Cu interconnects proved by atom probe tomography

    SciTech Connect

    Shima, K.; Shimizu, H.; Momose, T.; Shimogaki, Y.; Tu, Y.; Takamizawa, H.; Shimizu, Y.; Inoue, K.; Nagai, Y.

    2014-09-29

    We used atom probe tomography (APT) to study the use of a Cu(Mn) as a seed layer of Cu, and a Co(W) single-layer as reliable Cu diffusion barriers for future interconnects in ultra-large-scale integration. The use of Co(W) layer enhances adhesion of Cu to prevent electromigration and stress-induced voiding failures. The use of Cu(Mn) as seed layer may enhance the diffusion barrier performance of Co(W) by stuffing the Cu diffusion pass with Mn. APT was used to visualize the distribution of W and Mn in three dimensions with sub-nanometer resolution. W was found to segregate at the grain boundaries of Co, which prevents diffusion of Cu via the grain boundaries. Mn was found to diffuse from the Cu(Mn) layer to Co(W) layer and selectively segregate at the Co(W) grain boundaries with W, reinforcing the barrier properties of Co(W) layer. Hence, a Co(W) barrier coupled with a Cu(Mn) seed layer can form a sufficient diffusion barrier with film that is less than 2.0-nm-thick. The diffusion barrier behavior was preserved following a 1-h annealing at 400 °C. The underlayer of the Cu interconnects requires a large adhesion strength with the Cu, as well as low electrical resistivity. The use of Co(W) has previously been shown to satisfy these requirements, and addition of Mn is not expected to deteriorate these properties.

  4. Role of W and Mn for reliable 1X nanometer-node ultra-large-scale integration Cu interconnects proved by atom probe tomography

    NASA Astrophysics Data System (ADS)

    Shima, K.; Tu, Y.; Takamizawa, H.; Shimizu, H.; Shimizu, Y.; Momose, T.; Inoue, K.; Nagai, Y.; Shimogaki, Y.

    2014-09-01

    We used atom probe tomography (APT) to study the use of a Cu(Mn) as a seed layer of Cu, and a Co(W) single-layer as reliable Cu diffusion barriers for future interconnects in ultra-large-scale integration. The use of Co(W) layer enhances adhesion of Cu to prevent electromigration and stress-induced voiding failures. The use of Cu(Mn) as seed layer may enhance the diffusion barrier performance of Co(W) by stuffing the Cu diffusion pass with Mn. APT was used to visualize the distribution of W and Mn in three dimensions with sub-nanometer resolution. W was found to segregate at the grain boundaries of Co, which prevents diffusion of Cu via the grain boundaries. Mn was found to diffuse from the Cu(Mn) layer to Co(W) layer and selectively segregate at the Co(W) grain boundaries with W, reinforcing the barrier properties of Co(W) layer. Hence, a Co(W) barrier coupled with a Cu(Mn) seed layer can form a sufficient diffusion barrier with film that is less than 2.0-nm-thick. The diffusion barrier behavior was preserved following a 1-h annealing at 400 °C. The underlayer of the Cu interconnects requires a large adhesion strength with the Cu, as well as low electrical resistivity. The use of Co(W) has previously been shown to satisfy these requirements, and addition of Mn is not expected to deteriorate these properties.

  5. A study of thermal cycling and radiation effects on indium and solder bump bonding

    SciTech Connect

    Selcuk Cihangir et al.

    2001-09-12

    The BTeV hybrid pixel detector is constructed of readout chips and sensor arrays which are developed separately. The detector is assembled by flip-chip mating of the two parts. This method requires the availability of highly reliable, reasonably low cost fine-pitch flip-chip attachment technology. We have tested the quality of two bump-bonding technologies; indium bumps (by Advanced Interconnect Technology Ltd. (AIT) of Hong Kong) and fluxless solder bumps (by MCNC in North Carolina, USA). The results have been presented elsewhere[1]. In this paper we describe tests we performed to further evaluate these technologies. We subjected 15 indium bump-bonded and 15 fluxless solder bump-bonded dummy detectors through a thermal cycle and then a dose of radiation to observe the effects of cooling, heating and radiation on bump-bonds.

  6. An alternate interconnect method for joining flexible circuits using conductive adhesives

    SciTech Connect

    Schurman, W.R.

    1990-04-17

    Conductive adhesives were evaluated as a labor-saving alternate method for interconnecting flexible circuit layers in slapper detonators. Short-term aging, high temperature and high humidity storage, thermal cycle, and thermal shock studies were done. The adhesive interconnections were also studied under the high voltage and high current operating conditions of a slapper detonator. In all tests, interconnections made with conductive adhesive compared favorably with standard diffusion bonded joints, demonstrating the feasibility of joining flexible circuit components without metallic solders, brazes, thermo-compression bonds, diffusion bonds, or welds. 8 refs., 4 figs., 5 tabs.

  7. Design and analysis of tilt integral derivative controller with filter for load frequency control of multi-area interconnected power systems.

    PubMed

    Kumar Sahu, Rabindra; Panda, Sidhartha; Biswal, Ashutosh; Chandra Sekhar, G T

    2016-03-01

    In this paper, a novel Tilt Integral Derivative controller with Filter (TIDF) is proposed for Load Frequency Control (LFC) of multi-area power systems. Initially, a two-area power system is considered and the parameters of the TIDF controller are optimized using Differential Evolution (DE) algorithm employing an Integral of Time multiplied Absolute Error (ITAE) criterion. The superiority of the proposed approach is demonstrated by comparing the results with some recently published heuristic approaches such as Firefly Algorithm (FA), Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) optimized PID controllers for the same interconnected power system. Investigations reveal that proposed TIDF controllers provide better dynamic response compared to PID controller in terms of minimum undershoots and settling times of frequency as well as tie-line power deviations following a disturbance. The proposed approach is also extended to two widely used three area test systems considering nonlinearities such as Generation Rate Constraint (GRC) and Governor Dead Band (GDB). To improve the performance of the system, a Thyristor Controlled Series Compensator (TCSC) is also considered and the performance of TIDF controller in presence of TCSC is investigated. It is observed that system performance improves with the inclusion of TCSC. Finally, sensitivity analysis is carried out to test the robustness of the proposed controller by varying the system parameters, operating condition and load pattern. It is observed that the proposed controllers are robust and perform satisfactorily with variations in operating condition, system parameters and load pattern. PMID:26712682

  8. Alining Solder Pads on a Solar Cell

    NASA Technical Reports Server (NTRS)

    Lazzery, A. G.

    1984-01-01

    Mechanism consisting of stylus and hand-operated lever incorporated into screening machine to precisely register front and back solder pads during solar-cell assembly. Technique may interest those assembling solar cells manually for research or prototype work.

  9. High temperature solder device for flat cables

    NASA Technical Reports Server (NTRS)

    Haehner, Carl L. (Inventor)

    1992-01-01

    A high temperature solder device for flat cables includes a microwelder, an anvil which acts as a heat sink and supports a flexible flat ribbon cable that is to be connected to a multiple pin connector. The microwelder is made from a modified commercially available resistance welding machine such as the Split Tip Electrode microwelder by Weltek, which consists of two separate electrode halves with a removable dielectric spacer in between. The microwelder is not used to weld the items together, but to provide a controlled compressive force on, and energy pulse to, a solder preform placed between a pin of the connector and a conductor of the flexible flat ribbon cable. When the microwelder is operated, an electric pulse will flow down one electrode, through the solder preform and back up the other electrode. This pulse of electrical energy will cause the solder preform to heat up and melt, joining the pin and conductor.

  10. Synthesis of tin, silver and their alloy nanoparticles for lead-free interconnect applications

    NASA Astrophysics Data System (ADS)

    Jiang, Hongjin

    SnPb solders have long been used as interconnect materials in microelectronic packaging. Due to the health threat of lead to human beings, the use of lead-free interconnect materials is imperative. Three kinds of lead-free interconnect materials are being investigated, namely lead-free metal solders (SnAg, SnAgCu, etc.), electrically conductive adhesives (ECAs) and carbon nanotubes (CNTs). However, there are still limitations for the full utilization of these lead-free interconnect materials in the microelectronic packaging, such as higher melting point of lead-free metal solders, lower electrical conductivity of the ECAs and poor adhesion of CNTs to substrates. This thesis is devoted to the research and development of low processing temperature lead-free interconnect materials for microelectronic packaging applications with an emphasis on fundamental studies of nanoparticles synthesis, dispersion and oxidation prevention, and nanocomposites fabrication. Oxide-free tin (Sn), tin/silver (96.5Sn3.5Ag) and tin/silver/copper (96.5Sn3.0Ag0.5Cu) alloy nanoparticles with different sizes were synthesized by a low temperature chemical reduction method. Both size dependent melting point and latent heat of fusion of the synthesized nanoparticles were obtained. The nano lead-free solder pastes/composites created by dispersing the SnAg or SnAgCu alloy nanoparticles into an acidic type flux spread and wet on the cleaned copper surface at 220 to 230°C. This study demonstrated the feasibility of nano sized SnAg or SnAgCu alloy particle pastes for low processing temperature lead-free interconnect applications in microelectronic packaging.

  11. Shrink-Fit Solderable Inserts Seal Hermetically

    NASA Technical Reports Server (NTRS)

    Croucher, William C.

    1992-01-01

    Shrink-fit stainless-steel insert in aluminum equipment housing allows electrical connectors to be replaced by soldering, without degrading hermeticity of housing or connector. Welding could destroy electrostatic-sensitive components and harm housing and internal cables. Steel insert avoids problems because connector soldered directly to it rather than welded to housing. Seals between flange and housing, and between connector and flange resistant to leaks, even after mechanical overloading and thermal shocking.

  12. Fluxless soldering using activated acid vapors

    SciTech Connect

    Frear, D.R.; Keicher, D.M.

    1992-01-01

    Acid vapors have been used to fluxlessly reduce metal oxides and enhance wetting of solder on metallizations. Dilute solutions of hydrogen, acetic acid and formic acid in an inert carrier gas of nitrogen or argon were used with the sessile drop technique for 60Sn-40 Pb solder on Cu and Au/Ni metallizations. The time to reduce metal oxides and the extent of wetting as a function of acid vapor concentrations were characterized. Acetic and formic acids reduce the surface metal oxides sufficiently to form metallurgically sound solder joints. Hydrogen did not reduce oxides rapidly enough at 220{degree}C to be suitable for soldering applications. The optimum conditions for oxide reduction with formic acid was with an acid vapor concentration in nitrogen carrier gas of 4% for Cu metallizations and 1.6% on Au/Ni. The acetic acid vapor concentration, also in nitrogen, was optimized at 1.5% for both metallizations. Above a vapor concentration of 1.5%, the acetic acid combined with the bare metal to form acetates which increased the wetting time. These results indicate that acid vapor fluxless soldering is a viable alternative to traditional flux soldering.

  13. Whisker Formation on SAC305 Soldered Assemblies

    NASA Astrophysics Data System (ADS)

    Meschter, S.; Snugovsky, P.; Bagheri, Z.; Kosiba, E.; Romansky, M.; Kennedy, J.; Snugovsky, L.; Perovic, D.

    2014-11-01

    This article describes the results of a whisker formation study on SAC305 assemblies, evaluating the effects of lead-frame materials and cleanliness in different environments: low-stress simulated power cycling (50-85°C thermal cycling), thermal shock (-55°C to 85°C), and high temperature/high humidity (85°C/85% RH). Cleaned and contaminated small outline transistors, large leaded quad flat packs (QFP), plastic leaded chip carrier packages, and solder balls with and without rare earth elements (REE) were soldered to custom designed test boards with Sn3Ag0.5Cu (SAC305) solder. After assembly, all the boards were cleaned, and half of them were recontaminated (1.56 µg/cm2 Cl-). Whisker length, diameter, and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets, where the thickness is less than 25 µm, unless REE was present. The influence of lead-frame and solder ball material, microstructure, cleanliness, and environment on whisker characteristics is discussed. This article provides detailed metallurgical observations and select whisker length data obtained during this multiyear testing program.

  14. Microstructural influences on the mechanical properties of solder

    SciTech Connect

    Morris, J.W. Jr.; Goldstein, J.L.F.; Mei, Z.

    1993-04-01

    Intent of this book is to review analytic methods for predicting behavior of solder joints, based on continuum mechanics. The solder is treated as a continuous, homogeneous body, or composite of such bodies, whose mechanical behavior is uniform and governed by simple constitutive equations. The microstructure of a solder joint influences its mechanical properties in 3 ways: it governs deformation and failure; common solders deform inhomogeneously; and common solders are microstructurally unstable. The variety of microstructures often found in solder joints are briefly reviewed, and some of the ways are discussed in which the microstructure influences the common types of high-temperature mechanical behavior. 25 figs, 40 refs.

  15. Structured approaches to large-scale systems: Variational integrators for interconnected Lagrange-Dirac systems and structured model reduction on Lie groups

    NASA Astrophysics Data System (ADS)

    Parks, Helen Frances

    This dissertation presents two projects related to the structured integration of large-scale mechanical systems. Structured integration uses the considerable differential geometric structure inherent in mechanical motion to inform the design of numerical integration schemes. This process improves the qualitative properties of simulations and becomes especially valuable as a measure of accuracy over long time simulations in which traditional Gronwall accuracy estimates lose their meaning. Often, structured integration schemes replicate continuous symmetries and their associated conservation laws at the discrete level. Such is the case for variational integrators, which discretely replicate the process of deriving equations of motion from variational principles. This results in the conservation of momenta associated to symmetries in the discrete system and conservation of a symplectic form when applicable. In the case of Lagrange-Dirac systems, variational integrators preserve a discrete analogue of the Dirac structure preserved in the continuous flow. In the first project of this thesis, we extend Dirac variational integrators to accommodate interconnected systems. We hope this work will find use in the fields of control, where a controlled system can be thought of as a "plant" system joined to its controller, and in the approach of very large systems, where modular modeling may prove easier than monolithically modeling the entire system. The second project of the thesis considers a different approach to large systems. Given a detailed model of the full system, can we reduce it to a more computationally efficient model without losing essential geometric structures in the system? Asked without the reference to structure, this is the essential question of the field of model reduction. The answer there has been a resounding yes, with Principal Orthogonal Decomposition (POD) with snapshots rising as one of the most successful methods. Our project builds on previous work

  16. Printed Module Interconnects

    SciTech Connect

    Stockert, Talysa R.; Fields, Jeremy D.; Pach, Gregory F.; Mauger, Scott A.; van Hest, Maikel F. A. M.

    2015-06-14

    Monolithic interconnects in photovoltaic modules connect adjacent cells in series, and are typically formed sequentially involving multiple deposition and scribing steps. Interconnect widths of 500 um every 10 mm result in 5% dead area, which does not contribute to power generation in an interconnected solar panel. This work expands on previous work that introduced an alternative interconnection method capable of producing interconnect widths less than 100 um. The interconnect is added to the module in a single step after deposition of the photovoltaic stack, eliminating the need for scribe alignment. This alternative method can be used for all types of thin film photovoltaic modules. Voltage addition with copper-indium-gallium-diselenide (CIGS) solar cells using a 2-scribe printed interconnect approach is demonstrated. Additionally, interconnect widths of 250 um are shown.

  17. Use of organic solderability preservatives on solderability retention of copper after accelerated aging

    SciTech Connect

    Hernandez, C.L.; Sorensen, N.R.; Lucero, S.J.

    1997-02-01

    Organic solderability preservatives (OSP`s) have been used by the electronics industry for some time to maintain the solderability of circuit boards and components. Since solderability affects both manufacturing efficiency and product reliability, there is significant interest in maintaining good solder wettability. There is often a considerable time interval between the initial fabrication of a circuit board or component and its use at the assembly level. Parts are often stored under a variety of conditions, in many cases not well controlled. Solder wettability can deteriorate during storage, especially in harsh environments. This paper describes the ongoing efforts at Sandia National Laboratories to quantify solder watability on bare and aged copper surfaces. Benzotriazole and imidazole were applied to electronic grade copper to retard aging effects on solderability. The coupons were introduced into Sandia`s Facility for Atmospheric Corrosion Testing (FACT) to simulate aging in a typical indoor industrial environment. H{sub 2}S, NO{sub 2} and Cl{sub 2} mixed gas was introduced into the test cell and maintained at 35{degrees}C and 70% relative humidity for test periods of one day to two weeks. The OSP`s generally performed better than bare Cu, although solderability diminished with increasing exposure times.

  18. Effect of ashing conditions and optimization of nano process integration in copper/porous low-k nano-interconnects.

    PubMed

    Pyo, Sung Gyu; Kim, Soo Won

    2012-11-01

    We report the optimization of ashing conditions and the process integration of a chemical vapor deposition (CVD) ultra low-k (k = 2.2) organosilicate (OSG) dielectric in a top hard mask damascene structure. The N2/H2 ash showed the lowest resistance-capacitance (RC) product and a dual top hard mask approach for dual damascene processing was built, using 200 nm SiC/50 nm SiO2 as the hard mask. This CVD low-k material had no low-k voiding, unlike other spin-on dielectric (SOD) low-k materials. The presence of the densified layer around the trench during the ashing process could improve the precursor penetration during the CVD barrier metal deposition process.

  19. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  20. Sensitivity of Solder Joint Fatigue to Sources of Variation in Advanced Vehicular Power Electronics Cooling

    SciTech Connect

    Vlahinos, A.; O'Keefe, M.

    2010-06-01

    This paper demonstrates a methodology for taking variation into account in thermal and fatigue analyses of the die attach for an inverter of an electric traction drive vehicle. This method can be used to understand how variation and mission profile affect parameters of interest in a design. Three parameters are varied to represent manufacturing, material, and loading variation: solder joint voiding, aluminum nitride substrate thermal conductivity, and heat generation at the integrated gate bipolar transistor. The influence of these parameters on temperature and solder fatigue life is presented. The heat generation loading variation shows the largest influence on the results for the assumptions used in this problem setup.

  1. A systems approach to solder joint fatigue in spacecraft electronic packaging

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.

    1991-01-01

    Differential expansion induced fatigue resulting from temperature cycling is a leading cause of solder joint failures in spacecraft. Achieving high reliability flight hardware requires that each element of the fatigue issue be addressed carefully. This includes defining the complete thermal-cycle environment to be experienced by the hardware, developing electronic packaging concepts that are consistent with the defined environments, and validating the completed designs with a thorough qualification and acceptance test program. This paper describes a useful systems approach to solder fatigue based principally on the fundamental log-strain versus log-cycles-to-failure behavior of fatigue. This fundamental behavior has been useful to integrate diverse ground test and flight operational thermal-cycle environments into a unified electronics design approach. Each element of the approach reflects both the mechanism physics that control solder fatigue, as well as the practical realities of the hardware build, test, delivery, and application cycle.

  2. Prototyping lead-free solders on hand-soldered, through-hole circuit boards

    SciTech Connect

    Vianco, P.T.; Mizik, P.M.

    1993-12-31

    The lead-free solders 96.5Sn-3.5Ag (wt %), 95.5Sn-4.0Cu-0.5Ag, 91. 84Sn-3.33Ag-4.83Bi were used in the assembly of a through-hole circuit board to determine the feasibility of their suitability in hand soldering processes. Prototypes assembled with 63Sn-37Pb solder were manufactured to serve as control units. Implementation of the lead-free alloys were performed with a rosin-based, mildly activated (RMA) flux and a 700{degree}F soldering tip. A procedure was developed to remove the tin-lead finish from the leaded components and replace it with a 100Sn hot dipped coating. Assembly feasibility was demonstrated for all three lead-free solders. Defect counts were greater than observed with the tin-lead control alloy; however, the number of defects diminished with experience gained by the operator. Visual examination of the solder joints indicated satisfactory wetting of both the device leads and circuit board land with no apparent damage to the underlying laminate nor to the device packages. Cross sections of the lead-free solder joints showed that the were more susceptible to void formation within the holes than was the case with the tin-lead solder. Some cracking was observed at the interface between the Sn-Ag-Bi solder and the copper lands; the relatively high strength of this solder and fast cooling rate of the hand assembly process was believed responsible for this defect.

  3. Mechanical Shock Behavior of Environmentally-Benign Lead-free Solders

    NASA Astrophysics Data System (ADS)

    Yazzie, Kyle

    The mechanical behavior of Pb-free solder alloys is important, since they must maintain mechanical integrity under thermomechanical fatigue, creep, and mechanical shock conditions. Mechanical shock, in particular, has become an increasing concern in the electronics industry, since electronic packages can be subjected to mechanical shock by mishandling during manufacture or by accidental dropping. In this study, the mechanical shock behavior of Sn and Sn-Ag-Cu alloys was systematically analyzed over the strain rate range 10-3 -- 30 s-1 in bulk samples, and over 10-3 -- 12 s-1 on the single solder joint level. More importantly, the influences of solder microstructure and intermetallic compounds (IMC) on mechanical shock resistance were quantified. A thorough microstructural characterization of Sn-rich alloys was conducted using synchrotron x-ray computed tomography. The three-dimensional morphology and distribution of contiguous phases and precipitates was analyzed. A multiscale approach was utilized to characterize Sn-rich phases on the microscale with x-ray tomography and focused ion beam tomography to characterize nanoscale precipitates. A high strain rate servohydraulic test system was developed in conjunction with a modified tensile specimen geometry and a high speed camera for quantifying deformation. The effect of microstructure and applied strain rate on the local strain and strain rate distributions were quantified using digital image correlation. Necking behavior was analyzed using a novel mirror fixture, and the triaxial stresses associated with necking were corrected using a self-consistent method to obtain the true stress-true strain constitutive behavior. Fracture mechanisms were quantified as a function of strain rate. Finally, the relationship between solder microstructure and intermetallic compound layer thickness with the mechanical shock resistance of Sn-3.8Ag-0.7Cu solder joints was characterized. It was found that at low strain rates the dynamic

  4. Computer simulation of solder joint failure

    SciTech Connect

    Burchett, S.N.; Frear, D.R.; Rashid, M.M.

    1997-04-01

    The thermomechanical fatigue failure of solder joints is increasingly becoming an important reliability issue for electronic packages. The purpose of this Laboratory Directed Research and Development (LDRD) project was to develop computational tools for simulating the behavior of solder joints under strain and temperature cycling, taking into account the microstructural heterogeneities that exist in as-solidified near eutectic Sn-Pb joints, as well as subsequent microstructural evolution. The authors present two computational constitutive models, a two-phase model and a single-phase model, that were developed to predict the behavior of near eutectic Sn-Pb solder joints under fatigue conditions. Unique metallurgical tests provide the fundamental input for the constitutive relations. The two-phase model mathematically predicts the heterogeneous coarsening behavior of near eutectic Sn-Pb solder. The finite element simulations with this model agree qualitatively with experimental thermomechanical fatigue tests. The simulations show that the presence of an initial heterogeneity in the solder microstructure could significantly degrade the fatigue lifetime. The single-phase model was developed to predict solder joint behavior using materials data for constitutive relation constants that could be determined through straightforward metallurgical experiments. Special thermomechanical fatigue tests were developed to give fundamental materials input to the models, and an in situ SEM thermomechanical fatigue test system was developed to characterize microstructural evolution and the mechanical behavior of solder joints during the test. A shear/torsion test sample was developed to impose strain in two different orientations. Materials constants were derived from these tests. The simulation results from the two-phase model showed good fit to the experimental test results.

  5. Age-aware solder performance models : level 2 milestone completion.

    SciTech Connect

    Neilsen, Michael K.; Vianco, Paul Thomas; Neidigk, Matthew Aaron; Holm, Elizabeth Ann

    2010-09-01

    Legislated requirements and industry standards are replacing eutectic lead-tin (Pb-Sn) solders with lead-free (Pb-free) solders in future component designs and in replacements and retrofits. Since Pb-free solders have not yet seen service for long periods, their long-term behavior is poorly characterized. Because understanding the reliability of Pb-free solders is critical to supporting the next generation of circuit board designs, it is imperative that we develop, validate and exercise a solder lifetime model that can capture the thermomechanical response of Pb-free solder joints in stockpile components. To this end, an ASC Level 2 milestone was identified for fiscal year 2010: Milestone 3605: Utilize experimentally validated constitutive model for lead-free solder to simulate aging and reliability of solder joints in stockpile components. This report documents the completion of this milestone, including evidence that the milestone completion criteria were met and a summary of the milestone Program Review.

  6. Five-Segment Interconnection For Electromigration Tests

    NASA Technical Reports Server (NTRS)

    Hannaman, David J.; Buehler, Martin G.

    1991-01-01

    Proposed integrated-circuit conductive pattern intended for use in electromigration lifetime testing of interconnection lines of integrated circuits. Designed for collection of statistics on electromigration from smallest possible area. Includes 5 interconnection segments with Kelvin voltage taps, with total of 12 contact pads, and provides for simultaneous measurements on all of segments. Attempts to minimize thermal gradients within each segment and conforms to guidelines on electromigration test structures promulgated by National Institute of Standards and Technology (NIST).

  7. Fluxless laser soldering for electronic packaging

    SciTech Connect

    Hosking, F M; Keicher, D M

    1991-01-01

    Conventional soldering typically requires the use of reactive fluxes to promote wetting. The resulting flux residues are removed primarily with halogenated or chlorofluorocarbon (CFC) solvents. With the mandated phaseout of CFCs by the year 2000, there has been a concentrated effort to develop alternative, environmentally compatible manufacturing and cleaning technologies that will satisfy the restrictions placed on CFCs, but still yield high quality product. Sandia National Laboratories is currently evaluating a variety of alternative fluxless soldering technologies which can be applied to electronic packaging. Laser soldering in a controlled atmosphere has shown great potential as an environmentally compatible process. The effects of laser heating with a 100 watt CW Nd:YAG laser, joint design, and base/filler metal reactions on achieving fluxless wetting with good metallurgical bonds were examined. Satisfactory Ni-Au plated Kovar{reg sign} solder joints were made with 80In-15Pb-5Ag and 63Sn-37Pb (wt. %) solder alloys in a slightly reducing cover gas. Wetting generally increased with increasing laser power, decreasing laser beam spot size, and decreasing part travel speed. The materials and processing interaction effects are identified and discussed.

  8. Fluxless laser soldering for electronic packaging

    SciTech Connect

    Hosking, F.M.; Keicher, D.M.

    1991-12-31

    Conventional soldering typically requires the use of reactive fluxes to promote wetting. The resulting flux residues are removed primarily with halogenated or chlorofluorocarbon (CFC) solvents. With the mandated phaseout of CFCs by the year 2000, there has been a concentrated effort to develop alternative, environmentally compatible manufacturing and cleaning technologies that will satisfy the restrictions placed on CFCs, but still yield high quality product. Sandia National Laboratories is currently evaluating a variety of alternative fluxless soldering technologies which can be applied to electronic packaging. Laser soldering in a controlled atmosphere has shown great potential as an environmentally compatible process. The effects of laser heating with a 100 watt CW Nd:YAG laser, joint design, and base/filler metal reactions on achieving fluxless wetting with good metallurgical bonds were examined. Satisfactory Ni-Au plated Kovar{reg_sign} solder joints were made with 80In-15Pb-5Ag and 63Sn-37Pb (wt. %) solder alloys in a slightly reducing cover gas. Wetting generally increased with increasing laser power, decreasing laser beam spot size, and decreasing part travel speed. The materials and processing interaction effects are identified and discussed.

  9. Microstructural evolution of eutectic Au-Sn solder joints

    SciTech Connect

    Song, Ho Geon

    2002-05-31

    Current trends toward miniaturization and the use of lead(Pb)-free solder in electronic packaging present new problems in the reliability of solder joints. This study was performed in order to understand the microstructure and microstructural evolution of small volumes of nominally eutectic Au-Sn solder joints (80Au-20Sn by weight), which gives insight into properties and reliability.

  10. Efforts to Develop a 300°C Solder

    SciTech Connect

    Norann, Randy A

    2015-01-25

    This paper covers the efforts made to find a 300°C electrical solder solution for geothermal well monitoring and logging tools by Perma Works LLC. This paper covers: why a high temperature solder is needed, what makes for a good solder, testing flux, testing conductive epoxy and testing intermetallic bonds. Future areas of research are suggested.

  11. Testing of printed circuit board solder joints by optical correlation

    NASA Technical Reports Server (NTRS)

    Espy, P. N.

    1975-01-01

    An optical correlation technique for the nondestructive evaluation of printed circuit board solder joints was evaluated. Reliable indications of induced stress levels in solder joint lead wires are achievable. Definite relations between the inherent strength of a solder joint, with its associated ability to survive stress, are demonstrable.

  12. Thermal resistances of solder-boss/potting compound combinations

    NASA Technical Reports Server (NTRS)

    Veilleux, E. D.

    1968-01-01

    Formulas, which can be used as a design tool, are derived to calculate the thermal resistance of solder-boss/potting compound combinations, for different depths of a solder boss, in electronic cordwood modules. Since the solder boss is the heat source, its shape and position will affect the thermal resistance of the surrounding potting compound.

  13. Electromigration kinetics and critical current of Pb-free interconnects

    SciTech Connect

    Lu, Minhua; Rosenberg, Robert

    2014-04-07

    Electromigration kinetics of Pb-free solder bump interconnects have been studied using a single bump parameter sweep technique. By removing bump to bump variations in structure, texture, and composition, the single bump sweep technique has provided both activation energy and power exponents that reflect atomic migration and interface reactions with fewer samples, shorter stress time, and better statistics than standard failure testing procedures. Contact metallurgies based on Cu and Ni have been studied. Critical current, which corresponds to the Blech limit, was found to exist in the Ni metallurgy, but not in the Cu metallurgy. A temperature dependence of critical current was also observed.

  14. A novel method for direct solder bump pull testing using lead-free solders

    NASA Astrophysics Data System (ADS)

    Turner, Gregory Alan

    This thesis focuses on the design, fabrication, and evaluation of a new method for testing the adhesion strength of lead-free solders, named the Isotraction Bump Pull method (IBP). In order to develop a direct solder joint-strength testing method that did not require customization for different solder types, bump sizes, specific equipment, or trial-and-error, a combination of two widely used and accepted standards was created. First, solder bumps were made from three types of lead free solder were generated on untreated copper PCB substrates using an in-house fabricated solder bump-on-demand generator, Following this, the newly developed method made use of a polymer epoxy to encapsulate the solder bumps that could then be tested under tension using a high precision universal vertical load machine. The tests produced repeatable and predictable results for each of the three alloys tested that were in agreement with the relative behavior of the same alloys using other testing methods in the literature. The median peak stress at failure for the three solders tested were 2020.52 psi, 940.57 psi, and 2781.0 psi, and were within one standard deviation of the of all data collected for each solder. The assumptions in this work that brittle fracture occurred through the Intermetallic Compound layer (IMC) were validated with the use of Energy-Dispersive X-Ray Spectrometry and high magnification of the fractured surface of both newly exposed sides of the test specimens. Following this, an examination of the process to apply the results from the tensile tests into standard material science equations for the fracture of the systems was performed..

  15. Laparoscopic Mesh Fixation Using Laser-Assisted Tissue Soldering in a Porcine Model

    PubMed Central

    Soltz, Barbara A.; Stadler, Istvan; Soltz, Robert

    2009-01-01

    Background and Objective: Animal studies using open surgical models indicate that collagen solder is capable of fixation of surgical meshes without interfering with tissue integration, increasing adhesions, or increasing inflammation intraperitoneally. This study describes development of instrumentation and techniques for laparoscopic herniorrhaphy using laser-assisted soldering technology. Study Design and Methods: Anesthetized 20 kg to 25 kg female Yorkshire pigs underwent laparoscopy with a 3-trocar technique. Parietex TET, Parietex TEC, and Prolene mesh segments (5 × 5 cm) were embedded in 55% collagen solder. Segments were inserted by using a specially designed introducer and affixed to the peritoneum by using prototype laser devices (1.45 µ, 4.5 W continuous wave, 5-mm spot, 55° C set temperature) and a custom laparoscopic handpiece (IPOM). Parietex PCO mesh was inserted and affixed using the Endo-hernia stapler (Control). Animals were recovered and underwent second-look laparoscopy at 6 weeks. Mesh sites were harvested after animals were euthanized. Results: The mesh-solder constructs were easily inserted and affixed in an IPOM approach. Prolene mesh tended to curl at its edges as the solder was melted. Postoperative healing was similar to that in Control segments in all cases. Discussion and Conclusion: Collagen-based tissue soldering permits normal wound healing and may mitigate or reduce the use of staples or other foreign bodies for laparoscopic mesh fixation, prevent tissue ischemia and possibly nerve entrapment, which result in severe postoperative pain and morbidity. Laser-assisted mesh fixation is a promising alternative for laparoscopic herniorrhaphy. Further development of this strategy is warranted. PMID:19793465

  16. Nanocopper Based Solder-Free Electronic Assembly

    NASA Astrophysics Data System (ADS)

    Schnabl, K.; Wentlent, L.; Mootoo, K.; Khasawneh, S.; Zinn, A. A.; Beddow, J.; Hauptfleisch, E.; Blass, D.; Borgesen, P.

    2014-12-01

    CuantumFuse nano copper material has been used to assemble functional LED test boards and a small camera board with a 48 pad CMOS sensor quad-flat no-lead chip and a 10 in flexible electronics demo. Drop-in replacement of solder, by use of stencil printing and standard surface mount technology equipment, has been demonstrated. Applications in space and commercial systems are currently under consideration. The stable copper-nanoparticle paste has been examined and characterized by scanning electron microscopy and high-resolution transmission electron microscopy; this has shown that the joints are nanocrystalline but with substantial porosity. Assessment of reliability is expected to be complicated by this and by the effects of thermal and strain-enhanced coarsening of pores. Strength, creep, and fatigue properties were measured and results are discussed with reference to our understanding of solder reliability to assess the potential of this nano-copper based solder alternative.

  17. Pb-Free Soldering Iron Temperature Controller

    NASA Astrophysics Data System (ADS)

    Hamane, Hiroto; Wajima, Kenji; Hayashi, Yoichi; Komiyama, Eiichi; Tachibana, Toshiaki; Miyazaki, Kazuyoshi

    Recently, much importance has been attached to the environmental problem. The content of two directives to better control the management of waste electronic equipment was approved. The two directives are the Waste from Electrical and Electronic Equipment (WEEE) and the Restriction of Hazardous Substances (RoHS). These set phase-out dates for the use of lead materials contained in electronic products. Increasingly, attention is focusing on the potential use of Pb-free soldering in electronics manufacturing. It should be noted that many of the current solding irons are not suitable for Pb-free technology, due to the inferior wetting ability of Pb-free alloys compared with SnPb solder pastes. This paper presents a Pb-free soldering iron temperature controller using an embedded micro-processor with a low memory capacity.

  18. Solder Joint Health Monitoring Testbed System

    NASA Technical Reports Server (NTRS)

    Delaney, Michael M.

    2009-01-01

    The density and pin count for Field Programmable Gate Arrays (FPGAs) has been increasing, and has exceeded current methods of solder joint inspection, making early detection of failures more problematic. These failures are a concern for both flight safety and maintenance in commercial aviation. Ridgetop Group, Inc. has developed a method for detecting solder joint failures in real time. The NASA Dryden Flight Research Center is developing a set of boards to test this method in ground environmental and accelerated testing as well as flight test on a Dryden F-15 or F-18 research aircraft. In addition to detecting intermittent and total solder joint failures, environmental data on the boards, such as temperature and vibration, will be collected and time-correlated to aircraft state data. This paper details the technical approach involved in the detection process, and describes the design process and products to date for Dryden s FPGA failure detection boards.

  19. Solderability Study of RABiTS-Based YBCO Coated Conductors

    SciTech Connect

    Zhang, Yifei; Duckworth, Robert C; Ha, Tam T; Gouge, Michael J

    2011-01-01

    The solderability of commercially available YBa{sub 2}Cu{sub 3}O{sub 7-x} (YBCO) coated conductors that were made from Rolling Assisted Biaxially Textured Substrates (RABiTS)-based templates was studied. The coated conductors, also known as second-generation (2G) high temperature superconductor (HTS) wires (in the geometry of flat tapes about 4 mm wide), were laminated with copper, brass, or stainless steel strips as stabilizers. To understand the factors that influence their solderability, surface profilometry and scanning electron microscopy were used to characterize the wire surfaces. The solderability of three solders, 52In48Sn, 67Bi33In, and 100In (wt.%), was evaluated using a standard test (IPC/ECA J-STD-002) and with two different commercial fluxes. It was found that the solderability varied with the solder and flux but the three different wires showed similar solderability for a fixed combination of solder and flux. Solder joints of the 2G wires were fabricated using the tools and the procedures recommended by the HTS wire manufacturer. The solder joints were made in a lap-joint geometry and with the superconducting sides of the two wires face-to-face. The electrical resistances of the solder joints were measured at 77 K, and the results were analyzed to qualify the soldering materials and evaluate the soldering process. It was concluded that although the selection of soldering materials affected the resistance of a solder joint, the resistivity of the stabilizer was the dominant factor.

  20. Platinum solder core wire: Development and industrial implications

    NASA Astrophysics Data System (ADS)

    Watt, R. J.; Koursaris, A.

    1996-06-01

    Jewelry neck chain is joined by age-old techniques, the most popular being the rather involved solder powder method. The solder core method of chain manufacture is a simpler process and offers the possibility of higher productivity. Neat narrow joints are formed, and a color match between the solder and parent alloy may be approached. This is particularly important in the case of platinum alloys that have a high melting point, necessitating the use of solders with compositions substantially different from those of the parent alloy. The solder core method also lends itself to the possibility of higher levels of automation.

  1. Moisture and aging effects of solder wettability of copper surfaces

    SciTech Connect

    Hernandez, C.L.; Sorensen, N.R.; Lucero, S.J.

    1996-12-01

    Solderability is a critical property of electronic assembly that affects both manufacturing efficiency and product reliability. There is often a considerable time interval between initial fabrication of a circuit board or component and its use at the assembly level. Parts are often stored under a variety of conditions, usually not controlled. Solder wettability can soon deteriorate during storage, especially in extreme environments. This paper describes ongoing efforts at Sandia to quantify solder wettability on bare and aged Cu surfaces. In addition, organic solderability preservatives (OSPs) were applied to the bare Cu to retard solderability loss due to aging. The OSPs generally performed well, although wetting did decrease with exposure time.

  2. Lead (Pb)-Free Solder Applications

    SciTech Connect

    VIANCO,PAUL T.

    2000-08-15

    Legislative and marketing forces both abroad and in the US are causing the electronics industry to consider the use of Pb-free solders in place of traditional Sn-Pb alloys. Previous case studies have demonstrated the satisfactory manufacturability and reliability of several Pb-free compositions for printed circuit board applications. Those data, together with the results of fundamental studies on Pb-free solder materials, have indicated the general feasibility of their use in the broader range of present-day, electrical and electronic components.

  3. Microwave Tissue Soldering for Immediate Wound Closure

    NASA Technical Reports Server (NTRS)

    Arndt, G. Dickey; Ngo, Phong H.; Plan, Chau T.; Byerly, Diane; Dusl, John; Sognier, Marguerite A.

    2011-01-01

    A novel approach for the immediate sealing of traumatic wounds is under development. A portable microwave generator and handheld antenna are used to seal wounds, binding the edges of the wound together using a biodegradable protein sealant or solder. This method could be used for repairing wounds in emergency settings, by restoring the wound surface to its original strength within minutes. This technique could also be utilized for surgical purposes involving solid visceral organs (i.e., liver, spleen, and kidney) that currently do not respond well to ordinary surgical procedures. A miniaturized microwave generator and a handheld antenna are used to deliver microwave energy to the protein solder, which is applied to the wound. The antenna can be of several alternative designs optimized for placement either in contact with or proximity to the protein solder covering the wound. In either case, optimization of the design includes the matching of impedances to maximize the energy delivered to the protein solder and wound at a chosen frequency. For certain applications, an antenna could be designed that would emit power only when it is in direct contact with the wound. The optimum frequency or frequencies for a specific application would depend on the required depth of penetration of the microwave energy. In fact, a computational simulation for each specific application could be performed, which would then match the characteristics of the antenna with the protein solder and tissue to best effect wound closure. An additional area of interest with potential benefit that remains to be validated is whether microwave energy can effectively kill bacteria in and around the wound. Thus, this may be an efficient method for simultaneously sterilizing and closing wounds. Using microwave energy to seal wounds has a number of advantages over lasers, which are currently in experimental use in some hospitals. Laser tissue welding is unsuitable for emergency use because its large, bulky

  4. ESD Test Apparatus for Soldering Irons

    NASA Technical Reports Server (NTRS)

    Sancho, Jose; Esser, Robert

    2013-01-01

    ESDA (Electrostatic Discharge Association) ESD STM 13.1-2000 requires frequent testing of the voltage leakage from the tip of a soldering iron and the resistance from the tip of the soldering iron to the common point ground. Without this test apparatus, the process is time-consuming and requires several wires, alligator clips, or test probes, as well as additional equipment. Soldering iron tips must be tested for electrostatic discharge risks frequently, and this typically takes a lot of time in setup and testing. This device enables the operator to execute the full test in one minute or less. This innovation is a simple apparatus that plugs into a digital multimeter (DMM) and the Common Point Ground (CPG) reference. It enables the user to perform two of the electrostatic discharge tests required in ESD STM 13.1-2000. The device consists of a small black box with two prongs sticking out of one end, two inputs on the opposite end (one of the inputs is used to connect the reference CPG to the DMM), and a metal tab on one side. Inside the box are wires, several washers of various materials, and assembly hardware (nuts and screws/bolts). The device is a passive electronic component that is plugged into a DMM. The operator sets the DMM to read voltage. The operator places the heated tip of the soldering iron onto the metal tab with a small amount of solder to ensure a complete connection. The voltage is read and recorded. The operator switches the DMM to read resistance. The operator places the heated tip of the soldering iron onto the metal tab with a small amount of solder to ensure a complete connection. The resistance is recorded. If the recorded voltage and resistance are below a number stated in ESDA ESD STM 13.1-2000, the test is considered to pass. The device includes all the necessary wiring internal to its body so the operator does not need to do any independent wiring, except for grounding. It uses a stack of high-thermal-resistance washers to minimize the

  5. Perforation patterned electrical interconnects

    DOEpatents

    Frey, Jonathan

    2014-01-28

    This disclosure describes systems and methods for increasing the usable surface area of electrical contacts within a device, such as a thin film solid state device, through the implementation of electrically conductive interconnects. Embodiments described herein include the use of a plurality of electrically conductive interconnects that penetrate through a top contact layer, through one or more multiple layers, and into a bottom contact layer. The plurality of conductive interconnects may form horizontal and vertical cross-sectional patterns. The use of lasers to form the plurality of electrically conductive interconnects from reflowed layer material further aids in the manufacturing process of a device.

  6. Solder for oxide layer-building metals and alloys

    DOEpatents

    Kronberg, James W.

    1992-01-01

    A low temperature solder and method for soldering an oxide layer-building metal such as aluminum, titanium, tantalum or stainless steel. The comosition comprises tin and zinc; germanium as a wetting agent; preferably small amounts of copper and antimony; and a grit, such as silicon carbide. The grit abrades any oxide layer formed on the surface of the metal as the germanium penetrates beneath and loosens the oxide layer to provide good metal-to-metal contact. The germanium comprises less than aproximatley 10% by weight of the solder composition so that it provides sufficient wetting action but does not result in a melting temperature above approximately 300.degree. C. The method comprises the steps rubbing the solder against the metal surface so the grit in the solder abrades the surface while heating the surface until the solder begins to melt and the germanium penetrates the oxide layer, then brushing aside any oxide layer loosened by the solder.

  7. Solder for oxide layer-building metals and alloys

    DOEpatents

    Kronberg, J.W.

    1992-09-15

    A low temperature solder and method for soldering an oxide layer-building metal such as aluminum, titanium, tantalum or stainless steel is disclosed. The composition comprises tin and zinc; germanium as a wetting agent; preferably small amounts of copper and antimony; and a grit, such as silicon carbide. The grit abrades any oxide layer formed on the surface of the metal as the germanium penetrates beneath and loosens the oxide layer to provide good metal-to-metal contact. The germanium comprises less than approximately 10% by weight of the solder composition so that it provides sufficient wetting action but does not result in a melting temperature above approximately 300 C. The method comprises the steps rubbing the solder against the metal surface so the grit in the solder abrades the surface while heating the surface until the solder begins to melt and the germanium penetrates the oxide layer, then brushing aside any oxide layer loosened by the solder.

  8. Capillary flow of solder on chemically roughened PWB surfaces

    SciTech Connect

    Hosking, F.M.; Stevenson, J.O.; Yost, F.G.

    1996-02-01

    The Center for Solder Science and Technology at Sandia National Laboratories has developed a solderability test for evaluating fundamental solder flow over PWB (printed wiring boards) surface finishes. The work supports a cooperative research and development agreement between Sandia, the National Center for Manufacturing Sciences (NCMS), and several industrial partners. An important facet of the effort involved the ``engineering`` of copper surfaces through mechanical and chemical roughening. The roughened topography enhances solder flow, especially over very fine features. In this paper, we describe how etching with different chemical solutions can affect solder flow on a specially designed ball grid array test vehicle (BGATV). The effects of circuit geometry, solution concentration, and etching time are discussed. Surface roughness and solder flow data are presented to support the roughening premise. Noticeable improvements in solder wettability were observed on uniformly etched surfaces having relatively steep peak-to-valley slopes.

  9. Thermoelectric Coolers with Sintered Silver Interconnects

    NASA Astrophysics Data System (ADS)

    Kähler, Julian; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

    2014-06-01

    The fabrication and performance of a sintered Peltier cooler (SPC) based on bismuth telluride with sintered silver interconnects are described. Miniature SPC modules with a footprint of 20 mm2 were assembled using pick-and-place pressure-assisted silver sintering at low pressure (5.5 N/mm2) and moderate temperature (250°C to 270°C). A modified flip-chip bonder combined with screen/stencil printing for paste transfer was used for the pick-and-place process, enabling high positioning accuracy, easy handling of the tiny bismuth telluride pellets, and immediate visual process control. A specific contact resistance of (1.4 ± 0.1) × 10-5 Ω cm2 was found, which is in the range of values reported for high-temperature solder interconnects of bismuth telluride pellets. The realized SPCs were evaluated from room temperature to 300°C, considerably outperforming the operating temperature range of standard commercial Peltier coolers. Temperature cycling capability was investigated from 100°C to 235°C over more than 200 h, i.e., 850 cycles, during which no degradation of module resistance or cooling performance occurred.

  10. Microstructural Evolution of Lead-Free Solder Joints in Ultrasonic-Assisted Soldering

    NASA Astrophysics Data System (ADS)

    Ji, Hongjun; Wang, Qiang; Li, Mingyu

    2016-01-01

    Solder joint reliability greatly depends on the microstructure of the solder matrix and the morphology of intermetallic compounds (IMCs) in the joints. Addition of strengthening phases such as carbon nanotubes and ceramic particles to solder joints to improve their properties has been widely studied. In this work, ultrasonic vibration (USV) of casting ingots was applied to considerably improve their microstructure and properties, and the resulting influence on fluxless soldering of Cu/Sn-3.0Ag-0.5Cu/Cu joints and their microstructural evolution was investigated. It was demonstrated that USV application during reflow of Sn-based solder had favorable effects on β-Sn grain size refinement as well as the growth and distribution of various IMC phases within the joints. The β-Sn grain size was significantly refined as the ultrasound power was increased, with a reduction of almost 90% from more than 100 μm to below 10 μm. Long and large Cu6Sn5 tubes in the solder matrix of the joints were broken into tiny ones. Needle-shaped Ag3Sn was transformed into flake-shaped. These IMCs were mainly precipitated along β-Sn phase boundaries. High-temperature storage tests indicated that the growth rate of interfacial IMCs in joints formed with USV was slower than in conventional reflow joints. The mechanisms of grain refinement and IMC fragmentation are discussed and related to the ultrasonic effects.

  11. Flexible packaging and interconnect scheme for microfluidic systems

    NASA Astrophysics Data System (ADS)

    Benett, William J.; Krulevitch, Peter A.

    1999-06-01

    A slide-together compression package and microfluidic interconnects for microfabricated devices requiring fluidic and electrical connections is presented. The package assembles without tools, is reusable, and requires no epoxy, wirebonds, or solder, making chip replacement fast and easy. The microfluidic interconnects use standard HPLC PEEK tubing, with the tip machined to accept either an o-ring or custom molded ring which serves the dual function of forming the seal and providing mechanical retention strength. One design uses a screw to compress the o-ring, while others are simply plugged into a cartridge retained in the package. The connectors are helium leak-tight, can withstand hundreds of psi, are easy to connect and disconnect, are low dead volume, have a small footprint, and are adaptable to a broad range of microfabricated devices.

  12. Interconnections for fluidic circuits

    NASA Technical Reports Server (NTRS)

    Mangion, C.

    1972-01-01

    Circuit elements are grouped on functional basis in rectangular two-dimensional planar arrays or modules. Another interconnection method brings all connections out to module edge. For smaller fluidic circuits, manifold and interconnections are fabricated as single blocks. Advantages of methods are given.

  13. Multilead, Vaporization-Cooled Soldering Heat Sink

    NASA Technical Reports Server (NTRS)

    Rice, John

    1995-01-01

    Vaporization-cooled heat sink proposed for use during soldering of multiple electrical leads of packaged electronic devices to circuit boards. Heat sink includes compliant wicks held in grooves on edges of metal fixture. Wicks saturated with water. Prevents excessive increases in temperature at entrances of leads into package.

  14. Microwave Tissue Soldering for Immediate Wound Closure

    NASA Technical Reports Server (NTRS)

    Arndt, G. Dickey; Ngo, Phong H.; Phan, Chau T.; Byerly, Diane; Dusl, John; Sognier, Marguerite A.; Carl, James

    2011-01-01

    A novel approach for the immediate sealing of traumatic wounds is under development. A portable microwave generator and handheld antenna are used to seal wounds, binding the edges of the wound together using a biodegradable protein sealant or solder. This method could be used for repairing wounds in emergency settings by restoring the wound surface to its original strength within minutes. This technique could also be utilized for surgical purposes involving solid visceral organs (i.e., liver, spleen, and kidney) that currently do not respond well to ordinary surgical procedures. A miniaturized microwave generator and a handheld antenna are used to deliver microwave energy to the protein solder, which is applied to the wound. The antenna can be of several alternative designs optimized for placement either in contact with or in proximity to the protein solder covering the wound. In either case, optimization of the design includes the matching of impedances to maximize the energy delivered to the protein solder and wound at a chosen frequency. For certain applications, an antenna could be designed that would emit power only when it is in direct contact with the wound. The optimum frequency or frequencies for a specific application would depend on the required depth of penetration of the microwave energy. In fact, a computational simulation for each specific application could be performed, which would then match the characteristics of the antenna with the protein solder and tissue to best effect wound closure. An additional area of interest with potential benefit that remains to be validated is whether microwave energy can effectively kill bacteria in and around the wound. Thus, this may be an efficient method for simultaneously sterilizing and closing wounds.

  15. Thermal Cycling Life Prediction of Sn-3.0Ag-0.5Cu Solder Joint Using Type-I Censored Data

    PubMed Central

    Mi, Jinhua; Yang, Yuan-Jian; Huang, Hong-Zhong

    2014-01-01

    Because solder joint interconnections are the weaknesses of microelectronic packaging, their reliability has great influence on the reliability of the entire packaging structure. Based on an accelerated life test the reliability assessment and life prediction of lead-free solder joints using Weibull distribution are investigated. The type-I interval censored lifetime data were collected from a thermal cycling test, which was implemented on microelectronic packaging with lead-free ball grid array (BGA) and fine-pitch ball grid array (FBGA) interconnection structures. The number of cycles to failure of lead-free solder joints is predicted by using a modified Engelmaier fatigue life model and a type-I censored data processing method. Then, the Pan model is employed to calculate the acceleration factor of this test. A comparison of life predictions between the proposed method and the ones calculated directly by Matlab and Minitab is conducted to demonstrate the practicability and effectiveness of the proposed method. At last, failure analysis and microstructure evolution of lead-free solders are carried out to provide useful guidance for the regular maintenance, replacement of substructure, and subsequent processing of electronic products. PMID:25121138

  16. Thermal cycling life prediction of Sn-3.0Ag-0.5Cu solder joint using type-I censored data.

    PubMed

    Mi, Jinhua; Li, Yan-Feng; Yang, Yuan-Jian; Peng, Weiwen; Huang, Hong-Zhong

    2014-01-01

    Because solder joint interconnections are the weaknesses of microelectronic packaging, their reliability has great influence on the reliability of the entire packaging structure. Based on an accelerated life test the reliability assessment and life prediction of lead-free solder joints using Weibull distribution are investigated. The type-I interval censored lifetime data were collected from a thermal cycling test, which was implemented on microelectronic packaging with lead-free ball grid array (BGA) and fine-pitch ball grid array (FBGA) interconnection structures. The number of cycles to failure of lead-free solder joints is predicted by using a modified Engelmaier fatigue life model and a type-I censored data processing method. Then, the Pan model is employed to calculate the acceleration factor of this test. A comparison of life predictions between the proposed method and the ones calculated directly by Matlab and Minitab is conducted to demonstrate the practicability and effectiveness of the proposed method. At last, failure analysis and microstructure evolution of lead-free solders are carried out to provide useful guidance for the regular maintenance, replacement of substructure, and subsequent processing of electronic products. PMID:25121138

  17. Cross-border impacts of the restriction of hazardous substances: a perspective based on Japanese solders.

    PubMed

    Fuse, Masaaki; Tsunemi, Kiyotaka

    2013-08-20

    Despite the relevance of the global economy, Regulatory Impact Assessments of the restriction of hazardous substances (RoHS) in the European Union (EU) are based only on domestic impacts. This paper explores the cross-border environmental impacts of the RoHS by focusing on the shifts to lead-free solders in Japan, which exports many electronics to the EU. The regulatory impacts are quantified by integrating a material flow analysis for metals constituting a solder with a scenario analysis with and without the RoHS. The results indicate that the EU regulation, the RoHS, has triggered shifts in Japan to lead-free solders, not only for electronics subject to this regulation, but for other products as well. We also find that the RoHS leads to a slow reduction in environmental emissions of the target, lead, but results in a rapid increase in the use of tin and silver in lead-free solders. This indicates the importance of assessing potential alternative substances, the use of which may increase as a result of adhering to the RoHS. The latter constitutes a negative impact because of recent concerns regarding resource criticality.

  18. Cross-border impacts of the restriction of hazardous substances: a perspective based on Japanese solders.

    PubMed

    Fuse, Masaaki; Tsunemi, Kiyotaka

    2013-08-20

    Despite the relevance of the global economy, Regulatory Impact Assessments of the restriction of hazardous substances (RoHS) in the European Union (EU) are based only on domestic impacts. This paper explores the cross-border environmental impacts of the RoHS by focusing on the shifts to lead-free solders in Japan, which exports many electronics to the EU. The regulatory impacts are quantified by integrating a material flow analysis for metals constituting a solder with a scenario analysis with and without the RoHS. The results indicate that the EU regulation, the RoHS, has triggered shifts in Japan to lead-free solders, not only for electronics subject to this regulation, but for other products as well. We also find that the RoHS leads to a slow reduction in environmental emissions of the target, lead, but results in a rapid increase in the use of tin and silver in lead-free solders. This indicates the importance of assessing potential alternative substances, the use of which may increase as a result of adhering to the RoHS. The latter constitutes a negative impact because of recent concerns regarding resource criticality. PMID:23875815

  19. Damage mechanics characterization on fatigue behavior of a solder joint material

    SciTech Connect

    Chow, C.L.; Yang, F.; Fang, H.E.

    1998-08-01

    This paper presents the first part of a comprehensive mechanics approach capable of predicting the integrity and reliability of solder joint material under fatigue loading without viscoplastic damage considerations. A separate report will be made to present a comprehensive damage model describing life prediction of the solder material under thermomechanical fatigue loading. The method is based on a theory of damage mechanics which makes possible a macroscopic description of the successive material deterioration caused by the presence of microcracks/voids in engineering materials. A damage mechanics model based on the thermodynamic theory of irreversible processes with internal state variables is proposed and used to provide a unified approach in characterizing the cyclic behavior of a typical solder material. With the introduction of a damage effect tensor, the constitutive equations are derived to enable the formulation of a fatigue damage dissipative potential function and a fatigue damage criterion. The fatigue evolution is subsequently developed based on the hypothesis that the overall damage is induced by the accumulation of fatigue and plastic damage. This damage mechanics approach offers a systematic and versatile means that is effective in modeling the entire process of material failure ranging from damage initiation and propagation leading eventually to macro-crack initiation and growth. As the model takes into account the load history effect and the interaction between plasticity damage and fatigue damage, with the aid of a modified general purpose finite element program, the method can readily be applied to estimate the fatigue life of solder joints under different loading conditions.

  20. Quantifying Electromigration Processes in Sn-0.7Cu Solder with Lab-Scale X-Ray Computed Micro-Tomography

    NASA Astrophysics Data System (ADS)

    Mertens, James Charles Edwin

    For decades, microelectronics manufacturing has been concerned with failures related to electromigration phenomena in conductors experiencing high current densities. The influence of interconnect microstructure on device failures related to electromigration in BGA and flip chip solder interconnects has become a significant interest with reduced individual solder interconnect volumes. A survey indicates that x-ray computed micro-tomography (muXCT) is an emerging, novel means for characterizing the microstructures' role in governing electromigration failures. This work details the design and construction of a lab-scale muXCT system to characterize electromigration in the Sn-0.7Cu lead-free solder system by leveraging in situ imaging. In order to enhance the attenuation contrast observed in multi-phase material systems, a modeling approach has been developed to predict settings for the controllable imaging parameters which yield relatively high detection rates over the range of x-ray energies for which maximum attenuation contrast is expected in the polychromatic x-ray imaging system. In order to develop this predictive tool, a model has been constructed for the Bremsstrahlung spectrum of an x-ray tube, and calculations for the detector's efficiency over the relevant range of x-ray energies have been made, and the product of emitted and detected spectra has been used to calculate the effective x-ray imaging spectrum. An approach has also been established for filtering 'zinger' noise in x-ray radiographs, which has proven problematic at high x-ray energies used for solder imaging. The performance of this filter has been compared with a known existing method and the results indicate a significant increase in the accuracy of zinger filtered radiographs. The obtained results indicate the conception of a powerful means for the study of failure causing processes in solder systems used as interconnects in microelectronic packaging devices. These results include the

  1. Soldering of Carbon Materials Using Transition Metal Rich Alloys.

    PubMed

    Burda, Marek; Lekawa-Raus, Agnieszka; Gruszczyk, Andrzej; Koziol, Krzysztof K K

    2015-08-25

    Joining of carbon materials via soldering has not been possible up to now due to lack of wetting of carbons by metals at standard soldering temperatures. This issue has been a severely restricting factor for many potential electrical/electronic and mechanical applications of nanostructured and conventional carbon materials. Here we demonstrate the formation of alloys that enable soldering of these structures. By addition of several percent (2.5-5%) of transition metal such as chromium or nickel to a standard lead-free soldering tin based alloy we obtained a solder that can be applied using a commercial soldering iron at typical soldering temperatures of approximately 350 °C and at ambient conditions. The use of this solder enables the formation of mechanically strong and electrically conductive joints between carbon materials and, when supported by a simple two-step technique, can successfully bond carbon structures to any metal terminal. It has been shown using optical and scanning electron microscope images as well as X-ray diffraction patterns and energy dispersive X-ray mapping that the successful formation of carbon-solder bonds is possible, first, thanks to the uniform nonreactive dispersion of transition metals in the tin-based matrix. Further, during the soldering process, these free elements diffuse into the carbon-alloy border with no formation of brazing-like carbides, which would damage the surface of the carbon materials. PMID:26256042

  2. Effect of Solder Joint Length on Fracture Under Bending

    NASA Astrophysics Data System (ADS)

    Akbari, Saeed; Nourani, Amir; Spelt, Jan K.

    2016-01-01

    Fracture tests were conducted on copper-solder-copper joints of various lengths using double-cantilever-beam (DCB) specimens under mode I loading conditions. The thickness and length of the solder joints were large enough to neglect any anisotropy associated with the solder microstructure. It was found that the critical strain energy release rate at crack initiation, G ci, was insensitive to the length of the solder joint; however, for joints shorter than a characteristic length which was a function of the thickness and the mechanical properties of the solder layer and the substrates, the fracture load increased with increasing solder joint length. A sandwich model was developed for the analysis of the stress and strain in solder joints, taking into account the influence of both the bending deformation and the shear deformation of the substrates on the solder joint stresses. Consistent with the experimental results, it was found that solder joints longer than the characteristic length have a maximum peel stress that remains unchanged with joint length, causing the joint strength to become independent of the joint length. A closed-form analytical solution was developed for the characteristic length of DCB specimens under mode I loading. The experimental results were in good agreement with the analytical model and with finite element results. The generality of the G ci failure criterion was demonstrated by comparing the experimental results and the fracture load predictions of mode I DCB solder joints with different lengths.

  3. Electronic interconnects and devices with topological surface states and methods for fabricating same

    DOEpatents

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2016-05-03

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

  4. Micro-fluidic interconnect

    DOEpatents

    Okandan, Murat; Galambos, Paul C.; Benavides, Gilbert L.; Hetherington, Dale L.

    2006-02-28

    An apparatus for simultaneously aligning and interconnecting microfluidic ports is presented. Such interconnections are required to utilize microfluidic devices fabricated in Micro-Electromechanical-Systems (MEMS) technologies, that have multiple fluidic access ports (e.g. 100 micron diameter) within a small footprint, (e.g. 3 mm.times.6 mm). Fanout of the small ports of a microfluidic device to a larger diameter (e.g. 500 microns) facilitates packaging and interconnection of the microfluidic device to printed wiring boards, electronics packages, fluidic manifolds etc.

  5. Polarity effect of electromigration on kinetics of intermetallic compound formation in Pb-free solder V-groove samples

    NASA Astrophysics Data System (ADS)

    Gan, H.; Tu, K. N.

    2005-03-01

    Intermetallic compound (IMC) formation is critical for the reliability of microelectronic interconnections, especially for flip chip solder joints. In this article, we investigate the polarity effect of electromigration on kinetics of IMC formation at the anode and the cathode in solder V-groove samples. We use V-groove solder line samples, with width of 100 μm and length of 500-700 μm, to study interfacial IMC growth between Cu electrodes and Sn-3.8Ag-0.7Cu (in wt %) solder under different current density and temperature settings. The current densities are in the range of 103 to 104A/cm2 and the temperature settings are 120, 150, and 180 °C. While the same types of IMCs, Cu6Sn5 and Cu3Sn, form at the solder/Cu interfaces independent of the passage of electric current, the growth of the IMC layer has been enhanced by electric current at the anode and inhibited at the cathode, in comparison with the no-current case. We present a kinetic model, based on the Cu mass transport in the sample, to explain the growth rate of IMC at the anode and cathode. The growth of IMC at the anode follows a parabolic growth rule, and we propose that the back stress induced in the IMC plays a significant role. The model is in good agreement with our experimental data. We then discuss the influence of both chemical force and electrical force, and their combined effect on the IMC growth with electric current.

  6. Investigation of Solder Cracking Problems on Printed Circuit Boards

    NASA Technical Reports Server (NTRS)

    Berkebile, M. J.

    1967-01-01

    A Solder Committee designated to investigate a solder cracking phenomena occurring on the SATURN electrical/electronic hardware found the cause to be induced stress in the soldered connections rather than faulty soldering techniques. The design of the printed circuit (PC) board assemblies did not allow for thermal expansion of the boards that occurred during normal operation. The difference between the thermal expansion properties of the boards and component lead materials caused stress and cracking in the soldered connections. The failure mechanism and various PC boards component mounting configurations are examined in this report. Effective rework techniques using flanged tubelets, copper tubelets, and soft copper wiring are detailed. Future design considerations to provide adequate strain relief in mounting configurations are included to ensure successful solder terminations.

  7. Optimal solder and power density for diode-laser tissue soldering (LTS)

    NASA Astrophysics Data System (ADS)

    Schwartz, Ian P.; Suh, Donald D.; Canning, Douglas A.; Snyder, Howard M., III; Zderic, Stephen A.; Kirsch, Andrew J.

    1998-07-01

    Purpose: The purpose of the study was to determine the optimal indocyanine green dye (ICG) concentration and laser power density (PD) for tissue soldering using an 808-nm diode laser. Methods: Temperature profiles in vitro and in vivo were obtained using the ICG/albumin solder. [ICG] ranged from 0.31 mg/mL to 20 mg/mL while PD ranged from 3.2 to 63.7 W/cm2. Solder color and textural changes were noted. Eighteen rats were subjected to 1.5 cm incisions (N equals 128) created on the dorsal skin followed by closure with LTS at varying PD and [ICG]. Tensile strength profiles using rat skin were taken immediately and 10 days postoperatively. Histological examination was performed at the time of sacrifice. Results: Temperature profiles of the ICG/albumin solder did not differ with varying [ICG], but showed statistically significant variability at different laser PD. Using solder color change as a subjective endpoint, average peak solder temperature ranged from 69 degrees Celsius at a PD of 8.0 W/cm2, 105 degrees Celsius to 120 degrees Celsius at PD 15.9 to 31.8 W/cm2, and greater than 200 degrees Celsius at PD greater than or equal to 47.7 W/cm2. Peak intradermal temperatures remained below 50 degrees Celsius at all PD. The broadest range of color change in the solder was observed at [ICG] of 2.5 mg/mL. Immediate tensile strength data showed a trend towards greater strength at higher [ICG]. The greatest immediate tensile strength was reached at a PD of greater than or equal to 31.8 W/cm2 for all [ICG]. At 10 days an inverse trend existed only between PD (not ICG) and tensile strength, however this was not statically significant. Histologic analysis showed poorer healing and thermal injury to tissue soldered at a PD greater than or equal to 23.9 W/cm2. Conclusions: Based on these findings, optimal laser tissue soldering occurs with an [ICG] of 2.5 mg/ml and a PD of 15.9 W/cm2.

  8. Thin film interconnect processes

    NASA Astrophysics Data System (ADS)

    Malik, Farid

    Interconnects and associated photolithography and etching processes play a dominant role in the feature shrinkage of electronic devices. Most interconnects are fabricated by use of thin film processing techniques. Planarization of dielectrics and novel metal deposition methods are the focus of current investigations. Spin-on glass, polyimides, etch-back, bias-sputtered quartz, and plasma-enhanced conformal films are being used to obtain planarized dielectrics over which metal films can be reliably deposited. Recent trends have been towards chemical vapor depositions of metals and refractory metal silicides. Interconnects of the future will be used in conjunction with planarized dielectric layers. Reliability of devices will depend to a large extent on the quality of the interconnects.

  9. Solder Creep-Fatigue Interactions with Flexible Leaded Part

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.; Wen, L. C.

    1994-01-01

    In most electronic packaging applications it is not a single high stress event that breaks a component solder joint; rather it is repeated or prolonged load applications that result in fatigue or creep failure of the solder. The principal strain in solder joints is caused by differential expansion between the part and its mounting environment due to hanges in temperature (thermal cycles) and/or due to temperature gradients between the part and the board.

  10. Capillary flow solderability test for printed wiring boards

    SciTech Connect

    Hosking, F.M.; Yost, F.G.; Hernandez, C.L.; Sackinger, S.J.

    1994-04-01

    This report describes a new technique for evaluating capillary flow solderability on printed circuit boards. The test involves the flow of molten solder from a pad onto different-sized conductor lines. It simulates the spreading dynamics of either plated-through-hole (PTH) or surface mount technology (SMT) soldering. A standard procedure has been developed for the test. Preliminary experiments were conducted and the results demonstrate test feasibility. Test procedures and results are presented in this report.

  11. Anomalous creep in Sn-rich solder joints

    SciTech Connect

    Song, Ho Geon; Morris Jr., John W.; Hua, Fay

    2002-03-15

    This paper discusses the creep behavior of example Sn-rich solders that have become candidates for use in Pb-free solder joints. The specific solders discussed are Sn-3.5Ag, Sn-3Ag-0.5Cu, Sn-0.7Cu and Sn-10In-3.1Ag, used in thin joints between Cu and Ni-Au metallized pads.

  12. Multilevel Dual Damascene copper interconnections

    NASA Astrophysics Data System (ADS)

    Lakshminarayanan, S.

    Copper has been acknowledged as the interconnect material for future generations of ICs to overcome the bottlenecks on speed and reliability present with the current Al based wiring. A new set of challenges brought to the forefront when copper replaces aluminum, have to be met and resolved to make it a viable option. Unit step processes related to copper technology have been under development for the last few years. In this work, the application of copper as the interconnect material in multilevel structures with SiO2 as the interlevel dielectric has been explored, with emphasis on integration issues and complete process realization. Interconnect definition was achieved by the Dual Damascene approach using chemical mechanical polishing of oxide and copper. The choice of materials used as adhesion promoter/diffusion barrier included Ti, Ta and CVD TiN. Two different polish chemistries (NH4OH or HNO3 based) were used to form the interconnects. The diffusion barrier was removed during polishing (in the case of TiN) or by a post CMP etch (as with Ti or Ta). Copper surface passivation was performed using boron implantation and PECVD nitride encapsulation. The interlevel dielectric way composed of a multilayer stack of PECVD SiO2 and SixNy. A baseline process sequence which ensured the mechanical and thermal compatibility of the different unit steps was first created. A comprehensive test vehicle was designed and test structures were fabricated using the process flow developed. Suitable modifications were subsequently introduced in the sequence as and when processing problems were encountered. Electrical characterization was performed on the fabricated devices, interconnects, contacts and vias. The structures were subjected to thermal stressing to assess their stability and performance. The measurement of interconnect sheet resistances revealed lower copper loss due to dishing on samples polished using HNO3 based slurry. Interconnect resistances remained stable upto 400o

  13. Zee electrical interconnect

    NASA Technical Reports Server (NTRS)

    Rust, Thomas M. (Inventor); Gaddy, Edward M. (Inventor); Herriage, Michael J. (Inventor); Patterson, Robert E. (Inventor); Partin, Richard D. (Inventor)

    2001-01-01

    An interconnect, having some length, that reliably connects two conductors separated by the length of the interconnect when the connection is made but in which one length if unstressed would change relative to the other in operation. The interconnect comprises a base element an intermediate element and a top element. Each element is rectangular and formed of a conducting material and has opposed ends. The elements are arranged in a generally Z-shape with the base element having one end adapted to be connected to one conductor. The top element has one end adapted to be connected to another conductor and the intermediate element has its ends disposed against the other end of the base and the top element. Brazes mechanically and electrically interconnect the intermediate element to the base and the top elements proximate the corresponding ends of the elements. When the respective ends of the base and the top elements are connected to the conductors, an electrical connection is formed therebetween, and when the conductors are relatively moved or the interconnect elements change length the elements accommodate the changes and the associated compression and tension forces in such a way that the interconnect does not mechanically fatigue.

  14. Carbon Nanotube Interconnects Realized through Functionalization and Sintered Silver Attachment.

    PubMed

    Gopee, V; Thomas, O; Hunt, C; Stolojan, V; Allam, J; Silva, S R P

    2016-03-01

    Carbon nanotubes (CNTs) in the form of interconnects have many potential applications, and their ability to perform at high temperatures gives them a unique capability. We show the development of a novel transfer process using CNTs and sintered silver that offers a unique high-temperature, high-conductivity, and potentially flexible interconnect solution. Arrays of vertically aligned multiwalled carbon nanotubes of approximately 200 μm in length were grown on silicon substrates, using low-temperature photothermal chemical vapor deposition. Oxygen plasma treatment was used to introduce defects, in the form of hydroxyl, carbonyl, and carboxyl groups, on the walls of the carbon nanotubes so that they could bond to palladium (Pd). Nanoparticle silver was then used to bind the Pd-coated multiwalled CNTs to a copper substrate. The silver-CNT-silver interconnects were found to be ohmic conductors, with resistivity of 6.2 × 10(-4) Ωm; the interconnects were heated to temperatures exceeding 300 °C (where common solders fail) and were found to maintain their electrical performance. PMID:26835786

  15. Coarsening of the Sn-Pb Solder Microstructure in Constitutive Model-Based Predictions of Solder Joint Thermal Mechanical Fatigue

    SciTech Connect

    Vianco, P.T.; Burchett, S.N.; Neilsen, M.K.; Rejent, J.A.; Frear, D.R.

    1999-04-12

    Thermal mechanical fatigue (TMF) is an important damage mechanism for solder joints exposed to cyclic temperature environments. Predicting the service reliability of solder joints exposed to such conditions requires two knowledge bases: first, the extent of fatigue damage incurred by the solder microstructure leading up to fatigue crack initiation, must be quantified in both time and space domains. Secondly, fatigue crack initiation and growth must be predicted since this metric determines, explicitly, the loss of solder joint functionality as it pertains to its mechanical fastening as well as electrical continuity roles. This paper will describe recent progress in a research effort to establish a microstructurally-based, constitutive model that predicts TMF deformation to 63Sn-37Pb solder in electronic solder joints up to the crack initiation step. The model is implemented using a finite element setting; therefore, the effects of both global and local thermal expansion mismatch conditions in the joint that would arise from temperature cycling.

  16. Solderability preservation through the use of organic inhibitors

    SciTech Connect

    Sorensen, N.R.; Hosking, F.M.

    1994-12-01

    Organic inhibitors can be used to prevent corrosion of metals and have application in the electronics industry as solderability preservatives. We have developed a model to describe the action of two inhibitors (benzotriazole and imidazole) during the environmental aging and soldering process. The inhibitors bond with the metal surface and form a barrier that prevents or retards oxidation. At soldering temperatures, the metal-organic complex breaks down leaving an oxide-free metal surface that allows excellent wetting by molten solder. The presence of the inhibitor retards the wetting rate relative to clean copper, but provides a vast improvement relative to oxidized copper.

  17. Aging, stressing and solderability of electroplated and electroless copper

    SciTech Connect

    Sorensen, N.R.; Hosking, F.M.

    1995-08-01

    Organic inhibitors can be used to prevent corrosion of metals have application in the electronics industry as solderability preservatives. We have developed a model to describe the action of two inhibitors (benzotriazole and imidazole) during the environmental aging and soldering process. The inhibitors bond with the metal surface and form a barrier that prevents or retards oxidation. At soldering temperatures, the metal-organic complex breaks down leaving an oxide-free metal surface that allows excellent wetting by the molten solder. The presence of the inhibitor retards the wetting rate relative to clean copper but provides a vast improvement relative to oxidized copper.

  18. Study of heating capacity of focused IR light soldering systems.

    PubMed

    Anguiano, C; Félix, M; Medel, A; Bravo, M; Salazar, D; Márquez, H

    2013-10-01

    An experimental study about four optical setups used for developing a Focused IR Light Soldering System (FILSS) for Surface Mount Technology (SMT) lead-free electronic devices specifically for Ball Grid Arrays (BGA) is presented. An analysis of irradiance and infrared thermography at BGA surface is presented, as well as heat transfer by radiation and conduction process from the surface of the BGA to the solder balls. The results of this work show that the heating provided by our proposed optical setups, measured at the BGA under soldering process, meets the high temperature and uniform thermal distribution requirements, which are defined by the reflow solder method for SMT devices. PMID:24104296

  19. High temperature solder alloys for underhood applications: Final report

    SciTech Connect

    Kern, J.A.; Drewien, C.A.; Yost, F.G.; Sackinger, S.; Weiser, M.W.

    1996-06-01

    In this continued study, the microstructural evolution and peel strength as a function of thermal aging were evaluated for four Sn-Ag solders deposited on double layered Ag-Pt metallization. Additionally, activation energies for intermetallic growth over the temperature range of 134 to 190{degrees}C were obtained through thickness measurements of the Ag-Sn intermetallic that formed at the solder-metallization interface. It was found that Bi-containing solders yielded higher activation energies for the intermetallic growth, leading to thicker intermetallic layers at 175 and 190{degrees}C for times of 542 and 20.5 hrs, respectively, than the solders free of Bi. Complete reaction of the solder with the metallization occurred and lower peel strengths were measured on the Bi-containing solders. In all solder systems, a Ag-Sn intermetallic thickness of greater than {approximately}7 {mu}m contributed to lower peel strength values. The Ag-Sn binary eutectic composition and the Ag-Sn-Cu ternary eutectic composition solders yielded lower activation energies for intermetallic formation, less microstructural change with time, and higher peel strengths; these solder systems were resilient to the effects of temperatures up to 175{degrees}C. Accelerated isothermal aging studies provide useful criteria for recommendation of materials systems. The Sn-Ag and Sn-Ag-Cu eutectic compositions should be considered for future service life and reliability studies based upon their performance in this study.

  20. Object-oriented graphical tool for automated laser soldering

    NASA Astrophysics Data System (ADS)

    Fidan, Ismail

    1995-10-01

    Object-oriented interfaces (OOIs) have become an important component of automation activity. Object-oriented software techniques have provided some hope to cope with the complexity of modern software development tasks. Object orientation is expressed by many researchers as an important direction in designing and implementing software in the 1990s and beyond. In today's electronics industry, there are several different types of interfaces used for different pieces of manufacturing equipment. It is now possible to create a general, OOI for most manufacturing equipment that is easy to use, easy to learn how to use, and easy to modify. Such an interface can benefit the user in terms of savings in time and money. The laser soldering interface, designed and implemented in the Center for Integrated Electronics and Electronics Manufacturing (CIEEM) at Rensselaer, is one of the 'flexible' user interfaces described above. This paper describes the object-oriented graphical tool (OOGT) development and its final structure.

  1. Magellan/Galileo solder joint failure analysis and recommendations

    NASA Technical Reports Server (NTRS)

    Ross, Ronald G., Jr.

    1989-01-01

    On or about November 10, 1988 an open circuit solder joint was discovered in the Magellan Radar digital unit (DFU) during integration testing at Kennedy Space Center (KSC). A detailed analysis of the cause of the failure was conducted at the Jet Propulsion Laboratory leading to the successful repair of many pieces of affected electronic hardware on both the Magellan and Galileo spacecraft. The problem was caused by the presence of high thermal coefficient of expansion heat sink and conformal coating materials located in the large (0.055 inch) gap between Dual Inline Packages (DIPS) and the printed wiring board. The details of the observed problems are described and recommendations are made for improved design and testing activities in the future.

  2. Nanoconstruction by welding individual metallic nanowires together using nanoscale solder

    NASA Astrophysics Data System (ADS)

    Peng, Y.; Cullis, A. G.; Inkson, B. J.

    2010-07-01

    This work presents a new bottom-up nanowelding technique enabling building blocks to be assembled and welded together into complex 3D nanostructures using nanovolumes of metal solder. The building blocks of gold nanowires, (Co72Pt28/Pt)n multilayer nanowires, and nanosolder Sn99Au1 alloy nanowires were successfully fabricated by a template technique. Individual metallic nanowires were picked up and assembled together. Conductive nanocircuits were then welded together using similar or dissimilar nanosolder material. At the weld sites, nanoscale volumes of a chosen metal are deposited using nanosolder of a sacrificial nanowire, which ensures that the nanoobjects to be bonded retain their structural integrity. The whole nanowelding process is clean, controllable and reliable, and ensures both mechanically strong and electrically conductive contacts.

  3. Transient Crack Growth Behavior Under Cycle/Time-Dependent Step Loading for Pb-Containing and Pb-Free Solders

    NASA Astrophysics Data System (ADS)

    Fakpan, Kittichai; Otsuka, Yuichi; Miyashita, Yukio; Mutoh, Yoshiharu; Nagata, Kohsoku

    2013-12-01

    In the present study, fatigue crack growth tests of Pb-containing [Sn-37Pb (wt.%)] and Pb-free [Sn-3.0Ag-0.5Cu (wt.%)] solders were performed under cycle/time-dependent step loading at a constant J-integral range (Δ J). The C * parameter was also estimated for discussing time-dependent crack growth behavior. The experimental results indicated that acceleration of the crack growth rate at the beginning of the second loading step was induced when the C * value for the first loading step was high, regardless of time- or cycle-dependent crack growth and for both Sn-37Pb and Sn-3.0Ag-0.5Cu solders. The length of the acceleration region of the crack growth rate for both solders was in good agreement with the creep damage zone size estimated by the creep zone model proposed by Riedel and Rice.

  4. Shaping Transistor Leads for Better Solder Joints

    NASA Technical Reports Server (NTRS)

    Mandel, H.; Dillon, J. D.

    1982-01-01

    Special lead-forming tool puts step in leads of microwave power transistors without damaging braze joints that fasten leads to package. Stepped leads are soldered to circuit boards more reliably than straight leads, and stress on brazes is relieved. Lead-forming hand-tool has two parts: a forming die and an actuator. Spring-loaded saddle is adjusted so that when transistor package is placed on it, leads rest on forming rails.

  5. Sn-Ag-Cu solders and solder joints: Alloy development, microstructure, and properties

    NASA Astrophysics Data System (ADS)

    Anderson, I. E.; Cook, B. A.; Harringa, J. L.; Terpstra, R. L.

    2002-06-01

    Slow cooling of Sn-Ag-Cu and Sn-Ag-Cu-X (X = Fe, Co) solder-joint specimens made by hand soldering simulated reflow in surface-mount assembly to achieve similar as-solidified joint microstructures for realistic shearstrength testing, using Sn-3.5Ag (wt.%) as a baseline. Minor substitutions of either cobalt or iron for copper in Sn-3.7Ag-0.9Cu refined the joint matrix microstructure, modified the Cu6Sn5 intermetallic phase at the copper substrate/solder interface, and increased the shear strength. At elevated (150°C) temperature, no significant difference in shear strength was found in all of the alloys studied. Ambient temperature shear strength was reduced by largescale tin dendrites in the joint microstructure, especially by the coarse dendrites in solute poor Sn-Ag-Cu.

  6. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1987-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  7. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1989-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  8. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-06-24

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  9. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-08-23

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  10. Application of optical interconnect technology at Lawrence Livermore National Laboratory

    SciTech Connect

    Haigh, R.E.; Lowry, M.E.; McCammon, K.; Hills, R.; Mitchell, R.; Sweider, D.

    1995-08-10

    Optical interconnects will be required to meet the information bandwidth requirements of future communication and computing applications. At Lawrence Livermore National Laboratory, the authors are involved in applying optical interconnect technologies in two distinct application areas: Multi-Gigabit/sec Computer Backplanes and Gigabit/sec Wide Area Networking using Wavelength Division Multiplexing. In this paper, the authors discuss their efforts to integrate optical interconnect technologies into prototype computing and communication systems.

  11. Solder joint reliability in alternator power diode assemblies

    SciTech Connect

    Pan, T.Y.; White, S.C.; Lutz, E.L.; Blair, H.D.; Nicholson, J.M.

    1999-11-01

    Power diodes in an alternator convert alternating current, generated by the spinning magnetic field, to direct current to be used by the battery and all the automotive electrical/electronic components. The diodes are press-fit into aluminum heatsinks to quickly and efficiently dissipate the heat from the silicon dies in the diode body. The diodes are soldered to a rectifier circuit board through the diode leads by a wave soldering process using a Pb-free, eutectic Sn-3.5Ag solder. A set of positive diodes reside on a different substrate than the set of negative diodes, resulting in differences in the lengths of the diode leads. The distance from the diode body to the solder joint on the leads of the positive diodes is 7 mm less than those of the negative diodes. Solderability, cross-section micrographs, and thermal-cycling fatigue reliability studies were compared between the positive and negative diodes and between diode designs from different suppliers. Wetting balance testing showed significant differences in solderability between positive and negative diodes and between the two different diode designs. Combining the diode body and lead together had a more drastic effect on the solderability than the lead alone. It was discovered that, although the nature of the diode design is to dissipate the heat away from the diode quickly and efficiently, there is a large temperature gradient along the lead immediately above the solder bath which can be as much as 100 C just 2 mm from the bath. This large temperature gradient caused some leads to be too cold to form good solder fillets. The solder fillets obtained in the laboratory wetting tests matched those observed in the actual alternators. The inadequate solder fillets resulted in a 250% difference in the thermal cycling fatigue reliability between the two diode designs.

  12. SOFC INTERCONNECT DEVELOPMENT

    SciTech Connect

    Diane M. England

    2004-03-16

    An interconnect for an SOFC stack is used to connect fuel cells into a stack. SOFC stacks are expected to run for 40,000 hours and 10 thermal cycles for the stationary application and 10,000 hours and 7000 thermal cycles for the transportation application. The interconnect of a stack must be economical and robust enough to survive the SOFC stack operation temperature of 750 C and must maintain the electrical connection to the fuel cells throughout the lifetime and under thermal cycling conditions. Ferritic and austenitic stainless steels, and nickel-based superalloys were investigated as possible interconnect materials for solid oxide fuel cell (SOFC) stacks. The alloys were thermally cycled in air and in a wet nitrogen-argon-hydrogen (N2-Ar-H2-H2O) atmosphere. Thermogravimetry was used to determine the parabolic oxidation rate constants of the alloys in both atmospheres. The area-specific resistance of the oxide scale and metal substrates were measured using a two-probe technique with platinum contacts. The study identifies two new interconnect designs which can be used with both bonded and compressive stack sealing mechanisms. The new interconnect designs offer a solution to chromium vaporization, which can lead to degradation of some (chromium-sensitive) SOFC cathodes.

  13. Solder self-assembled, surface micromachined MEMS for micromirror applications and atom trapping

    NASA Astrophysics Data System (ADS)

    McCarthy, Brian

    Solder self-assembly can be used to expand the versatility of a commercial foundry, like MEMSCAP's PolyMUMPs process. These foundries are attractive for prototyping MEMS as they can offer consistent, low cost fabrication runs by sticking to a single process and integrating multiple customers on each wafer. However, this standardization limits the utility of the process for a given application. Solder self-assembly gives back some of this versatility and expands the envelope of surface micromachining capability in the form of a simple post-process step. Here it is used to create novel micromirrors and micromirror arrays as well as to delve into the field of ultracold atom optics where the utility of MEMS as an enabling technology for atom control is explored. Two types of torsional, electrostatic micromirrors are demonstrated, both of which can achieve +/-10° of rotation. The first is a novel out-of-plane micromirror that can be rotated to a desired angle from the substrate. This integrated, on-chip assembly allows much simpler packaging technology to be used for devices that require a laser beam to be steered off-chip. Planar micromirror arrays that use solder self-assembly to tailor the electrode gap height are also demonstrated. With these designs, no special fabrication techniques are required to achieve large gap heights, and micromirrors with a variety of gap heights can even be fabricated on the same chip. Finally, solder self-assembly is used to explore how complex micro-scale structures can be used to control ultracold atoms. For this study, a MEMS version of a magneto-optical trap, the basis for most ultracold atomic systems, is used to control Rb atoms. In doing so, it provides a path for the successful integration of a number of MEMS devices in these types of systems.

  14. Novel Three-Dimensional Vertical Interconnect Technology for Microwave and RF Applications

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.

    1999-01-01

    In this paper, novel 3D interconnects suitable for applications in microwave and RF integrated circuit technology have been presented. The interconnect fabrication process and design details are presented. In addition, measured and numerically modeled results of the performance of the interconnects have been shown. The results indicate that the proposed technology has tremendous potential applications in integrated circuit technology. C,

  15. Impact of an Elevated Temperature Environment on Sn-Ag-Cu Interconnect Board Level High-G Mechanical Shock Performance

    NASA Astrophysics Data System (ADS)

    Lee, Tae-Kyu; Chen, Zhiqiang; Baty, Greg; Bieler, Thomas R.; Kim, Choong-Un

    2016-09-01

    The mechanical stability of Sn-Ag-Cu interconnects with low and high silver content against mechanical shock at room and elevated temperatures was investigated. With a heating element-embedded printed circuit board design, a test temperature from room temperature to 80°C was established. High impact shock tests were applied to isothermally pre-conditioned ball-grid array interconnects. Under cyclic shock testing, degradation and improved shock performances were identified associated with test temperature variation and non-solder mask defined and solder-mask defined pad design configuration differences. Different crack propagation paths were observed, induced by the effect of the elevated temperature test conditions and isothermal aging pre-conditions.

  16. Characterization of Solder Joint Reliability Using Cyclic Mechanical Fatigue Testing

    NASA Astrophysics Data System (ADS)

    Kim, Choong-Un; Bang, Woong-Ho; Xu, Huili; Lee, Tae-Kyu

    2013-10-01

    This article summarizes the mechanics of two mechanical fatigue methods, cyclic bending fatigue and shear fatigue, in inducing failure in solder joints in package assemblies, and it presents the characteristics of fatigue failures resulting from these methods using example cases of Sn-Pb eutectic and Sn-rich Pb-free solder alloys. Numerical simulation suggests that both testing configurations induce fatigue failure by the crack-opening mode. In the case of bending fatigue, the strain induced by the bending displacement is found to be sensitive to chip geometry, and it induces fatigue cracks mainly at the solder matrix adjacent to the printed circuit board interface. In case of shear fatigue, the failure location is firmly fixed at the solder neck, created by solder mask, where an abrupt change in the solder geometry occurs. Both methods conclude that the Coffin-Manson model is the most appropriate model for the isothermal mechanical fatigue of solder alloys. An analysis of fatigue characteristics using the frame of the Coffin-Manson model produces several insightful results, such as the reason why Pb-free alloys show higher fatigue resistance than Sn-Pb alloys even if they are generally more brittle. Our analysis suggests that it is related to higher work hardening. All these results indicate that mechanical fatigue can be an extremely useful method for fast screening of defective package structures and also in gaining a better understanding of fatigue failure mechanism and prediction of reliability in solder joints.

  17. Modified soldering iron speeds cutting of synthetic materials

    NASA Technical Reports Server (NTRS)

    Schafer, W. G., Jr.

    1966-01-01

    Modified soldering iron cuts large lots of synthetic materials economically without leaving frayed or jagged edges. The soldering iron is modified by machining an axial slot in its heating element tip and mounting a cutting disk in it. An alternate design has an axially threaded bore in the tip to permit the use of various shapes of cutting blades.

  18. Low-temperature solder for laser tissue welding

    NASA Astrophysics Data System (ADS)

    Lauto, Antonio; Stewart, Robert B.; Felsen, D.; Foster, John; Poole-Warren, Laura; Poppas, Dix P.

    2003-12-01

    In this study, a two layer (TL) solid solder was developed with a fixed thickness to minimize the difference in temperature across the solder (ΔT) and to weld at low temperature. Solder strips comprising two layers (65% albumin, 35% water) were welded onto rectangular sections of dog small intestine by a diode laser (λ = 808 nm). The laser delivered a power of 170 +/- 10 mW through an optical fiber (spot size approximately 1 mm) for 100 seconds. A solder layer incorporated also a dye (carbon black, 0.25%) to absorb the laser radiation. A thermocouple and an infrared thermometer system recorded the temperatures at the tissue interface and at the external solder surface, during welding. The repaired tissue was tested for tensile strength by a calibrated tensiometer. The TL strips were able to minimize ΔT (12 +/- 4°C) and control the temperature at tissue-interface. The strips fused on tissue at 55<=T<=62°C had higher tensile strength than the strips soldered at 51<=T<55°C (19.1 +/- 6.6 versus 13.1 +/- 6.4 gmf). The solid solder could efficiently weld at 60°C as it became insoluble and formed stable bonds with tissue. Fluid albumin solders, by contrast, requires temperatures >=70°C for tissue repair, which cause more irreversible thermal damage.

  19. Laser-activated protein solder for peripheral nerve repair

    NASA Astrophysics Data System (ADS)

    Trickett, Rodney I.; Lauto, Antonio; Dawes, Judith M.; Owen, Earl R.

    1995-05-01

    A 100 micrometers core optical fiber-coupled 75 mW diode laser operating at a wavelength of 800 nm has been used in conjunction with a protein solder to stripe weld severed rat tibial nerves, reducing the long operating time required for microsurgical nerve repair. Welding is produced by selective laser denaturation of the albumin based solder which contains the dye indocyanine green. Operating time for laser soldering was 10 +/- 5 min. (n equals 20) compared to 23 +/- 9 min. (n equals 10) for microsuturing. The laser solder technique resulted in patent welds with a tensile strength of 15 +/- 5 g, while microsutured nerves had a tensile strength of 40 +/- 10 g. Histopathology of the laser soldered nerves, conducted immediately after surgery, displayed solder adhesion to the outer membrane with minimal damage to the inner axons of the nerves. An in vivo study is under way comparing laser solder repaired tibial nerves to conventional microsuture repair. At the time of submission 15 laser soldered nerves and 7 sutured nerves were characterized at 3 months and showed successful regeneration with compound muscle action potentials of 27 +/- 8 mV and 29 +/- 8 mW respectively. A faster, less damaging and long lasting laser based anastomotic technique is presented.

  20. SOFC INTERCONNECT DEVELOPMENT

    SciTech Connect

    Diane M. England

    2003-06-06

    This report summarizes the interconnect work being performed at Delphi. Materials were chosen for this interconnect project were chosen from ferritic and austenitic stainless steels, and nickel-based superalloys. The alloys are thermally cycled in air and a wet hydrogen atmosphere. The oxide scale adherence, electrical resistance and oxidation resistance are determined after long-term oxidation of each alloy. The oxide scale adherence will be observed using a scanning electron microscope. The electrical resistance of the oxidized alloys will be determined using an electrical resistance measurement apparatus which has been designed and is currently being built. Data from the electrical resistance measurement is expected to be provided in the second quarter.

  1. Cost comparison modeling between current solder sphere attachment technology and solder jetting technology

    SciTech Connect

    Davidson, R.N.

    1996-10-01

    By predicting the total life-cycle cost of owning and operating production equipment, it becomes possible for processors to make accurate and intelligent decisions regarding major capitol equipment investments as well as determining the most cost effective manufacturing processes and environments. Cost of Ownership (COO) is a decision making technique based on inputting the total costs of acquiring, operating and maintaining production equipment. All quantitative economic and production data can be modeled and processed using COO software programs such as the Cost of Ownership Luminator program TWO COOL{trademark}. This report investigated the Cost of Ownership differences between the current state-of-the-art solder ball attachment process and a prototype solder jetting process developed by Sandia National Laboratories. The prototype jetting process is a novel and unique approach to address the anticipated high rate ball grid array (BGA) production requirements currently forecasted for the next decade. The jetting process, which is both economically and environmentally attractive eliminates the solder sphere fabrication step, the solder flux application step as well as the furnace reflow and post cleaning operations.

  2. Fluxless eutectic bonding of GaAs-on-Si by using Ag/Sn solder

    NASA Astrophysics Data System (ADS)

    Eo, Sung-Hwa; Kim, Dae-Seon; Jeong, Ho-Jung; Jang, Jae-Hyung

    2013-11-01

    Fluxless GaAs-on-Si wafer bonding using Ag/Sn solder was investigated to realize uniform and void-free heterogeneous material integration. The effects of the diffusion barrier, Ag/Sn thickness, and Ar plasma treatment were studied to achieve the optimal fluxless bonding process. Pt on a GaAs wafer and Mo on a Si wafer act as diffusion barriers by preventing the flow of Ag/Sn solder into both the wafers. The bonding strength is closely related to the Ag/Sn thickness and Ar plasma treatment. A shear strength test was carried out to investigate the bonding strength. Under identical bonding conditions, the Ag/Sn thickness was optimized to achieve higher bonding strength and to avoid the formation of voids due to thermal stress. An Ar plasma pretreatment process improved the bonding strength because the Ar plasma removed carbon contaminants and metal-oxide bonds from the metal surface.

  3. Dry soldering with hot filament produced atomic hydrogen

    DOEpatents

    Panitz, J.K.G.; Jellison, J.L.; Staley, D.J.

    1995-04-25

    A system is disclosed for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs. 1 fig.

  4. Dry soldering with hot filament produced atomic hydrogen

    DOEpatents

    Panitz, Janda K. G.; Jellison, James L.; Staley, David J.

    1995-01-01

    A system for chemically transforming metal surface oxides to metal that is especially, but not exclusively, suitable for preparing metal surfaces for dry soldering and solder reflow processes. The system employs one or more hot, refractory metal filaments, grids or surfaces to thermally dissociate molecular species in a low pressure of working gas such as a hydrogen-containing gas to produce reactive species in a reactive plasma that can chemically reduce metal oxides and form volatile compounds that are removed in the working gas flow. Dry soldering and solder reflow processes are especially applicable to the manufacture of printed circuit boards, semiconductor chip lead attachment and packaging multichip modules. The system can be retrofitted onto existing metal treatment ovens, furnaces, welding systems and wave soldering system designs.

  5. A Study of Solder Alloy Ductility for Cryogenic Applications

    NASA Technical Reports Server (NTRS)

    Lupinacci, A.; Shapiro, A. A.; Suh, J-O.; Minor, A. M.

    2013-01-01

    For aerospace applications it is important to understand the mechanical performance of components at the extreme temperature conditions seen in service. For solder alloys used in microelectronics, cryogenic temperatures can prove problematic. At low temperatures Sn-based solders undergo a ductile to brittle transition that leads to brittle cracks, which can result in catastrophic failure of electronic components, assemblies and spacecraft payloads. As industrial processes begin to move away from Pb-Sn solder, it is even more critical to characterize the behavior of alternative Sn-based solders. Here we report on initial investigations using a modified Charpy test apparatus to characterize the ductile to brittle transformation temperature of nine different solder systems.

  6. The influence of microstructure on the mechanical properties of solder

    SciTech Connect

    Morris, J.W. Jr.; Reynolds, H.L.

    1996-06-01

    Solder joints in microelectronics devices consist of low-melting solder compositions that wet and join metal contacts and are, ordinarily, used at high homologous temperatures in the as-solidified condition. Differences in solidification rate and substrate interactions have the consequence that even solder joints of similar compositions exhibit a wide range of microstructures. The variation in microstructure causes a variation in properties; in particular, the high-temperature creep properties that govern much of the mechanical behavior of the solder may differ significantly from joint to joint. The present paper reviews the varieties of microstructure that are found in common solder joints, and describes some of the ways in which microstructural changes affect mechanical properties and joint reliability.

  7. Nanoscale soldering of axially positioned single-walled carbon nanotubes: a molecular dynamics simulation study.

    PubMed

    Cui, Jianlei; Yang, Lijun; Zhou, Liang; Wang, Yang

    2014-02-12

    The miniaturization of electronics devices into the nanometer scale is indispensable for next-generation semi-conductor technology. Carbon nanotubes (CNTs) are considered to be the promising candidates for future interconnection wires. To study the carbon nanotubes interconnection during nanosoldering, the melting process of nanosolder and nanosoldering process between single-walled carbon nanotubes are simulated with molecular dynamics method. As the simulation results, the melting point of 2 nm silver solder is about 605 K because of high surface energy, which is below the melting temperature of Ag bulk material. In the nanosoldering process simulations, Ag atoms may be dragged into the nanotubes to form different connection configuration, which has no apparent relationship with chirality of SWNTs. The length of core filling nanowires structure has the relationship with the diameter, and it does not become longer with the increasing diameter of SWNT. Subsequently, the dominant mechanism of was analyzed. In addition, as the heating temperature and time, respectively, increases, more Ag atoms can enter the SWNTs with longer length of Ag nanowires. And because of the strong metal bonds, less Ag atoms can remain with the tight atomic structures in the gap between SWNT and SWNT. The preferred interconnection configurations can be achieved between SWNT and SWNT in this paper.

  8. Nanoscale soldering of axially positioned single-walled carbon nanotubes: a molecular dynamics simulation study.

    PubMed

    Cui, Jianlei; Yang, Lijun; Zhou, Liang; Wang, Yang

    2014-02-12

    The miniaturization of electronics devices into the nanometer scale is indispensable for next-generation semi-conductor technology. Carbon nanotubes (CNTs) are considered to be the promising candidates for future interconnection wires. To study the carbon nanotubes interconnection during nanosoldering, the melting process of nanosolder and nanosoldering process between single-walled carbon nanotubes are simulated with molecular dynamics method. As the simulation results, the melting point of 2 nm silver solder is about 605 K because of high surface energy, which is below the melting temperature of Ag bulk material. In the nanosoldering process simulations, Ag atoms may be dragged into the nanotubes to form different connection configuration, which has no apparent relationship with chirality of SWNTs. The length of core filling nanowires structure has the relationship with the diameter, and it does not become longer with the increasing diameter of SWNT. Subsequently, the dominant mechanism of was analyzed. In addition, as the heating temperature and time, respectively, increases, more Ag atoms can enter the SWNTs with longer length of Ag nanowires. And because of the strong metal bonds, less Ag atoms can remain with the tight atomic structures in the gap between SWNT and SWNT. The preferred interconnection configurations can be achieved between SWNT and SWNT in this paper. PMID:24392855

  9. A study of thermal cycling and radiation effects on indium and solder bump bonds

    SciTech Connect

    Simon Kwan et al.

    2001-12-11

    The BTeV hybrid pixel detector is constructed of readout chips and sensor arrays which are developed separately. The detector is assembled by flip-chip mating of the two parts. This method requires the availability of highly reliable, reasonably low cost fine-pitch flip-chip attachment technology. We have tested the quality of two bump-bonding technologies; indium bumps (by Advanced Interconnect Technology Ltd. (AIT) of Hong Kong) and fluxless solder bumps (by MCNC in North Carolina, USA). The results have been presented elsewhere [1]. In this paper we describe tests we performed to further evaluate these technologies. We subjected 15 indium bump-bonded and 15 fluxless solder bump-bonded dummy detectors through a thermal cycle and then a dose of radiation to observe the effects of cooling, heating and radiation on bump-bonds. We also exercised the processes of HDI mounting and wire bonding to some of the dummy detectors to see the effect of these processes on bump bonds.

  10. Open Systems Interconnection.

    ERIC Educational Resources Information Center

    Denenberg, Ray

    1985-01-01

    Discusses the need for standards allowing computer-to-computer communication and gives examples of technical issues. The seven-layer framework of the Open Systems Interconnection (OSI) Reference Model is explained and illustrated. Sidebars feature public data networks and Recommendation X.25, OSI standards, OSI layer functions, and a glossary.…

  11. Coplanar interconnection module

    NASA Technical Reports Server (NTRS)

    Steward, R. D.; Windsor, H. F.

    1970-01-01

    Module for interconnecting a semiconductor array to external leads or components incorporates a metal external heat sink for cooling the array. Heat sink, extending down from the molded block that supports the array, is immersed in a liquid nitrogen bath which is designed to maintain the desired array temperature.

  12. Interconnecting with VIPs

    ERIC Educational Resources Information Center

    Collins, Robert

    2013-01-01

    Interconnectedness changes lives. It can even save lives. Recently the author got to witness and be part of something in his role as a teacher of primary science that has changed lives: it may even have saved lives. It involved primary science teaching--and the climate. Robert Collins describes how it is all interconnected. The "Toilet…

  13. CAISSON: Interconnect Network Simulator

    NASA Technical Reports Server (NTRS)

    Springer, Paul L.

    2006-01-01

    Cray response to HPCS initiative. Model future petaflop computer interconnect. Parallel discrete event simulation techniques for large scale network simulation. Built on WarpIV engine. Run on laptop and Altix 3000. Can be sized up to 1000 simulated nodes per host node. Good parallel scaling characteristics. Flexible: multiple injectors, arbitration strategies, queue iterators, network topologies.

  14. Capillary interconnect device

    SciTech Connect

    Renzi, Ronald F

    2013-11-19

    An interconnecting device for connecting a plurality of first fluid-bearing conduits to a corresponding plurality of second fluid-bearing conduits thereby providing fluid communication between the first fluid-bearing conduits and the second fluid-bearing conduits. The device includes a manifold and one or two ferrule plates that are held by compressive axial forces.

  15. Printability Optimization For Fine Pitch Solder Bonding

    SciTech Connect

    Kwon, Sang-Hyun; Lee, Chang-Woo; Yoo, Sehoon

    2011-01-17

    Effect of metal mask and pad design on solder printability was evaluated by DOE in this study. The process parameters were stencil thickness, squeegee angle, squeegee speed, mask separating speed, and pad angle of PCB. The main process parameters for printability were stencil thickness and squeegee angle. The response surface showed that maximum printability of 1005 chip was achieved at the stencil thickness of 0.12 mm while the maximum printability of 0603 and 0402 chip was obtained at the stencil thickness of 0.05 mm. The bonding strength of the MLCC chips was also directly related with the printability.

  16. Hierarchical optical ring interconnection (HORN): scalable interconnection network for multiprocessors and multicomputers.

    PubMed

    Louri, A; Gupta, R

    1997-01-10

    A new interconnection network for massively parallel computing is introduced. This network is called a hierarchal optical ring interconnection (HORN). The HORN consists of a single-hop, scalable, constant-degree, strictly nonblocking, fault-tolerant interconnection topology that uses wavelength-division multiple access to provide better utilization of the terahertz bandwidth offered by optics. The proposed optical network integrates the attractive features of hierarchical ring interconnections, e.g., a simple node interface, a constant node degree, better support for the locality of reference, and fault tolerance, with the advantages of optics. The HORN topology is presented, its architectural properties are analyzed, and an optical design methodology for it is described. Furthermore, a brief feasibility study of the HORN is conducted. The study shows that the topology is highly amenable to optical implementation with commercially available optical elements.

  17. Soldering-based easy packaging of thin polyimide multichannel electrodes for neuro-signal recording

    NASA Astrophysics Data System (ADS)

    Baek, Dong-Hyun; Han, Chang-Hee; Jung, Ha-Chul; Kim, Seon Min; Im, Chang-Hwan; Oh, Hyun-Jik; Jungho Pak, James; Lee, Sang-Hoon

    2012-11-01

    We propose a novel packaging method for preparing thin polyimide (PI) multichannel microelectrodes. The electrodes were connected simply by making a via-hole at the interconnection pad of a thin PI electrode, and a nickel (Ni) ring was constructed by electroplating through the via-hole to permit stable soldering with strong adhesion to the electrode and the printed circuit board. The electroplating conditions were optimized for the construction of a well-organized Ni ring. The electrical properties of the packaged electrode were evaluated by fabricating and packaging a 40-channel thin PI electrode. Animal experiments were performed using the packaged electrode for high-resolution recording of somatosensory evoked potential from the skull of a rat. The in vivo and in vitro tests demonstrated that the packaged PI electrode may be used broadly for the continuous measurement of bio-signals or for neural prosthetics.

  18. Graphene Nanoribbons (GNRs) for Future Interconnect

    NASA Astrophysics Data System (ADS)

    Saptono Duryat, Rahmat

    2016-05-01

    Selecting and developing materials for the future devices require a sound understanding of design requirements. Miniaturization of electronic devices, as commonly expressed by Moore Law, has involved the integration level. Increase of the level has caused some consequences in the design and selection of materials for interconnection. The present paper deals with the challenge of materials design and selection beyond the nanoscale limit and the ability of traditional materials to cope with. One of the emerging materials, i.e. Graphene, will be reviewed with particular reference to its characteristics and potentials for future interconnection.

  19. Fuel cell system with interconnect

    DOEpatents

    Liu, Zhien; Goettler, Richard; Delaforce, Philip Mark

    2016-03-08

    The present invention includes a fuel cell system having an interconnect that reduces or eliminates diffusion (leakage) of fuel and oxidant by providing an increased densification, by forming the interconnect as a ceramic/metal composite.

  20. Global optical free-space smart interconnects

    NASA Astrophysics Data System (ADS)

    Guilfoyle, Peter S.; Hessenbruch, John M.; Zeise, Frederick F.

    1993-07-01

    High fan-in/fan-out, low power (1 fJ per gate), high performance computing (HPC) modules are being developed that integrate global (multidimensional) free space `smart' optical interconnects with GaAs DANE technology. This new architecture implements N4 global free space optical interconnects coupled with 2-D arrays of N-bit Boolean multiplications by DeMorgan's theorem on wide word fan-ins. `Smart' interconnects provide a high speed inter- module alternative without the power requirements and cross-talk limitations of GaAs circuitry. Selected algorithms such as 64-bit addition can operate at lower power and higher speeds using global technology and GaAs logic. Thus, faster processing can be fully realized which allows for a reduction in pipeline delays.

  1. Evolution of intrachip interconnects and performance constraints

    NASA Astrophysics Data System (ADS)

    Caignet, Fabrice; Collet, Jacques H.; Sellaye, F.

    2003-04-01

    This work aims at defining the marks that optoelectronic solutions will have to beat for replacing electric interconnects at chip level. Thus, we first anlayze the communication performance of future electrical interconnects considering the reduction of the lithographic feature size λ from 0.7 to 0.05 μm. We mostly analyze the results with reduced units: Lengths are calculated in multiples of λ times are compared to the chip clock cycle Tc that we estimate from the foreseeable evolution of the processor operation frequency. From our simulations, we conclude that: 1) it does not seem necessary to consider the integration of optical interconnects (OI) over distance shorter than 1000λ, because the performacne of electric interconnects is sufficient; 2) The penetration of IOs between blocks separated by more than 10λ could be envisaged provided that the present performence of OIs could be dramatically improved to beat electric solutions at chip level. New generations of low-threshold high-effieincy VCSELs and ultra-fast high-efficiency photodiode are needed; 3) The first possible application of OIs in chips is likely not for inter-block communication but for clock distribution as the energy constaints are weaker and because the clock tree is an extremely long interconnect.

  2. Electromigration of composite Sn-Ag-Cu solder bumps

    NASA Astrophysics Data System (ADS)

    Sharma, Ashutosh; Xu, Di Erick; Chow, Jasper; Mayer, Michael; Sohn, Heung-Rak; Jung, Jae Pil

    2015-11-01

    This study investigates the electromigration (EM) behavior of lead free Sn-Ag-Cu (SAC) solder alloys that were reinforced with different types of nanoparticles [Copper-coated carbon nanotubes (Cu/CNT), La2O3, Graphene, SiC, and ZrO2]. The composite solders were bumped on a Cu substrate at 220°C, and the resistance of the bumped solders was measured using a four wire setup. Current aging was carried out for 4 hours at a temperature of 160°C, and an increase in resistance was noted during this time. Of all the composite solders that were studied, La2O3 and SiC reinforced SAC solders exhibited the smallest resistances after current aging. However, the rate of change in the resistance at room temperature was lower for the SiC-reinforced SAC solder. The SAC and Graphene reinforced SAC solder bumps completely failed within 15 - 20 min of these tests. The SiC nanoparticles were reported to possibly entrap the SAC atoms better than other nanoparticles with a lower rate of EM. [Figure not available: see fulltext.

  3. Fatigue and thermal fatigue of Pb-Sn solder joints

    SciTech Connect

    Frear, D.; Grivas, D.; McCormack, M.; Tribula, D.; Morris, J.W. Jr.

    1987-01-01

    This paper presents a fundamental investigation of the fatigue and thermal fatigue characteristics, with an emphasis on the microstructural development during fatigue, of Sn-Pb solder joints. Fatigue tests were performed in simple shear on both 60Sn-40Pb and 5Sn-95Pb solder joints. Isothermal fatigue tests show increasing fatigue life of 60Sn-40Pb solder joints with decreasing strain and temperature. In contrast, such behavior was not observed in the isothermal fatigue of 5Sn-95Pb solder joints. Thermal fatigue results on 60Sn-40Pb solder cycled between -55/sup 0/C and 125/sup 0/C show that a coarsened region develops in the center of the joint. Both Pb-rich and Sn-rich phases coarsen, and cracks form within these coarsened regions. The failure mode 60Sn-40Pb solder joints in thermal and isothermal fatigue is similar: cracks form intergranularly through the Sn-rich phase or along Sn/Pb interphase boundaries. Extensive cracking is found throughout the 5Sn-95Pb joint for both thermal and isothermal fatigue. In thermal fatigue the 5Sn-95Pb solder joints failed after fewer cycles than 60Sn-40Pb.

  4. Simulation of thermomechanical fatigue in solder joints

    SciTech Connect

    Fang, H.E.; Porter, V.L.; Fye, R.M.; Holm, E.A.

    1997-12-31

    Thermomechanical fatigue (TMF) is a very complex phenomenon in electronic component systems and has been identified as one prominent degradation mechanism for surface mount solder joints in the stockpile. In order to precisely predict the TMF-related effects on the reliability of electronic components in weapons, a multi-level simulation methodology is being developed at Sandia National Laboratories. This methodology links simulation codes of continuum mechanics (JAS3D), microstructural mechanics (GLAD), and microstructural evolution (PARGRAIN) to treat the disparate length scales that exist between the macroscopic response of the component and the microstructural changes occurring in its constituent materials. JAS3D is used to predict strain/temperature distributions in the component due to environmental variable fluctuations. GLAD identifies damage initiation and accumulation in detail based on the spatial information provided by JAS3D. PARGRAIN simulates the changes of material microstructure, such as the heterogeneous coarsening in Sn-Pb solder, when the component`s service environment varies.

  5. Albumin-genipin solder for laser tissue welding

    NASA Astrophysics Data System (ADS)

    Lauto, Antonio; Foster, John; Avolio, Albert; Poole-Warren, Laura

    2004-07-01

    Background. Laser tissue soldering (LTS) is an alternative technique to suturing for tissue repair. One of the major drawbacks of LTS is the weak tensile strength of the solder welds when compared to sutures. In this study, the possibility was investigated for a low cytotoxic crosslinker, acting on amino groups, to enhance the bond strength of albumin solders. Materials and Methods. Solder strips were welded onto rectangular sections of sheep small intestine by a diode laser. The laser delivered in continuous mode mode a power of 170 +/- 10 mW at λ=808 nm, through a multimode optical fiber (core size = 200 μm) to achieve a dose of 10.8 +/- 0.5 J/mg. The solder thickness and surface area were kept constant throughout the experiment (thickness = 0.15 +/- 1 mm, area = 12 +/- 1.2 mm2). The solder incorporated 62% bovine serum albumin, 0.38% genipin, 0.25% indocyanin green dye (IG) and water. Tissue welding was also performed with a similar solder, which did not incorporate genipin, as a control group. The repaired tissue was tested for tensile strength by a calibrated tensiometer. Results. The tensile strength of the "genipin" solder was twice as high as the strength of the BSA solder (0.21 +/- 0.04 N and 0.11 +/- 0.04 N respectively; p~10-15 unpaired t-test, N=30). Discussion. Addition of a chemical crosslinking agent, such as genipin, significantly increased the tensile strength of adhesive-tissue bonds. A proposed mechanism for this enhanced bond strength is the synergistic action of mechanical adhesion with chemical crosslinking by genipin.

  6. Wettability analysis of tin-based, lead free solders

    SciTech Connect

    Vianco, P T; Hosking, F M; Rejent, J A

    1992-01-01

    The overall program is comprised of two efforts. The first effort studies the wettability of tin-based, lead free solders on two commonly used substrate materials: copper and gold-nickel plated Kovar{trademark}. The evaluation is being conducted by the meniscometer/wetting balance technique which uses the contact angle as the primary metric to quantify wettability. Information about the rate of wetting is also obtainable with this test. The second part of the program is comprised of an assessment of the solderability of actual circuit board assemblies (surface mount and through-hole). This report will describe data from the wettability analysis of lead free solders on copper.

  7. Solder extrusion pressure bonding process and bonded products produced thereby

    DOEpatents

    Beavis, L.C.; Karnowsky, M.M.; Yost, F.G.

    1992-06-16

    Disclosed is a process for production of soldered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about [minus]40 C and 110 C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  8. Solder extrusion pressure bonding process and bonded products produced thereby

    DOEpatents

    Beavis, Leonard C.; Karnowsky, Maurice M.; Yost, Frederick G.

    1992-01-01

    Production of soldered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about -40.degree. C. and 110.degree. C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  9. Thermal fatigue evaluation of solder alloys. Final report

    SciTech Connect

    Jarboe, D.M.

    1980-02-01

    An evaluation was made of the relative thermal fatigue resistance of 29 solder alloys. A number of these alloys were found to be less susceptible to thermal fatigue cracking in encapsulated printed wiring board applications than the commonly used tin-lead eutectic (63Sn-37Pb). Three alloys, 95Sn-5Ag, 96.5Sn-3.5Ag, and 95Sn-5Sb offered the greatest resistance to thermal fatigue. The selection of the encapsulation materials was confirmed to be a significant factor in thermal fatigue of solder joints, regardless of the solder alloy used.

  10. Controlling microstructure and mechanical properties of the new microelectronic interconnect alloys

    NASA Astrophysics Data System (ADS)

    Mutuku, Francis M.

    An in-depth understanding of the physics of solidification could lead to the optimization of the properties of micro-electronic interconnects. Sn is the base material in the billions of interconnects in devices such as smart phones. These interconnects are formed by melting and solidifying a solder alloy (e.g. SnAgCu) in situ. But Sn has a low symmetry structure, Sn nucleation from the solder melt is complex and the morphology of the Sn and Sn alloys precipitates that form during solidification can vary tremendously (along with resultant mechanical properties). The effect of processing parameters on the solidification behavior, microstructure, and properties must be carefully addressed. Strong evidence adduced in this study shows that under many conditions, when cooling near eutectic SnAgCu from the melt, Ag3Sn nucleates before beta-Sn. The difficulty in the nucleation of beta-Sn provides a window of time between the nucleation of Ag3Sn precipitates and of beta-Sn solidification within which the Ag3Sn precipitate morphology can be manipulated. Thus distinct variations in precipitate number density, and inter-particle spacing were observed for different thermal histories, e.g. for different cooling rates. The average number density of Ag3Sn particles and the area of the pseudo-eutectic phase were observed to increase with increase in the Ag concentration, and with increase in the cooling rate. The shear strength and shear fatigue life increased with increase in the area fraction of the pseudo-eutectic phase. Upon aging of SnAgCu solder joints at an elevated temperature, the Ag3Sn particles coarsened, and became less effective in impeding dislocation motion. Consequently, the shear strength and shear fatigue performance degraded. On the other hand, alloys with constituents that formed solid solutions in Sn, such as small concentrations of Bi or Sb registered less degradation in both shear strength and shear fatigue life upon aging.

  11. Energy and water in the Western and Texas interconnects.

    SciTech Connect

    Tidwell, Vincent Carroll

    2010-08-01

    The Department of Energy's Office of Electricity has initiated a $60M program to assist the electric industry in interconnection-level analysis and planning. The objective of this effort is to facilitate the development or strengthening of capabilities in each of the three interconnections serving the lower 48 states of the United States, to prepare analyses of transmission requirements under a broad range of alternative futures and develop long-term interconnection-wide transmission expansion plans. The interconnections are the Western Interconnection, the Eastern Interconnection, and the Texas Interconnection. One element of this program address the support and development of an integrated energy-water Decision Support System (DSS) that will enable planners in the Western and Texas Interconnections to analyze the potential implications of water stress for transmission and resource planning (the Eastern Interconnection is not participating in this element). Specific objectives include: (1) Develop an integrated Energy-Water Decision Support System (DSS) that will enable planners in the Western and Texas Interconnections to analyze the potential implications of water stress for transmission and resource planning. (2) Pursue the formulation and development of the Energy-Water DSS through a strongly collaborative process between members of this proposal team and the Western Electricity Coordinating Council (WECC), Western Governors Association (WGA), the Electric Reliability Council of Texas (ERCOT) and their associated stakeholder teams. (3) Exercise the Energy-Water DSS to investigate water stress implications of the transmission planning scenarios put forward by WECC, WGA, and ERCOT. The goals of this project are: (1) Develop an integrated Energy-Water Decision Support System (DSS) that will enable planners to analyze the potential implications of water stress for transmission and resource planning. (2) Pursue the formulation and development of the Energy

  12. High temperature solder alloys for underhood applications. Progress report

    SciTech Connect

    Drewien, C.A.; Yost, F.G.; Sackinger, S.; Kern, J.; Weiser, M.W.

    1995-02-01

    Under a cooperative research and development agreement with General Motors Corporation, lead-free solder systems including the flux, metallization, and solder are being developed for high temperature, underhood applications. Six tin-rich solders, five silver-rich metallizations, and four fluxes were screened using an experimental matrix whereby every combination was used to make sessile drops via hot plate or Heller oven processing. The contact angle, sessile drop appearance, and in some instances the microstructure was evaluated to determine combinations that would yield contact angles of less than 30{degrees}, well-formed sessile drops, and fine, uniform microstructures. Four solders, one metallization, and one flux were selected and will be used for further aging and mechanical property studies.

  13. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

    1987-10-23

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In molecular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating. 1 tab.

  14. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, Timothy J.; Ginley, David S.; Zipperian, Thomas E.

    1989-01-01

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

  15. Substrate solder barriers for semiconductor epilayer growth

    DOEpatents

    Drummond, T.J.; Ginley, D.S.; Zipperian, T.E.

    1989-05-09

    During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

  16. Investigation of gold embrittlement in connector solder joints

    NASA Technical Reports Server (NTRS)

    Lane, F. L.

    1972-01-01

    An investigation was performed to determine to what extent typical flight connector solder joints may be embrittled by the presence of gold. In addition to mapping of gold content in connector solder joints by an electron microprobe analyzer, metallographic examinations and mechanical tests (thermal shock, vibration, impact and tensile strength) were also conducted. A description of the specimens and tests, a discussion of the data, and some conclusions are presented.

  17. Building interconnected membrane networks.

    PubMed

    Holden, Matthew A

    2015-01-01

    Reconstituted replica cell membranes are easily created by contacting two lipid-monolayer-encased aqueous droplets under an oil phase. Called the droplet interface bilayer (DIB), this technique has been used to study a wide range of membrane processes. Importantly, this method is compatible with electrical measurements, meaning that membrane protein activities are easily observed in DIBs. By positioning droplets in two- and three-dimensional networks, sophisticated interconnected systems can be created that possess collective properties. The methods described here summarize the approaches used to create DIB networks and how to operate the devices that have been constructed so far.

  18. Carbon Nanotube Interconnect

    NASA Technical Reports Server (NTRS)

    Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

    2006-01-01

    Method and system for fabricating an electrical interconnect capable of supporting very high current densities ( 10(exp 6)-10(exp 10) Amps/sq cm), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOw, or SiuNv is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

  19. Solderability perservative coatings: Electroless tin vs. organic azoles

    SciTech Connect

    Artaki, I.; Ray, U.; Jackson, A.M.; Gordon, H.M.; Vianco, P.T.

    1993-07-01

    This paper compares the solderability performance and corrosions ion protection effectiveness of electroless tin coatings versus organic azole films after exposure to a series of humidity and thermal (lead-free solders) cycling conditions. The solderability of immersion tin is directly related to the tin oxide growth on the surface and is not affected by the formation of Sn-Cu intermetallic phases as long as the intermetallic phase is protected by a Sn layer. For a nominal tin thickness of 60{mu}inches, the typical thermal excursions associated with assembly are not sufficient to cause the intermetallic phase to consume the entire tin layer. Exposure to humidity at moderate to elevated temperatures promotes heavy tin oxide formation which leads to solderability loss. In contrast, thin azole films are more robust to humidity exposure; however upon heating in the presence of oxygen, they decompose and lead to severe solderability degradation. Evaluations of lead-free solder pastes for surface mount assembly applications indicate that immersion tin significantly improves the spreading of Sn:Ag and Sn:Bi alloys as compared to azole surface finishes.

  20. Eutectic Solder Bonding for Highly Manufacturable Microelectromechanical Systems Probe Card

    NASA Astrophysics Data System (ADS)

    Kim, Bonghwan

    2011-06-01

    We developed eutectic solder bonding for the microelectromechanical systems (MEMS) probe card. We tested various eutectic solder materials, such as Sn, AgSn, and AuSn, and investigated the bonding ability of Sn-based multi-element alloys and their resistance to chemical solutions. The Sn-based alloys were formed by sputtering, electroplating, and the use of solder paste. According to our experimental results, Sn-rich solders, such as Ag3.5Sn, Ag3.5Sn96Cu0.5, and Sn, were severely damaged by silicon wet etchant such as potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). On the other hand Au80Sn20 was resistant to those chemicals. In order to verify the joint bondability of the solders, we used a cantilever probe beam, and bump which were made of nickel and nickel alloy. After flip-chip bonding of the cantilever beam and the bump with Au80Sn20 solder paste, we measured the contact force to verify the mechanical strength. We then re-inspected it with X-rays and found no voids in the joint.

  1. Microsurgical anastomosis of sperm duct by laser tissue soldering

    NASA Astrophysics Data System (ADS)

    Wehner, Martin M.; Teutu-Kengne, Alain-Fleury; Brkovic, Drasko; Henning, Thomas; Klee, Doris; Poprawe, Reinhart; Jakse, Gerhard

    2005-04-01

    Connection of small vessels is usually done by suturing which is very cumbersome. Laser tissue soldering can circumvent that obstacle if a handy procedure can be defined. Our principle approach consists of a bioresorbable hollow stent with an expected degradation time of 3 weeks in combination with laser soldering. The stent is to be fed into the vessel to stabilize both ends and should allow percolation immediately after joining. The stents are made of Poly(D,L-lactid-co-glycolid) and solder is prepared from bovine serum albumin (BSA) doped with Indocyanine green (ICG) as chromophore to increase the absorption of laser light. After insertion, solder is applied onto the outer surface of the vessel and coagulated by laser radiation. The wavelength of 810 nm of a diode laser fits favorably to absorption properties of tissue and solder such that heating up of tissue is limited to prevent from necrosis and wound healing complications. In our study the preparation of stents, the consistency and doping of solder, a beam delivery instrument and the irradiation conditions are worked out. In-vitro tests are carried out on sperm ducts of Sprague-Dowlae (SD) rats. Different irradiation conditions are investigated and a micro-optical system consisting of a lens and a reflecting prism to ensure simultaneous irradiation of front and back side of the vessels tested. Under these conditions, the short-term rupture strength of laser anastomosis revealed as high as those achieved by suturing.

  2. Creep properties of Pb-free solder joints

    SciTech Connect

    Song, H.G.; Morris Jr., J.W.; Hua, F.

    2002-04-01

    Describes the creep behavior of three Sn-rich solders that have become candidates for use in Pb-free solder joints: Sn-3.5Ag, Sn-3Ag-0.5Cu and Sn-0.7Cu. The three solders show the same general behavior when tested in thin joints between Cu and Ni/Au metallized pads at temperatures between 60 and 130 C. Their steady-state creep rates are separated into two regimes with different stress exponents(n). The low-stress exponents range from {approx}3-6, while the high-stress exponents are anomalously high (7-12). Strikingly, the high-stress exponent has a strong temperature dependence near room temperature, increasing significantly as the temperature drops from 95 to 60 C. The anomalous creep behavior of the solders appears to be due to the dominant Sn constituent. Joints of pure Sn have stress exponents, n, that change with stress and temperature almost exactly like those of the Sn-rich solder joints. Research on creep in bulk samples of pure Sn suggests that the anomalous temperature dependence of the stress exponent may show a change in the dominant mechanism of creep. Whatever its source, it has the consequence that conventional constitutive relations for steady-state creep must be used with caution in treating Sn-rich solder joints, and qualification tests that are intended to verify performance should be carefully designed.

  3. Optical backplane interconnect switch for data processors and computers

    NASA Technical Reports Server (NTRS)

    Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

    1989-01-01

    An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

  4. Lead-free solder technology transfer from ASE Americas

    SciTech Connect

    FTHENAKIS,V.

    1999-10-19

    To safeguard the environmental friendliness of photovoltaics, the PV industry follows a proactive, long-term environmental strategy involving a life-of-cycle approach to prevent environmental damage by its processes and products from cradle to grave. Part of this strategy is to examine substituting lead-based solder on PV modules with other solder alloys. Lead is a toxic metal that, if ingested, can damage the brain, nervous system, liver and kidneys. Lead from solder in electronic products has been found to leach out from municipal waste landfills and municipal incinerator ash was found to be high in lead also because of disposed consumer electronics and batteries. Consequently, there is a movement in Europe and Japan to ban lead altogether from use in electronic products and to restrict the movement across geographical boundaries of waste containing lead. Photovoltaic modules may contain small amounts of regulated materials, which vary from one technology to another. Environmental regulations impact the cost and complexity of dealing with end-of-life PV modules. If they were classified as hazardous according to Federal or State criteria, then special requirements for material handling, disposal, record-keeping and reporting would escalate the cost of decommissioning the modules. Fthenakis showed that several of today's x-Si modules failed the US-EPA Toxicity Characteristic Leaching Procedure (TCLP) for potential leaching of Pb in landfills and also California's standard on Total Threshold Limit Concentration (TTLC) for Pb. Consequently, such modules may be classified as hazardous waste. He highlighted potential legislation in Europe and Japan which could ban or restrict the use of lead and the efforts of the printed-circuit industries in developing Pb-free solder technologies in response to such expected legislation. Japanese firms already have introduced electronic products with Pb-free solder, and one PV manufacturer in the US, ASE Americas has used a Pb

  5. Fuel cell system with interconnect

    DOEpatents

    Goettler, Richard; Liu, Zhien

    2015-03-10

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  6. Fuel cell system with interconnect

    DOEpatents

    Goettler, Richard; Liu, Zhien

    2015-08-11

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  7. Fuel cell system with interconnect

    DOEpatents

    Liu, Zhien; Goettler, Richard

    2015-09-29

    The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.

  8. Policy issues in interconnecting networks

    NASA Technical Reports Server (NTRS)

    Leiner, Barry M.

    1989-01-01

    To support the activities of the Federal Research Coordinating Committee (FRICC) in creating an interconnected set of networks to serve the research community, two workshops were held to address the technical support of policy issues that arise when interconnecting such networks. The workshops addressed the required and feasible technologies and architectures that could be used to satisfy the desired policies for interconnection. The results of the workshop are documented.

  9. Characterization of Low-Melting-Point Sn-Bi-In Lead-Free Solders

    NASA Astrophysics Data System (ADS)

    Li, Qin; Ma, Ninshu; Lei, YongPing; Lin, Jian; Fu, HanGuang; Gu, Jian

    2016-11-01

    Development of lead-free solders with low melting temperature is important for substitution of Pb-based solders to reduce direct risks to human health and the environment. In the present work, Sn-Bi-In solders were studied for different ratios of Bi and Sn to obtain solders with low melting temperature. The microstructure, thermal properties, wettability, mechanical properties, and reliability of joints with Cu have been investigated. The results show that the microstructures of the Sn-Bi-In solders were composed of β-Sn, Bi, and InBi phases. The intermetallic compound (IMC) layer was mainly composed of Cu6Sn5, and its thickness increased slightly as the Bi content was increased. The melting temperature of the solders was around 100°C to 104°C. However, when the Sn content exceeded 50 wt.%, the melting range became larger and the wettability became worse. The tensile strength of the solder alloys and solder joints declined with increasing Bi content. Two fracture modes (IMC layer fracture and solder/IMC mixed fracture) were found in solder joints. The fracture mechanism of solder joints was brittle fracture. In addition, cleavage steps on the fracture surface and coarse grains in the fracture structure were comparatively apparent for higher Bi content, resulting in decreased elongation for both solder alloys and solder joints.

  10. Characterization of Low-Melting-Point Sn-Bi-In Lead-Free Solders

    NASA Astrophysics Data System (ADS)

    Li, Qin; Ma, Ninshu; Lei, YongPing; Lin, Jian; Fu, HanGuang; Gu, Jian

    2016-02-01

    Development of lead-free solders with low melting temperature is important for substitution of Pb-based solders to reduce direct risks to human health and the environment. In the present work, Sn-Bi-In solders were studied for different ratios of Bi and Sn to obtain solders with low melting temperature. The microstructure, thermal properties, wettability, mechanical properties, and reliability of joints with Cu have been investigated. The results show that the microstructures of the Sn-Bi-In solders were composed of β-Sn, Bi, and InBi phases. The intermetallic compound (IMC) layer was mainly composed of Cu6Sn5, and its thickness increased slightly as the Bi content was increased. The melting temperature of the solders was around 100°C to 104°C. However, when the Sn content exceeded 50 wt.%, the melting range became larger and the wettability became worse. The tensile strength of the solder alloys and solder joints declined with increasing Bi content. Two fracture modes (IMC layer fracture and solder/IMC mixed fracture) were found in solder joints. The fracture mechanism of solder joints was brittle fracture. In addition, cleavage steps on the fracture surface and coarse grains in the fracture structure were comparatively apparent for higher Bi content, resulting in decreased elongation for both solder alloys and solder joints.

  11. Microbial leaching of waste solder for recovery of metal.

    PubMed

    Hocheng, H; Hong, T; Jadhav, U

    2014-05-01

    This study proposes an environment-friendly bioleaching process for recovery of metals from solders. Tin-copper (Sn-Cu), tin-copper-silver (Sn-Cu-Ag), and tin-lead (Sn-Pb) solders were used in the current study. The culture supernatant of Aspergillus niger removed metals faster than the culture supernatant of Acidithiobacillus ferrooxidans. Also, the metal removal by A. niger culture supernatant is faster for Sn-Cu-Ag solder as compared to other solder types. The effect of various process parameters such as shaking speed, temperature, volume of culture supernatant, and increased solder weight on bioleaching of metals was studied. About 99 (±1.75) % metal dissolution was achieved in 60 h, at 200-rpm shaking speed, 30 °C temperature, and by using 100-ml A. niger culture supernatant. An optimum solder weight for bioleaching was found to be 5 g/l. Addition of sodium hydroxide (NaOH) and sodium chloride (NaCl) in the bioleached solution from Sn-Cu-Ag precipitated tin (85 ± 0.35 %) and silver (80 ± 0.08 %), respectively. Passing of hydrogen sulfide (H2S) gas at pH 8.1 selectively precipitated lead (57.18 ± 0.13 %) from the Sn-Pb bioleached solution. The proposed innovative bioleaching process provides an alternative technology for recycling waste solders to conserve resources and protect environment. PMID:24634142

  12. Development of a new Pb-free solder: Sn-Ag-Cu

    SciTech Connect

    Miller, C.M.

    1995-02-10

    With the ever increasing awareness of the toxicity of Pb, significant pressure has been put on the electronics industry to get the Pb out of solder. This work pertains to the development and characterization of an alloy which is Pb-free, yet retains the proven positive qualities of current Sn-Pb solders while enhancing the shortcomings of Sn-Pb solder. The solder studied is the Sn-4.7Ag-1.7Cu wt% alloy. By utilizing a variety of experimental techniques the alloy was characterized. The alloy has a melting temperature of 217{degrees}C and exhibits eutectic melting behavior. The solder was examined by subjecting to different annealing schedules and examining the microstructural stability. The effect of cooling rate on the microstructure of the solder was also examined. Overall, this solder alloy shows great promise as a viable alternative to Pb-bearing solders and, as such, an application for a patent has been filed.

  13. Solder wetting behavior enhancement via laser-textured surface microcosmic topography

    NASA Astrophysics Data System (ADS)

    Chen, Haiyan; Peng, Jianke; Fu, Li; Wang, Xincheng; Xie, Yan

    2016-04-01

    In order to reduce or even replace the use of Sn-Pb solder in electronics industry, the laser-textured surface microstructures were used to enhance the wetting behavior of lead free solder during soldering. According to wetting theory and Sn-Ag-Cu lead free solder performance, we calculated and designed four microcosmic structures with the similar shape and different sizes to control the wetting behavior of lead free solder. The micro-structured surfaces with different dimensions were processed on copper plates by fiber femtosecond laser, and the effect of microstructures on wetting behavior was verified experimentally. The results showed that the wetting angle of Sn-Ag-Cu solder on the copper plate with microstructures decreased effectively compared with that on the smooth copper plate. The wetting angles had a sound fit with the theoretical values calculated by wetting model. The novel method provided a feasible route for adjusting the wetting behavior of solders and optimizing solders system.

  14. Three-dimensional optical lines fabricated onto substrate for on-board interconnection

    NASA Astrophysics Data System (ADS)

    Matsubara, Takahiro; Oda, Keiko; Watanabe, Keiichiro; Maetani, Maraki; Tanaka, Kaori; Tanahashi, Shigeo

    2009-02-01

    Optical lines using polymer materials fabricated on an organic substrate with metal lines and pads are proposed to realize fully optical interconnections among high performance LSIs. This optical line enable transmit high speed optical signals not only on a plane surface but to vertical direction. It has following four particular portions; (1) Curved parallel optical waveguide; (2) 45 degree reflection mirror; (3) Optical via hole with coaxial structure; (4) Optical joint between package and board. The optical line characterized by transmission loss and passed through eye diagram, and good optical signal transmission is confirmed to really use for optical interconnection between LSIs. Then on-board optical signal transmission is demonstrated by that VCSEL and PIN-PD are assembled using flip-chip technology on a circuit board with other electric devices of driving circuit, and also package-to-board optical joint are demonstrated by passing through solder reflow process.

  15. Methylene blue solder re-absorption in microvascular anastomoses

    NASA Astrophysics Data System (ADS)

    Birch, Jeremy F.; Hepplewhite, J.; Frier, Malcolm; Bell, Peter R. F.

    2003-06-01

    Soldered vascular anastomoses have been reported using several chromophores but little is known of the optimal conditions for microvascular anastomosis. There are some indications of the optimal protein contents of a solder, and the effects of methylene blue on anastomotic strength. The effects of varying laser power density in vivo have also been described, showing a high rate of thrombosis with laser power over 22.9Wcm-2. However no evidence exists to describe how long the solder remains at the site of the anastomosis. Oz et al reported that the fibrin used in their study had been almost completely removed by 90 days but without objective evidence of solder removal. In order to address the issue of solder re-absorption from the site of an anastomosis we used radio-labelled albumin (I-125) incorporated into methylene blue based solder. This was investigated in both the situation of the patent and thrombosed anastomosis with anastomoses formed at high and low power. Iodine-125 (half life: 60.2 days) was covalently bonded to porcine albumin and mixed with the solder solution. Radio-iodine has been used over many years to determine protein turnover using either I-125 or I-131. Iodine-125 labelled human albumin is regularly used as a radiopharmaceutical tool for the determination of plasma volume. Radio-iodine has the advantages of not affecting protein metabolism and the label is rapidly excreted after metabolic breakdown. Labelling with chromium (Cr-51) causes protein denaturation and is lost from the protein with time. Labelled albumin has been reported in human studies over a 21-day period, with similar results reported by Matthews. Most significantly McFarlane reported a different rate of catabolism of I-131 and I-125 over a 22-day period. The conclusion from this is that the rate of iodine clearance is a good indicator of protein catabolism. In parallel with the surgery a series of blank standards were prepared with a known mass of solder to correct for isotope

  16. Microstructural evolution of eutectic gold-tin solder joints

    NASA Astrophysics Data System (ADS)

    Song, Ho Geon

    Current trends toward miniaturization and the use of lead (Pb)-free solders in electronic packaging present new problems in the reliability of solder joints. This study was performed in order to understand the microstructure and microstructural evolution of small volumes of nominally eutectic Au-Sn solder joints (80Au-20Sn by weight), which gives insight into properties and reliability. The study particularly concentrated on the effects that the joint size and the type of substrate metallization have on both the bulk and interface microstructures of the joints. The systems studied were eutectic Au-Sn on Cu and Cu/electroless Ni/Au and for each system, two sets of sample geometries were used. Eutectic Au-Sn solder joints on Cu have microstructures that are very coarse on the scale of the joint, where the microstructure is strongly affected by the amount of Cu dissolution during reflow process. During aging, steady diffusion of Cu leads to the growth of Cu-rich interfacial intermetallic layers, significant consumption of substrate Cu, and formation of Kirkendall pores along the interface. Thermal cycling of the joints caused decomposition of the thick zeta(Cu)-phase into a fine-grained multiphase microstructure. The microstructures of eutectic Au-Sn solder joints on Cu/electroless Ni/Au are also very coarse due to the dissolution of Au used as a protective layer during soldering. Electroless Ni is shown to effectively act as a diffusion barrier for Cu. The electroless Ni near the interface evolves into a complicated structure due to the interfacial reaction. The solubility characteristics and diffusional behavior of substrate metals into eutectic Au-Sn solder determines the detailed microstructure and microstructural evolution of the ultrafine eutectic Au-Sn joints. Two important things to be noted from the results are as follows: First, the overall microstructures of these joints are very coarse with respect to the size of joint, and hence the properties of the

  17. Reliability of lead-free solders in electronic packaging technology

    NASA Astrophysics Data System (ADS)

    Choi, Woojin

    The electromigration of flip chip solder bump (eutetic SnPb) has been studied at temperatures of 100, 125 and 150°C and current densities of 1.9 to 2.75 x 104 A/cm2. The under-bump-metallization on the chip side is thin film Al/Ni(V)/Cu and on the board side is thick Cu. By simulation, we found that current crowding occurs at the corner on the chip side where the electrons enter the solder ball. We are able to match this simulation to the real electromigration damage in the sample. The experimental result showed that voids initiated from the position of current crowding and propagated across the interface between UBM and the solder ball. The Cu-Sn intermetallic compounds formed during the reflow is known to adhere well to the thin film UBM, but they detached from the UBM after current stressing. Therefore, the UBM itself becomes part of the reliability problem of the flip chip solder joint under electromigration. Currently there is a renewed interest in Sn whisker growth owing to the introduction of Pb-free solder in electronic manufacturing. The leadframe is electroplated or finished with a layer of Pb-free solder. The solder is typically pure Sn or eutectic SnCu (0.7 atomic % Cu). It is a serious reliability concern in the use of the eutectic SnCu solder as leadframe surface finish due to the growth of long whiskers on it. The origin of the driving force of compressive stress can be mechanical, thermal, and chemical. Among them, the chemical force is the most important contribution to the whisker growth and its origin is due to the reaction between Sn and Cu to form intermetallic compound (IMC) at room temperature. For whisker or hillock growth, the surface cannot be free of oxide and it must be covered with oxide and the oxide must be a protective one so that it removes effectively all the vacancy sources and sinks on the surface. Hence, only those metals, which grow protective oxides such as Al and Sn, are known to have hillock growth or whisker growth. We

  18. Experimental Methods in Reduced-gravity Soldering Research

    NASA Technical Reports Server (NTRS)

    Pettegrew, Richard D.; Struk, Peter M.; Watson, John K.; Haylett, Daniel R.

    2002-01-01

    The National Center for Microgravity Research, NASA Glenn Research Center, and NASA Johnson Space Center are conducting an experimental program to explore the influence of reduced gravity environments on the soldering process. An improved understanding of the effects of the acceleration environment is important to application of soldering during current and future human space missions. Solder joint characteristics that are being considered include solder fillet geometry, porosity, and microstructural features. Both through-hole and surface mounted devices are being investigated. This paper focuses on the experimental methodology employed in this project and the results of macroscopic sample examination. The specific soldering process, sample configurations, materials, and equipment were selected to be consistent with those currently on-orbit. Other apparatus was incorporated to meet requirements imposed by operation onboard NASA's KC-135 research aircraft and instrumentation was provided to monitor both the atmospheric and acceleration environments. The contingent of test operators was selected to include both highly skilled technicians and less skilled individuals to provide a population cross-section that would be representative of the skill mix that might be encountered in space mission crews.

  19. Solder creep-fatigue interactions with flexible leaded parts

    NASA Technical Reports Server (NTRS)

    Ross, R. G., Jr.; Wen, L. C.; Mon, G. R.; Jetter, E.

    1992-01-01

    With flexible leaded parts, the solder-joint failure process involves a complex interplay of creep and fatigue mechanisms. To better understand the role of creep in typical multi-hour cyclic loading conditions, a specialized non-linear finite-element creep simulation computer program has been formulated. The numerical algorithm includes the complete part-lead-solder-PWB system, accounting for strain-rate dependence of creep on applied stress and temperature, and the role of the part-lead dimensions and flexibility that determine the total creep deflection (solder strain range) during stress relaxation. The computer program has been used to explore the effects of various solder creep-fatigue parameters such as lead height and stiffness, thermal-cycle test profile, and part/board differential thermal expansion properties. One of the most interesting findings is the strong presence of unidirectional creep-ratcheting that occurs during thermal cycling due to temperature dominated strain-rate effects. To corroborate the solder fatigue model predictions, a number of carefully controlled thermal-cycle tests have been conducted using special bimetallic test boards.

  20. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  1. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  2. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  3. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  4. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  5. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  6. 30 CFR 77.1916 - Welding, cutting, and soldering; fire protection.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, and soldering; fire... OF UNDERGROUND COAL MINES Slope and Shaft Sinking § 77.1916 Welding, cutting, and soldering; fire protection. (a) One portable fire extinguisher shall be provided where welding, cutting, or soldering...

  7. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  8. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  9. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  10. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  11. 30 CFR 75.1106 - Welding, cutting, or soldering with arc or flame underground.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, or soldering with arc or... Protection § 75.1106 Welding, cutting, or soldering with arc or flame underground. All welding, cutting, or... conducted in fireproof enclosures. Welding, cutting, or soldering with arc or flame in other than...

  12. 30 CFR 77.1112 - Welding, cutting, or soldering with arc or flame; safeguards.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, or soldering with arc or... WORK AREAS OF UNDERGROUND COAL MINES Fire Protection § 77.1112 Welding, cutting, or soldering with arc or flame; safeguards. (a) When welding, cutting, or soldering with arc or flame near...

  13. Oblique incidence of semi-guided waves on step-like folds in planar dielectric slabs: Lossless vertical interconnects in 3D integrated photonic circuits

    NASA Astrophysics Data System (ADS)

    Hildebrandt, Andre; Alhaddad, Samer; Hammer, Manfred; Förstner, Jens

    2016-02-01

    Semi-guided light propagation across linear folds of slab waveguides is being considered. Radiation losses vanish beyond certain critical angles of incidence, as can be understood by arguments resembling Snell's law. One thus realizes lossless propagation through 90-degree corner configurations, where the remaining guided waves are still subject to pronounced reflection and polarization conversion. A step-like system of two of these sharp corners can then be viewed as a system akin to a Fabry-Perot interferometer, with two partial reflectors at a distance given by the vertical separation of the slab cores. The respective resonance effect enables full transmission of semiguided, laterally plane waves through the step structures. One obtains a configuration that optically connects guiding layers at different elevation levels in a 3-D integrated optical chip, without radiation losses, over large distances, and reasonably broadband. We show rigorous quasi-analytical results for typical high-contrast Si/SiO2 structures. Although the full-transmission effect requires a symmetric system, here realized by slab waveguides with a silicon core sandwiched between thick silica substrate and cover layers, simulations for configurations with air cover show that a certain asymmetry can well be afforded.

  14. Hydraulically interconnected vehicle suspension: background and modelling

    NASA Astrophysics Data System (ADS)

    Zhang, Nong; Smith, Wade A.; Jeyakumaran, Jeku

    2010-01-01

    This paper presents a novel approach for the frequency domain analysis of a vehicle fitted with a general hydraulically interconnected suspension (HIS) system. Ideally, interconnected suspensions have the capability, unique among passive systems, to provide stiffness and damping characteristics dependent on the all-wheel suspension mode in operation. A basic, lumped-mass, four-degree-of-freedom half-car model is used to illustrate the proposed methodology. The mechanical-fluid boundary condition in the double-acting cylinders is modelled as an external force on the mechanical system and a moving boundary on the fluid system. The fluid system itself is modelled using the hydraulic impedance method, in which the relationships between the dynamic fluid states, i.e. pressures and flows, at the extremities of a single fluid circuit are determined by the transfer matrix method. A set of coupled, frequency-dependent equations, which govern the dynamics of the integrated half-car system, are then derived and the application of these equations to both free and forced vibration analysis is explained. The fluid system impedance matrix for the two general wheel-pair interconnection types-anti-synchronous and anti-oppositional-is also given. To further outline the application of the proposed methodology, the paper finishes with an example using a typical anti-roll HIS system. The integrated half-car system's free vibration solutions and frequency response functions are then obtained and discussed in some detail. The presented approach provides a scientific basis for investigating the dynamic characteristics of HIS-equipped vehicles, and the results offer further confirmation that interconnected suspension schemes can provide, at least to some extent, individual control of modal stiffness and damping characteristics.

  15. An Overview of Surface Finishes and Their Role in Printed Circuit Board Solderability and Solder Joint Performance

    SciTech Connect

    Vianco, P.T.

    1998-10-15

    A overview has been presented on the topic of alternative surface finishes for package I/Os and circuit board features. Aspects of processability and solder joint reliability were described for the following coatings: baseline hot-dipped, plated, and plated-and-fused 100Sn and Sn-Pb coatings; Ni/Au; Pd, Ni/Pd, and Ni/Pd/Au finishes; and the recently marketed immersion Ag coatings. The Ni/Au coatings appear to provide the all-around best option in terms of solderability protection and wire bondability. Nickel/Pal ftishes offer a slightly reduced level of performance in these areas that is most likely due to variable Pd surface conditions. It is necessmy to minimize dissolved Au or Pd contents in the solder material to prevent solder joint embrittlement. Ancillary aspects that included thickness measurement techniques; the importance of finish compatibility with conformal coatings and conductive adhesives; and the need for alternative finishes for the processing of non-Pb bearing solders were discussed.

  16. Effects of solder temperature on pin through-hole during wave soldering: thermal-fluid structure interaction analysis.

    PubMed

    Aziz, M S Abdul; Abdullah, M Z; Khor, C Y

    2014-01-01

    An efficient simulation technique was proposed to examine the thermal-fluid structure interaction in the effects of solder temperature on pin through-hole during wave soldering. This study investigated the capillary flow behavior as well as the displacement, temperature distribution, and von Mises stress of a pin passed through a solder material. A single pin through-hole connector mounted on a printed circuit board (PCB) was simulated using a 3D model solved by FLUENT. The ABAQUS solver was employed to analyze the pin structure at solder temperatures of 456.15 K (183(°)C) < T < 643.15 K (370(°)C). Both solvers were coupled by the real time coupling software and mesh-based parallel code coupling interface during analysis. In addition, an experiment was conducted to measure the temperature difference (ΔT) between the top and the bottom of the pin. Analysis results showed that an increase in temperature increased the structural displacement and the von Mises stress. Filling time exhibited a quadratic relationship to the increment of temperature. The deformation of pin showed a linear correlation to the temperature. The ΔT obtained from the simulation and the experimental method were validated. This study elucidates and clearly illustrates wave soldering for engineers in the PCB assembly industry. PMID:25225638

  17. Corrosion Issues in Solder Joint Design and Service

    SciTech Connect

    VIANCO,PAUL T.

    1999-11-24

    Corrosion is an important consideration in the design of a solder joint. It must be addressed with respect to the service environment or, as in the case of soldered conduit, as the nature of the medium being transported within piping or tubing. Galvanic-assisted corrosion is of particular concern, given the fact that solder joints are comprised of different metals or alloy compositions that are in contact with one-another. The (thermodynamic) potential for corrosion to take place in a particular environment requires the availability of the galvanic series for those conditions and which includes the metals or alloys in question. However, the corrosion kinetics, which actually determine the rate of material loss under the specified service conditions, are only available through laboratory evaluations or field data that are found in the existing literature or must be obtained by in-house testing.

  18. Solder wetting kinetics in narrow V-grooves

    SciTech Connect

    Yost, F.G.; Rye, R.R.; Mann, J.A. Jr.

    1997-12-01

    Experiments are performed to observe capillary flow in grooves cut into copper surfaces. Flow kinetics of two liquids, 1-heptanol and eutectic Sn-Pb solder, are modeled with modified Washburn kinetics and compared to flow data. It is shown that both liquids flow parabolically in narrow V-grooves, and the data scale as predicted by the modified Washburn model. The early portions of the flow kinetics are characterized by curvature in the length vs time relationship which is not accounted for in the modified Washburn model. This effect is interpreted in terms of a dynamic contact angle. It is concluded that under conditions of rapid flow, solder spreading can be understood as a simple fluid flow process. Slower kinetics, e.g. solder droplet spreading on flat surfaces, may be affected by subsidiary chemical processes such as reaction.

  19. Development of alternatives to lead-bearing solders

    SciTech Connect

    Vianco, P.T.

    1993-07-01

    Soldering technology, using tin-lead alloys has had a significant role in the packaging of highly functional, low cost electronic devices. The elimination of lead from all manufactured products, whether through legislation or tax incentives, will impact the electronics community which uses lead-containing solders. In response to these proposed measures, the National Center for Manufacturing Sciences has established a multi-year program involving participants from industry, academia, and the national laboratories with the objective to identify potential replacements for lead-bearing solders. Selection of candidate alloys is based upon the analysis of materials properties, manufacturability, modeling codes for reliability prediction, as well as toxicological properties and resource availability, data developed in the program.

  20. Materials chemistry. Composition-matched molecular "solders" for semiconductors.

    PubMed

    Dolzhnikov, Dmitriy S; Zhang, Hao; Jang, Jaeyoung; Son, Jae Sung; Panthani, Matthew G; Shibata, Tomohiro; Chattopadhyay, Soma; Talapin, Dmitri V

    2015-01-23

    We propose a general strategy to synthesize largely unexplored soluble chalcogenidometallates of cadmium, lead, and bismuth. These compounds can be used as "solders" for semiconductors widely used in photovoltaics and thermoelectrics. The addition of solder helped to bond crystal surfaces and link nano- or mesoscale particles together. For example, CdSe nanocrystals with Na2Cd2Se3 solder was used as a soluble precursor for CdSe films with electron mobilities exceeding 300 square centimeters per volt-second. CdTe, PbTe, and Bi2Te3 powders were molded into various shapes in the presence of a small additive of composition-matched chalcogenidometallate or chalcogel, thus opening new design spaces for semiconductor technologies. PMID:25569110

  1. Reliability assessment of indium solder for low temperature electronic packaging

    NASA Astrophysics Data System (ADS)

    Chang, Rui W.; Patrick McCluskey, F.

    2009-11-01

    Indium is the choice of material for cryogenic joining applications. It is superior under repeated wide temperature excursions including extreme cold temperatures (below -55 °C) because of its excellent electrical conductivity and ductility at cryogenic temperatures. In particular, it is being considered for die/substrate attaches in low temperature SiGe BiCMOS modules for Martian and Lunar exploration. An efficient and systematic assessment was conducted to evaluate the reliability of indium solder under thermal fatigue and extended cold temperature mechanical fatigue conditions encountered in space exploration missions. In addition, fatigue failure sites, modes and mechanisms in indium solder at low temperature were investigated. A fatigue model was also calibrated for indium solder joint at cryogenic temperatures.

  2. Materials chemistry. Composition-matched molecular "solders" for semiconductors.

    PubMed

    Dolzhnikov, Dmitriy S; Zhang, Hao; Jang, Jaeyoung; Son, Jae Sung; Panthani, Matthew G; Shibata, Tomohiro; Chattopadhyay, Soma; Talapin, Dmitri V

    2015-01-23

    We propose a general strategy to synthesize largely unexplored soluble chalcogenidometallates of cadmium, lead, and bismuth. These compounds can be used as "solders" for semiconductors widely used in photovoltaics and thermoelectrics. The addition of solder helped to bond crystal surfaces and link nano- or mesoscale particles together. For example, CdSe nanocrystals with Na2Cd2Se3 solder was used as a soluble precursor for CdSe films with electron mobilities exceeding 300 square centimeters per volt-second. CdTe, PbTe, and Bi2Te3 powders were molded into various shapes in the presence of a small additive of composition-matched chalcogenidometallate or chalcogel, thus opening new design spaces for semiconductor technologies.

  3. Electrical nanowelding and bottom-up nano-construction together using nanoscale solder.

    PubMed

    Peng, Yong; Cullis, Tony; Inkson, Beverley J

    2010-11-01

    A new bottom-up nanowelding technique enabling the welding of complex 3D nanoarchitectures assembled from individual building blocks using nanovolumes of metal solder is reported in this work. The building blocks of gold nanowires, (Co72Pt28/Pt)n multilayer nanowires, and nanosolder Sn99Au1 alloy nanowires were successfully fabricated by a template technique. Individual metallic nanowires dispersed on Si/SiO2(100 nm) wafers were manipulated and assembled together. Conductive nanostructures were then welded together by the new electrical nanowelding technique using nanovolumes of similar or dissimilar nanosolder. At the weld sites, nanoscale volumes of a chosen metal are deposited using nanosolder of a sacrificial nanowire, which ensures that the nanoobjects to be bonded retain their structural integrity. The whole nanowelding process is clean, controllable and reliable, and ensures both mechanically strong and electrically conductive contacts. The quality check of nanoweld achieve a resistance as low as 20 omega by using Sn99Au1 alloy solder. This technique should provide a promising way to conquer the challenge of the integration obstacle for bottom-up nanotechnology.

  4. Optics vs copper: from the perspective of "Thunderbolt" interconnect technology

    NASA Astrophysics Data System (ADS)

    Cheng, Hengju; Krause, Christine; Ko, Jamyuen; Gao, Miaobin; Liu, Guobin; Wu, Huichin; Qi, Mike; Lam, Chun-Chit

    2013-02-01

    Interconnect technology has been progressed at a very fast pace for the past decade. The signaling rates have steadily increased from 100:Mb/s to 25Gb/s. In every generation of interconnect technology evolution, optics always seems to take over at first, however, at the end, the cost advantage of copper wins over. Because of this, optical interconnects are limited to longer distance links where the attenuation in copper cable is too large for the integrated circuits to compensate. Optical interconnect has long been viewed as the premier solution in compared with copper interconnect. With the release of Thunderbolt technology, we are entering a new era in consumer electronics that runs at 10Gb/s line rate (20Gb/s throughput per connector interface). Thunderbolt interconnect technology includes both active copper cables and active optical cables as the transmission media which have very different physical characteristics. In order for optics to succeed in consumer electronics, several technology hurdles need to be cleared. For example, the optical cable needs to handle the consumer abuses such as pinch and bend. Also, the optical engine used in the active optical cable needs to be physically very small so that we don't change the looks and feels of the cable/connector. Most importantly, the cost of optics needs to come down significantly to effectively compete with the copper solution. Two interconnect technologies are compared and discussed on the relative cost, power consumption, form factor, density, and future scalability.

  5. Integration of thin film decoupling capacitors

    SciTech Connect

    Garino, T.; Dimos, D.; Lockwood, S.

    1994-10-01

    Thin film decoupling capacitors consisting of submicron thick, sol-gel Pb(Zr,Ti)O{sub 3} layers between Pt electrodes on a Si substrate have recently been developed. Because the capacitor structure needs to be only {approximately}3 {mu}m thick, these devices offer advantages such as decreased package volume and ability to integrate so that interconnect inductance is decreased, which allows faster IC processing rates. To fully utilize these devices, techniques of integrating them onto packages such as multi-chip modules and printed wiring boards or onto IC dies must be developed. The results of our efforts at developing integration processes for these capacitors are described here. Specifically, we have demonstrated a process for printing solder on the devices at the Si wafer level and reflowing it to form bumps and have developed a process for fabricating the devices on thin (25 to 75 {mu}m) substrates to facilitate integration onto ICs and printed wiring boards. Finally, we assessed the feasibility of fabricating the devices on rough surfaces to determine whether it would be possible to fabricate these capacitors directly on multi-layer ceramic substrates.

  6. A ban on use of lead-bearing solders: Implications for the electronics industry

    SciTech Connect

    Vianco, P.T.; Yost, F.G.

    1992-04-01

    This white paper addresses the issue of banning lead from solders used in electronics manufacturing. The current efforts by legislative bodies and regulatory agencies to curtail the use of lead in manufactured goods, including solders, are described. In response to a ban on lead or the imposition of a tax which makes lead uneconomical for use in solder alloys, alternative technologies including lead-free solders and conductive epoxies are presented. The recommendation is made that both users and producers of solder materials join together as partners in a consortium to address this issue in a timely and cost-effective manner.

  7. Comparison of isopropyl alcohol and trichloroethylene in removing solder flux: Topical report

    SciTech Connect

    Benkovich, M.G.

    1988-01-01

    This work evaluated a nontoxic solvent for its ability to remove solder flux as compared to trichloroethylene solvent. Isopropyl alcohol was evaluated for its cleaning efficiency for solder flux removal using a high pressure spray process (minimum spray pressure of 80 psig). Cleanliness levels were measured by the Meseran Surface Analyzer. Test samples also underwent gas chromatograph/mass spectrometer Analysis and were visually inspected under a longwave ultraviolet lamp. Detailed analyses of flux removal by the two solvents were made as related to solder flux types, solder flux diluted by 50% with isopropyl alcohol, and solder process conditions. 2 refs., 2 figs., 12 tabs.

  8. Process characterization and control of hand-soldered printed wiring assemblies

    SciTech Connect

    Cheray, D.L.; Mandl, R.G.

    1993-09-01

    A designed experiment was conducted to characterize the hand soldering process parameters for manufacturing printed wiring assemblies (PWAs). Component tinning was identified as the most important parameter in hand soldering. After tinning, the soldering iron tip temperature of 700{degrees}F and the choice of operators influence solder joint quality more than any other parameters. Cleaning and flux/flux core have little impact on the quality of the solder joint. The need for component cleaning prior to assembly must be evaluated for each component.

  9. Preparation of Sn—Ag—In ternary solder bumps by electroplating in sequence and reliability

    NASA Astrophysics Data System (ADS)

    Dongliang, Wang; Yuan, Yuan; Le, Luo

    2011-08-01

    This paper describes a technique that can obtain ternary Sn—Ag—In solder bumps with fine pitch and homogenous composition distribution. The mainfeature of this process is that tin-silver and indium are electroplated on copper under bump metallization (UBM) in sequence. After an accurate reflow process, Sn1.8Ag9.4In solder bumps are obtained. It is found that the intermetallic compounds (IMCs) between Sn—Ag—In solder and Cu grow with the reflow time, which results in an increase in Ag concentration in the solder area. So during solidification, more Ag2In nucleates and strengthens the solder.

  10. Solder extrusion pressure bonding process and bonded products produced thereby

    SciTech Connect

    Beavis, L.C.; Karnowsky, M.M.; Yost, F.G.

    1990-12-31

    Production of soldiered joints which are highly reliable and capable of surviving 10,000 thermal cycles between about {minus}40{degrees}C and 110{degrees}C. Process involves interposing a thin layer of a metal solder composition between the metal surfaces of members to be bonded and applying heat and up to about 1000 psi compression pressure to the superposed members, in the presence of a reducing atmosphere, to extrude the major amount of the solder composition, contaminants including fluxing gases and air, from between the members being bonded, to form a very thin, strong intermetallic bonding layer having a thermal expansion tolerant with that of the bonded members.

  11. Creep deformation behavior in eutectic Sn-Ag solder joints using a novel mapping technique

    SciTech Connect

    Lucas, J.P.; Guo, F.; McDougall, J.; Bieler, T.R.; Subramanian, K.N.; Park, J.K.

    1999-11-01

    Creep deformation behavior was measured for 60--100 {micro}m thick solder joints. The solder joints investigated consisted of: (1) non-composite solder joints made with eutectic Sn-Ag solder, and (2) composite solder joints with eutectic Sn-Ag solder containing 20 vol.%, 5 {micro}m diameter in-situ Cu{sub 6}Sn{sub 5} intermetallic reinforcements. All creep testing in this study was carried out at room temperature. Qualitative and quantitative assessment of creep deformation was characterized on the solder joints. Creep deformation was analyzed using a novel mapping technique where a geometrical-regular line pattern was etched over the entire solder joint using excimer laser ablation. During creep, the laser-ablation (LA) pattern becomes distorted due to deformation in the solder joint. By imaging the distortion of laser-ablation patterns using the SEM, actual deformation mapping for the entire solder joint is revealed. The technique involves sequential optical/digital imaging of the deformation versus time history during creep. By tracing and recording the deformation of the LA patterns on the solder over intervals of time, local creep data are obtained in many locations in the joint. This analysis enables global and localized creep shear strains and strain rate to be determined.

  12. IEEE P1547 Series of Standards for Interconnection: Preprint

    SciTech Connect

    Basso, T. S.; DeBlasio, R.

    2003-05-01

    The IEEE P1547 Standard For Interconnecting Distributed Resources With Electric Power Systems is the first in the P1547 series of planned interconnection standards, and additional standards are needed. There are major issues and obstacles to an orderly transition to the use and integration of distributed power resources with electric power systems (grid or utility grid). The lack of uniform national interconnection standards and tests for interconnection operation and certification-as well as the lack of uniform national building, electrical, and safety codes-is understood, and resolving this needs reasonable lead time to develop and promulgate consensus. The P1547 standard is a benchmark milestone for the IEEE standards consensus process and successfully demonstrates a model for ongoing success in the development of further national standards and for moving forward in modernizing our nation's electric power system.

  13. Printing Stretchable Spiral Interconnects Using Reactive Ink Chemistries.

    PubMed

    Mamidanna, Avinash; Song, Zeming; Lv, Cheng; Lefky, Christopher S; Jiang, Hanqing; Hildreth, Owen J

    2016-05-25

    Stretchable electronics have important applications in health monitoring and integrated lab-on-a-chip devices. This paper discusses the performance of serpentine stretchable interconnects printed using self-reducing, silver reactive inks. It details process optimization, device fabrication, and device characterization, while demonstrating the potential applications for reactive inks and new design strategies in stretchable electronics. Devices were printed with an ethanol stabilized silver diamine reactive ink and cycled to stretch ratios of 140 and 160% over 1000 cycles with less than 2.5% variation in electrical resistance. Maximum deformation before failure was measured at 180% elongation. Additionally, interconnect deformation was compared to finite element analysis (FEA) simulations to show that FEA can be used to accurately model the deformation of low-strain printed interconnects. Overall, this paper demonstrates a simple and affordable route toward stretchable electrical interconnects. PMID:27158736

  14. Renewable Systems Interconnection: Executive Summary

    SciTech Connect

    Kroposki, B.; Margolis, R.; Kuswa, G.; Torres, J.; Bower, W.; Key, T.; Ton, D.

    2008-02-01

    The U.S. Department of Energy launched the Renewable Systems Interconnection (RSI) study in 2007 to address the challenges to high penetrations of distributed renewable energy technologies. The RSI study consists of 14 additional reports.

  15. Reconfigurable Optical Interconnections Using Dynamic Optoelectronic Holograms

    NASA Astrophysics Data System (ADS)

    Schulze, Elmar

    1988-04-01

    Increasing complexity and processing speed of electronic circuits and a high device density have led to serious problems in electrical interconnections. Their limitations arise from their signal transmission capacity. power consumption. crosstalk. and reliability. Optical links may solve such problems by offering high data rates of several gigabits per second. large fanouts of up to 100 loads. good reliability and less power expenditure. Optical fibers, integrated optical waveguides or free-space transmission links may be applicable. For the free-space links, lenses. mirrors and holograms can be used to guide the light waves. In this paper, reconfigurable optical interconnection schemes are proposed and described which are based on optoelectronic holograms. Their interference patterns can be changed dynamically. To establish connections as free-space links, the light beams emitted from even hundreds of light sources are imaged onto an array of small dynamic holograms. Their interference patterns are optically and electronically controllable. These holograms diffract and focus each of the incident light beams individually onto the receiving photo-diodes. By changing the hologram interference patterns dynamically. an optical switch is obtained. It renders the establishment of reconfigurable optical interconnections. As optoelectronic holograms very-high-resolution spatial light modulators are proposed.

  16. Studies on in situ particulate reinforced tin-silver composite solders relevant to thermomechanical fatigue issues

    NASA Astrophysics Data System (ADS)

    Choi, Sunglak

    2001-07-01

    Global pressure based on environmental and health concerns regarding the use of Pb-bearing solder has forced the electronics industry to develop Pb-free alternative solders. Eutectic Sn-Ag solder has received much attention as a potential Pb-free candidate to replace Sn-Pb solder. Since introduction of surface mount technology, packaging density increased and the electronic devices became smaller. As a result, solders in electronic modules are forced to function as a mechanical connection as well as electrical contact. Solders are also exposed to very harsh service conditions such as automotive under-the-hood and aerospace applications. Solder joints experience thermomechanical fatigue, i.e. interaction of fatigue and creep, during thermal cycling due to temperature fluctuation in service conditions. Microstructural study on thermomechanical fatigue of the actual eutectic Sn-Ag and Sn-4Ag-0.5Cu solder joints was performed to better understand deformation and damage accumulation occurring during service. Incorporation of reinforcements has been pursued to improve the mechanical and particularly thermomechanical behavior of solders, and their service temperature capability. In-situ Sn-Ag composite solders were developed by incorporating Cu 6Sn5, Ni3Sn4, and FeSn2 particulate reinforcements in the eutectic Sn-Ag solder in an effort to enhance thermomechanical fatigue resistance. In-situ composite solders were investigated on the growth of interfacial intermetallic layer between solder and Cu substrate growth and creep properties. Solder joints exhibited significant deformation and damage on free surface and interior regions during thermomechanical fatigue. Cracks initiated on the free surface of the solder joints and propagated toward interior regions near the substrate of the solder joint. Crack grew along Sn grain boundaries by grain boundary sliding. There was significant residual stress within the solder joint causing more damage. Presence of small amount of Cu

  17. Polyhedral integrated and free space optical interconnection

    DOEpatents

    Erteza, I.A.

    1998-01-06

    An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment. 7 figs.

  18. Polyhedral integrated and free space optical interconnection

    DOEpatents

    Erteza, Ireena A.

    1998-01-01

    An optical communication system uses holographic optical elements to provide guided wave and non-guided communication, resulting in high bandwidth, high connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and non-guided communication allows compact polyhedral system geometries. Guided wave communications provided by multiplexed substrate-mode holographic optical elements eases system alignment.

  19. Aqueous cleaning of flux residue from solder joints. Final report

    SciTech Connect

    Krska, C.M.

    1992-08-01

    Solder joints have traditionally been cleaned using chlorinated or fluorinated solvents. This study addressed alternate processing. One process involved using a saponifier/water solution to remove rosin flux residues; the other process involved using a water-soluble flux and water to remove the residues. Although both processes were satisfactory, the water-soluble flux with water cleaning proved to be the best.

  20. Aqueous cleaning of flux residue from solder joints

    SciTech Connect

    Krska, C.M.

    1992-08-01

    Solder joints have traditionally been cleaned using chlorinated or fluorinated solvents. This study addressed alternate processing. One process involved using a saponifier/water solution to remove rosin flux residues; the other process involved using a water-soluble flux and water to remove the residues. Although both processes were satisfactory, the water-soluble flux with water cleaning proved to be the best.

  1. Fixture aids soldering of electronic components on circuit board

    NASA Technical Reports Server (NTRS)

    Ross, M. H.

    1966-01-01

    Spring clamp fixture holds small electronic components in a desired position while they are being soldered on a circuit board. The spring clamp is clipped on the edge of the circuit board and an adjustable spring-steel boom holds components against the board. The felt pad at the end of the boom is replaced with different attachments for other holding tasks.

  2. 28. VIEW OF THE SOLDERING NICHE FORMED WITH BRICKS. THE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    28. VIEW OF THE SOLDERING NICHE FORMED WITH BRICKS. THE BACK OF THE NICHE IS CEMENT FINISHED. THE BOTTOM HAS A 1 INCH THICK ASBESTOS SHELF. THIS PHOTO WAS TAKEN AT THE 3RD FLOOR. - Pacific Telephone & Telegraph Company Building, 1519 Franklin Street, Oakland, Alameda County, CA

  3. Fundamentals of wetting and spreading with emphasis on soldering

    SciTech Connect

    Yost, F.G.

    1991-01-01

    Soldering is often referred to as a mature technology whose fundamentals were established long ago. Yet a multitude of soldering problems persist, not the least of which are related to the wetting and spreading of solder. The Buff-Goodrich approach to thermodynamics of capillarity is utilized in a review of basic wetting principles. These thermodynamics allow a very compact formulation of capillary phenomena which is used to calculate various meniscus shapes and wetting forces. These shapes and forces lend themselves to experimental techniques, such as the sessile drop and the Wilhelmy plate, for measuring useful surface and interfacial energies. The familiar equations of Young, Wilhelmy, and Neumann are all derived with this approach. The force-energy duality of surface energy is discussed and the force method is developed and used to derive the Herring relations for anisotropic surfaces. The importance of contact angle hysteresis which results from surface roughness and chemical inhomogeneity is presented and Young's equation is modified to reflect these ever present effects. Finally, an analysis of wetting with simultaneous metallurigical reaction is given and used to discuss solder wetting phenomena. 60 refs., 13 figs.

  4. Inelastic Strain Analysis of Solder Joint in NASA Fatigue Specimen

    NASA Technical Reports Server (NTRS)

    Dasgupta, Abhijit; Oyan, Chen

    1991-01-01

    The solder fatigue specimen designed by NASA-GSFC/UNISYS is analyzed in order to obtain the inelastic strain history during two different representative temperature cycles specified by UNISYS. In previous reports (dated July 25, 1990, and November 15, 1990), results were presented of the elastic-plastic and creep analysis for delta T = 31 C cycle, respectively. Subsequent results obtained during the current phase, from viscoplastic finite element analysis of the solder fatigue specimen for delta T = 113 C cycle are summarized. Some common information is repeated for self-completeness. Large-deformation continuum formulations in conjunction with a standard linear solid model is utilized for modeling the solder constitutive creep-plasticity behavior. Relevant material properties are obtained from the literature. Strain amplitudes, mean strains, and residual strains (as well as stresses) accumulated due to a representative complete temperature cycle are obtained as a result of this analysis. The partitioning between elastic strains, time-independent inelastic (plastic) strains, and time-dependent inelastic (creep) strains is also explicitly obtained for two representative cycles. Detailed plots are presented for two representative temperature cycles. This information forms an important input for fatigue damage models, when predicting the fatigue life of solder joints under thermal cycling

  5. Robot End Effector To Place and Solder Solar Cells

    NASA Technical Reports Server (NTRS)

    Hagerty, J. J.

    1982-01-01

    Encapsulated in robot end effector is RF induction-heating coil for heating solar cell while in transit. Holes in encapsulant permit end of unit to act as vacuum pickup to grip solar cell. Use of RF induction heating allows cell to be heated without requiring direct mechanical and thermal contact of bonding tool such as soldering iron.

  6. A constitutive model for Sn-Pb solder.

    SciTech Connect

    Neilsen, Michael K.; Vianco, Paul Thomas; Boyce, Brad Lee

    2010-10-01

    A unified creep plasticity damage (UCPD) model for Sn-Pb solder is developed in this paper. Stephens and Frear (1999) studied the creep behavior of near-eutectic 60Sn-40Pb solder subjected to low strain rates and found that the inelastic (creep and plastic) strain rate could be accurately described using a hyperbolic Sine function of the applied effective stress. A recently developed high-rate servo-hydraulic method was employed to characterize the temperature and strain-rate dependent stress-strain behavior of eutectic Sn-Pb solder over a wide range of strain rates (10{sup -4} to 10{sup 2} per second). The steady state inelastic strain rate data from these latest experiments were also accurately captured by the hyperbolic Sine equation developed by Stephens and Frear. Thus, this equation was used as the basis for the UCPD model for Sn-Pb solder developed in this paper. Stephens, J.J., and Frear, D.R., Metallurgical and Materials Transactions A, Volume 30A, pp. 1301-1313, May 1999.

  7. Printed-Circuit-Board Soldering Training for Group IV Personnel.

    ERIC Educational Resources Information Center

    Hooprich, E. A.; Matlock, E. W.

    As part of a larger program to determine which Navy skills can be learned by lower aptitude personnel, and which methods and techniques would be most effective, an experimental course in printed circuit board soldering was given to 186 Group IV students in 13 classes. Two different training approaches--one stressing instructor guidance and the…

  8. Horizon shells and BMS-like soldering transformations

    NASA Astrophysics Data System (ADS)

    Blau, Matthias; O'Loughlin, Martin

    2016-03-01

    We revisit the theory of null shells in general relativity, with a particular emphasis on null shells placed at horizons of black holes. We study in detail the considerable freedom that is available in the case that one solders two metrics together across null hypersurfaces (such as Killing horizons) for which the induced metric is invariant under translations along the null generators. In this case the group of soldering transformations turns out to be infinite dimensional, and these solderings create non-trivial horizon shells containing both massless matter and impulsive gravitational wave components. We also rephrase this result in the language of Carrollian symmetry groups. To illustrate this phenomenon we discuss in detail the example of shells on the horizon of the Schwarzschild black hole (with equal interior and exterior mass), uncovering a rich classical structure at the horizon and deriving an explicit expression for the general horizon shell energy-momentum tensor. In the special case of BMS-like soldering supertranslations we find a conserved shell-energy that is strikingly similar to the standard expression for asymptotic BMS supertranslation charges, suggesting a direct relation between the physical properties of these horizon shells and the recently proposed BMS supertranslation hair of a black hole.

  9. Recycling of lead solder dross, Generated from PCB manufacturing

    NASA Astrophysics Data System (ADS)

    Lucheva, Biserka; Tsonev, Tsonio; Iliev, Peter

    2011-08-01

    The main purpose of this work is to analyze lead solder dross, a waste product from manufacturing of printed circuit boards by wave soldering, and to develop an effective and environmentally sound technology for its recycling. A methodology for determination of the content and chemical composition of the metal and oxide phases of the dross is developed. Two methods for recycling of lead solder dross were examined—carbothermal reduction and recycling using boron-containing substances. The influence of various factors on the metal yield was studied and the optimal parameters of the recycling process are defined. The comparison between them under the same parameters-temperature and retention time, showed that recycling of dross with a mixture of borax and boric acid in a 1:2 ratio provides higher metal yield (93%). The recycling of this hazardous waste under developed technology gets glassy slag and solder, which after correction of the chemical composition can be used again for production of PCB.

  10. Interconnection of Europe`s power systems

    SciTech Connect

    Manos, P.

    1996-03-01

    More than six years have passed since the Berlin Wall fell during Christmas of 1989, and a unified pan-European electricity-supply system is still not a reality. Progress toward that goal has been certain but slow. Technical and political differences still block the final step in the integration process: a full hookup between the grids of western and northern Europe and the transmission networks of the former Warsaw Pact nations. It has fallen to unified Germany, as the bridge between East and West, to serve as the catalyst of Europe`s electrical congress. This paper discusses the existing and planned interconnection along with a historical perspective.

  11. Size effects in tin-based lead-free solder joints: Kinetics of bond formation and mechanical characteristics

    NASA Astrophysics Data System (ADS)

    Abdelhadi, Ousama Mohamed Omer

    Continuous miniaturization of microelectronic interconnects demands smaller joints with comparable microstructural and structural sizes. As the size of joints become smaller, the volume of intermetallics (IMCs) becomes comparable with the joint size. As a result, the kinetics of bond formation changes and the types and thicknesses of IMC phases that form within the constrained region of the bond varies. This dissertation focuses on investigating combination effects of process parameters and size on kinetics of bond formation, resulting microstructure and the mechanical properties of joints that are formed under structurally constrained conditions. An experiment is designed where several process parameters such as time of bonding, temperature, and pressure, and bond thickness as structural chracteristic, are varied at multiple levels. The experiment is then implemented on the process. Scanning electron microscope (SEM) is then utilized to determine the bond thickness, IMC phases and their thicknesses, and morphology of the bonds. Electron backscatter diffraction (EBSD) is used to determine the grain size in different regions, including the bulk solder, and different IMC phases. Physics-based analytical models have been developed for growth kinetics of IMC compounds and are verified using the experimental results. Nanoindentation is used to determine the mechanical behavior of IMC phases in joints in different scales. Four-point bending notched multilayer specimen and four-point bending technique were used to determine fracture toughness of the bonds containing IMCs. Analytical modeling of peeling and shear stresses and fracture toughness in tri-layer four-point bend specimen containing intermetallic layer was developed and was verified and validated using finite element simulation and experimental results. The experiment is used in conjunction with the model to calculate and verify the fracture toughness of Cu6Sn5 IMC materials. As expected two different IMC phases

  12. End-to-end small bowel anastomosis by temperature controlled CO2 laser soldering and an albumin stent: a feasibility study

    NASA Astrophysics Data System (ADS)

    Simhon, David; Kopelman, Doron; Hashmonai, Moshe; Vasserman, Irena; Dror, Michael; Vasilyev, Tamar; Halpern, Marissa; Kariv, Naam; Katzir, Abraham

    2004-07-01

    Introduction: A feasibility study of small intestinal end to end anastomosis was performed in a rabbit model using temperature controlled CO2 laser system and an albumin stent. Compared with standard suturing or clipping, this method does not introduce foreign materials to the repaired wound and therefore, may lead to better and faster wound healing of the anastomotic site. Methods: Transected rabbits small intestines were either laser soldered using 47% bovine serum albumin and intraluminal albumin stent or served as controls in which conventional continuous two-layer end to end anastomosis was performed manually. The integrity of the anastomosis was investigated at the 14th postoperative day. Results: Postoperative course in both treatments was uneventful. The sutured group presented signs of partial bowel obstruction. Macroscopically, no signs of intraluminal fluid leakage were observed in both treatments. Yet, laser soldered intestinal anastomoses demonstrated significant superiority with respect to adhesions and narrowing of the intestinal lumen. Serial histological examinations revealed better wound healing characteristics of the laser soldered anastomotic site. Conclusion: Laser soldering of intestinal end to end anastomosis provide a faster surgical procedure, compared to standard suture technique, with better wound healing results. It is expected that this technique may be adopted in the future for minimal invasive surgeries.

  13. Finite width coplanar waveguide patch antenna with vertical fed through interconnect

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.; Lee, Richard Q.; Shalkhauser, Kurt A.; Owens, Jonathan; Demarco, James; Leen, Joan; Sturzebecher, Dana

    1996-01-01

    The paper presents the design, fabrication and characterization of a finite width Coplanar waveguide (FCPW) patch antenna and a FCPW-to-FCPW vertical interconnect. The experimental results demonstrate the antenna and interconnect performance. A scheme to integrate an eight element FCPW patch array with MMIC phase shifters and amplifiers using vertical interconnects is described. The antenna module has potential applications in an advanced satellite to ground transmit phased array at K-Band.

  14. Electromigration Behaviors of Cu Reinforced Sn-3.5Ag Composite Solder Joints

    NASA Astrophysics Data System (ADS)

    Wang, Yan; Han, Jing; Ma, Limin; Zuo, Yong; Guo, Fu

    2016-09-01

    The composite approach, by incorporating small amounts of reinforcement particles in the solder matrix, has proven to be one of the effective ways to improve the reliability of solder joints. The effects of Cu addition on electromigration were investigated in this study by incorporating 2% volume fraction Cu particles into Sn-3.5Ag eutectic solder paste by the in situ process. The one-dimensional solder joints, designed to prevent the current crowding effect, were stressed under a constant current density of 104 A/cm2 at room temperature, and the temperature of the sample could reach 105 ± 5°C due to the Joule heating effect. Doping 2 vol.% Cu was found to retard the electromigration phenomenon effectively. After electric current stressing for 528 h, the growth rate of an interfacial intermetallic compound (IMC) layer at the anode decreased 73% in contrast to that of Sn-3.5Ag solder joints, and the IMC layer at the cathode was almost unchanged. The polarization effect of Cu reinforced composite solder joints was also apparently mitigated. In addition, the surface damage of the composite solder joints was relieved by incorporating 2 vol.% Cu particles. Compared to Sn-3.5Ag solder joints, which had protruded Cu6Sn5 and wrinkles of Sn-solder matrix on the surface, the solder joints with Cu addition had a more even surface.

  15. Scaling of Metal Interconnects: Challenges to Functionality and Reliability

    SciTech Connect

    Engelhardt, M.; Schindler, G.; Traving, M.; Stich, A.; Gabric, Z.; Pamler, W.; Hoenlein, W.

    2006-02-07

    Copper-based nano interconnects featuring CDs well beyond today's chip generations and air gap structures were fabricated and subjected to electrical characterization and tests to get already today insight on functionality and reliability aspects of metallization schemes in future semiconductor products. Size effects observed already in today's advanced products will definitely limit the resistivity in future interconnects. Copper diffusion barrier layers were scaled down to the 1nm regime of thicknesses without observable degradation effects regarding adhesion properties and functionality. Interconnect reliability was found to decrease with decreasing barrier thickness. Worst results regarding adhesion properties and interconnect reliability were obtained for vanishing barrier thickness which promotes unrestricted mass flow of copper along the interconnect line. Air gaps were developed and characterized as an alternative approach to porous ultra low-k materials. They allowed the realization of effective k-values of the insulation of 2.4, which meet requirements of chip generations far in the future, while avoiding the integration issues associated with these soft materials. First reliability results obtained with air gaps are comparable with those obtained on full structures. Whereas leakage current behavior with electrical field strength expected to be present between neighboring lines in chip generations during the next 10 years were similar for air gaps and oxide, interconnects insulated by air gaps displayed lower breakdown fields than those insulated by oxide.

  16. Isothermal test as a WLR monitor for Cu interconnects

    NASA Astrophysics Data System (ADS)

    Marathe, Amit P.; Pham, Van; Chan, Jay; Weidner, Jorg-Oliver; Heinig, Volker; Thierbach, Steffi

    2000-08-01

    The need for higher interconnect current densities has been increasing rapidly for advanced integrated circuits. Cu interconnects have emerged as viable candidates to replace Aluminium due to the lower sheet resistivity and increased electro migration lifetime of Cu. Previously, we had reported the use of the isothermal test as a WLR monitor for detecting process defects such as voids in the Aluminium interconnects. This paper further extends the application of the isothermal test methodology for detecting and characterizing process defects in Cu interconnect technology. Package electro migration test are time consuming and may be impractical in detecting process defects in a timely manner. Isothermal test, on the other hand, can be effectively used as a fast WLR process monitor. This paper reports the influence of direction of test current as well as different types of test structures, such as a single level NIST structure and a via chain structure and a via chain structure, on the isothermal test results for Cu interconnects. The isothermal test data has been shown to be helpful in evaluating the location and severity of the process defects through a proper choice of test structures. Joule heating due to high current density is found to be the major driving force for the sensitivity of isothermal test failures. A good correlation is also seen with the package electro migration data. A simple wafer level isothermal test has thus been successfully demonstrated as a reliability tool for process monitoring in Cu VLSI interconnects.

  17. Manufacturing of planar ceramic interconnects

    SciTech Connect

    Armstrong, B.L.; Coffey, G.W.; Meinhardt, K.D.; Armstrong, T.R.

    1996-12-31

    The fabrication of ceramic interconnects for solid oxide fuel cells (SOFC) and separator plates for electrochemical separation devices has been a perennial challenge facing developers. Electrochemical vapor deposition (EVD), plasma spraying, pressing, tape casting and tape calendering are processes that are typically utilized to fabricate separator plates or interconnects for the various SOFC designs and electrochemical separation devices. For sake of brevity and the selection of a planar fuel cell or gas separation device design, pressing will be the only fabrication technique discussed here. This paper reports on the effect of the characteristics of two doped lanthanum manganite powders used in the initial studies as a planar porous separator for a fuel cell cathode and as a dense interconnect for an oxygen generator.

  18. Aspects of short-range interconnect packaging

    NASA Astrophysics Data System (ADS)

    Wohlfeld, Denis; Brenner, Karl-Heinz

    2012-01-01

    In short-range interconnect applications, one question arises frequently: When should optical solutions be chosen over electrical wiring? The answer to this question of course depends on several factors like costs, performance, reliability, availability of testing equipment and knowledge about optical technologies, and last but not least, it strongly depends on the application itself. Networking in high performance computing (HPC) is one such example. With bit rates around 10 Gbit/s per channel and cable length above 2 m, the high attenuation of electrical cables leads to a clear preference of optical or active optical cables (AOC) for most planned HPC systems. For AOCs, the electro-optical conversion is realized inside the connector housing, while for purely optical cables, the conversion is done at the edge of the board. Proceeding to 25 Gbit/s and higher, attenuation and loss of signal quality become critical. Therefore, either significantly more effort has to be spent on the electrical side, or the package for conversion has to be integrated closer to the chip, thus requiring new packaging technologies. The paper provides a state of the art overview of packaging concepts for short range interconnects, it describes the main challenges of optical package integration and illustrates new concepts and trends in this research area.

  19. Sticky interconnect for solution-processed tandem solar cells.

    PubMed

    Tung, Vincent C; Kim, Jaemyung; Cote, Laura J; Huang, Jiaxing

    2011-06-22

    Graphene oxide (GO) can be viewed as a two-dimensional, random diblock copolymer with distributed nanosize graphitic patches and highly oxidized domains, thus capable of guiding the assembly of other materials through both π-π stacking and hydrogen bonding. Upon mixing GO and conducting polymer poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) in water, a dispersion with dramatically increased viscosity is obtained, which turns into sticky thin films upon casting. Surprisingly, the insulating GO makes PEDOT much more conductive by altering its chain conformation and morphology. The GO/PEDOT gel can function as a metal-free solder for creating mechanical and electrical connections in organic optoelectronic devices. As a proof-of-concept, polymer tandem solar cells have been fabricated by a direct adhesive lamination process enabled by the sticky GO/PEDOT film. The sticky interconnect can greatly simplify the fabrication of organic tandem architectures, which has been quite challenging via solution processing. Thus, it could facilitate the construction of high-efficiency tandem solar cells with different combinations of solution-processable materials. PMID:21615169

  20. Corrosive microenvironments at lead solder surfaces arising from galvanic corrosion with copper pipe.

    PubMed

    Nguyen, Caroline K; Stone, Kendall R; Dudi, Abhijeet; Edwards, Marc A

    2010-09-15

    As stagnant water contacts copper pipe and lead solder (simulated soldered joints), a corrosion cell is formed between the metals in solder (Pb, Sn) and the copper. If the resulting galvanic current exceeds about 2 μA/cm(2), a highly corrosive microenvironment can form at the solder surface, with pH < 2.5 and chloride concentrations at least 11 times higher than bulk water levels. Waters with relatively high chloride tend to sustain high galvanic currents, preventing passivation of the solder surface, and contributing to lead contamination of potable water supplies. The total mass of lead corroded was consistent with predictions based on the galvanic current, and lead leaching to water was correlated with galvanic current. If the concentration of sulfate in the water increased relative to chloride, galvanic currents and associated lead contamination could be greatly reduced, and solder surfaces were readily passivated.

  1. Threshold current density of electromigration in eutectic SnPb solder

    SciTech Connect

    Yeh, Y.T.; Chou, C.K.; Hsu, Y.C.; Chen Chih; Tu, K.N.

    2005-05-16

    Electromigration has emerged as an important reliability issue in the microelectronics packaging industry since the dimension of solder joints has continued to shrink. In this letter, we report a technique that enables the precise measurement of the important parameters of solder electromigration, such as activation energy, critical length, threshold current density, effective charge numbers, and electromigration rate. Patterned Cu/Ti films in a Si trench were employed for eutectic SnPb solder to be reflowed on, and thus solder Blech specimens were fabricated. Atomic force microscope was used to measure the depletion volume caused by electromigration on the cathode end. The threshold current density is estimated to be 8.5x10{sup 3} A/cm{sup 2} at 100 deg. C, which relates directly to the maximum allowable current that a solder joint can carry without electromigration damage. This technique facilitates the scientifically systematic investigation of electromigration in solders.

  2. Improvement of High-Temperature Performance of Zn-Sn Solder Joint

    NASA Astrophysics Data System (ADS)

    Takahashi, Toshihide; Komatsu, Shuichi; Nishikawa, Hiroshi; Takemoto, Tadashi

    2010-08-01

    Pb-based solders are used as high-temperature solders in power semiconductor devices. Although the use of Pb is globally restricted, alternative materials cannot replace the Pb-based solder. This study proposes that the Pb-based solder can be replaced by Zn-Sn alloys. Die shear tests revealed that some Zn-Sn solder joints between Cu substrates had a higher shear strength between 300 K and 543 K than those between Fe-42Ni substrates. The microstructure of the Zn-Sn solder joints between Cu substrates showed network microstructures consisting of a Zn phase and ɛ-CuZn5 phase and direct connection between the network microstructures and intermetallic compound layer. These morphologies of the high melting phase should improve the shear strength even at the elevated temperature of 543 K.

  3. Technology, science, and environtmental impact of a novel Cu-Ag core-shell solderless interconnect system

    NASA Astrophysics Data System (ADS)

    Kammer, Milea Joy

    Tin-based solder is ubiquitous in microelectronics manufacturing and plays a critical role in electronic packaging and attachment. While manufacturers of consumer electronics have made the transition to the use of lead-free solder, there are still a variety of reliability issues associated with these lead-free alternatives, particularly for high performance, high reliability applications. Because of these performance short-comings, researchers are still searching for a material, an alloy, or a unique alternative that can meet the thermal, mechanical, and electrical requirements for conventional reflow solder applications. In an effort to produce a more reliable alternative, Kim et al. proposed the low-temperature (200°C) sintering of copper-silver core-shell particles as a viable solderless interconnect technology. This technology is based on the silver atoms from the shell diffusing by surface diffusion to form sintered necks between copper particles, and therefore dewetting most of the copper surfaces. This study presents a 3-fold, in-depth evaluation of this Cu-Ag core-shell lead-free solderless interconnect technology focusing on solder paste development and prototyping, silver thin film stress relaxation and dewetting kinetics, and the environmental impacts associated with this new technology. First, an evaluation of the starting particle consistency and sintered compact mechanical properties determined that a specific core-shell particle geometry (1microm average core diameter and 10nm shell thickness) outperformed other combinations, exhibiting the highest modulus and yield strengths in sintered compacts, of 620 MPa and 40-60 MPa respectively. In particular, yield strengths for sintered compacts are similar to those reported for Sn-3.5Ag-0.75Cu (a commonly used lead-free solder) for the same strain rate. Following particle evaluations, the development of a functioning flux formulation was a key factor in the creation of a viable drop-in replacement. The

  4. Interfacial reaction of Sn-based solder joint in the package system

    NASA Astrophysics Data System (ADS)

    Gu, Huandi

    In this thesis, I report a study on the effect of the solder size on intermetallic layer formation by comparing the morphology change and growth rate of two different size solder joint aged at a same temperature for different aging time. The layer thickness and microstructure were analyzed using scanning electron microscopy (SEM). Photoshop was used to measure the thickness of intermetallic compound. Two different size of solder joints with composition of Sn-Ag-Cu (305) were used.

  5. 3D FEM Simulations of Drop Test Reliability on 3D-WLP: Effects of Solder Reflow Residual Stress and Molding Resin Parameters

    NASA Astrophysics Data System (ADS)

    Belhenini, Soufyane; Tougui, Abdellah; Bouchou, Abdelhake; Mohan, Ranganathan; Dosseul, Franck

    2014-01-01

    Numerous three-dimensional (3D) packaging technologies are currently used for 3D integration. 3D-wafer level package (3D-WLP) appears to be a way to keep increasing the density of the microelectronic components. The reliability of 3D components has to be evaluated on mechanical demonstrators with daisy chains before real production. Numerical modeling is acknowledged as a very efficient tool for design optimization. In this paper, 3D finite-elements calculations are carried out to analyze the effects of molding resin's mechanical properties and thickness on the 3D component's dynamic response under drop loading conditions. Residual stress generated by solder reflow is also discussed. The influences of residual stresses on the numerical estimation of the component behavior during drop loading are studied. Solder reflow residual stresses have an impact on solder plastic strain and die equivalent stress calculations. We have compared the result of two numerical drop test models. Stress-free initial conduction is introduced for the first model. Solder reflow residual stresses are considered as the initial condition for the second drop test model. Quantitative and qualitative comparisons are carried out to show the effect of residual stress in drop test calculations. For the effect of molding resin thickness on the component behavior under drop loading, the stress-free initial condition is considered. The effect of the molding resin's thickness on critical area location is discussed. The solder bump maximum plastic shear strain and the silicon die maximum equivalent stress are used as reliability criteria. Numerical submodeling techniques are used to increase calculation accuracy. Numerical results have contributed to the design optimization of the 3D-WLP component.

  6. Optical interconnections and networks; Proceedings of the Meeting, The Hague, Netherlands, Mar. 14, 15, 1990

    NASA Technical Reports Server (NTRS)

    Bartelt, Hartmut (Editor)

    1990-01-01

    The conference presents papers on interconnections, clock distribution, neural networks, and components and materials. Particular attention is given to a comparison of optical and electrical data interconnections at the board and backplane levels, a wafer-level optical interconnection network layout, an analysis and simulation of photonic switch networks, and the integration of picosecond GaAs photoconductive devices with silicon circuits for optical clocking and interconnects. Consideration is also given to the optical implementation of neural networks, invariance in an optoelectronic implementation of neural networks, and the recording of reversible patterns in polymer lightguides.

  7. Optical interconnection techniques for Hypercube

    NASA Technical Reports Server (NTRS)

    Johnston, A. R.; Bergman, L. A.; Wu, W. H.

    1988-01-01

    Direct free-space optical interconnection techniques are described for the Hypercube concurrent processor machine using a holographic optical element. Computational requirements and optical constraints on implementation are briefly summarized with regard to topology, power consumption, and available technologies. A hybrid lens/HOE approach is described that can support an eight-dimensional cube of 256 nodes.

  8. Effects of simulated storage on the solder wettability of inhibited substrates

    SciTech Connect

    Hosking, F.M.; Sorensen, N.R.

    1992-01-01

    Solder wettability of Class II environmentally exposed Cu substrates coated with an organic solderability preservative (OSP) is being investigated. The OSP coatings slightly retarded the wetting behavior of 60Sn-40Pb solder during baseline testing of unaged coupons. A nominal increase in wetting angle, or decrease in wettability, was observed on the inhibited surfaces, particularly when less active fluxes were used. Small increases in the wetting time and decreases in the wetting rate were also measured. Simulated accelerated aging tests are underway to determine the effects of aging in a typical indoor industrial environment on the solder wettability of OSP coated Cu.

  9. Effects of simulated storage on the solder wettability of inhibited substrates

    SciTech Connect

    Hosking, F.M.; Sorensen, N.R.

    1992-12-01

    Solder wettability of Class II environmentally exposed Cu substrates coated with an organic solderability preservative (OSP) is being investigated. The OSP coatings slightly retarded the wetting behavior of 60Sn-40Pb solder during baseline testing of unaged coupons. A nominal increase in wetting angle, or decrease in wettability, was observed on the inhibited surfaces, particularly when less active fluxes were used. Small increases in the wetting time and decreases in the wetting rate were also measured. Simulated accelerated aging tests are underway to determine the effects of aging in a typical indoor industrial environment on the solder wettability of OSP coated Cu.

  10. High-power semiconductor laser array packaged on microchannel cooler using gold-tin soldering technology

    NASA Astrophysics Data System (ADS)

    Wang, Jingwei; Kang, Lijun; Zhang, Pu; Nie, Zhiqiang; Li, Xiaoning; Xiong, Lingling; Liu, Xingsheng

    2012-03-01

    High power semiconductor laser arrays have found increased applications in many fields. In this work, a hard soldering microchannel cooler (HSMCC) technology was developed for packaging high power diode laser array. Numerical simulations of the thermal behavior characteristics of hard solder and indium solder MCC-packaged diode lasers were conducted and analyzed. Based on the simulated results, a series of high power HSMCC packaged diode laser arrays were fabricated and characterized. The test and statistical results indicated that under the same output power the HSMCC packaged laser bar has lower smile and high reliability in comparison with the conventional copper MCC packaged laser bar using indium soldering technology.

  11. Automated inspection of solder joints for surface mount technology

    NASA Technical Reports Server (NTRS)

    Savage, Robert M.; Park, Hyun Soo; Fan, Mark S.

    1993-01-01

    Researchers at NASA/GSFC evaluated various automated inspection systems (AIS) technologies using test boards with known defects in surface mount solder joints. These boards were complex and included almost every type of surface mount device typical of critical assemblies used for space flight applications: X-ray radiography; X-ray laminography; Ultrasonic Imaging; Optical Imaging; Laser Imaging; and Infrared Inspection. Vendors, representative of the different technologies, inspected the test boards with their particular machine. The results of the evaluation showed limitations of AIS. Furthermore, none of the AIS technologies evaluated proved to meet all of the inspection criteria for use in high-reliability applications. It was found that certain inspection systems could supplement but not replace manual inspection for low-volume, high-reliability, surface mount solder joints.

  12. Laser tissue welding mediated with a protein solder

    SciTech Connect

    Small, W. IV; Heredia, N.J.; Celliers, P.M.

    1996-02-01

    A study of laser tissue welding mediated with an indocyanine green dye-enhanced protein solder was performed. Freshly obtained sections of porcine artery were used for the experiments. Sample arterial wall thickness ranged from two to three millimeters. Incisions approximately four millimeters in length were treated using an 805 nanometer continuous-wave diode laser coupled to a one millimeter diameter fiber. Controlled parameters included the power delivered by the laser, the duration of the welding process, and the concentration of dye in the solder. A two-color infrared detection system was constructed to monitor the surface temperatures achieved at the weld site. Burst pressure measurements were made to quantify the strengths of the welds immediately following completion of the welding procedure.

  13. Solderable and electroplatable flexible electronic circuit on a porous stretchable elastomer

    NASA Astrophysics Data System (ADS)

    Jeong, Gi Seok; Baek, Dong-Hyun; Jung, Ha Chul; Song, Ji Hoon; Moon, Jin Hee; Hong, Suck Won; Kim, In Young; Lee, Sang-Hoon

    2012-07-01

    A variety of flexible and stretchable electronics have been reported for use in flexible electronic devices or biomedical applications. The practical and wider application of such flexible electronics has been limited because commercial electronic components are difficult to be directly integrated into flexible stretchable electronics and electroplating is still challenging. Here, we propose a novel method for fabricating flexible and stretchable electronic devices using a porous elastomeric substrate. Pressurized steam was applied to an uncured polydimethylsiloxane layer for the simple and cost-effective production of porous structure. An electroplated nickel anchor had a key role in bonding commercial electronic components on elastomers by soldering techniques, and metals could be stably patterned and electroplated for practical uses. The proposed technology was applied to develop a plaster electrocardiogram dry electrode and multi-channel microelectrodes that could be used as a long-term wearable biosignal monitor and for brain signal monitoring, respectively.

  14. Solderable and electroplatable flexible electronic circuit on a porous stretchable elastomer.

    PubMed

    Jeong, Gi Seok; Baek, Dong-Hyun; Jung, Ha Chul; Song, Ji Hoon; Moon, Jin Hee; Hong, Suck Won; Kim, In Young; Lee, Sang-Hoon

    2012-01-01

    A variety of flexible and stretchable electronics have been reported for use in flexible electronic devices or biomedical applications. The practical and wider application of such flexible electronics has been limited because commercial electronic components are difficult to be directly integrated into flexible stretchable electronics and electroplating is still challenging. Here, we propose a novel method for fabricating flexible and stretchable electronic devices using a porous elastomeric substrate. Pressurized steam was applied to an uncured polydimethylsiloxane layer for the simple and cost-effective production of porous structure. An electroplated nickel anchor had a key role in bonding commercial electronic components on elastomers by soldering techniques, and metals could be stably patterned and electroplated for practical uses. The proposed technology was applied to develop a plaster electrocardiogram dry electrode and multi-channel microelectrodes that could be used as a long-term wearable biosignal monitor and for brain signal monitoring, respectively.

  15. Predicted ball grid array thermal response during reflow soldering

    SciTech Connect

    Voth, T.E.; Bergman, T.L.

    1995-12-31

    A numerical model is developed to predict the detailed thermomechanical response of a BGA assembly during reflow soldering. The governing coupled solid mechanics and heat diffusion equations are solved using a commercially available finite element package. Reported predictions illustrate the system`s sensitivity to both thermal and mechanical processing conditions, as well as component thermal properties. Specifically, assemblies with components of high thermal conductivity show the greatest sensitivity to mechanical loading conditions.

  16. Impact of lead and other metallic solders on water quality

    SciTech Connect

    Murrell, N.E.

    1990-02-01

    A study of the relationship between water quality at the consumer's taps and the corrosion of lead solder was conducted under actual field conditions in 90 homes supplied by public water in the South Huntington Water District (New York) and at 14 houses supplied by private wells in Suffolk County on Long Island (New York). The study was done in three phases three different pH ranges (5.0-6.8, 7.0-7.4, and 8.0 and greater). The phase I study was preformed without any pH adjustments on the water sources. Phase II and III studies consisted of raising the pH by the addition of caustic soda and maintaining pH for thirty days prior to the sampling. After an overnight period of nonuse, a series of samples were collected at specific time intervals to evaluate the effect of time on the leaching rate of lead. Data were collected on leaching of cadmium and copper and water quality parameters were monitored. In the 2nd part of the investigation, a more controlled, four-pipe loop study was conducted with the same corrosive Long Island water. Each pipe loop consisted of approximately 60 feet of copper pipe with 22 solder joints, each loop having a different type of solder: (1) tin/lead; (2) tin/antimony; (3) silver/copper, and (4) tin/copper. The four loop solder test results indicate the tin/antimony, silver/copper, and tin/copper can be used with only minor metal leaching.

  17. Solder joint fatigue analysis under low temperature Martian conditions

    NASA Technical Reports Server (NTRS)

    Tudryn, Carissa

    2006-01-01

    Electronics, without requiring heater power or enclosure in a centralized 'warm electronics box,' will need to survive mean surface temperatures of -120 degrees Celsius to +20 degrees Celsius for an extended Martian mission and an operational temperature up to 85 degrees Celsisus. Since these electronics will need to survive extended cycles under these conditions, fatigue is a significant concern. The solder joint reliability of connectors on a printed wiring board was investigated.

  18. Low-temperature sintering of nanoscale silver paste for semiconductor device interconnection

    NASA Astrophysics Data System (ADS)

    Bai, Guofeng

    This research has developed a lead-free semiconductor device interconnect technology by studying the processing-microstructure-property relationships of low-temperature sintering of nanoscale silver pastes. The nanoscale silver pastes have been formulated by adding organic components (dispersant, binder and thinner) into nano-silver particles. The selected organic components have the nano-particle polymeric stabilization, paste processing quality adjustment, and non-densifying diffusion retarding functions and thus help the pastes sinter to ˜80% bulk density at temperatures no more than 300°C. It has been found that the low-temperature sintered silver has better electrical, thermal and overall thermomechanical properties compared with the existing semiconductor device interconnecting materials such as solder alloys and conductive epoxies. After solving the organic burnout problems associated with the covered sintering, a lead-free semiconductor device interconnect technology has been designed to be compatible with the existing surface-mounting techniques with potentially low-cost. It has been found that the low-temperature sintered silver joints have high electrical, thermal, and mechanical performance. The reliability of the silver joints has also been studied by the 50-250°C thermal cycling experiment. Finally, the bonging strength drop of the silver joints has been suggested to be ductile fracture in the silver joints as micro-voids nucleated at microscale grain boundaries during the temperature cycling. The low-temperature silver sintering technology has enabled some benchmark packaging concepts and substantial advantages in future applications.

  19. Morphology and Shear Strength of Lead-Free Solder Joints with Sn3.0Ag0.5Cu Solder Paste Reinforced with Ceramic Nanoparticles

    NASA Astrophysics Data System (ADS)

    Yakymovych, A.; Plevachuk, Yu.; Švec, P.; Švec, P.; Janičkovič, D.; Šebo, P.; Beronská, N.; Roshanghias, A.; Ipser, H.

    2016-08-01

    To date, additions of different oxide nanoparticles is one of the most widespread procedures to improve the mechanical properties of metals and metal alloys. This research deals with the effect of minor ceramic nanoparticle additions (SiO2, TiO2 and ZrO2) on the microstructure and mechanical properties of Cu/solder/Cu joints. The reinforced Sn3.0Ag0.5Cu (SAC305) solder alloy with 0.5 wt.% and 1.0 wt.% of ceramic nanoparticles was prepared through mechanically stirring. The microstructure of as-solidified Cu/solder/Cu joints was studied using scanning electron microscopy. The additions of ceramic nanoparticles suppressed the growth of the intermetallic compound layer Cu6Sn5 at the interface solder/Cu and improved the microstructure of the joints. Furthermore, measurements of mechanical properties showed improved shear strength of Cu/composite solder/Cu joints compared to joints with unreinforced solder. This fact related to all investigated ceramic nanoinclusions and should be attributed to the adsorption of nanoparticles on the grain surface during solidification. However, this effect is less pronounced on increasing the nanoinclusion content from 0.5 wt.% to 1.0 wt.% due to agglomeration of nanoparticles. Moreover, a comparison analysis showed that the most beneficial influence was obtained by minor additions of SiO2 nanoparticles into the SAC305 solder alloy.

  20. Microstructural Evolution and Mechanical Properties in (AuSn)eut-Cu Interconnections

    NASA Astrophysics Data System (ADS)

    Dong, Hongqun; Vuorinen, Vesa; Laurila, Tomi; Paulasto-Kröckel, Mervi

    2016-06-01

    The interfacial reactions between the widely employed solder Au-20wt.%Sn and the common contact metallizations (e.g. Ni, Cu and Pt) are normally complex and not well determined. In order to identify the proper contactor for Au-20wt.%Sn solder, the present study focuses on (1) rationalizing the interfacial reaction mechanisms of Au-20wt.%Sn|Cu as well as (2) measuring the mechanical properties of individual intermetallics formed at the interface. The evolution of interfacial reaction products were rationalized by using the experimental results in combination with the calculated Au-Cu-Sn phase diagram information. It was found that the growth of the AuCu interfacial intermetallic layer was diffusion-controlled. The diffusion path of Au-20wt.%Sn|Cu at 150°C was proposed. The hardness and indentation modulus of the interfacial reaction products were measured using nanoindentation tests. The results revealed a significant influence of the Cu solubility on the mechanical properties of (Au,Cu)Sn and (Au,Cu)5Sn, i.e. their hardness and contact modulus increased with the increase in the amount of Cu. Furthermore, results obtained here for the Au-20wt.%Sn|Cu joints were compared to those from Au-20wt.%Sn|Ni in order to assess the similarities and differences between these widely used interconnection metallization systems.

  1. Microstructural Evolution and Mechanical Properties in (AuSn)eut-Cu Interconnections

    NASA Astrophysics Data System (ADS)

    Dong, Hongqun; Vuorinen, Vesa; Laurila, Tomi; Paulasto-Kröckel, Mervi

    2016-10-01

    The interfacial reactions between the widely employed solder Au-20wt.%Sn and the common contact metallizations (e.g. Ni, Cu and Pt) are normally complex and not well determined. In order to identify the proper contactor for Au-20wt.%Sn solder, the present study focuses on (1) rationalizing the interfacial reaction mechanisms of Au-20wt.%Sn|Cu as well as (2) measuring the mechanical properties of individual intermetallics formed at the interface. The evolution of interfacial reaction products were rationalized by using the experimental results in combination with the calculated Au-Cu-Sn phase diagram information. It was found that the growth of the AuCu interfacial intermetallic layer was diffusion-controlled. The diffusion path of Au-20wt.%Sn|Cu at 150°C was proposed. The hardness and indentation modulus of the interfacial reaction products were measured using nanoindentation tests. The results revealed a significant influence of the Cu solubility on the mechanical properties of (Au,Cu)Sn and (Au,Cu)5Sn, i.e. their hardness and contact modulus increased with the increase in the amount of Cu. Furthermore, results obtained here for the Au-20wt.%Sn|Cu joints were compared to those from Au-20wt.%Sn|Ni in order to assess the similarities and differences between these widely used interconnection metallization systems.

  2. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  3. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  4. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  5. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  6. 47 CFR 64.1401 - Expanded interconnection.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... such equipment to connect interconnectors' fiber optic systems or microwave radio transmission... interconnectors' fiber optic systems or microwave radio transmission facilities (where reasonably feasible) with... interconnection of fiber optic facilities, local exchange carriers shall provide: (1) An interconnection point...

  7. National Offshore Wind Energy Grid Interconnection Study

    SciTech Connect

    Daniel, John P.; Liu, Shu; Ibanez, Eduardo; Pennock, Ken; Reed, Greg; Hanes, Spencer

    2014-07-30

    The National Offshore Wind Energy Grid Interconnection Study (NOWEGIS) considers the availability and potential impacts of interconnecting large amounts of offshore wind energy into the transmission system of the lower 48 contiguous United States. A total of 54GW of offshore wind was assumed to be the target for the analyses conducted. A variety of issues are considered including: the anticipated staging of offshore wind; the offshore wind resource availability; offshore wind energy power production profiles; offshore wind variability; present and potential technologies for collection and delivery of offshore wind energy to the onshore grid; potential impacts to existing utility systems most likely to receive large amounts of offshore wind; and regulatory influences on offshore wind development. The technologies considered the reliability of various high-voltage ac (HVAC) and high-voltage dc (HVDC) technology options and configurations. The utility system impacts of GW-scale integration of offshore wind are considered from an operational steady-state perspective and from a regional and national production cost perspective.

  8. Formation of interconnections to microfluidic devices

    DOEpatents

    Matzke, Carolyn M.; Ashby, Carol I. H.; Griego, Leonardo

    2003-07-29

    A method is disclosed to form external interconnections to a microfluidic device for coupling of a fluid or light or both into a microchannel of the device. This method can be used to form optical or fluidic interconnections to microchannels previously formed on a substrate, or to form both the interconnections and microchannels during the same process steps. The optical and fluidic interconnections are formed parallel to the plane of the substrate, and are fluid tight.

  9. High temperature superconductors for computer interconnect applications

    SciTech Connect

    Nilsson, B.J.L.

    1994-12-31

    High temperature superconductors, because of their extremely low loss at high frequencies and their high current handling capability, have the potential for use in computer interconnect boards. They offer the potential advantages of high interconnect density, reduced interconnect delays, and higher data rate. Because silicon CMOS circuits dramatically improve in performance at low temperatures, cooled computers may become attractive in the future to capture both the improved interconnect and circuit benefits.

  10. Polyguide polymeric technology for optical interconnect circuits and components

    NASA Astrophysics Data System (ADS)

    Booth, Bruce L.; Marchegiano, Joseph E.; Chang, Catherine T.; Furmanak, Robert J.; Graham, Douglas M.; Wagner, Richard G.

    1997-04-01

    The expanding information revolution has been made possible by the development of optical communication technology. To meet the escalating demand for information transmitted and processed at high data rates and the need to circumvent the growing electronic circuit bottlenecks, mass deployment of not only optical fiber networks but manufacturable optical interconnect circuits, components and connectors for interfacing fibers and electronics that meet economic and performance constraints are absolutely necessary. Polymeric waveguide optical interconnection are considered increasingly important to meet these market needs. DuPont's polyguide polymeric integrated optic channel waveguide system is thought by many to have considerable potential for a broad range of passive optical interconnect applications. In this paper the recent advances, status, and unique attributes of the technology are reviewed. Product and technology developments currently in progress including parallel optical ink organization and polymer optical interconnect technology developments funded by DARPA are used as examples to describe polyguide breadth and potential for manufacture and deployment of optical interconnection products for single and multimode telecom and datacom waveguide applications.

  11. 47 CFR 69.124 - Interconnection charge.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 47 Telecommunication 3 2010-10-01 2010-10-01 false Interconnection charge. 69.124 Section 69.124... Computation of Charges § 69.124 Interconnection charge. (a) Until December 31, 2001, local exchange carriers not subject to price cap regulation shall assess an interconnection charge expressed in dollars...

  12. 47 CFR 51.305 - Interconnection.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 47 Telecommunication 3 2010-10-01 2010-10-01 false Interconnection. 51.305 Section 51.305 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) COMMON CARRIER SERVICES (CONTINUED) INTERCONNECTION Additional Obligations of Incumbent Local Exchange Carriers § 51.305 Interconnection. (a) An incumbent...

  13. The performance of multicomputer interconnection networks

    NASA Technical Reports Server (NTRS)

    Reed, Daniel A.; Grunwald, Dirk C.

    1987-01-01

    The interdependency of nodes and multicomputer interconnection networks is examined using simple calculations based on the asymptotic properties of queueing networks. Methods are described for choosing interconnection networks that fit individual classes of applications. It is also shown how analytic models can be extended to benchmark existing interconnection networks.

  14. 14 CFR 23.701 - Flap interconnection.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Flap interconnection. 23.701 Section 23.701... Systems § 23.701 Flap interconnection. (a) The main wing flaps and related movable surfaces as a system must— (1) Be synchronized by a mechanical interconnection between the movable flap surfaces that...

  15. 18 CFR 292.306 - Interconnection costs.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 18 Conservation of Power and Water Resources 1 2010-04-01 2010-04-01 false Interconnection costs... § 292.306 Interconnection costs. (a) Obligation to pay. Each qualifying facility shall be obligated to pay any interconnection costs which the State regulatory authority (with respect to any...

  16. Heat Pipe Integrated Microsystems

    SciTech Connect

    Gass, K.; Robertson, P.J.; Shul, R.; Tigges, C.

    1999-03-30

    The trend in commercial electronics packaging to deliver ever smaller component packaging has enabled the development of new highly integrated modules meeting the demands of the next generation nano satellites. At under ten kilograms, these nano satellites will require both a greater density electronics and a melding of satellite structure and function. Better techniques must be developed to remove the subsequent heat generated by the active components required to-meet future computing requirements. Integration of commercially available electronics must be achieved without the increased costs normally associated with current generation multi chip modules. In this paper we present a method of component integration that uses silicon heat pipe technology and advanced flexible laminate circuit board technology to achieve thermal control and satellite structure. The' electronics/heat pipe stack then becomes an integral component of the spacecraft structure. Thermal management on satellites has always been a problem. The shrinking size of electronics and voltage requirements and the accompanying reduction in power dissipation has helped the situation somewhat. Nevertheless, the demands for increased onboard processing power have resulted in an ever increasing power density within the satellite body. With the introduction of nano satellites, small satellites under ten kilograms and under 1000 cubic inches, the area available on which to place hot components for proper heat dissipation has dwindled dramatically. The resulting satellite has become nearly a solid mass of electronics with nowhere to dissipate heat to space. The silicon heat pipe is attached to an aluminum frame using a thermally conductive epoxy or solder preform. The frame serves three purposes. First, the aluminum frame provides a heat conduction path from the edge of the heat pipe to radiators on the surface of the satellite. Secondly, it serves as an attachment point for extended structures attached to

  17. Analysis of a short beam with application to solder joints: could larger stand-off heights relieve stress?

    NASA Astrophysics Data System (ADS)

    Suhir, Ephraim

    2015-08-01

    Physically meaningful and easy-to-use analytical (mathematical) stress model is developed for a short beam with clamped and known-in-advance offset ends. The analysis is limited to elastic deformations. While the classical Timoshenko short-beam theory seeks the beam's deflection caused by the combined bending and shear deformations for the given loading, an inverse problem is considered here: the lateral force is sought for the given ends offset. In short beams this force is larger than in long beams, since, in order to achieve the given displacement (offset), the applied force has to overcome both bending and shear resistance of the beam. It is envisioned that short beams could adequately mimic the state of stress in solder joint interconnections, including ball-grid-array (BGA) systems, with large, compared to conventional joints, stand-off heights. When the package/printed-circuit-board (PCB) assembly is subjected to the change in temperature, the thermal expansion (contraction) mismatch of the package and the PCB results in an easily predictable relative displacement (offset) of the ends of the solder joint. This offset can be determined from the known external thermal mismatch strain (determined as the product of the difference in the coefficients of thermal expansion and the change in temperature) and the position of the joint with respect to the mid-cross-section of the assembly. The maximum normal and shearing stresses could be viewed as suitable criteria of the beam's (joint's) material long-term reliability. It is shown that these stresses can be brought down by employing beam-like joints, i.e., joints with an increased stand-off height compared to conventional joints. It is imperative, of course, that, if such joints are employed, there is still enough interfacial real estate, so that the BGA bonding strength is not compromised. On the other hand, owing to the lower stress level, reliability assurance might be much less of a challenge than in the case of

  18. Flexible interconnects for fuel cell stacks

    DOEpatents

    Lenz, David J.; Chung, Brandon W.; Pham, Ai Quoc

    2004-11-09

    An interconnect that facilitates electrical connection and mechanical support with minimal mechanical stress for fuel cell stacks. The interconnects are flexible and provide mechanically robust fuel cell stacks with higher stack performance at lower cost. The flexible interconnects replace the prior rigid rib interconnects with flexible "fingers" or contact pads which will accommodate the imperfect flatness of the ceramic fuel cells. Also, the mechanical stress of stacked fuel cells will be smaller due to the flexibility of the fingers. The interconnects can be one-sided or double-sided.

  19. Microfabricated structures with electrical isolation and interconnections

    NASA Technical Reports Server (NTRS)

    Clark, William A. (Inventor); Juneau, Thor N. (Inventor); Roessig, Allen W. (Inventor); Lemkin, Mark A. (Inventor)

    2001-01-01

    The invention is directed to a microfabricated device. The device includes a substrate that is etched to define mechanical structures at least some of which are anchored laterally to the remainder of the substrate. Electrical isolation at points where mechanical structures are attached to the substrate is provided by filled isolation trenches. Filled trenches may also be used to electrically isolate structure elements from each other at points where mechanical attachment of structure elements is desired. The performance of microelectromechanical devices is improved by 1) having a high-aspect-ratio between vertical and lateral dimensions of the mechanical elements, 2) integrating electronics on the same substrate as the mechanical elements, 3) good electrical isolation among mechanical elements and circuits except where electrical interconnection is desired.

  20. Three-Layer Zn/Al/Zn Clad Solder for Die Attachment

    NASA Astrophysics Data System (ADS)

    Yamaguchi, T.; Ikeda, O.; Oda, Y.; Hata, S.; Kuroki, K.; Kuroda, H.; Hirose, A.

    2015-02-01

    Three-layer Zn/Al/Zn clad solders have been developed for high-temperature die attachment. The clad structure is used to improve the wettability and bondability of Zn-Al eutectic solder by preventing oxidation of the Al. The materials were produced by clad-rolling Zn and Al strips. TEM observations revealed that the Zn/Al clad interface was metallurgically bonded and that the Al oxide was almost entirely removed. The melting behavior of Zn/Al/Zn clad solder was examined. Eutectic melting began at the Zn/Al clad interface at 382°C, and all of the material melted within approximately 10 s. Unlike conventional Zn-Al solders, Zn/Al/Zn clad solders were successfully bonded without flux. The shear strength of a Zn/Al/Zn clad solder joint was three times that of a Pb-based solder joint. The bondability of Zn/Al/Zn clad solder was superior because the Al oxide films, which prevent bonding between chip and substrate, were fragmented by clad-rolling, and the outer Zn layers prevented Al oxidation during the bonding process.

  1. Generation of Tin(II) Oxide Crystals on Lead-Free Solder Joints in Deionized Water

    NASA Astrophysics Data System (ADS)

    Chang, Hong; Chen, Hongtao; Li, Mingyu; Wang, Ling; Fu, Yonggao

    2009-10-01

    The effect of the anode and cathode on the electrochemical corrosion behavior of lead-free Sn-Ag-Cu and Sn-Ag-Cu-Bi solder joints in deionized water was investigated. Corrosion studies indicate that SnO crystals were generated on the surfaces of all lead-free solder joints. The constituents of the lead-free solder alloys, such as Ag, Cu, and Bi, did not affect the corrosion reaction significantly. In contrast to lead-free solders, PbO x was formed on the surface of the traditional 63Sn-37Pb solder joint in deionized water. A cathode, such as Au or Cu, was necessary for the electrochemical corrosion reaction of solders to occur. The corrosion reaction rate decreased with reduction of the cathode area. The formation mechanism of SnO crystals was essentially a galvanic cell reaction. The anodic reaction of Sn in the lead-free solder joints occurred through solvation by water molecules to form hydrated cations. In the cathodic reaction, oxygen dissolved in the deionized water captures electrons and is deoxidized to hydroxyl at the Au or Cu cathode. By diffusion, the anodic reaction product Sn2+ and the cathodic reaction product OH- meet to form Sn(OH)2, some of which can dehydrate to form more stable SnO· xH2O crystals on the surface of the solder joints. In addition, thermodynamic analysis confirms that the Sn corrosion reaction could occur spontaneously.

  2. Microstructure and Properties of Sn-10Bi- xCu Solder Alloy/Joint

    NASA Astrophysics Data System (ADS)

    Lai, Zhongmin; Ye, Dan

    2016-07-01

    The effect of Cu on the microstructure and properties of Sn-10Bi solder alloy/joint were investigated. The results showed that the microstructure of Sn-10Bi-Cu solder alloy consisted of a Sn-rich phase, Bi-rich phase, and particles of Cu6Sn5 intermetallic compounds (IMCs). The pasty range of Sn-10Bi- xCu had an influence on the spreading property of Sn-10Bi- xCu. Cu improved the growth of the IMCs layer during the liquid reaction stage. Furthermore, the hardness of the solder alloy increased as the Cu concentration of increased. The strength of the solder joint was controlled by the solder alloy hardness and the interfacial IMCs layer thickness together. For the joints with low solder alloy hardness and a thin IMCs layer, the fracture was in the solder alloy. For the joints with high solder alloy hardness and a thick IMCs layer, the fracture was in the IMCs layer.

  3. Dural reconstruction by fascia using a temperature-controlled CO2 laser soldering system

    NASA Astrophysics Data System (ADS)

    Forer, Boaz; Vasilyev, Tamar; Brosh, Tamar; Kariv, Naam; Gil, Ziv; Fliss, Dan M.; Katzir, Abraham

    2005-04-01

    Conventional methods for dura repair are normally based on sutures or stitches. These methods have several disadvantages: (1) The dura is often brittle, and the standard procedures are difficult and time consuming. (2) The seal is leaky. (3) The introduction of a foreign body (e.g. sutures) may cause an inflammatory response. In order to overcome these difficulties we used a temperature controlled fiber optic based CO2 laser soldering system. In a set of in vitro experiments we generated a hole of diameter 10 mm in the dura of a pig corpse, covered the hole with a segment of fascia, and soldered the fascia to the edges of the hole, using 47% bovine albumin as a solder. The soldering was carried out spot by spot, and each spot was heated to 65° C for 3-6 seconds. The soldered dura was removed and the burst pressure of the soldered patch was measured. The average value for microscopic muscular side soldering was 194 mm Hg. This is much higher than the maximal physiological pressure of the CSF fluid in the brain, which is 15 mm Hg. In a set of in vivo experiments, fascia patches were soldered on holes in five farm pigs. The long term results of these experiments were very promising. In conclusion, we have developed an advanced technique for dural reconstruction, which will find important clinical applications.

  4. Tissue soldering with biodegradable polymer films: in-vitro investigation of hydration effects on weld strength

    NASA Astrophysics Data System (ADS)

    Sorg, Brian S.; Welch, Ashley J.

    2001-05-01

    Previous work demonstrated increased breaking strengths of tissue repaired with liquid albumin solder reinforced with a biodegradable polymer film compared to unreinforced control specimens. It was hypothesized that the breaking strength increase was due to reinforcement of the liquid solder cohesive strength. Immersion in a moist environment can decrease the adhesion of solder to tissue and negate any strength benefits gained from reinforcement. The purpose of this study was to determine if hydrated specimens repaired with reinforced solder would still be stronger than unreinforced controls. A 50%(w/v) bovine serum albumin solder with 0.5 mg/mL Indocyanine Green dye was used to repair an incision in bovine aorta. The solder was coagulated with 806-nm diode laser light. A poly(DL-lactic- co-glycolic acid) film was used to reinforce the solder (the controls had no reinforcement). The repaired tissues were immersed in phosphate buffered saline for time periods of 1 and 2 days. The breaking strengths of all of the hydrated specimens decreased compared to the acute breaking strengths. However, the reinforced specimens still had larger breaking strengths than the unreinforced controls. These results indicate that reinforcement of a liquid albumin solder may have the potential to improve the breaking strength in a clinical setting.

  5. Development of technique for laser welding of biological tissues using laser welding device and nanocomposite solder.

    PubMed

    Gerasimenko, A; Ichcitidze, L; Podgaetsky, V; Ryabkin, D; Pyankov, E; Saveliev, M; Selishchev, S

    2015-08-01

    The laser device for welding of biological tissues has been developed involving quality control and temperature stabilization of weld seam. Laser nanocomposite solder applied onto a wound to be weld has been used. Physicochemical properties of the nanocomposite solder have been elucidated. The nature of the tissue-organizing nanoscaffold has been analyzed at the site of biotissue welding. PMID:26738200

  6. Microstructural Evaluation and Comparison of Solder Samples Processed Aboard the International Space Station

    NASA Technical Reports Server (NTRS)

    Grugel, R. N.; Hua, F.; Anilkumar, A. V.

    2008-01-01

    Samples from the In-Space Soldering Investigation (ISSI), conducted aboard the International Space Station (ISS), are being examined for post-solidification microstructural development and porosity distribution. In this preliminary study, the internal structures of two ISSI processed samples are compared. In one case 10cm of rosin-core solder was wrapped around a coupon wire and melted by conduction, whereas, in the other a comparable length of solder was melted directly onto the hot wire; in both cases the molten solder formed ellipsoidal blobs, a shape that was maintained during subsequent solidification. In the former case, there is clear evidence of porosity throughout the sample, and an accumulation of larger pores near the hot end that implies thermocapillary induced migration and eventual coalescence of the flux vapor bubbles. In the second context, when solder was fed onto the wire. a part of the flux constituting the solder core is introduced into and remains within the liquid solder ball, becoming entombed upon solidification. In both cases the consequential porosity, particularly at a solder/contact interface, is very undesirable. In addition to compromising the desired electrical and thermal conductivity, it promotes mechanical failure.

  7. New multicomponent solder alloys of low melting pointfor low-cost commercial electronic assembly

    NASA Astrophysics Data System (ADS)

    Al-Ganainy, G. S.; Sakr, M. S.

    2003-09-01

    The requirements of the telecommunications, automobile, electronics and aircraft industries for non-toxic solders with melting points close to that of near-eutectic Pb-Sn alloys has led to the development of new Sn-Zn-In solder alloys. Differential thermal analysis (DTA) shows melting points of 198, 195, 190 and 185 +/- 2 °C for the alloys Sn-9Zn, Sn-9Zn-2In, Sn-9Zn-4In and Sn-9Zn-6In, respectively. An equation that fits the data relating the melting point to the In content in the solders is derived. The X-ray diffraction patterns are analyzed to determine the phases that exist in each solder. The stress-strain curves are studied in the temperature range from 90 to 130 °C for all the solders except for those that contain 4 wt% of In, where the temperature range continues to 150 °C. The work-hardening parameters, y (the yield stress), f (the fracture stress), and the parabolic work-hardening coefficient X, increase with increasing indium content in the solders at all working temperatures. They decrease with increasing working temperature for each solder, and show two relaxation stages only for the Sn-9Zn-4In solder around a temperature of 120 °C. (

  8. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  9. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 30 Mineral Resources 1 2012-07-01 2012-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  10. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  11. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 30 Mineral Resources 1 2014-07-01 2014-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  12. 30 CFR 77.1111 - Welding, cutting, soldering; use of fire extinguisher.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 30 Mineral Resources 1 2013-07-01 2013-07-01 false Welding, cutting, soldering; use of fire... OF UNDERGROUND COAL MINES Fire Protection § 77.1111 Welding, cutting, soldering; use of fire extinguisher. One portable fire extinguisher shall be provided at each location where welding, cutting,...

  13. Interconnectivity structure of a general interdependent network.

    PubMed

    Van Mieghem, P

    2016-04-01

    A general two-layer network consists of two networks G_{1} and G_{2}, whose interconnection pattern is specified by the interconnectivity matrix B. We deduce desirable properties of B from a dynamic process point of view. Many dynamic processes are described by the Laplacian matrix Q. A regular topological structure of the interconnectivity matrix B (constant row and column sum) enables the computation of a nontrivial eigenmode (eigenvector and eigenvalue) of Q. The latter eigenmode is independent from G_{1} and G_{2}. Such a regularity in B, associated to equitable partitions, suggests design rules for the construction of interconnected networks and is deemed crucial for the interconnected network to show intriguing behavior, as discovered earlier for the special case where B=wI refers to an individual node to node interconnection with interconnection strength w. Extensions to a general m-layer network are also discussed.

  14. The Resistance and Strength of Soft Solder Splices between Conductors in MICE Coils

    SciTech Connect

    Wu, Hong; Pan, Heng; Green, Michael A; Dietderich, Dan; Gartner, T. E.; Higley, Hugh C; Mentink, M.; Xu, FengYu; Trillaud, F.; Liu, X. K.; Wang, Li; Zheng, S. X.; Tam, D.G.

    2010-08-03

    Two of the three types of MICE magnets will have splices within their coils. The MICE coupling coils may have as many as fifteen one-meter long splices within them. Each of the MICE focusing coils may have a couple of 0.25-meter long conductor splices. Equations for the calculation of resistance of soldered lap splices of various types are presented. This paper presents resistance measurements of soldered lap splices of various lengths. Measured splice resistance is shown for one-meter long splices as a function of the fabrication method. Another important consideration is the strength of the splices. The measured breaking stress of splices of various lengths is presented in this paper. Tin-lead solders and tin-silver solders were used for the splices that were tested. From the data given in this report, the authors recommend that the use of lead free solders be avoided for low temperature coils.

  15. Bonding nature of rare-earth-containing lead-free solders

    NASA Astrophysics Data System (ADS)

    Ramirez, Ainissa G.; Mavoori, Hareesh; Jin, Sungho

    2002-01-01

    The ability of rare-earth-containing lead-free solders to wet and bond to silica was investigated. Small additions of Lu (0.5-2 wt. %) added to eutectic Sn-Ag or Au-Sn solder render it directly solderable to a silicon oxide surface. The bonding is attributed to the migration of the rare-earth element to the solder-silica interface for chemical reaction and the creation of an interfacial layer that contains a rare-earth oxide. It was found that additions of rare-earth materials did not significantly modify the solidification microstructure or the melting point. Such oxide-bondable solders can be useful for assembly of various optical communication devices.

  16. Learning algorithms for both real-time detection of solder shorts and for SPC measurement correction using cross-sectional x-ray images of PCBA solder joints

    NASA Astrophysics Data System (ADS)

    Roder, Paul A.

    1994-03-01

    Learning algorithms are introduced for use in the inspection of cross-sectional X-ray images of solder joints. These learning algorithms improve measurement accuracy by accounting for localized shading effects that can occur when inspecting double- sided printed circuit board assemblies. Two specific examples are discussed. The first is an algorithm for detection of solder short defects. The second algorithm utilizes learning to generate more accurate statistical process control measurements.

  17. Fast formation and growth of high-density Sn whiskers in Mg/Sn-based solder/Mg joints by ultrasonic-assisted soldering: Phenomena, mechanism and prevention.

    PubMed

    Li, M Y; Yang, H F; Zhang, Z H; Gu, J H; Yang, S H

    2016-01-01

    A universally applicable method for promoting the fast formation and growth of high-density Sn whiskers on solders was developed by fabricating Mg/Sn-based solder/Mg joints using ultrasonic-assisted soldering at 250 °C for 6 s and then subjected to thermal aging at 25 °C for 7 d. The results showed that the use of the ultrasonic-assisted soldering could produce the supersaturated dissolution of Mg in the liquid Sn and lead to the existence of two forms of Mg in Sn after solidification. Moreover, the formation and growth of the high-density whiskers were facilitated by the specific contributions of both of the Mg forms in the solid Sn. Specifically, interstitial Mg can provide the persistent driving force for Sn whisker growth, whereas the Mg2Sn phase can increase the formation probability of Sn whiskers. In addition, we presented that the formation and growth of Sn whiskers in the Sn-based solders can be significantly restricted by a small amount of Zn addition (≥3 wt.%), and the prevention mechanisms are attributed to the segregation of Zn atoms at grain or phase boundaries and the formation of the lamellar-type Zn-rich structures in the solder. PMID:27273421

  18. Fast formation and growth of high-density Sn whiskers in Mg/Sn-based solder/Mg joints by ultrasonic-assisted soldering: Phenomena, mechanism and prevention.

    PubMed

    Li, M Y; Yang, H F; Zhang, Z H; Gu, J H; Yang, S H

    2016-06-08

    A universally applicable method for promoting the fast formation and growth of high-density Sn whiskers on solders was developed by fabricating Mg/Sn-based solder/Mg joints using ultrasonic-assisted soldering at 250 °C for 6 s and then subjected to thermal aging at 25 °C for 7 d. The results showed that the use of the ultrasonic-assisted soldering could produce the supersaturated dissolution of Mg in the liquid Sn and lead to the existence of two forms of Mg in Sn after solidification. Moreover, the formation and growth of the high-density whiskers were facilitated by the specific contributions of both of the Mg forms in the solid Sn. Specifically, interstitial Mg can provide the persistent driving force for Sn whisker growth, whereas the Mg2Sn phase can increase the formation probability of Sn whiskers. In addition, we presented that the formation and growth of Sn whiskers in the Sn-based solders can be significantly restricted by a small amount of Zn addition (≥3 wt.%), and the prevention mechanisms are attributed to the segregation of Zn atoms at grain or phase boundaries and the formation of the lamellar-type Zn-rich structures in the solder.

  19. Fast formation and growth of high-density Sn whiskers in Mg/Sn-based solder/Mg joints by ultrasonic-assisted soldering: Phenomena, mechanism and prevention

    NASA Astrophysics Data System (ADS)

    Li, M. Y.; Yang, H. F.; Zhang, Z. H.; Gu, J. H.; Yang, S. H.

    2016-06-01

    A universally applicable method for promoting the fast formation and growth of high-density Sn whiskers on solders was developed by fabricating Mg/Sn-based solder/Mg joints using ultrasonic-assisted soldering at 250 °C for 6 s and then subjected to thermal aging at 25 °C for 7 d. The results showed that the use of the ultrasonic-assisted soldering could produce the supersaturated dissolution of Mg in the liquid Sn and lead to the existence of two forms of Mg in Sn after solidification. Moreover, the formation and growth of the high-density whiskers were facilitated by the specific contributions of both of the Mg forms in the solid Sn. Specifically, interstitial Mg can provide the persistent driving force for Sn whisker growth, whereas the Mg2Sn phase can increase the formation probability of Sn whiskers. In addition, we presented that the formation and growth of Sn whiskers in the Sn-based solders can be significantly restricted by a small amount of Zn addition (≥3 wt.%), and the prevention mechanisms are attributed to the segregation of Zn atoms at grain or phase boundaries and the formation of the lamellar-type Zn-rich structures in the solder.

  20. Effect of the Silver Content of SnAgCu Solder on the Interfacial Reaction and on the Reliability of Angle Joints Fabricated by Laser-Jet Soldering

    NASA Astrophysics Data System (ADS)

    Ji, Hongjun; Ma, Yuyou; Li, Mingyu; Wang, Chunqing

    2015-02-01

    The silver content of lead-free solders affects their microstructure, the interfacial reaction, and the performance of the joints in reliability tests. In this study, Sn3.0Ag0.5Cu (wt.%, SAC305) and Sn1.0Ag0.5Cu (wt.%, SAC105) solder balls of diameter 55 μm were reflowed on gold surface pads by laser-jet soldering. It was found that four types of layered intermetallic compound (IMC) were formed at the interfaces; these were Au5Sn/AuSn, AuSn, AuSn2, and AuSn4 from the pad side to the solder matrix. The Au5Sn/AuSn eutectic region, thickness 400 nm, formed because of the high cooling rate induced by the laser-jet soldering. During high-temperature storage tests, the silver became segregated at the interfaces between the Au-Sn IMC and the solder matrix, resulting in inhibition of IMC growth in SAC305 joints, the shear strengths of which were higher than those of SAC105 joints. In mechanical drop tests, however, percentage failure of the SAC305 joints was twice that of the SAC105 joints.

  1. Fast formation and growth of high-density Sn whiskers in Mg/Sn-based solder/Mg joints by ultrasonic-assisted soldering: Phenomena, mechanism and prevention

    PubMed Central

    Li, M. Y.; Yang, H. F.; Zhang, Z. H.; Gu, J. H.; Yang, S. H.

    2016-01-01

    A universally applicable method for promoting the fast formation and growth of high-density Sn whiskers on solders was developed by fabricating Mg/Sn-based solder/Mg joints using ultrasonic-assisted soldering at 250 °C for 6 s and then subjected to thermal aging at 25 °C for 7 d. The results showed that the use of the ultrasonic-assisted soldering could produce the supersaturated dissolution of Mg in the liquid Sn and lead to the existence of two forms of Mg in Sn after solidification. Moreover, the formation and growth of the high-density whiskers were facilitated by the specific contributions of both of the Mg forms in the solid Sn. Specifically, interstitial Mg can provide the persistent driving force for Sn whisker growth, whereas the Mg2Sn phase can increase the formation probability of Sn whiskers. In addition, we presented that the formation and growth of Sn whiskers in the Sn-based solders can be significantly restricted by a small amount of Zn addition (≥3 wt.%), and the prevention mechanisms are attributed to the segregation of Zn atoms at grain or phase boundaries and the formation of the lamellar-type Zn-rich structures in the solder. PMID:27273421

  2. Assessment of Solder Joint Fatigue Life Under Realistic Service Conditions

    NASA Astrophysics Data System (ADS)

    Hamasha, Sa'd.; Jaradat, Younis; Qasaimeh, Awni; Obaidat, Mazin; Borgesen, Peter

    2014-12-01

    The behavior of lead-free solder alloys under complex loading scenarios is still not well understood. Common damage accumulation rules fail to account for strong effects of variations in cycling amplitude, and random vibration test results cannot be interpreted in terms of performance under realistic service conditions. This is a result of the effects of cycling parameters on materials properties. These effects are not yet fully understood or quantitatively predictable, preventing modeling based on parameters such as strain, work, or entropy. Depending on the actual spectrum of amplitudes, Miner's rule of linear damage accumulation has been shown to overestimate life by more than an order of magnitude, and greater errors are predicted for other combinations. Consequences may be particularly critical for so-called environmental stress screening. Damage accumulation has, however, been shown to scale with the inelastic work done, even if amplitudes vary. This and the observation of effects of loading history on subsequent work per cycle provide for a modified damage accumulation rule which allows for the prediction of life. Individual joints of four different Sn-Ag-Cu-based solder alloys (SAC305, SAC105, SAC-Ni, and SACXplus) were cycled in shear at room temperature, alternating between two different amplitudes while monitoring the evolution of the effective stiffness and work per cycle. This helped elucidate general trends and behaviors that are expected to occur in vibrations of microelectronics assemblies. Deviations from Miner's rule varied systematically with the combination of amplitudes, the sequences of cycles, and the strain rates in each. The severity of deviations also varied systematically with Ag content in the solder, but major effects were observed for all the alloys. A systematic analysis was conducted to assess whether scenarios might exist in which the more fatigue-resistant high-Ag alloys would fail sooner than the lower-Ag ones.

  3. Pb-free Sn-Ag-Cu ternary eutectic solder

    DOEpatents

    Anderson, Iver E.; Yost, Frederick G.; Smith, John F.; Miller, Chad M.; Terpstra, Robert L.

    1996-06-18

    A Pb-free solder includes a ternary eutectic composition consisting essentially of about 93.6 weight % Sn-about 4.7 weight % Ag-about 1.7 weight % Cu having a eutectic melting temperature of about 217.degree. C. and variants of the ternary composition wherein the relative concentrations of Sn, Ag, and Cu deviate from the ternary eutectic composition to provide a controlled melting temperature range (liquid-solid "mushy" zone) relative to the eutectic melting temperature (e.g. up to 15.degree. C. above the eutectic melting temperature).

  4. Pb-free Sn-Ag-Cu ternary eutectic solder

    DOEpatents

    Anderson, I.E.; Yost, F.G.; Smith, J.F.; Miller, C.M.; Terpstra, R.L.

    1996-06-18

    A Pb-free solder includes a ternary eutectic composition consisting essentially of about 93.6 weight % Sn-about 4.7 weight % Ag-about 1.7 weight % Cu having a eutectic melting temperature of about 217 C and variants of the ternary composition wherein the relative concentrations of Sn, Ag, and Cu deviate from the ternary eutectic composition to provide a controlled melting temperature range (liquid-solid ``mushy`` zone) relative to the eutectic melting temperature (e.g. up to 15 C above the eutectic melting temperature). 5 figs.

  5. Double interconnection fuel cell array

    DOEpatents

    Draper, R.; Zymboly, G.E.

    1993-12-28

    A fuel cell array is made, containing number of tubular, elongated fuel cells which are placed next to each other in rows (A, B, C, D), where each cell contains inner electrodes and outer electrodes, with solid electrolyte between the electrodes, where the electrolyte and outer electrode are discontinuous, having two portions, and providing at least two opposed discontinuities which contain at least two oppositely opposed interconnections contacting the inner electrode, each cell having only three metallic felt electrical connectors which contact surrounding cells, where each row is electrically connected to the other. 5 figures.

  6. Double interconnection fuel cell array

    DOEpatents

    Draper, Robert; Zymboly, Gregory E.

    1993-01-01

    A fuel cell array (10) is made, containing number of tubular, elongated fuel cells (12) which are placed next to each other in rows (A, B, C, D), where each cell contains inner electrodes (14) and outer electrodes (18 and 18'), with solid electrolyte (16 and 16') between the electrodes, where the electrolyte and outer electrode are discontinuous, having two portions, and providing at least two opposed discontinuities which contain at least two oppositely opposed interconnections (20 and 20') contacting the inner electrode (14), each cell (12) having only three metallic felt electrical connectors (22) which contact surrounding cells, where each row is electrically connected to the other.

  7. The polarity effect of electromigration on intermetallic compound formation and back stress in v-groove solder lines

    NASA Astrophysics Data System (ADS)

    Ou, Shengquan

    2005-07-01

    The trend of the miniaturization of VLSI and electronic packaging toward higher input/output density, smaller feature size and greater performance makes electromigration a serious reliability concern in flip chip technology. As an integral part of the joint, intermetallic compound (IMC) formation is very important to achieve good joint strength. However, the effect of electromigration on the IMC formation is a subject in which still very little is known. We utilize solder v-groove samples etched on (001) Si wafer with 100 mum opening to study the polarity effect of electromigration on IMC formation in solder joints. We focus on the interaction between chemical and electrical forces, and the influence of interface morphology on the IMC dissolution. The current densities used are from 103 to 104 A/cm2 and the temperature settings are in the range of 120°C to 180°C. We have found in both 95.5Sn3.8Ag0.7Cu/Cu and 96.5Sn3.5Ag systems the growth of the IMC has been enhanced by electric current at the anode and inhibited at the cathode. For Ni-Sn compound, kinetic analysis using the motion of the two interfaces gives the general formula of the growth rate as dXdt=aX + b. We have introduced the concept of mean-field theory and the classic model of Zener's precipitation growth into the discussion of the Cu-Sn compound growth under electromigration. A parabolic dependence of the IMC growth on time at the anode is derived as x 2 ≅ (Cm-Ce)2 (Cs-Ce)2 Dt. The interaction between chemical and electrical forces brings a dynamic equilibrium in IMC dissolution at the cathode. This has been proved theoretically and experimentally. A new critical product has been derived from this dynamic equilibrium, which can provide us a critical IMC thickness before voids formation at a given current density. Our study shows the dissolution rate of Cu with current density 5x103 A/cm2 at 150°C is about 0.076 mum/hr. We also notice that the interface morphology plays an important role in the IMC

  8. Imaging and Analysis of Void-defects in Solder Joints Formed in Reduced Gravity using High-Resolution Computed Tomography

    NASA Technical Reports Server (NTRS)

    Easton, John W.; Struk, Peter M.; Rotella, Anthony

    2008-01-01

    As a part of efforts to develop an electronics repair capability for long duration space missions, techniques and materials for soldering components on a circuit board in reduced gravity must be developed. This paper presents results from testing solder joint formation in low gravity on a NASA Reduced Gravity Research Aircraft. The results presented include joints formed using eutectic tin-lead solder and one of the following fluxes: (1) a no-clean flux core, (2) a rosin flux core, and (3) a solid solder wire with external liquid no-clean flux. The solder joints are analyzed with a computed tomography (CT) technique which imaged the interior of the entire solder joint. This replaced an earlier technique that required the solder joint to be destructively ground down revealing a single plane which was subsequently analyzed. The CT analysis technique is described and results presented with implications for future testing as well as implications for the overall electronics repair effort discussed.

  9. An approach to the optical interconnect made in standard CMOS process

    NASA Astrophysics Data System (ADS)

    Changliang, Yu; Luhong, Mao; Xindong, Xiao; Sheng, Xie; Shilin, Zhang

    2009-05-01

    A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

  10. Compact Interconnection Networks Based on Quantum Dots

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

    2003-01-01

    Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary

  11. Novel organic-inorganic hybrid materials for optical interconnects

    NASA Astrophysics Data System (ADS)

    Sato, Tetsuo

    2011-01-01

    Optical materials in the optical printed circuit board are required to overcome soldering process. In detail, the material should not have absorption and shape changes after several tens of seconds heating at around 250°C. For such application field, we have developed a novel organic-inorganic hybrid material having a high thermal stability and low absorption at telecom wavelength. The material is designed to UV and/or Thermal curable resin, and soluble to popular organic solvents. We fabricated a rigid optical waveguides on a SiO2/Si wafers by UV lithography. The size of waveguide was 40 μm in width, 30 μm in height, and 7 cm in length. Optical attenuation of the waveguide measured by the cut back method was 0.1 dB/cm at 850 nm, 0.29 dB/cm at 1310 nm, and 0.45 dB/cm at 1550 nm. These values are good low attenuation for the Near-IR optical communication. The 5% weight loss temperature of the UV cured material was 402°C. The waveguide showed almost no attenuation increase even after 1min heating at 300°C. In addition, the material is having a high refractive index of n=1.60 at 633 nm and a low curing shrinkage of 4.7%. We have demonstrated to fabricate a bulk body sample by UV curing, and obtained high uniformity cured materials with 5 mm-thick and 1 cm-diameter. From these properties, the developed organic-inorganic material is expected to be beneficial for the optical interconnection such as micro lenses and optical packages.

  12. Reconfigurable optical interconnection network for multimode optical fiber sensor arrays

    NASA Technical Reports Server (NTRS)

    Chen, R. T.; Robinson, D.; Lu, H.; Wang, M. R.; Jannson, T.; Baumbick, R.

    1992-01-01

    A single-source, single-detector architecture has been developed to implement a reconfigurable optical interconnection network multimode optical fiber sensor arrays. The network was realized by integrating LiNbO3 electrooptic (EO) gratings working at the Raman Na regime and a massive fan-out waveguide hologram (WH) working at the Bragg regime onto a multimode glass waveguide. The glass waveguide utilized the whole substrate as a guiding medium. A 1-to-59 massive waveguide fan-out was demonstrated using a WH operating at 514 nm. Measured diffraction efficiency of 59 percent was experimentally confirmed. Reconfigurability of the interconnection was carried out by generating an EO grating through an externally applied electric field. Unlike conventional single-mode integrated optical devices, the guided mode demonstrated has an azimuthal symmetry in mode profile which is the same as that of a fiber mode.

  13. Interconnect fatigue design for terrestrial photovoltaic modules

    NASA Technical Reports Server (NTRS)

    Mon, G. R.; Moore, D. M.; Ross, R. G., Jr.

    1982-01-01

    The results of comprehensive investigation of interconnect fatigue that has led to the definition of useful reliability-design and life-prediction algorithms are presented. Experimental data indicate that the classical strain-cycle (fatigue) curve for the interconnect material is a good model of mean interconnect fatigue performance, but it fails to account for the broad statistical scatter, which is critical to reliability prediction. To fill this shortcoming the classical fatigue curve is combined with experimental cumulative interconnect failure rate data to yield statistical fatigue curves (having failure probability as a parameter) which enable (1) the prediction of cumulative interconnect failures during the design life of an array field, and (2) the unambiguous--ie., quantitative--interpretation of data from field-service qualification (accelerated thermal cycling) tests. Optimal interconnect cost-reliability design algorithms are derived based on minimizing the cost of energy over the design life of the array field.

  14. Microstructure Evolution and Shear Behavior of the Solder Joints for Flip-Chip LED on ENIG Substrate

    NASA Astrophysics Data System (ADS)

    Liu, Yang; Sun, Fenglian; Luo, Liangliang; Yuan, Cadmus A.; Zhang, Guoqi

    2015-07-01

    The microstructure evolution and shear behavior of the solder joints for the flip-chip light-emitting diode on the electroless nickel/immersion gold (ENIG) substrate were investigated in this study. The experimental results reveal that the solder joints for the anode and cathode have different microstructures and failure characteristics during the shear test before and after isothermal aging. For the solder joints for the anode, the interfacial intermetallic compound (IMC) is (Au, Ni)Sn4 at the solder/anode interface but dendritic Ni3Sn4 grains at the solder/ENIG interface after reflow. Meanwhile, the dendritic Ni3Sn4 grains are surrounded by (Au, Ni)Sn4, which suppresses the growth of the Ni3Sn4 grains during aging. For the solder joints for the cathode, a nano scaled Au-rich layer can be observed near the cathode/solder layer interface after reflow. And the Au-rich layer moves toward the bulk solder because of the volume expansion by the transformation from Au into (Au, Ni)Sn4 during reflow and isothermal aging. Due to the diffusion of the Au atom from the Au-rich layer into the bulk solder, the Au-rich layer transformed into an interface inside of the solder joint. The average shear force of the solder joints shows a decrease from 380 gf to 250 gf because of the microstructure evolution during the isothermal aging for 1000 h at 85°C. After long time aging, the primary failure mode of the solder joint for the anode changed from the anode broken to the brittle failure of the solder layer. The delamination between the IMC layer and the insulation layer is suggested to be the dominated failure mode of the solder joint for the cathode after aging.

  15. Cascade solar cell having conductive interconnects

    DOEpatents

    Borden, Peter G.; Saxena, Ram R.

    1982-10-26

    Direct ohmic contact between the cells in an epitaxially grown cascade solar cell is obtained by means of conductive interconnects formed through grooves etched intermittently in the upper cell. The base of the upper cell is directly connected by the conductive interconnects to the emitter of the bottom cell. The conductive interconnects preferably terminate on a ledge formed in the base of the upper cell.

  16. A microstructural study of creep and thermal fatigue deformation in 60Sn-40Pb solder joints

    SciTech Connect

    Tribula, D.

    1990-06-02

    Thermal fatigue failures of solder joints in electronic devices often arise from cyclic shear strains imposed by the mismatched thermal expansion coefficients of the materials that bind the joint as temperature changes are encountered. Increased solder joint reliability demands a fundamental understanding of the metallurigical mechanisms that control the fatigue to design accurate accelerated probative tests and new, more fatigue resistant solder alloys. The high temperatures and slow strain rates that pertain to thermal fatigue imply that creep is an important deformation mode in the thermal fatigue cycle. In this work, the creep behaviour of a solder joint is studied to determine the solder's microstructural response to this type of deformation and to relate this to the more complex problem of thermal fatigue. It is shown that creep failures arise from the inherent inhomogeneity and instability of the solder microstructure and suggest that small compositional changes of the binary near-eutectic Pn-Sn alloy may defeat the observed failure mechanisms. This work presents creep and thermal fatigue data for several near-eutectic Pb-Sn solder compositions and concludes that a 58Sn-40Pb-2In and a 58Sn-40Pb-2Cd alloy show significantly enhanced fatigue resistance over that of the simple binary material. 80 refs., 33 figs., 1 tab.

  17. Enhanced laser tissue soldering using indocyanine green chromophore and gold nanoshells combination.

    PubMed

    Khosroshahi, Mohammad E; Nourbakhsh, Mohammad S

    2011-08-01

    Gold nanoshells (GNs) are new materials that have an optical response dictated by the plasmon resonance. The wavelength at which the resonance occurs depends on the core and shell sizes. The purposes of this study were to use the combination of indocyanine green (ICG) and different concentration of gold nanoshells for skin tissue soldering and also to examine the effect of laser soldering parameters on the properties of repaired skin. Two mixtures of albumin solder and different combinations of ICG and gold nanoshells were prepared. A full thickness incision of 2 × 20 mm(2) was made on the surface and after addition of mixtures it was irradiated by an 810 nm diode laser at different power densities. The changes of tensile strength (σ(t)) due to temperature rise, number of scan (Ns), and scan velocity (Vs) were investigated. The results showed at constant laser power density (I), σ(t) of repaired incisions increases by increasing the concentration of gold nanoshells in solder, Ns, and decreasing Vs. It was demonstrated that laser soldering using combination of ICG + GNs could be practical provided the optothermal properties of the tissue are carefully optimized. Also, the tensile strength of soldered skin is higher than skins that soldered with only ICG or GNs. In our case, this corresponds to σ(t) = 1800 g cm(-2) at I ∼ 47 Wcm(-2), T ∼ 85 [ordinal indicator, masculine]C, Ns = 10, and Vs = 0.3 mms(-1). PMID:21895342

  18. Temperature-controlled laser-soldering system and its clinical application for bonding skin incisions.

    PubMed

    Simhon, David; Gabay, Ilan; Shpolyansky, Gregory; Vasilyev, Tamar; Nur, Israel; Meidler, Roberto; Hatoum, Ossama Abu; Katzir, Abraham; Hashmonai, Moshe; Kopelman, Doron

    2015-01-01

    Laser tissue soldering is a method of repairing incisions. It involves the application of a biological solder to the approximated edges of the incision and heating it with a laser beam. A pilot clinical study was carried out on 10 patients who underwent laparoscopic cholecystectomy. Of the four abdominal incisions in each patient, two were sutured and two were laser soldered. Cicatrization, esthetical appearance, degree of pain, and pruritus in the incisions were examined on postoperative days 1, 7, and 30. The soldered wounds were watertight and healed well, with no discharge from these wounds or infection. The total closure time was equal in both methods, but the net soldering time was much shorter than suturing. There was no difference between the two types of wound closure with respect to the pain and pruritus on a follow-up of one month. Esthetically, the soldered incisions were estimated as good as the sutured ones. The present study confirmed that temperature-controlled laser soldering of human skin incisions is clinically feasible, and the results obtained were at least equivalent to those of standard suturing. PMID:26720882

  19. Temperature-controlled laser-soldering system and its clinical application for bonding skin incisions

    NASA Astrophysics Data System (ADS)

    Simhon, David; Gabay, Ilan; Shpolyansky, Gregory; Vasilyev, Tamar; Nur, Israel; Meidler, Roberto; Hatoum, Ossama Abu; Katzir, Abraham; Hashmonai, Moshe; Kopelman, Doron

    2015-12-01

    Laser tissue soldering is a method of repairing incisions. It involves the application of a biological solder to the approximated edges of the incision and heating it with a laser beam. A pilot clinical study was carried out on 10 patients who underwent laparoscopic cholecystectomy. Of the four abdominal incisions in each patient, two were sutured and two were laser soldered. Cicatrization, esthetical appearance, degree of pain, and pruritus in the incisions were examined on postoperative days 1, 7, and 30. The soldered wounds were watertight and healed well, with no discharge from these wounds or infection. The total closure time was equal in both methods, but the net soldering time was much shorter than suturing. There was no difference between the two types of wound closure with respect to the pain and pruritus on a follow-up of one month. Esthetically, the soldered incisions were estimated as good as the sutured ones. The present study confirmed that temperature-controlled laser soldering of human skin incisions is clinically feasible, and the results obtained were at least equivalent to those of standard suturing.

  20. Long-term effects of soldering fumes upon respiratory symptoms and pulmonary function.

    PubMed

    Rastogi, S K; Gupta, B N; Husain, T; Pangtey, B S; Srivastava, S; Garg, N

    1991-06-01

    To evaluate the long-term effect of soldering gases and fumes, and of cigarette smoke on lung function, and the prevalence of respiratory symptoms, a comparative study of spirometric measurements in 57 solderers engaged in acetylene gas soldering of brassware joints in the brass industry (mean exposure: 12.4 +/- 1.1 years) and in 131 controls was performed. The two groups were similar in age, height, smoking habits and social class. The prevalence of respiratory symptoms in the solderers did not differ significantly from that in the unexposed controls (59.6 vs 56.4%). However, solderers who smoked showed higher prevalence of respiratory symptoms than those who did not smoke; a similar trend was observed in the controls. The study failed to demonstrate any association between the respiratory symptoms and length of exposure. The respiratory status of the solderers was unaffected as the results of spirometric measurements of lung function did not show any significant differences between the exposed and the control groups, indicating the absence of an additive effect of cigarette smoking and exposure to soldering fumes.