Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

A CMOS Humidity Sensor for Passive RFID Sensing Applications

PubMed Central

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

PubMed

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

High-speed bipolar phototransistors in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Zimmermann, H

2013-03-01

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm 2 and 100×100 μm 2 . Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p + wafer with a p - epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Design and fabrication of a CMOS-compatible MHP gas sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao

2014-03-15

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperaturemore » in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.« less

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

NASA Astrophysics Data System (ADS)

Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

2017-06-01

Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

CMOS dot matrix microdisplay

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

PubMed

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

Characteristics of Various Photodiode Structures in CMOS Technology with Monolithic Signal Processing Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mukhopadhyay, Sourav; Chandratre, V. B.; Sukhwani, Menka

2011-10-20

Monolithic optical sensor with readout electronics are needed in optical communication, medical imaging and scintillator based gamma spectroscopy system. This paper presents the design of three different CMOS photodiode test structures and two readout channels in a commercial CMOS technology catering to the need of nuclear instrumentation. The three photodiode structures each of 1 mm{sup 2} with readout electronics are fabricated in 0.35 um, 4 metal, double poly, N-well CMOS process. These photodiode structures are based on available P-N junction of standard CMOS process i.e. N-well/P-substrate, P+/N-well/P-substrate and inter-digitized P+/N-well/P-substrate. The comparisons of typical characteristics among three fabricated photo sensorsmore » are reported in terms of spectral sensitivity, dark current and junction capacitance. Among the three photodiode structures N-well/P-substrate photodiode shows higher spectral sensitivity compared to the other two photodiode structures. The inter-digitized P+/N-well/P-substrate structure has enhanced blue response compared to N-well/P-substrate and P+/N-well/P-substrate photodiode. Design and test results of monolithic readout electronics, for three different CMOS photodiode structures for application related to nuclear instrumentation, are also reported.« less

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

PubMed Central

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

PubMed

López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

NASA Astrophysics Data System (ADS)

Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

2013-09-01

This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

Expansion of CMOS array design techniques

NASA Technical Reports Server (NTRS)

Feller, A.; Ramondetta, P.

1977-01-01

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

NASA Astrophysics Data System (ADS)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

Integration of image capture and processing: beyond single-chip digital camera

NASA Astrophysics Data System (ADS)

Lim, SukHwan; El Gamal, Abbas

2001-05-01

An important trend in the design of digital cameras is the integration of capture and processing onto a single CMOS chip. Although integrating the components of a digital camera system onto a single chip significantly reduces system size and power, it does not fully exploit the potential advantages of integration. We argue that a key advantage of integration is the ability to exploit the high speed imaging capability of CMOS image senor to enable new applications such as multiple capture for enhancing dynamic range and to improve the performance of existing applications such as optical flow estimation. Conventional digital cameras operate at low frame rates and it would be too costly, if not infeasible, to operate their chips at high frame rates. Integration solves this problem. The idea is to capture images at much higher frame rates than he standard frame rate, process the high frame rate data on chip, and output the video sequence and the application specific data at standard frame rate. This idea is applied to optical flow estimation, where significant performance improvements are demonstrate over methods using standard frame rate sequences. We then investigate the constraints on memory size and processing power that can be integrated with a CMOS image sensor in a 0.18 micrometers process and below. We show that enough memory and processing power can be integrated to be able to not only perform the functions of a conventional camera system but also to perform applications such as real time optical flow estimation.

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

PubMed

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

An SEU immune logic family

NASA Technical Reports Server (NTRS)

Canaris, J.

1991-01-01

A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.

A back-illuminated megapixel CMOS image sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

An all-silicon optical PC-to-PC link utilizing USB

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Alberts, Antonie C.; Venter, Petrus J.; du Plessis, Monuko; Rademeyer, Pieter

2013-02-01

An integrated silicon light source still remains the Holy Grail for integrated optical communication systems. Hot carrier luminescent light sources provide a way to create light in a standard CMOS process, potentially enabling cost effective optical communication between CMOS integrated circuits. In this paper we present a 1 Mb/s integrated silicon optical link for information transfer, targeting a real-world integrated solution by connecting two PCs via a USB port while transferring data optically between the devices. This realization represents the first optical communication product prototype utilizing a CMOS light emitter. The silicon light sources which are implemented in a standard 0.35 μm CMOS technology are electrically modulated and detected using a commercial silicon avalanche photodiode. Data rates exceeding 10 Mb/s using silicon light sources have previously been demonstrated using raw bit streams. In this work data is sent in two half duplex streams accompanied with the separate transmission of a clock. Such an optical communication system could find application in high noise environments where data fidelity, range and cost are a determining factor.

A novel multi-actuation CMOS RF MEMS switch

NASA Astrophysics Data System (ADS)

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

The fabrication of a programmable via using phase-change material in CMOS-compatible technology.

PubMed

Chen, Kuan-Neng; Krusin-Elbaum, Lia

2010-04-02

We demonstrate an energy-efficient programmable via concept using indirectly heated phase-change material. This via structure has maximum phase-change volume to achieve a minimum on resistance for high performance logic applications. Process development and material investigations for this device structure are reported. The device concept is successfully demonstrated in a standard CMOS-compatible technology capable of multiple cycles between on/off states for reconfigurable applications.

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

NASA Astrophysics Data System (ADS)

Pernegger, H.; Bates, R.; Buttar, C.; Dalla, M.; van Hoorne, J. W.; Kugathasan, T.; Maneuski, D.; Musa, L.; Riedler, P.; Riegel, C.; Sbarra, C.; Schaefer, D.; Schioppa, E. J.; Snoeys, W.

2017-06-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 1015neq/cm2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

PubMed

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

Low-Power SOI CMOS Transceiver

NASA Technical Reports Server (NTRS)

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

Quantitative optical metrology with CMOS cameras

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Kolenovic, Ervin; Ferguson, Curtis F.

2004-08-01

Recent advances in laser technology, optical sensing, and computer processing of data, have lead to the development of advanced quantitative optical metrology techniques for high accuracy measurements of absolute shapes and deformations of objects. These techniques provide noninvasive, remote, and full field of view information about the objects of interest. The information obtained relates to changes in shape and/or size of the objects, characterizes anomalies, and provides tools to enhance fabrication processes. Factors that influence selection and applicability of an optical technique include the required sensitivity, accuracy, and precision that are necessary for a particular application. In this paper, sensitivity, accuracy, and precision characteristics in quantitative optical metrology techniques, and specifically in optoelectronic holography (OEH) based on CMOS cameras, are discussed. Sensitivity, accuracy, and precision are investigated with the aid of National Institute of Standards and Technology (NIST) traceable gauges, demonstrating the applicability of CMOS cameras in quantitative optical metrology techniques. It is shown that the advanced nature of CMOS technology can be applied to challenging engineering applications, including the study of rapidly evolving phenomena occurring in MEMS and micromechatronics.

Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

PubMed

Seong-Jin Kim; Euisik Yoon

2012-06-01

We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate

PubMed Central

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 μm UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is −42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 μA, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

NASA Technical Reports Server (NTRS)

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Drake, G.; Garcia-Scivres, M.; Paramonov, A.

We propose to use silicon photonics technology to build radiation-hard fiber-optic links for high-bandwidth readout of tracking detectors. The CMOS integrated silicon photonics was developed by Luxtera and commercialized by Molex. The commercial off-the-shelf (COTS) fiber-optic links feature moderate radiation tolerance insufficient for trackers. A transceiver contains four RX and four TX channels operating at 10 Gbps each. The next generation will likely operate at 25 Gbps per channel. The approach uses a standard CMOS process and single-mode fibers, providing low power consumption and good scalability and reliability.

A Low-Cost CMOS Programmable Temperature Switch

PubMed Central

Li, Yunlong; Wu, Nanjian

2008-01-01

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis. PMID:27879871

Monolithic optical phased-array transceiver in a standard SOI CMOS process.

PubMed

Abediasl, Hooman; Hashemi, Hossein

2015-03-09

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

Synchronous high speed multi-point velocity profile measurement by heterodyne interferometry

NASA Astrophysics Data System (ADS)

Hou, Xueqin; Xiao, Wen; Chen, Zonghui; Qin, Xiaodong; Pan, Feng

2017-02-01

This paper presents a synchronous multipoint velocity profile measurement system, which acquires the vibration velocities as well as images of vibrating objects by combining optical heterodyne interferometry and a high-speed CMOS-DVR camera. The high-speed CMOS-DVR camera records a sequence of images of the vibrating object. Then, by extracting and processing multiple pixels at the same time, a digital demodulation technique is implemented to simultaneously acquire the vibrating velocity of the target from the recorded sequences of images. This method is validated with an experiment. A piezoelectric ceramic plate with standard vibration characteristics is used as the vibrating target, which is driven by a standard sinusoidal signal.

Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

PubMed

Zargham, Meysam; Gulak, P Glenn

2015-04-01

Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique

PubMed Central

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz. PMID:22454581

Manufacture of Micromirror Arrays Using a CMOS-MEMS Technique.

PubMed

Kao, Pin-Hsu; Dai, Ching-Liang; Hsu, Cheng-Chih; Wu, Chyan-Chyi

2009-01-01

In this study we used the commercial 0.35 μm CMOS (complementary metal oxide semiconductor) process and simple maskless post-processing to fabricate an array of micromirrors exhibiting high natural frequency. The micromirrors were manufactured from aluminum; the sacrificial layer was silicon dioxide. Because we fabricated the micromirror arrays using the standard CMOS process, they have the potential to be integrated with circuitry on a chip. For post-processing we used an etchant to remove the sacrificial layer and thereby suspend the micromirrors. The micromirror array contained a circular membrane and four fixed beams set symmetrically around and below the circular mirror; these four fan-shaped electrodes controlled the tilting of the micromirror. A MEMS (microelectromechanical system) motion analysis system and a confocal 3D-surface topography were used to characterize the properties and configuration of the micromirror array. Each micromirror could be rotated in four independent directions. Experimentally, we found that the micromirror had a tilting angle of about 2.55° when applying a driving voltage of 40 V. The natural frequency of the micromirrors was 59.1 kHz.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

A 205GHz Amplifier in 90nm CMOS Technology

DTIC Science & Technology

2017-03-01

San Jose State University San Jose, CA, USA       Abstract: This paper presents a 205GHz amplifier drawing 43.4mA from a 0.9V power supply with...10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...reported in [2]. In this paper, two neutralization techniques, internal and external approaches, have been implemented to achieve higher power

High speed CMOS/SOS standard cell notebook

NASA Technical Reports Server (NTRS)

1978-01-01

The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

A process modification for CMOS monolithic active pixel sensors for enhanced depletion, timing performance and radiation tolerance

NASA Astrophysics Data System (ADS)

Snoeys, W.; Aglieri Rinella, G.; Hillemanns, H.; Kugathasan, T.; Mager, M.; Musa, L.; Riedler, P.; Reidt, F.; Van Hoorne, J.; Fenigstein, A.; Leitner, T.

2017-11-01

For the upgrade of its Inner Tracking System, the ALICE experiment plans to install a new tracker fully constructed with monolithic active pixel sensors implemented in a standard 180 nm CMOS imaging sensor process, with a deep pwell allowing full CMOS within the pixel. Reverse substrate bias increases the tolerance to non-ionizing energy loss (NIEL) well beyond 1013 1 MeVneq /cm2, but does not allow full depletion of the sensitive layer and hence full charge collection by drift, mandatory for more extreme radiation tolerance. This paper describes a process modification to fully deplete the epitaxial layer even with a small charge collection electrode. It uses a low dose blanket deep high energy n-type implant in the pixel array and does not require significant circuit or layout changes so that the same design can be fabricated both in the standard and modified process. When exposed to a 55 Fe source at a reverse substrate bias of -6 V, pixels implemented in the standard and the modified process in a low and high dose variant for the deep n-type implant respectively yield a signal of about 115 mV, 110 mV and 90 mV at the output of a follower circuit. Signal rise times heavily affected by the speed of this circuit are 27 . 8 + / - 5 ns, 23 . 2 + / - 4 . 2 ns, and 22 . 2 + / - 3 . 7 ns rms, respectively. In a different setup, the single pixel signal from a 90 Sr source only degrades by less than 20% for the modified process after a 1015 1 MeVneq /cm2 irradiation, while the signal rise time only degrades by about 16 + / - 2 ns to 19 + / - 2 . 8 ns rms. From sensors implemented in the standard process no useful signal could be extracted after the same exposure. These first results indicate the process modification maintains low sensor capacitance, improves timing performance and increases NIEL tolerance by at least an order of magnitude.

Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

NASA Astrophysics Data System (ADS)

Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

2018-04-01

This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

C-MOS bulk metal design handbook. [LSI standard cell (circuits)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The LSI standard cell array technique was used in the fabrication of more than 20 CMOS custom arrays. This technique consists of a series of computer programs and design automation techniques referred to as the Computer Aided Design And Test (CADAT) system that automatically translate a partitioned logic diagram into a set of instructions for driving an automatic plotter which generates precision mask artwork for complex LSI arrays of CMOS standard cells. The standard cell concept for producing LSI arrays begins with the design, layout, and validation of a group of custom circuits called standard cells. Once validated, these cells are given identification or pattern numbers and are permanently stored. To use one of these cells in a logic design, the user calls for the desired cell by pattern number. The Place, Route in Two Dimension (PR2D) computer program is then used to automatically generate the metalization and/or tunnels to interconnect the standard cells into the required function. Data sheets that describe the function, artwork, and performance of each of the standard cells, the general procedure for implementation of logic in CMOS standard cells, and additional detailed design information are presented.

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

PubMed

Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

2014-11-17

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

A pseudo differential Gm—C complex filter with frequency tuning for IEEE802.15.4 applications

NASA Astrophysics Data System (ADS)

Xin, Cheng; Lungui, Zhong; Haigang, Yang; Fei, Liu; Tongqiang, Gao

2011-07-01

This paper presents a CMOS Gm—C complex filter for a low-IF receiver of the IEEE 802.15.4 standard. A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator. A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated. The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately. The chip was fabricated in a standard 0.35 μm CMOS process, with a single 3.3 V power supply. The filter consumes 2.1mA current, has a measured in-band group delay ripple of less than 0.16 μs and an IRR larger than 28 dB at 2 MHz apart, which could meet the requirements oftheIEEE802.15.4 standard.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels.

PubMed

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshiari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-09-02

In this paper we present a novel, quadruple well process developed in a modern 0.18 mm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 mm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

PubMed

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

A 0.13µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

NASA Astrophysics Data System (ADS)

Agawa, Kenichi; Ishizuka, Shinichiro; Majima, Hideaki; Kobayashi, Hiroyuki; Koizumi, Masayuki; Nagano, Takeshi; Arai, Makoto; Shimizu, Yutaka; Maki, Asuka; Urakawa, Go; Terada, Tadashi; Itoh, Nobuyuki; Hamada, Mototsugu; Fujii, Fumie; Kato, Tadamasa; Yoshitomi, Sadayuki; Otsuka, Nobuaki

A 2.4GHz 0.13µm CMOS transceiver LSI, supporting Bluetooth V2.1 + enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40°C and +90°C. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13µm CMOS and operation at a low supply voltage of 1.5V result in small area and low power consumption.

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

PubMed

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

The Comfort Measures Order Set at a Tertiary Care Academic Hospital: Is There a Comparable Difference in End-of-Life Care Between Patients Dying in Acute Care When CMOS Is Utilized?

PubMed

Lau, Christine; Stilos, Kalli; Nowell, Allyson; Lau, Fanchea; Moore, Jennifer; Wynnychuk, Lesia

2018-04-01

Standardized protocols have been previously shown to be helpful in managing end-of-life (EOL) care in hospital. The comfort measures order set (CMOS), a standardized framework for assessing imminently dying patients' symptoms and needs, was implemented at a tertiary academic hospital. We assessed whether there were comparable differences in the care of a dying patient when the CMOS was utilized and when it was not. A retrospective chart review was completed on patients admitted under oncology and general internal medicine, who were referred to the inpatient palliative care team for "EOL care" between February 2015 and March 2016. Of 83 patients, 56 (67%) received intiation of the CMOS and 27 (33%) did not for EOL care. There was significant involvement of spiritual care with the CMOS (66%), as compared to the group without CMOS (19%), P < .05. The use of CMOS resulted in 1.7 adjustments to symptom management per patient by palliative care, which was significantly less than the number of symptom management adjustments per patient when CMOS was not used (3.3), P < .05. However, initiating CMOS did not result in a signficant difference in patient distress around the time of death ( P = .11). Dyspnea was the most frequently identified symptom causing distress in actively dying patients. Implementation of the CMOS is helpful in providing a foundation to a comfort approach in imminently dying patients. However, more education on its utility as a framework for EOL care and assessment across the organization is still required.

Experimental study of the spatially-modulated light detector

NASA Astrophysics Data System (ADS)

Coppée, Daniël; Pan, Wei; Stiens, Johan; Vounckx, Roger; Kuijk, Maarten

1999-03-01

Usually, integrated detectors in CMOS exhibit long recovery times, limiting the detector bandwidth to only a few MHz. This is due to the long absorption length and the slow diffusion speed of photo-generated carriers. Different approaches have been proposed to solve these problems hereby taxing the compatibility with standard CMOS fabrication processing. We present a novel detector for high-speed light detection in standard CMOS. To solve the problem of slow CMOS-detector recovery, the incident light is spatially modulated and the spatially modulated component of the photo-generated carrier distribution is measured. Though only a single light input signal is required, from the detector on, analog signal processing can be achieved fully differentially. Subsequently, expected good PSRR (Power supply rejection ratio) allows integration with digital circuits. Avoiding hybridization eliminates the conventional problems caused by bonding-pad capacitance, bonding-wire inductance. This reduces the associated signal degradation. In addition, the very low detector capacitance, due to the low effectively used detector area and the low area capacitance of the n-well junction, yields high voltage readout of the detector. This facilitates further amplification and conversion to digital signal levels. The detector will be applicable in arrays due to expected low cross talk. The expected fields of operation involve: serial and parallel optical communication receivers (e.g. for WDM), DVD-reading heads with integrated amplifier, etc. First measurements show 200 Mbit/s operation with a detector-responsivity of 0.05 A/W at λ=860 nm and 0.132 A/W at λ=635 nm. The detector has inherently a low capacitance, in this case only 50 fF (for an effective detector area of 70×70 μm 2).

Micrometer-scale fabrication of complex three dimensional lattice + basis structures in silicon

DOE PAGES

Burckel, D. Bruce; Resnick, Paul J.; Finnegan, Patrick S.; ...

2015-01-01

A complementary metal oxide semiconductor (CMOS) compatible version of membrane projection lithography (MPL) for fabrication of micrometer-scale three-dimensional structures is presented. The approach uses all inorganic materials and standard CMOS processing equipment. In a single layer, MPL is capable of creating all 5 2D-Bravais lattices. Furthermore, standard semiconductor processing steps can be used in a layer-by-layer approach to create fully three dimensional structures with any of the 14 3D-Bravais lattices. The unit cell basis is determined by the projection of the membrane pattern, with many degrees of freedom for defining functional inclusions. Here we demonstrate several unique structural motifs, andmore » characterize 2D arrays of unit cells with split ring resonators in a silicon matrix. The structures exhibit strong polarization dependent resonances and, for properly oriented split ring resonators (SRRs), coupling to the magnetic field of a normally incident transverse electromagnetic wave, a response unique to 3D inclusions.« less

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

NASA Astrophysics Data System (ADS)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.

2017-12-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

PubMed

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels

PubMed Central

Ballin, Jamie Alexander; Crooks, Jamie Phillip; Dauncey, Paul Dominic; Magnan, Anne-Marie; Mikami, Yoshinari; Miller, Owen Daniel; Noy, Matthew; Rajovic, Vladimir; Stanitzki, Marcel; Stefanov, Konstantin; Turchetta, Renato; Tyndel, Mike; Villani, Enrico Giulio; Watson, Nigel Keith; Wilson, John Allan

2008-01-01

In this paper we present a novel, quadruple well process developed in a modern 0.18 μm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 μm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency. PMID:27873817

IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

2015-08-01

SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Innovative monolithic detector for tri-spectral (THz, IR, Vis) imaging

NASA Astrophysics Data System (ADS)

Pocas, S.; Perenzoni, M.; Massari, N.; Simoens, F.; Meilhan, J.; Rabaud, W.; Martin, S.; Delplanque, B.; Imperinetti, P.; Goudon, V.; Vialle, C.; Arnaud, A.

2012-10-01

Fusion of multispectral images has been explored for many years for security and used in a number of commercial products. CEA-Leti and FBK have developed an innovative sensor technology that gathers monolithically on a unique focal plane arrays, pixels sensitive to radiation in three spectral ranges that are terahertz (THz), infrared (IR) and visible. This technology benefits of many assets for volume market: compactness, full CMOS compatibility on 200mm wafers, advanced functions of the CMOS read-out integrated circuit (ROIC), and operation at room temperature. The ROIC houses visible APS diodes while IR and THz detections are carried out by microbolometers collectively processed above the CMOS substrate. Standard IR bolometric microbridges (160x160 pixels) are surrounding antenna-coupled bolometers (32X32 pixels) built on a resonant cavity customized to THz sensing. This paper presents the different technological challenges achieved in this development and first electrical and sensitivity experimental tests.

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Color sensor and neural processor on one chip

NASA Astrophysics Data System (ADS)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Capacitance pressure sensor

DOEpatents

Eaton, William P.; Staple, Bevan D.; Smith, James H.

2000-01-01

A microelectromechanical (MEM) capacitance pressure sensor integrated with electronic circuitry on a common substrate and a method for forming such a device are disclosed. The MEM capacitance pressure sensor includes a capacitance pressure sensor formed at least partially in a cavity etched below the surface of a silicon substrate and adjacent circuitry (CMOS, BiCMOS, or bipolar circuitry) formed on the substrate. By forming the capacitance pressure sensor in the cavity, the substrate can be planarized (e.g. by chemical-mechanical polishing) so that a standard set of integrated circuit processing steps can be used to form the electronic circuitry (e.g. using an aluminum or aluminum-alloy interconnect metallization).

A high speed CCSDS encoder for space applications

NASA Technical Reports Server (NTRS)

Whitaker, S.; Liu, K.

1990-01-01

This paper reports a VLSI implementation of the CCSDS standard Reed Solomon encoder circuit for the Space Station. The 1.0 micron double metal CMOS chip is 5.9 mm by 3.6 mm, contains 48,000 transistors, operates at a sustained data rate of 320 Mbits/s, and executes 2,560 Mops. The chip features a pin selectable interleave depth of 1 to 8. Block lengths of up to 255 bytes, as well as shortened codes, are supported. The control circuitry uses register cells which are immune to Single Event Upset. In addition, the CMOS process used is reported to be tolerant of over 1 Mrad total dose radiation.

Self-calibrated humidity sensor in CMOS without post-processing.

PubMed

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

NASA Astrophysics Data System (ADS)

Davidson, Bradley Darren

This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3--5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5--3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-film NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 10-3. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin-film NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered.

Split Bull's eye shaped aluminum antenna for plasmon-enhanced nanometer scale germanium photodetector.

PubMed

Ren, Fang-Fang; Ang, Kah-Wee; Ye, Jiandong; Yu, Mingbin; Lo, Guo-Qiang; Kwong, Dim-Lee

2011-03-09

Bull's eye antennas are capable of efficiently collecting and concentrating optical signals into an ultrasmall area, offering an excellent solution to break the bottleneck between speed and photoresponse in subwavelength photodetectors. Here, we exploit the idea of split bull's eye antenna for a nanometer germanium photodetector operating at a standard communication wavelength of 1310 nm. The nontraditional plasmonic metal aluminum has been implemented in the resonant antenna structure fabricated by standard complementary metal-oxide-semiconductor (CMOS) processing. A significant enhancement in photoresponse could be achieved over the conventional bull's eye scheme due to an increased optical near-field in the active region. Moreover, with this novel antenna design the effective grating area could be significantly reduced without sacrificing device performance. This work paves the way for the future development of low-cost, high-density, and high-speed CMOS-compatible germanium-based optoelectronic devices.

Silicon-gate CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1979-01-01

Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discussed, as well as the following process variations: (1) the double epi process; and (2) ion implantation.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Floating Gate CMOS Dosimeter With Frequency Output

NASA Astrophysics Data System (ADS)

Garcia-Moreno, E.; Isern, E.; Roca, M.; Picos, R.; Font, J.; Cesari, J.; Pineda, A.

2012-04-01

This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

CMOS array design automation techniques. [metal oxide semiconductors

NASA Technical Reports Server (NTRS)

Ramondetta, P.; Feller, A.; Noto, R.; Lombardi, T.

1975-01-01

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Carbon Nanotube Integration with a CMOS Process

PubMed Central

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Spatial optical crosstalk in CMOS image sensors integrated with plasmonic color filters.

PubMed

Yu, Yan; Chen, Qin; Wen, Long; Hu, Xin; Zhang, Hui-Fang

2015-08-24

Imaging resolution of complementary metal oxide semiconductor (CMOS) image sensor (CIS) keeps increasing to approximately 7k × 4k. As a result, the pixel size shrinks down to sub-2μm, which greatly increases the spatial optical crosstalk. Recently, plasmonic color filter was proposed as an alternative to conventional colorant pigmented ones. However, there is little work on its size effect and the spatial optical crosstalk in a model of CIS. By numerical simulation, we investigate the size effect of nanocross array plasmonic color filters and analyze the spatial optical crosstalk of each pixel in a Bayer array of a CIS with a pixel size of 1μm. It is found that the small pixel size deteriorates the filtering performance of nanocross color filters and induces substantial spatial color crosstalk. By integrating the plasmonic filters in the low Metal layer in standard CMOS process, the crosstalk reduces significantly, which is compatible to pigmented filters in a state-of-the-art backside illumination CIS.

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE PAGES

An, Mangmang; Chen, Chufeng; Gao, Chaosong; ...

2015-12-12

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE Office of Scientific and Technical Information (OSTI.GOV)

An, Mangmang; Chen, Chufeng; Gao, Chaosong

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

A CMOS-Compatible, Low-Noise ISFET Based on High Efficiency Ion-Modulated Lateral-Bipolar Conduction

PubMed Central

Chang, Sheng-Ren; Chen, Hsin

2009-01-01

Ion-sensitive, field-effect transistors (ISFET) have been useful biosensors in many applications. However, the signal-to-noise ratio of the ISFET is limited by its intrinsic, low-frequency noise. This paper presents an ISFET capable of utilizing lateral-bipolar conduction to reduce low-frequency noise. With a particular layout design, the conduction efficiency is further enhanced. Moreover, the ISFET is compatible with the standard CMOS technology. All materials above the gate-oxide are removed by simple, die-level post-CMOS process, allowing ions to modulate the lateral-bipolar current directly. By varying the gate-to-bulk voltage, the operation mode of the ISFET is controlled effectively, so is the noise performance measured and compared. Finally, the biasing conditions preferable for different low-noise applications are identified. Under the identified biasing condition, the signal-to-noise ratio of the ISFET as a pH sensor is proved to be improved by more than five times. PMID:22408508

SU-E-I-25: Performance Evaluation of a Proposed CMOS-Based X-Ray Detector Using Linear Cascade Model Analysis.

PubMed

Jain, A; Bednarek, D; Rudin, S

2012-06-01

The need for high-resolution, dynamic x-ray imaging capability for neurovascular applications has put an ever increasing demand on x-ray detector technology. Present state-of-the-art detectors such as flat panels have limited resolution and noise performance. A linear cascade model analysis was used to estimate the theoretical performance for a proposed CMOS-based detector. The proposed CMOS-based detector was assumed to have a 300-micron thick HL type CsI phosphor, 35-micron pixels, a variable gain light image intensifier (LU), and 400 electron readout noise. The proposed detector has a CMOS sensor coupled to an LII which views the output of the CsI phosphor. For the analysis the whole imaging chain was divided into individual stages characterized by one of the basic processes (stochastic/deterministic blurring, binomial selection, quantum gain, additive noise). Standard linear cascade modeling was used for the propagation of signal and noise through the stages and an RQA5 spectrum was assumed. The gain, blurring or transmission of different stages was either measured or taken from manufacturer's specifications. The theoretically calculated MTF and DQE for the proposed detector were compared with a high-resolution, high-sensitive Micro-Angio Fluoroscope (MAF), predecessor of the proposed detector. Signal and noise for each of the 19 stages in the complete imaging chain were calculated and showed improved performance. For example, at 5 cycles/mm the MTF and DQE were 0.08 and 0.28, respectively, for the CMOS detector compared to 0.05 and 0.07 for the MAF detector. The proposed detector will have improved MTF and DQE and slimmer physical dimension due to the elimination of the large fiber-optic taper used in the MAF. Once operational, the proposed CMOS detector will serve as a further improvement over standard flat panel detectors compared to the MAF which is already receiving a very positive reception by neuro-vascular interventionalists. (Support:NIH-Grant R01EB002873) NIH Grants R01- EB008425, R01-EB002873 and an equipment grant from Toshiba Medical Systems Corp. © 2012 American Association of Physicists in Medicine.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

Fabrication of the planar angular rotator using the CMOS process

NASA Astrophysics Data System (ADS)

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Jiafeng; Fan, Xiangning; Shi, Xiaoyang; Wang, Zhigong

2017-12-01

With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source-coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. Δ-Σ modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18μm CMOS process, the fractional-N frequency divider occupies a chip area of 1130 × 510 μm2 and it can correctly divide within the frequency range of 0.8-9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.

Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

NASA Astrophysics Data System (ADS)

Mahzabeen, Tabassum

The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be recovered using several methods; for example, using tunable transmission line lengths in the amplifier or using a variable supply voltage. This concept of estimating process variation has been demonstrated in Agilent Design System (ADS).

Investigation of high-speed Si photodetectors in standard CMOS technology

NASA Astrophysics Data System (ADS)

Wang, Huaqiang; Guo, Xia

2018-05-01

In this paper, the frequency response characteristics of the photodetector(PD) were studied considering intrinsic and extrinsic effects. Then we designed the interdigitated p-i-n PD on Silicon-on-Insulator (SOI) and epitaxial (EPI) substrates with photosensitive area of 30-μm diameter, fabricated by CMOS process. The 2-μm finger-spacing devices exhibited a 205 MHz bandwidth at a reverse bias of 3 V processed on 2-μm SOI substrates. EPI devices with 1 μm finger spacing exhibited a 131 MHz bandwidth under -3 V. Responsivity of 0.051 A/W and 0.21 A/W were measured at 850 nm on SOI and EPI substrates, respectively. Compared with the bulk silicon PD, the bandwidth is greatly improved. The PD gains the high cost performance ratio, which can be widely used in short distance communication such as visible light communication and free space optical communication.

Nano-patterned visible wavelength filter integrated with an image sensor exploiting a 90-nm CMOS process

NASA Astrophysics Data System (ADS)

Yoon, Yeo-Taek; Lee, Sang-Shin; Lee, Byoung-Su

2012-01-01

A highly efficient visible wavelength filter enabling a homogeneous integration with an image sensor was proposed and manufactured by employing a standard 90-nm CMOS process. A one dimensional subwavelength Al grating overlaid with an oxide film was built on top of an image sensor to serve as a low-pass wavelength filter; a microlens was then formed atop the filter to achieve beam focusing. The structural parameters for the filter were: a grating pitch of 300 nm, a grating height of 170 nm, and a 150-nm thick oxide overlay. The overall transmission was observed to reach up to 80% in the visible band with a decent roll-off near ∼700 nm. Finally, the discrepancy between the observed and calculated result was accounted for by appropriately modeling the implemented metallic grating structure, accompanying an undercut sidewall.

A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis.

PubMed

Huang, Xiwei; Yu, Hao; Liu, Xu; Jiang, Yu; Yan, Mei; Wu, Dongping

2015-09-01

The existing ISFET-based DNA sequencing detects hydrogen ions released during the polymerization of DNA strands on microbeads, which are scattered into microwell array above the ISFET sensor with unknown distribution. However, false pH detection happens at empty microwells due to crosstalk from neighboring microbeads. In this paper, a dual-mode CMOS ISFET sensor is proposed to have accurate pH detection toward DNA sequencing. Dual-mode sensing, optical and chemical modes, is realized by integrating a CMOS image sensor (CIS) with ISFET pH sensor, and is fabricated in a standard 0.18-μm CIS process. With accurate determination of microbead physical locations with CIS pixel by contact imaging, the dual-mode sensor can correlate local pH for one DNA slice at one location-determined microbead, which can result in improved pH detection accuracy. Moreover, toward a high-throughput DNA sequencing, a correlated-double-sampling readout that supports large array for both modes is deployed to reduce pixel-to-pixel nonuniformity such as threshold voltage mismatch. The proposed CMOS dual-mode sensor is experimentally examined to show a well correlated pH map and optical image for microbeads with a pH sensitivity of 26.2 mV/pH, a fixed pattern noise (FPN) reduction from 4% to 0.3%, and a readout speed of 1200 frames/s. A dual-mode CMOS ISFET sensor with suppressed FPN for accurate large-arrayed pH sensing is proposed and demonstrated with state-of-the-art measured results toward accurate and high-throughput DNA sequencing. The developed dual-mode CMOS ISFET sensor has great potential for future personal genome diagnostics with high accuracy and low cost.

Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Delta Doping High Purity CCDs and CMOS for LSST

NASA Technical Reports Server (NTRS)

Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

2006-01-01

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

Determining the Performance of Fluorescence Molecular Imaging Devices using Traceable Working Standards with SI Units of Radiance

PubMed Central

Zhu, Banghe; Rasmussen, John C.; Litorja, Maritoni

2017-01-01

To date, no emerging preclinical or clinical near-infrared fluorescence (NIRF) imaging devices for non-invasive and/or surgical guidance have their performances validated on working standards with SI units of radiance that enable comparison or quantitative quality assurance. In this work, we developed and deployed a methodology to calibrate a stable, solid phantom for emission radiance with units of mW · sr−1 · cm−2 for use in characterizing the measurement sensitivity of ICCD and IsCMOS detection, signal-to-noise ratio, and contrast. In addition, at calibrated radiances, we assess transverse and lateral resolution of ICCD and IsCMOS camera systems. The methodology allowed determination of superior SNR of the ICCD over the IsCMOS camera system and superior resolution of the IsCMOS over the ICCD camera system. Contrast depended upon the camera settings (binning and integration time) and gain of intensifier. Finally, because of architecture of CMOS and CCD camera systems resulting in vastly different performance, we comment on the utility of these systems for small animal imaging as well as clinical applications for non-invasive and surgical guidance. PMID:26552078

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

A Review on Passive and Integrated Near-Field Microwave Biosensors

PubMed Central

Guha, Subhajit; Jamal, Farabi Ibne

2017-01-01

In this paper we review the advancement of passive and integrated microwave biosensors. The interaction of microwave with biological material is discussed in this paper. Passive microwave biosensors are microwave structures, which are fabricated on a substrate and are used for sensing biological materials. On the other hand, integrated biosensors are microwave structures fabricated in standard semiconductor technology platform (CMOS or BiCMOS). The CMOS or BiCMOS sensor technology offers a more compact sensing approach which has the potential in the future for point of care testing systems. Various applications of the passive and the integrated sensors have been discussed in this review paper. PMID:28946617

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nam, Chang-Yong; Stein, Aaron

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

Extreme Carrier Depletion and Superlinear Photoconductivity in Ultrathin Parallel-Aligned ZnO Nanowire Array Photodetectors Fabricated by Infiltration Synthesis

DOE PAGES

Nam, Chang-Yong; Stein, Aaron

2017-11-15

Ultrathin semiconductor nanowires enable high-performance chemical sensors and photodetectors, but their synthesis and device integration by standard complementary metal-oxide-semiconductor (CMOS)-compatible processes remain persistent challenges. This work demonstrates fully CMOS-compatible synthesis and integration of parallel-aligned polycrystalline ZnO nanowire arrays into ultraviolet photodetectors via infiltration synthesis, material hybridization technique derived from atomic layer deposition. The nanowire photodetector features unique, high device performances originating from extreme charge carrier depletion, achieving photoconductive on–off ratios of >6 decades, blindness to visible light, and ultralow dark currents as low as 1 fA, the lowest reported for nanostructure-based photoconductive photodetectors. Surprisingly, the low dark current is invariantmore » with increasing number of nanowires and the photodetector shows unusual superlinear photoconductivity, observed for the first time in nanowires, leading to increasing detector responsivity and other parameters for higher incident light powers. Temperature-dependent carrier concentration and mobility reveal the photoelectrochemical-thermionic emission process at grain boundaries, responsible for the observed unique photodetector performances and superlinear photoconductivity. Here, the results elucidate fundamental processes responsible for photogain in polycrystalline nanostructures, providing useful guidelines for developing nanostructure-based detectors and sensors. Lastly, the developed fully CMOS-compatible nanowire synthesis and device fabrication methods also have potentials for scalable integration of nanowire sensor devices and circuitries.« less

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

Application of CMOS Technology to Silicon Photomultiplier Sensors.

PubMed

D'Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-09-25

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

A dual-mode secure UHF RFID tag with a crypto engine in 0.13-μm CMOS

NASA Astrophysics Data System (ADS)

Tao, Yang; Linghao, Zhu; Xi, Tan; Junyu, Wang; Lirong, Zheng; Hao, Min

2016-07-01

An ultra-high-frequency (UHF) radio frequency identification (RFID) secure tag chip with a non-crypto mode and a crypto mode is presented. During the supply chain management, the tag works in the non-crypto mode in which the on-chip crypto engine is not enabled and the tag chip has a sensitivity of -12.8 dBm for long range communication. At the point of sales (POS), the tag will be switched to the crypto mode in order to protect the privacy of customers. In the crypto mode, an advanced encryption standard (AES) crypto engine is enabled and the sensitivity of the tag chip is switched to +2 dBm for short range communication, which is a method of physical protection. The tag chip is implemented and verified in a standard 0.13-μm CMOS process. Project supported by the National Science & Technology Pillar Program of China (No. 2015BAK36B01).

Implementation of a wireless ECG acquisition SoC for IEEE 802.15.4 (ZigBee) applications.

PubMed

Wang, Liang-Hung; Chen, Tsung-Yen; Lin, Kuang-Hao; Fang, Qiang; Lee, Shuenn-Yuh

2015-01-01

This paper presents a wireless biosignal acquisition system-on-a-chip (WBSA-SoC) specialized for electrocardiogram (ECG) monitoring. The proposed system consists of three subsystems, namely, 1) the ECG acquisition node, 2) the protocol for standard IEEE 802.15.4 ZigBee system, and 3) the RF transmitter circuits. The ZigBee protocol is adopted for wireless communication to achieve high integration, applicability, and portability. A fully integrated CMOS RF front end containing a quadrature voltage-controlled oscillator and a 2.4-GHz low-IF (i.e., zero-IF) transmitter is employed to transmit ECG signals through wireless communication. The low-power WBSA-SoC is implemented by the TSMC 0.18-μm standard CMOS process. An ARM-based displayer with FPGA demodulation and an RF receiver with analog-to-digital mixed-mode circuits are constructed as verification platform to demonstrate the wireless ECG acquisition system. Measurement results on the human body show that the proposed SoC can effectively acquire ECG signals.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

USB video image controller used in CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhang, Wenxuan; Wang, Yuxia; Fan, Hong

2002-09-01

CMOS process is mainstream technique in VLSI, possesses high integration. SE402 is multifunction microcontroller, which integrates image data I/O ports, clock control, exposure control and digital signal processing into one chip. SE402 reduces the number of chips and PCB's room. The paper studies emphatically on USB video image controller used in CMOS image sensor and give the application on digital still camera.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

NASA Technical Reports Server (NTRS)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

PubMed Central

Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

2014-01-01

Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

3D MEMS in Standard Processes: Fabrication, Quality Assurance, and Novel Measurement Microstructures

NASA Technical Reports Server (NTRS)

Lin, Gisela; Lawton, Russell A.

2000-01-01

Three-dimensional MEMS microsystems that are commercially fabricated require minimal post-processing and are easily integrated with CMOS signal processing electronics. Measurements to evaluate the fabrication process (such as cross-sectional imaging and device performance characterization) provide much needed feedback in terms of reliability and quality assurance. MEMS technology is bringing a new class of microscale measurements to fruition. The relatively small size of MEMS microsystems offers the potential for higher fidelity recordings compared to macrosize counterparts, as illustrated in the measurement of muscle cell forces.

Application of CMOS Technology to Silicon Photomultiplier Sensors

PubMed Central

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

A microfluidic device integrating dual CMOS polysilicon nanowire sensors for on-chip whole blood processing and simultaneous detection of multiple analytes.

PubMed

Kuan, Da-Han; Wang, I-Shun; Lin, Jiun-Rue; Yang, Chao-Han; Huang, Chi-Hsien; Lin, Yen-Hung; Lin, Chih-Ting; Huang, Nien-Tsu

2016-08-02

The hemoglobin-A1c test, measuring the ratio of glycated hemoglobin (HbA1c) to hemoglobin (Hb) levels, has been a standard assay in diabetes diagnosis that removes the day-to-day glucose level variation. Currently, the HbA1c test is restricted to hospitals and central laboratories due to the laborious, time-consuming whole blood processing and bulky instruments. In this paper, we have developed a microfluidic device integrating dual CMOS polysilicon nanowire sensors (MINS) for on-chip whole blood processing and simultaneous detection of multiple analytes. The micromachined polymethylmethacrylate (PMMA) microfluidic device consisted of a serpentine microchannel with multiple dam structures designed for non-lysed cells or debris trapping, uniform plasma/buffer mixing and dilution. The CMOS-fabricated polysilicon nanowire sensors integrated with the microfluidic device were designed for the simultaneous, label-free electrical detection of multiple analytes. Our study first measured the Hb and HbA1c levels in 11 clinical samples via these nanowire sensors. The results were compared with those of standard Hb and HbA1c measurement methods (Hb: the sodium lauryl sulfate hemoglobin detection method; HbA1c: cation-exchange high-performance liquid chromatography) and showed comparable outcomes. Finally, we successfully demonstrated the efficacy of the MINS device's on-chip whole blood processing followed by simultaneous Hb and HbA1c measurement in a clinical sample. Compared to current Hb and HbA1c sensing instruments, the MINS platform is compact and can simultaneously detect two analytes with only 5 μL of whole blood, which corresponds to a 300-fold blood volume reduction. The total assay time, including the in situ sample processing and analyte detection, was just 30 minutes. Based on its on-chip whole blood processing and simultaneous multiple analyte detection functionalities with a lower sample volume requirement and shorter process time, the MINS device can be effectively applied to real-time diabetes diagnostics and monitoring in point-of-care settings.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Fundamental performance differences of CMOS and CCD imagers: part V

NASA Astrophysics Data System (ADS)

Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

2013-02-01

Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

A Low Cost Rad-Tolerant Standard Cell Library

NASA Technical Reports Server (NTRS)

Gambles, Jody W.; Maki, Gary K.

1997-01-01

This paper describes circuit design techniques developed at the NASA Institute of Advanced Microelectronics that have been shown to protect CMOS circuits from the deleterious effects of the natural space radiation environment. The IAuE is leading a program to incorporate these radiation-tolerance providing design techniques into a commercial standard cell library that will be used in conjunction with available Electronic Design Automation tools to produce space flight qualified microelectronics fabricated at modern commercial CMOS foundries.

1024-Pixel CMOS Multimodality Joint Cellular Sensor/Stimulator Array for Real-Time Holistic Cellular Characterization and Cell-Based Drug Screening.

PubMed

Park, Jong Seok; Aziz, Moez Karim; Li, Sensen; Chi, Taiyun; Grijalva, Sandra Ivonne; Sung, Jung Hoon; Cho, Hee Cheol; Wang, Hua

2018-02-01

This paper presents a fully integrated CMOS multimodality joint sensor/stimulator array with 1024 pixels for real-time holistic cellular characterization and drug screening. The proposed system consists of four pixel groups and four parallel signal-conditioning blocks. Every pixel group contains 16 × 16 pixels, and each pixel includes one gold-plated electrode, four photodiodes, and in-pixel circuits, within a pixel footprint. Each pixel supports real-time extracellular potential recording, optical detection, charge-balanced biphasic current stimulation, and cellular impedance measurement for the same cellular sample. The proposed system is fabricated in a standard 130-nm CMOS process. Rat cardiomyocytes are successfully cultured on-chip. Measured high-resolution optical opacity images, extracellular potential recordings, biphasic current stimulations, and cellular impedance images demonstrate the unique advantages of the system for holistic cell characterization and drug screening. Furthermore, this paper demonstrates the use of optical detection on the on-chip cultured cardiomyocytes to real-time track their cyclic beating pattern and beating rate.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

Analysis of the resistive network in a bio-inspired CMOS vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

A highly efficient CMOS nanoplasmonic crystal enhanced slow-wave thermal emitter improves infrared gas-sensing devices

PubMed Central

Pusch, Andreas; De Luca, Andrea; Oh, Sang S.; Wuestner, Sebastian; Roschuk, Tyler; Chen, Yiguo; Boual, Sophie; Ali, Zeeshan; Phillips, Chris C.; Hong, Minghui; Maier, Stefan A.; Udrea, Florin; Hopper, Richard H.; Hess, Ortwin

2015-01-01

The application of plasmonics to thermal emitters is generally assisted by absorptive losses in the metal because Kirchhoff’s law prescribes that only good absorbers make good thermal emitters. Based on a designed plasmonic crystal and exploiting a slow-wave lattice resonance and spontaneous thermal plasmon emission, we engineer a tungsten-based thermal emitter, fabricated in an industrial CMOS process, and demonstrate its markedly improved practical use in a prototype non-dispersive infrared (NDIR) gas-sensing device. We show that the emission intensity of the thermal emitter at the CO2 absorption wavelength is enhanced almost 4-fold compared to a standard non-plasmonic emitter, which enables a proportionate increase in the signal-to-noise ratio of the CO2 gas sensor. PMID:26639902

Photo-Spectrometer Realized In A Standard Cmos Ic Process

DOEpatents

Simpson, Michael L.; Ericson, M. Nance; Dress, William B.; Jellison, Gerald E.; Sitter, Jr., David N.; Wintenberg, Alan L.

1999-10-12

A spectrometer, comprises: a semiconductor having a silicon substrate, the substrate having integrally formed thereon a plurality of layers forming photo diodes, each of the photo diodes having an independent spectral response to an input spectra within a spectral range of the semiconductor and each of the photo diodes formed only from at least one of the plurality of layers of the semiconductor above the substrate; and, a signal processing circuit for modifying signals from the photo diodes with respective weights, the weighted signals being representative of a specific spectral response. The photo diodes have different junction depths and different polycrystalline silicon and oxide coverings. The signal processing circuit applies the respective weights and sums the weighted signals. In a corresponding method, a spectrometer is manufactured by manipulating only the standard masks, materials and fabrication steps of standard semiconductor processing, and integrating the spectrometer with a signal processing circuit.

Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

PubMed Central

Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

2010-01-01

This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

NASA Astrophysics Data System (ADS)

Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

2013-07-01

In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

A CMOS high speed imaging system design based on FPGA

NASA Astrophysics Data System (ADS)

Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

2015-10-01

CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

Advancement of CMOS Doping Technology in an External Development Framework

NASA Astrophysics Data System (ADS)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Comparative study of various pixel photodiodes for digital radiography: Junction structure, corner shape and noble window opening

NASA Astrophysics Data System (ADS)

Kang, Dong-Uk; Cho, Minsik; Lee, Dae Hee; Yoo, Hyunjun; Kim, Myung Soo; Bae, Jun Hyung; Kim, Hyoungtaek; Kim, Jongyul; Kim, Hyunduk; Cho, Gyuseong

2012-05-01

Recently, large-size 3-transistors (3-Tr) active pixel complementary metal-oxide silicon (CMOS) image sensors have been being used for medium-size digital X-ray radiography, such as dental computed tomography (CT), mammography and nondestructive testing (NDT) for consumer products. We designed and fabricated 50 µm × 50 µm 3-Tr test pixels having a pixel photodiode with various structures and shapes by using the TSMC 0.25-m standard CMOS process to compare their optical characteristics. The pixel photodiode output was continuously sampled while a test pixel was continuously illuminated by using 550-nm light at a constant intensity. The measurement was repeated 300 times for each test pixel to obtain reliable results on the mean and the variance of the pixel output at each sampling time. The sampling rate was 50 kHz, and the reset period was 200 msec. To estimate the conversion gain, we used the mean-variance method. From the measured results, the n-well/p-substrate photodiode, among 3 photodiode structures available in a standard CMOS process, showed the best performance at a low illumination equivalent to the typical X-ray signal range. The quantum efficiencies of the n+/p-well, n-well/p-substrate, and n+/p-substrate photodiodes were 18.5%, 62.1%, and 51.5%, respectively. From a comparison of pixels with rounded and rectangular corners, we found that a rounded corner structure could reduce the dark current in large-size pixels. A pixel with four rounded corners showed a reduced dark current of about 200fA compared to a pixel with four rectangular corners in our pixel sample size. Photodiodes with round p-implant openings showed about 5% higher dark current, but about 34% higher sensitivities, than the conventional photodiodes.

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

PubMed

Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

2012-01-01

Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel

PubMed Central

Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

2012-01-01

Modern “smart” CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage “smart” image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel. PMID:23112588

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alloatti, L., E-mail: luca.alloatti@gmail.com; Cheian, D.; Ram, R. J.

A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

NASA Astrophysics Data System (ADS)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

Detection of Short-Waved Spin Waves in Individual Microscopic Spin-Wave Waveguides Using the Inverse Spin Hall Effect.

PubMed

Brächer, T; Fabre, M; Meyer, T; Fischer, T; Auffret, S; Boulle, O; Ebels, U; Pirro, P; Gaudin, G

2017-12-13

The miniaturization of complementary metal-oxide-semiconductor (CMOS) devices becomes increasingly difficult due to fundamental limitations and the increase of leakage currents. Large research efforts are devoted to find alternative concepts that allow for a larger data-density and lower power consumption than conventional semiconductor approaches. Spin waves have been identified as a potential technology that can complement and outperform CMOS in complex logic applications, profiting from the fact that these waves enable wave computing on the nanoscale. The practical application of spin waves, however, requires the demonstration of scalable, CMOS compatible spin-wave detection schemes in material systems compatible with standard spintronics as well as semiconductor circuitry. Here, we report on the wave-vector independent detection of short-waved spin waves with wavelengths down to 150 nm by the inverse spin Hall effect in spin-wave waveguides made from ultrathin Ta/Co 8 Fe 72 B 20 /MgO. These findings open up the path for miniaturized scalable interconnects between spin waves and CMOS and the use of ultrathin films made from standard spintronic materials in magnonics.

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

NASA Astrophysics Data System (ADS)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive electro-optic characterization of these components will be presented.

Simple BiCMOS CCCTA design and resistorless analog function realization.

PubMed

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

A UHF RFID system with on-chip-antenna tag for short range communication

NASA Astrophysics Data System (ADS)

Qi, Peng; Chun, Zhang; Xijin, Zhao; Zhihua, Wang

2015-05-01

A UHF RF identification system based on the 0.18 μm CMOS process has been developed for short range and harsh size requirement applications, which is composed of a fully integrated tag and a special reader. The whole tag chip with the antenna takes up an area of 0.36 mm2, which is smaller than other reported tags with an on-chip antenna (OCA) using the standard CMOS process. A self-defined protocol is proposed to reduce the power consumption, and minimize the size of the tag. The specialized SOC reader system consists of the RF transceiver, digital baseband, MCU and host interface. Its power consumption is about 500 mW. Measurement results show that the system's reading range is 2 mm with 20 dBm reader output power. With an inductive antenna printed on a paper substrate around the OCA tag, the reading range can be extended from several centimeters to meters, depending on the shape and size of the inductive antenna.

Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

Mechanical characterization of poly-SiGe layers for CMOS-MEMS integrated application

NASA Astrophysics Data System (ADS)

Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; Puers, Robert; De Wolf, Ingrid

2010-01-01

Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups.

Fully Integrated Linear Single Photon Avalanche Diode (SPAD) Array with Parallel Readout Circuit in a Standard 180 nm CMOS Process

NASA Astrophysics Data System (ADS)

Isaak, S.; Bull, S.; Pitter, M. C.; Harrison, Ian.

2011-05-01

This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system, and was fabricated in a UMC 0.18 μm CMOS process. A low-doped p- guard ring (t-well layer) encircling the active area to prevent the premature reverse breakdown. The array is a 16×1 parallel output SPAD array, which comprises of an active quenched SPAD circuit in each pixel with the current value being set by an external resistor RRef = 300 kΩ. The SPAD I-V response, ID was found to slowly increase until VBD was reached at excess bias voltage, Ve = 11.03 V, and then rapidly increase due to avalanche multiplication. Digital circuitry to control the SPAD array and perform the necessary data processing was designed in VHDL and implemented on a FPGA chip. At room temperature, the dark count was found to be approximately 13 KHz for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns.

Portable design rules for bulk CMOS

NASA Technical Reports Server (NTRS)

Griswold, T. W.

1982-01-01

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

3-D readout-electronics packaging for high-bandwidth massively paralleled imager

DOEpatents

Kwiatkowski, Kris; Lyke, James

2007-12-18

Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Huang, Shaoyan; Liu, Minbo

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10{sup 8} n/cm{sup 2}s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10{sup 11}, 5 × 10{sup 11}, and 1 × 10{sup 12} n/cm{sup 2}, respectively. The mean dark signal (K{sub D}), dark signal spike, dark signal non-uniformity (DSNU), noise (V{sub N}), saturation output signal voltage (V{sub S}), and dynamic rangemore » (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.« less

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Fully CMOS-compatible titanium nitride nanoantennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Briggs, Justin A., E-mail: jabriggs@stanford.edu; Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305; Naik, Gururaj V.

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements onmore » plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.« less

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2010-01-01

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n+/p-sub, n-well/p-sub and p+/n-well/p-sub. All structures were fabricated in a 0.5 μm 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated—the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 × and 1.6 × over the n+/p-sub and p+/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 × and 1.2 × improvement over the n+/p-sub and p+/n-well/p-sub diodes, respectively) while the p+/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity. PMID:20454596

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2009-07-01

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n(+)/p-sub, n-well/p-sub and p(+)/n-well/p-sub. All structures were fabricated in a 0.5 mum 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated-the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 x and 1.6 x over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 x and 1.2 x improvement over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) while the p(+)/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

NASA Technical Reports Server (NTRS)

Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

2015-01-01

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

PubMed Central

Abdulrazzaq, Bilal I.; Ibrahim, Omar J.; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md.; Lee, Lini; Halin, Izhal Abdul

2016-01-01

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. PMID:27690040

An analog gamma correction scheme for high dynamic range CMOS logarithmic image sensors.

PubMed

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-12-15

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process.

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

PubMed Central

Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

2014-01-01

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1979-01-01

Modifications and additions to the present process of making CMOS microcircuits which are designed to provide protective layers on the chip to guard against moisture and contaminants were investigated. High and low temperature Si3N4 protective layers were tested on the CMOS microcircuits and no conclusive improvements in device reliability characteristics were evidenced.

Co-integrating plasmonics with Si3N4 photonics towards a generic CMOS compatible PIC platform for high-sensitivity multi-channel biosensors: the H2020 PlasmoFab approach (Conference Presentation)

NASA Astrophysics Data System (ADS)

Tsiokos, Dimitris M.; Dabos, George; Ketzaki, Dimitra; Weeber, Jean-Claude; Markey, Laurent; Dereux, Alain; Giesecke, Anna Lena; Porschatis, Caroline; Chmielak, Bartos; Wahlbrink, Thorsten; Rochracher, Karl; Pleros, Nikos

2017-05-01

Silicon photonics meet most fabrication requirements of standard CMOS process lines encompassing the photonics-electronics consolidation vision. Despite this remarkable progress, further miniaturization of PICs for common integration with electronics and for increasing PIC functional density is bounded by the inherent diffraction limit of light imposed by optical waveguides. Instead, Surface Plasmon Polariton (SPP) waveguides can guide light at sub-wavelength scales at the metal surface providing unique light-matter interaction properties, exploiting at the same time their metallic nature to naturally integrate with electronics in high-performance ASPICs. In this article, we demonstrate the main goals of the recently introduced H2020 project PlasmoFab towards addressing the ever increasing needs for low energy, small size and high performance mass manufactured PICs by developing a revolutionary yet CMOS-compatible fabrication platform for seamless co-integration of plasmonics with photonic and supporting electronic. We demonstrate recent advances on the hosting SiN photonic hosting platform reporting on low-loss passive SiN waveguide and Grating Coupler circuits for both the TM and TE polarization states. We also present experimental results of plasmonic gold thin-film and hybrid slot waveguide configurations that can allow for high-sensitivity sensing, providing also the ongoing activities towards replacing gold with Cu, Al or TiN metal in order to yield the same functionality over a CMOS metallic structure. Finally, the first experimental results on the co-integrated SiN+plasmonic platform are demonstrated, concluding to an initial theoretical performance analysis of the CMOS plasmo-photonic biosensor that has the potential to allow for sensitivities beyond 150000nm/RIU.

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

PubMed Central

Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

2009-01-01

We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

Prediction and measurement of radiation damage to CMOS devices on board spacecraft

NASA Technical Reports Server (NTRS)

Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1976-01-01

The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

A new physical unclonable function architecture

NASA Astrophysics Data System (ADS)

Chuang, Bai; Xuecheng, Zou; Kui, Dai

2015-03-01

This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabricated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier, comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical characteristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 μm CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from -40 to 100 °C, and supply voltage variation from 1.7 to 1.9 V. Project supported by the National Natural Science Foundation of China (No. 61376031).

Investigation on thermodynamics of ion-slicing of GaN and heterogeneously integrating high-quality GaN films on CMOS compatible Si(100) substrates.

PubMed

Huang, Kai; Jia, Qi; You, Tiangui; Zhang, Runchun; Lin, Jiajie; Zhang, Shibin; Zhou, Min; Zhang, Bo; Yu, Wenjie; Ou, Xin; Wang, Xi

2017-11-08

Die-to-wafer heterogeneous integration of single-crystalline GaN film with CMOS compatible Si(100) substrate using the ion-cutting technique has been demonstrated. The thermodynamics of GaN surface blistering is in-situ investigated via a thermal-stage optical microscopy, which indicates that the large activation energy (2.5 eV) and low H ions utilization ratio (~6%) might result in the extremely high H fluence required for the ion-slicing of GaN. The crystalline quality, surface topography and the microstructure of the GaN films are characterized in detail. The full width at half maximum (FWHM) for GaN (002) X-ray rocking curves is as low as 163 arcsec, corresponding to a density of threading dislocation of 5 × 10 7  cm -2 . Different evolution of the implantation-induced damage was observed and a relationship between the damage evolution and implantation-induced damage is demonstrated. This work would be beneficial to understand the mechanism of ion-slicing of GaN and to provide a platform for the hybrid integration of GaN devices with standard Si CMOS process.

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

NASA Astrophysics Data System (ADS)

Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

2016-05-01

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from -40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

Behavioral Model of Spin-Transfer Torque Driven Oscillation in a Nanomagnet

NASA Astrophysics Data System (ADS)

Buford, Benjamin; Jander, Albrecht; Dhagat, Pallavi

2011-10-01

We present a model written in Verilog-A, a behavioral description language, for spin-torque driven oscillations in a nanomagnet. Recent experiments have shown that spin-polarized current passing through a nanomagnet can cause magnetic dynamics from transfer of spin angular momentum. This can result in steady state oscillation of the magnetization at microwave frequencies [1]. Such spin torque oscillators are of interest due to the ability to rapidly tune their operating frequency by adjusting the applied magnetic field and their compatibility with existing CMOS fabrication methods. Our model is based upon the Landau-Lifshitz-Gilbert dynamics of a single- domain nanomagnet [2] and includes thermal agitation. We demonstrate the ability to model small angle, large angle, and out-of-plane precession. Additionally, we characterize the field and current boundaries between these regimes. Our Verilog-A model can be used in industry standard simulation tools alongside CMOS device models to simulate circuits that combine spintronic devices with CMOS control and processing circuitry. [4pt] [1] S. I. Kiselev et al., Nature, Vol. 425, pp. 380(3), (2003). [0pt] [2] L. Engelbrecht, Ph.D. Dissertation, Dept. Elect. Eng., Oregon State Univ., Corvallis, OR, (2011).

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

PubMed Central

Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

2016-01-01

An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

Wobbly strings: calculating the capture rate of a webcam using the rolling shutter effect in a guitar

NASA Astrophysics Data System (ADS)

Cunnah, David

2014-07-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

Gyroscope and Micromirror Design Using Vertical-Axis CMOS-MEMS Actuation and Sensing

DTIC Science & Technology

2002-01-01

Interference pattern around the upper anchor (each fringe occurs at 310 nm vertical displacement...described above require extra lithography step(s) other than standard CMOS lithography steps and/or deposition of structural and sacrificial materials...Instruments’ dig- ital mirror device ( DMD ) [43]. The aluminum thin-film technology with vertical parallel- plate actuation has difficulty in achieving

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Wobbly Strings: Calculating the Capture Rate of a Webcam Using the Rolling Shutter Effect in a Guitar

ERIC Educational Resources Information Center

Cunnah, David

2014-01-01

In this paper I propose a method of calculating the time between line captures in a standard complementary metal-oxide-semiconductor (CMOS) webcam using the rolling shutter effect when filming a guitar. The exercise links the concepts of wavelength and frequency, while outlining the basic operation of a CMOS camera through vertical line capture.

Study Casts Doubt on Strength of Charter Managers: Author Says Final Text Eased Negative Findings on CMOs

ERIC Educational Resources Information Center

Viadero, Debra

2009-01-01

A report from Education Sector raises questions about the ability of charter schools and charter-management organizations (CMOs) to scale up as dramatically as their supporters might hope. "The extraordinary demands of educating disadvantaged students to higher standards, the challenges of attracting the talent required to do that work, the burden…

A CMOS-based high-resolution fluoroscope (HRF) detector prototype with 49.5μm pixels for use in endovascular image guided interventions (EIGI)

NASA Astrophysics Data System (ADS)

Russ, M.; Shankar, A.; Setlur Nagesh, S. V.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

2017-03-01

X-ray detectors to meet the high-resolution requirements for endovascular image-guided interventions (EIGIs) are being developed and evaluated. A new 49.5-micron pixel prototype detector is being investigated and compared to the current suite of high-resolution fluoroscopic (HRF) detectors. This detector featuring a 300-micron thick CsI(Tl) scintillator, and low electronic noise CMOS readout is designated the HRF- CMOS50. To compare the abilities of this detector with other existing high resolution detectors, a standard performance metric analysis was applied, including the determination of the modulation transfer function (MTF), noise power spectra (NPS), noise equivalent quanta (NEQ), and detective quantum efficiency (DQE) for a range of energies and exposure levels. The advantage of the smaller pixel size and reduced blurring due to the thin phosphor was exemplified when the MTF of the HRF-CMOS50 was compared to the other high resolution detectors, which utilize larger pixels, other optical designs or thicker scintillators. However, the thinner scintillator has the disadvantage of a lower quantum detective efficiency (QDE) for higher diagnostic x-ray energies. The performance of the detector as part of an imaging chain was examined by employing the generalized metrics GMTF, GNEQ, and GDQE, taking standard focal spot size and clinical imaging parameters into consideration. As expected, the disparaging effects of focal spot unsharpness, exacerbated by increasing magnification, degraded the higher-frequency performance of the HRF-CMOS50, while increasing scatter fraction diminished low-frequency performance. Nevertheless, the HRF-CMOS50 brings improved resolution capabilities for EIGIs, but would require increased sensitivity and dynamic range for future clinical application.

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Drop casting of stiffness gradients for chip integration into stretchable substrates

NASA Astrophysics Data System (ADS)

Naserifar, Naser; LeDuc, Philip R.; Fedder, Gary K.

2017-04-01

Stretchable electronics have demonstrated promise within unobtrusive wearable systems in areas such as health monitoring and medical therapy. One significant question is whether it is more advantageous to develop holistic stretchable electronics or to integrate mature CMOS into stretchable electronic substrates where the CMOS process is separated from the mechanical processing steps. A major limitation with integrating CMOS is the dissimilar interface between the soft stretchable and hard CMOS materials. To address this, we developed an approach to pattern an elastomeric polymer layer with spatially varying mechanical properties around CMOS electronics to create a controllable material stiffness gradient. Our experimental approach reveals that modifying the interfaces can increase the strain failure threshold up to 30% and subsequently decreases delamination. The stiffness gradient in the polymer layer provides a safe region for electronic chips to function under a substrate tensile strain up to 150%. These results will have impacts in diverse applications including skin sensors and wearable health monitoring systems.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

SRAM As An Array Of Energetic-Ion Detectors

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Lieneweg, Udo; Nixon, Robert H.

1993-01-01

Static random-access memory (SRAM) designed for use as array of energetic-ion detectors. Exploits well-known tendency of incident energetic ions to cause bit flips in cells of electronic memories. Design of ion-detector SRAM involves modifications of standard SRAM design to increase sensitivity to ions. Device fabricated by use of conventional complementary metal oxide/semiconductor (CMOS) processes. Potential uses include gas densimetry, position sensing, and measurement of cosmic-ray spectrum.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-11-01

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement

NASA Astrophysics Data System (ADS)

Vornicu, I.; Carmona-Galán, R.; Rodríguez-Vázquez, Á.

2015-03-01

The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reverse start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.

Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

PubMed

Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

2015-07-10

This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH.

Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

PubMed Central

Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

2015-01-01

This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly measures humidity in % RH. PMID:26184204

Test results for SEU and SEL immune memory circuits

NASA Technical Reports Server (NTRS)

Wiseman, D.; Canaris, J.; Whitaker, S.; Gambles, J.; Arave, K.; Arave, L.

1993-01-01

Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

NASA Astrophysics Data System (ADS)

Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

2004-06-01

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

NASA Astrophysics Data System (ADS)

Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

2009-05-01

This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF<2.8dB, S21>13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

Quantitative evaluation of the accuracy and variance of individual pixels in a scientific CMOS (sCMOS) camera for computational imaging

NASA Astrophysics Data System (ADS)

Watanabe, Shigeo; Takahashi, Teruo; Bennett, Keith

2017-02-01

The"scientific" CMOS (sCMOS) camera architecture fundamentally differs from CCD and EMCCD cameras. In digital CCD and EMCCD cameras, conversion from charge to the digital output is generally through a single electronic chain, and the read noise and the conversion factor from photoelectrons to digital outputs are highly uniform for all pixels, although quantum efficiency may spatially vary. In CMOS cameras, the charge to voltage conversion is separate for each pixel and each column has independent amplifiers and analog-to-digital converters, in addition to possible pixel-to-pixel variation in quantum efficiency. The "raw" output from the CMOS image sensor includes pixel-to-pixel variability in the read noise, electronic gain, offset and dark current. Scientific camera manufacturers digitally compensate the raw signal from the CMOS image sensors to provide usable images. Statistical noise in images, unless properly modeled, can introduce errors in methods such as fluctuation correlation spectroscopy or computational imaging, for example, localization microscopy using maximum likelihood estimation. We measured the distributions and spatial maps of individual pixel offset, dark current, read noise, linearity, photoresponse non-uniformity and variance distributions of individual pixels for standard, off-the-shelf Hamamatsu ORCA-Flash4.0 V3 sCMOS cameras using highly uniform and controlled illumination conditions, from dark conditions to multiple low light levels between 20 to 1,000 photons / pixel per frame to higher light conditions. We further show that using pixel variance for flat field correction leads to errors in cameras with good factory calibration.

An integrated CMOS high voltage supply for lab-on-a-chip systems.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

2008-09-01

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip.

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

PubMed

Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

2009-01-01

The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

PubMed

Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

2016-06-01

Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

Fixed-pattern noise correction method based on improved moment matching for a TDI CMOS image sensor.

PubMed

Xu, Jiangtao; Nie, Huafeng; Nie, Kaiming; Jin, Weimin

2017-09-01

In this paper, an improved moment matching method based on a spatial correlation filter (SCF) and bilateral filter (BF) is proposed to correct the fixed-pattern noise (FPN) of a time-delay-integration CMOS image sensor (TDI-CIS). First, the values of row FPN (RFPN) and column FPN (CFPN) are estimated and added to the original image through SCF and BF, respectively. Then the filtered image will be processed by an improved moment matching method with a moving window. Experimental results based on a 128-stage TDI-CIS show that, after correcting the FPN in the image captured under uniform illumination, the standard deviation of row mean vector (SDRMV) decreases from 5.6761 LSB to 0.1948 LSB, while the standard deviation of the column mean vector (SDCMV) decreases from 15.2005 LSB to 13.1949LSB. In addition, for different images captured by different TDI-CISs, the average decrease of SDRMV and SDCMV is 5.4922/2.0357 LSB, respectively. Comparative experimental results indicate that the proposed method can effectively correct the FPNs of different TDI-CISs while maintaining image details without any auxiliary equipment.

An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2011-01-01

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm2 of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested. PMID:22174666

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness.

PubMed

Cao, Q; Brehler, M; Sisniega, A; Stayman, J W; Yorkston, J; Siewerdsen, J H; Zbijewski, W

2017-03-01

CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μ m, ~80 μ m and ~40 μ m, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μ m pixels) with CsI scintillator thicknesses of 400 μ m and 700 μ m, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6-5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μ m scintillator compared to the standard nominal CsI thickness of 700 μ m. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index ( d' 2 ) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μ m CsI compared to 700 μ m CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μ m panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μ m scinitllator. Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μ m CsI onto the clinical prototype of CMOS-based extremity CBCT.

High-resolution extremity cone-beam CT with a CMOS detector: Task-based optimization of scintillator thickness

PubMed Central

Cao, Q.; Brehler, M.; Sisniega, A.; Stayman, J. W.; Yorkston, J.; Siewerdsen, J. H.; Zbijewski, W.

2017-01-01

Purpose CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. Methods A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of ~250 μm, ~80 μm and ~40 μm, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μm pixels) with CsI scintillator thicknesses of 400 μm and 700 μm, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6–5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Results Experimental studies show ~35% improvement in the frequency of 50% MTF modulation when using the 400 μm scintillator compared to the standard nominal CsI thickness of 700 μm. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index (d′2) of high- and ultrahigh resolution tasks, respectively, for the detector with 400 μm CsI compared to 700 μm CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μm panel in the visibility of the radiographic pattern (2× improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular structures with the CMOS detector with 400 μm scinitllator. Conclusion Applications on CMOS detectors in high resolution CBCT imaging of trabecular bone will benefit from using a thinner scintillator than the current standard in general radiography. The results support the translation of the CMOS sensor with 400 μm CsI onto the clinical prototype of CMOS-based extremity CBCT. PMID:28989220

Ultrasonic Fingerprint Sensor With Transmit Beamforming Based on a PMUT Array Bonded to CMOS Circuitry.

PubMed

Jiang, Xiaoyue; Tang, Hao-Yen; Lu, Yipeng; Ng, Eldwin J; Tsai, Julius M; Boser, Bernhard E; Horsley, David A

2017-09-01

In this paper, we present a single-chip 65 ×42 element ultrasonic pulse-echo fingerprint sensor with transmit (TX) beamforming based on piezoelectric micromachined ultrasonic transducers directly bonded to a CMOS readout application-specific integrated circuit (ASIC). The readout ASIC was realized in a standard 180-nm CMOS process with a 24-V high-voltage transistor option. Pulse-echo measurements are performed column-by-column in sequence using either one column or five columns to TX the ultrasonic pulse at 20 MHz. TX beamforming is used to focus the ultrasonic beam at the imaging plane where the finger is located, increasing the ultrasonic pressure and narrowing the 3-dB beamwidth to [Formula: see text], a factor of 6.4 narrower than nonbeamformed measurements. The surface of the sensor is coated with a poly-dimethylsiloxane (PDMS) layer to provide good acoustic impedance matching to skin. Scanning laser Doppler vibrometry of the PDMS surface was used to map the ultrasonic pressure field at the imaging surface, demonstrating the expected increase in pressure, and reduction in beamwidth. Imaging experiments were conducted using both PDMS phantoms and real fingerprints. The average image contrast is increased by a factor of 1.5 when beamforming is used.

Flip-chip fabrication of integrated micromirror arrays using a novel latching off-chip hinge mechanism

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, fabrication, modeling, and testing of various arrays of cantilever micromirror devices integrated atop CMOS control electronics. The upper layers of the arrays are prefabricated in the MUMPs process and then flip-chip transferred to CMOS receiving modules using a novel latching off-chip hinge mechanism. This mechanism allows the micromirror arrays to be released, rotated off the edge of the host module and then bonded to the receiving module using a standard probe station. The hinge mechanism supports the arrays by tethers that are severed to free the arrays once bonded. The resulting devices are inherently planarized since the bottom of the first releasable MUMPs layer becomes the surface of the integrated mirror. The working devices are formed by mirror surfaces bonded to address electrodes fabricated above static memory cells on the CMOS module. These arrays demonstrate highly desirable features such as compatible address potentials, less than 2 nm of RMS roughness, approximately 1 micrometers of lateral position accuracy and the unique ability to metallize reflective surfaces without masking. Ultimately, the off-chip hinge mechanism enables very low-cost, simple, reliable, repeatable and accurate assembly of advanced MEMS and integrated microsystems without specialized equipment or complex procedures.

A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2014-01-01

In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std. CMOS process, occupying 0.144 mm2 of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages. PMID:23853321

1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.

PubMed

Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

2010-01-01

This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications.

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

Advanced ROICs design for cooled IR detectors

NASA Astrophysics Data System (ADS)

Zécri, Michel; Maillart, Patrick; Sanson, Eric; Decaens, Gilbert; Lefoul, Xavier; Baud, Laurent

2008-04-01

The CMOS silicon focal plan array technologies hybridized with infrared detectors materials allow to cover a wide range of applications in the field of space, airborne and grounded-based imaging. Regarding other industries which are also using embedded systems, the requirements of such sensor assembly can be seen as very similar; high reliability, low weight, low power, radiation hardness for space applications and cost reduction. Comparing to CCDs technology, excepted the fact that CMOS fabrication uses standard commercial semiconductor foundry, the interest of this technology used in cooled IR sensors is its capability to operate in a wide range of temperature from 300K to cryogenic with a high density of integration and keeping at the same time good performances in term of frequency, noise and power consumption. The CMOS technology roadmap predict aggressive scaling down of device size, transistor threshold voltage, oxide and metal thicknesses to meet the growing demands for higher levels of integration and performance. At the same time infrared detectors manufacturing process is developing IR materials with a tunable cut-off wavelength capable to cover bandwidths from visible to 20μm. The requirements of third generation IR detectors are driving to scaling down the pixel pitch, to develop IR materials with high uniformity on larger formats, to develop Avalanche Photo Diodes (APD) and dual band technologies. These needs in IR detectors technologies developments associated to CMOS technology, used as a readout element, are offering new capabilities and new opportunities for cooled infrared FPAs. The exponential increase of new functionalities on chip, like the active 2D and 3D imaging, the on chip analog to digital conversion, the signal processing on chip, the bicolor, the dual band and DTI (Double Time Integration) mode ...is aiming to enlarge the field of application for cooled IR FPAs challenging by the way the design activity.

Progress on uncooled PbSe detectors for low-cost applications

NASA Astrophysics Data System (ADS)

Vergara, German; Gomez, Luis J.; Villamayor, Victor; Alvarez, M.; Rodrigo, Maria T.; del Carmen Torquemada, Maria; Sanchez, Fernando J.; Verdu, Marina; Diezhandino, Jorge; Rodriguez, Purificacion; Catalan, Irene; Almazan, Rosa; Plaza, Julio; Montojo, Maria T.

2004-08-01

This work reports on progress on development of polycrystalline PbSe infrared detectors at the Centro de Investigacion y Desarrollo de la Armada (CIDA). Since mid nineties, the CIDA owns an innovative technology for processing uncooled MWIR detectors of polycrystalline PbSe. Based on this technology, some applications have been developed. However, future applications demand smarter, more complex, faster yet cheaper detectors. Aiming to open new perspectives to polycrystalline PbSe detectors, we are currently working on different directions: 1) Processing of 2D arrays: a) Designing and processing low density x-y addressed arrays with 16x16 and 32x32 elements, as an extension of our standard technology. b) Trying to make compatible standard CMOS and polycrystalline PbSe technologies in order to process monolithic large format arrays. 2) Adding new features to the detector such as monolithically integrated spectral discrimination.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

NASA Astrophysics Data System (ADS)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of circulator shows how crucial this device is to many industries and the need for smaller, cost effective RF components.

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

NASA Astrophysics Data System (ADS)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

CMOS-compatible photonic devices for single-photon generation

NASA Astrophysics Data System (ADS)

Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

2016-09-01

Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Overlap junctions for high coherence superconducting qubits

NASA Astrophysics Data System (ADS)

Wu, X.; Long, J. L.; Ku, H. S.; Lake, R. E.; Bal, M.; Pappas, D. P.

2017-07-01

Fabrication of sub-micron Josephson junctions is demonstrated using standard processing techniques for high-coherence, superconducting qubits. These junctions are made in two separate lithography steps with normal-angle evaporation. Most significantly, this work demonstrates that it is possible to achieve high coherence with junctions formed on aluminum surfaces cleaned in situ by Ar plasma before junction oxidation. This method eliminates the angle-dependent shadow masks typically used for small junctions. Therefore, this is conducive to the implementation of typical methods for improving margins and yield using conventional CMOS processing. The current method uses electron-beam lithography and an additive process to define the top and bottom electrodes. Extension of this work to optical lithography and subtractive processes is discussed.

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

NASA Astrophysics Data System (ADS)

Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

2013-12-01

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

Nonvolatile programmable neural network synaptic array

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1994-01-01

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

DNA decorated carbon nanotube sensors on CMOS circuitry for environmental monitoring

NASA Astrophysics Data System (ADS)

Liu, Yu; Chen, Chia-Ling; Agarwal, V.; Li, Xinghui; Sonkusale, S.; Dokmeci, Mehmet R.; Wang, Ming L.

2010-04-01

Single-walled carbon nanotubes (SWNTs) with their large surface area, high aspect ratio are one of the novel materials which have numerous attractive features amenable for high sensitivity sensors. Several nanotube based sensors including, gas, chemical and biosensors have been demonstrated. Moreover, most of these sensors require off chip components to detect the variations in the signals making them complicated and hard to commercialize. Here we present a novel complementary metal oxide semiconductor (CMOS) integrated carbon nanotube sensors for portable high sensitivity chemical sensing applications. Multiple zincation steps have been developed to ascertain proper electrical connectivity between the carbon nanotubes and the foundry made CMOS circuitry. The SWNTs have been integrated onto (CMOS) circuitry as the feedback resistor of a Miller compensated operational amplifier utilizing low temperature Dielectrophoretic (DEP) assembly process which has been tailored to be compatible with the post-CMOS integration at the die level. Building nanotube sensors directly on commercial CMOS circuitry allows single chip solutions eliminating the need for long parasitic lines and numerous wire bonds. The carbon nanotube sensors realized on CMOS circuitry show strong response to various vapors including Dimethyl methylphosphonate and Dinitrotoluene. The remarkable set of attributes of the SWNTs realized on CMOS electronic chips provides an attractive platform for high sensitivity portable nanotube based bio and chemical sensors.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly.

PubMed

Gall, Oren Z; Zhong, Xiahua; Schulman, Daniel S; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S

2017-06-30

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO 2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly

NASA Astrophysics Data System (ADS)

Gall, Oren Z.; Zhong, Xiahua; Schulman, Daniel S.; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S.

2017-06-01

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Theoretical performance analysis for CMOS based high resolution detectors.

PubMed

Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

2013-03-06

High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

Improved Space Object Observation Techniques Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

2013-08-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

SiGe BiCMOS manufacturing platform for mmWave applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

2010-10-01

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

Characterisation results of the CMOS VISNIR spectral band detector for the METimage instrument

NASA Astrophysics Data System (ADS)

Pratlong, Jérôme; Schmuelling, Frank; Benitez, Victor; Breart De Boisanger, Michel; Skegg, Michael; Simpson, Robert; Bowring, Steve; Krzizok, Natalie

2017-09-01

The METimage instrument is part of the EPS-SG (EUMETSAT Polar System Second Generation) program. It will be situated on the MetOp-SG platform which in operation has an objective of collecting data for meteorology and climate monitoring as well as their forecasting. Teledyne e2v has developed and characterised the CMOS VISNIR detector flight module part of the METimage instrument. This paper will focus on the silicon results obtained from the CMOS VISNIR detector flight model. The detector is a large multi-linear device composed of 7 spectral bands covering a wavelength range from 428 nm to 923 nm (some bands are placed twice and added together to enhance the signal-to-noise performance). This detector uses a 4T pixel, with a size of 250μm square, presenting challenges to achieve good charge transfer efficiency with high conversion factor and good linearity for signal levels up to 2M electrons and with high line rates. Low noise has been achieved using correlated double sampling to suppress the read-out noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. The photodiode occupies a significant fraction of the large pixel area. This makes it possible to meet the detection efficiency when front illuminated. A thicker than standard epitaxial silicon is used to improve NIR response. However, the dielectric stack on top of the sensor produces Fabry-Perot étalon effects, which are problematic for narrow band illumination as this causes the detection efficiency to vary significantly over a small wavelength range. In order to reduce this effect and to meet the specification, the silicon manufacturing process has been modified. The flight model will have black coating deposited between each spectral channel, onto the active silicon regions.

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

CMOS sensors for atmospheric imaging

NASA Astrophysics Data System (ADS)

Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

2017-09-01

Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the required optical performance and this has driven the development of a black coating layer that can be applied between the active silicon regions.

A Hybrid CMOS-Memristor Neuromorphic Synapse.

PubMed

Azghadi, Mostafa Rahimi; Linares-Barranco, Bernabe; Abbott, Derek; Leong, Philip H W

2017-04-01

Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper proposes a high-performance nano-scale Complementary Metal Oxide Semiconductor (CMOS)-memristive circuit, which mimics a number of essential learning properties of biological synapses. The proposed synaptic circuit that is composed of memristors and CMOS transistors, alters its memristance in response to timing differences among its pre- and post-synaptic action potentials, giving rise to a family of Spike Timing Dependent Plasticity (STDP). The presented design advances preceding memristive synapse designs with regards to the ability to replicate essential behaviours characterised in a number of electrophysiological experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid device CMOS area is estimated as [Formula: see text] in a [Formula: see text] process-this represents a factor of ten reduction in area with respect to prior CMOS art. The new design is integrated with silicon neurons in a crossbar array structure amenable to large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent learning features. These systems are emerging for deployment in various applications ranging from basic neuroscience research, to pattern recognition, to Brain-Machine-Interfaces.

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

PubMed Central

Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

2007-01-01

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Fully depleted CMOS pixel sensor development and potential applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baudot, J.; Kachel, M.; CNRS, UMR7178, 67037 Strasbourg

CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) highmore » resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a low noise figure. Especially, an energy resolution of about 400 eV for 5 keV X-rays was obtained for single pixels. The prototypes have then been exposed to gradually increased fluences of neutrons, from 10{sup 13} to 5x10{sup 14} neq/cm{sup 2}. Again laboratory tests allowed to evaluate the signal over noise persistence on the different pixels implemented. Currently our development mostly targets the detection of soft X-rays, with the ambition to develop a pixel sensor matching counting rates as affordable with hybrid pixel sensors, but with an extended sensitivity to low energy and finer pixel about 25 x 25 μm{sup 2}. The original readout architecture proposed relies on a two tiers chip. The first tier consists of a sensor with a modest dynamic in order to insure low noise performances required by sensitivity. The interconnected second tier chip enhances the read-out speed by introducing massive parallelization. Performances reachable with this strategy combining counting and integration will be detailed. (authors)« less

A novel wireless power and data transmission AC to DC converter for an implantable device.

PubMed

Liu, Jhao-Yan; Tang, Kea-Tiong

2013-01-01

This article presents a novel AC to DC converter implemented by standard CMOS technology, applied for wireless power transmission. This circuit combines the functions of the rectifier and DC to DC converter, rather than using the rectifier to convert AC to DC and then supplying the required voltage with regulator as in the transitional method. This modification can reduce the power consumption and the area of the circuit. This circuit also transfers the loading condition back to the external circuit by the load shift keying(LSK), determining if the input power is not enough or excessive, which increases the efficiency of the total system. The AC to DC converter is fabricated with the TSMC 90nm CMOS process. The circuit area is 0.071mm(2). The circuit can produce a 1V DC voltage with maximum output current of 10mA from an AC input ranging from 1.5V to 2V, at 1MHz to 10MHz.

Jitter and phase noise of ADPLL due to PSN with deterministic frequency

NASA Astrophysics Data System (ADS)

Deng, Xiaoying; Yang, Jun; Wu, Jianhui

2011-09-01

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13 µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100 mVpk-pk, the measured jitters were 33.9 ps at the rate of fG = 192 MHz and 148.5 ps at the rate of fG = 40 MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40 MHz, respectively.

A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

NASA Astrophysics Data System (ADS)

Yijun, Song; Wenyuan, Li

2014-06-01

A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 μm CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which canperform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within ±0.28 LSB and ±0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 mW.

Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

PubMed

Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

2017-10-02

Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

First light from a very large area pixel array for high-throughput x-ray polarimetry

NASA Astrophysics Data System (ADS)

Bellazzini, R.; Spandre, G.; Minuti, M.; Baldini, L.; Brez, A.; Cavalca, F.; Latronico, L.; Omodei, N.; Massai, M. M.; Sgrò, C.; Costa, E.; Soffitta, P.; Krummenacher, F.; de Oliveira, R.

2006-06-01

We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50μm pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and single poly-silicon layers of a standard 0.18μm CMOS VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The very small pixel area and the use of a deep sub-micron CMOS technology has brought the noise down to 50 electrons ENC. Results from in depth tests of this device when coupled to a fine pitch (50μm on a triangular pattern) Gas Electron Multiplier are presented. The matching of readout and gas amplification pitch allows getting optimal results. The application of this detector for Astronomical X-Ray Polarimetry is discussed. The experimental detector response to polarized and unpolarized X-ray radiation when working with two gas mixtures and two different photon energies is shown. Results from a full MonteCarlo simulation for several galactic and extragalactic astronomical sources are also reported.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

Design of CMOS imaging system based on FPGA

NASA Astrophysics Data System (ADS)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

PubMed

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A CMOS image sensor with stacked photodiodes for lensless observation system of digital enzyme-linked immunosorbent assay

NASA Astrophysics Data System (ADS)

Takehara, Hironari; Miyazawa, Kazuya; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Kim, Soo Hyeon; Iino, Ryota; Noji, Hiroyuki; Ohta, Jun

2014-01-01

A CMOS image sensor with stacked photodiodes was fabricated using 0.18 µm mixed signal CMOS process technology. Two photodiodes were stacked at the same position of each pixel of the CMOS image sensor. The stacked photodiodes consist of shallow high-concentration N-type layer (N+), P-type well (PW), deep N-type well (DNW), and P-type substrate (P-sub). PW and P-sub were shorted to ground. By monitoring the voltage of N+ and DNW individually, we can observe two monochromatic colors simultaneously without using any color filters. The CMOS image sensor is suitable for fluorescence imaging, especially contact imaging such as a lensless observation system of digital enzyme-linked immunosorbent assay (ELISA). Since the fluorescence increases with time in digital ELISA, it is possible to observe fluorescence accurately by calculating the difference from the initial relation between the pixel values for both photodiodes.

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Hofbauer, M; Zimmermann, H

2012-08-01

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm 2 and 100 × 100 μm 2 . Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

NASA Astrophysics Data System (ADS)

Aytar, Oktay; Tangel, Ali; Afacan, Engin

2017-11-01

This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/-0.22 LSB of DNL and +0.01/-0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

An integrated low phase noise radiation-pressure-driven optomechanical oscillator chipset

PubMed Central

Luan, Xingsheng; Huang, Yongjun; Li, Ying; McMillan, James F.; Zheng, Jiangjun; Huang, Shu-Wei; Hsieh, Pin-Chun; Gu, Tingyi; Wang, Di; Hati, Archita; Howe, David A.; Wen, Guangjun; Yu, Mingbin; Lo, Guoqiang; Kwong, Dim-Lee; Wong, Chee Wei

2014-01-01

High-quality frequency references are the cornerstones in position, navigation and timing applications of both scientific and commercial domains. Optomechanical oscillators, with direct coupling to continuous-wave light and non-material-limited f × Q product, are long regarded as a potential platform for frequency reference in radio-frequency-photonic architectures. However, one major challenge is the compatibility with standard CMOS fabrication processes while maintaining optomechanical high quality performance. Here we demonstrate the monolithic integration of photonic crystal optomechanical oscillators and on-chip high speed Ge detectors based on the silicon CMOS platform. With the generation of both high harmonics (up to 59th order) and subharmonics (down to 1/4), our chipset provides multiple frequency tones for applications in both frequency multipliers and dividers. The phase noise is measured down to −125 dBc/Hz at 10 kHz offset at ~400 μW dropped-in powers, one of the lowest noise optomechanical oscillators to date and in room-temperature and atmospheric non-vacuum operating conditions. These characteristics enable optomechanical oscillators as a frequency reference platform for radio-frequency-photonic information processing. PMID:25354711

Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

PubMed

Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

2015-02-01

An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

Portable fiber-optic taper coupled optical microscopy platform

NASA Astrophysics Data System (ADS)

Wang, Weiming; Yu, Yan; Huang, Hui; Ou, Jinping

2017-04-01

The optical fiber taper coupled with CMOS has advantages of high sensitivity, compact structure and low distortion in the imaging platform. So it is widely used in low light, high speed and X-ray imaging systems. In the meanwhile, the peculiarity of the coupled structure can meet the needs of the demand in microscopy imaging. Toward this end, we developed a microscopic imaging platform based on the coupling of cellphone camera module and fiber optic taper for the measurement of the human blood samples and ascaris lumbricoides. The platform, weighing 70 grams, is based on the existing camera module of the smartphone and a fiber-optic array which providing a magnification factor of 6x.The top facet of the taper, on which samples are placed, serves as an irregular sampling grid for contact imaging. The magnified images of the sample, located on the bottom facet of the fiber, are then projected onto the CMOS sensor. This paper introduces the portable medical imaging system based on the optical fiber coupling with CMOS, and theoretically analyzes the feasibility of the system. The image data and process results either can be stored on the memory or transmitted to the remote medical institutions for the telemedicine. We validate the performance of this cell-phone based microscopy platform using human blood samples and test target, achieving comparable results to a standard bench-top microscope.

A 13.56 MHz CMOS Active Rectifier With Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems.

PubMed

Yan Lu; Wing-Hung Ki

2014-06-01

A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |VAC|. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm(2). For the proposed rectifier measured at |VAC| = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for RL=500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |VAC| ranges from 1.5 to 4 V for RL=500 Ω.

Macromolecular crystallography with a large format CMOS detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nix, Jay C., E-mail: jcnix@lbl.gov

Recent advances in CMOS technology have allowed the production of large surface area detectors suitable for macromolecular crystallography experiments [1]. The Molecular Biology Consortium (MBC) Beamline 4.2.2 at the Advanced Light Source in Berkeley, CA, has installed a 2952 x 2820 mm RDI CMOS-8M detector with funds from NIH grant S10OD012073. The detector has a 20nsec dead pixel time and performs well with shutterless data collection strategies. The sensor obtains sharp point response and minimal optical distortion by use of a thin fiber-optic plate between the phosphor and sensor module. Shutterless data collections produce high-quality redundant datasets that can bemore » obtained in minutes. The fine-sliced data are suitable for processing in standard crystallographic software packages (XDS, HKL2000, D*TREK, MOSFLM). Faster collection times relative to the previous CCD detector have resulted in a record number of datasets collected in a calendar year and de novo phasing experiments have resulted in publications in both Science and Nature [2,3]. The faster collections are due to a combination of the decreased overhead requirements of shutterless collections combined with exposure times that have decreased by over a factor of 2 for images with comparable signal to noise of the NOIR-1 detector. The overall increased productivity has allowed the development of new beamline capabilities and data collection strategies.« less

A CMOS merged CDR and continuous-time adaptive equalizer

NASA Astrophysics Data System (ADS)

Sánchez-Azqueta, C.; Aguirre, J.; Gimeno, C.; Aldea, C.; Celma, S.

2015-06-01

We present a low-voltage merged CDR and cntinuous-time adaptive equalizer capable to compensate the attenu- ation of a SI-POF channel while at the same time synchronizing and regenerating the incoming signal in a single stage. The system operates at 1.25 Gbps for NRZ modulation through a 50-m SI-POF channel and it is designed in standard 0.18-μm CMOS fed at 1 V with a power consumption of 43.4 mW.

An 80x80 microbolometer type thermal imaging sensor using the LWIR-band CMOS infrared (CIR) technology

NASA Astrophysics Data System (ADS)

Tankut, Firat; Cologlu, Mustafa H.; Askar, Hidir; Ozturk, Hande; Dumanli, Hilal K.; Oruc, Feyza; Tilkioglu, Bilge; Ugur, Beril; Akar, Orhan Sevket; Tepegoz, Murat; Akin, Tayfun

2017-02-01

This paper introduces an 80x80 microbolometer array with a 35 μm pixel pitch operating in the 8-12 μm wavelength range, where the detector is fabricated with the LWIR-band CMOS infrared technology, shortly named as CIR, which is a novel microbolometer implementation technique developed to reduce the detector cost in order to enable the use of microbolometer type sensors in high volume markets, such as the consumer market and IoT. Unlike the widely used conventional surface micromachined microbolometer approaches, MikroSens' CIR detector technology does not require the use of special high TCR materials like VOx or a-Si, instead, it allows to implement microbolometers with standard CMOS layers, where the suspended bulk micromachined structure is obtained by only few consecutive selective MEMS etching steps while protecting the wirebond pads with a simple lithograpy step. This approach not only reduces the fabrication cost but also increases the production yield. In addition, needing simple subtractive post-CMOS fabrication steps allows the CIR technology to be carried out in any CMOS and MEMS foundry in a truly fabless fashion, where industrially mature and Au-free wafer level vacuum packaging technologies can also be carried out, leading to cost advantage, simplicity, scalability, and flexibility. The CIR approach is used to implement an 80x80 FPA with 35 μm pixel pitch, namely MS0835A, using a 0.18 μm CMOS process. The fabricated sensor is measured to provide NETD (Noise Equivalent Temperature Difference) value of 163 mK at 17 fps (frames per second) and 71 mK at 4 fps with F/1.0 optics in a dewar environment. The measurement results of the wafer level vacuum packaged sensors with one side AR coating shows an NETD values of 112 mK at 4 fps with F/1.1 optics, i.e., demonstrates a good performance for high volume low-cost applications like advanced presence detection and human counting applications. The CIR approach of MikroSens is scalable and can be used to reduce the pixel pitch even further while increasing the array size if necessary for various other low-cost, high volume applications.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

NASA Technical Reports Server (NTRS)

Blaes, B. R.; Soli, G. A.; Buehler, M. G.

1991-01-01

A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

Resolution Properties of a Calcium Tungstate (CaWO4) Screen Coupled to a CMOS Imaging Detector

NASA Astrophysics Data System (ADS)

Koukou, Vaia; Martini, Niki; Valais, Ioannis; Bakas, Athanasios; Kalyvas, Nektarios; Lavdas, Eleftherios; Fountos, George; Kandarakis, Ioannis; Michail, Christos

2017-11-01

The aim of the current work was to assess the resolution properties of a calcium tungstate (CaWO4) screen (screen coating thickness: 50.09 mg/cm2, actual thickness: 167.2 μm) coupled to a high resolution complementary metal oxide semiconductor (CMOS) digital imaging sensor. A 2.7x3.6 cm2 CaWO4 sample was extracted from an Agfa Curix universal screen and was coupled directly with the active area of the active pixel sensor (APS) CMOS sensor. Experiments were performed following the new IEC 62220-1-1:2015 International Standard, using an RQA-5 beam quality. Resolution was assessed in terms of the Modulation Transfer Function (MTF), using the slanted-edge method. The CaWO4/CMOS detector configuration was found with linear response, in the exposure range under investigation. The final MTF was obtained through averaging the oversampled edge spread function (ESF), using a custom-made software developed by our team, according to the IEC 62220-1-1:2015. Considering the renewed interest in calcium tungstate for various applications, along with the resolution results of this work, CaWO4 could be also considered for use in X-ray imaging devices such as charged-coupled devices (CCD) and CMOS.

Accurate estimation of camera shot noise in the real-time

NASA Astrophysics Data System (ADS)

Cheremkhin, Pavel A.; Evtikhiev, Nikolay N.; Krasnov, Vitaly V.; Rodin, Vladislav G.; Starikov, Rostislav S.

2017-10-01

Nowadays digital cameras are essential parts of various technological processes and daily tasks. They are widely used in optics and photonics, astronomy, biology and other various fields of science and technology such as control systems and video-surveillance monitoring. One of the main information limitations of photo- and videocameras are noises of photosensor pixels. Camera's photosensor noise can be divided into random and pattern components. Temporal noise includes random noise component while spatial noise includes pattern noise component. Temporal noise can be divided into signal-dependent shot noise and signal-nondependent dark temporal noise. For measurement of camera noise characteristics, the most widely used methods are standards (for example, EMVA Standard 1288). It allows precise shot and dark temporal noise measurement but difficult in implementation and time-consuming. Earlier we proposed method for measurement of temporal noise of photo- and videocameras. It is based on the automatic segmentation of nonuniform targets (ASNT). Only two frames are sufficient for noise measurement with the modified method. In this paper, we registered frames and estimated shot and dark temporal noises of cameras consistently in the real-time. The modified ASNT method is used. Estimation was performed for the cameras: consumer photocamera Canon EOS 400D (CMOS, 10.1 MP, 12 bit ADC), scientific camera MegaPlus II ES11000 (CCD, 10.7 MP, 12 bit ADC), industrial camera PixeLink PL-B781F (CMOS, 6.6 MP, 10 bit ADC) and video-surveillance camera Watec LCL-902C (CCD, 0.47 MP, external 8 bit ADC). Experimental dependencies of temporal noise on signal value are in good agreement with fitted curves based on a Poisson distribution excluding areas near saturation. Time of registering and processing of frames used for temporal noise estimation was measured. Using standard computer, frames were registered and processed during a fraction of second to several seconds only. Also the accuracy of the obtained temporal noise values was estimated.

Single-poly EEPROM cell with lightly doped MOS capacitors

DOEpatents

Riekels, James E [New Hope, MN; Lucking, Thomas B [Maple Grove, MN; Larsen, Bradley J [Mound, MN; Gardner, Gary R [Golden Valley, MN

2008-05-27

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.

A multi-channel instrumentation system for biosignal recording.

PubMed

Yu, Hong; Li, Pengfei; Xiao, Zhiming; Peng, Chung-Ching; Bashirullah, Rizwan

2008-01-01

This paper reports a highly integrated battery operated multi-channel instrumentation system intended for physiological signal recording. The mixed signal IC has been fabricated in standard 0.5microm 5V 3M-2P CMOS process and features 32 instrumentation amplifiers, four 8b SAR ADCs, a wireless power interface with Li-ion battery charger, low power bidirectional telemetry and FSM controller with power gating control for improved energy efficiency. The chip measures 3.2mm by 4.8mm and dissipates approximately 2.1mW when fully operational.

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

NASA Technical Reports Server (NTRS)

Katzman, Vladimir

2012-01-01

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2012-12-17

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

NASA Astrophysics Data System (ADS)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

Systematic analysis of CMOS-micromachined inductors with application to mixer matching circuits

NASA Astrophysics Data System (ADS)

Wu, Jerry Chun-Li

The growing demand for consumer voice and data communication systems and military communication applications has created a need for low-power, low-cost, high-performance radio-frequency (RF) front-end. To achieve this goal, bringing passive components, especially inductors, to silicon is imperative. On-chip passive components such as inductors and capacitors generally enhance the reliability and efficiency of silicon-integrated RF cells. They can provide circuit solutions with superior performance and contribute to a higher level of integration. With passive components on chip, there is a great opportunity to have transformers, filters, and matching networks on chip. However, inductors on silicon have a low quality factor (Q) due to both substrate and metal loss. This dissertation demonstrates the systematic analysis of inductors fabricated using standard complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) system technologies. We report system-on-chip inductor modeling, simulation, and measurements of effective inductance and quality factors. In this analysis methodology, a number of systematic simulations are performed on regular and micromachined inductors with different parameters such as spiral topology, number of turns, outer diameter, thickness, and percentage of substrate removed by using micromachining technologies. Three different novel support structures of the micromachined spiral inductor are proposed, analyzed, and implemented for larger size suspended inductors. The sensitivity of the structure support and different degree of substrate etching by post-processing is illustrated. The results provide guidelines for the selection of inductor parameters, post-processing methodologies, and its spiral supports to meet the RF design specifications and the stability requirements for mobile communication. The proposed CMOS-micromachined inductor is used in a low cost-effective double-balanced Gilbert mixer with on-chip matching network. The integrated mixer inductor was implemented and tested to prove the concept.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

PubMed

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

Radiation imaging with a new scintillator and a CMOS camera

NASA Astrophysics Data System (ADS)

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

NASA Technical Reports Server (NTRS)

Cable, J. S.; Carter, J. R.; Witteles, A. A.

1986-01-01

Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

Mk x Nk gated CMOS imager

NASA Astrophysics Data System (ADS)

Janesick, James; Elliott, Tom; Andrews, James; Tower, John; Bell, Perry; Teruya, Alan; Kimbrough, Joe; Bishop, Jeanne

2014-09-01

Our paper will describe a recently designed Mk x Nk x 10 um pixel CMOS gated imager intended to be first employed at the LLNL National Ignition Facility (NIF). Fabrication involves stitching MxN 1024x1024x10 um pixel blocks together into a monolithic imager (where M = 1, 2, . .10 and N = 1, 2, . . 10). The imager has been designed for either NMOS or PMOS pixel fabrication using a base 0.18 um/3.3V CMOS process. Details behind the design are discussed with emphasis on a custom global reset feature which erases the imager of unwanted charge in ~1 us during the fusion ignition process followed by an exposure to obtain useful data. Performance data generated by prototype imagers designed similar to the Mk x Nk sensor is presented.

Analog CMOS design for optical coherence tomography signal detection and processing.

PubMed

Xu, Wei; Mathine, David L; Barton, Jennifer K

2008-02-01

A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

A third-generation density-functional-theory-based method for calculating canonical molecular orbitals of large molecules.

PubMed

Hirano, Toshiyuki; Sato, Fumitoshi

2014-07-28

We used grid-free modified Cholesky decomposition (CD) to develop a density-functional-theory (DFT)-based method for calculating the canonical molecular orbitals (CMOs) of large molecules. Our method can be used to calculate standard CMOs, analytically compute exchange-correlation terms, and maximise the capacity of next-generation supercomputers. Cholesky vectors were first analytically downscaled using low-rank pivoted CD and CD with adaptive metric (CDAM). The obtained Cholesky vectors were distributed and stored on each computer node in a parallel computer, and the Coulomb, Fock exchange, and pure exchange-correlation terms were calculated by multiplying the Cholesky vectors without evaluating molecular integrals in self-consistent field iterations. Our method enables DFT and massively distributed memory parallel computers to be used in order to very efficiently calculate the CMOs of large molecules.

A CMOS VLSI IC for Real-Time Opto-Electronic Two-Dimensional Histogram Generation

DTIC Science & Technology

1993-12-01

large scale integration) design; MAGIC ; CMOS; optics; image processing; 93 16. PRICE CODE 17. SECURITY CLASSIFICATION 18. SECURITY CLASSIFICATiON 19...1. Sun SPARCstation ............. .............. 6 2. Magic .................. ................... 6 a. Peg ................. .................. 7 b...38 v APPENDIX B. MAGIC CELL LAYOUTS .... ............ .. 39 APPENDIX C: SIMULATION DATA ....... ............. .. 56 A. FINITE STATE MACHINE

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

NASA Astrophysics Data System (ADS)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Imaging system design and image interpolation based on CMOS image sensor

NASA Astrophysics Data System (ADS)

Li, Yu-feng; Liang, Fei; Guo, Rui

2009-11-01

An image acquisition system is introduced, which consists of a color CMOS image sensor (OV9620), SRAM (CY62148), CPLD (EPM7128AE) and DSP (TMS320VC5509A). The CPLD implements the logic and timing control to the system. SRAM stores the image data, and DSP controls the image acquisition system through the SCCB (Omni Vision Serial Camera Control Bus). The timing sequence of the CMOS image sensor OV9620 is analyzed. The imaging part and the high speed image data memory unit are designed. The hardware and software design of the image acquisition and processing system is given. CMOS digital cameras use color filter arrays to sample different spectral components, such as red, green, and blue. At the location of each pixel only one color sample is taken, and the other colors must be interpolated from neighboring samples. We use the edge-oriented adaptive interpolation algorithm for the edge pixels and bilinear interpolation algorithm for the non-edge pixels to improve the visual quality of the interpolated images. This method can get high processing speed, decrease the computational complexity, and effectively preserve the image edges.

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

NASA Astrophysics Data System (ADS)

Zhang, L.; Fu, M.; Zhang, Y.; Yan, W.; Wang, M.

2017-01-01

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm2.

USAF Logistics Process Optimization Study for the Aircraft Asset Sustainment Process. Volume 1.

DTIC Science & Technology

1998-12-31

solely to have a record that could be matched with the CMOS receipt data. (This problem is caused by DLA systems that currently do not populate CMOS with...unable to obtain passwords to the Depot D035 systems. Figure 16 shows daily savings as of 30 September 1998 (current time frame ) and projects savings...Engineering, modeling, and systems/software development company LAN Local Area Network LFA Large Frame Aircraft LMA Logistics Management Agency LMR

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

A Computationally Efficient Visual Saliency Algorithm Suitable for an Analog CMOS Implementation.

PubMed

D'Angelo, Robert; Wood, Richard; Lowry, Nathan; Freifeld, Geremy; Huang, Haiyao; Salthouse, Christopher D; Hollosi, Brent; Muresan, Matthew; Uy, Wes; Tran, Nhut; Chery, Armand; Poppe, Dorothy C; Sonkusale, Sameer

2018-06-27

Computer vision algorithms are often limited in their application by the large amount of data that must be processed. Mammalian vision systems mitigate this high bandwidth requirement by prioritizing certain regions of the visual field with neural circuits that select the most salient regions. This work introduces a novel and computationally efficient visual saliency algorithm for performing this neuromorphic attention-based data reduction. The proposed algorithm has the added advantage that it is compatible with an analog CMOS design while still achieving comparable performance to existing state-of-the-art saliency algorithms. This compatibility allows for direct integration with the analog-to-digital conversion circuitry present in CMOS image sensors. This integration leads to power savings in the converter by quantizing only the salient pixels. Further system-level power savings are gained by reducing the amount of data that must be transmitted and processed in the digital domain. The analog CMOS compatible formulation relies on a pulse width (i.e., time mode) encoding of the pixel data that is compatible with pulse-mode imagers and slope based converters often used in imager designs. This letter begins by discussing this time-mode encoding for implementing neuromorphic architectures. Next, the proposed algorithm is derived. Hardware-oriented optimizations and modifications to this algorithm are proposed and discussed. Next, a metric for quantifying saliency accuracy is proposed, and simulation results of this metric are presented. Finally, an analog synthesis approach for a time-mode architecture is outlined, and postsynthesis transistor-level simulations that demonstrate functionality of an implementation in a modern CMOS process are discussed.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A CMOS current-mode log(x) and log(1/x) functions generator

NASA Astrophysics Data System (ADS)

Al-Absi, Munir A.; Al-Tamimi, Karama M.

2014-08-01

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

High-performance, mechanically flexible, and vertically integrated 3D carbon nanotube and InGaZnO complementary circuits with a temperature sensor.

PubMed

Honda, Wataru; Harada, Shingo; Ishida, Shohei; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-08-26

A vertically integrated inorganic-based flexible complementary metal-oxide-semiconductor (CMOS) inverter with a temperature sensor with a high inverter gain of ≈50 and a low power consumption of <7 nW mm(-1) is demonstrated using a layer-by-layer assembly process. In addition, the negligible influence of the mechanical flexibility on the performance of the CMOS inverter and the temperature dependence of the CMOS inverter characteristics are discussed. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

NASA Astrophysics Data System (ADS)

Moradi, Behzad; Mirzaei, Abdolreza

2016-11-01

A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

PubMed Central

Wei, Liping.; Doughan, Samer.; Han, Yi.; DaCosta, Matthew V.; Krull, Ulrich J.; Ho, Derek.

2014-01-01

Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology.

PubMed

Llobet, J; Rius, G; Chuquitarqui, A; Borrisé, X; Koops, R; van Veghel, M; Perez-Murano, F

2018-04-02

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

NASA Astrophysics Data System (ADS)

Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

2018-04-01

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Addressable inverter matrix for process and device characterization

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sayah, H. R.

1985-01-01

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold vltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Addressable inverter matrix for process and device characterization

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Sayah, H. R.

1985-01-01

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated in this study, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

PubMed Central

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-01-01

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation

NASA Astrophysics Data System (ADS)

Bourree, Loig E.

2014-05-01

Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

PubMed Central

Roever, Stefan

2012-01-01

A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results.

PubMed

Carboni, Caterina; Bisoni, Lorenzo; Carta, Nicola; Puddu, Roberto; Raspopovic, Stanisa; Navarro, Xavier; Raffo, Luigi; Barbaro, Massimo

2016-04-01

The prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of 2 integrated circuits: a standard CMOS device for neural recording and a HVCMOS device for neural stimulation. The integrated circuits have been realized in 2 different 0.35μ m CMOS processes available from ams. The complete system incorporates 8 channels each including the analog front-end, the A/D conversion, based on a sigma delta architecture and a programmable stimulation module implemented as a 5-bit current DAC; two voltage boosters supply the output stimulation stage with a programmable voltage scalable up to 17V. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μ V r m s , and to selectively elicit the tibial and plantar muscles using different active sites of the electrode.

Evaluation of electron beam stabilization for ion implant processing

NASA Astrophysics Data System (ADS)

Buffat, Stephen J.; Kickel, Bee; Philipps, B.; Adams, J.; Ross, Matthew F.; Minter, Jason P.; Marlowe, Trey; Wong, Selmer S.

1999-06-01

With the integration of high energy ion implant processes into volume CMOS manufacturing, the need for thick resist stabilization to achieve a stable ion implant process is critical. With new photoresist characteristics, new implant end station characteristics arise. The resist outgassing needs to be addressed as well as the implant profile to ensure that the dosage is correct and the implant angle does not interfere with other underlying features. This study compares conventional deep-UV/thermal with electron beam stabilization. The electron beam system used in this study utilizes a flood electron source and is a non-thermal process. These stabilization techniques are applied to a MeV ion implant process in a CMOS production process flow.

Fully Digital Arrays of Silicon Photomultipliers (dSiPM) - a Scalable Alternative to Vacuum Photomultiplier Tubes (PMT)

NASA Astrophysics Data System (ADS)

Haemisch, York; Frach, Thomas; Degenhardt, Carsten; Thon, Andreas

Silicon Photomultipliers (SiPMs) have emerged as promising alternative to fast vacuum photomultiplier tubes (PMT). A fully digital implementation of the Silicon Photomultiplier (dSiPM) has been developed in order to overcome the deficiencies and limitations of the so far only analog SiPMs (aSiPMs). Our sensor is based on arrays of single photon avalanche photodiodes (SPADs) integrated in a standard CMOS process. Photons are detected directly by sensing the voltage at the SPAD anode using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective inhibit of detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the integrated time-to-digital converter. In consequence, photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The integration with CMOS logic provides the added benefit of low power consumption and possible integration of data post-processing directly in the sensor. In this overview paper, we discuss the sensor architecture together with its characteristics with a focus on scalability and practicability aspects for applications in medical imaging, high energy- and astrophysics.

Ultrananocrystalline diamond films with optimized dielectric properties for advanced RF MEMS capacitive switches

DOEpatents

Sumant, Anirudha V.; Auciello, Orlando H.; Mancini, Derrick C.

2013-01-15

An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Magnan, Pierre; Bernard, Frédéric; Rolland, Guy; Saint-Pé, Olivier; Huger, Nicolas; Corbière, Franck

2008-02-01

We present here a study on both CMOS sensors and elementary structures (photodiodes and in-pixel MOSFETs) manufactured in a deep submicron process dedicated to imaging. We designed a test chip made of one 128×128-3T-pixel array with 10 μm pitch and more than 120 isolated test structures including photodiodes and MOSFETs with various implants and different sizes. All these devices were exposed to ionizing radiation up to 100 krad and their responses were correlated to identify the CMOS sensor weaknesses. Characterizations in darkness and under illumination demonstrated that dark current increase is the major sensor degradation. Shallow trench isolation was identified to be responsible for this degradation as it increases the number of generation centers in photodiode depletion regions. Consequences on hardness assurance and hardening-by-design are discussed.

Break-before-make CMOS inverter for power-efficient delay implementation.

PubMed

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

PubMed Central

Raič, Dušan

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

NASA Technical Reports Server (NTRS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-01-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

NASA Astrophysics Data System (ADS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-10-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders - from Optical Triangulation to the Automotive Field.

PubMed

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-03-13

With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS) image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET) of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

NASA Astrophysics Data System (ADS)

Schatz, A.; Pantel, D.; Hanemann, T.

2017-09-01

Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

PubMed Central

Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

Attentional gating models of object substitution masking.

PubMed

Põder, Endel

2013-11-01

Di Lollo, Enns, and Rensink (2000) proposed the computational model of object substitution (CMOS) to explain their experimental results with sparse visual maskers. This model supposedly is based on reentrant hypotheses testing in the visual system, and the modeled experiments are believed to demonstrate these reentrant processes in human vision. In this study, I analyze the main assumptions of this model. I argue that CMOS is a version of the attentional gating model and that its relationship with reentrant processing is rather illusory. The fit of this model to the data indicates that reentrant hypotheses testing is not necessary for the explanation of object substitution masking (OSM). Further, the original CMOS cannot predict some important aspects of the experimental data. I test 2 new models incorporating an unselective processing (divided attention) stage; these models are more consistent with data from OSM experiments. My modeling shows that the apparent complexity of OSM can be reduced to a few simple and well-known mechanisms of perception and memory. PsycINFO Database Record (c) 2013 APA, all rights reserved.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Flexible All-Digital Receiver for Bandwidth Efficient Modulations

NASA Technical Reports Server (NTRS)

Gray, Andrew; Srinivasan, Meera; Simon, Marvin; Yan, Tsun-Yee

2000-01-01

An all-digital high data rate parallel receiver architecture developed jointly by Goddard Space Flight Center and the Jet Propulsion Laboratory is presented. This receiver utilizes only a small number of high speed components along with a majority of lower speed components operating in a parallel frequency domain structure implementable in CMOS, and can currently process up to 600 Mbps with standard QPSK modulation. Performance results for this receiver for bandwidth efficient QPSK modulation schemes such as square-root raised cosine pulse shaped QPSK and Feher's patented QPSK are presented, demonstrating the flexibility of the receiver architecture.

Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

PubMed

Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

2016-02-01

Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications.

Design and simulation of multi-color infrared CMOS metamaterial absorbers

NASA Astrophysics Data System (ADS)

Cheng, Zhengxi; Chen, Yongping; Ma, Bin

2016-05-01

Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

Embedded CMOS basecalling for nanopore DNA sequencing.

PubMed

Chengjie Wang; Junli Zheng; Magierowski, Sebastian; Ghafar-Zadeh, Ebrahim

2016-08-01

DNA sequencing based on nanopore sensors is now entering the marketplace. The ability to interface this technology to established CMOS microelectronics promises significant improvements in functionality and miniaturization. Among the key functions to benefit from this interface will be basecalling, the conversion of raw electronic molecular signatures to nucleotide sequence predictions. This paper presents the design and performance potential of custom CMOS base-callers embedded alongside nanopore sensors. A basecalliing architecture implemented in 32-nm technology is discussed with the ability to process the equivalent of 20 human genomes per day in real-time at a power density of 5 W/cm2 assuming a 3-mer nanopore sensor.

Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector.

PubMed

Jain, A; Takemoto, H; Silver, M D; Nagesh, S V S; Ionita, C N; Bednarek, D R; Rudin, S

Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm × 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

A focal plane metrology system and PSF centroiding experiment

NASA Astrophysics Data System (ADS)

Li, Haitao; Li, Baoquan; Cao, Yang; Li, Ligang

2016-10-01

In this paper, we present an overview of a detector array equipment metrology testbed and a micro-pixel centroiding experiment currently under development at the National Space Science Center, Chinese Academy of Sciences. We discuss on-going development efforts aimed at calibrating the intra-/inter-pixel quantum efficiency and pixel positions for scientific grade CMOS detector, and review significant progress in achieving higher precision differential centroiding for pseudo star images in large area back-illuminated CMOS detector. Without calibration of pixel positions and intrapixel response, we have demonstrated that the standard deviation of differential centroiding is below 2.0e-3 pixels.

A new Recoil Proton Telescope for energy and fluence measurement of fast neutron fields

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lebreton, Lena; Bachaalany, Mario; Husson, Daniel

The spectrometer ATHENA (Accurate Telescope for High Energy Neutron metrology Applications), is being developed at the IRSN / LMDN (Institut de Radioprotection et de Surete nucleaire / Laboratoire de Metrologie et de dosimetrie des neutrons) and aims at characterizing energy and fluence of fast neutron fields. The detector is a Recoil Proton Telescope and measures neutron fields in the range of 5 to 20 MeV. This telescope is intended to become a primary standard for both energy and fluence measurements. The neutron detection is achieved by a polyethylene radiator for n-p conversion, three 50{sub m} thick silicon sensors that usemore » CMOS technology for the proton tracking and a 3 mm thick silicon diode to measure the residual proton energy. This first prototype used CMOS sensors called MIMOSTAR, initially developed for heavy ion physics. The use of CMOS sensors and silicon diode increases the intrinsic efficiency of the detector by a factor of ten compared with conventional designs. The first prototype has already been done and was a successful study giving the results it offered in terms of energy and fluence measurements. For mono energetic beams going from 5 to 19 MeV, the telescope offered an energy resolution between 5 and 11% and fluence difference going from 5 to 7% compared to other home standards. A second and final prototype of the detector is being designed. It will hold upgraded CMOS sensors called FastPixN. These CMOS sensors are supposed to run 400 times faster than the older version and therefore give the telescope the ability to support neutron flux in the order of 107 to 108cm{sup 2}:s{sup 1}. The first prototypes results showed that a 50 m pixel size is enough for a precise scattering angle reconstruction. Simulations using MCNPX and GEANT4 are already in place for further improvements. A DeltaE diode will replace the third CMOS sensor and will be installed right before the silicon diode for a better recoil proton selection. The final prototype with its new geometry will increase the telescopes efficiency by a factor of 1.5. It will also cover some of the most important points in metrology; repeatability, reproducibility and sustainability. (authors)« less

A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback

NASA Astrophysics Data System (ADS)

Huang, Zhangcai; Jiang, Minglu; Inoue, Yasuaki

Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6Vpp with 0.159% linearity error on VX and 4.8Vpp with 0.51% linearity error on VY for ±2.5V power supply voltages, respectively.

Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

NASA Astrophysics Data System (ADS)

Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

2016-09-01

The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

System-level analysis and design for RGB-NIR CMOS camera

NASA Astrophysics Data System (ADS)

Geelen, Bert; Spooren, Nick; Tack, Klaas; Lambrechts, Andy; Jayapala, Murali

2017-02-01

This paper presents system-level analysis of a sensor capable of simultaneously acquiring both standard absorption based RGB color channels (400-700nm, 75nm FWHM), as well as an additional NIR channel (central wavelength: 808 nm, FWHM: 30nm collimated light). Parallel acquisition of RGB and NIR info on the same CMOS image sensor is enabled by monolithic pixel-level integration of both a NIR pass thin film filter and NIR blocking filters for the RGB channels. This overcomes the need for a standard camera-level NIR blocking filter to remove the NIR leakage present in standard RGB absorption filters from 700-1000nm. Such a camera-level NIR blocking filter would inhibit the acquisition of the NIR channel on the same sensor. Thin film filters do not operate in isolation. Rather, their performance is influenced by the system context in which they operate. The spectral distribution of light arriving at the photo diode is shaped a.o. by the illumination spectral profile, optical component transmission characteristics and sensor quantum efficiency. For example, knowledge of a low quantum efficiency (QE) of the CMOS image sensor above 800nm may reduce the filter's blocking requirements and simplify the filter structure. Similarly, knowledge of the incoming light angularity as set by the objective lens' F/# and exit pupil location may be taken into account during the thin film's optimization. This paper demonstrates how knowledge of the application context can facilitate filter design and relax design trade-offs and presents experimental results.

Traceable working standards with SI units of radiance for characterizing the measurement performance of investigational clinical NIRF imaging devices

NASA Astrophysics Data System (ADS)

Zhu, Banghe; Rasmussen, John C.; Litorja, Maritoni; Sevick-Muraca, Eva M.

2017-03-01

All medical devices for Food and Drug market approval require specifications of performance based upon International System of Units (SI) or units derived from SI for reasons of traceability. Recently, near-infrared fluorescence (NIRF) imaging devices of a variety of designs have emerged on the market and in investigational clinical studies. Yet the design of devices used in the clinical studies vary widely, suggesting variable device performance. Device performance depends upon optimal excitation of NIRF imaging agents, rejection of backscattered excitation and ambient light, and selective collection of fluorescence emanating from the fluorophore. There remains no traceable working standards with SI units of radiance to enable prediction that a given molecular imaging agent can be detected in humans by a given NIRF imaging device. Furthermore, as technologies evolve and as NIRF imaging device components change, there remains no standardized means to track device improvements over time and establish clinical performance without involving clinical trials, often costly. In this study, we deployed a methodology to calibrate luminescent radiance of a stable, solid phantom in SI units of mW/cm2/sr for characterizing the measurement performance of ICCD and IsCMOS camera based NIRF imaging devices, such as signal-to-noise ratio (SNR) and contrast. The methodology allowed determination of superior SNR of the ICCD over the IsCMOS system; comparable contrast of ICCD and IsCMOS depending upon binning strategies.

Design and implementation of non-linear image processing functions for CMOS image sensor

NASA Astrophysics Data System (ADS)

Musa, Purnawarman; Sudiro, Sunny A.; Wibowo, Eri P.; Harmanto, Suryadi; Paindavoine, Michel

2012-11-01

Today, solid state image sensors are used in many applications like in mobile phones, video surveillance systems, embedded medical imaging and industrial vision systems. These image sensors require the integration in the focal plane (or near the focal plane) of complex image processing algorithms. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well as low power consumption. To achieve these objectives, low-level analog processing allows extracting the useful information in the scene directly. For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene. Our goal was to design an intelligent image sensor prototype achieving high-speed image acquisition and non-linear image processing (like local minima and maxima calculations). For this purpose, we present in this article the design and test of a 64×64 pixels image sensor built in a standard CMOS Technology 0.35 μm including non-linear image processing. The architecture of our sensor, named nLiRIC (non-Linear Rapid Image Capture), is based on the implementation of an analog Minima/Maxima Unit. This MMU calculates the minimum and maximum values (non-linear functions), in real time, in a 2×2 pixels neighbourhood. Each MMU needs 52 transistors and the pitch of one pixel is 40×40 mu m. The total area of the 64×64 pixels is 12.5mm2. Our tests have shown the validity of the main functions of our new image sensor like fast image acquisition (10K frames per second), minima/maxima calculations in less then one ms.

Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

NASA Technical Reports Server (NTRS)

Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

2002-01-01

We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

Smart CMOS image sensor for lightning detection and imaging.

PubMed

Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

2013-03-01

We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

Optical, analog and digital domain architectural considerations for visual communications

NASA Astrophysics Data System (ADS)

Metz, W. A.

2008-01-01

The end of the performance entitlement historically achieved by classic scaling of CMOS devices is within sight, driven ultimately by fundamental limits. Performance entitlements predicted by classic CMOS scaling have progressively failed to be realized in recent process generations due to excessive leakage, increasing interconnect delays and scaling of gate dielectrics. Prior to reaching fundamental limits, trends in technology, architecture and economics will pressure the industry to adopt new paradigms. A likely response is to repartition system functions away from digital implementations and into new architectures. Future architectures for visual communications will require extending the implementation into the optical and analog processing domains. The fundamental properties of these domains will in turn give rise to new architectural concepts. The limits of CMOS scaling and impact on architectures will be briefly reviewed. Alternative approaches in the optical, electronic and analog domains will then be examined for advantages, architectural impact and drawbacks.

Application specific serial arithmetic arrays

NASA Technical Reports Server (NTRS)

Winters, K.; Mathews, D.; Thompson, T.

1990-01-01

High performance systolic arrays of serial-parallel multiplier elements may be rapidly constructed for specific applications by applying hardware description language techniques to a library of full-custom CMOS building blocks. Single clock pre-charged circuits have been implemented for these arrays at clock rates in excess of 100 Mhz using economical 2-micron (minimum feature size) CMOS processes, which may be quickly configured for a variety of applications. A number of application-specific arrays are presented, including a 2-D convolver for image processing, an integer polynomial solver, and a finite-field polynomial solver.

Advanced CMOS Radiation Effects Testing and Analysis

NASA Technical Reports Server (NTRS)

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus

The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various attributes that would make them superior for use in X-ray astronomy. In particular, PMOS has: "no" photo-charge recombination; "no" Random Telegraph Signal noise (RTS); and lower read noise. The existing SRI/Sarnoff PMOS devices are small and have been developed for non-intensified night vision applications, however, no x-ray evaluation of a monolithic PMOS device has ever been made. In addition to these PMOS devices, SAO will also evaluate existing NMOS scale-able format devices that can be fabricated in any rectangular size/shape using stitchable reticles. These "Mk by Nk" devices would be ideal for large X-ray focal planes or long grating readouts. The Sarnoff/SRI Mk by Nk format devices have been designed, with foresight, so that they can be fabricated in either PMOS or NMOS by changing a single fabrication reticle and by changing the type of Si substrate. If X-ray performance results are expected, this proposal will lead the way to future fabrication of Mk by Nk PMOS devices that would be ideal for X-ray astronomy missions such as "X-ray Surveyor". SAO will also investigate the interaction of directly deposited Optical Blocking Filters (OBFs) on various back side passivated devices, and their resultant effects on very "soft" x-ray response. The latest CMOS processes and very fast on-chip, and off-chip digital readout signal chains and camera systems will be demonstrated.

A Multidisciplinary Approach to High Throughput Nuclear Magnetic Resonance Spectroscopy

PubMed Central

Pourmodheji, Hossein; Ghafar-Zadeh, Ebrahim; Magierowski, Sebastian

2016-01-01

Nuclear Magnetic Resonance (NMR) is a non-contact, powerful structure-elucidation technique for biochemical analysis. NMR spectroscopy is used extensively in a variety of life science applications including drug discovery. However, existing NMR technology is limited in that it cannot run a large number of experiments simultaneously in one unit. Recent advances in micro-fabrication technologies have attracted the attention of researchers to overcome these limitations and significantly accelerate the drug discovery process by developing the next generation of high-throughput NMR spectrometers using Complementary Metal Oxide Semiconductor (CMOS). In this paper, we examine this paradigm shift and explore new design strategies for the development of the next generation of high-throughput NMR spectrometers using CMOS technology. A CMOS NMR system consists of an array of high sensitivity micro-coils integrated with interfacing radio-frequency circuits on the same chip. Herein, we first discuss the key challenges and recent advances in the field of CMOS NMR technology, and then a new design strategy is put forward for the design and implementation of highly sensitive and high-throughput CMOS NMR spectrometers. We thereafter discuss the functionality and applicability of the proposed techniques by demonstrating the results. For microelectronic researchers starting to work in the field of CMOS NMR technology, this paper serves as a tutorial with comprehensive review of state-of-the-art technologies and their performance levels. Based on these levels, the CMOS NMR approach offers unique advantages for high resolution, time-sensitive and high-throughput bimolecular analysis required in a variety of life science applications including drug discovery. PMID:27294925

An easily accessible carbon material derived from carbonization of polyacrylonitrile ultrathin films: ambipolar transport properties and application in a CMOS-like inverter.

PubMed

Jiao, Fei; Zhang, Fengjiao; Zang, Yaping; Zou, Ye; Di, Chong'an; Xu, Wei; Zhu, Daoben

2014-03-04

Ultrathin carbon films were prepared by carbonization of a solution processed polyacrylonitrile (PAN) film in a moderate temperature range (500-700 °C). The films displayed balanced hole (0.50 cm(2) V(-1) s(-1)) and electron mobilities (0.20 cm(2) V(-1) s(-1)) under ambient conditions. Spectral characterization revealed that the electrical transport is due to the formation of sp(2) hybridized carbon during the carbonization process. A CMOS-like inverter demonstrated the potential application of this material in the area of carbon electronics, considering its processability and low-cost.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

PubMed Central

Wu, Jih-Huah; Pen, Cheng-Chung; Jiang, Joe-Air

2008-01-01

With their significant features, the applications of complementary metal-oxide semiconductor (CMOS) image sensors covers a very extensive range, from industrial automation to traffic applications such as aiming systems, blind guidance, active/passive range finders, etc. In this paper CMOS image sensor-based active and passive range finders are presented. The measurement scheme of the proposed active/passive range finders is based on a simple triangulation method. The designed range finders chiefly consist of a CMOS image sensor and some light sources such as lasers or LEDs. The implementation cost of our range finders is quite low. Image processing software to adjust the exposure time (ET) of the CMOS image sensor to enhance the performance of triangulation-based range finders was also developed. An extensive series of experiments were conducted to evaluate the performance of the designed range finders. From the experimental results, the distance measurement resolutions achieved by the active range finder and the passive range finder can be better than 0.6% and 0.25% within the measurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests on applications of the developed CMOS image sensor-based range finders to the automotive field were also conducted. The experimental results demonstrated that our range finders are well-suited for distance measurements in this field. PMID:27879789

Development of a CMOS-compatible PCR chip: comparison of design and system strategies

NASA Astrophysics Data System (ADS)

Erill, Ivan; Campoy, Susana; Rus, José; Fonseca, Luis; Ivorra, Antoni; Navarro, Zenón; Plaza, José A.; Aguiló, Jordi; Barbé, Jordi

2004-11-01

In the last decade research in chips for DNA amplification through the polymerase chain reaction (PCR) has been relatively abundant, but has taken very diverse approaches, leaving little common ground for a straightforward comparison of results. Here we report the development of a line of PCR chips that is fully compatible with complementary-metal-oxide-semiconductor (CMOS) technology and its revealing use as a general platform to test and compare a wide range of experimental parameters involved in PCR-chip design and operation. Peltier-heated and polysilicon thin-film driven PCR chips have been produced and directly compared in terms of efficiency, speed and power consumption, showing that thin-film systems run faster and more efficiently than Peltier-based ones, but yield inferior PCR products. Serpentine-like chamber designs have also been compared with standard rectangular designs and with the here reported rhomboidal chamber shape, showing that serpentine-like chambers do not have detrimental effects in PCR efficiency when using non-flow-through schemes, and that chamber design has a strong impact on sample insertion/extraction yields. With an accurate temperature control (±0.2 °C) we have optimized reaction kinetics to yield sound PCR amplifications of 25 µl mixtures in 20 min and with 24.4 s cycle times, confirming that a titrated amount of bovine albumin serum (BSA, 2.5 µg µl-1) is essential to counteract polymerase adsorption at chip walls. The reported use of a CMOS-compatible technological process paves the way for an easy adaption to foundry requirements and for a scalable integration of electro-optic detection and control circuitry.

Towards High Throughput Cell Growth Screening: A New CMOS 8 × 8 Biosensor Array for Life Science Applications.

PubMed

Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Letourneau, Antoine; Sawan, Mohamad

2017-04-01

In this paper we present a CMOS capacitive sensor array as a compact and low-cost platform for high-throughput cell growth monitoring. The proposed biosensor, consists of an array of 8 × 8 CMOS fully differential charge-based capacitive measurement sensors. A DC-input Σ∆ modulator is used to convert the sensors' signals to digital values for reading out the biological/chemical data and further signal processing. To compensate the mismatch variations between the current mirror transistors, a calibration circuitry is proposed which removes the output voltage offset with less than 8.2% error. We validate the chip functionality using various organic solvents with different dielectric constants. Moreover, we show the response of the chip to different concentrations of Polystyrene beads that have the same electrical properties as the living cells. The experimental results show that the chip allows the detection of a wide range of Polystyrene beads concentrations from as low as 10 beads/ml to 100 k beads/ml. In addition, we present the experimental results from H1299 (human lung carcinoma) cell line where we show that the chip successfully allows the detection of cell attachment and growth over capacitive electrodes in a 30 h measurement time and the results are in consistency with the standard cell-based assays. The capability of proposed device for label-free and real-time detection of cell growth with very high sensitivity opens up the important opportunity for utilizing the device in rapid screening of living cells.

Research on HDR image fusion algorithm based on Laplace pyramid weight transform with extreme low-light CMOS

NASA Astrophysics Data System (ADS)

Guan, Wen; Li, Li; Jin, Weiqi; Qiu, Su; Zou, Yan

2015-10-01

Extreme-Low-Light CMOS has been widely applied in the field of night-vision as a new type of solid image sensor. But if the illumination in the scene has drastic changes or the illumination is too strong, Extreme-Low-Light CMOS can't both clearly present the high-light scene and low-light region. According to the partial saturation problem in the field of night-vision, a HDR image fusion algorithm based on the Laplace Pyramid was researched. The overall gray value and the contrast of the low light image is very low. We choose the fusion strategy based on regional average gradient for the top layer of the long exposure image and short exposure image, which has rich brightness and textural features. The remained layers which represent the edge feature information of the target are based on the fusion strategy based on regional energy. In the process of source image reconstruction with Laplacian pyramid image, we compare the fusion results with four kinds of basal images. The algorithm is tested using Matlab and compared with the different fusion strategies. We use information entropy, average gradient and standard deviation these three objective evaluation parameters for the further analysis of the fusion result. Different low illumination environment experiments show that the algorithm in this paper can rapidly get wide dynamic range while keeping high entropy. Through the verification of this algorithm features, there is a further application prospect of the optimized algorithm. Keywords: high dynamic range imaging, image fusion, multi-exposure image, weight coefficient, information fusion, Laplacian pyramid transform.

Fabrication and characterization of resonant SOI micromechanical silicon sensors based on DRIE micromachining, freestanding release process and silicon direct bonding

NASA Astrophysics Data System (ADS)

Gigan, Olivier; Chen, Hua; Robert, Olivier; Renard, Stephane; Marty, Frederic

2002-11-01

This paper is dedicated to the fabrication and technological aspect of a silicon microresonator sensor. The entire project includes the fabrication processes, the system modelling/simulation, and the electronic interface. The mechanical model of such resonator is presented including description of frequency stability and Hysterises behaviour of the electrostatically driven resonator. Numeric model and FEM simulations are used to simulate the system dynamic behaviour. The complete fabrication process is based on standard microelectronics technology with specific MEMS technological steps. The key steps are described: micromachining on SOI by Deep Reactive Ion Etching (DRIE), specific release processes to prevent sticking (resist and HF-vapour release process) and collective vacuum encapsulation by Silicon Direct Bonding (SDB). The complete process has been validated and prototypes have been fabricated. The ASIC was designed to interface the sensor and to control the vibration amplitude. This electronic was simulated and designed to work up to 200°C and implemented in a standard 0.6μ CMOS technology. Characterizations of sensor prototypes are done both mechanically and electrostatically. These measurements showed good agreements with theory and FEM simulations.

Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

PubMed

Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

2015-08-01

This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

2.4 GHz CMOS power amplifier with mode-locking structure to enhance gain.

PubMed

Lee, Changhyun; Park, Changkun

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm(2).

2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

PubMed Central

2014-01-01

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2. PMID:25045755

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

CMOS single-stage input-powered bridge rectifier with boost switch and duty cycle control

NASA Astrophysics Data System (ADS)

Radzuan, Roskhatijah; Mohd Salleh, Mohd Khairul; Hamzah, Mustafar Kamal; Ab Wahab, Norfishah

2017-06-01

This paper presents a single-stage input-powered bridge rectifier with boost switch for wireless-powered devices such as biomedical implants and wireless sensor nodes. Realised using CMOS process technology, it employs a duty cycle switch control to achieve high output voltage using boost technique, leading to a high output power conversion. It has only six external connections with the boost inductance. The input frequency of the bridge rectifier is set at 50 Hz, while the switching frequency is 100 kHz. The proposed circuit is fabricated on a single 0.18-micron CMOS die with a space area of 0.024 mm2. The simulated and measured results show good agreement.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

PubMed

Wei, Liping; Yan, Wenrong; Ho, Derek

2017-12-04

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics

PubMed Central

Yan, Wenrong; Ho, Derek

2017-01-01

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. PMID:29207568

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

NASA Astrophysics Data System (ADS)

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector

NASA Astrophysics Data System (ADS)

Parkalian, N.; Robens, M.; Grewing, C.; Christ, V.; Kruth, A.; Liebau, D.; Muralidharan, P.; Nielinger, D.; Roth, C.; Yegin, U.; Zambanini, A.; van Waasen, S.

2018-02-01

This paper presents a 4 GHz phase locked loop (PLL), which is implemented in a 65 nm standard CMOS process to provide low noise and high frequency sampling clocks for readout electronics to be used in the Jiangmen Underground Neutrino Observatory (JUNO) experiment. Based on the application requirements the target of the design is to find the best compromise between power consumption, area and phase noise for a highly reliable topology. The design implements a novel method for the charge pump that suppresses current mismatch when the PLL is locked. This reduces static phase offset at the inputs of the phase-frequency detector (PFD) that otherwise would introduce spurs at the PLL output. In addition, a technique of amplitude regulation for the voltage controlled oscillator (VCO) is presented to provide low noise and reliable operation. The combination of thin and thick oxide varactor transistors ensures optimum tuning range and linearity over process as well as temperature changes for the VCO without additional calibration steps. The current mismatch at the output of the charge pump for the control voltage at about half the 1 V supply voltage is below 0.3% and static phase offset down to 0.25% is reached. The total PLL consumes 18.5 mW power at 1.8 V supply for the VCO and 1 V supply for the other parts.

Design of ultra-low power biopotential amplifiers for biosignal acquisition applications.

PubMed

Zhang, Fan; Holleman, Jeremy; Otis, Brian P

2012-08-01

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply.

Advanced Sensors for TBI

DTIC Science & Technology

2015-07-01

CMOS clean • Commercialization of the sensor is aided by this process as use of CMOS -clean commercial foundries will not be restricted Bench...AD_________________ Award Number: W81XWH-10-2-0040 TITLE: Advanced Sensors for TBI PRINCIPAL INVESTIGATOR: Bruce Lyeth, Ph.D. CONTRACTING...ABOVE ADDRESS. 1. REPORT DATE July 2015 2. REPORT TYPE Annual 3. DATES COVERED 1Jul2014 - 30Jun2015 4. TITLE AND SUBTITLE Advanced Sensors for TBI 5a

CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

PubMed

Hussain, Aftab M; Hussain, Muhammad M

2016-06-01

Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Ma, Wuying; Huang, Shaoyan

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a {sup 60}Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo responsemore » non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.« less

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Wang, Zujun; Ma, Wuying; Huang, Shaoyan; Yao, Zhibin; Liu, Minbo; He, Baoping; Liu, Jing; Sheng, Jiangkun; Xue, Yuan

2016-03-01

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a 60Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo response non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

PubMed

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications

DOE PAGES

Mincey, John Stephen; Su, Eric C.; Silva-Martinez, Jose; ...

2018-02-28

A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar applications. Also, to eliminate dispersion effects in the received waveform, a finite impulse response (FIR) topology is proposed, which has a measured standard deviation of an in-band group delay of 11 ns that is primarily dominated by the inherent, fully predictable delay introduced by the sample-and-hold. The filter operates at an IF of 20 MHz, and is tunable in BW from 1.5 to 15 MHz, which makes it optimal to be used with varying pulse widths in the radar. Employing a total of 128 taps, the FIR filtermore » provides greater than 50-dB sharp attenuation in the stopband in order to minimize all out-of-band noise in the low signal-to-noise received radar signal. Fabricated in a 0.18-μm silicon on insulator CMOS process, the proposed filter consumes approximately 3.5 mW/tap with a 1.8-V supply. Finally, a 20-MHz two-tone measurement with 200-kHz tone separation shows IIP3 greater than 8.5 dBm.« less

Simulation environment based on the Universal Verification Methodology

NASA Astrophysics Data System (ADS)

Fiergolski, A.

2017-01-01

Universal Verification Methodology (UVM) is a standardized approach of verifying integrated circuit designs, targeting a Coverage-Driven Verification (CDV). It combines automatic test generation, self-checking testbenches, and coverage metrics to indicate progress in the design verification. The flow of the CDV differs from the traditional directed-testing approach. With the CDV, a testbench developer, by setting the verification goals, starts with an structured plan. Those goals are targeted further by a developed testbench, which generates legal stimuli and sends them to a device under test (DUT). The progress is measured by coverage monitors added to the simulation environment. In this way, the non-exercised functionality can be identified. Moreover, the additional scoreboards indicate undesired DUT behaviour. Such verification environments were developed for three recent ASIC and FPGA projects which have successfully implemented the new work-flow: (1) the CLICpix2 65 nm CMOS hybrid pixel readout ASIC design; (2) the C3PD 180 nm HV-CMOS active sensor ASIC design; (3) the FPGA-based DAQ system of the CLICpix chip. This paper, based on the experience from the above projects, introduces briefly UVM and presents a set of tips and advices applicable at different stages of the verification process-cycle.

A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mincey, John Stephen; Su, Eric C.; Silva-Martinez, Jose

A configurable-bandwidth (BW) filter is presented in this paper for pulsed radar applications. Also, to eliminate dispersion effects in the received waveform, a finite impulse response (FIR) topology is proposed, which has a measured standard deviation of an in-band group delay of 11 ns that is primarily dominated by the inherent, fully predictable delay introduced by the sample-and-hold. The filter operates at an IF of 20 MHz, and is tunable in BW from 1.5 to 15 MHz, which makes it optimal to be used with varying pulse widths in the radar. Employing a total of 128 taps, the FIR filtermore » provides greater than 50-dB sharp attenuation in the stopband in order to minimize all out-of-band noise in the low signal-to-noise received radar signal. Fabricated in a 0.18-μm silicon on insulator CMOS process, the proposed filter consumes approximately 3.5 mW/tap with a 1.8-V supply. Finally, a 20-MHz two-tone measurement with 200-kHz tone separation shows IIP3 greater than 8.5 dBm.« less

A novel multi-level IC-compatible surface microfabrication technology for MEMS with independently controlled lateral and vertical submicron transduction gaps

NASA Astrophysics Data System (ADS)

Cicek, Paul-Vahe; Elsayed, Mohannad; Nabki, Frederic; El-Gamal, Mourad

2017-11-01

An above-IC compatible multi-level MEMS surface microfabrication technology based on a silicon carbide structural layer is presented. The fabrication process flow provides optimal electrostatic transduction by allowing the creation of independently controlled submicron vertical and lateral gaps without the need for high resolution lithography. Adopting silicon carbide as the structural material, the technology ensures material, chemical and thermal compatibility with modern semiconductor nodes, reporting the lowest peak processing temperature (i.e. 200 °C) of all comparable works. This makes this process ideally suited for integrating capacitive-based MEMS directly above standard CMOS substrates. Process flow design and optimization are presented in the context of bulk-mode disk resonators, devices that are shown to exhibit improved performance with respect to previous generation flexural beam resonators, and that represent relatively complex MEMS structures. The impact of impending improvements to the fabrication technology is discussed.

The resonant body transistor.

PubMed

Weinstein, Dana; Bhave, Sunil A

2010-04-14

This paper introduces the resonant body transistor (RBT), a silicon-based dielectrically transduced nanoelectromechanical (NEM) resonator embedding a sense transistor directly into the resonator body. Combining the benefits of FET sensing with the frequency scaling capabilities and high quality factors (Q) of internal dielectrically transduced bar resonators, the resonant body transistor achieves >10 GHz frequencies and can be integrated into a standard CMOS process for on-chip clock generation, high-Q microwave circuits, fundamental quantum-state preparation and observation, and high-sensitivity measurements. An 11.7 GHz bulk-mode RBT is demonstrated with a quality factor Q of 1830, marking the highest frequency acoustic resonance measured to date on a silicon wafer.

A research on radiation calibration of high dynamic range based on the dual channel CMOS

NASA Astrophysics Data System (ADS)

Ma, Kai; Shi, Zhan; Pan, Xiaodong; Wang, Yongsheng; Wang, Jianghua

2017-10-01

The dual channel complementary metal-oxide semiconductor (CMOS) can get high dynamic range (HDR) image through extending the gray level of the image by using image fusion with high gain channel image and low gain channel image in a same frame. In the process of image fusion with dual channel, it adopts the coefficients of radiation response of a pixel from dual channel in a same frame, and then calculates the gray level of the pixel in the HDR image. For the coefficients of radiation response play a crucial role in image fusion, it has to find an effective method to acquire these parameters. In this article, it makes a research on radiation calibration of high dynamic range based on the dual channel CMOS, and designs an experiment to calibrate the coefficients of radiation response for the sensor it used. In the end, it applies these response parameters in the dual channel CMOS which calibrates, and verifies the correctness and feasibility of the method mentioned in this paper.

RF Design of a Wideband CMOS Integrated Receiver for Phased Array Applications

NASA Astrophysics Data System (ADS)

Jackson, Suzy A.

2004-06-01

New silicon CMOS processes developed primarily for the burgeoning wireless networking market offer significant promise as a vehicle for the implementation of highly integrated receivers, especially at the lower end of the frequency range proposed for the Square Kilometre Array (SKA). An RF-CMOS ‘Receiver-on-a-Chip’ is being developed as part of an Australia Telescope program looking at technologies associated with the SKA. The receiver covers the frequency range 500 1700 MHz, with instantaneous IF bandwidth of 500 MHz and, on simulation, yields an input noise temperature of < 50 K at mid-band. The receiver will contain all active circuitry (LNA, bandpass filter, quadrature mixer, anti-aliasing filter, digitiser and serialiser) on one 0.18 μm RF-CMOS integrated circuit. This paper outlines receiver front-end development work undertaken to date, including design and simulation of an LNA using noise cancelling techniques to achieve a wideband input-power-match with little noise penalty.

CMOS direct time interval measurement of long-lived luminescence lifetimes.

PubMed

Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-01-01

We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters.

PubMed

Lee, Han Sol; Choi, Kyunghee; Kim, Jin Sung; Yu, Sanghyuck; Ko, Kyeong Rok; Im, Seongil

2017-05-10

We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe 2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 10 4 . Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet-oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics.

ZnO on nickel RF micromechanical resonators for monolithic wireless communication applications

NASA Astrophysics Data System (ADS)

Wei, Mian; Avila, Adrian; Rivera, Ivan; Baghelani, Masoud; Wang, Jing

2017-05-01

On-chip integrability of high-Q RF passives alongside CMOS transistors is crucial for the implementation of monolithic radio transceivers. One of the most significant bottlenecks in back-end-of-line (BEoL) integration of MEMS devices on CMOS processed wafers is their relatively low thermal budget, which is less than that required for typical MEMS material deposition processes. This paper investigates electroplated nickel as a structural material for piezoelectrically-transduced resonators to demonstrate ZnO-on-nickel resonators with a CMOS-compatible low temperature process for the first time. Aside from the obvious manufacturing cost benefit, electroplated nickel is a reasonable substitute for polycrystalline or single crystal silicon and thin-film microcrystalline diamond device layers, while realizing decent acoustic velocity and moderate Q. Electroplated nickel has been already adopted by MEMSCAP, a multi-user MEMS process foundry, in its MetalMUMPs process. Furthermore, it is observed that a localized annealing process through Joule heating can be exploited to significantly improve the effective mechanical quality factor for the ZnO-on-nickel resonators, which is still lower than the reported AlN resonators. This work demonstrates ZnO-on-nickel piezoelectrically-actuated MEMS resonators and resonator arrays by using an IC compatible low temperature process. There is room for performance improvement by lowering the acoustic energy losses in the ZnO and nickel layers.

Amorphous selenium direct detection CMOS digital x-ray imager with 25 micron pixel pitch

NASA Astrophysics Data System (ADS)

Scott, Christopher C.; Abbaszadeh, Shiva; Ghanbarzadeh, Sina; Allan, Gary; Farrier, Michael; Cunningham, Ian A.; Karim, Karim S.

2014-03-01

We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.

HF-Release of Sacrificial Layers in CMOS-integrated MOEMS structures

NASA Astrophysics Data System (ADS)

Döring, S.; Friedrichs, M.; Pufe, W.; Schulze, M.

2016-10-01

In this paper we will present details of the release process of SiO2 sacrificial layers we use within a multi-level MOEMS process developed by IPMS. Using such sacrificial layers gain a lot of benefits necessary for the production of high-end MOEMS devices like high surface quality and great surface planarity. However the HF-release of the sacrificial layer can be connected with specific issues. We present, which mechanisms are involved in the release process and how knowing them, can be the key for an optimized performance of the device. More-over we will present how to protect the CMOS backplane of our devices from unwanted HF attack during the release.

A triple-mode hexa-standard reconfigurable TI cross-coupled ΣΔ modulator

NASA Astrophysics Data System (ADS)

Prakash A. V, Jos; Jose, Babita R.; Mathew, Jimson; Jose, Bijoy A.

2017-07-01

Hardware reconfigurability is an attractive solution for modern multi-standard wireless systems. This paper analyses the performance and implementation of an efficient triple-mode hexa-standard reconfigurable sigma-delta (∑Δ) modulator designed for six different wireless communication standards. Enhanced noise-shaping characteristics and increased digitisation rate, obtained by time-interleaved cross-coupling of ∑Δ paths, have been utilised for the modulator design. Power/hardware efficiency and the capability to acclimate the requirements of wide hexa-standard specifications are achieved by introducing an advanced noise-shaping structure, the dual-extended architecture. Simulation results of the proposed architecture using Hspice shows that the proposed modulator obtains a peak signal-to-noise ratio of 83.4/80.2/67.8/61.5/60.8/51.03 dB for hexa-standards, i.e. GSM/Bluetooth/GPS/WCDMA/WLAN/WiMAX standards with significantly less hardware and low operating frequency. The proposed architecture is implemented in 45 nm CMOS process using a 1 V supply and 0.7 V input range with a power consumption of 1.93 mW. Both architectural- and transistor-level simulation results prove the effectiveness and feasibility of this architecture to accomplish multi-standard cellular communication characteristics.

A new single-photon avalanche diode in 90nm standard CMOS technology.

PubMed

Karami, Mohammad Azim; Gersbach, Marek; Yoon, Hyung-June; Charbon, Edoardo

2010-10-11

We report on the first implementation of a single-photon avalanche diode (SPAD) in 90nm complementary metal oxide semiconductor (CMOS) technology. The detector features an octagonal multiplication region and a guard ring to prevent premature edge breakdown using a standard mask set exclusively. The proposed structure emerged from a systematic study aimed at miniaturization, while optimizing overall performance. The guard ring design is the result of an extensive modeling effort aimed at constraining the multiplication region within a well-defined area where the electric field exceeds the critical value for impact ionization. The device exhibits a dark count rate of 8.1 kHz, a maximum photon detection probability of 9% and the jitter of 398ps at a wavelength of 637nm, all of them measured at room temperature and 0.13V of excess bias voltage. An afterpulsing probability of 32% is achieved at the nominal dead time. Applications include time-of-flight 3D vision, fluorescence lifetime imaging microscopy, fluorescence correlation spectroscopy, and time-resolved gamma/X-ray imaging. Standard characterization of the SPAD was performed in different bias voltages and temperatures.

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

PubMed Central

Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

2008-01-01

A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications. PMID:27873887

Fundamental performance differences between CMOS and CCD imagers: Part II

NASA Astrophysics Data System (ADS)

Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

2007-09-01

A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

Photon counting readout pixel array in 0.18-μm CMOS technology for on-line gamma-ray imaging of 103palladium seeds for permanent breast seed implant (PBSI) brachytherapy

NASA Astrophysics Data System (ADS)

Goldan, A. H.; Karim, K. S.; Reznik, A.; Caldwell, C. B.; Rowlands, J. A.

2008-03-01

Permanent breast seed implant (PBSI) brachytherapy technique was recently introduced as an alternative to high dose rate (HDR) brachytherapy and involves the permanent implantation of radioactive 103Palladium seeds into the surgical cavity of the breast for cancer treatment. To enable accurate seed implantation, this research introduces a gamma camera based on a hybrid amorphous selenium detector and CMOS readout pixel architecture for real-time imaging of 103Palladium seeds during the PBSI procedure. A prototype chip was designed and fabricated in 0.18-μm n-well CMOS process. We present the experimental results obtained from this integrated photon counting readout pixel.

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, X.; Mamaluy, D.; Cyr, E. C.

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE PAGES

Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

2016-05-10

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Development of Integrated Preamplifier for High-Frequency Ultrasonic Transducers and Low-Power Handheld Receiver

PubMed Central

Choi, Hojong; Li, Xiang; Lau, Sien-Ting; Hu, ChangHong; Zhou, Qifa; Shung, K. Kirk

2012-01-01

This paper describes the design of a front-end circuit consisting of an integrated preamplifier with a Sallen-Key Butterworth filter for very-high-frequency ultrasonic transducers and a low-power handheld receiver. This preamplifier was fabricated using a 0.18-μm 7WL SiGe bi-polar complementary metal oxide semiconductor (BiCMOS) process. The Sallen-Key filter is used to increase the voltage gain of the front-end circuit for high-frequency transducers which are generally low in sensitivity. The measured peak voltage gain of the frontend circuits for the BiCMOS preamplifier with the Sallen-Key filter was 41.28 dB at 100 MHz with a −6-dB bandwidth of 91%, and the dc power consumption of the BiCMOS preamplifier was 49.53 mW. The peak voltage gain of the front-end circuits for the CMOS preamplifier with the Sallen-Key filter was 39.52 dB at 100 MHz with a −6-dB bandwidth of 108%, and the dc power consumption of the CMOS preamplifier was 43.57 mW. Pulse-echo responses and wire phantom images with a single-element ultrasonic transducer have been acquired to demonstrate the performance of the front-end circuit. PMID:23443700

Design automation techniques for custom LSI arrays

NASA Technical Reports Server (NTRS)

Feller, A.

1975-01-01

The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Performance and Transient Behavior of Vertically Integrated Thin-film Silicon Sensors

PubMed Central

Wyrsch, Nicolas; Choong, Gregory; Miazza, Clément; Ballif, Christophe

2008-01-01

Vertical integration of amorphous hydrogenated silicon diodes on CMOS readout chips offers several advantages compared to standard CMOS imagers in terms of sensitivity, dynamic range and dark current while at the same time introducing some undesired transient effects leading to image lag. Performance of such sensors is here reported and their transient behaviour is analysed and compared to the one of corresponding amorphous silicon test diodes deposited on glass. The measurements are further compared to simulations for a deeper investigation. The long time constant observed in dark or photocurrent decay is found to be rather independent of the density of defects present in the intrinsic layer of the amorphous silicon diode. PMID:27873778

Importance of ion energy on SEU in CMOS SRAMs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dodd, P.E.; Shaneyfelt, M.R.; Sexton, F.W.

1998-03-01

The single-event upset (SEU) responses of 16 Kbit to 1 Mbit SRAMs irradiated with low and high-energy heavy ions are reported. Standard low-energy heavy ion tests appear to be sufficiently conservative for technologies down to 0.5 {micro}m.

Energy-efficient STDP-based learning circuits with memristor synapses

NASA Astrophysics Data System (ADS)

Wu, Xinyu; Saxena, Vishal; Campbell, Kristy A.

2014-05-01

It is now accepted that the traditional von Neumann architecture, with processor and memory separation, is ill suited to process parallel data streams which a mammalian brain can efficiently handle. Moreover, researchers now envision computing architectures which enable cognitive processing of massive amounts of data by identifying spatio-temporal relationships in real-time and solving complex pattern recognition problems. Memristor cross-point arrays, integrated with standard CMOS technology, are expected to result in massively parallel and low-power Neuromorphic computing architectures. Recently, significant progress has been made in spiking neural networks (SNN) which emulate data processing in the cortical brain. These architectures comprise of a dense network of neurons and the synapses formed between the axons and dendrites. Further, unsupervised or supervised competitive learning schemes are being investigated for global training of the network. In contrast to a software implementation, hardware realization of these networks requires massive circuit overhead for addressing and individually updating network weights. Instead, we employ bio-inspired learning rules such as the spike-timing-dependent plasticity (STDP) to efficiently update the network weights locally. To realize SNNs on a chip, we propose to use densely integrating mixed-signal integrate-andfire neurons (IFNs) and cross-point arrays of memristors in back-end-of-the-line (BEOL) of CMOS chips. Novel IFN circuits have been designed to drive memristive synapses in parallel while maintaining overall power efficiency (<1 pJ/spike/synapse), even at spike rate greater than 10 MHz. We present circuit design details and simulation results of the IFN with memristor synapses, its response to incoming spike trains and STDP learning characterization.

Micromachined ultrasound transducers with improved coupling factors from a CMOS compatible process

PubMed

Eccardt; Niederer

2000-03-01

For medical high frequency acoustic imaging purposes the reduction in size of a single transducer element for one-dimensional and even more for two-dimensional arrays is more and more limited by fabrication and cabling technology. In the fields of industrial distance measurement and simple object recognition low cost phased arrays are lacking. Both problems can be solved with micromachined ultrasound transducers (MUTs). A single transducer is made of a large number of microscopic elements. Because of the array structure of these transducers, groups of elements can be built up and used as a phased array. By integrating parts of the sensor electronics on chip, the cabling effort for arrays can be reduced markedly. In contrast to standard ultrasonic technology, which is based on massive thickness resonators, vibrating membranes are the radiating elements of the MUTs. New micromachining technologies have emerged, allowing a highly reproducible fabrication of electrostatically driven membranes with gap heights below 500 nm. A microelectronic BiCMOS process was extended for surface micromechanics (T. Scheiter et al., Proceedings 11th European Conference on Solid-State Transducers, Warsaw, Vol. 3, 1997, pp. 1595-1598). Additional process steps were included for the realization of the membranes which form sealed cavities with the underlying substrate. Membrane and substrate are the opposite electrodes of a capacitive transducer. The transducers can be integrated monolithically on one chip together with the driving, preamplifying and multiplexing circuitry, thus reducing parasitic capacities and noise level significantly. Owing to their low mass the transducers are very well matched to fluid loads, resulting in a very high bandwidth of 50-100% (C. Eccardt et al., Proceedings Ultrasonics Symposium, San Antonio, Vol. 2, 1996, pp. 959-962; P.C. Eccardt et al., Proceedings of the 1997 Ultrasonics Symposium, Toronto, Vol. 2, 1997, pp. 1609-1618). In the following it is shown how the BiCMOS process has been modified to meet the demands for ultrasound generation and reception. Bias and driving voltages have been reduced down to the 10 V range. The electromechanical coupling is now almost comparable with that for piezoelectric transducers. The measurements exhibit sound pressures and bandwidths that are at least comparable with those of conventional piezoelectric transducer arrays.

Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

NASA Astrophysics Data System (ADS)

Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

2012-01-01

We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

A low jitter all - digital phase - locked loop in 180 nm CMOS technology

NASA Astrophysics Data System (ADS)

Shumkin, O. V.; Butuzov, V. A.; Normanov, D. D.; Ivanov, P. Yu

2016-02-01

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.

Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Y.; Hu-Guo, C.; Husson, D.

2011-07-01

Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial pointsmore » of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)« less

All-digital pulse-expansion-based CMOS digital-to-time converter.

PubMed

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μm Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm 2 . Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

All-digital pulse-expansion-based CMOS digital-to-time converter

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Chu, Che-Hsun

2017-02-01

This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μ m Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Interferometry-based free space communication and information processing

NASA Astrophysics Data System (ADS)

Arain, Muzammil Arshad

This dissertation studies, analyzes, and experimentally demonstrates the innovative use of interference phenomenon in the field of opto-electronic information processing and optical communications. A number of optical systems using interferometric techniques both in the optical and the electronic domains has been demonstrated in the filed of signal transmission and processing, optical metrology, defense, and physical sensors. Specifically it has been shown that the interference of waves in the form of holography can be exploited to realize a novel optical scanner called Code Multiplexed Optical Scanner (C-MOS). The C-MOS features large aperture, wide scan angles, 3-D beam control, no moving parts, and high beam scanning resolution. A C-MOS based free space optical transceiver for bi-directional communication has also been experimentally demonstrated. For high speed, large bandwidth, and high frequency operation, an optically implemented reconfigurable RF transversal filter design is presented that implements wide range of filtering algorithms. A number of techniques using heterodyne interferometry via acousto-optic device for optical path length measurements have been described. Finally, a whole new class of interferometric sensors for optical metrology and sensing applications is presented. A non-traditional interferometric output signal processing scheme has been developed. Applications include, for example, temperature sensors for harsh environments for a wide temperature range from room temperature to 1000°C.

System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

PubMed

Lee, Sung Pil

2015-10-01

Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display.

Design and fabrication of reflective spatial light modulator for high-dynamic-range wavefront control

NASA Astrophysics Data System (ADS)

Zhu, Hao; Bierden, Paul; Cornelissen, Steven; Bifano, Thomas; Kim, Jin-Hong

2004-10-01

This paper describes design and fabrication of a microelectromechanical metal spatial light modulator (SLM) integrated with complementary metal-oxide semiconductor (CMOS) electronics, for high-dynamic-range wavefront control. The metal SLM consists of a large array of piston-motion MEMS mirror segments (pixels) which can deflect up to 0.78 µm each. Both 32x32 and 150x150 arrays of the actuators (1024 and 22500 elements respectively) were fabricated onto the CMOS driver electronics and individual pixels were addressed. A new process has been developed to reduce the topography during the metal MEMS processing to fabricate mirror pixels with improved optical quality.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

Real-time optically sectioned wide-field microscopy employing structured light illumination and a CMOS detector

NASA Astrophysics Data System (ADS)

Mitic, Jelena; Anhut, Tiemo; Serov, Alexandre; Lasser, Theo; Bourquin, Stephane

2003-07-01

Real-time optically sectioned microscopy is demonstrated using an AC-sensitive detection concept realized with smart CMOS image sensor and structured light illumination by a continuously moving periodic pattern. We describe two different detection systems based on CMOS image sensors for the detection and on-chip processing of the sectioned images in real time. A region-of-interest is sampled at high frame rate. The demodulated signal delivered by the detector corresponds to the depth discriminated image of the sample. The measured FWHM of the axial response depends on the spatial frequency of the projected grid illumination and is in the μm-range. The effect of using broadband incoherent illumination is discussed. The performance of these systems is demonstrated by imaging technical as well as biological samples.

Ultralow-Loss CMOS Copper Plasmonic Waveguides.

PubMed

Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

2016-01-13

Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

2015-12-01

This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

CMOS micromachined capacitive cantilevers for mass sensing

NASA Astrophysics Data System (ADS)

Li, Ying-Chung; Ho, Meng-Han; Hung, Shi-Jie; Chen, Meng-Huei; S-C Lu, Michael

2006-12-01

In this paper, we present the design, fabrication and characterization of the CMOS micromachined cantilevers for mass sensing in the femtogram range. The cantilevers consisting of multiple metal and dielectric layers are fabricated after completion of a conventional CMOS process by dry etching steps. The cantilevers are electrostatically actuated to resonance by in-plane electrodes. The mechanical resonant frequency is detected capacitively with on-chip circuitry, where the modulation technique is applied to eliminate capacitive feedthrough from the driving port and to lessen the effect of flicker noise. The highest resonant frequency of the cantilevers is measured at 396.46 kHz with a quality factor of 2600 at 10 mTorr. The resonant frequency shift after deposition of a 0.1 µm SiO2 layer is 140 Hz, averaging 353 fg Hz-1.

Combined reactor neutron beam and {sup 60}Co γ-ray radiation effects on CMOS APS image sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zujun, E-mail: wangzujun@nint.ac.cn; Chen, Wei; Sheng, Jiangkun

The combined reactor neutron beam and {sup 60}Co γ-ray radiation effects on complementary metal-oxide semiconductor (CMOS) active pixel sensors (APS) have been discussed and some new experimental phenomena are presented. The samples are manufactured in the standard 0.35-μm CMOS technology. Two samples were first exposed to {sup 60}Co γ-rays up to the total ionizing dose (TID) level of 200 krad(Si) at the dose rates of 50.0 and 0.2 rad(Si)/s, and then exposed to neutron fluence up to 1 × 10{sup 11} n/cm{sup 2} (1-MeV equivalent neutron fluence). One sample was first exposed to neutron fluence up to 1 × 10{supmore » 11} n/cm{sup 2} (1-MeV equivalent neutron fluence), and then exposed to {sup 60}Co γ-rays up to the TID level of 200 krad(Si) at the dose rate of 0.2 rad(Si)/s. The mean dark signal (K{sub D}), the dark signal non-uniformity (DSNU), and the noise (V{sub N}) versus the total dose and neutron fluence has been investigated. The degradation mechanisms of CMOS APS image sensors have been analyzed, especially for the interaction induced by neutron displacement damage and TID damage.« less

Tuning the thickness of electrochemically grafted layers in large area molecular junctions

NASA Astrophysics Data System (ADS)

Fluteau, T.; Bessis, C.; Barraud, C.; Della Rocca, M. L.; Martin, P.; Lacroix, J.-C.; Lafarge, P.

2014-09-01

We have investigated the thickness, the surface roughness, and the transport properties of oligo(1-(2-bisthienyl)benzene) (BTB) thin films grafted on evaporated Au electrodes, thanks to a diazonium-based electro-reduction process. The thickness of the organic film is tuned by varying the number of electrochemical cycles during the growth process. Atomic force microscopy measurements reveal the evolution of the thickness in the range of 2-27 nm. Its variation displays a linear dependence with the number of cycles followed by a saturation attributed to the insulating behavior of the organic films. Both ultrathin (2 nm) and thin (12 and 27 nm) large area BTB-based junctions have then been fabricated using standard CMOS processes and finally electrically characterized. The electronic responses are fully consistent with a tunneling barrier in case of ultrathin BTB film whereas a pronounced rectifying behavior is reported for thicker molecular films.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

A digital output piezoelectric accelerometer using a Pb(Zr, Ti)O3 thin film array electrically connected in series

NASA Astrophysics Data System (ADS)

Kobayashi, T.; Okada, H.; Masuda, T.; Maeda, R.; Itoh, T.

2010-10-01

A digital output piezoelectric accelerometer is proposed to realize an ultra-low power consumption wireless sensor node. The accelerometer has patterned piezoelectric thin films (piezoelectric plates) electrically connected in series accompanied by CMOS switches at the end of some of the piezoelectric plates. The connected piezoelectric plates amplify the output voltage without the use of amplifiers. The CMOS switches turn on when the output voltage of the piezoelectric plates is higher than the CMOS threshold voltage. The piezoelectric accelerometer converts the acceleration into a number of on-state CMOS switches, which can be called the digital output. The proposed digital output piezoelectric accelerometer, using Pb(Zr, Ti)O3 (PZT) thin films as the piezoelectric material, was fabricated through a microelectromechanical system (MEMS) microfabrication process. The output voltage was found to be amplified by the number of connected piezoelectric plates. The DC output voltage obtained by using an AC to DC conversion circuit is proportional to the number of connections. The results show the potential for realizing the proposed digital output piezoelectric accelerometer.

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

Micron-Scale Differential Scanning Calorimeter on a Chip

DOEpatents

Cavicchi, Richard E; Poirier, Gregory Ernest; Suehle, John S; Gaitan, Michael; Tea, Nim H

1998-06-30

A differential scanning microcalorimeter produced on a silicon chip enables microscopic scanning calorimetry measurements of small samples and thin films. The chip may be fabricated using standard CMOS processes. The microcalorimeter includes a reference zone and a sample zone. The reference and sample zones may be at opposite ends of a suspended platform or may reside on separate platforms. An integrated polysilicon heater provides heat to each zone. A thermopile consisting of a succession of thermocouple junctions generates a voltage representing the temperature difference between the reference and sample zones. Temperature differences between the zones provide information about the chemical reactions and phase transitions that occur in a sample placed in the sample zone.

Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

PubMed

Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

2012-10-29

Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

Architecture, Design and Implementation of RC64, a Many-Core High-Performance DSP for Space Applications

NASA Astrophysics Data System (ADS)

Ginosar, Ran; Aviely, Peleg; Liran, Tuvia; Alon, Dov; Dobkin, Reuven; Goldberg, Michael

2013-08-01

RC64, a novel 64-core many-core signal processing chip targets DSP performance of 12.8 GIPS, 100 GOPS and 12.8 single precision GFLOS while dissipating only 3 Watts. RC64 employs advanced DSP cores, a multi-bank shared memory and a hardware scheduler, supports DDR2 memory and communicates over five proprietary 6.4 Gbps channels. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 is implemented as a 200 MHz ASIC on Tower 130nm CMOS technology, assembled in hermetically sealed ceramic QFP package and qualified to the highest space standards.

Performance Analysis of Visible Light Communication Using CMOS Sensors.

PubMed

Do, Trong-Hop; Yoo, Myungsik

2016-02-29

This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Ultra compact 45 GHz CMOS compatible Germanium waveguide photodiode with low dark current.

PubMed

DeRose, Christopher T; Trotter, Douglas C; Zortman, William A; Starbuck, Andrew L; Fisher, Moz; Watts, Michael R; Davids, Paul S

2011-12-05

We present a compact 1.3 × 4 μm2 Germanium waveguide photodiode, integrated in a CMOS compatible silicon photonics process flow. This photodiode has a best-in-class 3 dB cutoff frequency of 45 GHz, responsivity of 0.8 A/W and dark current of 3 nA. The low intrinsic capacitance of this device may enable the elimination of transimpedance amplifiers in future optical data communication receivers, creating ultra low power consumption optical communications.

Performance Analysis of Visible Light Communication Using CMOS Sensors

PubMed Central

Do, Trong-Hop; Yoo, Myungsik

2016-01-01

This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

1987-01-01

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Low-Loss Photonic Reservoir Computing with Multimode Photonic Integrated Circuits.

PubMed

Katumba, Andrew; Heyvaert, Jelle; Schneider, Bendix; Uvin, Sarah; Dambre, Joni; Bienstman, Peter

2018-02-08

We present a numerical study of a passive integrated photonics reservoir computing platform based on multimodal Y-junctions. We propose a novel design of this junction where the level of adiabaticity is carefully tailored to capture the radiation loss in higher-order modes, while at the same time providing additional mode mixing that increases the richness of the reservoir dynamics. With this design, we report an overall average combination efficiency of 61% compared to the standard 50% for the single-mode case. We demonstrate that with this design, much more power is able to reach the distant nodes of the reservoir, leading to increased scaling prospects. We use the example of a header recognition task to confirm that such a reservoir can be used for bit-level processing tasks. The design itself is CMOS-compatible and can be fabricated through the known standard fabrication procedures.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Detection of cavitated or non-cavitated approximal enamel caries lesions using CMOS and CCD digital X-ray sensors and conventional D and F-speed films at different exposure conditions.

PubMed

Bottenberg, Peter; Jacquet, Wolfgang; Stachniss, Vitus; Wellnitz, Johann; Schulte, Andreas G

2011-04-01

To determine the ability of digital sensors (CMOS and CCD sensors) and D and F-speed films to detect cavitated and non-cavitated enamel caries lesions at different exposure conditions compared to a gold standard. 100 extracted human molars and premolars were selected and mounted in a block between two neighboring teeth. Sensors or films were exposed with voltages of 60 or 70 kVp at varying times. Three observers assessed each approximal site independently. Lesion depth was rated according to an anatomical five-point scale (0 = no lesion to 4 = lesion reaching inner half of dentin). Serial sections of resin-embedded teeth were prepared. Gold-standard scores were established by consensus based on histological sectioning. A carious lesion was present at scores of 1 and higher. Statistical evaluation (sensitivity, specificity and receiver-operating curves) was based on caries-free surfaces and those presenting enamel caries (n=116). The ROC curves had "area under the curve" values (Az) from 0.50 (F-speed, 70 kVp, 0.20 seconds) to 0.58 (CCD 60 kVp, 0.08 seconds). The detection percentage of cavitated lesions was generally higher (0-52%, depending on technique and observer) than that of non-cavitated lesions (3-32%). The CMOS sensor showed Az values comparable to the CCD sensors but required higher exposure times. There was no significant difference between 60 and 70 kVp.

Research-grade CMOS image sensors for remote sensing applications

NASA Astrophysics Data System (ADS)

Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

2004-11-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

PubMed

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

2018-04-05

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing.

PubMed

Karimi-Bidhendi, Alireza; Malekzadeh-Arasteh, Omid; Lee, Mao-Cheng; McCrimmon, Colin M; Wang, Po T; Mahajan, Akshay; Liu, Charles Yu; Nenadic, Zoran; Do, An H; Heydari, Payam

2017-08-01

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

NASA Technical Reports Server (NTRS)

Stahl, R. H.

1977-01-01

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

Modeling and evaluation of a high-resolution CMOS detector for cone-beam CT of the extremities.

PubMed

Cao, Qian; Sisniega, Alejandro; Brehler, Michael; Stayman, J Webster; Yorkston, John; Siewerdsen, Jeffrey H; Zbijewski, Wojciech

2018-01-01

Quantitative assessment of trabecular bone microarchitecture in extremity cone-beam CT (CBCT) would benefit from the high spatial resolution, low electronic noise, and fast scan time provided by complementary metal-oxide semiconductor (CMOS) x-ray detectors. We investigate the performance of CMOS sensors in extremity CBCT, in particular with respect to potential advantages of thin (<0.7 mm) scintillators offering higher spatial resolution. A cascaded systems model of a CMOS x-ray detector incorporating the effects of CsI:Tl scintillator thickness was developed. Simulation studies were performed using nominal extremity CBCT acquisition protocols (90 kVp, 0.126 mAs/projection). A range of scintillator thickness (0.35-0.75 mm), pixel size (0.05-0.4 mm), focal spot size (0.05-0.7 mm), magnification (1.1-2.1), and dose (15-40 mGy) was considered. The detectability index was evaluated for both CMOS and a-Si:H flat-panel detector (FPD) configurations for a range of imaging tasks emphasizing spatial frequencies associated with feature size aobj. Experimental validation was performed on a CBCT test bench in the geometry of a compact orthopedic CBCT system (SAD = 43.1 cm, SDD = 56.0 cm, matching that of the Carestream OnSight 3D system). The test-bench studies involved a 0.3 mm focal spot x-ray source and two CMOS detectors (Dalsa Xineos-3030HR, 0.099 mm pixel pitch) - one with the standard CsI:Tl thickness of 0.7 mm (C700) and one with a custom 0.4 mm thick scintillator (C400). Measurements of modulation transfer function (MTF), detective quantum efficiency (DQE), and CBCT scans of a cadaveric knee (15 mGy) were obtained for each detector. Optimal detectability for high-frequency tasks (feature size of ~0.06 mm, consistent with the size of trabeculae) was ~4× for the C700 CMOS detector compared to the a-Si:H FPD at nominal system geometry of extremity CBCT. This is due to ~5× lower electronic noise of a CMOS sensor, which enables input quantum-limited imaging at smaller pixel size. Optimal pixel size for high-frequency tasks was <0.1 mm for a CMOS, compared to ~0.14 mm for an a-Si:H FPD. For this fine pixel pitch, detectability of fine features could be improved by using a thinner scintillator to reduce light spread blur. A 22% increase in detectability of 0.06 mm features was found for the C400 configuration compared to C700. An improvement in the frequency at 50% modulation (f 50 ) of MTF was measured, increasing from 1.8 lp/mm for C700 to 2.5 lp/mm for C400. The C400 configuration also achieved equivalent or better DQE as C700 for frequencies above ~2 mm -1 . Images of cadaver specimens confirmed improved visualization of trabeculae with the C400 sensor. The small pixel size of CMOS detectors yields improved performance in high-resolution extremity CBCT compared to a-Si:H FPDs, particularly when coupled with a custom 0.4 mm thick scintillator. The results indicate that adoption of a CMOS detector in extremity CBCT can benefit applications in quantitative imaging of trabecular microstructure in humans. © 2017 American Association of Physicists in Medicine.

A CAM-based LZ data compression IC

NASA Technical Reports Server (NTRS)

Winters, K.; Bode, R.; Schneider, E.

1993-01-01

A custom CMOS processor is introduced that implements the Data Compression Lempel-Ziv (DCLZ) standard, a variation of the LZ2 Algorithm. This component presently achieves a sustained compression and decompression rate of 10 megabytes/second by employing an on-chip content-addressable memory for string table storage.

A method for compression of intra-cortically-recorded neural signals dedicated to implantable brain-machine interfaces.

PubMed

Shaeri, Mohammad Ali; Sodagar, Amir M

2015-05-01

This paper proposes an efficient data compression technique dedicated to implantable intra-cortical neural recording devices. The proposed technique benefits from processing neural signals in the Discrete Haar Wavelet Transform space, a new spike extraction approach, and a novel data framing scheme to telemeter the recorded neural information to the outside world. Based on the proposed technique, a 64-channel neural signal processor was designed and prototyped as a part of a wireless implantable extra-cellular neural recording microsystem. Designed in a 0.13- μ m standard CMOS process, the 64-channel neural signal processor reported in this paper occupies ∼ 0.206 mm(2) of silicon area, and consumes 94.18 μW when operating under a 1.2-V supply voltage at a master clock frequency of 1.28 MHz.

An analog neural hardware implementation using charge-injection multipliers and neutron-specific gain control.

PubMed

Massengill, L W; Mundie, D B

1992-01-01

A neural network IC based on a dynamic charge injection is described. The hardware design is space and power efficient, and achieves massive parallelism of analog inner products via charge-based multipliers and spatially distributed summing buses. Basic synaptic cells are constructed of exponential pulse-decay modulation (EPDM) dynamic injection multipliers operating sequentially on propagating signal vectors and locally stored analog weights. Individually adjustable gain controls on each neutron reduce the effects of limited weight dynamic range. A hardware simulator/trainer has been developed which incorporates the physical (nonideal) characteristics of actual circuit components into the training process, thus absorbing nonlinearities and parametric deviations into the macroscopic performance of the network. Results show that charge-based techniques may achieve a high degree of neural density and throughput using standard CMOS processes.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process.

PubMed

Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

2018-01-12

To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke - . Readout noise under the highest pixel gain condition is 1 e - with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7", 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach.

A fully integrated neural recording amplifier with DC input stabilization.

PubMed

Mohseni, Pedram; Najafi, Khalil

2004-05-01

This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least +/- 0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm2 in die area, and dissipates 115 microW from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 microVrms. It is fabricated using AMI 1.5 microm double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes.

Lensless digital holography with diffuse illumination through a pseudo-random phase mask.

PubMed

Bernet, Stefan; Harm, Walter; Jesacher, Alexander; Ritsch-Marte, Monika

2011-12-05

Microscopic imaging with a setup consisting of a pseudo-random phase mask, and an open CMOS camera, without an imaging objective, is demonstrated. The pseudo random phase mask acts as a diffuser for an incoming laser beam, scattering a speckle pattern to a CMOS chip, which is recorded once as a reference. A sample which is afterwards inserted somewhere in the optical beam path changes the speckle pattern. A single (non-iterative) image processing step, comparing the modified speckle pattern with the previously recorded one, generates a sharp image of the sample. After a first calibration the method works in real-time and allows quantitative imaging of complex (amplitude and phase) samples in an extended three-dimensional volume. Since no lenses are used, the method is free from lens abberations. Compared to standard inline holography the diffuse sample illumination improves the axial sectioning capability by increasing the effective numerical aperture in the illumination path, and it suppresses the undesired so-called twin images. For demonstration, a high resolution spatial light modulator (SLM) is programmed to act as the pseudo-random phase mask. We show experimental results, imaging microscopic biological samples, e.g. insects, within an extended volume at a distance of 15 cm with a transverse and longitudinal resolution of about 60 μm and 400 μm, respectively.

Variability of multilevel switching in scaled hybrid RS/CMOS nanoelectronic circuits: theory

NASA Astrophysics Data System (ADS)

Heittmann, Arne; Noll, Tobias G.

2013-07-01

A theory is presented which describes the variability of multilevel switching in scaled hybrid resistive-switching/CMOS nanoelectronic circuits. Variability is quantified in terms of conductance variation using the first two moments derived from the probability density function (PDF) of the RS conductance. For RS, which are based on the electrochemical metallization effect (ECM), this variability is - to some extent - caused by discrete events such as electrochemical reactions, which occur on atomic scale and are at random. The theory shows that the conductance variation depends on the joint interaction between the programming circuit and the resistive switch (RS), and explicitly quantifies the impact of RS device parameters and parameters of the programming circuit on the conductance variance. Using a current mirror as an exemplary programming circuit an upper limit of 2-4 bits (dependent on the filament surface area) is estimated as the storage capacity exploiting the multilevel capabilities of an ECM cell. The theoretical results were verified by Monte Carlo circuit simulations on a standard circuit simulation environment using an ECM device model which models the filament growth by a Poisson process. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process †

PubMed Central

Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

2018-01-01

To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach. PMID:29329210

CMOS-compatible spot-size converter for optical fiber to sub-μm silicon waveguide coupling with low-loss low-wavelength dependence and high tolerance to misalignment

NASA Astrophysics Data System (ADS)

Picard, Marie-Josée.; Latrasse, Christine; Larouche, Carl; Painchaud, Yves; Poulin, Michel; Pelletier, François; Guy, Martin

2016-03-01

One of the biggest challenges of silicon photonics is the efficient coupling of light between the sub-micron SiP waveguides and a standard optical fiber (SMF-28). We recently proposed a novel approach based on a spot-size converter (SSC) that fulfills this need. The SSC integrates a tapered silicon waveguide and a superimposed structure made of a plurality of rods of high index material, disposed in an array-like configuration and embedded in a cladding of lower index material. This superimposed structure defines a waveguide designed to provide an efficient adiabatic transfer, through evanescent coupling, to a 220 nm thick Si waveguide tapered down to a narrow tip on one side, while providing a large mode overlap to the optical fiber on the other side. An initial demonstration was made using a SSC fabricated with post-processing steps. Great coupling to a SMF-28 fiber with a loss of 0.6 dB was obtained for TEpolarized light at 1550 nm with minimum wavelength dependence. In this paper, SSCs designed for operation at 1310 and 1550 nm for TE/TM polarizations and entirely fabricated in a CMOS fab are presented.

Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

NASA Astrophysics Data System (ADS)

Di Pendina, G.; Zianbetov, E.; Beigne, E.

2015-05-01

Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

Optimization of CMOS image sensor utilizing variable temporal multisampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

NASA Astrophysics Data System (ADS)

Kabir, Salman; Smith, Craig; Armstrong, Frank; Barnard, Gerrit; Schneider, Alex; Guidash, Michael; Vogelsang, Thomas; Endsley, Jay

2018-03-01

Differential binary pixel technology is a threshold-based timing, readout, and image reconstruction method that utilizes the subframe partial charge transfer technique in a standard four-transistor (4T) pixel CMOS image sensor to achieve a high dynamic range video with stop motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21 dB. The method is verified in silicon using a Taiwan Semiconductor Manufacturing Company's 65 nm 1.1 μm pixel technology 1 megapixel test chip array and is compared with a traditional 4 × oversampling technique using full charge transfer to show low light SNR superiority of the presented technology.

Triple inverter pierce oscillator circuit suitable for CMOS

DOEpatents

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

NASA Astrophysics Data System (ADS)

Kim, Jungsuk

2016-12-01

This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

PubMed

Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

2013-01-01

One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

High-resolution, continuous field-of-view (FOV), non-rotating imaging system

NASA Technical Reports Server (NTRS)

Huntsberger, Terrance L. (Inventor); Stirbl, Robert C. (Inventor); Aghazarian, Hrand (Inventor); Padgett, Curtis W. (Inventor)

2010-01-01

A high resolution CMOS imaging system especially suitable for use in a periscope head. The imaging system includes a sensor head for scene acquisition, and a control apparatus inclusive of distributed processors and software for device-control, data handling, and display. The sensor head encloses a combination of wide field-of-view CMOS imagers and narrow field-of-view CMOS imagers. Each bank of imagers is controlled by a dedicated processing module in order to handle information flow and image analysis of the outputs of the camera system. The imaging system also includes automated or manually controlled display system and software for providing an interactive graphical user interface (GUI) that displays a full 360-degree field of view and allows the user or automated ATR system to select regions for higher resolution inspection.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 μm technology for the ALICE Inner Tracking System front-end ASIC

NASA Astrophysics Data System (ADS)

Mazza, G.; Aglieri Rinella, G.; Benotto, F.; Corrales Morales, Y.; Kugathasan, T.; Lattuca, A.; Lupi, M.; Ravasenga, I.

2017-02-01

The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 μ m process. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process. The DTU includes a clock multiplier PLL, a double data rate serializer and a pseudo-LVDS driver with pre-emphasis and is designed to be SEU tolerant.

A simple and low-cost biofilm quantification method using LED and CMOS image sensor.

PubMed

Kwak, Yeon Hwa; Lee, Junhee; Lee, Junghoon; Kwak, Soo Hwan; Oh, Sangwoo; Paek, Se-Hwan; Ha, Un-Hwan; Seo, Sungkyu

2014-12-01

A novel biofilm detection platform, which consists of a cost-effective red, green, and blue light-emitting diode (RGB LED) as a light source and a lens-free CMOS image sensor as a detector, is designed. This system can measure the diffraction patterns of cells from their shadow images, and gather light absorbance information according to the concentration of biofilms through a simple image processing procedure. Compared to a bulky and expensive commercial spectrophotometer, this platform can provide accurate and reproducible biofilm concentration detection and is simple, compact, and inexpensive. Biofilms originating from various bacterial strains, including Pseudomonas aeruginosa (P. aeruginosa), were tested to demonstrate the efficacy of this new biofilm detection approach. The results were compared with the results obtained from a commercial spectrophotometer. To utilize a cost-effective light source (i.e., an LED) for biofilm detection, the illumination conditions were optimized. For accurate and reproducible biofilm detection, a simple, custom-coded image processing algorithm was developed and applied to a five-megapixel CMOS image sensor, which is a cost-effective detector. The concentration of biofilms formed by P. aeruginosa was detected and quantified by varying the indole concentration, and the results were compared with the results obtained from a commercial spectrophotometer. The correlation value of the results from those two systems was 0.981 (N = 9, P < 0.01) and the coefficients of variation (CVs) were approximately threefold lower at the CMOS image-sensor platform. Copyright © 2014 Elsevier B.V. All rights reserved.

A cochlear implant fabricated using a bulk silicon-surface micromachining process

NASA Astrophysics Data System (ADS)

Bell, Tracy Elizabeth

1999-11-01

This dissertation presents the design and fabrication of two generations of a silicon microelectrode array for use in a cochlear implant. A cochlear implant is a device that is inserted into the inner ear and uses electrical stimulation to provide sound sensations to the profoundly deaf. The first-generation silicon cochlear implant is a passive device fabricated using silicon microprobe technology developed at the University of Michigan. It contains twenty-two iridium oxide (IrO) stimulating sites that are 250 mum in diameter and spaced at 750 mum intervals. In-vivo recordings were made in guinea pig auditory cortex in response to electrical stimulation with this device, verifying its ability to electrically evoke an auditory response. Auditory thresholds as low as 78 muA were recorded. The second-generation implant is a thirty-two site, four-channel device with on-chip CMOS site-selection circuitry and integrated position sensing. It was fabricated using a novel bulk silicon surface micromachining process which was developed as a part of this dissertation work. While the use of semiconductor technology offers many advantages in fabricating cochlear implants over the methods currently used, it was felt that even further advantages could be gained by developing a new micromachining process which would allow circuitry to be distributed along the full length of the cochlear implant substrate. The new process uses electropolishing of an n+ bulk silicon sacrificial layer to undercut and release n- epitaxial silicon structures from the wafer. An extremely abrupt etch-stop between the n+ and n- silicon is obtained, with no electropolishing taking place in the n-type silicon that is doped lower than 1 x 1017 cm-3 in concentration. Lateral electropolishing rates of up to 50 mum/min were measured using this technique, allowing one millimeter-wide structures to be fully undercut in as little as 10 minutes. The new micromachining process was integrated with a standard p-well CMOS integrated circuit process to fabricate the second-generation active silicon cochlear implants.

Machine Learning Based Single-Frame Super-Resolution Processing for Lensless Blood Cell Counting

PubMed Central

Huang, Xiwei; Jiang, Yu; Liu, Xu; Xu, Hang; Han, Zhi; Rong, Hailong; Yang, Haiping; Yan, Mei; Yu, Hao

2016-01-01

A lensless blood cell counting system integrating microfluidic channel and a complementary metal oxide semiconductor (CMOS) image sensor is a promising technique to miniaturize the conventional optical lens based imaging system for point-of-care testing (POCT). However, such a system has limited resolution, making it imperative to improve resolution from the system-level using super-resolution (SR) processing. Yet, how to improve resolution towards better cell detection and recognition with low cost of processing resources and without degrading system throughput is still a challenge. In this article, two machine learning based single-frame SR processing types are proposed and compared for lensless blood cell counting, namely the Extreme Learning Machine based SR (ELMSR) and Convolutional Neural Network based SR (CNNSR). Moreover, lensless blood cell counting prototypes using commercial CMOS image sensors and custom designed backside-illuminated CMOS image sensors are demonstrated with ELMSR and CNNSR. When one captured low-resolution lensless cell image is input, an improved high-resolution cell image will be output. The experimental results show that the cell resolution is improved by 4×, and CNNSR has 9.5% improvement over the ELMSR on resolution enhancing performance. The cell counting results also match well with a commercial flow cytometer. Such ELMSR and CNNSR therefore have the potential for efficient resolution improvement in lensless blood cell counting systems towards POCT applications. PMID:27827837

Challenges of nickel silicidation in CMOS technologies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet

2015-04-01

In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of themore » nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.« less

Development of on-line laser power monitoring system

NASA Astrophysics Data System (ADS)

Ding, Chien-Fang; Lee, Meng-Shiou; Li, Kuan-Ming

2016-03-01

Since the laser was invented, laser has been applied in many fields such as material processing, communication, measurement, biomedical engineering, defense industries and etc. Laser power is an important parameter in laser material processing, i.e. laser cutting, and laser drilling. However, the laser power is easily affected by the environment temperature, we tend to monitor the laser power status, ensuring there is an effective material processing. Besides, the response time of current laser power meters is too long, they cannot measure laser power accurately in a short time. To be more precisely, we can know the status of laser power and help us to achieve an effective material processing at the same time. To monitor the laser power, this study utilize a CMOS (Complementary metal-oxide-semiconductor) camera to develop an on-line laser power monitoring system. The CMOS camera captures images of incident laser beam after it is split and attenuated by beam splitter and neutral density filter. By comparing the average brightness of the beam spots and measurement results from laser power meter, laser power can be estimated. Under continuous measuring mode, the average measuring error is about 3%, and the response time is at least 3.6 second shorter than thermopile power meters; under trigger measuring mode which enables the CMOS camera to synchronize with intermittent laser output, the average measuring error is less than 3%, and the shortest response time is 20 millisecond.

Amorphous silicon as high index photonic material

NASA Astrophysics Data System (ADS)

Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

2009-05-01

Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

VLSI design of lossless frame recompression using multi-orientation prediction

NASA Astrophysics Data System (ADS)

Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo

2016-01-01

Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.

Improved Space Object Orbit Determination Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario a sensor in a sun-synchronous LEO orbit, always pointing in the anti-sun direction to achieve optimum illumination conditions for small LEO debris, was simulated. For the space-based scenario the simulations showed a 20 130 % improvement of the accuracy of all orbital parameters when varying the frame rate from 1/3 fps, which is the fastest rate for a typical CCD detector, to 50 fps, which represents the highest rate of scientific CMOS cameras. Changing the epoch registration accuracy from a typical 20.0 ms for a mechanical shutter to 0.025 ms, the theoretical value for the electronic shutter of a CMOS camera, improved the orbit accuracy by 4 to 190 %. The ground-based scenario also benefit from the specific CMOS characteristics, but to a lesser extent.

Radiation Characteristics of a 0.11 Micrometer Modified Commercial CMOS Process

NASA Technical Reports Server (NTRS)

Poivey, Christian; Kim, Hak; Berg, Melanie D.; Forney, Jim; Seidleck, Christina; Vilchis, Miguel A.; Phan, Anthony; Irwin, Tim; LaBel, Kenneth A.; Saigusa, Rajan K.;