a Study of Oxygen Precipitation in Heavily Doped Silicon.

NASA Astrophysics Data System (ADS)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

Single-crystal silicon optical fiber by direct laser crystallization

DOE PAGES

Ji, Xiaoyu; Lei, Shiming; Yu, Shih -Ying; ...

2016-12-05

Semiconductor core optical fibers with a silica cladding are of great interest in nonlinear photonics and optoelectronics applications. Laser crystallization has been recently demonstrated for crystallizing amorphous silicon fibers into crystalline form. Here we explore the underlying mechanism by which long single-crystal silicon fibers, which are novel platforms for silicon photonics, can be achieved by this process. Using finite element modeling, we construct a laser processing diagram that reveals a parameter space within which single crystals can be grown. Utilizing this diagram, we illustrate the creation of single-crystal silicon core fibers by laser crystallizing amorphous silicon deposited inside silica capillarymore » fibers by high-pressure chemical vapor deposition. The single-crystal fibers, up to 5.1 mm long, have a very welldefined core/cladding interface and a chemically pure silicon core that leads to very low optical losses down to ~0.47-1dB/cm at the standard telecommunication wavelength (1550 nm). Furthermore, tt also exhibits a photosensitivity that is comparable to bulk silicon. Creating such laser processing diagrams can provide a general framework for developing single-crystal fibers in other materials of technological importance.« less

Silicon on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Pickering, C.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon was investigated. It was hoped this could be done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Work was directed towards the solution of unique cell processing/design problems encountered with the silicon-ceramic (SOC) material due to its intimate contact with the ceramic substrate. Significant progress was demonstrated in the following areas; (1) the continuous coater succeeded in producing small-area coatings exhibiting unidirectional solidification and substatial grain size; (2) dip coater succeeded in producing thick (more than 500 micron) dendritic layers at coating speeds of 0.2-0.3 cm/sec; and (3) a standard for producing total area SOC solar cells using slotted ceramic substrates was developed.

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

PubMed Central

Hazut, Ori; Agarwala, Arunava; Subramani, Thangavel; Waichman, Sharon; Yerushalmi, Roie

2013-01-01

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms. In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station. PMID:24326774

Design, fabrication and characterization of a poly-silicon PN junction

NASA Astrophysics Data System (ADS)

Tower, Jason D.

This thesis details the design, fabrication, and characterization of a PN junction formed from p-type mono-crystalline silicon and n-type poly-crystalline silicon. The primary product of this project was a library of standard operating procedures (SOPs) for the fabrication of such devices, laying the foundations for future work and the development of a class in fabrication processes. The fabricated PN junction was characterized; in particular its current-voltage relationship was measured and fit to models. This characterization was to determine whether or not the fabrication process could produce working PN junctions with acceptable operational parameters.

Rapid Prototyping of Nanofluidic Slits in a Silicone Bilayer

PubMed Central

Kole, Thomas P.; Liao, Kuo-Tang; Schiffels, Daniel; Ilic, B. Robert; Strychalski, Elizabeth A.; Kralj, Jason G.; Liddle, J. Alexander; Dritschilo, Anatoly; Stavis, Samuel M.

2015-01-01

This article reports a process for rapidly prototyping nanofluidic devices, particularly those comprising slits with microscale widths and nanoscale depths, in silicone. This process consists of designing a nanofluidic device, fabricating a photomask, fabricating a device mold in epoxy photoresist, molding a device in silicone, cutting and punching a molded silicone device, bonding a silicone device to a glass substrate, and filling the device with aqueous solution. By using a bilayer of hard and soft silicone, we have formed and filled nanofluidic slits with depths of less than 400 nm and aspect ratios of width to depth exceeding 250 without collapse of the slits. An important attribute of this article is that the description of this rapid prototyping process is very comprehensive, presenting context and details which are highly relevant to the rational implementation and reliable repetition of the process. Moreover, this process makes use of equipment commonly found in nanofabrication facilities and research laboratories, facilitating the broad adaptation and application of the process. Therefore, while this article specifically informs users of the Center for Nanoscale Science and Technology (CNST) at the National Institute of Standards and Technology (NIST), we anticipate that this information will be generally useful for the nanofabrication and nanofluidics research communities at large, and particularly useful for neophyte nanofabricators and nanofluidicists. PMID:26958449

Solubilization and spore recovery from silicone polymers. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Hsiao, Y. C.

1974-01-01

A non-sporicidal technique for solvent degradation of cured silicone polymers was developed which involves chemical degradation of cured silicone polymers by amine solvents at room temperature. Substantial improvements were obtained in the recovery of seeded spores from room temperature cured polymers as compared to the standard recovery procedures, which indicates that the curing process is not sufficiently exothermic to reduce spore viability. The dissolution reaction of cured silicone polymers whith amine solvents is proposed to occur by bimolecular nucleophilic displacement. The chemical structure of silicone polymers was determined by spectroscopic methods. The phenyl to methyl ratio, R/Si ratio, molecular weight, and hydroxyl content of the silicone resins were determined.

Numerical analysis of thermal stress and dislocation density distributions in large size multi-crystalline silicon ingots during the seeded growth process

NASA Astrophysics Data System (ADS)

Nguyen, Thi Hoai Thu; Chen, Jyh-Chen; Hu, Chieh; Chen, Chun-Hung; Huang, Yen-Hao; Lin, Huang-Wei; Yu, Andy; Hsu, Bruce

2017-06-01

In this study, a global transient numerical simulation of silicon growth from the beginning of the solidification process until the end of the cooling process is carried out modeling the growth of an 800 kg ingot in an industrial seeded directional solidification furnace. The standard furnace is modified by the addition of insulating blocks in the hot zone. The simulation results show that there is a significant decrease in the thermal stress and dislocation density in the modified model as compared to the standard one (a maximal decrease of 23% and 75% along the center line of ingot for thermal stress and dislocation density, respectively). This modification reduces the heating power consumption for solidification of the silicon melt by about 17% and shortens the growth time by about 2.5 h. Moreover, it is found that adjusting the operating conditions of modified model to obtain the lower growth rate during the early stages of the solidification process can lower dislocation density and total heater power.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

Nanostructure size determination in p-type porous silicon by the use of transmission electron diffraction image processing

NASA Astrophysics Data System (ADS)

Ramirez-Porras, A.

2005-06-01

The structure of p-type porous silicon (PS) has been investigated by the use of transmission electron diffraction (TED) microscopy and image processing. The results suggest the presence of well oriented crystalline phases and polycrystalline phases characterized by random orientation. These phases are believed to be formed by spheres with a mean diameter of 4.3 nm and a standard deviation of 1.3 nm.

Determination of a Definition of Solar Grade Silicon

NASA Technical Reports Server (NTRS)

Hill, D. E.; Gutsche, H. W.

1975-01-01

A definition of solar grade silicon was determined by investigating the singular and the combined effect of the impurities usually found in metallurgical grade silicon on solar cell device performance. The impurity matrix was defined by Jet Propulsion Laboratory Technical Direction Memorandum. The initial work was focussed on standardizing the solar cell process and test procedure, growing baseline crystals, growing crystals contaminated with carbon, iron, nickel, zirconium, aluminum and vanadium, solar blank preparation, and material characterization.

An all-silicon optical PC-to-PC link utilizing USB

NASA Astrophysics Data System (ADS)

Goosen, Marius E.; Alberts, Antonie C.; Venter, Petrus J.; du Plessis, Monuko; Rademeyer, Pieter

2013-02-01

An integrated silicon light source still remains the Holy Grail for integrated optical communication systems. Hot carrier luminescent light sources provide a way to create light in a standard CMOS process, potentially enabling cost effective optical communication between CMOS integrated circuits. In this paper we present a 1 Mb/s integrated silicon optical link for information transfer, targeting a real-world integrated solution by connecting two PCs via a USB port while transferring data optically between the devices. This realization represents the first optical communication product prototype utilizing a CMOS light emitter. The silicon light sources which are implemented in a standard 0.35 μm CMOS technology are electrically modulated and detected using a commercial silicon avalanche photodiode. Data rates exceeding 10 Mb/s using silicon light sources have previously been demonstrated using raw bit streams. In this work data is sent in two half duplex streams accompanied with the separate transmission of a clock. Such an optical communication system could find application in high noise environments where data fidelity, range and cost are a determining factor.

Single-Run Single-Mask Inductively-Coupled-Plasma Reactive-Ion-Etching Process for Fabricating Suspended High-Aspect-Ratio Microstructures

NASA Astrophysics Data System (ADS)

Yang, Yao-Joe; Kuo, Wen-Cheng; Fan, Kuang-Chao

2006-01-01

In this work, we present a single-run single-mask (SRM) process for fabricating suspended high-aspect-ratio structures on standard silicon wafers using an inductively coupled plasma-reactive ion etching (ICP-RIE) etcher. This process eliminates extra fabrication steps which are required for structure release after trench etching. Released microstructures with 120 μm thickness are obtained by this process. The corresponding maximum aspect ratio of the trench is 28. The SRM process is an extended version of the standard process proposed by BOSCH GmbH (BOSCH process). The first step of the SRM process is a standard BOSCH process for trench etching, then a polymer layer is deposited on trench sidewalls as a protective layer for the subsequent structure-releasing step. The structure is released by dry isotropic etching after the polymer layer on the trench floor is removed. All the steps can be integrated into a single-run ICP process. Also, only one mask is required. Therefore, the process complexity and fabrication cost can be effectively reduced. Discussions on each SRM step and considerations for avoiding undesired etching of the silicon structures during the release process are also presented.

Low-loss slot waveguides with silicon (111) surfaces realized using anisotropic wet etching

NASA Astrophysics Data System (ADS)

Debnath, Kapil; Khokhar, Ali; Boden, Stuart; Arimoto, Hideo; Oo, Swe; Chong, Harold; Reed, Graham; Saito, Shinichi

2016-11-01

We demonstrate low-loss slot waveguides on silicon-on-insulator (SOI) platform. Waveguides oriented along the (11-2) direction on the Si (110) plane were first fabricated by a standard e-beam lithography and dry etching process. A TMAH based anisotropic wet etching technique was then used to remove any residual side wall roughness. Using this fabrication technique propagation loss as low as 3.7dB/cm was realized in silicon slot waveguide for wavelengths near 1550nm. We also realized low propagation loss of 1dB/cm for silicon strip waveguides.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Silicon micro-mold

DOEpatents

Morales, Alfredo M [Livermore, CA

2006-10-24

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Mathematical model of silicon smelting process basing on pelletized charge from technogenic raw materials

NASA Astrophysics Data System (ADS)

Nemchinova, N. V.; Tyutrin, A. A.; Salov, V. M.

2018-03-01

The silicon production process in the electric arc reduction furnaces (EAF) is studied using pelletized charge as an additive to the standard on the basis of the generated mathematical model. The results obtained due to the model will contribute to the analysis of the charge components behavior during melting with the achievement of optimum final parameters of the silicon production process. The authors proposed using technogenic waste as a raw material for the silicon production in a pelletized form using liquid glass and aluminum production dust from the electrostatic precipitators as a binder. The method of mathematical modeling with the help of the ‘Selector’ software package was used as a basis for the theoretical study. A model was simulated with the imitation of four furnace temperature zones and a crystalline silicon phase (25 °C). The main advantage of the created model is the ability to analyze the behavior of all burden materials (including pelletized charge) in the carbothermic process. The behavior analysis is based on the thermodynamic probability data of the burden materials interactions in the carbothermic process. The model accounts for 17 elements entering the furnace with raw materials, electrodes and air. The silicon melt, obtained by the modeling, contained 91.73 % wt. of the target product. The simulation results showed that in the use of the proposed combined charge, the recovery of silicon reached 69.248 %, which is in good agreement with practical data. The results of the crystalline silicon chemical composition modeling are compared with the real silicon samples of chemical analysis data, which showed the results of convergence. The efficiency of the mathematical modeling methods in the studying of the carbothermal silicon obtaining process with complex interphase transformations and the formation of numerous intermediate compounds using a pelletized charge as an additive to the traditional one is shown.

A cochlear implant fabricated using a bulk silicon-surface micromachining process

NASA Astrophysics Data System (ADS)

Bell, Tracy Elizabeth

1999-11-01

This dissertation presents the design and fabrication of two generations of a silicon microelectrode array for use in a cochlear implant. A cochlear implant is a device that is inserted into the inner ear and uses electrical stimulation to provide sound sensations to the profoundly deaf. The first-generation silicon cochlear implant is a passive device fabricated using silicon microprobe technology developed at the University of Michigan. It contains twenty-two iridium oxide (IrO) stimulating sites that are 250 mum in diameter and spaced at 750 mum intervals. In-vivo recordings were made in guinea pig auditory cortex in response to electrical stimulation with this device, verifying its ability to electrically evoke an auditory response. Auditory thresholds as low as 78 muA were recorded. The second-generation implant is a thirty-two site, four-channel device with on-chip CMOS site-selection circuitry and integrated position sensing. It was fabricated using a novel bulk silicon surface micromachining process which was developed as a part of this dissertation work. While the use of semiconductor technology offers many advantages in fabricating cochlear implants over the methods currently used, it was felt that even further advantages could be gained by developing a new micromachining process which would allow circuitry to be distributed along the full length of the cochlear implant substrate. The new process uses electropolishing of an n+ bulk silicon sacrificial layer to undercut and release n- epitaxial silicon structures from the wafer. An extremely abrupt etch-stop between the n+ and n- silicon is obtained, with no electropolishing taking place in the n-type silicon that is doped lower than 1 x 1017 cm-3 in concentration. Lateral electropolishing rates of up to 50 mum/min were measured using this technique, allowing one millimeter-wide structures to be fully undercut in as little as 10 minutes. The new micromachining process was integrated with a standard p-well CMOS integrated circuit process to fabricate the second-generation active silicon cochlear implants.

Surface-micromachined 2D optical scanners with optically flat single-crystalline silicon micromirrors

NASA Astrophysics Data System (ADS)

Su, John G.; Patterson, Pamela R.; Wu, Ming C.

2001-05-01

We have developed a novel wafer-scale single-crystalline silicon micromirror bonding process to fabricate optically flat micromirrors on polysilicon surface-micromachined 2D scanners. The electrostatically actuated 2D scanner has a mirror area of 450 micrometers x 450 micrometers and an optical scan angle of +/- +/-7.5 degree(s). Compared to micromirrors made with a standard polysilicon surface-micromachining process, the radius of curvature of the micromirror has been improved by 1 50 times from 1.8 cm to 265 cm, with surface roughness < 10 nm. Besides, single-crystalline honeycomb micromirrors derived from silicon on insulator (SOI) have been developed to reduce the mass of the bonded mirror.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Single-crystal silicon trench etching for fabrication of highly integrated circuits

NASA Astrophysics Data System (ADS)

Engelhardt, Manfred

1991-03-01

The development of single crystal silicon trench etching for fabrication of memory cells in 4 16 and 64Mbit DRAMs is reviewed in this paper. A variety of both etch tools and process gases used for the process development is discussed since both equipment and etch chemistry had to be improved and changed respectively to meet the increasing requirements for high fidelity pattern transfer with increasing degree of integration. In additon to DRAM cell structures etch results for deep trench isolation in advanced bipolar ICs and ASICs are presented for these applications grooves were etched into silicon through a highly doped buried layer and at the borderline of adjacent p- and n-well areas respectively. Shallow trench etching of large and small exposed areas with identical etch rates is presented as an approach to replace standard LOCOS isolation by an advanced isolation technique. The etch profiles were investigated with SEM TEM and AES to get information on contathination and damage levels and on the mechanism leading to anisotropy in the dry etch process. Thermal wave measurements were performed on processed single crystal silicon substrates for a fast evaluation of the process with respect to plasma-induced substrate degradation. This useful technique allows an optimization ofthe etch process regarding high electrical performance of the fully processed memory chip. The benefits of the use of magnetic fields for the development of innovative single crystal silicon dry

IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

2015-08-01

SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2011-06-08

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Optoelectronic properties of Black-Silicon generated through inductively coupled plasma (ICP) processing for crystalline silicon solar cells

NASA Astrophysics Data System (ADS)

Hirsch, Jens; Gaudig, Maria; Bernhard, Norbert; Lausch, Dominik

2016-06-01

The optoelectronic properties of maskless inductively coupled plasma (ICP) generated black silicon through SF6 and O2 are analyzed by using reflection measurements, scanning electron microscopy (SEM) and quasi steady state photoconductivity (QSSPC). The results are discussed and compared to capacitively coupled plasma (CCP) and industrial standard wet chemical textures. The ICP process forms parabolic like surface structures in a scale of 500 nm. This surface structure reduces the average hemispherical reflection between 300 and 1120 nm up to 8%. Additionally, the ICP texture shows a weak increase of the hemispherical reflection under tilted angles of incidence up to 60°. Furthermore, we report that the ICP process is independent of the crystal orientation and the surface roughness. This allows the texturing of monocrystalline, multicrystalline and kerf-less wafers using the same parameter set. The ICP generation of black silicon does not apply a self-bias on the silicon sample. Therefore, the silicon sample is exposed to a reduced ion bombardment, which reduces the plasma induced surface damage. This leads to an enhancement of the effective charge carrier lifetime up to 2.5 ms at 1015 cm-3 minority carrier density (MCD) after an atomic layer deposition (ALD) with Al2O3. Since excellent etch results were obtained already after 4 min process time, we conclude that the ICP generation of black silicon is a promising technique to substitute the industrial state of the art wet chemical textures in the solar cell mass production.

The development of a method of producing etch resistant wax patterns on solar cells

NASA Technical Reports Server (NTRS)

Pastirik, E.

1980-01-01

A potentially attractive technique for wax masking of solar cells prior to etching processes was studied. This technique made use of a reuseable wax composition which was applied to the solar cell in patterned form by means of a letterpress printing method. After standard wet etching was performed, wax removal by means of hot water was investigated. Application of the letterpress wax printing process to silicon was met with a number of difficulties. The most serious shortcoming of the process was its inability to produce consistently well-defined printed patterns on the hard silicon cell surface.

Control of the interaction strength of photonic molecules by nanometer precise 3D fabrication.

PubMed

Rawlings, Colin D; Zientek, Michal; Spieser, Martin; Urbonas, Darius; Stöferle, Thilo; Mahrt, Rainer F; Lisunova, Yuliya; Brugger, Juergen; Duerig, Urs; Knoll, Armin W

2017-11-28

Applications for high resolution 3D profiles, so-called grayscale lithography, exist in diverse fields such as optics, nanofluidics and tribology. All of them require the fabrication of patterns with reliable absolute patterning depth independent of the substrate location and target materials. Here we present a complete patterning and pattern-transfer solution based on thermal scanning probe lithography (t-SPL) and dry etching. We demonstrate the fabrication of 3D profiles in silicon and silicon oxide with nanometer scale accuracy of absolute depth levels. An accuracy of less than 1nm standard deviation in t-SPL is achieved by providing an accurate physical model of the writing process to a model-based implementation of a closed-loop lithography process. For transfering the pattern to a target substrate we optimized the etch process and demonstrate linear amplification of grayscale patterns into silicon and silicon oxide with amplification ratios of ∼6 and ∼1, respectively. The performance of the entire process is demonstrated by manufacturing photonic molecules of desired interaction strength. Excellent agreement of fabricated and simulated structures has been achieved.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

PubMed

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Ion beam figuring of silicon aspheres

NASA Astrophysics Data System (ADS)

Demmler, Marcel; Zeuner, Michael; Luca, Alfonz; Dunger, Thoralf; Rost, Dirk; Kiontke, Sven; Krüger, Marcus

2011-03-01

Silicon lenses are widely used for infrared applications. Especially for portable devices the size and weight of the optical system are very important factors. The use of aspherical silicon lenses instead of spherical silicon lenses results in a significant reduction of weight and size. The manufacture of silicon lenses is more challenging than the manufacture of standard glass lenses. Typically conventional methods like diamond turning, grinding and polishing are used. However, due to the high hardness of silicon, diamond turning is very difficult and requires a lot of experience. To achieve surfaces of a high quality a polishing step is mandatory within the manufacturing process. Nevertheless, the required surface form accuracy cannot be achieved through the use of conventional polishing methods because of the unpredictable behavior of the polishing tools, which leads to an unstable removal rate. To overcome these disadvantages a method called Ion Beam Figuring can be used to manufacture silicon lenses with high surface form accuracies. The general advantage of the Ion Beam Figuring technology is a contactless polishing process without any aging effects of the tool. Due to this an excellent stability of the removal rate without any mechanical surface damage is achieved. The related physical process - called sputtering - can be applied to any material and is therefore also applicable to materials of high hardness like Silicon (SiC, WC). The process is realized through the commercially available ion beam figuring system IonScan 3D. During the process, the substrate is moved in front of a focused broad ion beam. The local milling rate is controlled via a modulated velocity profile, which is calculated specifically for each surface topology in order to mill the material at the associated positions to the target geometry. The authors will present aspherical silicon lenses with very high surface form accuracies compared to conventionally manufactured lenses.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

Flat-plate solar array project process development area: Process research of non-CZ silicon material

NASA Technical Reports Server (NTRS)

Campbell, R. B.

1986-01-01

Several different techniques to simultaneously diffuse the front and back junctions in dendritic web silicon were investigated. A successful simultaneous diffusion reduces the cost of the solar cell by reducing the number of processing steps, the amount of capital equipment, and the labor cost. The three techniques studied were: (1) simultaneous diffusion at standard temperatures and times using a tube type diffusion furnace or a belt furnace; (2) diffusion using excimer laser drive-in; and (3) simultaneous diffusion at high temperature and short times using a pulse of high intensity light as the heat source. The use of an excimer laser and high temperature short time diffusion experiment were both more successful than the diffusion at standard temperature and times. The three techniques are described in detail and a cost analysis of the more successful techniques is provided.

Porous silicon micro-resonator implemented by standard photolithography process for sensing application

NASA Astrophysics Data System (ADS)

Girault, P.; Azuelos, P.; Lorrain, N.; Poffo, L.; Lemaitre, J.; Pirasteh, P.; Hardy, I.; Thual, M.; Guendouz, M.; Charrier, J.

2017-10-01

A micro-resonator based on porous silicon ridge waveguides is implemented by a large scale standard photolithography process to obtain a low cost and sensitive sensor based on volume detection principle instead of the evanescent one usually used. The porous nature of the ridge waveguides allows the target molecules to be infiltrated in the core and to be detected by direct interaction with the propagated light. Racetrack resonator with radius of 100 μm and a coupling length of 70 μm is optically characterized for the volume detection of different concentrations of glucose. A high sensitivity of 560 nm/RIU is reached with only one micro-resonator and a limit of detection of 8.10-5 RIU, equivalent to a glucose concentration of 0.7 g/L, is obtained.

High-speed detection at two micrometres with monolithic silicon photodiodes

NASA Astrophysics Data System (ADS)

Ackert, Jason J.; Thomson, David J.; Shen, Li; Peacock, Anna C.; Jessop, Paul E.; Reed, Graham T.; Mashanovich, Goran Z.; Knights, Andrew P.

2015-06-01

With continued steep growth in the volume of data transmitted over optical networks there is a widely recognized need for more sophisticated photonics technologies to forestall a ‘capacity crunch’. A promising solution is to open new spectral regions at wavelengths near 2 μm and to exploit the long-wavelength transmission and amplification capabilities of hollow-core photonic-bandgap fibres and the recently available thulium-doped fibre amplifiers. To date, photodetector devices for this window have largely relied on III-V materials or, where the benefits of integration with silicon photonics are sought, GeSn alloys, which have been demonstrated thus far with only limited utility. Here, we describe a silicon photodiode operating at 20 Gbit s-1 in this wavelength region. The detector is compatible with standard silicon processing and is integrated directly with silicon-on-insulator waveguides, which suggests future utility in silicon-based mid-infrared integrated optics for applications in communications.

A quantitative comparison of resolution, scanning speed and lifetime behavior of CVD grown Single Wall Carbon Nanotubes and silicon SPM probes using spectral methods

NASA Astrophysics Data System (ADS)

Krause, O.; Bouchiat, V.; Bonnot, A. M.

2007-03-01

Due to their extreme aspect ratios and exceptional mechanical properties Carbon Nanotubes terminated silicon probes have proven to be the ''ideal'' probe for Atomic Force Microscopy. But especially for the manufacturing and use of Single Walled Carbon Nanotubes there are serious problems, which have not been solved until today. Here, Single and Double Wall Carbon Nanotubes, batch processed and used as deposited by Chemical Vapor Deposition without any postprocessing, are compared to standard and high resolution silicon probes concerning resolution, scanning speed and lifetime behavior.

Graphoepitaxy integration and pattern transfer of lamellar silicon-containing high-chi block copolymers

NASA Astrophysics Data System (ADS)

Bézard, P.; Chevalier, X.; Legrain, A.; Navarro, C.; Nicolet, C.; Fleury, G.; Cayrefourcq, I.; Tiron, R.; Zelsmann, M.

2018-03-01

In this work, we present our recent achievements on the integration and transfer etching of a novel silicon-containing high-χ block copolymer for lines/spaces applications. Developed carbo-silane BCPs are synthesized under industrial conditions and present periodicities as low as 14 nm. A full directed self-assembly by graphoepitaxy process is shown using standard photolithography stacks and all processes are performed on 300 mm wafer compatible tools. Specific plasma processes are developed to isolate perpendicular lamellae and sub-12 nm features are finally transferred into silicon substrates. The quality of the final BCP hard mask (CDU, LWR, LER) are also investigated. Finally, thanks to the development of dedicated neutral layers and top-coats allowing perpendicular orientations, it was possible to investigate plasma etching experiments on full-sheets at 7 nm resolution, opening the way to the integration of these polymers in chemoepitaxy stacks.

Development of standardized specifications for silicon solar cells

NASA Technical Reports Server (NTRS)

Scott-Monck, J. A.

1977-01-01

A space silicon solar cell assembly (cell and coverglass) specification aimed at standardizing the diverse requirements of current cell or assembly specifications was developed. This specification was designed to minimize both the procurement and manufacturing costs for space qualified silicon solar cell assembilies. In addition, an impact analysis estimating the technological and economic effects of employing a standardized space silicon solar cell assembly was performed.

An innovative large scale integration of silicon nanowire-based field effect transistors

NASA Astrophysics Data System (ADS)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Process for Smoothing an Si Substrate after Etching of SiO2

NASA Technical Reports Server (NTRS)

Turner, Tasha; Wu, Chi

2003-01-01

A reactive-ion etching (RIE) process for smoothing a silicon substrate has been devised. The process is especially useful for smoothing those silicon areas that have been exposed by etching a pattern of holes in a layer of silicon dioxide that covers the substrate. Applications in which one could utilize smooth silicon surfaces like those produced by this process include fabrication of optical waveguides, epitaxial deposition of silicon on selected areas of silicon substrates, and preparation of silicon substrates for deposition of adherent metal layers. During etching away of a layer of SiO2 that covers an Si substrate, a polymer becomes deposited on the substrate, and the substrate surface becomes rough (roughness height approximately equal to 50 nm) as a result of over-etching or of deposition of the polymer. While it is possible to smooth a silicon substrate by wet chemical etching, the undesired consequences of wet chemical etching can include compromising the integrity of the SiO2 sidewalls and undercutting of the adjacent areas of the silicon dioxide that are meant to be left intact. The present RIE process results in anisotropic etching that removes the polymer and reduces height of roughness of the silicon substrate to less than 10 nm while leaving the SiO2 sidewalls intact and vertical. Control over substrate versus sidewall etching (in particular, preferential etching of the substrate) is achieved through selection of process parameters, including gas flow, power, and pressure. Such control is not uniformly and repeatably achievable in wet chemical etching. The recipe for the present RIE process is the following: Etch 1 - A mixture of CF4 and O2 gases flowing at rates of 25 to 75 and 75 to 125 standard cubic centimeters per minute (stdcm3/min), respectively; power between 44 and 55 W; and pressure between 45 and 55 mtorr (between 6.0 and 7.3 Pa). The etch rate lies between approximately equal to 3 and approximately equal to 6 nm/minute. Etch 2 - O2 gas flowing at 75 to 125 stdcm3/min, power between 44 and 55 W, and pressure between 50 and 100 mtorr (between 6.7 and 13.3 Pa).

Response of murine bone marrow-derived mesenchymal stromal cells to dry-etched porous silicon scaffolds.

PubMed

Hajj-Hassan, Mohamad; Khayyat-Kholghi, Maedeh; Wang, Huifen; Chodavarapu, Vamsy; Henderson, Janet E

2011-11-01

Porous silicon shows great promise as a bio-interface material due to its large surface to volume ratio, its stability in aqueous solutions and to the ability to precisely regulate its pore characteristics. In the current study, porous silicon scaffolds were fabricated from single crystalline silicon wafers by a novel xenon difluoride dry etching technique. This simplified dry etch fabrication process allows selective formation of porous silicon using a standard photoresist as mask material and eliminates the post-formation drying step typically required for the wet etching techniques, thereby reducing the risk of damaging the newly formed porous silicon. The porous silicon scaffolds supported the growth of primary cultures of bone marrow derived mesenchymal stromal cells (MSC) plated at high density for up to 21 days in culture with no significant loss of viability, assessed using Alamar Blue. Scanning electron micrographs confirmed a dense lawn of cells at 9 days of culture and the presence of MSC within the pores of the porous silicon scaffolds. Copyright © 2011 Wiley Periodicals, Inc.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip

PubMed Central

Schuck, C.; Guo, X.; Fan, L.; Ma, X.; Poot, M.; Tang, H. X.

2016-01-01

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips. PMID:26792424

Passively aligned multichannel fiber-pigtailing of planar integrated optical waveguides

NASA Astrophysics Data System (ADS)

Kremmel, Johannes; Lamprecht, Tobias; Crameri, Nino; Michler, Markus

2017-02-01

A silicon device to simplify the coupling of multiple single-mode fibers to embedded single-mode waveguides has been developed. The silicon device features alignment structures that enable a passive alignment of fibers to integrated waveguides. For passive alignment, precisely machined V-grooves on a silicon device are used and the planar lightwave circuit board features high-precision structures acting as a mechanical stop. The approach has been tested for up to eight fiber-to-waveguide connections. The alignment approach, the design, and the fabrication of the silicon device as well as the assembly process are presented. The characterization of the fiber-to-waveguide link reveals total coupling losses of (0.45±0.20 dB) per coupling interface, which is significantly lower than the values reported in earlier works. Subsequent climate tests reveal that the coupling losses remain stable during thermal cycling but increases significantly during an 85°C/85 Rh-test. All applied fabrication and bonding steps have been performed using standard MOEMS fabrication and packaging processes.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boccard, Mathieu; Holman, Zachary C.

Amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphous silicon carbide beingmore » shown to surpass amorphous silicon for temperatures above 300 °C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boccard, Mathieu; Holman, Zachary C.

With this study, amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphousmore » silicon carbide being shown to surpass amorphous silicon for temperatures above 300°C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Amorphous silicon carbide passivating layers for crystalline-silicon-based heterojunction solar cells

DOE PAGES

Boccard, Mathieu; Holman, Zachary C.

2015-08-14

With this study, amorphous silicon enables the fabrication of very high-efficiency crystalline-silicon-based solar cells due to its combination of excellent passivation of the crystalline silicon surface and permeability to electrical charges. Yet, amongst other limitations, the passivation it provides degrades upon high-temperature processes, limiting possible post-deposition fabrication possibilities (e.g., forcing the use of low-temperature silver pastes). We investigate the potential use of intrinsic amorphous silicon carbide passivating layers to sidestep this issue. The passivation obtained using device-relevant stacks of intrinsic amorphous silicon carbide with various carbon contents and doped amorphous silicon are evaluated, and their stability upon annealing assessed, amorphousmore » silicon carbide being shown to surpass amorphous silicon for temperatures above 300°C. We demonstrate open-circuit voltage values over 700 mV for complete cells, and an improved temperature stability for the open-circuit voltage. Transport of electrons and holes across the hetero-interface is studied with complete cells having amorphous silicon carbide either on the hole-extracting side or on the electron-extracting side, and a better transport of holes than of electrons is shown. Also, due to slightly improved transparency, complete solar cells using an amorphous silicon carbide passivation layer on the hole-collecting side are demonstrated to show slightly better performances even prior to annealing than obtained with a standard amorphous silicon layer.« less

Waveguide silicon nitride grating coupler

NASA Astrophysics Data System (ADS)

Litvik, Jan; Dolnak, Ivan; Dado, Milan

2016-12-01

Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

NASA Astrophysics Data System (ADS)

Bisadi, Zahra; Acerbi, Fabio; Fontana, Giorgio; Zorzi, Nicola; Piemonte, Claudio; Pucker, Georg; Pavesi, Lorenzo

2018-02-01

A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED) coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST) suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

Porous silicon technology for integrated microsystems

NASA Astrophysics Data System (ADS)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially rough surface on the porous silicon sample without introducing significant thermal stress. (Abstract shortened by UMI.)

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

PubMed Central

López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

PubMed

López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

2011-01-01

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Drake, G.; Garcia-Scivres, M.; Paramonov, A.

We propose to use silicon photonics technology to build radiation-hard fiber-optic links for high-bandwidth readout of tracking detectors. The CMOS integrated silicon photonics was developed by Luxtera and commercialized by Molex. The commercial off-the-shelf (COTS) fiber-optic links feature moderate radiation tolerance insufficient for trackers. A transceiver contains four RX and four TX channels operating at 10 Gbps each. The next generation will likely operate at 25 Gbps per channel. The approach uses a standard CMOS process and single-mode fibers, providing low power consumption and good scalability and reliability.

How the new optoelectronic design automation industry is taking advantage of preexisting EDA standards

NASA Astrophysics Data System (ADS)

Nesmith, Kevin A.; Carver, Susan

2014-05-01

With the advancements in design processes down to the sub 7nm levels, the Electronic Design Automation industry appears to be coming to an end of advancements, as the size of the silicon atom becomes the limiting factor. Or is it? The commercial viability of mass-producing silicon photonics is bringing about the Optoelectronic Design Automation (OEDA) industry. With the science of photonics in its infancy, adding these circuits to ever-increasing complex electronic designs, will allow for new generations of advancements. Learning from the past 50 years of the EDA industry's mistakes and missed opportunities, the photonics industry is starting with electronic standards and extending them to become photonically aware. Adapting the use of pre-existing standards into this relatively new industry will allow for easier integration into the present infrastructure and faster time to market.

Stability and rheology of dispersions of silicon nitride and silicon carbide

NASA Technical Reports Server (NTRS)

Feke, Donald L.

1987-01-01

The relationship between the surface and colloid chemistry of commercial ultra-fine silicon carbide and silicon nitride powders was examined by a variety of standard characterization techniques and by methodologies especially developed for ceramic dispersions. These include electrokinetic measurement, surface titration, and surface spectroscopies. The effects of powder pretreatment and modification strategies, which can be utilized to augment control of processing characteristics, were monitored with these technologies. Both silicon carbide and nitride were found to exhibit silica-like surface chemistries, but silicon nitride powders possess an additional amine surface functionality. Colloidal characteristics of the various nitride powders in aqueous suspension is believed to be highly dependent on the relative amounts of the two types of surface groups, which in turn is determined by the powder synthesis route. The differences in the apparent colloidal characteristics for silicon nitride powders cannot be attributed to the specific absorption of ammonium ions. Development of a model for the prediction of double-layer characteristics of materials with a hybrid site interface facilitated understanding and prediction of the behavior of both surface charge and surface potential for these materials. The utility of the model in application to silicon nitride powders was demonstrated.

Yield enhancement with DFM

NASA Astrophysics Data System (ADS)

Paek, Seung Weon; Kang, Jae Hyun; Ha, Naya; Kim, Byung-Moo; Jang, Dae-Hyun; Jeon, Junsu; Kim, DaeWook; Chung, Kun Young; Yu, Sung-eun; Park, Joo Hyun; Bae, SangMin; Song, DongSup; Noh, WooYoung; Kim, YoungDuck; Song, HyunSeok; Choi, HungBok; Kim, Kee Sup; Choi, Kyu-Myung; Choi, Woonhyuk; Jeon, JoongWon; Lee, JinWoo; Kim, Ki-Su; Park, SeongHo; Chung, No-Young; Lee, KangDuck; Hong, YoungKi; Kim, BongSeok

2012-03-01

A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.

Nanofabrication on unconventional substrates using transferred hard masks

DOE PAGES

Li, Luozhou; Bayn, Igal; Lu, Ming; ...

2015-01-15

Here, a major challenge in nanofabrication is to pattern unconventional substrates that cannot be processed for a variety of reasons, such as incompatibility with spin coating, electron beam lithography, optical lithography, or wet chemical steps. Here, we present a versatile nanofabrication method based on re-usable silicon membrane hard masks, patterned using standard lithography and mature silicon processing technology. These masks, transferred precisely onto targeted regions, can be in the millimetre scale. They allow for fabrication on a wide range of substrates, including rough, soft, and non-conductive materials, enabling feature linewidths down to 10 nm. Plasma etching, lift-off, and ion implantationmore » are realized without the need for scanning electron/ion beam processing, UV exposure, or wet etching on target substrates.« less

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Determination of the implantation dose in silicon wafers by X-ray fluorescence analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klockenkaemper, R.; Becker, M.; Bubert, H.

1990-08-01

The ion dose implanted in silicon wafers was determined by X-ray fluorescence analysis after the implantation process. As only near-surface layers below 1-{mu}m thickness were considered, the calibration could be carried out with external standards consisting of thin films of doped gelatine spread on pure wafers. Dose values for Cr and Co were determined between 4 {times} 10{sup 15} and 2 {times} 10{sup 17} atoms/cm{sup 2}, the detection limits being about 3 {times} 10{sup 14} atoms/cm{sup 2}. The results are precise and accurate apart from a residual scatter of less than 7%. This was confirmed by flame atomic absorption spectrometrymore » after volatilization of the silicon matrix as SiF{sub 4}. It was found that ion-current measurements carried out during the implantation process can have considerable systematic errors.« less

Micro-Raman spectroscopy as a tool for the characterization of silicon carbide in power semiconductor material processing

NASA Astrophysics Data System (ADS)

De Biasio, M.; Kraft, M.; Schultz, M.; Goller, B.; Sternig, D.; Esteve, R.; Roesner, M.

2017-05-01

Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

Phosphorus Diffusion Gettering Efficacy in Upgraded Metallurgical-Grade Solar Silicon

NASA Astrophysics Data System (ADS)

Jiménez, A.; del Cañizo, C.; Cid, C.; Peral, A.

2018-05-01

In the context of the continuous price reduction in photovoltaics (PV) in recent years, Si feedstock continues to be a relevant component in the cost breakdown of a PV module, highlighting the need for low-cost, low-capital expenditure (CAPEX) silicon technologies to further reduce this cost component. Upgraded metallurgical-grade silicon (UMG Si) has recently received much attention, improving its quality and even attaining, in some cases, solar cell efficiencies similar to those of conventional material. However, some technical challenges still have to be addressed when processing this material to compensate efficiently for the high content of impurities and contaminants. Adaptation of a conventional solar cell process to monocrystalline UMG Si wafers has been studied in this work. In particular, a tailored phosphorus diffusion gettering step followed by a low-temperature anneal at 700°C was implemented, resulting in enhanced bulk lifetime and emitter recombination properties. In spite of the need for further research and material optimization, UMG Si wafers were successfully processed, achieving efficiencies in the range of 15% for a standard laboratory solar cell process with aluminum back surface field.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

Silicon based nanogap device for studying electrical transport phenomena in molecule-nanoparticle hybrids.

PubMed

Strobel, Sebastian; Hernández, Rocío Murcia; Hansen, Allan G; Tornow, Marc

2008-09-17

We report the fabrication and characterization of vertical nanogap electrode devices using silicon-on-insulator substrates. Using only standard silicon microelectronic process technology, nanogaps down to 26 nm electrode separation were prepared. Transmission electron microscopy cross-sectional analysis revealed the well defined material architecture of the nanogap, comprising two electrodes of dissimilar geometrical shape. This asymmetry is directly reflected in transport measurements on molecule-nanoparticle hybrid systems formed by self-assembling a monolayer of mercaptohexanol on the electrode surface and the subsequent dielectrophoretic trapping of 30 nm diameter Au nanoparticles. The observed Coulomb staircase I-V characteristic measured at T = 4.2 K is in excellent agreement with theoretical modelling, whereby junction capacitances of the order of a few 10(-18) farad and asymmetric resistances of 30 and 300 MΩ, respectively, are also supported well by our independent estimates for the formed double barrier tunnelling system. We propose our nanoelectrode system for integrating novel functional electronic devices such as molecular junctions or nanoparticle hybrids into existing silicon microelectronic process technology.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Measurement of Quantum Interference in a Silicon Ring Resonator Photon Source.

PubMed

Steidle, Jeffrey A; Fanto, Michael L; Preble, Stefan F; Tison, Christopher C; Howland, Gregory A; Wang, Zihao; Alsing, Paul M

2017-04-04

Silicon photonic chips have the potential to realize complex integrated quantum information processing circuits, including photon sources, qubit manipulation, and integrated single-photon detectors. Here, we present the key aspects of preparing and testing a silicon photonic quantum chip with an integrated photon source and two-photon interferometer. The most important aspect of an integrated quantum circuit is minimizing loss so that all of the generated photons are detected with the highest possible fidelity. Here, we describe how to perform low-loss edge coupling by using an ultra-high numerical aperture fiber to closely match the mode of the silicon waveguides. By using an optimized fusion splicing recipe, the UHNA fiber is seamlessly interfaced with a standard single-mode fiber. This low-loss coupling allows the measurement of high-fidelity photon production in an integrated silicon ring resonator and the subsequent two-photon interference of the produced photons in a closely integrated Mach-Zehnder interferometer. This paper describes the essential procedures for the preparation and characterization of high-performance and scalable silicon quantum photonic circuits.

Membrane transfer of crystalline silicon thin film solar cells

NASA Astrophysics Data System (ADS)

Vempati, Venkata Kesari Nandan

Silicon has been dominating the solar industry for many years and has been touted as the gold standard of the photovoltaic world. The factors for its dominance: government subsidies and ease of processing. Silicon holds close to 90% of the market share in the material being used for solar cell production. Of which 14% belongs to single-crystalline Silicon. Although 24% efficient bulk crystalline solar cells have been reported, the industry has been looking for thin film alternatives to reduce the cost of production. Moreover with the new avenues like flexible consumer electronics opening up, there is a need to introduce the flexibility into the solar cells. Thin film films make up for their inefficiency keeping their mechanical properties intact by incorporating Anti-reflective schemes such as surface texturing, textured back reflectors and low reflective surfaces. This thesis investigates the possibility of using thin film crystalline Silicon for fabricating solar cells and has demonstrated a low cost and energy efficient way for fabricating 2microm thick single crystalline Silicon solar cells with an efficiency of 0.8% and fill factor of 35%.

High-temperature electronics

NASA Technical Reports Server (NTRS)

Seng, Gary T.

1987-01-01

In recent years, there was a growing need for electronics capable of sustained high-temperature operation for aerospace propulsion system instrumentation, control and condition monitoring, and integrated sensors. The desired operating temperature in some applications exceeds 600 C, which is well beyond the capability of currently available semiconductor devices. Silicon carbide displays a number of properties which make it very attractive as a semiconductor material, one of which is the ability to retain its electronic integrity at temperatures well above 600 C. An IR-100 award was presented to NASA Lewis in 1983 for developing a chemical vapor deposition process to grow single crystals of this material on standard silicon wafers. Silicon carbide devices were demonstrated above 400 C, but much work remains in the areas of crystal growth, characterization, and device fabrication before the full potential of silicon carbide can be realized. The presentation will conclude with current and future high-temperature electronics program plans. Although the development of silicon carbide falls into the category of high-risk research, the future looks promising, and the potential payoffs are tremendous.

Silicone substrate with in situ strain relief for stretchable thin-film transistors

NASA Astrophysics Data System (ADS)

Graz, Ingrid M.; Cotton, Darryl P. J.; Robinson, Adam; Lacour, Stéphanie P.

2011-03-01

We have manufactured stretchable thin-film transistors and interconnects directly onto an engineered silicone matrix with localized and graded mechanical compliance. The fabrication only involves planar and standard processing. Brittle active device materials are patterned on non deformable elastomer regions (strain <1% at all times) while interconnects run smoothly from "stiff" to "soft" elastomer. Pentacene thin-film transistors sustain applied strain up to 13% without electrical degradation and mechanical fracture. This integrated approach opens promising options for the manufacture of physically adaptable and transformable circuitry.

X-ray mask and method for providing same

DOEpatents

Morales, Alfredo M [Pleasanton, CA; Skala, Dawn M [Fremont, CA

2004-09-28

The present invention describes a method for fabricating an x-ray mask tool which can achieve pattern features having lateral dimension of less than 1 micron. The process uses a thin photoresist and a standard lithographic mask to transfer an trace image pattern in the surface of a silicon wafer by exposing and developing the resist. The exposed portion of the silicon substrate is then anisotropically etched to provide an etched image of the trace image pattern consisting of a series of channels in the silicon having a high depth-to-width aspect ratio. These channels are then filled by depositing a metal such as gold to provide an inverse image of the trace image and thereby providing a robust x-ray mask tool.

X-ray mask and method for providing same

DOEpatents

Morales, Alfredo M.; Skala, Dawn M.

2002-01-01

The present invention describes a method for fabricating an x-ray mask tool which can achieve pattern features having lateral dimension of less than 1 micron. The process uses a thin photoresist and a standard lithographic mask to transfer an trace image pattern in the surface of a silicon wafer by exposing and developing the resist. The exposed portion of the silicon substrate is then anisotropically etched to provide an etched image of the trace image pattern consisting of a series of channels in the silicon having a high depth-to-width aspect ratio. These channels are then filled by depositing a metal such as gold to provide an inverse image of the trace image and thereby providing a robust x-ray mask tool.

Methods of producing strain in a semiconductor waveguide and related devices

DOEpatents

Cox, Johathan Albert; Rakich, Peter Thomas

2016-02-16

Quasi-phase matched (QPM), semiconductor photonic waveguides include periodically-poled alternating first and second sections. The first sections exhibit a high degree of optical coupling (abbreviated "X.sup.2"), while the second sections have a low X.sup.2. The alternating first and second sections may comprise high-strain and low-strain sections made of different material states (such as crystalline and amorphous material states) that exhibit high and low X.sup.2 properties when formed on a particular substrate, and/or strained corrugated sections of different widths. The QPM semiconductor waveguides may be implemented as silicon-on-insulator (SOI), or germanium-on-silicon structures compatible with standard CMOS processes, or as silicon-on-sapphire (SOS) structures.

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project. Third quarterly report, September 20, 1976--December 19, 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holden, S.C.

1976-12-27

The stability of tensioned blades used in multiblade sawing does not seem to be the limitation in cutting with thin blades. So far, 0.010 cm thick blades have been totally unsuccessful. Recently, 0.015 cm blades have proven successful in wafering, offering an 0.005 cm reduction in the silicon used per slice. The failure of thin blades is characterized as a possible result of blade misalignment or from the inherent uncontrollability of the loose abrasive multiblade process. Corrective procedures will be employed in the assembly of packages to eliminate one type of blade misalignment. Two ingots were sliced with the samemore » batch of standard silicon carbide abrasive slurry to determine the useful lifetime of this expendable material. After 250 slices, the cutting efficiency had not degraded. Further tests will be continued to establish the maximum lifetime of both silicon carbide and boron carbide abrasive. Electron microscopy will be employed to evaluate the wear of abrasive particles in the failure of abrasive slurry. The surface damage of silicon wafers has been characterized as predominantly subsurface fracture. Damage with No. 600 SiC is between 10 and 15 microns into the wafer surface. This agrees well with previous investigations of damage from silicon carbide abrasive papers.« less

Effect of Fermentation Broths on Performance of Hydrophobic Zeolite-Silicone Rubber Mixed Matrix Pervaporation Membranes

EPA Science Inventory

Fermentative organisms produce a range of compounds in addition to the desired product. For example, in addition to ethanol, standard yeast produce longer straight-chained and branched alcohols and organic acids. Additionally, biomass pretreatment process, particularly acid-bas...

Micrometer-scale fabrication of complex three dimensional lattice + basis structures in silicon

DOE PAGES

Burckel, D. Bruce; Resnick, Paul J.; Finnegan, Patrick S.; ...

2015-01-01

A complementary metal oxide semiconductor (CMOS) compatible version of membrane projection lithography (MPL) for fabrication of micrometer-scale three-dimensional structures is presented. The approach uses all inorganic materials and standard CMOS processing equipment. In a single layer, MPL is capable of creating all 5 2D-Bravais lattices. Furthermore, standard semiconductor processing steps can be used in a layer-by-layer approach to create fully three dimensional structures with any of the 14 3D-Bravais lattices. The unit cell basis is determined by the projection of the membrane pattern, with many degrees of freedom for defining functional inclusions. Here we demonstrate several unique structural motifs, andmore » characterize 2D arrays of unit cells with split ring resonators in a silicon matrix. The structures exhibit strong polarization dependent resonances and, for properly oriented split ring resonators (SRRs), coupling to the magnetic field of a normally incident transverse electromagnetic wave, a response unique to 3D inclusions.« less

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

ELAS - SCIENCE & TECHNOLOGY LABORATORY APPLICATIONS SOFTWARE (SILICON GRAPHICS VERSION)

NASA Technical Reports Server (NTRS)

Walters, D.

1994-01-01

The Science and Technology Laboratory Applications Software (ELAS) was originally designed to analyze and process digital imagery data, specifically remotely-sensed scanner data. This capability includes the processing of Landsat multispectral data; aircraft-acquired scanner data; digitized topographic data; and numerous other ancillary data, such as soil types and rainfall information, that can be stored in digitized form. ELAS has the subsequent capability to geographically reference this data to dozens of standard, as well as user created projections. As an integrated image processing system, ELAS offers the user of remotely-sensed data a wide range of capabilities in the areas of land cover analysis and general purpose image analysis. ELAS is designed for flexible use and operation and includes its own FORTRAN operating subsystem and an expandable set of FORTRAN application modules. Because all of ELAS resides in one "logical" FORTRAN program, data inputs and outputs, directives, and module switching are convenient for the user. There are over 230 modules presently available to aid the user in performing a wide range of land cover analyses and manipulation. The file management modules enable the user to allocate, define, access, and specify usage for all types of files (ELAS files, subfiles, external files etc.). Various other modules convert specific types of satellite, aircraft, and vector-polygon data into files that can be used by other ELAS modules. The user also has many module options which aid in displaying image data, such as magnification/reduction of the display; true color display; and several memory functions. Additional modules allow for the building and manipulation of polygonal areas of the image data. Finally, there are modules which allow the user to select and classify the image data. An important feature of the ELAS subsystem is that its structure allows new applications modules to be easily integrated in the future. ELAS has as a standard the flexibility to process data elements exceeding 8 bits in length, including floating point (noninteger) elements and 16 or 32 bit integers. Thus it is able to analyze and process "non-standard" nonimage data. The VAX (ERL-10017) and Concurrent (ERL-10013) versions of ELAS 9.0 are written in FORTRAN and ASSEMBLER for DEC VAX series computers running VMS and Concurrent computers running MTM. The Sun (SSC-00019), Masscomp (SSC-00020), and Silicon Graphics (SSC-00021) versions of ELAS 9.0 are written in FORTRAN 77 and C-LANGUAGE for Sun4 series computers running SunOS, Masscomp computers running UNIX, and Silicon Graphics IRIS computers running IRIX. The Concurrent version requires at least 15 bit addressing and a direct memory access channel. The VAX and Concurrent versions of ELAS both require floating-point hardware, at least 1Mb of RAM, and approximately 70Mb of disk space. Both versions also require a COMTAL display device in order to display images. For the Sun, Masscomp, and Silicon Graphics versions of ELAS, the disk storage required is approximately 115Mb, and a minimum of 8Mb of RAM is required for execution. The Sun version of ELAS requires either the X-Window System Version 11 Revision 4 or Sun OpenWindows Version 2. The Masscomp version requires a GA1000 display device and the associated "gp" library. The Silicon Graphics version requires Silicon Graphics' GL library. ELAS display functions will not work with a monochrome monitor. The standard distribution medium for the VAX version (ERL10017) is a set of two 9-track 1600 BPI magnetic tapes in DEC VAX BACKUP format. This version is also available on a TK50 tape cartridge in DEC VAX BACKUP format. The standard distribution medium for the Concurrent version (ERL-10013) is a set of two 9-track 1600 BPI magnetic tapes in Concurrent BACKUP format. The standard distribution medium for the Sun version (SSC-00019) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Masscomp version, (SSC-00020) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Silicon Graphics version (SSC-00021) is a .25 inch streaming magnetic IRIS tape cartridge in UNIX tar format. Version 9.0 was released in 1991. Sun4, SunOS, and Open Windows are trademarks of Sun Microsystems, Inc. MIT X Window System is licensed by Massachusetts Institute of Technology.

Optimizing photon-pair generation electronically using a p-i-n diode incorporated in a silicon microring resonator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Savanier, Marc, E-mail: msavanier@eng.ucsd.edu; Kumar, Ranjeet; Mookherjea, Shayan, E-mail: smookherjea@eng.ucsd.edu

Silicon photonic microchips may be useful for compact, inexpensive, room-temperature optically pumped photon-pair sources, which unlike conventional photon-pair generators based on crystals or optical fibers, can be manufactured using CMOS-compatible processes on silicon wafers. It has been shown that photon pairs can be created in simple structures such as microring resonators at a rate of a few hundred kilohertz using less than a milliwatt of optical pump power, based on the process of spontaneous four-wave mixing. To create a practical photon-pair source, however, also requires some way of monitoring the device and aligning the pump wavelength when the temperature varies,more » since silicon resonators are highly sensitive to temperature. In fact, monitoring photodiodes are standard components in classical laser diodes, but the incorporation of germanium or InGaAs photodiodes would raise the cost and fabrication complexity. Here, we present a simple and effective all-electronic technique for finding the optimum operating point for the microring used to generate photon pairs, based on measuring the reverse-biased current in a silicon p-i-n junction diode fabricated across the waveguide that constitutes the silicon microring. We show that by monitoring the current, and using it to tune the pump laser wavelength, the photon-pair generation properties of the microring can be preserved over a temperature range of more than 30 °C.« less

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Significant accomplishments during this reporting period include design of a plan to provide standard silicon wafers for four-probe resistivity measurements for the industry, publication of a summary report on the photoconductive decay method for measuring carrier lifetime, publication of a comprehensive review of the field of wire bond fabrication and testing, and successful completion of organizational activity leading to the establishment of a new group on quality and hardness assurance in ASTM Committee F-1 on Electronics. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers in silicon; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

A novel multi-level IC-compatible surface microfabrication technology for MEMS with independently controlled lateral and vertical submicron transduction gaps

NASA Astrophysics Data System (ADS)

Cicek, Paul-Vahe; Elsayed, Mohannad; Nabki, Frederic; El-Gamal, Mourad

2017-11-01

An above-IC compatible multi-level MEMS surface microfabrication technology based on a silicon carbide structural layer is presented. The fabrication process flow provides optimal electrostatic transduction by allowing the creation of independently controlled submicron vertical and lateral gaps without the need for high resolution lithography. Adopting silicon carbide as the structural material, the technology ensures material, chemical and thermal compatibility with modern semiconductor nodes, reporting the lowest peak processing temperature (i.e. 200 °C) of all comparable works. This makes this process ideally suited for integrating capacitive-based MEMS directly above standard CMOS substrates. Process flow design and optimization are presented in the context of bulk-mode disk resonators, devices that are shown to exhibit improved performance with respect to previous generation flexural beam resonators, and that represent relatively complex MEMS structures. The impact of impending improvements to the fabrication technology is discussed.

Ultra Low Outgassing silicone performance in a simulated space ionizing radiation environment

NASA Astrophysics Data System (ADS)

Velderrain, M.; Malave, V.; Taylor, E. W.

2010-09-01

The improvement of silicone-based materials used in space and aerospace environments has garnered much attention for several decades. Most recently, an Ultra Low Outgassing™ silicone incorporating innovative reinforcing and functional fillers has shown that silicone elastomers with unique and specific properties can be developed to meet applications requiring stringent outgassing requirements. This paper will report on the next crucial step in qualifying these materials for spacecraft applications requiring chemical and physical stability in the presence of ionizing radiation. As a first step in this process, selected materials were irradiated with Co-60 gamma-rays to simulate the total dose received in near- Earth orbits. The paper will present pre-and post-irradiation response data of Ultra Low Outgassing silicone samples exposed under ambient air environment coupled with measurements of collected volatile condensable material (CVCM) and total mass loss (TML) per the standard conditions in ASTM E 595. The data will show an insignificant effect on the CVCMs and TMLs after exposure to various dosages of gamma radiation. This data may favorably impact new applications for these silicone materials for use as an improved sealant for space solar cell systems, space structures, satellite systems and aerospace systems.

Integration of mask and silicon metrology in DFM

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Sugiyama, Akiyuki; Toyoda, Yasutaka

2009-03-01

We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Optimization and characterization of biomolecule immobilization on silicon substrates using (3-aminopropyl)triethoxysilane (APTES) and glutaraldehyde linker

NASA Astrophysics Data System (ADS)

Gunda, Naga Siva Kumar; Singh, Minashree; Norman, Lana; Kaur, Kamaljit; Mitra, Sushanta K.

2014-06-01

In the present work, we developed and optimized a technique to produce a thin, stable silane layer on silicon substrate in a controlled environment using (3-aminopropyl)triethoxysilane (APTES). The effect of APTES concentration and silanization time on the formation of silane layer is studied using spectroscopic ellipsometry and Fourier transform infrared spectroscopy (FTIR). Biomolecules of interest are immobilized on optimized silane layer formed silicon substrates using glutaraldehyde linker. Surface analytical techniques such as ellipsometry, FTIR, contact angle measurement system, and atomic force microscopy are employed to characterize the bio-chemically modified silicon surfaces at each step of the biomolecule immobilization process. It is observed that a uniform, homogenous and highly dense layer of biomolecules are immobilized with optimized silane layer on the silicon substrate. The developed immobilization method is successfully implemented on different silicon substrates (flat and pillar). Also, different types of biomolecules such as anti-human IgG (rabbit monoclonal to human IgG), Listeria monocytogenes, myoglobin and dengue capture antibodies were successfully immobilized. Further, standard sandwich immunoassay (antibody-antigen-antibody) is employed on respective capture antibody coated silicon substrates. Fluorescence microscopy is used to detect the respective FITC tagged detection antibodies bound to the surface after immunoassay.

Electrochemical assembly of organic molecules by the reduction of iodonium salts

DOEpatents

Dirk, Shawn M [Albuquerque, NM; Howell, Stephen W [Albuquerque, NM; Wheeler, David R [Albuquerque, NM

2009-06-23

Methods are described for the electrochemical assembly of organic molecules on silicon, or other conducting or semiconducting substrates, using iodonium salt precursors. Iodonium molecules do not assemble on conducting surfaces without a negative bias. Accordingly, the iodonium salts are preferred for patterning applications that rely on direct writing with negative bias. The stability of the iodonium molecule to acidic conditions allows them to be used with standard silicon processing. As a directed assembly process, the use of iodonium salts provides for small features while maintaining the ability to work on a surface and create structures on a wafer level. Therefore, the process is amenable for mass production. Furthermore, the assembled monolayer (or multilayer) is chemically robust, allowing for subsequent chemical manipulations and the introduction of various molecular functionalities for various chemical and biological applications.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

The Effect of Fermentation Broth Components on Performance of High Silica ZSM-5/Silicone Rubber Mixed Matrix Membranes

EPA Science Inventory

Fermentative organisms produce a range of compounds in addition to the desired product. For example, in addition to ethanol, standard yeast produces longer straight-chained and branched alcohols and organic acids. Additionally, biomass pretreatment process, particularly acid-base...

Extracting Silicon From Sodium-Process Products

NASA Technical Reports Server (NTRS)

Kapur, V.; Sanjurjo, A.; Sancier, K. M.; Nanis, L.

1982-01-01

New acid leaching process purifies silicon produced in reaction between silicon fluoride and sodium. Concentration of sodium fluoride and other impurities and byproducts remaining in silicon are within acceptable ranges for semi-conductor devices. Leaching process makes sodium reduction process more attractive for making large quantities of silicon for solar cells.

A new method of metallization for silicon solar cells

NASA Technical Reports Server (NTRS)

Macha, M.

1979-01-01

The new metallization process based on Mo-Sn system was studied. The reaction mechanism of MoO3 and its mixture with Sn was examined. The basic ink composition was modified in order to obtain a low ohmic contact to the cell. The electrical characteristics of the cells were comparable with the existing metallization processes. However, in comparison with the standard processes using silver as the contacting metal, the saving obtained by the use of the new process was substantial.

Comparative surface studies on wet and dry sacrificial thermal oxidation on silicon carbide

NASA Astrophysics Data System (ADS)

Koh, A.; Kestle, A.; Wright, C.; Wilks, S. P.; Mawby, P. A.; Bowen, W. R.

2001-04-01

A comparative study on the effect of wet and dry thermal oxidation on 4H-silicon carbide (SiC) and on sacrificial silicon (Si) thermal oxidation on 4H-SiC surface has been conducted using atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS). The AFM images show the formation of 'nano-islands' of varying density on the SiC surface after the removal of thermal oxide using hydrofluoric (HF) acid etch. These nano-islands are resistant to HF acid and have been previously linked to residual carbon [1-3] resulting from the oxidation process. This paper presents the use of a sacrificial silicon oxidation (SSO) step as a form of surface preparation that gives a reproducible clean SiC surface. XPS results show a slight electrical shift in binding energy between the wet and dry thermal oxidation on the standard SiC surface, while the surface produced by the SSO technique shows a minimal shift.

Slicing of silicon into sheet material: Silicon sheet growth development for the large area silicon sheet task of the Low Cost Silicon Solar Array project

NASA Technical Reports Server (NTRS)

Fleming, J. R.

1978-01-01

The limits of blade tolerance were defined. The standard blades are T-2 thickness tolerance. Good results were obtained by using a slurry fluid consisting of mineral oil and a lubricity additive. Adjustments of the formulation and fine tuning of the cutting process with the new fluid are necessary. Test results and consultation indicate that the blade breakage encountered with water based slurries is unavoidable. Two full capacity (974 wafer) runs were made on the large prototype saw. Both runs resulted in extremely low yield. However, the reasons for the low yield were lack of proper technique rather than problems with machine function. The test on the effect of amount of material etched off of an as-sawn wafer on solar cell efficiency were completed. The results agree with previous work at JPL in that the minimum material removed per side that gives maximum efficiency is on the order of 10 microns.

A silicon carbide array for electrocorticography and peripheral nerve recording.

PubMed

Diaz-Botia, C A; Luna, L E; Neely, R M; Chamanzar, M; Carraro, C; Carmena, J M; Sabes, P N; Maboudian, R; Maharbiz, M M

2017-10-01

Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

A silicon carbide array for electrocorticography and peripheral nerve recording

NASA Astrophysics Data System (ADS)

Diaz-Botia, C. A.; Luna, L. E.; Neely, R. M.; Chamanzar, M.; Carraro, C.; Carmena, J. M.; Sabes, P. N.; Maboudian, R.; Maharbiz, M. M.

2017-10-01

Objective. Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. Approach. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. Main results. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Significance. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Nanofabrication of insulated scanning probes for electromechanical imaging in liquid solutions

PubMed Central

Noh, Joo Hyon; Nikiforov, Maxim; Kalinin, Sergei V.; Vertegel, Alexey A.; Rack, Philip D.

2011-01-01

In this paper, the fabrication and electrical and electromechanical characterization of insulated scanning probes have been demonstrated in liquid solutions. The silicon cantilevers were sequentially coated with chromium and silicon dioxide, and the silicon dioxide was selectively etched at tip apex using focused electron beam induced etching (FEBIE) with XeF2 The chromium layer acted not only as the conductive path from the tip, but also as an etch resistant layer. This insulated scanning probe fabrication process is compatible with any commercial AFM tip and can be used to easily tailor the scanning probe tip properties because FEBIE does not require lithography. The suitability of the fabricated probes is demonstrated by imaging of standard topographical calibration grid as well as piezoresponse force microscopy (PFM) and electrical measurements in ambient and liquid environments. PMID:20702930

Effect of the carrier gas flow rate on the microstructure evolution and the generation of the charged nanoparticles during silicon chemical vapor deposition.

PubMed

Youn, Woong-Kyu; Kim, Chan-Soo; Hwang, Nong-Moon

2013-10-01

The generation of charged nanoparticles in the gas phase has been continually reported in many chemical vapor deposition processes. Charged silicon nanoparticles in the gas phase were measured using a differential mobility analyzer connected to an atmospheric-pressure chemical vapor deposition reactor at various nitrogen carrier gas flow rates (300-1000 standard cubic centimeter per minute) under typical conditions for silicon deposition at the reactor temperature of 900 degrees C. The carrier gas flow rate affected not only the growth behavior of nanostructures but also the number concentration and size distribution of both negatively and positively charged nanoparticles. As the carrier gas flow rate decreased, the growth behavior changed from films to nanowires, which grew without catalytic metal nanoparticles on a quartz substrate.

Metal-capped silicon organic micro-ring electro-optical modulator (Conference Presentation)

NASA Astrophysics Data System (ADS)

Zaki, Aya O.; Kirah, Khaled A.; Swillam, Mohamed A.

2017-02-01

An ultra-compact hybrid plasmonic waveguide ring electro-optical modulator is designed to be easily fabricated on silicon on insulator (SOI) substrates using standard silicon photonics technology. The proposed waveguide is based on a buried standard silicon waveguide of height 220 nm topped with polymer and metal. The key advantage of this novel design is that only the silicon layer of the waveguide is structured as a coupled ring resonator. Then, the device is covered with electro-optical polymer and metal in post processes with no need for lithography or accurate mask alignment techniques. The simple fabrication method imposes many design challenges to obtain a resonator of reasonable loaded quality factor and high extinction ratio. Here, the performance of the resonator is optimized in the telecom wavelength range around 1550 nm using 3D FDTD simulations. The design of the coupling junction between the access waveguide and the tightly bent ring is thoroughly studied. The extension of the metal over the coupling region is exploited to make the critical dimension of the design geometry at least 2.5 times larger than conventional plasmonic resonators and the design is thus more robust. In this paper, we demonstrate an electro-optical modulator that offers an insertion loss < 1 dB, a modulation depth of 12 dB for an applied peak to peak voltage of only 2 V and energy consumption of 1.74 fJ/bit. The performance is superior to previously reported hybrid plasmonic ring resonator based modulators while the design shows robustness and low fabrication cost.

Reduction in Recombination Current Density in Boron Doped Silicon Using Atomic Hydrogen

NASA Astrophysics Data System (ADS)

Young, Matthew Garett

The solar industry has grown immensely in recent years and has reached a point where solar energy has now become inexpensive enough that it is starting to emerge as a mainstream electrical generation source. However, recent economic analysis has suggested that for solar to become a truly wide spread source of electricity, the costs still need to plummet by a factor of 8x. This demands new and innovative concepts to help lower such cost. In pursuit of this goal, this dissertation examines the use of atomic hydrogen to lessen the recombination current density in the boron doped region of n-type silicon solar cells. This required the development of a boron diffusion process that maintained the bulk lifetime of n-type silicon such that the recombination current density could be extracted by photoconductance spectroscopy. It is demonstrated that by hydrogenating boron diffusions, the majority carrier concentration can be controlled. By using symmetrically diffused test structures with quinhydrone-methanol surface passivation the recombination current density of a hydrogenated boron profile is shown to be less than that of a standard boron profile, by as much as 30%. This is then applied to a modified industrial silicon solar cell process to demonstrate an efficiency enhancement of 0.4%.

Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

NASA Astrophysics Data System (ADS)

Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2011-06-01

For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

Effects of Impurities and Processing on Silicon Solar Cells, Phase 3

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Davis, J. R.; Blais, P. D.; Rohatgi, A.; Campbell, R. B.; Rai-Choudhury, P.; Stapleton, R. E.; Mollenkopf, H. C.; Mccormick, J. R.

1979-01-01

Results of the 14th quarterly report are presented for a program designed to assess the effects of impurities, thermochemical processes and any impurity process interactions on the performance of terrestrial silicon solar cells. The Phase 3 effort encompasses: (1) potential interactions between impurities and thermochemical processing of silicon; (2) impurity-cell performance relationships in n-base silicon; (3) effect of contaminants introduced during silicon production, refining or crystal growth on cell performance; (4) effects of nonuniform impurity distributions in large area silicon wafers; and (5) a preliminary study of the permanence of impurity effects in silicon solar cells.

Low cost solar array project. Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

NASA Technical Reports Server (NTRS)

1980-01-01

Technical activities are reported in the design of process, facilities, and equipment for producing silicon at a rate and price comensurate with production goals for low cost solar cell modules. The silane-silicone process has potential for providing high purity poly-silicon on a commercial scale at a price of fourteen dollars per kilogram by 1986, (1980 dollars). Commercial process, economic analysis, process support research and development, and quality control are discussed.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

The resonant body transistor.

PubMed

Weinstein, Dana; Bhave, Sunil A

2010-04-14

This paper introduces the resonant body transistor (RBT), a silicon-based dielectrically transduced nanoelectromechanical (NEM) resonator embedding a sense transistor directly into the resonator body. Combining the benefits of FET sensing with the frequency scaling capabilities and high quality factors (Q) of internal dielectrically transduced bar resonators, the resonant body transistor achieves >10 GHz frequencies and can be integrated into a standard CMOS process for on-chip clock generation, high-Q microwave circuits, fundamental quantum-state preparation and observation, and high-sensitivity measurements. An 11.7 GHz bulk-mode RBT is demonstrated with a quality factor Q of 1830, marking the highest frequency acoustic resonance measured to date on a silicon wafer.

Fabrication of porous silicon nitride ceramics using binder jetting technology

NASA Astrophysics Data System (ADS)

Rabinskiy, L.; Ripetsky, A.; Sitnikov, S.; Solyaev, Y.; Kahramanov, R.

2016-07-01

This paper presents the results of the binder jetting technology application for the processing of the Si3N4-based ceramics. The difference of the developed technology from analogues used for additive manufacturing of silicon nitride ceramics is a method of the separate deposition of the mineral powder and binder without direct injection of suspensions/slurries. It is assumed that such approach allows reducing the technology complexity and simplifying the process of the feedstock preparation, including the simplification of the composite materials production. The binders based on methyl ester of acrylic acid with polyurethane and modified starch were studied. At this stage of the investigations, the technology of green body's fabrication is implemented using a standard HP cartridge mounted on the robotic arm. For the coordinated operation of the cartridge and robot the specially developed software was used. Obtained green bodies of silicon powder were used to produce the ceramic samples via reaction sintering. The results of study of ceramics samples microstructure and composition are presented. Sintered ceramics are characterized by fibrous α-Si3N4 structure and porosity up to 70%.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Nucleation and atomic layer reaction in nickel silicide for defect-engineered Si nanochannels.

PubMed

Tang, Wei; Picraux, S Tom; Huang, Jian Yu; Gusak, Andriy M; Tu, King-Ning; Dayeh, Shadi A

2013-06-12

At the nanoscale, defects can significantly impact phase transformation processes and change materials properties. The material nickel silicide has been the industry standard electrical contact of silicon microelectronics for decades and is a rich platform for scientific innovation at the conjunction of materials and electronics. Its formation in nanoscale silicon devices that employ high levels of strain, intentional, and unintentional twins or grain boundaries can be dramatically different from the commonly conceived bulk processes. Here, using in situ high-resolution transmission electron microscopy (HRTEM), we capture single events during heterogeneous nucleation and atomic layer reaction of nickel silicide at various crystalline boundaries in Si nanochannels for the first time. We show through systematic experiments and analytical modeling that unlike other typical face-centered cubic materials such as copper or silicon the twin defects in NiSi2 have high interfacial energies. We observe that these twin defects dramatically change the behavior of new phase nucleation and can have direct implications for ultrascaled devices that are prone to defects or may utilize them to improve device performance.

Evaluation of Electrospun Nanofiber-Anchored Silicone for the Degenerative Intervertebral Disc

PubMed Central

Riahanizad, S.

2017-01-01

The nucleus pulposus (NP) substitution by polymeric gel is one of the promising techniques for the repair of the degenerative intervertebral disc (IVD). Silicone gel is one of the potential candidates for a NP replacement material. Electrospun fiber anchorage to silicone disc, referred as ENAS disc, may not only improve the biomechanical performances of the gel but it can also improve restoration capability of the gel, which is unknown. This study successfully produced a novel process to anchor any size and shape of NP gel with electrospun fiber mesh. Viscoelastic properties of silicone and ENAS disc were measured using standard experimental techniques and compared with the native tissue properties. Ex vivo mechanical tests were conducted on ENAS disc-implanted rabbit tails to the compare the mechanical stability between intact and ENAS implanted spines. This study found that viscoelastic properties of ENAS disc are higher than silicone disc and comparable to the viscoelastic properties of human NP. The ex vivo studies found that the ENAS disc restore the mechanical functionality of rabbit tail spine, after discectomy of native NP and replacing the NP by ENAS disc. Therefore, the PCL ENF mesh anchoring technique to a NP implant can have clinical potential. PMID:29181144

Current-voltage characteristics and increase in the quantum efficiency of three-terminal gate and avalanche-based silicon LEDs.

PubMed

Xu, Kaikai

2013-09-20

In this paper, the emission of visible light by a monolithically integrated silicon p-n junction under reverse-bias is discussed. The modulation of light intensity is achieved using an insulated-gate terminal on the surface of the p-n junction. By varying the gate voltage, the breakdown voltage of the p-n junction will be adjustable so that the reverse current I(sub) flowing through the p-n junction at a fixed reverse-bias voltage is changed. It is observed that the light, which is emitted from the defects located at the p-n junction, depends closely on the reverse current I(sub). In regard to the phenomenon of electroluminescence, the relationship between the optical emission power and the reverse current I(sub) is linear. On the other hand, it is observed that both the quantum efficiency and the power conversion efficiency are able to have obvious enhancement, although the reverse-bias of the p-n junction is reduced and the corresponding reverse-current is much lower. Moreover, the successful fabrication on monolithic silicon light source on the bulk silicon by means of standard silicon complementary metal-oxide-semiconductor process technology is presented.

Controlling the optical properties of monocrystalline 3C-SiC heteroepitaxially grown on silicon at low temperatures

NASA Astrophysics Data System (ADS)

Colston, Gerard; Myronov, Maksym

2017-11-01

Cubic silicon carbide (3C-SiC) offers an alternative wide bandgap semiconductor to conventional materials such as hexagonal silicon carbide (4H-SiC) or gallium nitride (GaN) for the detection of UV light and can offer a closely lattice matched virtual substrate for subsequent GaN heteroepitaxy. As 3C-SiC can be heteroepitaxially grown on silicon (Si) substrates its optical properties can be manipulated by controlling the thickness and doping concentrations. The optical properties of 3C-SiC epilayers have been characterized by measuring the transmission of light through suspended membranes. Decreasing the thickness of the 3C-SiC epilayers is shown to shift the absorbance edge to lower wavelengths, a result of the indirect bandgap nature of silicon carbide. This property, among others, can be exploited to fabricate very low-cost, tuneable 3C-SiC based UV photodetectors. This study investigates the effect of thickness and doping concentration on the optical properties of 3C-SiC epilayers grown at low temperatures by a standard Si based growth process. The results demonstrate the potential photonic applications of 3C-SiC and its heterogeneous integration into the Si industry.

Study on Silicon Microstructure Processing Technology Based on Porous Silicon

NASA Astrophysics Data System (ADS)

Shang, Yingqi; Zhang, Linchao; Qi, Hong; Wu, Yalin; Zhang, Yan; Chen, Jing

2018-03-01

Aiming at the heterogeneity of micro - sealed cavity in silicon microstructure processing technology, the technique of preparing micro - sealed cavity of porous silicon is proposed. The effects of different solutions, different substrate doping concentrations, different current densities, and different etching times on the rate, porosity, thickness and morphology of the prepared porous silicon were studied. The porous silicon was prepared by different process parameters and the prepared porous silicon was tested and analyzed. For the test results, optimize the process parameters and experiments. The experimental results show that the porous silicon can be controlled by optimizing the parameters of the etching solution and the doping concentration of the substrate, and the preparation of porous silicon with different porosity can be realized by different doping concentration, so as to realize the preparation of silicon micro-sealed cavity, to solve the sensor sensitive micro-sealed cavity structure heterogeneous problem, greatly increasing the application of the sensor.

Process for forming retrograde profiles in silicon

DOEpatents

Weiner, K.H.; Sigmon, T.W.

1996-10-15

A process is disclosed for forming retrograde and oscillatory profiles in crystalline and polycrystalline silicon. The process consisting of introducing an n- or p-type dopant into the silicon, or using prior doped silicon, then exposing the silicon to multiple pulses of a high-intensity laser or other appropriate energy source that melts the silicon for short time duration. Depending on the number of laser pulses directed at the silicon, retrograde profiles with peak/surface dopant concentrations which vary are produced. The laser treatment can be performed in air or in vacuum, with the silicon at room temperature or heated to a selected temperature.

A high voltage dielectrically isolated smart power technology based on silicon direct bonding

NASA Astrophysics Data System (ADS)

Macary, Veronique

1992-09-01

The feasibility of a dielectrically isolated technology based on the silicon direct bonding technique, for high voltage smart power applications in the 1000 to 1550 V/1 to 20 A range, where a vertical power switch is necessary, is investigated and demonstrated. Static and dynamic isolation of the low voltage circuitry integrated beside the vertical power transistor is the main concern of this family of circuits. The dielectric isolation offers better protection to the low voltage part than does the junction isolation, because of the elimination of the parasitic bipolar transistor inherent to the latter isolation technique. Silicon direct bonding provides a cost effective way to obtain a buried oxide isolation layer. In addition, the application requires a Si/Si bonded area in the active region of the vertical power switch. Strong influence of the prebonding cleaning in the electrical characteristics of the Si/Si interface is pointed out, and presence of crystalline defects is assumed to be at the origin of electrical failures. The main problems of silicon direct bonding process compatibility with standard processes were overcome, and a complete process flow, including the simultaneous integration of a vertical power bipolar transistor together with a bipolar control circuitry, was validated. Using a peripheral biased ring is shown to provide an easy way to optimize high voltage termination for the smart power circuit, while adding a non-additional technological step. This technique was studied by dimensional electrical simulations (BIDIM2 software), as well as analytically computed.

ELAS - SCIENCE & TECHNOLOGY LABORATORY APPLICATIONS SOFTWARE (CONCURRENT VERSION)

NASA Technical Reports Server (NTRS)

Pearson, R. W.

1994-01-01

The Science and Technology Laboratory Applications Software (ELAS) was originally designed to analyze and process digital imagery data, specifically remotely-sensed scanner data. This capability includes the processing of Landsat multispectral data; aircraft-acquired scanner data; digitized topographic data; and numerous other ancillary data, such as soil types and rainfall information, that can be stored in digitized form. ELAS has the subsequent capability to geographically reference this data to dozens of standard, as well as user created projections. As an integrated image processing system, ELAS offers the user of remotely-sensed data a wide range of capabilities in the areas of land cover analysis and general purpose image analysis. ELAS is designed for flexible use and operation and includes its own FORTRAN operating subsystem and an expandable set of FORTRAN application modules. Because all of ELAS resides in one "logical" FORTRAN program, data inputs and outputs, directives, and module switching are convenient for the user. There are over 230 modules presently available to aid the user in performing a wide range of land cover analyses and manipulation. The file management modules enable the user to allocate, define, access, and specify usage for all types of files (ELAS files, subfiles, external files etc.). Various other modules convert specific types of satellite, aircraft, and vector-polygon data into files that can be used by other ELAS modules. The user also has many module options which aid in displaying image data, such as magnification/reduction of the display; true color display; and several memory functions. Additional modules allow for the building and manipulation of polygonal areas of the image data. Finally, there are modules which allow the user to select and classify the image data. An important feature of the ELAS subsystem is that its structure allows new applications modules to be easily integrated in the future. ELAS has as a standard the flexibility to process data elements exceeding 8 bits in length, including floating point (noninteger) elements and 16 or 32 bit integers. Thus it is able to analyze and process "non-standard" nonimage data. The VAX (ERL-10017) and Concurrent (ERL-10013) versions of ELAS 9.0 are written in FORTRAN and ASSEMBLER for DEC VAX series computers running VMS and Concurrent computers running MTM. The Sun (SSC-00019), Masscomp (SSC-00020), and Silicon Graphics (SSC-00021) versions of ELAS 9.0 are written in FORTRAN 77 and C-LANGUAGE for Sun4 series computers running SunOS, Masscomp computers running UNIX, and Silicon Graphics IRIS computers running IRIX. The Concurrent version requires at least 15 bit addressing and a direct memory access channel. The VAX and Concurrent versions of ELAS both require floating-point hardware, at least 1Mb of RAM, and approximately 70Mb of disk space. Both versions also require a COMTAL display device in order to display images. For the Sun, Masscomp, and Silicon Graphics versions of ELAS, the disk storage required is approximately 115Mb, and a minimum of 8Mb of RAM is required for execution. The Sun version of ELAS requires either the X-Window System Version 11 Revision 4 or Sun OpenWindows Version 2. The Masscomp version requires a GA1000 display device and the associated "gp" library. The Silicon Graphics version requires Silicon Graphics' GL library. ELAS display functions will not work with a monochrome monitor. The standard distribution medium for the VAX version (ERL10017) is a set of two 9-track 1600 BPI magnetic tapes in DEC VAX BACKUP format. This version is also available on a TK50 tape cartridge in DEC VAX BACKUP format. The standard distribution medium for the Concurrent version (ERL-10013) is a set of two 9-track 1600 BPI magnetic tapes in Concurrent BACKUP format. The standard distribution medium for the Sun version (SSC-00019) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Masscomp version, (SSC-00020) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Silicon Graphics version (SSC-00021) is a .25 inch streaming magnetic IRIS tape cartridge in UNIX tar format. Version 9.0 was released in 1991. Sun4, SunOS, and Open Windows are trademarks of Sun Microsystems, Inc. MIT X Window System is licensed by Massachusetts Institute of Technology.

ELAS - SCIENCE & TECHNOLOGY LABORATORY APPLICATIONS SOFTWARE (SUN VERSION)

NASA Technical Reports Server (NTRS)

Walters, D.

1994-01-01

The Science and Technology Laboratory Applications Software (ELAS) was originally designed to analyze and process digital imagery data, specifically remotely-sensed scanner data. This capability includes the processing of Landsat multispectral data; aircraft-acquired scanner data; digitized topographic data; and numerous other ancillary data, such as soil types and rainfall information, that can be stored in digitized form. ELAS has the subsequent capability to geographically reference this data to dozens of standard, as well as user created projections. As an integrated image processing system, ELAS offers the user of remotely-sensed data a wide range of capabilities in the areas of land cover analysis and general purpose image analysis. ELAS is designed for flexible use and operation and includes its own FORTRAN operating subsystem and an expandable set of FORTRAN application modules. Because all of ELAS resides in one "logical" FORTRAN program, data inputs and outputs, directives, and module switching are convenient for the user. There are over 230 modules presently available to aid the user in performing a wide range of land cover analyses and manipulation. The file management modules enable the user to allocate, define, access, and specify usage for all types of files (ELAS files, subfiles, external files etc.). Various other modules convert specific types of satellite, aircraft, and vector-polygon data into files that can be used by other ELAS modules. The user also has many module options which aid in displaying image data, such as magnification/reduction of the display; true color display; and several memory functions. Additional modules allow for the building and manipulation of polygonal areas of the image data. Finally, there are modules which allow the user to select and classify the image data. An important feature of the ELAS subsystem is that its structure allows new applications modules to be easily integrated in the future. ELAS has as a standard the flexibility to process data elements exceeding 8 bits in length, including floating point (noninteger) elements and 16 or 32 bit integers. Thus it is able to analyze and process "non-standard" nonimage data. The VAX (ERL-10017) and Concurrent (ERL-10013) versions of ELAS 9.0 are written in FORTRAN and ASSEMBLER for DEC VAX series computers running VMS and Concurrent computers running MTM. The Sun (SSC-00019), Masscomp (SSC-00020), and Silicon Graphics (SSC-00021) versions of ELAS 9.0 are written in FORTRAN 77 and C-LANGUAGE for Sun4 series computers running SunOS, Masscomp computers running UNIX, and Silicon Graphics IRIS computers running IRIX. The Concurrent version requires at least 15 bit addressing and a direct memory access channel. The VAX and Concurrent versions of ELAS both require floating-point hardware, at least 1Mb of RAM, and approximately 70Mb of disk space. Both versions also require a COMTAL display device in order to display images. For the Sun, Masscomp, and Silicon Graphics versions of ELAS, the disk storage required is approximately 115Mb, and a minimum of 8Mb of RAM is required for execution. The Sun version of ELAS requires either the X-Window System Version 11 Revision 4 or Sun OpenWindows Version 2. The Masscomp version requires a GA1000 display device and the associated "gp" library. The Silicon Graphics version requires Silicon Graphics' GL library. ELAS display functions will not work with a monochrome monitor. The standard distribution medium for the VAX version (ERL10017) is a set of two 9-track 1600 BPI magnetic tapes in DEC VAX BACKUP format. This version is also available on a TK50 tape cartridge in DEC VAX BACKUP format. The standard distribution medium for the Concurrent version (ERL-10013) is a set of two 9-track 1600 BPI magnetic tapes in Concurrent BACKUP format. The standard distribution medium for the Sun version (SSC-00019) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Masscomp version, (SSC-00020) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Silicon Graphics version (SSC-00021) is a .25 inch streaming magnetic IRIS tape cartridge in UNIX tar format. Version 9.0 was released in 1991. Sun4, SunOS, and Open Windows are trademarks of Sun Microsystems, Inc. MIT X Window System is licensed by Massachusetts Institute of Technology.

ELAS - SCIENCE & TECHNOLOGY LABORATORY APPLICATIONS SOFTWARE (MASSCOMP VERSION)

NASA Technical Reports Server (NTRS)

Walters, D.

1994-01-01

The Science and Technology Laboratory Applications Software (ELAS) was originally designed to analyze and process digital imagery data, specifically remotely-sensed scanner data. This capability includes the processing of Landsat multispectral data; aircraft-acquired scanner data; digitized topographic data; and numerous other ancillary data, such as soil types and rainfall information, that can be stored in digitized form. ELAS has the subsequent capability to geographically reference this data to dozens of standard, as well as user created projections. As an integrated image processing system, ELAS offers the user of remotely-sensed data a wide range of capabilities in the areas of land cover analysis and general purpose image analysis. ELAS is designed for flexible use and operation and includes its own FORTRAN operating subsystem and an expandable set of FORTRAN application modules. Because all of ELAS resides in one "logical" FORTRAN program, data inputs and outputs, directives, and module switching are convenient for the user. There are over 230 modules presently available to aid the user in performing a wide range of land cover analyses and manipulation. The file management modules enable the user to allocate, define, access, and specify usage for all types of files (ELAS files, subfiles, external files etc.). Various other modules convert specific types of satellite, aircraft, and vector-polygon data into files that can be used by other ELAS modules. The user also has many module options which aid in displaying image data, such as magnification/reduction of the display; true color display; and several memory functions. Additional modules allow for the building and manipulation of polygonal areas of the image data. Finally, there are modules which allow the user to select and classify the image data. An important feature of the ELAS subsystem is that its structure allows new applications modules to be easily integrated in the future. ELAS has as a standard the flexibility to process data elements exceeding 8 bits in length, including floating point (noninteger) elements and 16 or 32 bit integers. Thus it is able to analyze and process "non-standard" nonimage data. The VAX (ERL-10017) and Concurrent (ERL-10013) versions of ELAS 9.0 are written in FORTRAN and ASSEMBLER for DEC VAX series computers running VMS and Concurrent computers running MTM. The Sun (SSC-00019), Masscomp (SSC-00020), and Silicon Graphics (SSC-00021) versions of ELAS 9.0 are written in FORTRAN 77 and C-LANGUAGE for Sun4 series computers running SunOS, Masscomp computers running UNIX, and Silicon Graphics IRIS computers running IRIX. The Concurrent version requires at least 15 bit addressing and a direct memory access channel. The VAX and Concurrent versions of ELAS both require floating-point hardware, at least 1Mb of RAM, and approximately 70Mb of disk space. Both versions also require a COMTAL display device in order to display images. For the Sun, Masscomp, and Silicon Graphics versions of ELAS, the disk storage required is approximately 115Mb, and a minimum of 8Mb of RAM is required for execution. The Sun version of ELAS requires either the X-Window System Version 11 Revision 4 or Sun OpenWindows Version 2. The Masscomp version requires a GA1000 display device and the associated "gp" library. The Silicon Graphics version requires Silicon Graphics' GL library. ELAS display functions will not work with a monochrome monitor. The standard distribution medium for the VAX version (ERL10017) is a set of two 9-track 1600 BPI magnetic tapes in DEC VAX BACKUP format. This version is also available on a TK50 tape cartridge in DEC VAX BACKUP format. The standard distribution medium for the Concurrent version (ERL-10013) is a set of two 9-track 1600 BPI magnetic tapes in Concurrent BACKUP format. The standard distribution medium for the Sun version (SSC-00019) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Masscomp version, (SSC-00020) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Silicon Graphics version (SSC-00021) is a .25 inch streaming magnetic IRIS tape cartridge in UNIX tar format. Version 9.0 was released in 1991. Sun4, SunOS, and Open Windows are trademarks of Sun Microsystems, Inc. MIT X Window System is licensed by Massachusetts Institute of Technology.

ELAS - SCIENCE & TECHNOLOGY LABORATORY APPLICATIONS SOFTWARE (DEC VAX VERSION)

NASA Technical Reports Server (NTRS)

Junkin, B. G.

1994-01-01

The Science and Technology Laboratory Applications Software (ELAS) was originally designed to analyze and process digital imagery data, specifically remotely-sensed scanner data. This capability includes the processing of Landsat multispectral data; aircraft-acquired scanner data; digitized topographic data; and numerous other ancillary data, such as soil types and rainfall information, that can be stored in digitized form. ELAS has the subsequent capability to geographically reference this data to dozens of standard, as well as user created projections. As an integrated image processing system, ELAS offers the user of remotely-sensed data a wide range of capabilities in the areas of land cover analysis and general purpose image analysis. ELAS is designed for flexible use and operation and includes its own FORTRAN operating subsystem and an expandable set of FORTRAN application modules. Because all of ELAS resides in one "logical" FORTRAN program, data inputs and outputs, directives, and module switching are convenient for the user. There are over 230 modules presently available to aid the user in performing a wide range of land cover analyses and manipulation. The file management modules enable the user to allocate, define, access, and specify usage for all types of files (ELAS files, subfiles, external files etc.). Various other modules convert specific types of satellite, aircraft, and vector-polygon data into files that can be used by other ELAS modules. The user also has many module options which aid in displaying image data, such as magnification/reduction of the display; true color display; and several memory functions. Additional modules allow for the building and manipulation of polygonal areas of the image data. Finally, there are modules which allow the user to select and classify the image data. An important feature of the ELAS subsystem is that its structure allows new applications modules to be easily integrated in the future. ELAS has as a standard the flexibility to process data elements exceeding 8 bits in length, including floating point (noninteger) elements and 16 or 32 bit integers. Thus it is able to analyze and process "non-standard" nonimage data. The VAX (ERL-10017) and Concurrent (ERL-10013) versions of ELAS 9.0 are written in FORTRAN and ASSEMBLER for DEC VAX series computers running VMS and Concurrent computers running MTM. The Sun (SSC-00019), Masscomp (SSC-00020), and Silicon Graphics (SSC-00021) versions of ELAS 9.0 are written in FORTRAN 77 and C-LANGUAGE for Sun4 series computers running SunOS, Masscomp computers running UNIX, and Silicon Graphics IRIS computers running IRIX. The Concurrent version requires at least 15 bit addressing and a direct memory access channel. The VAX and Concurrent versions of ELAS both require floating-point hardware, at least 1Mb of RAM, and approximately 70Mb of disk space. Both versions also require a COMTAL display device in order to display images. For the Sun, Masscomp, and Silicon Graphics versions of ELAS, the disk storage required is approximately 115Mb, and a minimum of 8Mb of RAM is required for execution. The Sun version of ELAS requires either the X-Window System Version 11 Revision 4 or Sun OpenWindows Version 2. The Masscomp version requires a GA1000 display device and the associated "gp" library. The Silicon Graphics version requires Silicon Graphics' GL library. ELAS display functions will not work with a monochrome monitor. The standard distribution medium for the VAX version (ERL10017) is a set of two 9-track 1600 BPI magnetic tapes in DEC VAX BACKUP format. This version is also available on a TK50 tape cartridge in DEC VAX BACKUP format. The standard distribution medium for the Concurrent version (ERL-10013) is a set of two 9-track 1600 BPI magnetic tapes in Concurrent BACKUP format. The standard distribution medium for the Sun version (SSC-00019) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Masscomp version, (SSC-00020) is a .25 inch streaming magnetic tape cartridge in UNIX tar format. The standard distribution medium for the Silicon Graphics version (SSC-00021) is a .25 inch streaming magnetic IRIS tape cartridge in UNIX tar format. Version 9.0 was released in 1991. Sun4, SunOS, and Open Windows are trademarks of Sun Microsystems, Inc. MIT X Window System is licensed by Massachusetts Institute of Technology.

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

25-Gb/s broadband silicon modulator with 0.31-V·cm VπL based on forward-biased PIN diodes embedded with passive equalizer.

PubMed

Baba, Takeshi; Akiyama, Suguru; Imai, Masahiko; Usuki, Tatsuya

2015-12-28

We investigated the broadband operations of a silicon Mach-Zehnder modulator (MZM) based on a forward-biased-PIN diode. The phase shifter was integrated with a passive-circuit equalizer to compensate for the narrowband characteristics of the diodes, which consists of a simple resistance of doped silicon and a parallel-plate metal capacitance. The device structure was simple and fabricated using standard CMOS processes. The measured results for a 50-Ω driver indicated there was a small VπL of 0.31 V·cm and a flat frequency response for a 3-dB bandwidth (f(3dB)) of 17 GHz, which agree well with the designed values. A 25-Gb/s large-signal operation was obtained using binary signals without pre-emphasis. The modulator showed a linear modulation property to the applied voltage, due to the metal capacitance of the equalizer.

Carbon-carbon mirrors for exoatmospheric and space applications

NASA Astrophysics Data System (ADS)

Krumweide, Duane E.; Wonacott, Gary D.; Woida, Patrick M.; Woida, Rigel Q.; Shih, Wei

2007-09-01

The cost and leadtime associated with beryllium has forced the MDA and other defense agencies to look for alternative materials with similar structural and thermal properties. The use of carbon-carbon material, specifically in optical components has been demonstrated analytically in prior SBIR work at San Diego Composites. Carbon-carbon material was chosen for its low in-plane and through-thickness CTE (athermal design), high specific stiffness, near-zero coefficient of moisture expansion, availability of material (specifically c-c honeycomb for lightweight substrates), and compatibility with silicon monoxide (SiO) and silicon dioxide (SiO II) coatings. Subsequent development work has produced shaped carbon-carbon sandwich substrates which have been ground, polished, coated and figured using traditional optical processing. Further development has also been done on machined monolithic carbon-carbon mirror substrates which have also been processed using standard optical finishing techniques.

New technologies for solar energy silicon - Cost analysis of dichlorosilane process

NASA Technical Reports Server (NTRS)

Yaws, C. L.; Li, K.-Y.; Chu, T. C. T.; Fang, C. S.; Lutwack, R.; Briglio, A., Jr.

1981-01-01

A reduction in the cost of silicon for solar cells is an important objective in a project concerned with the reduction of the cost of electricity produced with solar cells. The cost goal for the silicon material is about $14 per kg (1980 dollars). The process which is currently employed to produce semiconductor grade silicon from trichlorosilane is not suited for meeting this cost goal. Other processes for producing silicon are, therefore, being investigated. A description is presented of results obtained for the DCS process which involves the production of dichlorosilane as a silicon source material for solar energy silicon. Major benefits of dichlorosilane as a silicon source material include faster reaction rates for chemical vapor deposition of silicon. The DCS process involves the reaction 2SiHCl3 yields reversibly SiH2Cl2 + SiCl4. The results of a cost analysis indicate a total product cost without profit of $1.29/kg of SiH2Cl2.

Flat-plate solar array project: Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

NASA Technical Reports Server (NTRS)

1981-01-01

The engineering design, fabrication, assembly, operation, economic analysis, and process support research and development for an Experimental Process System Development Unit for producing semiconductor-grade silicon using the slane-to-silicon process are reported. The design activity was completed. About 95% of purchased equipment was received. The draft of the operations manual was about 50% complete and the design of the free-space system continued. The system using silicon power transfer, melting, and shotting on a psuedocontinuous basis was demonstrated.

Methods To Determine the Silicone Oil Layer Thickness in Sprayed-On Siliconized Syringes.

PubMed

Loosli, Viviane; Germershaus, Oliver; Steinberg, Henrik; Dreher, Sascha; Grauschopf, Ulla; Funke, Stefanie

2018-01-01

The silicone lubricant layer in prefilled syringes has been investigated with regards to siliconization process performance, prefilled syringe functionality, and drug product attributes, such as subvisible particle levels, in several studies in the past. However, adequate methods to characterize the silicone oil layer thickness and distribution are limited, and systematic evaluation is missing. In this study, white light interferometry was evaluated to close this gap in method understanding. White light interferometry demonstrated a good accuracy of 93-99% for MgF 2 coated, curved standards covering a thickness range of 115-473 nm. Thickness measurements for sprayed-on siliconized prefilled syringes with different representative silicone oil distribution patterns (homogeneous, pronounced siliconization at flange or needle side, respectively) showed high instrument (0.5%) and analyst precision (4.1%). Different white light interferometry instrument parameters (autofocus, protective shield, syringe barrel dimensions input, type of non-siliconized syringe used as base reference) had no significant impact on the measured average layer thickness. The obtained values from white light interferometry applying a fully developed method (12 radial lines, 50 mm measurement distance, 50 measurements points) were in agreement with orthogonal results from combined white and laser interferometry and 3D-laser scanning microscopy. The investigated syringe batches (lot A and B) exhibited comparable longitudinal silicone oil layer thicknesses ranging from 170-190 nm to 90-100 nm from flange to tip and homogeneously distributed silicone layers over the syringe barrel circumference (110- 135 nm). Empty break-loose (4-4.5 N) and gliding forces (2-2.5 N) were comparably low for both analyzed syringe lots. A silicone oil layer thickness of 100-200 nm was thus sufficient for adequate functionality in this particular study. Filling the syringe with a surrogate solution including short-term exposure and emptying did not significantly influence the silicone oil layer at the investigated silicone level. It thus appears reasonable to use this approach to characterize silicone oil layers in filled syringes over time. The developed method characterizes non-destructively the layer thickness and distribution of silicone oil in empty syringes and provides fast access to reliable results. The gained information can be further used to support optimization of siliconization processes and increase the understanding of syringe functionality. LAY ABSTRACT: Silicone oil layers as lubricant are required to ensure functionality of prefilled syringes. Methods evaluating these layers are limited, and systematic evaluation is missing. The aim of this study was to develop and assess white light interferometry as an analytical method to characterize sprayed-on silicone oil layers in 1 mL prefilled syringes. White light interferometry showed a good accuracy (93-99%) as well as instrument and analyst precision (0.5% and 4.1%, respectively). Different applied instrument parameters had no significant impact on the measured layer thickness. The obtained values from white light interferometry applying a fully developed method concurred with orthogonal results from 3D-laser scanning microscopy and combined white light and laser interferometry. The average layer thicknesses in two investigated syringe lots gradually decreased from 170-190 nm at the flange to 100-90 nm at the needle side. The silicone layers were homogeneously distributed over the syringe barrel circumference (110-135 nm) for both lots. Empty break-loose (4-4.5 N) and gliding forces (2-2.5 N) were comparably low for both analyzed syringe lots. Syringe filling with a surrogate solution, including short-term exposure and emptying, did not significantly affect the silicone oil layer. The developed, non-destructive method provided reliable results to characterize the silicone oil layer thickness and distribution in empty siliconized syringes. This information can be further used to support optimization of siliconization processes and increase understanding of syringe functionality. © PDA, Inc. 2018.

Control of single-electron charging of metallic nanoparticles onto amorphous silicon surface.

PubMed

Weis, Martin; Gmucová, Katarína; Nádazdy, Vojtech; Capek, Ignác; Satka, Alexander; Kopáni, Martin; Cirák, Július; Majková, Eva

2008-11-01

Sequential single-electron charging of iron oxide nanoparticles encapsulated in oleic acid/oleyl amine envelope and deposited by the Langmuir-Blodgett technique onto Pt electrode covered with undoped hydrogenated amorphous silicon film is reported. Single-electron charging (so-called quantized double-layer charging) of nanoparticles is detected by cyclic voltammetry as current peaks and the charging effect can be switched on/off by the electric field in the surface region induced by the excess of negative/positive charged defect states in the amorphous silicon layer. The particular charge states in amorphous silicon are created by the simultaneous application of a suitable bias voltage and illumination before the measurement. The influence of charged states on the electric field in the surface region is evaluated by the finite element method. The single-electron charging is analyzed by the standard quantized double layer model as well as two weak-link junctions model. Both approaches are in accordance with experiment and confirm single-electron charging by tunnelling process at room temperature. This experiment illustrates the possibility of the creation of a voltage-controlled capacitor for nanotechnology.

Process feasibility study in support of silicon material task 1

NASA Technical Reports Server (NTRS)

Yaws, C. L.; Li, K. Y.; Hopper, J. R.; Fang, C. S.; Hansen, K. C.

1981-01-01

Results for process system properties, chemical engineering and economic analyses of the new technologies and processes being developed for the production of lower cost silicon for solar cells are presented. Analyses of process system properties are important for chemical materials involved in the several processes under consideration for semiconductor and solar cell grade silicon production. Major physical, thermodynamic and transport property data are reported for silicon source and processing chemical materials.

Development of advanced second-generation micromirror devices fabricated in a four-level planarized surface-micromachined polycrystalline silicon process

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Comtois, John H.; Schriner, Heather K.

1998-04-01

This paper describes the design and characterization of several types of micromirror devices to include process capabilities, device modeling, and test data resulting in deflection versus applied potential curves and surface contour measurements. These devices are the first to be fabricated in the state-of-the-art four-level planarized polysilicon process available at Sandia National Laboratories known as the Sandia Ultra-planar Multi-level MEMS Technology. This enabling process permits the development of micromirror devices with near-ideal characteristics which have previously been unrealizable in standard three-layer polysilicon processes. This paper describes such characteristics which have previously been unrealizable in standard three-layer polysilicon processes. This paper describes such characteristics as elevated address electrodes, various address wiring techniques, planarized mirror surfaces suing Chemical Mechanical Polishing, unique post-process metallization, and the best active surface area to date.

Silicon material technology status. [assessment for electronic and photovoltaic applications

NASA Technical Reports Server (NTRS)

Lutwack, R.

1983-01-01

Silicon has been the basic element for the electronic and photovoltaic industries. The use of silicon as the primary element for terrestrial photovoltaic solar arrays is projected to continue. The reasons for this projection are related to the maturity of silicon technology, the ready availability of extremely pure silicon, the performance of silicon solar cells, and the considerable present investment in technology and manufacturing facilities. The technologies for producing semiconductor grade silicon and, to a lesser extent, refined metallurgical grade silicon are considered. It is pointed out that nearly all of the semiconductor grade silicon is produced by processes based on the Siemens deposition reactor, a technology developed 26 years ago. The state-of-the-art for producing silicon by this process is discussed. It is expected that efforts to reduce polysilicon process costs will continue.

Measuring silicon pore optics

NASA Astrophysics Data System (ADS)

Vacanti, Giuseppe; Barrière, Nicolas; Bavdaz, Marcos; Chatbi, Abdelhakim; Collon, Maximilien; Dekker, Daniëlle; Girou, David; Günther, Ramses; van der Hoeven, Roy; Krumrey, Michael; Landgraf, Boris; Müller, Peter; Schreiber, Swenja; Vervest, Mark; Wille, Eric

2017-09-01

While predictions based on the metrology (local slope errors and detailed geometrical details) play an essential role in controlling the development of the manufacturing processes, X-ray characterization remains the ultimate indication of the actual performance of Silicon Pore Optics (SPO). For this reason SPO stacks and mirror modules are routinely characterized at PTB's X-ray Pencil Beam Facility at BESSY II. Obtaining standard X-ray results quickly, right after the production of X-ray optics is essential to making sure that X-ray results can inform decisions taken in the lab. We describe the data analysis pipeline in operations at cosine, and how it allows us to go from stack production to full X-ray characterization in 24 hours.

Dense arrays of millimeter-sized glass lenses fabricated at wafer-level.

PubMed

Albero, Jorge; Perrin, Stéphane; Bargiel, Sylwester; Passilly, Nicolas; Baranski, Maciej; Gauthier-Manuel, Ludovic; Bernard, Florent; Lullin, Justine; Froehly, Luc; Krauter, Johann; Osten, Wolfgang; Gorecki, Christophe

2015-05-04

This paper presents the study of a fabrication technique of lenses arrays based on the reflow of glass inside cylindrical silicon cavities. Lenses whose sizes are out of the microfabrication standards are considered. In particular, the case of high fill factor arrays is discussed in detail since the proximity between lenses generates undesired effects. These effects, not experienced when lenses are sufficiently separated so that they can be considered as single items, are corrected by properly designing the silicon cavities. Complete topographic as well as optical characterizations are reported. The compatibility of materials with Micro-Opto-Electromechanical Systems (MOEMS) integration processes makes this technology attractive for the miniaturization of inspection systems, especially those devoted to imaging.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2004-12-07

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process For Direct Integration Of A Thin-Film Silicon P-N Junction Diode With A Magnetic Tunnel Junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2005-08-23

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2003-01-01

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Fluidized bed silicon deposition from silane

NASA Technical Reports Server (NTRS)

Hsu, George C. (Inventor); Levin, Harry (Inventor); Hogle, Richard A. (Inventor); Praturi, Ananda (Inventor); Lutwack, Ralph (Inventor)

1982-01-01

A process and apparatus for thermally decomposing silicon containing gas for deposition on fluidized nucleating silicon seed particles is disclosed. Silicon seed particles are produced in a secondary fluidized reactor by thermal decomposition of a silicon containing gas. The thermally produced silicon seed particles are then introduced into a primary fluidized bed reactor to form a fluidized bed. Silicon containing gas is introduced into the primary reactor where it is thermally decomposed and deposited on the fluidized silicon seed particles. Silicon seed particles having the desired amount of thermally decomposed silicon product thereon are removed from the primary fluidized reactor as ultra pure silicon product. An apparatus for carrying out this process is also disclosed.

Fluidized bed silicon deposition from silane

NASA Technical Reports Server (NTRS)

Hsu, George (Inventor); Levin, Harry (Inventor); Hogle, Richard A. (Inventor); Praturi, Ananda (Inventor); Lutwack, Ralph (Inventor)

1984-01-01

A process and apparatus for thermally decomposing silicon containing gas for deposition on fluidized nucleating silicon seed particles is disclosed. Silicon seed particles are produced in a secondary fluidized reactor by thermal decomposition of a silicon containing gas. The thermally produced silicon seed particles are then introduced into a primary fluidized bed reactor to form a fludized bed. Silicon containing gas is introduced into the primary reactor where it is thermally decomposed and deposited on the fluidized silicon seed particles. Silicon seed particles having the desired amount of thermally decomposed silicon product thereon are removed from the primary fluidized reactor as ultra pure silicon product. An apparatus for carrying out this process is also disclosed.

Microwave absorbing property of silicone rubber composites with added carbonyl iron particles and graphite platelet

NASA Astrophysics Data System (ADS)

Xu, Yonggang; Zhang, Deyuan; Cai, Jun; Yuan, Liming; Zhang, Wenqiang

2013-02-01

Silicone rubber composites filled with carbonyl iron particles (CIPs) and graphite platelet (GP) were prepared using non-coating or coating processes. The complex permittivity and permeability of the composites were measured using a vector network analyzer in the frequency range of 1-18 GHz and dc electric conductivity was measured by the standard four-point contact method. The results showed that CIPs/GP composites fabricated in the coating process had the highest permittivity and permeability due to the particle orientation and interactions between the two absorbents. The coating process resulted in a decreased effective eccentricity of the absorbents, and the dc conductivity increased according to Neelakanta's equations. The reflection loss (RL) value showed that the composites had an excellent absorbing property in the L-band, minimum -11.85 dB at 1.5 mm and -15.02 dB at 2 mm. Thus, GP could be an effective additive in preparing thin absorbing composites in the L-band.

A continuous silicon-coating facility

NASA Technical Reports Server (NTRS)

Butter, C.; Heaps, J. D.

1979-01-01

Automatic continuous silicon-coating facility is used to process 100 by 10 cm graphite-coated ceramic substrates for silicon solar cells. Process reduces contamination associated with conventional dip-coating processes, improving material service life.

Three-dimensional atomic mapping of hydrogenated polymorphous silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Wanghua, E-mail: wanghua.chen@polytechnique.edu; Roca i Cabarrocas, Pere; Pareige, Philippe

Hydrogenated polymorphous silicon (pm-Si:H) is a nanostructured material consisting of silicon nanocrystals embedded in an amorphous silicon matrix. Its use as the intrinsic layer in thin film p-i-n solar cells has led to good cell properties in terms of stability and efficiency. Here, we have been able to assess directly the concentration and distribution of nanocrystals and impurities (dopants) in p-i-n solar cells, by using femtosecond laser-assisted atom probe tomography (APT). An effective sample preparation method for APT characterization is developed. Based on the difference in atomic density between hydrogenated amorphous and crystalline silicon, we are able to distinguish themore » nanocrystals from the amorphous matrix by using APT. Moreover, thanks to the three-dimensional reconstruction, we demonstrate that Si nanocrystals are homogeneously distributed in the entire intrinsic layer of the solar cell. The influence of the process pressure on the incorporation of nanocrystals and their distribution is also investigated. Thanks to APT we could determine crystalline fractions as low as 4.2% in the pm-Si:H films, which is very difficult to determine by standard techniques, such as X-ray diffraction, Raman spectroscopy, and spectroscopic ellipsometry. Moreover, we also demonstrate a sharp p/i interface in our solar cells.« less

Investigation of high-speed Si photodetectors in standard CMOS technology

NASA Astrophysics Data System (ADS)

Wang, Huaqiang; Guo, Xia

2018-05-01

In this paper, the frequency response characteristics of the photodetector(PD) were studied considering intrinsic and extrinsic effects. Then we designed the interdigitated p-i-n PD on Silicon-on-Insulator (SOI) and epitaxial (EPI) substrates with photosensitive area of 30-μm diameter, fabricated by CMOS process. The 2-μm finger-spacing devices exhibited a 205 MHz bandwidth at a reverse bias of 3 V processed on 2-μm SOI substrates. EPI devices with 1 μm finger spacing exhibited a 131 MHz bandwidth under -3 V. Responsivity of 0.051 A/W and 0.21 A/W were measured at 850 nm on SOI and EPI substrates, respectively. Compared with the bulk silicon PD, the bandwidth is greatly improved. The PD gains the high cost performance ratio, which can be widely used in short distance communication such as visible light communication and free space optical communication.

The quantitative analysis of silicon carbide surface smoothing by Ar and Xe cluster ions

NASA Astrophysics Data System (ADS)

Ieshkin, A. E.; Kireev, D. S.; Ermakov, Yu. A.; Trifonov, A. S.; Presnov, D. E.; Garshev, A. V.; Anufriev, Yu. V.; Prokhorova, I. G.; Krupenin, V. A.; Chernysh, V. S.

2018-04-01

The gas cluster ion beam technique was used for the silicon carbide crystal surface smoothing. The effect of processing by two inert cluster ions, argon and xenon, was quantitatively compared. While argon is a standard element for GCIB, results for xenon clusters were not reported yet. Scanning probe microscopy and high resolution transmission electron microscopy techniques were used for the analysis of the surface roughness and surface crystal layer quality. The gas cluster ion beam processing results in surface relief smoothing down to average roughness about 1 nm for both elements. It was shown that xenon as the working gas is more effective: sputtering rate for xenon clusters is 2.5 times higher than for argon at the same beam energy. High resolution transmission electron microscopy analysis of the surface defect layer gives values of 7 ± 2 nm and 8 ± 2 nm for treatment with argon and xenon clusters.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

2013-05-01

Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

Development of processes for the production of solar grade silicon from halides and alkali metals, phase 1 and phase 2

NASA Technical Reports Server (NTRS)

Dickson, C. R.; Gould, R. K.; Felder, W.

1981-01-01

High temperature reactions of silicon halides with alkali metals for the production of solar grade silicon are described. Product separation and collection processes were evaluated, measure heat release parameters for scaling purposes and effects of reactants and/or products on materials of reactor construction were determined, and preliminary engineering and economic analysis of a scaled up process were made. The feasibility of the basic process to make and collect silicon was demonstrated. The jet impaction/separation process was demonstrated to be a purification process. The rate at which gas phase species from silicon particle precursors, the time required for silane decomposition to produce particles, and the competing rate of growth of silicon seed particles injected into a decomposing silane environment were determined. The extent of silane decomposition as a function of residence time, temperature, and pressure was measured by infrared absorption spectroscopy. A simplistic model is presented to explain the growth of silicon in a decomposing silane enviroment.

[Study of purity tests for silicone resins].

PubMed

Sato, Kyoko; Otsuki, Noriko; Ohori, Akio; Chinda, Mitsuru; Furusho, Noriko; Osako, Tsutomu; Akiyama, Hiroshi; Kawamura, Yoko

2012-01-01

In the 8th edition of Japan's Specifications and Standards for Food Additives, the purity test for silicone resins requires the determination of the refractive index and kinetic viscosity of the extracted silicone oil, and allows for only a limited amount of silicon dioxide. In the purity test, carbon tetrachloride is used to separate the silicone oil and silicon dioxide. To exclude carbon tetrachloride, methods were developed for separating the silicone oil and silicon dioxide from silicone resin, which use hexane and 10% n-dodecylbenzenesulfonic acid in hexane. For silicone oil, the measured refractive index and kinetic viscosity of the silicone oil obtained from the hexane extract were shown to be equivalent to those of the intact silicone oil. In regard to silicon dioxide, it was confirmed that, following the separation with 10% n-dodecylbenzenesulfonic acid in hexane, the level of silicon dioxide in silicone resin can be accurately determined. Therefore, in this study, we developed a method for testing the purity of silicone resins without the use of carbon tetrachloride, which is a harmful reagent.

Silicon photonics and challenges for fabrication

NASA Astrophysics Data System (ADS)

Feilchenfeld, N. B.; Nummy, K.; Barwicz, T.; Gill, D.; Kiewra, E.; Leidy, R.; Orcutt, J. S.; Rosenberg, J.; Stricker, A. D.; Whiting, C.; Ayala, J.; Cucci, B.; Dang, D.; Doan, T.; Ghosal, M.; Khater, M.; McLean, K.; Porth, B.; Sowinski, Z.; Willets, C.; Xiong, C.; Yu, C.; Yum, S.; Giewont, K.; Green, W. M. J.

2017-03-01

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

Dimensional Stability of Hexoloy SA® Silicon Carbide and Zerodur™ Materials for the LISA Mission

NASA Astrophysics Data System (ADS)

Preston, Alix; Cruz, Rachel J.; Thorpe, J. Ira; Mueller, Guido; Boothe, G. Trask; Delgadillo, Rodrigo; Guntaka, Sridhar R.

2006-11-01

In the LISA mission, incoming gravitational waves will modulate the distance between proof masses while laser beams monitor the optical path length changes with 20 pm/√Hz accuracy. Optical path length changes between bench components or the relative motion between the primary and secondary mirrors of the telescope need to be well below this level to result in a successful operation of LISA. The reference cavity for frequency stabilization must have a dimensional stability of a few fm/√Hz. While the effects of temperature fluctuations are well characterized in most materials at the macroscopic level (i.e. coefficients of thermal expansion), microscopic material internal processes and long term processes in the bonds between different components can dominate the dimensional stability at the pm or fm levels. Zerodur and ULE have been well studied, but the ultimate stabilities of other materials like silicon carbide or CFRP are virtually unknown. Chemical bonding techniques, like hydroxide bonding, provide significantly stronger bonds than the standard optical contacts. However, the noise levels of these bonds are also unknown. In this paper we present our latest results on the stability of silicon carbide and hydroxide bonds on Zerodur.

Thermo-mechanical performance of precision C/SiC mounts

NASA Astrophysics Data System (ADS)

Goodman, William A.; Mueller, Claus E.; Jacoby, Marc T.; Wells, Jim D.

2001-12-01

For complex shaped, lightweight, high precision opto- mechanical structures that must operate in adverse environments and over wide ranges of temperature, we consider IABG's optical grade silicon carbide composite ceramic (C/SiC) as the material of choice. C/SiC employs conventional NC machining/milling equipment to rapidly fabricate near-net shape parts, providing substantial schedule, cost, and risk savings for high precision components. Unlike powder based SiC ceramics, C/SiC does not experience significant shrinkage during processing, nor does it suffer from incomplete densification. If required, e.g. for large-size components, a fully-monolithic ceramic joining technique can be applied. Generally, the thermal and mechanical properties of C/SiC are tunable in certain ranges by modifying certain process steps. This paper focuses on the thermo-mechanical performance of new, high precision mounts designed by Schafer Corporation and manufactured by IABG. The mounts were manufactured using standard optical grade C/SiC (formulation internally called A-3). The A-3 formulation has a near-perfect CTE match with silicon, making it the ideal material to athermally support Schafer produced Silicon Lightweight Mirrors (SLMs) that will operate in a cryogenic environment. Corresponding thermo- mechanical testing and analysis is presented in this manuscript.

Short Shot Tower for Silicon

NASA Technical Reports Server (NTRS)

Bates, H. E.; Hill, D. M.; Jewett, D. N.

1983-01-01

Drop length necessary to convert molten silicon to shot reduced by proposed new process. Conversion of silicon from powder or chunks to shot often simplifies processing. Shot is more easily handled in most processing equipment. Drops of liquid silicon fall through protective cloud of argon, then through rapidly cooling bath of methanol, where they quickly turn into solid shot.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Topics investigated include: measurements of transistor delay time; application of the infrared response technique to the study of radiation-damaged, lithium-drifted silicon detectors; and identification of a condition that minimizes wire flexure and reduces the failure rate of wire bonds in transistors and integrated circuits under slow thermal cycling conditions. Supplementary data concerning staff, standards committee activities, technical services, and publications are included as appendixes.

Fabricating solar cells with silicon nanoparticles

DOEpatents

Loscutoff, Paul; Molesa, Steve; Kim, Taeseok

2014-09-02

A laser contact process is employed to form contact holes to emitters of a solar cell. Doped silicon nanoparticles are formed over a substrate of the solar cell. The surface of individual or clusters of silicon nanoparticles is coated with a nanoparticle passivation film. Contact holes to emitters of the solar cell are formed by impinging a laser beam on the passivated silicon nanoparticles. For example, the laser contact process may be a laser ablation process. In that case, the emitters may be formed by diffusing dopants from the silicon nanoparticles prior to forming the contact holes to the emitters. As another example, the laser contact process may be a laser melting process whereby portions of the silicon nanoparticles are melted to form the emitters and contact holes to the emitters.

Process for Polycrystalline film silicon growth

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2001-01-01

A process for depositing polycrystalline silicon on substrates, including foreign substrates, occurs in a chamber at about atmospheric pressure, wherein a temperature gradient is formed, and both the atmospheric pressure and the temperature gradient are maintained throughout the process. Formation of a vapor barrier within the chamber that precludes exit of the constituent chemicals, which include silicon, iodine, silicon diiodide, and silicon tetraiodide. The deposition occurs beneath the vapor barrier. One embodiment of the process also includes the use of a blanketing gas that precludes the entrance of oxygen or other impurities. The process is capable of repetition without the need to reset the deposition zone conditions.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Improved process for epitaxial deposition of silicon on prediffused substrates

NASA Technical Reports Server (NTRS)

Clarke, M. G.; Halsor, J. L.; Word, J. C.

1968-01-01

Process for fabricating integrated circuits uniformly deposits silicon epitaxially on prediffused substrates without affecting the sublayer diffusion pattern. Two silicon deposits from different sources, and deposited at different temperatures, protect the sublayer pattern from the silicon tetrachloride reaction.

Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

PubMed

Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

2013-01-01

The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

Application of EAP materials toward a refreshable Braille display

NASA Astrophysics Data System (ADS)

Di Spigna, N.; Chakraborti, P.; Yang, P.; Ghosh, T.; Franzon, P.

2009-03-01

The development of a multiline, refreshable Braille display will assist with the full inclusion and integration of blind people into society. The use of both polyvinylidene fluoride (PVDF) film planar bending mode actuators and silicone dielectric elastomer cylindrical tube actuators have been investigated for their potential use in a Braille cell. A liftoff process that allows for aggressive scaling of miniature bimorph actuators has been developed using standard semiconductor lithography techniques. The PVDF bimorphs have been demonstrated to provide enough displacement to raise a Braille dot using biases less than 1000V and operating at 10Hz. In addition, silicone tube actuators have also been demonstrated to achieve the necessary displacement, though requiring higher voltages. The choice of electrodes and prestrain conditions aimed at maximizing axial strain in tube actuators are discussed. Characterization techniques measuring actuation displacement and blocking forces appropriate for standard Braille cell specifications are presented. Finally, the integration of these materials into novel cell designs and the fabrication of a prototype Braille cell are discussed.

Flat-plate solar array project: Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

NASA Technical Reports Server (NTRS)

1983-01-01

The process technology for the manufacture of semiconductor-grade silicon in a large commercial plant by 1986, at a price less than $14 per kilogram of silicon based on 1975 dollars is discussed. The engineering design, installation, checkout, and operation of an Experimental Process System Development unit was discussed. Quality control of scaling-up the process and an economic analysis of product and production costs are discussed.

The economic payoff for a state-of-the-art high-efficiency flat-plate crystalline silicon solar cell technology

NASA Technical Reports Server (NTRS)

Bickler, Donald B.; Callaghan, W. T.

1987-01-01

In 1986 during the flat-plate solar array project, silicon solar cells 4.0 sq cm in area were fabricated at the Jet Propulsion Laboratory (JPL) with a conversion efficiency of 20.1 percent (AM1.5-global). Sixteen cells were processed with efficiencies measuring 19.5 percent (AM1.5 global) or better. These cells were produced using refined versions of conventional processing methods, aside from certain advanced techniques that bring about a significant reduction in a major mechanism (surface recombination) that limits cell efficiency. Wacker Siltronic p-type float-zone 0.18-ohm-cm wafers were used. Conversion efficiencies in this range have previously been reported by other researchers, but generally on much smaller (0.5 vs. 4.0 cm) devices which have undergone sophisticated and costly processing steps. An economic analysis is presented of the potential payoffs for this approach, using the Solar Array Manufacturing Industry Costing Standards (SAMICS) methodology. The process sequence used and the assumptions made for capturing the economies of scale are presented.

Silicon web process development

NASA Technical Reports Server (NTRS)

Duncan, C. S.; Seidensticker, R. G.; Mchugh, J. P.; Skutch, M. E.; Driggers, J. M.; Hopkins, R. H.

1981-01-01

The silicon web process takes advantage of natural crystallographic stabilizing forces to grow long, thin single crystal ribbons directly from liquid silicon. The ribbon, or web, is formed by the solidification of a liquid film supported by surface tension between two silicon filaments, called dendrites, which border the edges of the growing strip. The ribbon can be propagated indefinitely by replenishing the liquid silicon as it is transformed to crystal. The dendritic web process has several advantages for achieving low cost, high efficiency solar cells. These advantages are discussed.

Silicon web process development

NASA Technical Reports Server (NTRS)

Duncan, C. S.; Seidensticker, R. G.; Mchugh, J. P.; Blais, P. D.; Davis, J. R., Jr.

1977-01-01

Thirty-five (35) furnace runs were carried out during this quarter, of which 25 produced a total of 120 web crystals. The two main thermal models for the dendritic growth process were completed and are being used to assist the design of the thermal geometry of the web growth apparatus. The first model, a finite element representation of the susceptor and crucible, was refined to give greater precision and resolution in the critical central region of the melt. The second thermal model, which describes the dissipation of the latent heat to generate thickness-velocity data, was completed. Dendritic web samples were fabricated into solar cells using a standard configuration and a standard process for a N(+) -P-P(+) configuration. The detailed engineering design was completed for a new dendritic web growth facility of greater width capability than previous facilities.

Chemical vapor deposition growth

NASA Technical Reports Server (NTRS)

Ruth, R. P.; Manasevit, H. M.; Kenty, J. L.; Moudy, L. A.; Simpson, W. I.; Yang, J. J.

1976-01-01

The chemical vapor deposition (CVD) method for the growth of Si sheet on inexpensive substrate materials is investigated. The objective is to develop CVD techniques for producing large areas of Si sheet on inexpensive substrate materials, with sheet properties suitable for fabricating solar cells meeting the technical goals of the Low Cost Silicon Solar Array Project. Specific areas covered include: (1) modification and test of existing CVD reactor system; (2) identification and/or development of suitable inexpensive substrate materials; (3) experimental investigation of CVD process parameters using various candidate substrate materials; (4) preparation of Si sheet samples for various special studies, including solar cell fabrication; (5) evaluation of the properties of the Si sheet material produced by the CVD process; and (6) fabrication and evaluation of experimental solar cell structures, using standard and near-standard processing techniques.

Process Feasibility Study in Support of Silicon Material Task 1

NASA Technical Reports Server (NTRS)

Li, K. Y.; Hansen, K. C.; Yaws, C. L.

1979-01-01

Analysis of process system properties was continued for silicon source materials under consideration for producing silicon. The following property data are reported for dichlorosilane which is involved in processing operations for silicon: critical constants, vapor pressure, heat of vaporization, heat capacity, density, surface tension, thermal conductivity, heat of formation and Gibb's free energy of formation. The properties are reported as a function of temperature to permit rapid engineering usage. The preliminary economic analysis of the process is described. Cost analysis results for the process (case A-two deposition reactors and six electrolysis cells) are presented based on a preliminary process design of a plant to produce 1,000 metric tons/year of silicon. Fixed capital investment estimate for the plant is $12.47 million (1975 dollars) ($17.47 million, 1980 dollars). Product cost without profit is 8.63 $/kg of silicon (1975 dollars)(12.1 $/kg, 1980 dollars).

Flat-plate solar array project. Volume 2: Silicon material

NASA Technical Reports Server (NTRS)

Lutwack, R.

1986-01-01

The goal of the Silicon Material Task, a part of the Flat Plate Solar Array (FSA) Project, was to develop and demonstate the technology for the low cost production of silicon of suitable purity to be used as the basic material for the manufacture of terrestrial photovoltaic solar cells. Summarized are 11 different processes for the production of silicon that were investigated and developed to varying extent by industrial, university, and Government researchers. The silane production section of the Union Carbide Corp. (UCC) silane process was developed completely in this program. Coupled with Siemens-type chemical vapor deposition reactors, the process was carried through the pilot stage. The overall UCC process involves the conversion of metallurgical-grade silicon to silane followed by decomposition of the silane to purified silicon. The other process developments are described to varying extents. Studies are reported on the effects of impurities in silicon on both silicon-material properties and on solar cell performance. These studies on the effects of impurities yielded extensive information and models for relating specific elemental concentrations to levels of deleterious effects.

Flat-plate solar array project. Volume 2: Silicon material

NASA Astrophysics Data System (ADS)

Lutwack, R.

1986-10-01

The goal of the Silicon Material Task, a part of the Flat Plate Solar Array (FSA) Project, was to develop and demonstate the technology for the low cost production of silicon of suitable purity to be used as the basic material for the manufacture of terrestrial photovoltaic solar cells. Summarized are 11 different processes for the production of silicon that were investigated and developed to varying extent by industrial, university, and Government researchers. The silane production section of the Union Carbide Corp. (UCC) silane process was developed completely in this program. Coupled with Siemens-type chemical vapor deposition reactors, the process was carried through the pilot stage. The overall UCC process involves the conversion of metallurgical-grade silicon to silane followed by decomposition of the silane to purified silicon. The other process developments are described to varying extents. Studies are reported on the effects of impurities in silicon on both silicon-material properties and on solar cell performance. These studies on the effects of impurities yielded extensive information and models for relating specific elemental concentrations to levels of deleterious effects.

New technologies for solar energy silicon - Cost analysis of BCL process

NASA Technical Reports Server (NTRS)

Yaws, C. L.; Li, K.-Y.; Fang, C. S.; Lutwack, R.; Hsu, G.; Leven, H.

1980-01-01

New technologies for producing polysilicon are being developed to provide lower cost material for solar cells which convert sunlight into electricity. This article presents results for the BCL Process, which produces the solar-cell silicon by reduction of silicon tetrachloride with zinc vapor. Cost, sensitivity, and profitability analysis results are presented based on a preliminary process design of a plant to produce 1000 metric tons/year of silicon by the BCL Process. Profitability analysis indicates a sales price of $12.1-19.4 per kg of silicon (1980 dollars) at a 0-25 per cent DCF rate of return on investment after taxes. These results indicate good potential for meeting the goal of providing lower cost material for silicon solar cells.

Silicon materials task of the low cost solar array project. Phase 3: Effect of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Davis, J. R.; Blais, P. D.; Rohatgi, A.; Campbell, R. B.; Rai-Choudhury, P.; Mollenkopf, H. C.; Mccormick, J. R.

1979-01-01

The 13th quarterly report of a study entitled an Investigation of the Effects of Impurities and Processing on Silicon Solar Cells is given. The objective of the program is to define the effects of impurities, various thermochemical processes and any impurity-process interactions on the performance of terrestrial silicon solar cells. The Phase 3 program effort falls in five areas: (1) cell processing studies; (2) completion of the data base and impurity-performance modeling for n-base cells; (3) extension of p-base studies to include contaminants likely to be introduced during silicon production, refining or crystal growth; (4) anisotropy effects; and (5) a preliminary study of the permanence of impurity effects in silicon solar cells. The quarterly activities for this report focus on tasks (1), (3) and (4).

Application Of Optical Processing For Growth Of Silicon Dioxide

DOEpatents

Sopori, Bhushan L.

1997-06-17

A process for producing a silicon dioxide film on a surface of a silicon substrate. The process comprises illuminating a silicon substrate in a substantially pure oxygen atmosphere with a broad spectrum of visible and infrared light at an optical power density of from about 3 watts/cm.sup.2 to about 6 watts/cm.sup.2 for a time period sufficient to produce a silicon dioxide film on the surface of the silicon substrate. An optimum optical power density is about 4 watts/cm.sup.2 for growth of a 100.ANG.-300.ANG. film at a resultant temperature of about 400.degree. C. Deep level transient spectroscopy analysis detects no measurable impurities introduced into the silicon substrate during silicon oxide production and shows the interface state density at the SiO.sub.2 /Si interface to be very low.

Improved toughness of silicon carbide

NASA Technical Reports Server (NTRS)

Palm, J. A.

1975-01-01

Several techniques were employed to apply or otherwise form porous layers of various materials on the surface of hot-pressed silicon carbide ceramic. From mechanical properties measurements and studies, it was concluded that although porous layers could be applied to the silicon carbide ceramic, sufficient damage was done to the silicon carbide surface by the processing required so as to drastically reduce its mechanical strength. It was further concluded that there was little promise of success in forming an effective energy absorbing layer on the surface of already densified silicon carbide ceramic that would have the mechanical strength of the untreated or unsurfaced material. Using a process for the pressureless sintering of silicon carbide powders it was discovered that porous layers of silicon carbide could be formed on a dense, strong silicon carbide substrate in a single consolidation process.

Solar silicon via the Dow Corning process

NASA Technical Reports Server (NTRS)

Hunt, L. P.; Dosaj, V. D.

1979-01-01

Technical feasibility for high volume production of solar cell-grade silicon is investigated. The process consists of producing silicon from pure raw materials via the carbothermic reduction of quartz. This silicon was then purified to solar grade by impurity segregation during Czochralski crystal growth. Commercially available raw materials were used to produce 100 kg quantities of silicon during 60 hour periods in a direct arc reactor. This silicon produced single crystalline ingot, during a second Czochralski pull, that was fabricated into solar cells having efficiencies ranging from 8.2 percent to greater than 14 percent. An energy analysis of the entire process indicated a 5 month payback time.

Field-induced negative differential spin lifetime in silicon.

PubMed

Li, Jing; Qing, Lan; Dery, Hanan; Appelbaum, Ian

2012-04-13

We show that the electric-field-induced thermal asymmetry between the electron and lattice systems in pure silicon substantially impacts the identity of the dominant spin relaxation mechanism. Comparison of empirical results from long-distance spin transport devices with detailed Monte Carlo simulations confirms a strong spin depolarization beyond what is expected from the standard Elliott-Yafet theory even at low temperatures. The enhanced spin-flip mechanism is attributed to phonon emission processes during which electrons are scattered between conduction band valleys that reside on different crystal axes. This leads to anomalous behavior, where (beyond a critical field) reduction of the transit time between spin-injector and spin-detector is accompanied by a counterintuitive reduction in spin polarization and an apparent negative spin lifetime.

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Rai-Choudhury, P.; Mollenkopf, H. C.

1981-01-01

The effects of impurities, various thermochemical processes, and any impurity-process interactions upon the performance of terrestrial solar cells are defined. The results form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost benefit relationships for the use of less pure, less costly solar grade silicon.

Process for strengthening silicon based ceramics

DOEpatents

Kim, Hyoun-Ee; Moorhead, A. J.

1993-01-01

A process for strengthening silicon based ceramic monolithic materials and omposite materials that contain silicon based ceramic reinforcing phases that requires that the ceramic be exposed to a wet hydrogen atmosphere at about 1400.degree. C. The process results in a dense, tightly adherent silicon containing oxide layer that heals, blunts , or otherwise negates the detrimental effect of strength limiting flaws on the surface of the ceramic body.

Process for strengthening silicon based ceramics

DOEpatents

Kim, Hyoun-Ee; Moorhead, A. J.

1993-04-06

A process for strengthening silicon based ceramic monolithic materials and omposite materials that contain silicon based ceramic reinforcing phases that requires that the ceramic be exposed to a wet hydrogen atmosphere at about 1400.degree. C. The process results in a dense, tightly adherent silicon containing oxide layer that heals, blunts , or otherwise negates the detrimental effect of strength limiting flaws on the surface of the ceramic body.

Process of preparing tritiated porous silicon

DOEpatents

Tam, Shiu-Wing

1997-01-01

A process of preparing tritiated porous silicon in which porous silicon is equilibrated with a gaseous vapor containing HT/T.sub.2 gas in a diluent for a time sufficient for tritium in the gas phase to replace hydrogen present in the pore surfaces of the porous silicon.

60-nm-thick basic photonic components and Bragg gratings on the silicon-on-insulator platform.

PubMed

Zou, Zhi; Zhou, Linjie; Li, Xinwan; Chen, Jianping

2015-08-10

We demonstrate integrated basic photonic components and Bragg gratings using 60-nm-thick silicon-on-insulator strip waveguides. The ultra-thin waveguides exhibit a propagation loss of 0.61 dB/cm and a bending loss of approximately 0.015 dB/180° with a 30 μm bending radius (including two straight-bend waveguide junctions). Basic structures based on the ultra-thin waveguides, including micro-ring resonators, 1 × 2 MMI couplers, and Mach-Zehnder interferometers are realized. Upon thinning-down, the waveguide effective refractive index is reduced, making the fabrication of Bragg gratings possible using the standard 248-nm deep ultra-violet (DUV) photolithography process. The Bragg grating exhibits a stopband width of 1 nm and an extinction ratio of 35 dB, which is practically applicable as an optical filter or a delay line. The transmission spectrum can be thermally tuned via an integrated resistive micro-heater formed by a heavily doped silicon slab beside the waveguide.

High-directionality fiber-chip grating coupler with interleaved trenches and subwavelength index-matching structure.

PubMed

Benedikovic, Daniel; Alonso-Ramos, Carlos; Cheben, Pavel; Schmid, Jens H; Wang, Shurui; Xu, Dan-Xia; Lapointe, Jean; Janz, Siegfried; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, J Gonzalo; Molina-Fernández, Iñigo; Fédéli, Jean-Marc; Vivien, Laurent; Dado, Milan

2015-09-15

We present the first experimental demonstration of a new fiber-chip grating coupler concept that exploits the blazing effect by interleaving the standard full (220 nm) and shallow etch (70 nm) trenches in a 220 nm thick silicon layer. The high directionality is obtained by controlling the separation between the deep and shallow trenches to achieve constructive interference in the upward direction and destructive interference toward the silicon substrate. Utilizing this concept, the grating directionality can be maximized independent of the bottom oxide thickness. The coupler also includes a subwavelength-engineered index-matching region, designed to reduce the reflectivity at the interface between the injection waveguide and the grating. We report a measured fiber-chip coupling efficiency of -1.3  dB, the highest coupling efficiency achieved to date for a surface grating coupler in a 220 nm silicon-on-insulator platform fabricated in a conventional dual-etch process without high-index overlays or bottom mirrors.

Demonstration of bacterial biofilms in culture-negative silicone stent and jones tube.

PubMed

Parsa, Kami; Schaudinn, Christoph; Gorur, Amita; Sedghizadeh, Parish P; Johnson, Thomas; Tse, David T; Costerton, John W

2010-01-01

To demonstrate the presence of bacterial biofilms on a dacryocystorhinostomy silicone stent and a Jones tube. One dacryocystorhinostomy silicone stent and one Jones tube were removed from 2 patients who presented with an infection of their respective nasolacrimal system. Cultures were obtained, and the implants were processed for scanning electron microscopy and confocal laser scanning microscopy, advanced microscopic methods that are applicable for detection of uncultivable biofilm organisms. Routine bacterial cultures revealed no growth, but bacterial biofilms on outer and inner surfaces of both implants were confirmed by advanced microscopic techniques. To the authors' knowledge, this is the first article that documents the presence of biofilms on a Crawford stent or a Jones tube on patients who presented with infections involving the nasolacrimal system. Although initial cultures revealed absence of any bacterial growth, confocal laser scanning microscopy and scanning electron microscopy documented bacterial colonization. Clinicians should consider the role of biofilms and the limitation of our standard culturing techniques while treating patients with device- or implant-related infections.

Efficient Near-Infrared-Transparent Perovskite Solar Cells Enabling Direct Comparison of 4-Terminal and Monolithic Perovskite/Silicon Tandem Cells

DOE PAGES

Werner, Jeremie; Barraud, Loris; Walter, Arnaud; ...

2016-07-30

Combining market-proven silicon solar cell technology with an efficient wide band gap top cell into a tandem device is an attractive approach to reduce the cost of photovoltaic systems. For this, perovskite solar cells are promising high-efficiency top cell candidates, but their typical device size (<0.2 cm 2), is still far from standard industrial sizes. Here, we present a 1 cm 2 near-infrared transparent perovskite solar cell with 14.5% steadystate efficiency, as compared to 16.4% on 0.25 cm 2. By mechanically stacking these cells with silicon heterojunction cells, we experimentally demonstrate a 4-terminal tandem measurement with a steady-state efficiency ofmore » 25.2%, with a 0.25 cm 2 top cell. The developed top cell processing methods enable the fabrication of a 20.5% efficient and 1.43 cm 2 large monolithic perovskite/silicon heterojunction tandem solar cell, featuring a rear-side textured bottom cell to increase its near-infrared spectral response. Finally, we compare both tandem configurations to identify efficiency-limiting factors and discuss the potential for further performance improvement.« less

Efficient Near-Infrared-Transparent Perovskite Solar Cells Enabling Direct Comparison of 4-Terminal and Monolithic Perovskite/Silicon Tandem Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Werner, Jeremie; Barraud, Loris; Walter, Arnaud

Combining market-proven silicon solar cell technology with an efficient wide band gap top cell into a tandem device is an attractive approach to reduce the cost of photovoltaic systems. For this, perovskite solar cells are promising high-efficiency top cell candidates, but their typical device size (<0.2 cm 2), is still far from standard industrial sizes. Here, we present a 1 cm 2 near-infrared transparent perovskite solar cell with 14.5% steadystate efficiency, as compared to 16.4% on 0.25 cm 2. By mechanically stacking these cells with silicon heterojunction cells, we experimentally demonstrate a 4-terminal tandem measurement with a steady-state efficiency ofmore » 25.2%, with a 0.25 cm 2 top cell. The developed top cell processing methods enable the fabrication of a 20.5% efficient and 1.43 cm 2 large monolithic perovskite/silicon heterojunction tandem solar cell, featuring a rear-side textured bottom cell to increase its near-infrared spectral response. Finally, we compare both tandem configurations to identify efficiency-limiting factors and discuss the potential for further performance improvement.« less

Reduction of metal artifact in three-dimensional computed tomography (3D CT) with dental impression materials.

PubMed

Park, W S; Kim, K D; Shin, H K; Lee, S H

2007-01-01

Metal Artifact still remains one of the main drawbacks in craniofacial Three-Dimensional Computed Tomography (3D CT). In this study, we tried to test the efficacy of additional silicone dental impression materials as a "tooth shield" for the reduction of metal artifact caused by metal restorations and orthodontic appliances. 6 phantoms with 4 teeth were prepared for this in vitro study. Orthodontic bracket, bands and amalgam restorations were placed in each tooth to reproduce various intraoral conditions. Standardized silicone shields were fabricated and placed around the teeth. CT image acquisition was performed with and without silicone shields. Maximum value, mean, and standard deviation of Hounsfield Units (HU) were compared with the presence of silicone shields. In every situation, metal artifacts were reduced in quality and quantity when silicone shields are used. Amalgam restoration made most serious metal artifact. Silicone shields made by dental impression material might be effective way to reduce the metal artifact caused by dental restoration and orthodontic appliances. This will help more excellent 3D image from 3D CT in craniofacial area.

Process for producing amorphous and crystalline silicon nitride

DOEpatents

Morgan, P.E.D.; Pugar, E.A.

1985-11-12

A process for producing amorphous or crystalline silicon nitride is disclosed which comprises reacting silicon disulfide ammonia gas at elevated temperature. In a preferred embodiment silicon disulfide in the form of whiskers'' or needles is heated at temperature ranging from about 900 C to about 1,200 C to produce silicon nitride which retains the whisker or needle morphological characteristics of the silicon disulfide. Silicon carbide, e.g. in the form of whiskers, also can be prepared by reacting substituted ammonia, e.g. methylamine, or a hydrocarbon containing active hydrogen-containing groups, such as ethylene, with silicon disulfide, at elevated temperature, e.g. 900 C. 6 figs.

Process for producing amorphous and crystalline silicon nitride

DOEpatents

Morgan, Peter E. D.; Pugar, Eloise A.

1985-01-01

A process for producing amorphous or crystalline silicon nitride is disclosed which comprises reacting silicon disulfide ammonia gas at elevated temperature. In a preferred embodiment silicon disulfide in the form of "whiskers" or needles is heated at temperature ranging from about 900.degree. C. to about 1200.degree. C. to produce silicon nitride which retains the whisker or needle morphological characteristics of the silicon disulfide. Silicon carbide, e.g. in the form of whiskers, also can be prepared by reacting substituted ammonia, e.g. methylamine, or a hydrocarbon containing active hydrogen-containing groups, such as ethylene, with silicon disulfide, at elevated temperature, e.g. 900.degree. C.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

Relative efficiency calibration between two silicon drift detectors performed with a monochromatized X-ray generator over the 0.1-1.5 keV range

NASA Astrophysics Data System (ADS)

Hubert, S.; Boubault, F.

2018-03-01

In this article, we present the first X-ray calibration performed over the 0.1-1.5 keV spectral range by means of a soft X-ray Manson source and the monochromator SYMPAX. This monochromator, based on a classical Rowland geometry, presents the novelty to be able to board simultaneously two detectors and move them under vacuum in front of the exit slit of the monochromatizing stage. This provides the great advantage to perform radiometric measurements of the monochromatic X-ray photon flux with one reference detector while calibrating another X-ray detector. To achieve this, at least one secondary standard must be operated with SYMPAX. This paper presents thereby an efficiency transfer experiment between a secondary standard silicon drift detector (SDD), previously calibrated on BESSY II synchrotron Facility, and another one ("unknown" SDD), devoted to be used permanently with SYMPAX. The associated calibration process is described as well as corresponding results. Comparison with calibrated measurements performed at the Physikalisch-Technische Bundesanstalt (PTB) Radiometric Laboratory shows a very good agreement between the secondary standard and the unknown SDD.

Process of preparing tritiated porous silicon

DOEpatents

Tam, S.W.

1997-02-18

A process of preparing tritiated porous silicon is described in which porous silicon is equilibrated with a gaseous vapor containing HT/T{sub 2} gas in a diluent for a time sufficient for tritium in the gas phase to replace hydrogen present in the pore surfaces of the porous silicon. 1 fig.

Characterization of solar-grade silicon produced by the SiF4-Na process

NASA Technical Reports Server (NTRS)

Sanjurjo, A.; Sancier, K. M.; Emerson, R. M.; Leach, S. C.; Minahan, J.

1986-01-01

A process was developed for producing low cost solar grade silicon by the reaction between SiF4 gas and sodium metal. The results of the characterization of the silicon are presented. These results include impurity levels, electronic properties of the silicon after crystal growth, and the performance of solar photovoltaic cells fabricated from wafers of the single crystals. The efficiency of the solar cells fabricated from semiconductor silicon and SiF4-Na silicon was the same.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Process feasibility study in support of silicon material task 1

NASA Technical Reports Server (NTRS)

Li, K. Y.; Hansen, K. C.; Yaws, C. L.

1978-01-01

Process system properties are analyzed for materials involved in the alternate processes under consideration for solar cell grade silicon. The following property data are reported for trichlorosilane: critical constants, vapor pressure, heat of vaporization, gas heat capacity, liquid heat capacity, density, surface tension, viscosity, thermal conductivity, heat of formation, and Gibb's free energy of formation. Work continued on the measurement of gas viscosity values of silicon source materials. Gas phase viscosity values for silicon tetrafluoride between 40 C and 200 C were experimentally determined. Major efforts were expended on completion of the preliminary economic analysis of the silane process. Cost, sensitivity and profitability analysis results are presented based on a preliminary process design of a plant to produce 1,000 metric tons/year of silicon by the revised process.

Application of optical processing for growth of silicon dioxide

DOEpatents

Sopori, B.L.

1997-06-17

A process for producing a silicon dioxide film on a surface of a silicon substrate is disclosed. The process comprises illuminating a silicon substrate in a substantially pure oxygen atmosphere with a broad spectrum of visible and infrared light at an optical power density of from about 3 watts/cm{sup 2} to about 6 watts/cm{sup 2} for a time period sufficient to produce a silicon dioxide film on the surface of the silicon substrate. An optimum optical power density is about 4 watts/cm{sup 2} for growth of a 100{angstrom}-300{angstrom} film at a resultant temperature of about 400 C. Deep level transient spectroscopy analysis detects no measurable impurities introduced into the silicon substrate during silicon oxide production and shows the interface state density at the SiO{sub 2}/Si interface to be very low. 1 fig.

Forming high efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2014-09-09

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Forming high-efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2015-07-07

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Process for coating an object with silicon carbide

NASA Technical Reports Server (NTRS)

Levin, Harry (Inventor)

1989-01-01

A process for coating a carbon or graphite object with silicon carbide by contacting it with silicon liquid and vapor over various lengths of contact time. In the process, a stream of silicon-containing precursor material in gaseous phase below the decomposition temperature of said gas and a co-reactant, carrier or diluent gas such as hydrogen is passed through a hole within a high emissivity, thin, insulating septum into a reaction chamber above the melting point of silicon. The thin septum has one face below the decomposition temperature of the gas and an opposite face exposed to the reaction chamber. The precursor gas is decomposed directly to silicon in the reaction chamber. A stream of any decomposition gas and any unreacted precursor gas from said reaction chamber is removed. The object within the reaction chamber is then contacted with silicon, and recovered after it has been coated with silicon carbide.

Integrated Microreactor for Chemical and Biochemical Applications

NASA Technical Reports Server (NTRS)

Schwesinger, N.; Dressler, L.; Frank, Th.; Wurmus, H.

1995-01-01

A completely integrated microreactor was developed that allows for the processing of very small amounts of chemical solutions. The entire system comprises several pumps and valves arranged in different branches as well as a mixing unit and a reaction chamber. The streaming path of each branch contains two valves and one pump each. The pumps are driven by piezoelectric elements mounted on thin glass membranes. Each pump is about 3.5 mm x 3.5 mm x 0.7 mm. A pumping rate up to 25 microliters per hour can be achieved. The operational voltage ranges between 40 and 200 V. A volume stroke up to 1.5 millimeter is achievable from the membrane structures. The valves are designed as passive valves. Sealing is by thin metal films. The dimension of a valve unit is 0.8 x 0.8. 07 mm. The ends of the separate streaming branches are arranged to meet in one point. This point acts as the beginning of a mixer unit which contains several fork-shaped channels. The arrangement of these channels allows for the division of the whole liquid stream into partial streams and their reuniting. A homogeneous mixing of solutions and/or gases can be observed after having passed about 10 of the fork elements. A reaction chamber is arranged behind the mixing unit to support the chemical reaction of special fluids. This unit contains heating elements placed outside of the chamber. The complete system is arranged in a modular structure and is built up of silicon. It comprises three silicon wafers bonded together by applying the silicon direct bonding technology. The silicon structures are made only by wet chemical etching processes. The fluid connections to the outside are realized using standard injection needles glued into v-shaped structures on the silicon wafers. It is possible to integrate other components, like sensors or electronic circuits using silicon as the basic material.

FTIR study of silicon carbide amorphization by heavy ion irradiations

NASA Astrophysics Data System (ADS)

Costantini, Jean-Marc; Miro, Sandrine; Pluchery, Olivier

2017-03-01

We have measured at room temperature (RT) the Fourier-transform infra-red (FTIR) absorption spectra of ion-irradiated thin epitaxial films of cubic silicon carbide (3C-SiC) with 1.1 µm thickness on a 500 µm thick (1 0 0) silicon wafer substrate. Irradiations were carried out at RT with 2.3 MeV 28Si+ ions and 3.0 MeV 84Kr+ ions for various fluences in order to induce amorphization of the SiC film. Ion projected ranges were adjusted to be slightly larger than the film thickness so that the whole SiC layers were homogeneously damaged. FTIR spectra of virgin and irradiated samples were recorded for various incidence angles from normal incidence to Brewster’s angle. We show that the amorphization process in ion-irradiated 3C-SiC films can be monitored non-destructively by FTIR absorption spectroscopy without any major interference of the substrate. The compared evolutions of TO and LO peaks upon ion irradiation yield valuable information on the damage process. Complementary test experiments were also performed on virgin silicon nitride (Si3N4) self-standing films for similar conditions. Asymmetrical shapes were found for TO peaks of SiC, whereas Gaussian profiles are found for LO peaks. Skewed Gaussian profiles, with a standard deviation depending on wave number, were used to fit asymmetrical peaks for both materials. A new methodology for following the amorphization process is proposed on the basis of the evolution of fitted IR absorption peak parameters with ion fluence. Results are discussed with respect to Rutherford backscattering spectrometry channeling and Raman spectroscopy analysis.

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

NASA Astrophysics Data System (ADS)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

Chemical vapor deposition growth

NASA Technical Reports Server (NTRS)

Ruth, R. P.; Manasevit, H. M.; Campbell, A. G.; Johnson, R. E.; Kenty, J. L.; Moudy, L. A.; Shaw, G. L.; Simpson, W. I.; Yang, J. J.

1978-01-01

The objective was to investigate and develop chemical vapor deposition (CVD) techniques for the growth of large areas of Si sheet on inexpensive substrate materials, with resulting sheet properties suitable for fabricating solar cells that would meet the technical goals of the Low Cost Silicon Solar Array Project. The program involved six main technical tasks: (1) modification and test of an existing vertical-chamber CVD reactor system; (2) identification and/or development of suitable inexpensive substrate materials; (3) experimental investigation of CVD process parameters using various candidate substrate materials; (4) preparation of Si sheet samples for various special studies, including solar cell fabrication; (5) evaluation of the properties of the Si sheet material produced by the CVD process; and (6) fabrication and evaluation of experimental solar cell structures, using impurity diffusion and other standard and near-standard processing techniques supplemented late in the program by the in situ CVD growth of n(+)/p/p(+) sheet structures subsequently processed into experimental cells.

Hot Electron Injection into Uniaxially Strained Silicon

NASA Astrophysics Data System (ADS)

Kim, Hyun Soo

In semiconductor spintronics, silicon attracts great attention due to the long electron spin lifetime. Silicon is also one of the most commonly used semiconductor in microelectronics industry. The spin relaxation process of diamond crystal structure such as silicon is dominant by Elliot-Yafet mechanism. Yafet shows that intravalley scattering process is dominant. The conduction electron spin lifetime measured by electron spin resonance measurement and electronic measurement using ballistic hot electron method well agrees with Yafet's theory. However, the recent theory predicts a strong contribution of intervalley scattering process such as f-process in silicon. The conduction band minimum is close the Brillouin zone edge, X point which causes strong spin mixing at the conduction band. A recent experiment of electric field-induced hot electron spin relaxation also shows the strong effect of f-process in silicon. In uniaxially strained silicon along crystal axis [100], the suppression of f-process is predicted which leads to enhance electron spin lifetime. By inducing a change in crystal structure due to uniaxial strain, the six fold degeneracy becomes two fold degeneracy, which is valley splitting. As the valley splitting increases, intervalley scattering is reduced. A recent theory predicts 4 times longer electron spin lifetime in 0.5% uniaxially strained silicon. In this thesis, we demonstrate ballistic hot electron injection into silicon under various uniaxial strain. Spin polarized hot electron injection under strain is experimentally one of the most challenging part to measure conduction electron spin lifetime in silicon. Hot electron injection adopts tunnel junction which is a thin oxide layer between two conducting materials. Tunnel barrier, which is an oxide layer, is only 4 ˜ 5 nm thick. Also, two conducting materials are only tens of nanometer. Therefore, under high pressure to apply 0.5% strain on silicon, thin films on silicon substrate can be easily destroyed. In order to confirm the performance of tunnel junction, we use tunnel magnetoresistance(TMR). TMR consists of two kinds of ferromagnetic materials and an oxide layer as tunnel barrier in order to measure spin valve effect. Using silicon as a collector with Schottky barrier interface between metal and silicon, ballistic hot spin polarized electron injection into silicon is demonstrated. We also observed change of coercive field and magnetoresistance due to modification of local states in ferromagnetic materials and surface states at the interface between metal and silicon due to strain.

High-efficiency power transfer for silicon-based photonic devices

NASA Astrophysics Data System (ADS)

Son, Gyeongho; Yu, Kyoungsik

2018-02-01

We demonstrate an efficient coupling of guided light of 1550 nm from a standard single-mode optical fiber to a silicon waveguide using the finite-difference time-domain method and propose a fabrication method of tapered optical fibers for efficient power transfer to silicon-based photonic integrated circuits. Adiabatically-varying fiber core diameters with a small tapering angle can be obtained using the tube etching method with hydrofluoric acid and standard single-mode fibers covered by plastic jackets. The optical power transmission of the fundamental HE11 and TE-like modes between the fiber tapers and the inversely-tapered silicon waveguides was calculated with the finite-difference time-domain method to be more than 99% at a wavelength of 1550 nm. The proposed method for adiabatic fiber tapering can be applied in quantum optics, silicon-based photonic integrated circuits, and nanophotonics. Furthermore, efficient coupling within the telecommunication C-band is a promising approach for quantum networks in the future.

Silicon production process evaluations

NASA Technical Reports Server (NTRS)

1982-01-01

Engineering design of the third distillation column in the process was accomplished. The initial design is based on a 94.35% recovery of dichlorosilane in the distillate and a 99.9% recovery of trichlorosilane in the bottoms. The specified separation is achieved at a reflux ratio of 15 with 20 trays (equilibrium stages). Additional specifications and results are reported including equipment size, temperatures and pressure. Specific raw material requirements necessary to produce the silicon in the process are presented. The primary raw materials include metallurgical grade silicon, silicon tetrachloride, hydrogen, copper (catalyst) and lime (waste treatment). Hydrogen chloride is produced as by product in the silicon deposition. Cost analysis of the process was initiated during this reporting period.

Oblique patterned etching of vertical silicon sidewalls

NASA Astrophysics Data System (ADS)

Bruce Burckel, D.; Finnegan, Patrick S.; David Henry, M.; Resnick, Paul J.; Jarecki, Robert L.

2016-04-01

A method for patterning on vertical silicon surfaces in high aspect ratio silicon topography is presented. A Faraday cage is used to direct energetic reactive ions obliquely through a patterned suspended membrane positioned over the topography. The technique is capable of forming high-fidelity pattern (100 nm) features, adding an additional fabrication capability to standard top-down fabrication approaches.

Influence of hydrogen effusion from hydrogenated silicon nitride layers on the regeneration of boron-oxygen related defects in crystalline silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wilking, S., E-mail: Svenja.Wilking@uni-konstanz.de; Ebert, S.; Herguth, A.

The degradation effect boron doped and oxygen-rich crystalline silicon materials suffer from under illumination can be neutralized in hydrogenated silicon by the application of a regeneration process consisting of a combination of slightly elevated temperature and carrier injection. In this paper, the influence of variations in short high temperature steps on the kinetics of the regeneration process is investigated. It is found that hotter and longer firing steps allowing an effective hydrogenation from a hydrogen-rich silicon nitride passivation layer result in an acceleration of the regeneration process. Additionally, a fast cool down from high temperature to around 550 °C seems tomore » be crucial for a fast regeneration process. It is suggested that high cooling rates suppress hydrogen effusion from the silicon bulk in a temperature range where the hydrogenated passivation layer cannot release hydrogen in considerable amounts. Thus, the hydrogen content of the silicon bulk after the complete high temperature step can be increased resulting in a faster regeneration process. Hence, the data presented here back up the theory that the regeneration process might be a hydrogen passivation of boron-oxygen related defects.« less

Modified low-temperture direct bonding method for vacuum microelectronics application

NASA Astrophysics Data System (ADS)

Ju, Byeong-Kwon; Lee, Duck-Jung; Choi, Woo-Beom; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1997-06-01

This paper presents the process and experimental results for the improved silicon-to-glass bonding using silicon direct bonding (SDB) followed by anodic bonding. The initial bonding between glass and silicon was caused by the hydrophilic surfaces of silicon-glass ensemble using SDB method. Then the initially bonded specimen had to be strongly bonded by anodic bonding process. The effects of the bonding process parameters on the interface energy were investigated as functions of the bonding temperature and voltage. We found that the specimen which was bonded using SDB process followed by anodic bonding process had higher interface energy than one using anodic bonding process only. The main factor contributing to the higher interface energy in the glass-to-silicon assemble bonded by SDB followed by anodic bonding was investigated by secondary ion mass spectroscopy analysis.

Fabricating amorphous silicon solar cells by varying the temperature _of the substrate during deposition of the amorphous silicon layer

DOEpatents

Carlson, David E.

1982-01-01

An improved process for fabricating amorphous silicon solar cells in which the temperature of the substrate is varied during the deposition of the amorphous silicon layer is described. Solar cells manufactured in accordance with this process are shown to have increased efficiencies and fill factors when compared to solar cells manufactured with a constant substrate temperature during deposition of the amorphous silicon layer.

Monolithically integrated self-rolled-up microtube-based vertical coupler for three-dimensional photonic integration

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yu, Xin; Arbabi, Ehsan; Goddard, Lynford L.

2015-07-20

We demonstrate a self-rolled-up microtube-based vertical photonic coupler monolithically integrated on top of a ridge waveguide to achieve three-dimensional (3D) photonic integration. The fabrication process is fully compatible with standard planar silicon processing technology. Strong light coupling between the vertical coupler and the ridge waveguide was observed experimentally, which may provide an alternative route for 3D heterogeneous photonic integration. The highest extinction ratio observed in the transmission spectrum passing through the ridge waveguide was 23 dB.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

Silicon Nanowire Growth at Chosen Positions and Orientations

NASA Technical Reports Server (NTRS)

Getty, Stephanie A.

2009-01-01

It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.

Analysis and evaluation in the production process and equipment area of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Goldman, H.; Wolf, M.

1979-01-01

The energy consumed in manufacturing silicon solar cell modules was calculated for the current process, as well as for 1982 and 1986 projected processes. In addition, energy payback times for the above three sequences are shown. The module manufacturing energy was partitioned two ways. In one way, the silicon reduction, silicon purification, sheet formation, cell fabrication, and encapsulation energies were found. In addition, the facility, equipment, processing material and direct material lost-in-process energies were appropriated in junction formation processes and full module manufacturing sequences. A brief methodology accounting for the energy of silicon wafers lost-in-processing during cell manufacturing is described.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, Stephen M.; Tao, Hongyi; Todd-Copley, Judith A.

1991-01-01

A process for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, S.M.; Tao, H.; Todd-Copley, J.A.

1991-06-11

A process is disclosed for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength. 1 figure.

Al transmon qubits on silicon-on-insulator for quantum device integration

NASA Astrophysics Data System (ADS)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

NASA Technical Reports Server (NTRS)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

2016-01-01

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Fully Digital Arrays of Silicon Photomultipliers (dSiPM) - a Scalable Alternative to Vacuum Photomultiplier Tubes (PMT)

NASA Astrophysics Data System (ADS)

Haemisch, York; Frach, Thomas; Degenhardt, Carsten; Thon, Andreas

Silicon Photomultipliers (SiPMs) have emerged as promising alternative to fast vacuum photomultiplier tubes (PMT). A fully digital implementation of the Silicon Photomultiplier (dSiPM) has been developed in order to overcome the deficiencies and limitations of the so far only analog SiPMs (aSiPMs). Our sensor is based on arrays of single photon avalanche photodiodes (SPADs) integrated in a standard CMOS process. Photons are detected directly by sensing the voltage at the SPAD anode using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective inhibit of detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the integrated time-to-digital converter. In consequence, photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The integration with CMOS logic provides the added benefit of low power consumption and possible integration of data post-processing directly in the sensor. In this overview paper, we discuss the sensor architecture together with its characteristics with a focus on scalability and practicability aspects for applications in medical imaging, high energy- and astrophysics.

Mechanical characterization of poly-SiGe layers for CMOS-MEMS integrated application

NASA Astrophysics Data System (ADS)

Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; Puers, Robert; De Wolf, Ingrid

2010-01-01

Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups.

Reference Data for the Density and Viscosity of Liquid Cadmium, Cobalt, Gallium, Indium, Mercury, Silicon, Thallium, and Zinc

NASA Astrophysics Data System (ADS)

Assael, Marc J.; Armyra, Ivi J.; Brillo, Juergen; Stankus, Sergei V.; Wu, Jiangtao; Wakeham, William A.

2012-09-01

The available experimental data for the density and viscosity of liquid cadmium, cobalt, gallium, indium, mercury, silicon, thallium, and zinc have been critically examined with the intention of establishing both a density and a viscosity standard. All experimental data have been categorized into primary and secondary data according to the quality of measurement, the technique employed and the presentation of the data, as specified by a series of criteria. The proposed standard reference correlations for the density of liquid cadmium, cobalt, gallium, indium, silicon, thallium, and zinc are characterized by percent deviations at the 95% confidence level of 0.6, 2.1, 0.4, 0.5, 2.2, 0.9, and 0.7, respectively. In the case of mercury, since density reference values already exist, no further work was carried out. The standard reference correlations for the viscosity of liquid cadmium, cobalt, gallium, indium, mercury, silicon, thallium, and zinc are characterized by percent deviations at the 95% confidence level of 9.4, 14.0, 13.5, 2.1, 7.3, 15.7, 5.1, and 9.3, respectively.

Fluorescent porous silicon biological probes with high quantum efficiency and stability.

PubMed

Tu, Chang-Ching; Chou, Ying-Nien; Hung, Hsiang-Chieh; Wu, Jingda; Jiang, Shaoyi; Lin, Lih Y

2014-12-01

We demonstrate porous silicon biological probes as a stable and non-toxic alternative to organic dyes or cadmium-containing quantum dots for imaging and sensing applications. The fluorescent silicon quantum dots which are embedded on the porous silicon surface are passivated with carboxyl-terminated ligands through stable Si-C covalent bonds. The porous silicon bio-probes have shown photoluminescence quantum yield around 50% under near-UV excitation, with high photochemical and thermal stability. The bio-probes can be efficiently conjugated with antibodies, which is confirmed by a standard enzyme-linked immunosorbent assay (ELISA) method.

Surface reaction of silicon chlorides during atomic layer deposition of silicon nitride

NASA Astrophysics Data System (ADS)

Yusup, Luchana L.; Park, Jae-Min; Mayangsari, Tirta R.; Kwon, Young-Kyun; Lee, Won-Jun

2018-02-01

The reaction of precursor with surface active site is the critical step in atomic layer deposition (ALD) process. We performed the density functional theory calculation with DFT-D correction to study the surface reaction of different silicon chloride precursors during the first half cycle of ALD process. SiCl4, SiH2Cl2, Si2Cl6 and Si3Cl8 were considered as the silicon precursors, and an NH/SiNH2*-terminated silicon nitride surface was constructed to model the thermal ALD processes using NH3 as well as the PEALD processes using NH3 plasma. The total energies of the system were calculated for the geometry-optimized structures of physisorption, chemisorption, and transition state. The order of silicon precursors in energy barrier, from lowest to highest, is Si3Cl8 (0.92 eV), Si2Cl6 (3.22 eV), SiH2Cl2 (3.93 eV) and SiCl4 (4.49 eV). Silicon precursor with lower energy barrier in DFT calculation showed lower saturation dose in literature for both thermal and plasma-enhanced ALD of silicon nitride. Therefore, DFT calculation is a promising tool in predicting the reactivity of precursor during ALD process.

Process for producing silicon

DOEpatents

Olson, J.M.; Carleton, K.L.

1982-06-10

A process of producing silicon includes forming an alloy of copper and silicon and positioning the alloy in a dried, molten salt electrolyte to form a solid anode structure therein. An electrically conductive cathode is placed in the electrolyte for plating silicon thereon. The electrolyte is then purified to remove dissolved oxides. Finally, an electrical potential is applied between the anode and cathode in an amount sufficient to form substantially pure silicon on the cathode in the form of substantially dense, coherent deposits.

Process for producing silicon

DOEpatents

Olson, Jerry M.; Carleton, Karen L.

1984-01-01

A process for producing silicon includes forming an alloy of copper and silicon and positioning the alloy in a dried, molten salt electrolyte to form a solid anode structure therein. An electrically conductive cathode is placed in the electrolyte for plating silicon thereon. The electrolyte is then purified to remove dissolved oxides. Finally, an electrical potential is applied between the anode and cathode in an amount sufficient to form substantially pure silicon on the cathode in the form of substantially dense, coherent deposits.

Electroless epitaxial etching for semiconductor applications

DOEpatents

McCarthy, Anthony M.

2002-01-01

A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.

Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Hsieh, I.-Wei

In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic devices are quite different from those of electronic devices. Minimizing propagation losses by reducing sidewall roughness to nanometer scale over a device length of several millimeters or even centimeters has prompted researchers in academia and industry to refine the fabrication process. Chapter 3 of this thesis summarizes our efforts in fabricating silicon photonic devices using standard CMOS technology. Chapter 4 describes the characterization of nonlinear effects, including self-phase modulation (SPM), cross-phase modulation (XPM), and supercontinuum generation in silicon-wire waveguides. Silicon-wire waveguides are strip waveguides with submicron transverse dimensions, which allow strong light confinement inside the silicon core. This strong optical confinement, in addition to the large third-order nonlinear optical susceptibility of crystalline silicon, leads to a net nonlinearity which is several orders of magnitude higher than the nonlinearity of silica fiber. Significant nonlinear effects can be observed and characterized over a device length of only several millimeters in silicon wires with very small input power. These effects provide opportunities for engineers to design active silicon photonic devices which are compact and energy-efficient. Chapter 5 presents a realization of an integrated SOI optical isolator, which is a critical yet often overlooked component in photonic integrated circuits. This study shows the feasibility to make a hybrid garnet/SOI active device with very promising results. Finally, Chapter 6 summarizes our demonstration of transmitting terabit-scale data streams in silicon-wire waveguides, which is an important first-step towards enabling intra-chip interconnection networks with ultra-high bandwidths. Although the scope of this thesis is limited to providing only fractional views of the whole silicon photonics area, it provides enough references for interested readers to conduct further literature research in other aspects of silicon photonics. It is the author's hope that the thesis would convey to its readers the significance and potential of this exciting emerging technology.

Low Cost Fabrication of Silicon Carbide Based Ceramics and Fiber Reinforced Composites

NASA Technical Reports Server (NTRS)

Singh, M.; Levine, S. R.

1995-01-01

A low cost processing technique called reaction forming for the fabrication of near-net and complex shaped components of silicon carbide based ceramics and composites is presented. This process consists of the production of a microporous carbon preform and subsequent infiltration with liquid silicon or silicon-refractory metal alloys. The microporous preforms are made by the pyrolysis of a polymerized resin mixture with very good control of pore volume and pore size thereby yielding materials with tailorable microstructure and composition. Mechanical properties (elastic modulus, flexural strength, and fracture toughness) of reaction-formed silicon carbide ceramics are presented. This processing approach is suitable for various kinds of reinforcements such as whiskers, particulates, fibers (tows, weaves, and filaments), and 3-D architectures. This approach has also been used to fabricate continuous silicon carbide fiber reinforced ceramic composites (CFCC's) with silicon carbide based matrices. Strong and tough composites with tailorable matrix microstructure and composition have been obtained. Microstructure and thermomechanical properties of a silicon carbide (SCS-6) fiber reinforced reaction-formed silicon carbide matrix composites are discussed.

Preparation of High Purity Crystalline Silicon by Electro-Catalytic Reduction of Sodium Hexafluorosilicate with Sodium below 180°C

PubMed Central

Chen, Yuan; Liu, Yang; Wang, Xin; Li, Kai; Chen, Pu

2014-01-01

The growing field of silicon solar cells requires a substantial reduction in the cost of semiconductor grade silicon, which has been mainly produced by the rod-based Siemens method. Because silicon can react with almost all of the elements and form a number of alloys at high temperatures, it is highly desired to obtain high purity crystalline silicon at relatively low temperatures through low cost process. Here we report a fast, complete and inexpensive reduction method for converting sodium hexafluorosilicate into silicon at a relatively low reaction temperature (∼200°C). This temperature could be further decreased to less than 180°C in combination with an electrochemical approach. The residue sodium fluoride is dissolved away by pure water and hydrochloric acid solution in later purifying processes below 15°C. High purity silicon in particle form can be obtained. The relative simplicity of this method might lead to a low cost process in producing high purity silicon. PMID:25153509

Design, fabrication, and measurement of two silicon-based ultraviolet and blue-extended photodiodes

NASA Astrophysics Data System (ADS)

Chen, Changping; Wang, Han; Jiang, Zhenyu; Jin, Xiangliang; Luo, Jun

2014-12-01

Two silicon-based ultraviolet (UV) and blue-extended photodiodes are presented, which were fabricated for light detection in the ultraviolet/blue spectral range. Stripe-shaped and octagon-ring-shaped structures were designed to verify parameters of the UV-responsivity, UV-selectivity, breakdown voltage, and response time. The ultra-shallow lateral pn junction had been successfully realized in a standard 0.5-μm complementary metal oxide semiconductor (CMOS) process to enlarge the pn junction area, enhance the absorption of UV light, and improve the responsivity and quantum efficiency. The test results illustrated that the stripe-shaped structure has the lower breakdown voltage, higher UV-responsicity, and higher UV-selectivity. But the octagon-ring-shaped structure has the lower dark current. The response time of both structures was almost the same.

Research and development of low cost processes for integrated solar arrays. Final report, April 15, 1974--January 14, 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Graham, C.D.; Kulkarni, S.; Louis, E.

1976-05-01

Results of a program to study process routes leading to a low cost large area integrated silicon solar array manufacture for terrestrial applications are reported. Potential processes for the production of solar-grade silicon are evaluated from thermodynamic, economic, and technical feasibility points of view. Upgrading of the present arc-furnace process is found most favorable. Experimental studies of the Si/SiF/sub 4/ transport and purification process show considerable impurity removal and reasonable transport rates. Silicon deformation experiments indicate production of silicon sheet by rolling at 1350/sup 0/C is feasible. Significant recrystallization by strain-anneal technique has been observed. Experimental recrystallization studies using anmore » electron beam line source are discussed. A maximum recrystallization velocity of approximately 9 m/hr is calculated for silicon sheet. A comparative process rating technique based on detailed cost analysis is presented.« less

Characterisation results of the CMOS VISNIR spectral band detector for the METimage instrument

NASA Astrophysics Data System (ADS)

Pratlong, Jérôme; Schmuelling, Frank; Benitez, Victor; Breart De Boisanger, Michel; Skegg, Michael; Simpson, Robert; Bowring, Steve; Krzizok, Natalie

2017-09-01

The METimage instrument is part of the EPS-SG (EUMETSAT Polar System Second Generation) program. It will be situated on the MetOp-SG platform which in operation has an objective of collecting data for meteorology and climate monitoring as well as their forecasting. Teledyne e2v has developed and characterised the CMOS VISNIR detector flight module part of the METimage instrument. This paper will focus on the silicon results obtained from the CMOS VISNIR detector flight model. The detector is a large multi-linear device composed of 7 spectral bands covering a wavelength range from 428 nm to 923 nm (some bands are placed twice and added together to enhance the signal-to-noise performance). This detector uses a 4T pixel, with a size of 250μm square, presenting challenges to achieve good charge transfer efficiency with high conversion factor and good linearity for signal levels up to 2M electrons and with high line rates. Low noise has been achieved using correlated double sampling to suppress the read-out noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. The photodiode occupies a significant fraction of the large pixel area. This makes it possible to meet the detection efficiency when front illuminated. A thicker than standard epitaxial silicon is used to improve NIR response. However, the dielectric stack on top of the sensor produces Fabry-Perot étalon effects, which are problematic for narrow band illumination as this causes the detection efficiency to vary significantly over a small wavelength range. In order to reduce this effect and to meet the specification, the silicon manufacturing process has been modified. The flight model will have black coating deposited between each spectral channel, onto the active silicon regions.

Amorphous silicon Schottky barrier solar cells incorporating a thin insulating layer and a thin doped layer

DOEpatents

Carlson, David E.

1980-01-01

Amorphous silicon Schottky barrier solar cells which incorporate a thin insulating layer and a thin doped layer adjacent to the junction forming metal layer exhibit increased open circuit voltages compared to standard rectifying junction metal devices, i.e., Schottky barrier devices, and rectifying junction metal insulating silicon devices, i.e., MIS devices.

N-Type delta Doping of High-Purity Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Blacksberg, Jordana; Hoenk, Michael; Nikzad, Shouleh

2005-01-01

A process for n-type (electron-donor) delta doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays. Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac delta function (impulse function): the dopant is highly concentrated in a very thin layer. Preferably, the dopant is concentrated in one or at most two atomic layers in a crystal plane and, therefore, delta doping is also known as atomic-plane doping. The use of doping to enable detection of high-energy photons and low-energy particles was reported in several prior NASA Tech Briefs articles. As described in more detail in those articles, the main benefit afforded by delta doping of a back-illuminated silicon detector is to eliminate a "dead" layer at the back surface of the silicon wherein high-energy photons and low-energy particles are absorbed without detection. An additional benefit is that the delta-doped layer can serve as a back-side electrical contact. Delta doping of p-type silicon detectors is well established. The development of the present process addresses concerns specific to the delta doping of high-purity silicon detectors, which are typically n-type. The present process involves relatively low temperatures, is fully compatible with other processes used to fabricate the detectors, and does not entail interruption of those processes. Indeed, this process can be the last stage in the fabrication of an imaging detector that has, in all other respects, already been fully processed, including metallized. This process includes molecular-beam epitaxy (MBE) for deposition of three layers, including metallization. The success of the process depends on accurate temperature control, surface treatment, growth of high-quality crystalline silicon, and precise control of thicknesses of layers. MBE affords the necessary nanometer- scale control of the placement of atoms for delta doping. More specifically, the process consists of MBE deposition of a thin silicon buffer layer, the n-type delta doping layer, and a thin silicon cap layer. The n dopant selected for initial experiments was antimony, but other n dopants as (phosphorus or arsenic) could be used. All n-type dopants in silicon tend to surface-segregate during growth, leading to a broadened dopant-concentration- versus-depth profile. In order to keep the profile as narrow as possible, the substrate temperature is held below 300 C during deposition of the silicon cap layer onto the antimony delta layer. The deposition of silicon includes a silicon- surface-preparation step, involving H-termination, that enables the growth of high-quality crystalline silicon at the relatively low temperature with close to full electrical activation of donors in the surface layer.

Development of a process for high capacity-arc heater production of silicon

NASA Technical Reports Server (NTRS)

Reed, W. H.; Meyer, T. N.; Fey, M. G.; Harvey, F. J.; Arcella, F. G.

1978-01-01

The realization of low cost, electric power from large-area silicon, photovoltaic arrays will depend on the development of new methods for large capacity production of solar grade (SG) silicon with a cost of less than $10 per kilogram by 1986 (established Department of Energy goal). The objective of the program is to develop a method to produce SG silicon in large quantities based on the high temperature-sodium reduction of silicon tetrachloride (SiCl4) to yield molten silicon and the coproduct salt vapor (NaCl). Commercial ac electric arc heaters will be utilized to provide a hyper-heated mixture of argon and hydrogen which will furnish the required process energy. The reactor is designed for a nominal silicon flow rate of 45 kg/hr. Analyses and designs have been conducted to evaluate the process and complete the initial design of the experimental verification unit.

Porous siliconformation and etching process for use in silicon micromachining

DOEpatents

Guilinger, Terry R.; Kelly, Michael J.; Martin, Jr., Samuel B.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

A reproducible process for uniformly etching silicon from a series of micromechanical structures used in electrical devices and the like includes providing a micromechanical structure having a silicon layer with defined areas for removal thereon and an electrochemical cell containing an aqueous hydrofluoric acid electrolyte. The micromechanical structure is submerged in the electrochemical cell and the defined areas of the silicon layer thereon are anodically biased by passing a current through the electrochemical cell for a time period sufficient to cause the defined areas of the silicon layer to become porous. The formation of the depth of the porous silicon is regulated by controlling the amount of current passing through the electrochemical cell. The micromechanical structure is then removed from the electrochemical cell and submerged in a hydroxide solution to remove the porous silicon. The process is subsequently repeated for each of the series of micromechanical structures to achieve a reproducibility better than 0.3%.

Neuromorphic photonic networks using silicon photonic weight banks.

PubMed

Tait, Alexander N; de Lima, Thomas Ferreira; Zhou, Ellen; Wu, Allie X; Nahmias, Mitchell A; Shastri, Bhavin J; Prucnal, Paul R

2017-08-07

Photonic systems for high-performance information processing have attracted renewed interest. Neuromorphic silicon photonics has the potential to integrate processing functions that vastly exceed the capabilities of electronics. We report first observations of a recurrent silicon photonic neural network, in which connections are configured by microring weight banks. A mathematical isomorphism between the silicon photonic circuit and a continuous neural network model is demonstrated through dynamical bifurcation analysis. Exploiting this isomorphism, a simulated 24-node silicon photonic neural network is programmed using "neural compiler" to solve a differential system emulation task. A 294-fold acceleration against a conventional benchmark is predicted. We also propose and derive power consumption analysis for modulator-class neurons that, as opposed to laser-class neurons, are compatible with silicon photonic platforms. At increased scale, Neuromorphic silicon photonics could access new regimes of ultrafast information processing for radio, control, and scientific computing.

Impacts of Modification of Alloying Method on Inclusion Evolution in RH Refining of Silicon Steel.

PubMed

Li, Fangjie; Li, Huigai; Zheng, Shaobo; You, Jinglin; Han, Ke; Zhai, Qijie

2017-10-19

This study explores the effect of introducing additional alloy elements not only in a different order but also at different stages of the Ruhrstahl-Heraeus (RH) process of low-carbon silicon steel production. A more economical method, described as "pre-alloying", has been introduced. The evolution of MnO-FeO inclusions produced by pre-alloying was investigated. Results show that spherical 3FeO·MnO inclusions form first, then shelled FeO·zMnO (z = 0.7-4) inclusions nucleate on the surface of pre-existing 3FeO·MnO. Spherical FeO·zMnO (z = 3-5) is further evolved from shelled 3FeO·MnO by diffusion. Because these MnO-FeO inclusions float up into the slag before degassing, the pre-alloying process does not affect the quality of the melt in the end. Both carbon content and inclusion size conform to industry standards.

Impacts of Modification of Alloying Method on Inclusion Evolution in RH Refining of Silicon Steel

PubMed Central

Li, Huigai; Zheng, Shaobo; You, Jinglin; Han, Ke; Zhai, Qijie

2017-01-01

This study explores the effect of introducing additional alloy elements not only in a different order but also at different stages of the Ruhrstahl-Heraeus (RH) process of low-carbon silicon steel production. A more economical method, described as “pre-alloying”, has been introduced. The evolution of MnO-FeO inclusions produced by pre-alloying was investigated. Results show that spherical 3FeO·MnO inclusions form first, then shelled FeO·zMnO (z = 0.7–4) inclusions nucleate on the surface of pre-existing 3FeO·MnO. Spherical FeO·zMnO (z = 3–5) is further evolved from shelled 3FeO·MnO by diffusion. Because these MnO-FeO inclusions float up into the slag before degassing, the pre-alloying process does not affect the quality of the melt in the end. Both carbon content and inclusion size conform to industry standards. PMID:29048379

Biosensors based on cantilevers.

PubMed

Alvarez, Mar; Carrascosa, Laura G; Zinoviev, Kiril; Plaza, Jose A; Lechuga, Laura M

2009-01-01

Microcantilevers based-biosensors are a new label-free technique that allows the direct detection of biomolecular interactions in a label-less way and with great accuracy by translating the biointeraction into a nanomechanical motion. Low cost and reliable standard silicon technologies are widely used for the fabrication of cantilevers with well-controlled mechanical properties. Over the last years, the number of applications of these sensors has shown a fast growth in diverse fields, such as genomic or proteomic, because of the biosensor flexibility, the low sample consumption, and the non-pretreated samples required. In this chapter, we report a dedicated design and a fabrication process of highly sensitive microcantilever silicon sensors. We will describe as well an application of the device in the environmental field showing the immunodetection of an organic toxic pesticide as an example. The cantilever biofunctionalization process and the subsequent pesticide determination are detected in real time by monitoring the nanometer-scale bending of the microcantilever due to a differential surface stress generated between both surfaces of the device.

Method for analyzing passive silicon carbide thermometry with a continuous dilatometer to determine irradiation temperature

DOE PAGES

Campbell, Anne A.; Porter, Wallace D.; Katoh, Yutai; ...

2016-01-14

Silicon carbide is used as a passive post-irradiation temperature monitor because the irradiation defects will anneal out above the irradiation temperature. The irradiation temperature is determined by measuring a property change after isochronal annealing, i.e., lattice spacing, dimensions, electrical resistivity, thermal diffusivity, or bulk density. However, such methods are time-consuming since the steps involved must be performed in a serial manner. This work presents the use of thermal expansion from continuous dilatometry to calculate the SiC irradiation temperature, which is an automated process requiring minimal setup time. Analysis software was written that performs the calculations to obtain the irradiation temperaturemore » and removes possible user-introduced error while standardizing the analysis. In addition, this method has been compared to an electrical resistivity and isochronal annealing investigation, and the results revealed agreement of the calculated temperatures. These results show that dilatometry is a reliable and less time-intensive process for determining irradiation temperature from passive SiC thermometry.« less

Method for analyzing passive silicon carbide thermometry with a continuous dilatometer to determine irradiation temperature

NASA Astrophysics Data System (ADS)

Campbell, Anne A.; Porter, Wallace D.; Katoh, Yutai; Snead, Lance L.

2016-03-01

Silicon carbide is used as a passive post-irradiation temperature monitor because the irradiation defects will anneal out above the irradiation temperature. The irradiation temperature is determined by measuring a property change after isochronal annealing, i.e., lattice spacing, dimensions, electrical resistivity, thermal diffusivity, or bulk density. However, such methods are time-consuming since the steps involved must be performed in a serial manner. This work presents the use of thermal expansion from continuous dilatometry to calculate the SiC irradiation temperature, which is an automated process requiring minimal setup time. Analysis software was written that performs the calculations to obtain the irradiation temperature and removes possible user-introduced error while standardizing the analysis. This method has been compared to an electrical resistivity and isochronal annealing investigation, and the results revealed agreement of the calculated temperatures. These results show that dilatometry is a reliable and less time-intensive process for determining irradiation temperature from passive SiC thermometry.

Interaction between antimony atoms and micropores in silicon

NASA Astrophysics Data System (ADS)

Odzhaev, V. B.; Petlitskii, A. N.; Plebanovich, V. I.; Sadovskii, P. K.; Tarasik, M. I.; Chelyadinskii, A. R.

2018-01-01

The interaction between Sb atoms and micropores of a getter layer in silicon is studied. The getter layer was obtained via implantation of Sb+ ions into silicon and subsequent heat treatment processes. The antimony atoms located in the vicinity of micropores are captured by micropores during gettering annealing and lose its electrical activity. The activation energy of capture process to the pores for antimony is lower than that of antimony diffusion in silicon deformation fields around microvoids on the diffusion process.

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

NASA Technical Reports Server (NTRS)

Reck, Theodore (Inventor); Perez, Jose Vicente Siles (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Jung-Kubiak, Cecile (Inventor); Mehdi, Imran (Inventor); Chattopadhyay, Goutam (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Naturally occurring 32Si and low-background silicon dark matter detectors

DOE PAGES

Orrell, John L.; Arnquist, Isaac J.; Bliss, Mary; ...

2018-02-10

Here, the naturally occurring radioisotope 32Si represents a potentially limiting background in future dark matter direct-detection experiments. We investigate sources of 32Si and the vectors by which it comes to reside in silicon crystals used for fabrication of radiation detectors. We infer that the 32Si concentration in commercial single-crystal silicon is likely variable, dependent upon the specific geologic and hydrologic history of the source (or sources) of silicon “ore” and the details of the silicon-refinement process. The silicon production industry is large, highly segmented by refining step, and multifaceted in terms of final product type, from which we conclude thatmore » production of 32Si-mitigated crystals requires both targeted silicon material selection and a dedicated refinement-through-crystal-production process. We review options for source material selection, including quartz from an underground source and silicon isotopically reduced in 32Si. To quantitatively evaluate the 32Si content in silicon metal and precursor materials, we propose analytic methods employing chemical processing and radiometric measurements. Ultimately, it appears feasible to produce silicon detectors with low levels of 32Si, though significant assay method development is required to validate this claim and thereby enable a quality assurance program during an actual controlled silicon-detector production cycle.« less

Naturally occurring 32Si and low-background silicon dark matter detectors

NASA Astrophysics Data System (ADS)

Orrell, John L.; Arnquist, Isaac J.; Bliss, Mary; Bunker, Raymond; Finch, Zachary S.

2018-05-01

The naturally occurring radioisotope 32Si represents a potentially limiting background in future dark matter direct-detection experiments. We investigate sources of 32Si and the vectors by which it comes to reside in silicon crystals used for fabrication of radiation detectors. We infer that the 32Si concentration in commercial single-crystal silicon is likely variable, dependent upon the specific geologic and hydrologic history of the source (or sources) of silicon "ore" and the details of the silicon-refinement process. The silicon production industry is large, highly segmented by refining step, and multifaceted in terms of final product type, from which we conclude that production of 32Si-mitigated crystals requires both targeted silicon material selection and a dedicated refinement-through-crystal-production process. We review options for source material selection, including quartz from an underground source and silicon isotopically reduced in 32Si. To quantitatively evaluate the 32Si content in silicon metal and precursor materials, we propose analytic methods employing chemical processing and radiometric measurements. Ultimately, it appears feasible to produce silicon detectors with low levels of 32Si, though significant assay method development is required to validate this claim and thereby enable a quality assurance program during an actual controlled silicon-detector production cycle.

Naturally occurring 32Si and low-background silicon dark matter detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orrell, John L.; Arnquist, Isaac J.; Bliss, Mary

Here, the naturally occurring radioisotope 32Si represents a potentially limiting background in future dark matter direct-detection experiments. We investigate sources of 32Si and the vectors by which it comes to reside in silicon crystals used for fabrication of radiation detectors. We infer that the 32Si concentration in commercial single-crystal silicon is likely variable, dependent upon the specific geologic and hydrologic history of the source (or sources) of silicon “ore” and the details of the silicon-refinement process. The silicon production industry is large, highly segmented by refining step, and multifaceted in terms of final product type, from which we conclude thatmore » production of 32Si-mitigated crystals requires both targeted silicon material selection and a dedicated refinement-through-crystal-production process. We review options for source material selection, including quartz from an underground source and silicon isotopically reduced in 32Si. To quantitatively evaluate the 32Si content in silicon metal and precursor materials, we propose analytic methods employing chemical processing and radiometric measurements. Ultimately, it appears feasible to produce silicon detectors with low levels of 32Si, though significant assay method development is required to validate this claim and thereby enable a quality assurance program during an actual controlled silicon-detector production cycle.« less

Naturally occurring 32 Si and low-background silicon dark matter detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orrell, John L.; Arnquist, Isaac J.; Bliss, Mary

The naturally occurring radioisotope Si-32 represents a potentially limiting background in future dark matter direct-detection experiments. We investigate sources of Si-32 and the vectors by which it comes to reside in silicon crystals used for fabrication of radiation detectors. We infer that the Si-32 concentration in commercial single-crystal silicon is likely variable, dependent upon the specific geologic and hydrologic history of the source (or sources) of silicon “ore” and the details of the silicon-refinement process. The silicon production industry is large, highly segmented by refining step, and multifaceted in terms of final product type, from which we conclude that productionmore » of Si-32-mitigated crystals requires both targeted silicon material selection and a dedicated refinement-through-crystal-production process. We review options for source material selection, including quartz from an underground source and silicon isotopically reduced in Si-32. To quantitatively evaluate the Si-32 content in silicon metal and precursor materials, we propose analytic methods employing chemical processing and radiometric measurements. Ultimately, it appears feasible to produce silicon-based detectors with low levels of Si-32, though significant assay method development is required to validate this claim and thereby enable a quality assurance program during an actual controlled silicon-detector production cycle.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lutwack, R.

The goal of the Silicon Material Task, a part of the FSA Project, was to develop and demonstrate the technology for the low-cost production of silicon of suitable purity to be used as the basic material for the manufacture of terrestrial photovoltaic solar cells. To be compatible with the price goals of the FSA Project, the price of the produced silicon was to be less than $10/kg (in 1975 dollars). Summarized in this document are 11 different processes for the production of silicon that were investigated and developed to varying extent by industrial, university, and government researchers. The silane-production sectionmore » of the Union Carbide Corp. (UCC) silane process was developed completely in this program. Coupled with Siemens-type chemical vapor deposition reactors, the process was carried through the pilot plant stage. The overall UCC process involves the conversion of metallurgical-grade silicon to silane followed by decomposition of the silane to purified silicon. Production of very high-purity silane and silicon was demonstrated. Although it has as yet not achieved commercial application, the development of fluidized-bed technology for the low-cost, high-throughput conversion of silane-to-silicon has been demonstrated in the research laboratory and now is in engineering development.« less

Porous silicon carbide (SIC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Process Research On Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.; Wohlgemuth, J. H.

1982-01-01

Performance limiting mechanisms in polycrystalline silicon are investigated by fabricating a matrix of solar cells of various thicknesses from polycrystalline silicon wafers of several bulk resistivities. The analysis of the results for the entire matrix indicates that bulk recombination is the dominant factor limiting the short circuit current in large grain (greater than 1 to 2 mm diameter) polycrystalline silicon, the same mechanism that limits the short circuit current in single crystal silicon. An experiment to investigate the limiting mechanisms of open circuit voltage and fill factor for large grain polycrystalline silicon is designed. Two process sequences to fabricate small cells are investigated.

Thermodynamics of Volatile Species in the Silicon-Oxygen-Hydrogen System Studied

NASA Technical Reports Server (NTRS)

Jacobson, Nathan S.; Opila, Elizabeth J.; Copland, Evan H.; Myers, Dwight

2005-01-01

The volatilization of silica (SiO2) to silicon hydroxides and oxyhydroxides because of reaction with water vapor is important in a variety of high-temperature corrosion processes. For example, the lifetimes of silicon carbide (SiC) and silicon nitride (Si3N4) - based components in combustion environments are limited by silica volatility. To understand and model this process, it is essential to have accurate thermodynamic data for the formation of volatile silicon hydroxides and oxyhydroxides.

Solar technology assessment project. Volume 6: Photovoltaic technology assessment

NASA Astrophysics Data System (ADS)

Backus, C. E.

1981-04-01

Industrial production of photovoltaic systems and volume of sales are reviewed. Low cost silicon production techniques are reviewed, including the Czochralski process, heat exchange method, edge defined film fed growth, dentritic web growth, and silicon on ceramic process. Semicrystalline silicon, amorphous silicon, and low cost poly-silicon are discussed as well as advanced materials and concentrator systems. Balance of system components beyond those needed to manufacture the solar panels are included. Nontechnical factors are assessed. The 1986 system cost goals are briefly reviewed.

Silicon-gate CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1979-01-01

Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discussed, as well as the following process variations: (1) the double epi process; and (2) ion implantation.

Process for producing organic products containing silicon, hydrogen, nitrogen, and carbon by the direct reaction between elemental silicon and organic amines and products formed thereby

DOEpatents

Pugar, E.A.; Morgan, P.E.D.

1988-04-04

A process is disclosed for producing, at a low temperature, a high purity organic reaction product consisting essentially of silicon, hydrogen, nitrogen, and carbon. The process comprises reacting together a particulate elemental high purity silicon with a high purity reactive amine reactant in a liquid state at a temperature of from about O/degree/C up to about 300/degree/C. A high purity silicon carbide/silicon nitride ceramic product can be formed from this intermediate product, if desired, by heating the intermediate product at a temperature of from about 1200-1700/degree/C for a period from about 15 minutes up to about 2 hours or the organic reaction product may be employed in other chemical uses.

Process for producing organic products containing silicon, hydrogen, nitrogen, and carbon by the direct reaction between elemental silicon and organic amines

DOEpatents

Pugar, Eloise A.; Morgan, Peter E. D.

1990-04-03

A process is disclosed for producing, at a low temperature, a high purity organic reaction product consisting essentially of silicon, hydrogen, nitrogen, and carbon. The process comprises reacting together a particulate elemental high purity silicon with a high purity reactive amine reactant in a liquid state at a temperature of from about 0.degree. C. up to about 300.degree. C. A high purity silicon carbide/silicon nitride ceramic product can be formed from this intermediate product, if desired, by heating the intermediate product at a temperature of from about 1200.degree.-1700.degree. C. for a period from about 15 minutes up to about 2 hours or the organic reaction product may be employed in other chemical uses.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Silicon photonics for high-performance interconnection networks

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr

2011-12-01

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow.

IIIV/Si Nanoscale Lasers and Their Integration with Silicon Photonics

NASA Astrophysics Data System (ADS)

Bondarenko, Olesya

The rapidly evolving global information infrastructure requires ever faster data transfer within computer networks and stations. Integrated chip scale photonics can pave the way to accelerated signal manipulation and boost bandwidth capacity of optical interconnects in a compact and ergonomic arrangement. A key building block for integrated photonic circuits is an on-chip laser. In this dissertation we explore ways to reduce the physical footprint of semiconductor lasers and make them suitable for high density integration on silicon, a standard material platform for today's integrated circuits. We demonstrated the first room temperature metalo-dielectric nanolaser, sub-wavelength in all three dimensions. Next, we demonstrated a nanolaser on silicon, showing the feasibility of its integration with this platform. We also designed and realized an ultracompact feedback laser with edge-emitting structure, amenable for in-plane coupling with a standard silicon waveguide. Finally, we discuss the challenges and propose solutions for improvement of the device performance and practicality.

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

DOE Office of Scientific and Technical Information (OSTI.GOV)

Springer, J.; Allen, B.; Wriggins, W.

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirementmore » for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.« less

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

NASA Astrophysics Data System (ADS)

Springer, J.; Allen, B.; Wriggins, W.; Kuzbyt, R.; Sinclair, R.

2012-11-01

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirement for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.

Processes for producing low cost, high efficiency silicon solar cells

DOEpatents

Rohatgi, Ajeet; Chen, Zhizhang; Doshi, Parag

1996-01-01

Processes which utilize rapid thermal processing (RTP) are provided for inexpensively producing high efficiency silicon solar cells. The RTP processes preserve minority carrier bulk lifetime .tau. and permit selective adjustment of the depth of the diffused regions, including emitter and back surface field (bsf), within the silicon substrate. Silicon solar cell efficiencies of 16.9% have been achieved. In a first RTP process, an RTP step is utilized to simultaneously diffuse phosphorus and aluminum into the front and back surfaces, respectively, of a silicon substrate. Moreover, an in situ controlled cooling procedure preserves the carrier bulk lifetime .tau. and permits selective adjustment of the depth of the diffused regions. In a second RTP process, both simultaneous diffusion of the phosphorus and aluminum as well as annealing of the front and back contacts are accomplished during the RTP step. In a third RTP process, the RTP step accomplishes simultaneous diffusion of the phosphorus and aluminum, annealing of the contacts, and annealing of a double-layer antireflection/passivation coating SiN/SiO.sub.x.

Neurovascular Modeling: Small-Batch Manufacturing of Silicone Vascular Replicas

PubMed Central

Chueh, J.Y.; Wakhloo, A.K.; Gounis, M.J.

2009-01-01

BACKGROUND AND PURPOSE Realistic, population based cerebrovascular replicas are required for the development of neuroendovascular devices. The objective of this work was to develop an efficient methodology for manufacturing realistic cerebrovascular replicas. MATERIALS AND METHODS Brain MR angiography data from 20 patients were acquired. The centerline of the vasculature was calculated, and geometric parameters were measured to describe quantitatively the internal carotid artery (ICA) siphon. A representative model was created on the basis of the quantitative measurements. Using this virtual model, we designed a mold with core-shell structure and converted it into a physical object by fused-deposit manufacturing. Vascular replicas were created by injection molding of different silicones. Mechanical properties, including the stiffness and luminal coefficient of friction, were measured. RESULTS The average diameter, length, and curvature of the ICA siphon were 4.15 ± 0.09 mm, 22.60 ± 0.79 mm, and 0.34 ± 0.02 mm-1 (average ± standard error of the mean), respectively. From these image datasets, we created a median virtual model, which was transformed into a physical replica by an efficient batch-manufacturing process. The coefficient of friction of the luminal surface of the replica was reduced by up to 55% by using liquid silicone rubber coatings. The modulus ranged from 0.67 to 1.15 MPa compared with 0.42 MPa from human postmortem studies, depending on the material used to make the replica. CONCLUSIONS Population-representative, smooth, and true-to-scale silicone arterial replicas with uniform wall thickness were successfully built for in vitro neurointerventional device-testing by using a batch-manufacturing process. PMID:19321626

Converting a carbon preform object to a silicon carbide object

NASA Technical Reports Server (NTRS)

Levin, Harry (Inventor)

1990-01-01

A process for converting in depth a carbon or graphite preform object to a silicon carbide object, silicon carbide/silicon object, silicon carbide/carbon-core object, or a silicon carbide/silicon/carbon-core object, by contacting it with silicon liquid and vapor over various lengths of contact time in a reaction chamber. In the process, a stream comprised of a silicon-containing precursor material in gaseous phase below the decomposition temperature of said gas and a coreactant, carrier or diluent gas such as hydrogen is passed through a hole within a high emissivity, thin, insulating septum into the reaction chamber above the melting point of silicon. The thin septum has one face below the decomposition temperature of the gas and an opposite face exposed to the reaction chamber. Thus, the precursor gas is decomposed directly to silicon in the reaction chamber. Any stream of decomposition gas and any unreacted precursor gas from the reaction chamber is removed. A carbon or graphite preform object placed in the reaction chamber is contacted with the silicon. The carbon or graphite preform object is recovered from the reactor chamber after it has been converted to a desired silicon carbide, silicon and carbon composition.

Mode-converting coupler for silicon-on-sapphire devices

NASA Astrophysics Data System (ADS)

Zlatanovic, S.; Offord, B. W.; Owen, M.; Shimabukuro, R.; Jacobs, E. W.

2015-02-01

Silicon-on-sapphire devices are attractive for the mid-infrared optical applications up to 5 microns due to the low loss of both silicon and sapphire in this wavelength band. Designing efficient couplers for silicon-on-sapphire devices presents a challenge due to a highly confined mode in silicon and large values of refractive index of both silicon and sapphire. Here, we present design, fabrication, and measurements of a mode-converting coupler for silicon-on-sapphire waveguides. We utilize a mode converter layout that consists of a large waveguide that is overlays a silicon inverse tapered waveguide. While this geometry was previously utilized for silicon-on-oxide devices, the novelty is in using materials that are compatible with the silicon-on-sapphire platform. In the current coupler the overlaying waveguide is made of silicon nitride. Silicon nitride is the material of choice because of the large index of refraction and low absorption from near-infrared to mid-infrared. The couplers were fabricated using a 0.25 micron silicon-on-sapphire process. The measured coupling loss from tapered lensed silica fibers to the silicon was 4.8dB/coupler. We will describe some challenges in fabrication process and discuss ways to overcome them.

Process feasibility study in support of silicon material, task 1

NASA Technical Reports Server (NTRS)

Li, K. Y.; Hansen, K. C.; Yaws, C. L.

1979-01-01

Analyses of process system properties were continued for materials involved in the alternate processes under consideration for semiconductor silicon. Primary efforts centered on physical and thermodynamic property data for dichlorosilane. The following property data are reported for dichlorosilane which is involved in processing operations for solar cell grade silicon: critical temperature, critical pressure, critical volume, critical density, acentric factor, vapor pressure, heat of vaporization, gas heat capacity, liquid heat capacity and density. Work was initiated on the assembly of a system to prepare binary gas mixtures of known proportions and to measure the thermal conductivity of these mixtures between 30 and 350 C. The binary gas mixtures include silicon source material such as silanes and halogenated silanes which are used in the production of semiconductor silicon.

Optimization of the bake-on siliconization of cartridges. Part I: Optimization of the spray-on parameters.

PubMed

Funke, Stefanie; Matilainen, Julia; Nalenz, Heiko; Bechtold-Peters, Karoline; Mahler, Hanns-Christian; Friess, Wolfgang

2016-07-01

Biopharmaceutical products are increasingly commercialized as drug/device combinations to enable self-administration. Siliconization of the inner syringe/cartridge glass barrel for adequate functionality is either performed at the supplier or drug product manufacturing site. Yet, siliconization processes are often insufficiently investigated. In this study, an optimized bake-on siliconization process for cartridges using a pilot-scale siliconization unit was developed. The following process parameters were investigated: spray quantity, nozzle position, spray pressure, time for pump dosing and the silicone emulsion concentration. A spray quantity of 4mg emulsion showed best, immediate atomization into a fine spray. 16 and 29mg of emulsion, hence 4-7-times the spray volume, first generated an emulsion jet before atomization was achieved. Poor atomization of higher quantities correlated with an increased spray loss and inhomogeneous silicone distribution, e.g., due to runlets forming build-ups at the cartridge lower edge and depositing on the star wheel. A prolonged time for pump dosing of 175ms led to a more intensive, long-lasting spray compared to 60ms as anticipated from a higher air-to-liquid ratio. A higher spray pressure of 2.5bar did not improve atomization but led to an increased spray loss. At a 20mm nozzle-to-flange distance the spray cone exactly reached the cartridge flange, which was optimal for thicker silicone layers at the flange to ease piston break-loose. Initially, 10μg silicone was sufficient for adequate extrusion in filled cartridges. However, both maximum break-loose and gliding forces in filled cartridges gradually increased from 5-8N to 21-22N upon 80weeks storage at room temperature. The increase for a 30μg silicone level from 3-6N to 10-12N was moderate. Overall, the study provides a comprehensive insight into critical process parameters during the initial spray-on process and the impact of these parameters on the characteristics of the silicone layer, also in context of long-term product storage. The presented experimental toolbox may be utilized for development or evaluation of siliconization processes. Copyright © 2016 Elsevier B.V. All rights reserved.

Study Methods to Standardize Thermography NDE

NASA Technical Reports Server (NTRS)

Walker, James L.; Workman, Gary L.

1998-01-01

The purpose of this work is to develop thermographic inspection methods and standards for use in evaluating structural composites and aerospace hardware. Qualification techniques and calibration methods are investigated to standardize the thermographic method for use in the field. Along with the inspections of test standards structural hardware, support hardware is designed and fabricated to aid in the thermographic process. Also, a standard operating procedure is developed for performing inspections with the Bales Thermal Image Processor (TIP). Inspections are performed on a broad range of structural composites. These materials include various graphite/epoxies, graphite/cyanide-ester, graphite/silicon-carbide, graphite phenolic and Keviar/epoxy. Also metal honeycomb (titanium and aluminum faceplates over an aluminum honeycomb core) structures are investigated. Various structural shapes are investigated and the thickness of the structures vary from as few as 3 plies to as many as 80 plies. Special emphasis is placed on characterizing defects in attachment holes and bondlines, in addition to those resulting from impact damage and the inclusion of foreign matter. Image processing through statistical analysis and digital filtering is investigated to enhance the quality and quantify the NDE thermal images when necessary.

Study Methods to Standardize Thermography NDE

NASA Technical Reports Server (NTRS)

Walker, James L.; Workman, Gary L.

1998-01-01

The purpose of this work is to develop thermographic inspection methods and standards for use in evaluating structural composites and aerospace hardware. Qualification techniques and calibration methods are investigated to standardize the thermographic method for use in the field. Along with the inspections of test standards structural hardware, support hardware is designed and fabricated to aid in the thermographic process. Also, a standard operating procedure is developed for performing inspections with the Bales Thermal Image Processor (TIP). Inspections are performed on a broad range of structural composites. These materials include graphite/epoxies, graphite/cyanide-ester, graphite/silicon-carbide, graphite phenolic and Kevlar/epoxy. Also metal honeycomb (titanium and aluminum faceplates over an aluminum honeycomb core) structures are investigated. Various structural shapes are investigated and the thickness of the structures vary from as few as 3 plies to as many as 80 plies. Special emphasis is placed on characterizing defects in attachment holes and bondlines, in addition to those resulting from impact damage and the inclusion of foreign matter. Image processing through statistical analysis and digital filtering is investigated to enhance the quality and quantify the NDE thermal images when necessary.

Formation of silicon nanowire packed films from metallurgical-grade silicon powder using a two-step metal-assisted chemical etching method.

PubMed

Ouertani, Rachid; Hamdi, Abderrahmen; Amri, Chohdi; Khalifa, Marouan; Ezzaouia, Hatem

2014-01-01

In this work, we use a two-step metal-assisted chemical etching method to produce films of silicon nanowires shaped in micrograins from metallurgical-grade polycrystalline silicon powder. The first step is an electroless plating process where the powder was dipped for few minutes in an aqueous solution of silver nitrite and hydrofluoric acid to permit Ag plating of the Si micrograins. During the second step, corresponding to silicon dissolution, we add a small quantity of hydrogen peroxide to the plating solution and we leave the samples to be etched for three various duration (30, 60, and 90 min). We try elucidating the mechanisms leading to the formation of silver clusters and silicon nanowires obtained at the end of the silver plating step and the silver-assisted silicon dissolution step, respectively. Scanning electron microscopy (SEM) micrographs revealed that the processed Si micrograins were covered with densely packed films of self-organized silicon nanowires. Some of these nanowires stand vertically, and some others tilt to the silicon micrograin facets. The thickness of the nanowire films increases from 0.2 to 10 μm with increasing etching time. Based on SEM characterizations, laser scattering estimations, X-ray diffraction (XRD) patterns, and Raman spectroscopy, we present a correlative study dealing with the effect of the silver-assisted etching process on the morphological and structural properties of the processed silicon nanowire films.

Formation of silicon nanowire packed films from metallurgical-grade silicon powder using a two-step metal-assisted chemical etching method

PubMed Central

2014-01-01

In this work, we use a two-step metal-assisted chemical etching method to produce films of silicon nanowires shaped in micrograins from metallurgical-grade polycrystalline silicon powder. The first step is an electroless plating process where the powder was dipped for few minutes in an aqueous solution of silver nitrite and hydrofluoric acid to permit Ag plating of the Si micrograins. During the second step, corresponding to silicon dissolution, we add a small quantity of hydrogen peroxide to the plating solution and we leave the samples to be etched for three various duration (30, 60, and 90 min). We try elucidating the mechanisms leading to the formation of silver clusters and silicon nanowires obtained at the end of the silver plating step and the silver-assisted silicon dissolution step, respectively. Scanning electron microscopy (SEM) micrographs revealed that the processed Si micrograins were covered with densely packed films of self-organized silicon nanowires. Some of these nanowires stand vertically, and some others tilt to the silicon micrograin facets. The thickness of the nanowire films increases from 0.2 to 10 μm with increasing etching time. Based on SEM characterizations, laser scattering estimations, X-ray diffraction (XRD) patterns, and Raman spectroscopy, we present a correlative study dealing with the effect of the silver-assisted etching process on the morphological and structural properties of the processed silicon nanowire films. PMID:25349554

Surface Fluorination of Reactive Battery Anode Materials for Enhanced Stability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhao, Jie; Liao, Lei; Shi, Feifei

Significant increases in the energy density of batteries must be achieved by exploring new materials and cell configurations. Lithium metal and lithiated silicon are two promising high-capacity anode materials. Unfortunately, both of these anodes require a reliable passivating layer to survive the serious environmental corrosion during handling and cycling. Here we developed a surface fluorination process to form a homogeneous and dense LiF coating on reactive anode materials, with in situ generated fluorine gas, by using a fluoropolymer, CYTOP, as the precursor. The process is effectively a “reaction in the beaker”, avoiding direct handling of highly toxic fluorine gas. Formore » lithium metal, this LiF coating serves as a chemically stable and mechanically strong interphase, which minimizes the corrosion reaction with carbonate electrolytes and suppresses dendrite formation, enabling dendrite-free and stable cycling over 300 cycles with current densities up to 5 mA/cm 2. Lithiated silicon can serve as either a pre-lithiation additive for existing lithium-ion batteries or a replacement for lithium metal in Li–O 2 and Li–S batteries. However, lithiated silicon reacts vigorously with the standard slurry solvent N-methyl-2-pyrrolidinone (NMP), indicating it is not compatible with the real battery fabrication process. With the protection of crystalline and dense LiF coating, Li xSi can be processed in anhydrous NMP with a high capacity of 2504 mAh/g. With low solubility of LiF in water, this protection layer also allows Li xSi to be stable in humid air (~40% relative humidity). Furthermore, this facile surface fluorination process brings huge benefit to both the existing lithium-ion batteries and next-generation lithium metal batteries.« less

Surface Fluorination of Reactive Battery Anode Materials for Enhanced Stability

DOE PAGES

Zhao, Jie; Liao, Lei; Shi, Feifei; ...

2017-07-26

Significant increases in the energy density of batteries must be achieved by exploring new materials and cell configurations. Lithium metal and lithiated silicon are two promising high-capacity anode materials. Unfortunately, both of these anodes require a reliable passivating layer to survive the serious environmental corrosion during handling and cycling. Here we developed a surface fluorination process to form a homogeneous and dense LiF coating on reactive anode materials, with in situ generated fluorine gas, by using a fluoropolymer, CYTOP, as the precursor. The process is effectively a “reaction in the beaker”, avoiding direct handling of highly toxic fluorine gas. Formore » lithium metal, this LiF coating serves as a chemically stable and mechanically strong interphase, which minimizes the corrosion reaction with carbonate electrolytes and suppresses dendrite formation, enabling dendrite-free and stable cycling over 300 cycles with current densities up to 5 mA/cm 2. Lithiated silicon can serve as either a pre-lithiation additive for existing lithium-ion batteries or a replacement for lithium metal in Li–O 2 and Li–S batteries. However, lithiated silicon reacts vigorously with the standard slurry solvent N-methyl-2-pyrrolidinone (NMP), indicating it is not compatible with the real battery fabrication process. With the protection of crystalline and dense LiF coating, Li xSi can be processed in anhydrous NMP with a high capacity of 2504 mAh/g. With low solubility of LiF in water, this protection layer also allows Li xSi to be stable in humid air (~40% relative humidity). Furthermore, this facile surface fluorination process brings huge benefit to both the existing lithium-ion batteries and next-generation lithium metal batteries.« less

Method of fabricating porous silicon carbide (SiC)

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Process for purification of solids

NASA Technical Reports Server (NTRS)

Herzer, H.; Rath, H. J.; Schmidt, D.

1981-01-01

A process for purifying solids, especially silicon, by melting and subsequent resolidification, is described. Silicon used in solar cell manufacturing is processed more efficiently and cost effectively.

Silicon production process evaluations

NASA Technical Reports Server (NTRS)

1981-01-01

The chemical engineering analysis of the preliminary process design of a process for producing solar cell grade silicon from dichlorosilane is presented. A plant to produce 1,000 MT/yr of silicon is analyzed. Progress and status for the plant design are reported for the primary activities of base case conditions (60 percent), reaction chemistry (50 percent), process flow diagram (35 percent), energy balance (10 percent), property data (10 percent) and equipment design (5 percent).

Investigation of nickel-silicon metallization process

NASA Technical Reports Server (NTRS)

Macha, M.

1983-01-01

The metallization of silicon solar cells passivated with silicon nitride coating was investigated by using commercial Ni pastes #5517 from Thick Film Systems, #7028-5 from Cermalloy, experimental formulation # X-A by Sollos, Inc. and evaporated Ti-Ni film. Comparative and reference tests were done with the Dupont Ag paste #7095 and with a mixture of Ni paste #5517 with Ag paste #7095 in the respective ratio of 9 to 1 by weight. The evaluation criteria for the metallization was the mechanical bond strength of the contact, solderability, copper plating ability and electrical characteristics in terms of Voc, Isc values and shape of the V-I curve. The results revealed that the Dupont Ag paste #7095 mt all required criteria, while the quality of the cells metalized with the commercial Ni paste #5517 from Thick Film Systems, #7028-5 from Cermalloy as well as the experimental paste # X-A from Sollos, Inc. was below the acceptable standards. A significant improvement was obtained with the mixture of Ni paste #5517 from Thick Film Systems with 10% addition of Dupont paste # 7095.

Method for processing silicon solar cells

DOEpatents

Tsuo, Y.S.; Landry, M.D.; Pitts, J.R.

1997-05-06

The instant invention teaches a novel method for fabricating silicon solar cells utilizing concentrated solar radiation. The solar radiation is concentrated by use of a solar furnace which is used to form a front surface junction and back-surface field in one processing step. The present invention also provides a method of making multicrystalline silicon from amorphous silicon. The invention also teaches a method of texturing the surface of a wafer by forming a porous silicon layer on the surface of a silicon substrate and a method of gettering impurities. Also contemplated by the invention are methods of surface passivation, forming novel solar cell structures, and hydrogen passivation. 2 figs.

Method for processing silicon solar cells

DOEpatents

Tsuo, Y. Simon; Landry, Marc D.; Pitts, John R.

1997-01-01

The instant invention teaches a novel method for fabricating silicon solar cells utilizing concentrated solar radiation. The solar radiation is concentrated by use of a solar furnace which is used to form a front surface junction and back-surface field in one processing step. The present invention also provides a method of making multicrystallline silicon from amorphous silicon. The invention also teaches a method of texturing the surface of a wafer by forming a porous silicon layer on the surface of a silicon substrate and a method of gettering impurities. Also contemplated by the invention are methods of surface passivation, forming novel solar cell structures, and hydrogen passivation.

Silicon material development for terrestrial solar cells. Phase of exploration

NASA Astrophysics Data System (ADS)

Sirtl, E.

1983-03-01

A material project based on a multicrystalline silicon is reported. It consists of refining the metallurgical grade silicon via hydro and pyrometallurgical processes, preparation of square shaped ingots by (inert) gas protected or open hearth casting methods, and high speed slicing, using a multiple blade slurry saw. Second generation pilot equipment was constructed. Aluminothermic reduction of quartz sand into silicon and the foil casting process were tested. It is concluded that the production of silicon thru the gaseous phase depends upon the marketing of very cheap basic material (SG-Si 10 dollar/Kg) and that the purification of metallurgical grade silicon by refining is the most promising method.

Anisotropic Tribological Properties of Silicon Carbide

NASA Technical Reports Server (NTRS)

Miyoshi, K.; Buckley, D. H.

1980-01-01

The anisotropic friction, deformation and fracture behavior of single crystal silicon carbide surfaces were investigated in two categories. The categories were called adhesive and abrasive wear processes, respectively. In the adhesive wear process, the adhesion, friction and wear of silicon carbide were markedly dependent on crystallographic orientation. The force to reestablish the shearing fracture of adhesive bond at the interface between silicon carbide and metal was the lowest in the preferred orientation of silicon carbide slip system. The fracturing of silicon carbide occurred near the adhesive bond to metal and it was due to primary cleavages of both prismatic (10(-1)0) and basal (0001) planes.

Silicon production in a fluidized bed reactor

NASA Technical Reports Server (NTRS)

Rohatgi, N. K.

1986-01-01

Part of the development effort of the JPL in-house technology involved in the Flat-Plate Solar Array (FSA) Project was the investigation of a low-cost process to produce semiconductor-grade silicon for terrestrial photovoltaic cell applications. The process selected was based on pyrolysis of silane in a fluidized-bed reactor (FBR). Following initial investigations involving 1- and 2-in. diameter reactors, a 6-in. diameter, engineering-scale FBR was constructed to establish reactor performance, mechanism of silicon deposition, product morphology, and product purity. The overall mass balance for all experiments indicates that more than 90% of the total silicon fed into the reactor is deposited on silicon seed particles and the remaining 10% becomes elutriated fines. Silicon production rates were demonstrated of 1.5 kg/h at 30% silane concentration and 3.5 kg/h at 80% silane concentration. The mechanism of silicon deposition is described by a six-path process: heterogeneous deposition, homogeneous decomposition, coalescence, coagulation, scavenging, and heterogeneous growth on fines. The bulk of the growth silicon layer appears to be made up of small diameter particles. This product morphology lends support to the concept of the scavenging of homogeneously nucleated silicon.

Incubation behavior of silicon nanowire growth investigated by laser-assisted rapid heating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ryu, Sang-gil; Kim, Eunpa; Grigoropoulos, Costas P., E-mail: cgrigoro@berkeley.edu

2016-08-15

We investigate the early stage of silicon nanowire growth by the vapor-liquid-solid mechanism using laser-localized heating combined with ex-situ chemical mapping analysis by energy-filtered transmission electron microscopy. By achieving fast heating and cooling times, we can precisely determine the nucleation times for nanowire growth. We find that the silicon nanowire nucleation process occurs on a time scale of ∼10 ms, i.e., orders of magnitude faster than the times reported in investigations using furnace processes. The rate-limiting step for silicon nanowire growth at temperatures in the vicinity of the eutectic temperature is found to be the gas reaction and/or the silicon crystalmore » growth process, whereas at higher temperatures it is the rate of silicon diffusion through the molten catalyst that dictates the nucleation kinetics.« less

Conformal chemically resistant coatings for microflow devices

DOEpatents

Folta, James A.; Zdeblick, Mark

2003-05-13

A process for coating the inside surfaces of silicon microflow devices, such as electrophoresis microchannels, with a low-stress, conformal (uniform) silicon nitride film which has the ability to uniformly coat deeply-recessed cavities with, for example, aspect ratios of up to 40:1 or higher. The silicon nitride coating allows extended exposure to caustic solutions. The coating enables a microflow device fabricated in silicon to be resistant to all classes of chemicals: acids, bases, and solvents. The process involves low-pressure (vacuum) chemical vapor deposition. The ultra-low-stress silicon nitride deposition process allows 1-2 .mu.m thick films without cracks, and so enables extended chemical protection of a silicon microflow device against caustics for up to 1 year. Tests have demonstrated the resistance of the films to caustic solutions at both ambient and elevated temperatures to 65.degree. C.

Silicon Materials Task of the Low Cost Solar Array Project, Phase 3. Effect of Impurities and Processing on Silicon Solar Cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Davis, J. R.; Blais, P. D.; Rohatgi, A.; Campbell, R. B.; Rai-Choudhury, P.; Stapleton, R. E.; Mollenkopf, H. C.; Mccormick, J. R.

1979-01-01

The effects of impurities, various thermochemical processes, and any impurity process interactions on the performance of terrestrial silicon solar cells are defined. Determinations of the segregation coefficients of tungsten, tantalum, and cobalt for the Czochralski pulling of silicon single crystals are reported. Sensitive neutron activation analysis was used to determine the metal impurity content of the silicon while atomic absorption was used to measure the metal content of the residual liquid from which the doped crystals were grown. Gettering of Ti doped silicon wafers improved cell performance by one to two percent for the highest temperatures and longest times. The HCl is more effective than POCl3 treatments for deactivating Ti but POCl3 and HCl produced essentially identical results for Mo or Fe.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.

2016-03-15

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materialsmore » on the basis of porous silicon and nanostructures with a high aspect ratio.« less

Heat exchanger-ingot casting/slicing process, phase 1: Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Schmid, F.; Khattak, C. P.

1977-01-01

A controlled growth, heat-flow and cool-down process is described that yielded silicon with a high degree of single crystallinity. Even when the seed melted out, very large grains formed. Solar cell samples made from cast material yielded conversion efficiency of over 9%. Representative characterizations of grown silicon demonstrated a dislocation density of less than 100/sq cm and a minority carrier diffusion length of 31 micron. The source of silicon carbide in silicon ingots was identified to be from graphite retainers in contact with silica crucibles. Higher growth rates were achieved with the use of a graphite plug at the bottom of the silica crucible.

Towards nanometer-spaced silicon contacts to proteins

NASA Astrophysics Data System (ADS)

Schukfeh, Muhammed I.; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Towards nanometer-spaced silicon contacts to proteins.

PubMed

Schukfeh, Muhammed I; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-18

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p(+) silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices' electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes' edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions' conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein's denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Use of Patient and Observer Scar Assessment Scale for evaluation of facial scars treated with self-drying silicone gel.

PubMed

Bianchi, Francesca A; Roccia, Fabio; Fiorini, Paola; Berrone, Sid

2010-05-01

In this prospective study, we used the Patient and Observer Scar Assessment Scale (POSAS) to evaluate the outcome of the healing process of posttraumatic and surgical facial scars that were treated with self-drying silicone gel, by both the patient and the observer. In our division, the application of base cream and massage represents the standard management of facial scars after suture removal. In the current study, 15 patients (7 men and 8 women) with facial scars were treated with self-drying silicone gel that was applied without massage, and 15 patients (8 men and 7 women) were treated with base cream and massage. Both groups underwent a clinical evaluation of facial scars by POSAS at the time of suture removal (T0) and after 2 months of treatment (T1). The patient rated scar pain, itch, color, stiffness, thickness, and surface (Patient Scale), and the observer rated scar vascularity, pigmentation, thickness, relief, pliability, and surface area (Observer Scale [OS]). The Patient Scale reported the greatest improvement in the items color, stiffness, and thickness. Itch was the only item that worsened in the group self-drying silicone gel. The OS primarily reported an improvement in the items vascularization, pigmentation, and pliability. The only item in the OS that underwent no change from T0 to T1 was surface area. The POSAS revealed satisfactory healing of posttraumatic and surgical facial scars that were treated with self-drying silicone gel.

Process for producing high purity silicon nitride by the direct reaction between elemental silicon and nitrogen-hydrogen liquid reactants

DOEpatents

Pugar, Eloise A.; Morgan, Peter E. D.

1990-01-01

A process is disclosed for producing, at a low temperature, a high purity reaction product consisting essentially of silicon, nitrogen, and hydrogen which can then be heated to produce a high purity alpha silicon nitride. The process comprises: reacting together a particulate elemental high purity silicon with a high purity nitrogen-hydrogen reactant in its liquid state (such as ammonia or hydrazine) having the formula: N.sub.n H.sub.(n+m) wherein: n=1-4 and m=2 when the nitrogen-hydrogen reactant is straight chain, and 0 when the nitrogen-hydrogen reactant is cyclic. High purity silicon nitride can be formed from this intermediate product by heating the intermediate product at a temperature of from about 1200.degree.-1700.degree. C. for a period from about 15 minutes up to about 2 hours to form a high purity alpha silicon nitride product. The discovery of the existence of a soluble Si-N-H intermediate enables chemical pathways to be explored previously unavailable in conventional solid state approaches to silicon-nitrogen ceramics.

High-Performance Ultrathin Organic-Inorganic Hybrid Silicon Solar Cells via Solution-Processed Interface Modification.

PubMed

Zhang, Jie; Zhang, Yinan; Song, Tao; Shen, Xinlei; Yu, Xuegong; Lee, Shuit-Tong; Sun, Baoquan; Jia, Baohua

2017-07-05

Organic-inorganic hybrid solar cells based on n-type crystalline silicon and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) exhibited promising efficiency along with a low-cost fabrication process. In this work, ultrathin flexible silicon substrates, with a thickness as low as tens of micrometers, were employed to fabricate hybrid solar cells to reduce the use of silicon materials. To improve the light-trapping ability, nanostructures were built on the thin silicon substrates by a metal-assisted chemical etching method (MACE). However, nanostructured silicon resulted in a large amount of surface-defect states, causing detrimental charge recombination. Here, the surface was smoothed by solution-processed chemical treatment to reduce the surface/volume ratio of nanostructured silicon. Surface-charge recombination was dramatically suppressed after surface modification with a chemical, associated with improved minority charge-carrier lifetime. As a result, a power conversion efficiency of 9.1% was achieved in the flexible hybrid silicon solar cells, with a substrate thickness as low as ∼14 μm, indicating that interface engineering was essential to improve the hybrid junction quality and photovoltaic characteristics of the hybrid devices.

Process for producing high purity silicon nitride by the direct reaction between elemental silicon and nitrogen-hydrogen liquid reactants

DOEpatents

Pugar, E.A.; Morgan, P.E.D.

1987-09-15

A process is disclosed for producing, at a low temperature, a high purity reaction product consisting essentially of silicon, nitrogen, and hydrogen which can then be heated to produce a high purity alpha silicon nitride. The process comprises: reacting together a particulate elemental high purity silicon with a high purity nitrogen-hydrogen reactant in its liquid state (such as ammonia or hydrazine) having the formula: N/sub n/H/sub (n+m)/ wherein: n = 1--4 and m = 2 when the nitrogen-hydrogen reactant is straight chain, and 0 when the nitrogen-hydrogen reactant is cyclic. High purity silicon nitride can be formed from this intermediate product by heating the intermediate product at a temperature of from about 1200--1700/degree/C for a period from about 15 minutes up to about 2 hours to form a high purity alpha silicon nitride product. The discovery of the existence of a soluble Si/endash/N/endash/H intermediate enables chemical pathways to be explored previously unavailable in conventional solid-state approaches to silicon-nitrogen ceramics

Silicon crystal growth in vacuum

NASA Technical Reports Server (NTRS)

Khattak, C. P.; Schmid, F.

1982-01-01

The most developed process for silicon crystal growth is the Czochralski (CZ) method which was in production for over two decades. In an effort to reduce cost of single crystal silicon for photovoltaic applications, a directional solidification technique, Heat Exchanger Method (HEM), was adapted. Materials used in HEM and CZ furnaces are quite similar (heaters, crucibles, insulation, etc.). To eliminate the cost of high purity argon, it was intended to use vacuum operation in HEM. Two of the major problems encountered in vacuum processing of silicon are crucible decomposition and silicon carbide formation in the melt.

Process and apparatus for obtaining silicon from fluosilicic acid

DOEpatents

Sanjurjo, Angel

1988-06-28

Process and apparatus for producing low cost, high purity solar grade silicon ingots in single crystal or quasi single crystal ingot form in a substantially continuous operation in a two stage reactor starting with sodium fluosilicate and a metal more electropositive than silicon (preferably sodium) in separate compartments having easy vapor transport therebetween and thermally decomposing the sodium fluosilicate to cause formation of substantially pure silicon and a metal fluoride which may be continuously separated in the melt and silicon may be directly and continuously cast from the melt.

Studies on the reactive melt infiltration of silicon and silicon-molybdenum alloys in porous carbon

NASA Technical Reports Server (NTRS)

Singh, M.; Behrendt, D. R.

1992-01-01

Investigations on the reactive melt infiltration of silicon and silicon-1.7 and 3.2 at percent molybdenum alloys into porous carbon preforms have been carried out by process modeling, differential thermal analysis (DTA) and melt infiltration experiments. These results indicate that the initial pore volume fraction of the porous carbon preform is a critical parameter in determining the final composition of the raction-formed silicon carbide and other residual phases. The pore size of the carbon preform is very detrimental to the exotherm temperatures due to liquid silicon-carbon reactions encountered during the reactive melt infiltration process. A possible mechanism for the liquid silicon-porous (glassy) carbon reaction has been proposed. The composition and microstructure of the reaction-formed silicon carbide has been discussed in terms of carbon preform microstructures, infiltration materials, and temperatures.

HOLE-BLOCKING LAYERS FOR SILICON/ORGANIC HETEROJUNCTIONS: A NEW CLASS OF HIGH-EFFICIENCY LOW-COST PV

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sturm, James

This project is the first investigation of the use of thin titanium dioxide layers on silicon as a hole-blocking / electron-transparent selective contact to silicon. The work was motivated by the goal of a high-efficiency low-cost silicon-based solar cells that could be processed entirely at low temperature (300 Degree Celsius) or less, without requiring plasma-processing.

Buried oxide layer in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2001-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Formation mechanism of a silicon carbide coating for a reinforced carbon-carbon composite

NASA Technical Reports Server (NTRS)

Rogers, D. C.; Shuford, D. M.; Mueller, J. I.

1975-01-01

Results are presented for a study to determine the mechanisms involved in a high-temperature pack cementation process which provides a silicon carbide coating on a carbon-carbon composite. The process and materials used are physically and chemically analyzed. Possible reactions are evaluated using the results of these analytical data. The coating is believed to develop in two stages. The first is a liquid controlled phase process in which silicon carbide is formed due to reactions between molten silicon metal and the carbon. The second stage is a vapor transport controlled reaction in which silicon vapors react with the carbon. There is very little volume change associated with the coating process. The original thickness changes by less than 0.7%. This indicates that the coating process is one of reactive penetration. The coating thickness can be increased or decreased by varying the furnace cycle process time and/or temperature to provide a wide range of coating thicknesses.

Mixed Matrix Silicone and Fluorosilicone/Zeolite 4A Membranes for Ethanol Dehydration by Pervaporation

EPA Science Inventory

The ability of homogeneous and mixed matrix membranes prepared using standard silicone rubber, poly(dimethylsiloxane) (PDMS), and fluorosilicone rubber, poly(trifluoropropylmethylsiloxane) (PTFPMS), to dehydrate ethanol by pervaporation was evaluated. Although PDMS is generally c...

International Workshop on Light Emission and Electronic Properties of Nanoscale Silicon

DTIC Science & Technology

1994-04-01

matrix elements, quantum confinement, surface effects ? CHARLOTFE STANDARD R. Tsu Comparison of Luminescence Efficiency ROLE OF NANOSCALE Si-DEVICES...confinement effects in microcrystalline silicon [2,3] may lead to revolutionary advances in speed and dramatically reduced energy consumption of silicon...Formation: A Quantum Wire Effect ," Avpl. Phys. Lett., 58, 856 (1991). 5. R. Tsu, H. Shen, and M. Dutta, "Correlation of Raman and Photoluminescence

Silicon-on-Insulator Pin Diodes.

DTIC Science & Technology

1987-12-01

Thin (0.5 Micron) Silicon-on-Oxidized Silicon Fig. 2.8 SEM Photographs of CVD Silicon Dioxide on Aluminum 28 After 1500 0 C Anneal in Oxygen...silicon nitride over the silicon dioxide encapsu- -9- lation layer and by depositing the silicon dioxide with a plasma CVD process which uses N20 as...relief via thermal expansion matching varies lin- -27- A B Figure 2.8: SEM Photographs of CVD Silicon Dioxide on Aluminum after 15000 C Anneal in Oxygen

Silicon-on-ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Whitehead, A. B.; Zook, J. D.; Grung, B. L.; Heaps, J. D.; Schmit, F.; Schuldt, S. B.; Chapman, P. W.

1981-01-01

The technical feasibility of producing solar cell quality sheet silicon to meet the DOE 1986 cost goal of 70 cents/watt was investigated. The silicon on ceramic approach is to coat a low cost ceramic substrate with large grain polycrystalline silicon by unidirectional solidification of molten silicon. Results and accomplishments are summarized.

In situ spectroscopic ellipsometry study of low-temperature epitaxial silicon growth

NASA Astrophysics Data System (ADS)

Halagačka, L.; Foldyna, M.; Leal, R.; Roca i Cabarrocas, P.

2018-07-01

Low-temperature growth of doped epitaxial silicon layers is a promising way to reduce the cost of p-n junction formation in c-Si solar cells. In this work, we study process of highly doped epitaxial silicon layer growth using in situ spectroscopic ellipsometry. The film was deposited by plasma-enhanced chemical vapor deposition (PECVD) on a crystalline silicon substrate at a low substrate temperature of 200 °C. In the deposition process, SiF4 was used as a precursor, B2H6 as doping gas, and a hydrogen/argon mixture as carrier gas. A spectroscopic ellipsometer with a wide spectral range was used for in situ spectroscopic measurements. Since the temperature during process is 200 °C, the optical functions of silicon differ from these at room temperature and have to be adjusted. Thickness of the epitaxial silicon layer was fitted on in situ ellipsometric data. As a result we were able to determine the dynamics of epitaxial layer growth, namely initial layer formation time and epitaxial growth rate. This study opens new perspectives in understanding and monitoring the epitaxial silicon deposition processes as the model fitting can be applied directly during the growth.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Process for purification of silicon

NASA Technical Reports Server (NTRS)

Rath, H. J.; Sirtl, E.; Pfeiffer, W.

1981-01-01

The purification of metallurgically pure silicon having a silicon content of more than 95% by weight is accomplished by leaching with an acidic solution which substantially does not attack silicon. A mechanical treatment leading to continuous particle size reduction of the granulated silicon to be purified is combined with the chemical purification step.

Thermodynamics of a phase transition of silicon nanoparticles at the annealing and carbonization of porous silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nagornov, Yu. S., E-mail: Nagornov.Yuri@gmail.com

2015-12-15

The formation of SiC nanocrystals of the cubic modification in the process of high-temperature carbonization of porous silicon has been analyzed. A thermodynamic model has been proposed to describe the experimental data obtained by atomic-force microscopy, Raman scattering, spectral analysis, Auger spectroscopy, and X-ray diffraction spectroscopy. It has been shown that the surface energy of silicon nanoparticles and quantum filaments is released in the process of annealing and carbonization. The Monte Carlo simulation has shown that the released energy makes it possible to overcome the nucleation barrier and to form SiC nanocrystals. The processes of laser annealing and electron irradiationmore » of carbonized porous silicon have been analyzed.« less

Steric stabilization of nonaqueous silicon slips. I - Control of particle agglomeration and packing. II - Pressure casting of powder compacts

NASA Technical Reports Server (NTRS)

Kerkar, Awdhoot V.; Henderson, Robert J. M.; Feke, Donald L.

1990-01-01

The application of steric stabilization to control particle agglomeration and packing of silicon powder in benzene and trichloroethylene is reported. The results provide useful guidelines for controlling unfavorable particle-particle interactions during nonaqueous processing of silicon-based ceramic materials. The application of steric stabilization to the control and improvement of green processing of nonaqueous silicon slips in pressure consolidation is also demonstrated.

The automated array assembly task of the low-cost silicon solar array project, phase 2

NASA Technical Reports Server (NTRS)

Coleman, M. G.; Pryor, R. A.; Sparks, T. G.; Legge, R.; Saltzman, D. L.

1980-01-01

Several specific processing steps as part of a total process sequence for manufacturing silicon solar cells were studied. Ion implantation was identified as the preferred process step for impurity doping. Unanalyzed beam ion implantation was shown to have major cost advantages over analyzed beam implantation. Further, high quality cells were fabricated using a high current unanalyzed beam. Mechanically masked plasma patterning of silicon nitride was shown to be capable of forming fine lines on silicon surfaces with spacings between mask and substrate as great as 250 micrometers. Extensive work was performed on advances in plated metallization. The need for the thick electroless palladium layer was eliminated. Further, copper was successfully utilized as a conductor layer utilizing nickel as a barrier to copper diffusion into the silicon. Plasma etching of silicon for texturing and saw damage removal was shown technically feasible but not cost effective compared to wet chemical etching techniques.

Silicon materials task of the Low Cost Solar Array Project: Effect of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Davis, J. R.; Rohatgi, A.; Hanes, M. H.; Rai-Choudhury, P.; Mollenkopf, H. C.

1982-01-01

The effects of impurities and processing on the characteristics of silicon and terrestrial silicon solar cells were defined in order to develop cost benefit relationships for the use of cheaper, less pure solar grades of silicon. The amount of concentrations of commonly encountered impurities that can be tolerated in typical p or n base solar cells was established, then a preliminary analytical model from which the cell performance could be projected depending on the kinds and amounts of contaminants in the silicon base material was developed. The impurity data base was expanded to include construction materials, and the impurity performace model was refined to account for additional effects such as base resistivity, grain boundary interactions, thermal processing, synergic behavior, and nonuniform impurity distributions. A preliminary assessment of long term (aging) behavior of impurities was also undertaken.

Cleaning up Silicon

NASA Technical Reports Server (NTRS)

2000-01-01

A development program that started in 1975 between Union Carbide and JPL, led to Advanced Silicon Materials LLC's, formerly ASiMI, commercial process for producing silane in viable quantities. The process was expanded to include the production of high-purity polysilicon for electronic devices. The technology came out of JPL's Low Cost Silicon Array Project.

Silicon on ceramic process. Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Zook, J. D.; Heaps, J. D.; Maciolek, R. B.; Koepke, B. G.; Butter, C. D.; Schuldt, S. B.

1977-01-01

The technical and economic feasibility of producing solar-cell-quality sheet silicon was investigated. The sheets were made by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Significant progress was made in all areas of the program.

Method for silicon carbide production by reacting silica with hydrocarbon gas

DOEpatents

Glatzmaier, G.C.

1994-06-28

A method is described for producing silicon carbide particles using a silicon source material and a hydrocarbon. The method is efficient and is characterized by high yield. Finely divided silicon source material is contacted with hydrocarbon at a temperature of 400 C to 1000 C where the hydrocarbon pyrolyzes and coats the particles with carbon. The particles are then heated to 1100 C to 1600 C to cause a reaction between the ingredients to form silicon carbide of very small particle size. No grinding of silicon carbide is required to obtain small particles. The method may be carried out as a batch process or as a continuous process. 5 figures.

Method for silicon carbide production by reacting silica with hydrocarbon gas

DOEpatents

Glatzmaier, Gregory C.

1994-01-01

A method is described for producing silicon carbide particles using a silicon source material and a hydrocarbon. The method is efficient and is characterized by high yield. Finely divided silicon source material is contacted with hydrocarbon at a temperature of 400.degree. C. to 1000.degree. C. where the hydrocarbon pyrolyzes and coats the particles with carbon. The particles are then heated to 1100.degree. C. to 1600.degree. C. to cause a reaction between the ingredients to form silicon carbide of very small particle size. No grinding of silicon carbide is required to obtain small particles. The method may be carried out as a batch process or as a continuous process.

Method of forming buried oxide layers in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2000-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

3D Integration for Wireless Multimedia

NASA Astrophysics Data System (ADS)

Kimmich, Georg

The convergence of mobile phone, internet, mapping, gaming and office automation tools with high quality video and still imaging capture capability is becoming a strong market trend for portable devices. High-density video encode and decode, 3D graphics for gaming, increased application-software complexity and ultra-high-bandwidth 4G modem technologies are driving the CPU performance and memory bandwidth requirements close to the PC segment. These portable multimedia devices are battery operated, which requires the deployment of new low-power-optimized silicon process technologies and ultra-low-power design techniques at system, architecture and device level. Mobile devices also need to comply with stringent silicon-area and package-volume constraints. As for all consumer devices, low production cost and fast time-to-volume production is key for success. This chapter shows how 3D architectures can bring a possible breakthrough to meet the conflicting power, performance and area constraints. Multiple 3D die-stacking partitioning strategies are described and analyzed on their potential to improve the overall system power, performance and cost for specific application scenarios. Requirements and maturity of the basic process-technology bricks including through-silicon via (TSV) and die-to-die attachment techniques are reviewed. Finally, we highlight new challenges which will arise with 3D stacking and an outlook on how they may be addressed: Higher power density will require thermal design considerations, new EDA tools will need to be developed to cope with the integration of heterogeneous technologies and to guarantee signal and power integrity across the die stack. The silicon/wafer test strategies have to be adapted to handle high-density IO arrays, ultra-thin wafers and provide built-in self-test of attached memories. New standards and business models have to be developed to allow cost-efficient assembly and testing of devices from different silicon and technology providers.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Decontamination of Surfaces Exposed to Carbonbased Nanotubes and Nanomaterials

NASA Astrophysics Data System (ADS)

Karimi, Zahra

Contamination of surfaces by nanomaterials can happen due to accidental spillage and release or gradual accumulation during processing or handling. Considering the increasingly wide use of nanomaterials in industry and research labs and also taking into account the diversity of physical and chemical properties of different nanomaterials (such as solubility, aggregation/agglomeration, and surface reactivity), there is a pressing need to define reliable nanomaterial-specific decontamination guidelines. In this project, we propose and investigate a potential method for surface decontamination of carbon-based nanomaterials using solvent cleaning and wipes. The results show that the surfactant-assisted removal efficiencies of multi-walled carbon nanotubes, single walled carbon nantubes and single walled carbon nano-horns from silicon wafers through wiping is greater than 95%, 90% and 78%, respectively. The need for further studies to understand the mechanisms of nanomaterial removal from surfaces and development of standard techniques for surface decontamination of nanomaterials is highlighted. Another phase of experiments were performed to examine the efficiency of surfactants to remove multi-walled carbon nanotubes (MWCNTs) from silicon substrates with nano and microscaled features. In the first set of experiments, nanoscale features were induced on silicon wafers using SF6 and O2 plasma. Atomic force microscopy (AFM) was used to observe the surface topology and roughness. In the second set, well-defined microscale topological features were induced on silicon wafers using photo lithography and plasma etching. The etching time was varied to create semi-ellipsoidal pits with average diameter and height of ~ 7-9 microm, and ~ 1-3 microm, respectively. MWCNTs in the form of liquid solution were deposited on the surface of silicon wafers using the spin coating process. For the cleaning process, the contaminated surfaces were first sprayed with different types of surfactant or water. Then, the MWCNTs were wiped off using a simple wiping mechanism. The areal density of the MWCNTs was quantified prior to and after the removal using scanning electron microscopy (SEM) and post-image processing. For a surface featured with nanoscale asperities, the removal efficiency was measured to be in the range 83-99% based on substrate type and surface roughness. No evident relationship was observed between the etching time and the removal efficiency. For microscale features, increase of the etching time significantly decreases the removal efficiency.

Process for the production of ultrahigh purity silane with recycle from separation columns

NASA Technical Reports Server (NTRS)

Coleman, Larry M. (Inventor)

1982-01-01

Tri- and dichlorosilanes formed by hydrogenation in the course of the reaction of metallurgical silicon, hydrogen and recycle silicon tetrachloride are employed as feed into a separation column arrangement of sequential separation columns and redistribution reactors which processes the feed into ultrahigh purity silane and recycle silicon tetrachloride. A slip stream is removed from the bottom of two sequential columns and added to the recycle silicon tetrachloride process stream causing impurities in the slip streams to be subjected to reactions in the hydrogenation step whereby waste materials can be formed and readily separated.

Process for the production of ultrahigh purity silane with recycle from separation columns

DOEpatents

Coleman, Larry M.

1982-07-20

Tri- and dichlorosilanes formed by hydrogenation in the course of the reaction of metallurgical silicon, hydrogen and recycle silicon tetrachloride are employed as feed into a separation column arrangement of sequential separation columns and redistribution reactors which processes the feed into ultrahigh purity silane and recycle silicon tetrachloride. A slip stream is removed from the bottom of two sequential columns and added to the recycle silicon tetrachloride process stream causing impurities in the slip streams to be subjected to reactions in the hydrogenation step whereby waste materials can be formed and readily separated.

Method of fabricating silicon carbide coatings on graphite surfaces

DOEpatents

Varacalle, D.J. Jr.; Herman, H.; Burchell, T.D.

1994-07-26

The vacuum plasma spray process produces well-bonded, dense, stress-free coatings for a variety of materials on a wide range of substrates. The process is used in many industries to provide for the excellent wear, corrosion resistance, and high temperature behavior of the fabricated coatings. In this application, silicon metal is deposited on graphite. This invention discloses the optimum processing parameters for as-sprayed coating qualities. The method also discloses the effect of thermal cycling on silicon samples in an inert helium atmosphere at about 1,600 C which transforms the coating to silicon carbide. 3 figs.

Method of fabricating silicon carbide coatings on graphite surfaces

DOEpatents

Varacalle, Jr., Dominic J.; Herman, Herbert; Burchell, Timothy D.

1994-01-01

The vacuum plasma spray process produces well-bonded, dense, stress-free coatings for a variety of materials on a wide range of substrates. The process is used in many industries to provide for the excellent wear, corrosion resistance, and high temperature behavior of the fabricated coatings. In this application, silicon metal is deposited on graphite. This invention discloses the optimum processing parameters for as-sprayed coating qualities. The method also discloses the effect of thermal cycling on silicon samples in an inert helium atmosphere at about 1600.degree.C. which transforms the coating to silicon carbide.

Method for Molding Structural Parts Utilizing Modified Silicone Rubber

NASA Technical Reports Server (NTRS)

Weiser, Erik S. (Inventor); Baucom, Robert M. (Inventor); Snoha, John J. (Inventor)

1998-01-01

This invention improves upon a method for molding structural parts from preform material. Preform material to be used for the part is provided. A silicone rubber composition containing entrained air voids is prepared. The silicone rubber and preform material assembly is situated within a rigid mold cavity used to shape the preform material to die desired shape. The entire assembly is heated in a standard heating device so that the thermal expansion of the silicone rubber exerts the pressure necessary to force the preform material into contact with the mold container. The introduction of discrete air voids into the silicone rubber allows for accurately controlled pressure application on the preform material at the cure temperature.

Temperature Effects on the Magnetic Properties of Silicon-Steel Sheets Using Standardized Toroidal Frame

PubMed Central

Wu, Cheng-Ju; Lin, Shih-Yu; Chou, Shang-Chin; Tsai, Chia-Yun; Yen, Jia-Yush

2014-01-01

This study designed a detachable and standardized toroidal test frame to measure the electromagnetic characteristic of toroidal laminated silicon steel specimens. The purpose of the design was to provide the measurements with standardized and controlled environment. The device also can withstand high temperatures (25–300°C) for short time period to allow high temperature tests. The accompanying driving circuit facilitates testing for high frequency (50–5,000 Hz) and high magnetic flux (0.2–1.8 T) conditions and produces both sinusoidal and nonsinusoidal test waveforms. The thickness of the stacked laminated silicon-steel sheets must be 30~31 mm, with an internal diameter of 72 mm and an outer diameter of 90 mm. With the standardized setup, it is possible to carry out tests for toroidal specimen in high temperature and high flux operation. The test results show that there is a tendency of increased iron loss under high temperature operation. The test results with various driving waveforms also provide references to the required consideration in engineering designs. PMID:25525629

Temperature effects on the magnetic properties of silicon-steel sheets using standardized toroidal frame.

PubMed

Wu, Cheng-Ju; Lin, Shih-Yu; Chou, Shang-Chin; Tsai, Chia-Yun; Yen, Jia-Yush

2014-01-01

This study designed a detachable and standardized toroidal test frame to measure the electromagnetic characteristic of toroidal laminated silicon steel specimens. The purpose of the design was to provide the measurements with standardized and controlled environment. The device also can withstand high temperatures (25-300°C) for short time period to allow high temperature tests. The accompanying driving circuit facilitates testing for high frequency (50-5,000 Hz) and high magnetic flux (0.2-1.8 T) conditions and produces both sinusoidal and nonsinusoidal test waveforms. The thickness of the stacked laminated silicon-steel sheets must be 30~31 mm, with an internal diameter of 72 mm and an outer diameter of 90 mm. With the standardized setup, it is possible to carry out tests for toroidal specimen in high temperature and high flux operation. The test results show that there is a tendency of increased iron loss under high temperature operation. The test results with various driving waveforms also provide references to the required consideration in engineering designs.

Production of electronic grade lunar silicon by disproportionation of silicon difluoride

NASA Technical Reports Server (NTRS)

Agosto, William N.

1993-01-01

Waldron has proposed to extract lunar silicon by sodium reduction of sodium fluorosilicate derived from reacting sodium fluoride with lunar silicon tetrafluoride. Silicon tetrafluoride is obtained by the action of hydrofluoric acid on lunar silicates. While these reactions are well understood, the resulting lunar silicon is not likely to meet electronic specifications of 5 nines purity. Dale and Margrave have shown that silicon difluoride can be obtained by the action of silicon tetrafluoride on elemental silicon at elevated temperatures (1100-1200 C) and low pressures (1-2 torr). The resulting silicon difluoride will then spontaneously disproportionate into hyperpure silicon and silicon tetrafluoride in vacuum at approximately 400 C. On its own merits, silicon difluoride polymerizes into a tough waxy solid in the temperature range from liquid nitrogen to about 100 C. It is the silicon analog of teflon. Silicon difluoride ignites in moist air but is stable under lunar surface conditions and may prove to be a valuable industrial material that is largely lunar derived for lunar surface applications. The most effective driver for lunar industrialization may be the prospects for industrial space solar power systems in orbit or on the moon that are built with lunar materials. Such systems would require large quantities of electronic grade silicon or compound semiconductors for photovoltaics and electronic controls. Since silicon is the most abundant semimetal in the silicate portion of any solar system rock (approximately 20 wt percent), lunar silicon production is bound to be an important process in such a solar power project. The lunar silicon extraction process is discussed.

Water-assisted pulsed Er:YAG laser interaction with silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Jaehun; Ki, Hyungson, E-mail: hski@unist.ac.kr

2015-07-07

Silicon is virtually transparent to the Er:YAG laser with a wavelength of 2.94 μm. In this study, we report that moderately doped silicon (1–10 Ω cm) can be processed by a pulsed Er:YAG laser with a pulse duration of 350 μs and a peak laser intensity of 1.7 × 10{sup 5} W/cm{sup 2} by applying a thin water layer on top of silicon as a light absorbing medium. In this way, water is heated first by strongly absorbing the laser energy and then heats up the silicon wafer indirectly. As the silicon temperature rises, the free carrier concentration and therefore the absorption coefficient of silicon willmore » increase significantly, which may enable the silicon to get directly processed by the Er:YAG laser when the water is vaporized completely. We also believe that the change in surface morphology after melting could contribute to the increase in the laser beam absorptance. It was observed that 525 nm-thick p-type wafer specimens were fully penetrated after 15 laser pulses were irradiated. Bright yellow flames were observed during the process, which indicates that the silicon surface reached the melting point.« less

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

New dynamic silicon photonic components enabled by MEMS technology

NASA Astrophysics Data System (ADS)

Errando-Herranz, Carlos; Edinger, Pierre; Colangelo, Marco; Björk, Joel; Ahmed, Samy; Stemme, Göran; Niklaus, Frank; Gylfason, Kristinn B.

2018-02-01

Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

Economics of polysilicon process: A view from Japan

NASA Technical Reports Server (NTRS)

Shimizu, Y.

1986-01-01

The production process of solar grade silicon (SOG-Si) through trichlorosilane (TCS) was researched in a program sponsored by New Energy Development Organization (NEDO). The NEDO process consists of the following two steps: TCS production from by-product silicon tetrachloride (STC) and SOG-Si formation from TCS using a fluidized bed reactor. Based on the data obtained during the research program, the manufacturing cost of the NEDO process and other polysilicon manufacturing processes were compared. The manufacturing cost was calculated on the basis of 1000 tons/year production. The cost estimate showed that the cost of producing silicon by all of the new processes is less than the cost by the conventional Siemens process. Using a new process, the cost of producing semiconductor grade silicon was found to be virtually the same with any to the TCS, diclorosilane, and monosilane processes when by-products were recycled. The SOG-Si manufacturing processes using the fluidized bed reactor, which needs further development, shows a greater probablility of cost reduction than the filament processes.

Development of silicon grisms and immersion gratings for high-resolution infrared spectroscopy

NASA Astrophysics Data System (ADS)

Ge, Jian; McDavitt, Daniel L.; Bernecker, John L.; Miller, Shane; Ciarlo, Dino R.; Kuzmenko, Paul J.

2002-01-01

We report new results on silicon grism and immersion grating development using photolithography and anisotropic chemical etching techniques, which include process recipe finding, prototype grism fabrication, lab performance evaluation and initial scientific observations. The very high refractive index of silicon (n=3.4) enables much higher dispersion power for silicon-based gratings than conventional gratings, e.g. a silicon immersion grating can offer a factor of 3.4 times the dispersion of a conventional immersion grating. Good transmission in the infrared (IR) allows silicon-based gratings to operate in the broad IR wavelength regions (~1- 10 micrometers and far-IR), which make them attractive for both ground and space-based spectroscopic observations. Coarser gratings can be fabricated with these new techniques rather than conventional techniques, allowing observations at very high dispersion orders for larger simultaneous wavelength coverage. We have found new etching techniques for fabricating high quality silicon grisms with low wavefront distortion, low scattered light and high efficiency. Particularly, a new etching process using tetramethyl ammonium hydroxide (TMAH) is significantly simplifying the fabrication process on large, thick silicon substrates, while providing comparable grating quality to our traditional potassium hydroxide (KOH) process. This technique is being used for fabricating inch size silicon grisms for several IR instruments and is planned to be used for fabricating ~ 4 inch size silicon immersion gratings later. We have obtained complete K band spectra of a total of 6 T Tauri and Ae/Be stars and their close companions at a spectral resolution of R ~ 5000 using a silicon echelle grism with a 5 mm pupil diameter at the Lick 3m telescope. These results represent the first scientific observations conducted by the high-resolution silicon grisms, and demonstrate the extremely high dispersing power of silicon- based gratings. The future of silicon-based grating applications in ground and space-based IR instruments is promising. Silicon immersion gratings will make very high-resolution spectroscopy (R>100,000) feasible with compact instruments for implementation on large telescopes. Silicon grisms will offer an efficient way to implement low-cost medium to high resolution IR spectroscopy (R~ 1000-50000) through the conversion of existing cameras into spectrometers by locating a grism in the instrument's pupil location.

Evaluation of selected chemical processes for production of low-cost silicon

NASA Technical Reports Server (NTRS)

Blocher, J. M., Jr.; Browning, M. F.; Wilson, W. J.; Carmichael, D. C.

1976-01-01

Plant construction costs and manufacturing costs were estimated for the production of solar-grade silicon by the reduction of silicon tetrachloride in a fluidized bed of seed particles, and several modifications of the iodide process using either thermal decomposition on heated filaments (rods) or hydrogen reduction in a fluidized bed of seed particles. Energy consumption data for the zinc reduction process and each of the iodide process options are given and all appear to be acceptable from the standpoint of energy pay back. Information is presented on the experimental zinc reduction of SiCl4 and electrolytic recovery of zinc from ZnCl2. All of the experimental work performed thus far has supported the initial assumption as to technical feasibility of producing semiconductor silicon by the zinc reduction or iodide processes proposed. The results of a more thorough thermodynamic evaluation of the iodination of silicon oxide/carbon mixtures are presented which explain apparent inconsistencies in an earlier cursory examination of the system.

Effect of extraoral aging conditions on mechanical properties of maxillofacial silicone elastomer.

PubMed

Hatamleh, Muhanad M; Polyzois, Gregory L; Silikas, Nick; Watts, David C

2011-08-01

The purpose of this study was to investigate the effect of extraoral human and environmental conditions on the mechanical properties (tensile strength and modulus, elongation, tear strength hardness) of maxillofacial silicone elastomer. Specimens were fabricated using TechSil-S25 silicone elastomer (Technovent Ltd, Leeds, UK). Eight groups were prepared (21 specimens in each group; eight tensile, eight tear, five hardness) and conditioned differently as follows (groups 1 through 8): Dry storage for 24 hours; dry storage in dark for 6 months; storage in simulated sebum solution for 6 months; storage in simulated acidic perspiration for 6 months; accelerated artificial daylight aging under controlled moisture for 360 hours; outdoor weathering for 6 months; storage in antimicrobial silicone-cleaning solution for 30 hours; and mixed conditioning of sebum storage and light aging for 360 hours. The conditioning period selected simulated a prosthesis being in service for up to 12 months. Tensile and tear test specimens were fabricated and tested according to the International Standards Organization (ISO) standards no. 37 and 34, respectively. Shore A hardness test specimens were fabricated and tested according to the American Standards for Testing and Materials (ASTM) D 2240. Data were analyzed with one-way ANOVA, Bonferroni, and Dunnett's T3 post hoc tests (p < 0.05). Weibull analysis was also used for tensile strength and tear strength. Statistically significant differences were evident among all properties tested. Mixed conditioning of simulated sebum storage under accelerated artificial daylight aging significantly degraded mechanical properties of the silicone (p < 0.05). Mechanical properties of maxillofacial elastomers are adversely affected by human and environmental factors. Mixed aging of storage in simulated sebum under accelerated daylight aging was the most degrading regime. Accelerated aging of silicone specimens in simulated sebum under artificial daylight for 12 months of simulated clinical service greatly affected functional properties of silicone elastomer; however, in real practice, the effect is modest, since sebum concentration is lower, and daylight is less concentrated. © 2011 by The American College of Prosthodontists.

Emission measurement and safety assessment for the production process of silicon nanoparticles in a pilot-scale facility

NASA Astrophysics Data System (ADS)

Wang, Jing; Asbach, Christof; Fissan, Heinz; Hülser, Tim; Kaminski, Heinz; Kuhlbusch, Thomas A. J.; Pui, David Y. H.

2012-03-01

Emission into the workplace was measured for the production process of silicon nanoparticles in a pilot-scale facility at the Institute of Energy and Environmental Technology e.V. (IUTA). The silicon nanoparticles were produced in a hot-wall reactor and consisted of primary particles around 60 nm in diameter. We employed real-time aerosol instruments to measure particle number and lung-deposited surface area concentrations and size distribution; airborne particles were also collected for off-line electron microscopic analysis. Emission of silicon nanoparticles was not detected during the processes of synthesis, collection, and bagging. This was attributed to the completely closed production system and other safety measures against particle release which will be discussed briefly. Emission of silicon nanoparticles significantly above the detection limit was only observed during the cleaning process when the production system was open and manually cleaned. The majority of the detected particles was in the size range of 100-400 nm and were silicon nanoparticle agglomerates first deposited in the tubing then re-suspended during the cleaning process. Appropriate personal protection equipment is recommended for safety protection of the workers during cleaning.

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

Low cost solar array project: Experimental process system development unit for producing semiconductor-grade silicon using silane-to-silicon process

NASA Technical Reports Server (NTRS)

1980-01-01

The design, fabrication, and installation of an experimental process system development unit (EPSDU) were analyzed. Supporting research and development were performed to provide an information data base usable for the EPSDU and for technological design and economical analysis for potential scale-up of the process. Iterative economic analyses were conducted for the estimated product cost for the production of semiconductor grade silicon in a facility capable of producing 1000-MT/Yr.

Plasma processes for producing silanes and derivatives thereof

DOEpatents

Laine, Richard M; Massey, Dean Richard; Peterson, Peter Young

2014-03-25

The invention is generally related to process for generating one or more molecules having the formula Si.sub.xH.sub.y, Si.sub.xD.sub.y, Si.sub.xH.sub.yD.sub.z, and mixtures thereof, where x,y and z are integers .gtoreq.1, H is hydrogen and D is deuterium, such as silane, comprising the steps of: providing a silicon containing material, wherein the silicon containing material includes at least 20 weight percent silicon atoms based on the total weight of the silicon containing material; generating a plasma capable of vaporizing a silicon atom, sputtering a silicon atom, or both using a plasma generating device; and contacting the plasma to the silicon containing material in a chamber having an atmosphere that includes at least about 0.5 mole percent hydrogen atoms and/or deuterium atoms based on the total moles of atoms in the atmosphere; so that a molecule having the formula Si.sub.xH.sub.y; (e.g., silane) is generated. The process preferably includes a step of removing one or more impurities from the Si.sub.xH.sub.y (e.g., the silane) to form a clean Si.sub.xH.sub.y, Si.sub.xD.sub.y, Si.sub.xH.sub.yD.sub.z (e.g., silane). The process may also include a step of reacting the Si.sub.xH.sub.y, Si.sub.xD.sub.y, Si.sub.xH.sub.yD.sub.z (e.g., the silane) to produce a high purity silicon containing material such as electronic grade metallic silicon, photovoltaic grade metallic silicon, or both.

Polycrystalline silicon study: Low-cost silicon refining technology prospects and semiconductor-grade polycrystalline silicon availability through 1988

NASA Technical Reports Server (NTRS)

Costogue, E. N.; Ferber, R.; Lutwack, R.; Lorenz, J. H.; Pellin, R.

1984-01-01

Photovoltaic arrays that convert solar energy into electrical energy can become a cost effective bulk energy generation alternative, provided that an adequate supply of low cost materials is available. One of the key requirements for economic photovoltaic cells is reasonably priced silicon. At present, the photovoltaic industry is dependent upon polycrystalline silicon refined by the Siemens process primarily for integrated circuits, power devices, and discrete semiconductor devices. This dependency is expected to continue until the DOE sponsored low cost silicon refining technology developments have matured to the point where they are in commercial use. The photovoltaic industry can then develop its own source of supply. Silicon material availability and market pricing projections through 1988 are updated based on data collected early in 1984. The silicon refining industry plans to meet the increasing demands of the semiconductor device and photovoltaic product industries are overviewed. In addition, the DOE sponsored technology research for producing low cost polycrystalline silicon, probabilistic cost analysis for the two most promising production processes for achieving the DOE cost goals, and the impacts of the DOE photovoltaics program silicon refining research upon the commercial polycrystalline silicon refining industry are addressed.

A metallurgical route to solar-grade silicon

NASA Technical Reports Server (NTRS)

Schei, A.

1986-01-01

The aim of the process is to produce silicon for crystallization into ingots that can be sliced to wafers for processing into photovoltaic cells. If the potential purity can be realized, the silicon will also be applicable for ribbon pulling techniques where the purification during crystallization is negligible. The process consists of several steps: selection and purification of raw materials, carbothermic reduction of silica, ladle treatment, casting, crushing, leaching, and melting. The leaching step is crucial for high purity, and the obtainable purity is determined by the solidification before leaching. The most difficult specifications to fulfill are the low contents of boron, phosphorus, and carbon. Boron and phosphorus can be excluded from the raw materials, but the carbothermic reduction will unavoidably saturate the silicon with carbon at high temperature. During cooling carbon will precipitate as silicon carbide crystals, which will be harmful in solar cells. The cost of this solar silicon will depend strongly on the scale of production. It is as yet premature to give exact figures, but with a scale of some thousand tons per year, the cost will only be a few times the cost of ordinary metallurgical silicon.

A method to enhance the measurement accuracy of Raman shift based on high precision calibration technique

NASA Astrophysics Data System (ADS)

Ding, Xiang; Li, Fei; Zhang, Jiyan; Liu, Wenli

2016-10-01

Raman spectrometers are usually calibrated periodically to ensure their measurement accuracy of Raman shift. A combination of a piece of monocrystalline silicon chip and a low pressure discharge lamp is proposed as a candidate for the reference standard of Raman shift. A high precision calibration technique is developed to accurately determine the standard value of the silicon's Raman shift around 520cm-1. The technique is described and illustrated by measuring a piece of silicon chip against three atomic spectral lines of a neon lamp. A commercial Raman spectrometer is employed and its error characteristics of Raman shift are investigated. Error sources are evaluated based on theoretical analysis and experiments, including the sample factor, the instrumental factor, the laser factor and random factors. Experimental results show that the expanded uncertainty of the silicon's Raman shift around 520cm-1 can acheive 0.3 cm-1 (k=2), which is more accurate than most of currently used reference materials. The results are validated by comparison measurement between three Raman spectrometers. It is proved that the technique can remarkably enhance the accuracy of Raman shift, making it possible to use the silicon and the lamp to calibrate Raman spectrometers.

Trapped rubber processing for advanced composites

NASA Technical Reports Server (NTRS)

Marra, P. J.

1976-01-01

Trapped rubber processing is a molding technique for composites in which precast silicone rubber is placed within a closed cavity where it thermally expands against the composite's surface supported by the vessel walls. The method has been applied by the Douglas Aircraft Company, under contract to NASA-Langley, to the design and fabrication of 10 DC-10 graphite/epoxy upper aft rudder assemblies. A three-bay development tool form mold die has been designed and manufactured, and tooling parameters have been established. Fabrication procedures include graphite layup, assembly of details in the tool, and a cure cycle. The technique has made it possible for the cocured fabrication of complex primary box structures otherwise impracticable via standard composite material processes.

Process development

NASA Technical Reports Server (NTRS)

Bickler, D. B.

1985-01-01

An overview is given of seven process development activities which were presented at this session. Pulsed excimer laser processing of photovoltaic cells was presented. A different pulsed excimer laser annealing was described using a 50 w laser. Diffusion barrier research focused on lowering the chemical reactivity of amorphous thin film on silicon. In another effort adherent and conductive films were successfully achieved. Other efforts were aimed at achieving a simultaneous front and back junction. Microwave enhanced plasma deposition experiments were performed. An updated version of the Solar Array Manufacturing Industry Costing Standards (SAMICS) was presented, along with a life cycle cost analysis of high efficiency cells. The last presentation was on the evaluation of the ethyl vinyl acetate encapsulating system.

Fluidized-Bed Cleaning of Silicon Particles

NASA Technical Reports Server (NTRS)

Rohatgi, Naresh K.; Hsu, George C.

1987-01-01

Fluidized-bed chemical cleaning process developed to remove metallic impurities from small silicon particles. Particles (250 micrometer in size) utilized as seed material in silane pyrolysis process for production of 1-mm-size silicon. Product silicon (1 mm in size) used as raw material for fabrication of solar cells and other semiconductor devices. Principal cleaning step is wash in mixture of hydrochloric and nitric acids, leaching out metals and carrying them away as soluble chlorides. Particles fluidized by cleaning solution to assure good mixing and uniform wetting.

Control of carbon balance in a silicon smelting furnace

DOEpatents

Dosaj, Vishu D.; Haines, Cathryn M.; May, James B.; Oleson, John D.

1992-12-29

The present invention is a process for the carbothermic reduction of silicon dioxide to form elemental silicon. Carbon balance of the process is assessed by measuring the amount of carbon monoxide evolved in offgas exiting the furnace. A ratio of the amount of carbon monoxide evolved and the amount of silicon dioxide added to the furnace is determined. Based on this ratio, the carbon balance of the furnace can be determined and carbon feed can be adjusted to maintain the furnace in carbon balance.

Process for strengthening aluminum based ceramics and material

DOEpatents

Moorhead, Arthur J.; Kim, Hyoun-Ee

2000-01-01

A process for strengthening aluminum based ceramics is provided. A gaseous atmosphere consisting essentially of silicon monoxide gas is formed by exposing a source of silicon to an atmosphere consisting essentially of hydrogen and a sufficient amount of water vapor. The aluminum based ceramic is exposed to the gaseous silicon monoxide atmosphere for a period of time and at a temperature sufficient to produce a continuous, stable silicon-containing film on the surface of the aluminum based ceramic that increases the strength of the ceramic.

Process for forming silicon carbide films and microcomponents

DOEpatents

Hamza, A.V.; Balooch, M.; Moalem, M.

1999-01-19

Silicon carbide films and microcomponents are grown on silicon substrates at surface temperatures between 900 K and 1700 K via C{sub 60} precursors in a hydrogen-free environment. Selective crystalline silicon carbide growth can be achieved on patterned silicon-silicon oxide samples. Patterned SiC films are produced by making use of the high reaction probability of C{sub 60} with silicon at surface temperatures greater than 900 K and the negligible reaction probability for C{sub 60} on silicon dioxide at surface temperatures less than 1250 K. 5 figs.

Process for forming silicon carbide films and microcomponents

DOEpatents

Hamza, Alex V.; Balooch, Mehdi; Moalem, Mehran

1999-01-01

Silicon carbide films and microcomponents are grown on silicon substrates at surface temperatures between 900 K and 1700 K via C.sub.60 precursors in a hydrogen-free environment. Selective crystalline silicon carbide growth can be achieved on patterned silicon-silicon oxide samples. Patterned SiC films are produced by making use of the high reaction probability of C.sub.60 with silicon at surface temperatures greater than 900 K and the negligible reaction probability for C.sub.60 on silicon dioxide at surface temperatures less than 1250 K.

Ultrasonic Measurement Of Silicon-Growth Interface

NASA Technical Reports Server (NTRS)

Heyser, Richard C.

1988-01-01

Position of interface between silicon melt and growing ribbon of silicon measured with aid of reflected ultrasound, according to proposal. Reflections reveal characteristics of ribbon and melt. Ultrasound pulses travel through rods to silicon ribbon growing by dendritic-web process. Rods return reflections of pulses to sonic transducers. Isolate transducers thermally, but not acoustically, from hot silicon melt.

Development of processes for the production of solar grade silicon from halides and alkali metals

NASA Technical Reports Server (NTRS)

Dickson, C. R.; Gould, R. K.

1980-01-01

High temperature reactions of silicon halides with alkali metals for the production of solar grade silicon in volume at low cost were studied. Experiments were performed to evaluate product separation and collection processes, measure heat release parameters for scaling purposes, determine the effects of reactants and/or products on materials of reactor construction, and make preliminary engineering and economic analyses of a scaled-up process.

Current status of solar cell performance of unconventional silicon sheets

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Liu, J. K.

1981-01-01

It is pointed out that activities in recent years directed towards reduction in the cost of silicon solar cells for terrestrial photovoltaic applications have resulted in impressive advancements in the area of silicon sheet formation from melt. The techniques used in the process of sheet formation can be divided into two general categories. All approaches in one category require subsequent ingot wavering. The various procedures of the second category produce silicon in sheet form. The performance of baseline solar cells is discussed. The baseline process included identification marking, slicing to size, and surface treatment (etch-polishing) when needed. Attention is also given to the performance of cells with process variations, and the effects of sheet quality on performance and processing.

Superacid Passivation of Crystalline Silicon Surfaces.

PubMed

Bullock, James; Kiriya, Daisuke; Grant, Nicholas; Azcatl, Angelica; Hettick, Mark; Kho, Teng; Phang, Pheng; Sio, Hang C; Yan, Di; Macdonald, Daniel; Quevedo-Lopez, Manuel A; Wallace, Robert M; Cuevas, Andres; Javey, Ali

2016-09-14

The reduction of parasitic recombination processes commonly occurring within the silicon crystal and at its surfaces is of primary importance in crystalline silicon devices, particularly in photovoltaics. Here we explore a simple, room temperature treatment, involving a nonaqueous solution of the superacid bis(trifluoromethane)sulfonimide, to temporarily deactivate recombination centers at the surface. We show that this treatment leads to a significant enhancement in optoelectronic properties of the silicon wafer, attaining a level of surface passivation in line with state-of-the-art dielectric passivation films. Finally, we demonstrate its advantage as a bulk lifetime and process cleanliness monitor, establishing its compatibility with large area photoluminescence imaging in the process.

Weld microfissuring in Inconel 718 minimized by minor elements

NASA Technical Reports Server (NTRS)

Morrison, T. J.; Shira, C. S.; Weisenberg, L. A.

1968-01-01

Manganese, silicon, and magnesium markedly reduce the tendency of Inconel 718 to weld microfissuring. By combining a manganese, 0.20 percent by content, with silicon, greater than 0.25 percent content, or by adding 20 ppm of magnesium, the weld microfissuring decreased in the standard alloy.

Tracking serum antibody response to viral antigens with arrayed imaging reflectometry

NASA Astrophysics Data System (ADS)

Mace, Charles R.; Rose, Robert C.; Miller, Benjamin L.

2009-02-01

Arrayed Imaging Reflectometry, or "AIR", is a new label-free technique for detecting proteins that relies on bindinginduced changes in the response of an antireflective coating on the surface of a silicon ship. Because the technique provides high sensitivity, excellent dynamic range, and readily integrates with standard silicon wafer processing technology, it is an exceptionally attractive platform on which to build systems for detecting proteins in complex solutions. In our early research, we used AIR chips bearing secreted receptor proteins from enteropathogenic E. coli to develop sensors for this pathogen. Recently, we have been exploring an alternative strategy: Rather than detecting the pathogen directly, can one immobilize antigens from a pathogen, and employ AIR to detect antibody responses to those antigens? Such a strategy would provide enhanced sensitivity for pathogen detection (as the immune system essentially amplifies the "signal" caused by the presence of an organism to which it responds), and would also potentially prove useful in the process of vaccine development. We describe herein preliminary results in the application of such a strategy to the detection of antibodies to human papillomavirus (HPV).

Joining and Integration of Silicon Carbide-Based Materials for High Temperature Applications

NASA Technical Reports Server (NTRS)

Halbig, Michael C.; Singh, Mrityunjay

2016-01-01

Advanced joining and integration technologies of silicon carbide-based ceramics and ceramic matrix composites are enabling for their implementation into wide scale aerospace and ground-based applications. The robust joining and integration technologies allow for large and complex shapes to be fabricated and integrated with the larger system. Potential aerospace applications include lean-direct fuel injectors, thermal actuators, turbine vanes, blades, shrouds, combustor liners and other hot section components. Ground based applications include components for energy and environmental systems. Performance requirements and processing challenges are identified for the successful implementation different joining technologies. An overview will be provided of several joining approaches which have been developed for high temperature applications. In addition, various characterization approaches were pursued to provide an understanding of the processing-microstructure-property relationships. Microstructural analysis of the joint interfaces was conducted using optical, scanning electron, and transmission electron microscopy to identify phases and evaluate the bond quality. Mechanical testing results will be presented along with the need for new standardized test methods. The critical need for tailoring interlayer compositions for optimum joint properties will also be highlighted.

Fabrication of 20.19% Efficient Single-Crystalline Silicon Solar Cell with Inverted Pyramid Microstructure.

PubMed

Zhang, Chunyang; Chen, Lingzhi; Zhu, Yingjie; Guan, Zisheng

2018-04-03

This paper reports inverted pyramid microstructure-based single-crystalline silicon (sc-Si) solar cell with a conversion efficiency up to 20.19% in standard size of 156.75 × 156.75 mm 2 . The inverted pyramid microstructures were fabricated jointly by metal-assisted chemical etching process (MACE) with ultra-low concentration of silver ions and optimized alkaline anisotropic texturing process. And the inverted pyramid sizes were controlled by changing the parameters in both MACE and alkaline anisotropic texturing. Regarding passivation efficiency, the textured sc-Si with normal reflectivity of 9.2% and inverted pyramid size of 1 μm was used to fabricate solar cells. The best batch of solar cells showed a 0.19% higher of conversion efficiency and a 0.22 mA cm -2 improvement in short-circuit current density, and the excellent photoelectric property surpasses that of the same structure solar cell reported before. This technology shows great potential to be an alternative for large-scale production of high efficient sc-Si solar cells in the future.

Asymmetric Multilevel Outphasing (AMO): A New Architecture for All-Silicon mm-Wave Transmitter ICs

DTIC Science & Technology

2015-06-12

power-amplifiers for mobile basestation infrastructure and handsets. NanoSemi Inc. designs linearization solutions for analog front-ends such as...ward flexible, multi-standard radio chips, increases the need for high-precision, high-throughput and energy-efficient backend processing. The desire...peak PAE is affected by less than 1% (46 mW/(46 mW 1.8 W/0.4)) by this 64-QAM capable AMO SCS backend . 378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48

Toroidal silicon polarization analyzer for resonant inelastic x-ray scattering

DOE PAGES

Gao, Xuan; Casa, Diego; Kim, Jungho; ...

2016-08-15

Resonant Inelastic X-ray Scattering (RIXS) is a powerful probe for studying electronic excitations in materials. Standard high energy RIXS measurements do not measure the polarization of the scattered x-rays, which is unfortunate since it carries information about the nature and symmetry of the excitations involved in the scattering process. Moreover we report the fabrication of thin Si-based polarization analyzers with a double-concave toroidal surface, useful for L-edge RIXS studies in heavier atoms such as the 5-d transition metals.

Studies of the Crystallization Process of Aluminum-Silicon Alloys Using a High Temperature Microscope. Thesis

NASA Technical Reports Server (NTRS)

Justi, S.

1985-01-01

It is shown that primary silicon crystals grow polyhedral in super-eutectic AlSi melts and that phosphorus additives to the melt confirm the strong seeding capacity. Primary silicon exhibits strong dendritic seeding effects in eutectic silicon phases of various silicon alloys, whereas primary aluminum does not possess this capacity. Sodium addition also produces a dendritic silicon network growth in the interior of the sample that is attributed to the slower silicon diffusion velocity during cooling.

Fabrication of wear-resistant silicon microprobe tips for high-speed surface roughness scanning devices

NASA Astrophysics Data System (ADS)

Wasisto, Hutomo Suryo; Yu, Feng; Doering, Lutz; Völlmeke, Stefan; Brand, Uwe; Bakin, Andrey; Waag, Andreas; Peiner, Erwin

2015-05-01

Silicon microprobe tips are fabricated and integrated with piezoresistive cantilever sensors for high-speed surface roughness scanning systems. The fabrication steps of the high-aspect-ratio silicon microprobe tips were started with photolithography and wet etching of potassium hydroxide (KOH) resulting in crystal-dependent micropyramids. Subsequently, thin conformal wear-resistant layer coating of aluminum oxide (Al2O3) was demonstrated on the backside of the piezoresistive cantilever free end using atomic layer deposition (ALD) method in a binary reaction sequence with a low thermal process and precursors of trimethyl aluminum and water. The deposited Al2O3 layer had a thickness of 14 nm. The captured atomic force microscopy (AFM) image exhibits a root mean square deviation of 0.65 nm confirming the deposited Al2O3 surface quality. Furthermore, vacuum-evaporated 30-nm/200-nm-thick Au/Cr layers were patterned by lift-off and served as an etch mask for Al2O3 wet etching and in ICP cryogenic dry etching. By using SF6/O2 plasma during inductively coupled plasma (ICP) cryogenic dry etching, micropillar tips were obtained. From the preliminary friction and wear data, the developed silicon cantilever sensor has been successfully used in 100 fast measurements of 5- mm-long standard artifact surface with a speed of 15 mm/s and forces of 60-100 μN. Moreover, the results yielded by the fabricated silicon cantilever sensor are in very good agreement with those of calibrated profilometer. These tactile sensors are targeted for use in high-aspect-ratio microform metrology.

Modified Process For Formation Of Silicon Carbide Matrix Composites

NASA Technical Reports Server (NTRS)

Behrendt, Donald R.; Singh, Mrityunjay

1996-01-01

Modified version of process for making SiC-fiber/SiC-matrix composite material reduces damage to SiC (SCS-6) fibers and to carbon-rich coatings on fibers. Modification consists of addition of second polymer-infiltration-and-pyrolysis step to increase carbon content of porous matrix before infiltration with liquid silicon or silicon alloy.

Heavily Boron-Doped Silicon Layer for the Fabrication of Nanoscale Thermoelectric Devices

PubMed Central

Liu, Yang; Deng, Lingxiao; Zhang, Mingliang; Zhang, Shuyuan; Ma, Jing; Song, Peishuai; Liu, Qing; Ji, An; Yang, Fuhua; Wang, Xiaodong

2018-01-01

Heavily boron-doped silicon layers and boron etch-stop techniques have been widely used in the fabrication of microelectromechanical systems (MEMS). This paper provides an introduction to the fabrication process of nanoscale silicon thermoelectric devices. Low-dimensional structures such as silicon nanowire (SiNW) have been considered as a promising alternative for thermoelectric applications in order to achieve a higher thermoelectric figure of merit (ZT) than bulk silicon. Here, heavily boron-doped silicon layers and boron etch-stop processes for the fabrication of suspended SiNWs will be discussed in detail, including boron diffusion, electron beam lithography, inductively coupled plasma (ICP) etching and tetramethylammonium hydroxide (TMAH) etch-stop processes. A 7 μm long nanowire structure with a height of 280 nm and a width of 55 nm was achieved, indicating that the proposed technique is useful for nanoscale fabrication. Furthermore, a SiNW thermoelectric device has also been demonstrated, and its performance shows an obvious reduction in thermal conductivity. PMID:29385759

Demonstration of the feasibility of automated silicon solar cell fabrication

NASA Technical Reports Server (NTRS)

Taylor, W. E.; Schwartz, F. M.

1975-01-01

A study effort was undertaken to determine the process, steps and design requirements of an automated silicon solar cell production facility. Identification of the key process steps was made and a laboratory model was conceptually designed to demonstrate the feasibility of automating the silicon solar cell fabrication process. A detailed laboratory model was designed to demonstrate those functions most critical to the question of solar cell fabrication process automating feasibility. The study and conceptual design have established the technical feasibility of automating the solar cell manufacturing process to produce low cost solar cells with improved performance. Estimates predict an automated process throughput of 21,973 kilograms of silicon a year on a three shift 49-week basis, producing 4,747,000 hexagonal cells (38mm/side), a total of 3,373 kilowatts at an estimated manufacturing cost of $0.866 per cell or $1.22 per watt.

Addressing the amorphous content issue in quantitative phase analysis: the certification of NIST standard reference material 676a.

PubMed

Cline, James P; Von Dreele, Robert B; Winburn, Ryan; Stephens, Peter W; Filliben, James J

2011-07-01

A non-diffracting surface layer exists at any boundary of a crystal and can comprise a mass fraction of several percent in a finely divided solid. This has led to the long-standing issue of amorphous content in standards for quantitative phase analysis (QPA). NIST standard reference material (SRM) 676a is a corundum (α-Al(2)O(3)) powder, certified with respect to phase purity for use as an internal standard in powder diffraction QPA. The amorphous content of SRM 676a is determined by comparing diffraction data from mixtures with samples of silicon powders that were engineered to vary their specific surface area. Under the (supported) assumption that the thickness of an amorphous surface layer on Si was invariant, this provided a method to control the crystalline/amorphous ratio of the silicon components of 50/50 weight mixtures of SRM 676a with silicon. Powder diffraction experiments utilizing neutron time-of-flight and 25 keV and 67 keV X-ray energies quantified the crystalline phase fractions from a series of specimens. Results from Rietveld analyses, which included a model for extinction effects in the silicon, of these data were extrapolated to the limit of zero amorphous content of the Si powder. The certified phase purity of SRM 676a is 99.02% ± 1.11% (95% confidence interval). This novel certification method permits quantification of amorphous content for any sample of interest, by spiking with SRM 676a.

Solar cell efficiency and high temperature processing of n-type silicon grown by the noncontact crucible method

DOE PAGES

Jensen, Mallory A.; LaSalvia, Vincenzo; Morishige, Ashley E.; ...

2016-08-01

The capital expense (capex) of conventional crystal growth methods is a barrier to sustainable growth of the photovoltaic industry. It is challenging for innovative techniques to displace conventional growth methods due the low dislocation density and high lifetime required for high efficiency devices. One promising innovation in crystal growth is the noncontact crucible method (NOC-Si), which combines aspects of Czochralski (Cz) and conventional casting. This material has the potential to satisfy the dual requirements, with capex likely between that of Cz (high capex) and multicrystalline silicon (mc-Si, low capex). In this contribution, we observe a strong dependence of solar cellmore » efficiency on ingot height, correlated with the evolution of swirl-like defects, for single crystalline n-type silicon grown by the NOC-Si method. We posit that these defects are similar to those observed in Cz, and we explore the response of NOC-Si to high temperature treatments including phosphorous diffusion gettering (PDG) and Tabula Rasa (TR). The highest lifetimes (2033 us for the top of the ingot and 342 us for the bottom of the ingot) are achieved for TR followed by a PDG process comprising a standard plateau and a low temperature anneal. Further improvements can be gained by tailoring the time-temperature profiles of each process. Lifetime analysis after the PDG process indicates the presence of a getterable impurity in the as-grown material, while analysis after TR points to the presence of oxide precipitates especially at the bottom of the ingot. Uniform lifetime degradation is observed after TR which we assign to a presently unknown defect. Lastly, future work includes additional TR processing to uncover the nature of this defect, microstructural characterization of suspected oxide precipitates, and optimization of the TR process to achieve the dual goals of high lifetime and spatial homogenization.« less

A sub-atmospheric chemical vapor deposition process for deposition of oxide liner in high aspect ratio through silicon vias.

PubMed

Lisker, Marco; Marschmeyer, Steffen; Kaynak, Mehmet; Tekin, Ibrahim

2011-09-01

The formation of a Through Silicon Via (TSV) includes a deep Si trench etching and the formation of an insulating layer along the high-aspect-ratio trench and the filling of a conductive material into the via hole. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling of the signal to the silicon. The importance of the oxide thickness on the via wall isolation can be verified using electromagnetic field simulators. To satisfy the needs on the Silicon dioxide deposition, a sub-atmospheric chemical vapor deposition (SA-CVD) process has been developed to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides excellent step coverage of the 100 microm depth silicon trenches with the high aspect ratio of 20 and more. The developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key factor for the performance of TSVs for mm-wave 3D packaging.

Bioactivating Silicon (100) Surfaces with Novel UV Grafting of Cyclopropylamine for Promotion of Cell Adhesion

PubMed Central

Ching, Jing Yuan

2018-01-01

In this report, utraviolent (UV) photoionization of cyclopropylamine on silicon (100) hydride was employed to examine interfacing with three different epithelial cell types (MDA-MB 231, AGS and HEC1A). The cellular viability using this novel methodology had been quantified to evaluate the bioactivating potential of this ring-opening chemistry when compared to standardized controls (aminopropyltriethoxylamine, collagen and poly-L lysine). X-ray photospectroscopy (XPS) and atomic force microscopy (AFM) were used to characterize surface chemistry composition, while cell viability and confocal microscopy after 24 h of incubation were performed. Based on the results acquired from this novel ring-opening metastasis process, the promotion of cell adhesion and viability was found to be higher using this chemistry when compared to other conventional control groups, even for the collagen coating, without any observable issues of cytotoxicity. PMID:29724039

3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications.

PubMed

Sang-Jin Lee; Kavehei, O; Yoon-Ki Hong; Tae Won Cho; Younggap You; Kyoungrok Cho; Eshraghian, K

2010-12-01

This paper presents the implementation of a 3-D architecture for a biomedical-imaging system based on a multilayered system-on-system structure. The architecture consists of a complementary metal-oxide semiconductor image sensor layer, memory, 3-D discrete wavelet transform (3D-DWT), 3-D Advanced Encryption Standard (3D-AES), and an RF transmitter as an add-on layer. Multilayer silicon (Si) stacking permits fabrication and optimization of individual layers by different processing technology to achieve optimal performance. Utilization of through silicon via scheme can address required low-power operation as well as high-speed performance. Potential benefits of 3-D vertical integration include an improved form factor as well as a reduction in the total wiring length, multifunctionality, power efficiency, and flexible heterogeneous integration. The proposed imaging architecture was simulated by using Cadence Spectre and Synopsys HSPICE while implementation was carried out by Cadence Virtuoso and Mentor Graphic Calibre.

Implementation of the CMOS MEMS Condenser Microphone with Corrugated Metal Diaphragm and Silicon Back-Plate

PubMed Central

Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

2011-01-01

This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 μm UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is −42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz–10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 μA, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

Process Feasibility Study in Support of Silicon Material, Task 1

NASA Technical Reports Server (NTRS)

Li, K. Y.; Hansen, K. C.; Yaws, C. L.

1979-01-01

During this reporting period, major activies were devoted to process system properties, chemical engineering and economic analyses. Analyses of process system properties was continued for materials involved in the alternate processes under consideration for solar cell grade silicon. The following property data are reported for silicon tetrafluoride: critical constants, vapor pressure, heat of varporization, heat capacity, density, surface tension, viscosity, thermal conductivity, heat of formation and Gibb's free energy of formation. Chemical engineering analysis of the BCL process was continued with primary efforts being devoted to the preliminary process design. Status and progress are reported for base case conditions; process flow diagram; reaction chemistry; material and energy balances; and major process equipment design.

Evaluation of the Effect of Silicone Contamination on Various Bond Systems and the Feasibility of Removing the Contamination

NASA Technical Reports Server (NTRS)

Stanley, Stephanie D.

2008-01-01

Silicone is a contaminant that can cause catastrophic failure of a bond system depending on the materials and processes used to fabricate the bond system, Unfortunately, more and more materials are fabricated using silicone. The purpose of this testing was to evaluate which bond systems are sensitive to silicone contamination and whether or not a cleaning process could be utilized to remove the silicone to bring the bond system performance back to baseline. Due to the extensive nature of the testing attempts will be made to generalize the understanding within classes of substrates, bond systems, and surface preparation and cleaning methods. This study was done by contaminating various meta! (steel, inconel, and aluminum), phenolic (carbon cloth phenolic and glass cloth phenolic), and rubber (natural rubber, asbestos-silicone dioxide filled natural butyldiene rubber, silica-filled ethylene propylenediene monomer, and carbon-filled ethylene propylenediene monomer) substrates which were then bonded using various adhesives and coatings (epoxy-based adhesives, paints, ablative compounds, and Chemlok adhesives) to determine the effect silicone contamination has on a given bond system's performance. The test configurations depended on the bond system being evaluated. The study also evaluated the feasibility of removing the silicone contamination by cleaning the contaminated substrate prior to bonding. The cleaning processes also varied depending on bond system.

Development of a process for high capacity arc heater production of silicon for solar arrays

NASA Technical Reports Server (NTRS)

Meyer, T. N.

1980-01-01

A high temperature silicon production process using existing electric arc heater technology is discussed. Silicon tetrachloride and a reductant, liquid sodium, were injected into an arc heated mixture of hydrogen and argon. Under these high temperature conditions, a very rapid reaction occurred, yielding silicon and gaseous sodium chloride. Techniques for high temperature separation and collection of the molten silicon were developed. The desired degree of separation was not achieved. The electrical, control and instrumentation, cooling water, gas, SiCl4, and sodium systems are discussed. The plasma reactor, silicon collection, effluent disposal, the gas burnoff stack, and decontamination and safety are also discussed. Procedure manuals, shakedown testing, data acquisition and analysis, product characterization, disassembly and decontamination, and component evaluation are reviewed.

Silicone absorption of elastomeric closures--an accelerated study.

PubMed

Degrazio, F L; Hlobik, T; Vaughan, S

1998-01-01

There is a trend in the parenteral industry to move from the use of elastomeric closures which are washed, siliconized, dried and sterilized in-house at the pharmaceutical manufacturers' site to pre-prepared closures purchased from the closure supplier. This preparation can consist of washing to reduce particle-load and bioburden, siliconization, placement in ready-to-sterilize bags and may eventually extend to sterilization by steam autoclave or gamma irradiation. Since silicone oil lubrication is critical to the processability/machinability of closures, research was designed to investigate this phenomenon in closures prepared using the Westar RS (Ready-to-Sterilize) process. This paper presents the data gathered in a study of the characteristic of silicone absorption into elastomeric closures under accelerated conditions. Variables such as silicone viscosity, rubber formulation, effect of sterilization and others are considered.

Silicon Graphics' IRIS InSight: An SGML Success Story.

ERIC Educational Resources Information Center

Glushko, Robert J.; Kershner, Ken

1993-01-01

Offers a case history of the development of the Silicon Graphics "IRIS InSight" system, a system for viewing on-line documentation using Standard Generalized Markup Language. Notes that SGML's explicit encoding of structure and separation of structure and presentation make possible structure-based search, alternative structural views of…

Application of CMOS Technology to Silicon Photomultiplier Sensors.

PubMed

D'Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-09-25

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments.

Flat-plate solar-array project. Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

NASA Technical Reports Server (NTRS)

1981-01-01

The engineering design, fabrication, assembly, operation, economic analysis, and process support R and D for an Experimental Process System Development Unit (EPSDU) are reported. About 95% of purchased equipment is received and will be reshipped to the West Coast location. The Data Collection System is completed. In the area of melting/consolidation, to the system using silicon powder transfer, melting and shotting on a pseudocontinuous basis is demonstrated. It is proposed to continue the very promising fluid bed work.

Semiconductor technology program: Progress briefs

NASA Technical Reports Server (NTRS)

Galloway, K. F.; Scace, R. I.; Walters, E. J.

1981-01-01

Measurement technology for semiconductor materials, process control, and devices, is discussed. Silicon and silicon based devices are emphasized. Highlighted activities include semiinsulating GaAs characterization, an automatic scanning spectroscopic ellipsometer, linewidth measurement and coherence, bandgap narrowing effects in silicon, the evaluation of electrical linewidth uniformity, and arsenicomplanted profiles in silicon.

Electromigration process for the purification of molten silicon during crystal growth

DOEpatents

Lovelace, Alan M. Administrator of the National Aeronautics and Space; Shlichta, Paul J.

1982-01-01

A process for the purification of molten materials during crystal growth by electromigration of impurities to localized dirty zones. The process has particular applications for silicon crystal growth according to Czochralski techniques and edge-defined film-fed growth (EFG) conditions. In the Czochralski crystal growing process, the impurities are electromigrated away from the crystallization interface by applying a direct electrical current to the molten silicon for electromigrating the charged impurities away from the crystal growth interface. In the EFG crystal growth process, a direct electrical current is applied between the two faces which are used in forming the molten silicon into a ribbon. The impurities are thereby migrated to one side only of the crystal ribbon. The impurities may be removed or left in place. If left in place, they will not adversely affect the ribbon when used in solar collectors. The migration of the impurity to one side only of the silicon ribbon is especially suitable for use with asymmetric dies which preferentially crystallize uncharged impurities along one side or face of the ribbon.

Alternative process for thin layer etching: Application to nitride spacer etching stopping on silicon germanium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Posseme, N., E-mail: nicolas.posseme@cea.fr; Pollet, O.; Barnola, S.

2014-08-04

Silicon nitride spacer etching realization is considered today as one of the most challenging of the etch process for the new devices realization. For this step, the atomic etch precision to stop on silicon or silicon germanium with a perfect anisotropy (no foot formation) is required. The situation is that none of the current plasma technologies can meet all these requirements. To overcome these issues and meet the highly complex requirements imposed by device fabrication processes, we recently proposed an alternative etching process to the current plasma etch chemistries. This process is based on thin film modification by light ionsmore » implantation followed by a selective removal of the modified layer with respect to the non-modified material. In this Letter, we demonstrate the benefit of this alternative etch method in term of film damage control (silicon germanium recess obtained is less than 6 A), anisotropy (no foot formation), and its compatibility with other integration steps like epitaxial. The etch mechanisms of this approach are also addressed.« less

Evaluation of selected chemical processes for production of low-cost silicon. Quarterly progress report, 15 Dec 1975--31 Mar 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blocher, J.M. Jr; Browning, M.F.; Wilson, W.J.

1976-04-08

Plant construction costs and manufacturing costs were estimmated for the production of solar-grade silicon by the reduction of silicon tetrachloride in a fluidized bed of seed particles, and several modifications of the iodide process using either thermal decomposition on heated filaments (rods) or hydrogen reduction in a fluidized bed of seed particles. Energy consumption data for the zinc reduction process and each of the iodide process options are given and all appear to be acceptable from the standpoint of energy pay back. Information is presented on the experimental zinc reduction of SiCl4 and electrolytic recovery of zinc from ZnCl2. Allmore » of the experimental work performed thus far has supported the initial assumption as to technical feasibility of producing semiconductor silicon by the zinc reduction or iodide processes proposed. The results of a more thorough thermodynamic evaluation of the iodination of silicon oxide/carbon mixtures are presented which explain apparent inconsistencies in an earlier cursory examination of the system.« less

Polarization-selective infrared bandpass filter based on a two-layer subwavelength metallic grating

NASA Astrophysics Data System (ADS)

Hohne, Andrew J.; Moon, Benjamin; Baumbauer, Carol L.; Gray, Tristan; Dilts, James; Shaw, Joseph A.; Dickensheets, David L.; Nakagawa, Wataru

2017-08-01

We present the design, fabrication, and characterization of a polarization-selective infrared bandpass filter based on a two-layer subwavelength metallic grating for use in polarimetric imaging. Gold nanowires were deposited via physical vapor deposition (PVD) onto a silicon surface relief grating that was patterned using electron beam lithography (EBL) and fabricated using standard silicon processing techniques. Optical characterization with a broad-spectrum tungsten halogen light source and a grating spectrometer showed normalized peak TM transmission of 53% with a full-width at half-maximum (FWHM) of 122 nm, which was consistent with rigorous coupled-wave analysis (RCWA) simulations. Simulation results suggested that device operation relied on suppression of the TM transmission caused by surface plasmon polariton (SPP) excitation at the gold-silicon interface and an increase in TM transmission caused by a Fabry-Perot (FP) resonance in the cavity between the gratings. TE rejection occurred at the initial air/gold interface. We also present simulation results of an improved design based on a two-dielectric grating where two different SPP resonances allowed us to improve the shape of the passband by suppressing the side lobes. This newer design resulted in improved side-band performance and increased peak TM transmission.

Palladium nanoparticle deposition via precipitation: a new method to functionalize macroporous silicon

PubMed Central

Scheen, Gilles; Bassu, Margherita; Douchamps, Antoine; Zhang, Chao; Debliquy, Marc; Francis, Laurent A

2014-01-01

We present an original two-step method for the deposition via precipitation of Pd nanoparticles into macroporous silicon. The method consists in immersing a macroporous silicon sample in a PdCl2/DMSO solution and then in annealing the sample at a high temperature. The impact of composition and concentration of the solution and annealing time on the nanoparticle characteristics is investigated. This method is compared to electroless plating, which is a standard method for the deposition of Pd nanoparticles. Scanning electron microscopy and computerized image processing are used to evaluate size, shape, surface density and deposition homogeneity of the Pd nanoparticles on the pore walls. Energy-dispersive x-ray spectroscopy (EDX) and x-ray photoelectron spectroscopy (XPS) analyses are used to evaluate the composition of the deposited nanoparticles. In contrast to electroless plating, the proposed method leads to homogeneously distributed Pd nanoparticles along the macropores depth with a surface density that increases proportionally with the PdCl2 concentration. Moreover EDX and XPS analysis showed that the nanoparticles are composed of Pd in its metallic state, while nanoparticles deposited by electroless plating are composed of both metallic Pd and PdOx. PMID:27877732

Mass measurement of 1 kg silicon spheres to establish a density standard

NASA Astrophysics Data System (ADS)

Mizushima, S.; Ueki, M.; Fujii, K.

2004-04-01

Air buoyancy causes a significant systematic effect in precision mass determination of 1 kg silicon spheres. In order to correct this effect accurately, mass measurement of the silicon sphere was conducted using buoyancy artefacts; additionally, in order to stabilize atmospheric conditions, we used a vacuum chamber in which a mass comparator had been installed. The silicon sphere was also weighed in vacuum to verify the air buoyancy correction. Mass differences measured in air and in vacuum showed good agreement with each other in spite of the desorption effect from weight surfaces. Furthermore, the result of weighing under vacuum conditions demonstrated better repeatability than that obtained in air.

Process Research of Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1984-01-01

A passivation process (hydrogenation) that will improve the power generation of solar cells fabricated from presently produced, large grain, cast polycrystalline silicon (Semix), a potentially low cost material are developed. The first objective is to verify the operation of a DC plasma hydrogenation system and to investigate the effect of hydrogen on the electrical performance of a variety of polycrystalline silicon solar cells. The second objective is to parameterize and optimize a hydrogenation process for cast polycrystalline silicon, and will include a process sensitivity analysis. The sample preparation for the first phase is outlined. The hydrogenation system is described, and some early results that were obtained using the hydrogenation system without a plasma are summarized. Light beam induced current (LBIC) measurements of minicell samples, and their correlation to dark current voltage characteristics, are discussed.

Key Processes of Silicon-On-Glass MEMS Fabrication Technology for Gyroscope Application.

PubMed

Ma, Zhibo; Wang, Yinan; Shen, Qiang; Zhang, Han; Guo, Xuetao

2018-04-17

MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.

Mid-IR soliton compression in silicon optical fibers and fiber tapers.

PubMed

Peacock, Anna C

2012-03-01

Numerical simulations are used to investigate soliton compression in silicon core optical fibers at 2.3 μm in the mid-infrared waveguide regime. Compression in both standard silicon fibers and fiber tapers is compared to establish the relative compression ratios for a range of input pulse conditions. The results show that tapered fibers can be used to obtain higher levels of compression for moderate soliton orders and thus lower input powers. © 2012 Optical Society of America

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

Thermal sensing of cryogenic wind tunnel model surfaces Evaluation of silicon diodes

NASA Technical Reports Server (NTRS)

Daryabeigi, K.; Ash, R. L.; Dillon-Townes, L. A.

1986-01-01

Different sensors and installation techniques for surface temperature measurement of cryogenic wind tunnel models were investigated. Silicon diodes were selected for further consideration because of their good inherent accuracy. Their average absolute temperature deviation in comparison tests with standard platinum resistance thermometers was found to be 0.2 K in the range from 125 to 273 K. Subsurface temperature measurement was selected as the installation technique in order to minimize aerodynamic interference. Temperature distortion caused by an embedded silicon diode was studied numerically.

Thermal sensing of cryogenic wind tunnel model surfaces - Evaluation of silicon diodes

NASA Technical Reports Server (NTRS)

Daryabeigi, Kamran; Ash, Robert L.; Dillon-Townes, Lawrence A.

1986-01-01

Different sensors and installation techniques for surface temperature measurement of cryogenic wind tunnel models were investigated. Silicon diodes were selected for further consideration because of their good inherent accuracy. Their average absolute temperature deviation in comparison tests with standard platinum resistance thermometers was found to be 0.2 K in the range from 125 to 273 K. Subsurface temperature measurement was selected as the installation technique in order to minimize aerodynamic interference. Temperature distortion caused by an embedded silicon diode was studied numerically.

Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

PubMed

Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

2013-11-15

We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

Silicon quantum dots for energetic material applications

NASA Astrophysics Data System (ADS)

Adams, Sarah K.; Piekiel, Nicholas W.; Ervin, Matthew H.; Morris, Christopher J.

2018-06-01

In its history as an energetic material, porous silicon has demonstrated flame speeds in excess of 3 km s-1, tunable combustion behavior, and high energy output, which in theory makes it a very attractive energetic system. In practice, its application within the field is limited by porous silicon's typical substrate-adhered form and caustic chemical processing requirements that limit how and when porous silicon is made. In this work, we have relieved porous silicon of these constraints by creating reactive silicon quantum dots from free-standing porous silicon films. The resulting material is composed of crystalline silicon nanoparticles with diameters as small as 2 nm that retain the chemical properties of the original films including the SiH2 termination layer. The fabricated silicon particles were characterized using FTIR Spectroscopy, TEM, and EDS for determining the size and the chemical composition. For testing as an energetic material fuel, porous silicon was mixed with an oft used oxidizer, sodium perchlorate. During open-channel combustion tests, silicon quantum dots mixed with sodium perchlorate demonstrated flame speeds over 2.5 km s-1, while bomb calorimetry tests showed an average heat of combustion of 7.4 kJ g-1. These results demonstrate the ability to retain the porous silicon material properties that allow for highly energetic material reactions to occur, despite the additional processing steps to create silicon quantum dots. This opens the door for the use of porous silicon in the bulk of the energetic material application space, much of which was previously limited due to the substrate-attached nature of typical porous silicon.

Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process

DOEpatents

McKee, Rodney A.; Walker, Frederick J.

1993-01-01

A process and structure involving a silicon substrate utilizes an ultra high vacuum and molecular beam epitaxy (MBE) methods to grow an epitaxial oxide film upon a surface of the substrate. As the film is grown, the lattice of the compound formed at the silicon interface becomes stabilized, and a base layer comprised of an oxide having a sodium chloride-type lattice structure grows epitaxially upon the compound so as to cover the substrate surface. A perovskite may then be grown epitaxially upon the base layer to render a product which incorporates silicon, with its electronic capabilities, with a perovskite having technologically-significant properties of its own.

Toxic Compounds in Our Food: Arsenic Uptake By Rice and Potential Mitigation By Silicon

NASA Astrophysics Data System (ADS)

Seyfferth, A.; Gill, R.; Penido, E.

2014-12-01

Arsenic is a ubiquitous element in soils worldwide and has the potential to negatively impact human and ecosystem health under certain biogeochemical conditions. While arsenic is relatively immobile in most oxidized soils due to a high affinity for soil solids, arsenic becomes mobilized under reduced soil conditions due to the reductive dissolution of iron(III) oxides thereby releasing soil-bound arsenic. Since arsenic is a well-known carcinogen, this plant-soil process has the potential to negatively impact the lives of billions of rice consumers worldwide upon plant uptake and grain storage of released arsenic. Moreover, arsenic uptake by rice is excacerbated by the use of As-laden groundwater for rice irrigation. One proposed strategy to decrease arsenic uptake by rice plants is via an increase in dissolved silicon in paddy soil solution (pore-water), since silicic acid and arsenous acid share an uptake pathway. However, several soil processes that influence arsenic cycling may be affected by silicon including desorption from bulk soil, formation and mineralogy of iron(III) oxide plaque, and adsorption/desorption onto/from iron plaque; the effect of silicon on these soil processes will ultimately dictate the effectiveness of altered dissolved silicon in decreasing arsenic uptake at the root, which in turn dictates the concentration of arsenic found in grains. Furthermore, the source of silicon may impact carbon cycling and, in particular, methane emissions. Here, impacts of altered dissolved silicon on processes that affect rhizospheric biogeochemical cycling of arsenic and subsequent plant-uptake, and how it influences other biogeochemical cycles such as carbon and iron are investigated. We show that silicon can decrease arsenic uptake and grain storage under certain conditions, and that altered silicon affects the type of iron (III) oxide that comprises iron plaque.

Negative-tone development of photoresists in environmentally friendly silicone fluids

NASA Astrophysics Data System (ADS)

Ouyang, Christine Y.; Lee, Jin-Kyun; Ober, Christopher K.

2012-03-01

The large amount of organic solvents and chemicals that are used in today's microelectronic fabrication process can lead to environmental, health and safety hazards. It is therefore necessary to design new materials and new processes to reduce the environmental impact of the lithographic process. In addition, as the feature sizes decrease, other issues such as pattern collapse, which is related to the undesirable high surface tension of the developers and rinse liquids, can occur and limit the resolution. In order to solve these issues, silicone fluids are chosen as alternative developing solvents in this paper. Silicone fluids, also known as linear methyl siloxanes, are a class of mild, non-polar solvents that are non-toxic, not ozone-depleting, and contribute little to global warming. They are considered as promising developers because of their environmental-friendliness and their unique physical properties such as low viscosity and low surface tension. Recently, there have been emerging interests in negative-tone development (NTD) due to its better ability in printing contact holes and trenches. It is also found that the performance of negative-tone development is closely related to the developing solvents. Silicone fluids are thus promising developers for NTD because of their non-polar nature and high contrast negative-tone images are expected with chemical amplification photoresists due to the high chemical contrast of chemical amplification. We have previously shown some successful NTD with conventional photoresists such as ESCAP in silicone fluids. In this paper, another commercially available TOK resist was utilized to study the NTD process in silicone fluids. Because small and non-polar molecules are intrinsically soluble in silicone fluids, we have designed a molecular glass resist for silicone fluids. Due to the low surface tension of silicone fluids, we are able achieve high aspect-ratio, high-resolution patterns without pattern collapse.

Development of a Process for a High Capacity Arc Heater Production of Silicon for Solar Arrays

NASA Technical Reports Server (NTRS)

Reed, W. H.

1979-01-01

A program was established to develop a high temperature silicon production process using existing electric arc heater technology. Silicon tetrachloride and a reductant (sodium) are injected into an arc heated mixture of hydrogen and argon. Under these high temperature conditions, a very rapid reaction is expected to occur and proceed essentially to completion, yielding silicon and gaseous sodium chloride. Techniques for high temperature separation and collection were developed. Included in this report are: test system preparation; testing; injection techniques; kinetics; reaction demonstration; conclusions; and the project status.

Bond Testing for Effects of Silicone Contamination

NASA Technical Reports Server (NTRS)

Plaia, James; Evans, Kurt

2005-01-01

In 2003 ATK Thiokol discovered that the smocks and coveralls worn by its operations personnel for safety and contamination control were themselves contaminated with a silicone defoamer and a silicone oil. As a growing list of items have been identified as having this form of contamination, it was desirable to devise a test method to determine if the contamination level detected could cause subsequent processing concerns. The smocks and coveralls could potentially contact bonding surfaces during processing so the test method focused on dry transfer of the silicone from the clothing to the bonding surface.

Mesoporous silicon synthesis and applications in Li-ion batteries and solar hydrogen fuel cells

DOEpatents

Wang, Donghai; Dai, Fang; Yi, Ran; Zai, Jianto

2017-05-23

We provide a mesoporous silicon material (PSi) prepared via a template-free and HF-free process. The production process is facile and scalable, and it may be conducted under mild reaction conditions. The silicon may be produced directly by the reduction of a silicon-halogenide precursor (for example, SiCl.sub.4) with an alkaline alloy (for example, NaK alloy). The resulting Si-salt matrix is then annealed for the pore formation and crystallite growth. Final product is obtained by removal of the salt by-products with water.

Manufacture of silicon carbide using solar energy

DOEpatents

Glatzmaier, Gregory C.

1992-01-01

A method is described for producing silicon carbide particles using solar energy. The method is efficient and avoids the need for use of electrical energy to heat the reactants. Finely divided silica and carbon are admixed and placed in a solar-heated reaction chamber for a time sufficient to cause a reaction between the ingredients to form silicon carbide of very small particle size. No grinding of silicon carbide is required to obtain small particles. The method may be carried out as a batch process or as a continuous process.

EPITAXIAL GROWTH OF SILICON

DTIC Science & Technology

Epitaxial growth of silicon on a silicon substrate by hydrogen reduction of SiCl4 was investigated. The chemical and physical processes involved in...silicon layers were produced at temperatures between 1100 and 1300 C. The effects of the concentration of SiCl4 in H2, the flow rate of the gas, the

Monitoring of the Irradiated Neutron Fluence in the Neutron Transmutation Doping Process of Hanaro

NASA Astrophysics Data System (ADS)

Kim, Myong-Seop; Park, Sang-Jun

2009-08-01

Neutron transmutation doping (NTD) for silicon is a process of the creation of phosphorus impurities in intrinsic or extrinsic silicon by neutron irradiation to obtain silicon semiconductors with extremely uniform dopant distribution. HANARO has two vertical holes for the NTD, and the irradiation for 5 and 6 inch silicon ingots has been going on at one hole. In order to achieve the accurate neutron fluence corresponding to the target resistivity, the real time neutron flux is monitored by self-powered neutron detectors. After irradiation, the total irradiation fluence is confirmed by measuring the absolute activity of activation detectors. In this work, a neutron fluence monitoring method using zirconium foils with the mass of 10 ~ 50 mg was applied to the NTD process of HANARO. We determined the proportional constant of the relationship between the resistivity of the irradiated silicon and the neutron fluence determined by using zirconium foils. The determined constant for the initially n-type silicon was 3.126 × 1019 n·Ω/cm. It was confirmed that the difference between this empirical value and the theoretical one was only 0.5%. Conclusively, the practical methodology to perform the neutron transmutation doping of silicon was established.

Study of the deposition process of vinpocetine on the surface of porous silicon

NASA Astrophysics Data System (ADS)

Lenshin, A. S.; Polkovnikova, Yu. A.; Seredin, P. V.

Currently the most prospective way in pharmacotherapy is the obtaining of nanoparticles involving pharmaceutical substances. Application of porous inorganic materials on the basis of silicon is among the main features in solving of this problem. The present work is concerned with the problem of the deposition of pharmaceutical drug with nootropic activity - vinpocetine - into porous silicon. Silicon nanoparticles were obtained by electrochemical anodic etching of Si plates. The process of vinpocetine deposition was studied in dependence of the deposition time. As a result of the investigations it was found that infrared transmission spectra of porous silicon with the deposited vinpocetine revealed the absorption bands characteristic of vinpocetine substance.

Evaluation of selected chemical processes for production of low-cost silicon phase 2. silicon material task, low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Blocher, J. M., Jr.; Browning, M. F.; Rose, E. E.; Thompson, W. B.; Schmitt, W. A.; Fippin, J. S.; Kidd, R. W.; Liu, C. Y.; Kerbler, P. S.; Ackley, W. R.

1978-01-01

Progress from October 1, 1977, through December 31, 1977, is reported in the design of the 50 MT/year experimental facility for the preparation of high purity silicon by the zinc vapor reduction of silicon tetrachloride in a fluidized bed of seed particles to form a free flowing granular product.

Use of silicon in liquid sintered silicon nitrides and sialons

DOEpatents

Raj, Rishi; Baik, Sunggi

1984-12-11

This invention relates to the production of improved high density nitrogen based ceramics by liquid-phase densification of silicon nitride or a compound of silicon-nitrogen-oxygen-metal, e.g. a sialon. In the process and compositions of the invention minor amounts of finely divided silicon are employed together with the conventional liquid phase producing additives to enhance the densification of the resultant ceramic.

Simultaneous Purification and Perforation of Low-Grade Si Sources for Lithium-Ion Battery Anode.

PubMed

Jin, Yan; Zhang, Su; Zhu, Bin; Tan, Yingling; Hu, Xiaozhen; Zong, Linqi; Zhu, Jia

2015-11-11

Silicon is regarded as one of the most promising candidates for lithium-ion battery anodes because of its abundance and high theoretical capacity. Various silicon nanostructures have been heavily investigated to improve electrochemical performance by addressing issues related to structure fracture and unstable solid-electrolyte interphase (SEI). However, to further enable widespread applications, scalable and cost-effective processes need to be developed to produce these nanostructures at large quantity with finely controlled structures and morphologies. In this study, we develop a scalable and low cost process to produce porous silicon directly from low grade silicon through ball-milling and modified metal-assisted chemical etching. The morphology of porous silicon can be drastically changed from porous-network to nanowire-array by adjusting the component in reaction solutions. Meanwhile, this perforation process can also effectively remove the impurities and, therefore, increase Si purity (up to 99.4%) significantly from low-grade and low-cost ferrosilicon (purity of 83.4%) sources. The electrochemical examinations indicate that these porous silicon structures with carbon treatment can deliver a stable capacity of 1287 mAh g(-1) over 100 cycles at a current density of 2 A g(-1). This type of purified porous silicon with finely controlled morphology, produced by a scalable and cost-effective fabrication process, can also serve as promising candidates for many other energy applications, such as thermoelectrics and solar energy conversion devices.

Application of CMOS Technology to Silicon Photomultiplier Sensors

PubMed Central

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

PLA and two components silicon rubber blends aiming for frozen foods packaging applications

NASA Astrophysics Data System (ADS)

Meekum, Utai; Khiansanoi, Apichart

2018-03-01

Designing of PLA and two components silicone rubber blends was studies. Frozen food packaging application is the main ultimate aim. The statistical method using 23 DOE was conducted. The standard testing methods, in particular impact testing at sub-zero temperature, were performed. The preliminary blend formula comprised 1.0 phr of silane and polyester polyols, respectively, was initially resolved. Then, the optimize the silicone portion in the blends was determined. Blending formula using 8.0 phr of silicone with respect to PLA matrix gave rise to the overall satisfactory properties. 3. TETA was used as the silicone curing agent and reactively blended onto the ingredients. TETA at 0.4 phr, with respect to the silicone, enhanced the mechanical properties, especially flexibility and toughness, of the PLA/silicone blend. Exceeding the optimal TETA loading would cause the chain scission and also the dilution effects. Hence, marginal inferior properties of the blends were be experienced. The preliminary biodegradability investigation found that the PLA/silicone blend initially triggered at the second week. Its degradation rate was likely to be faster than neat PLA.

III-V-on-silicon solar cells reaching 33% photoconversion efficiency in two-terminal configuration

NASA Astrophysics Data System (ADS)

Cariou, Romain; Benick, Jan; Feldmann, Frank; Höhn, Oliver; Hauser, Hubert; Beutel, Paul; Razek, Nasser; Wimplinger, Markus; Bläsi, Benedikt; Lackner, David; Hermle, Martin; Siefer, Gerald; Glunz, Stefan W.; Bett, Andreas W.; Dimroth, Frank

2018-04-01

Silicon dominates the photovoltaic industry but the conversion efficiency of silicon single-junction solar cells is intrinsically constrained to 29.4%, and practically limited to around 27%. It is possible to overcome this limit by combining silicon with high-bandgap materials, such as III-V semiconductors, in a multi-junction device. Significant challenges associated with this material combination have hindered the development of highly efficient III-V/Si solar cells. Here, we demonstrate a III-V/Si cell reaching similar performances to standard III-V/Ge triple-junction solar cells. This device is fabricated using wafer bonding to permanently join a GaInP/GaAs top cell with a silicon bottom cell. The key issues of III-V/Si interface recombination and silicon's weak absorption are addressed using poly-silicon/SiOx passivating contacts and a novel rear-side diffraction grating for the silicon bottom cell. With these combined features, we demonstrate a two-terminal GaInP/GaAs//Si solar cell reaching a 1-sun AM1.5G conversion efficiency of 33.3%.

High-speed bipolar phototransistors in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Zimmermann, H

2013-03-01

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm 2 and 100×100 μm 2 . Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p + wafer with a p - epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Low cost silicon solar array project silicon materials task: Establishment of the feasibility of a process capable of low-cost, high volume production of silane (step 1) and the pyrolysis of silane to semiconductor-grade silicon (step 2)

NASA Technical Reports Server (NTRS)

Breneman, W. C.; Farrier, E. G.; Rexer, J.

1977-01-01

Extended operation of a small process-development unit routinely produced high quality silane in 97+% yield from dichlorosilane. The production rate was consistent with design loadings for the fractionating column and for the redistribution reactor. A glass fluid-bed reactor was constructed for room temperature operation. The behavior of a bed of silcon particles was observed as a function of various feedstocks, component configurations, and operating conditions. For operating modes other than spouting, the bed behaved in an erratic and unstable manner. A method was developed for casting molten silicon powder into crack-free solid pellets for process evaluation. The silicon powder was melted and cast into thin walled quartz tubes that sacrificially broke on cooling.

Solar silicon via improved and expanded metallurgical silicon technology

NASA Technical Reports Server (NTRS)

Hunt, L. P.; Dosaj, V. D.; Mccormick, J. R.

1977-01-01

A completed preliminary survey of silica sources indicates that sufficient quantities of high-purity quartz are available in the U.S. and Canada to meet goals. Supply can easily meet demand for this little-sought commodity. Charcoal, as a reductant for silica, can be purified to a sufficient level by high-temperature fluorocarbon treatment and vacuum processing. High-temperature treatment causes partial graphitization which can lead to difficulty in smelting. Smelting of Arkansas quartz and purified charcoal produced kilogram quantities of silicon having impurity levels generally much lower than in MG-Si. Half of the goal was met of increasing the boron resistivity from 0.03 ohm-cm in metallurgical silicon to 0.3 ohm-cm in solar silicon. A cost analysis of the solidification process indicate $3.50-7.25/kg Si for the Czochralski-type process and $1.50-4.25/kg Si for the Bridgman-type technique.

Crystal growth for high-efficiency silicon solar cells workshop: Summary

NASA Technical Reports Server (NTRS)

Dumas, K. A.

1985-01-01

The state of the art in the growth of silicon crystals for high-efficiency solar cells are reviewed, sheet requirements are defined, and furture areas of research are identified. Silicon sheet material characteristics that limit cell efficiencies and yields were described as well as the criteria for the ideal sheet-growth method. The device engineers wish list to the material engineer included: silicon sheet with long minority carrier lifetime that is uniform throughout the sheet, and which doesn't change during processing; and sheet material that stays flat throughout device processing, has uniform good mechanical strength, and is low cost. Impurities in silicon solar cells depreciate cell performance by reducing diffusion length and degrading junctions. The impurity behavior, degradation mechanisms, and variations in degradation threshold with diffusion length for silicon solar cells were described.

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

NASA Technical Reports Server (NTRS)

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

MicroElectroMechanical devices and fabrication technologies for radio-frequency analog signal processing

NASA Astrophysics Data System (ADS)

Young, Darrin Jun

The proliferation of wireless services creates a pressing need for compact and low cost RF transceivers. Modern sub-micron technologies provide the active components needed for miniaturization but fail to deliver high quality passives needed in oscillators and filters. This dissertation demonstrates procedures for adding high quality inductors and tunable capacitors to a standard silicon integrated circuits. Several voltage-controlled oscillators operating in the low Giga-Hertz range demonstrate the suitability of these components for high performance RF building blocks. Two low-temperature processes are described to add inductors and capacitors to silicon ICs. A 3-D coil geometry is used for the inductors rather than the conventional planar spiral to substantially reduce substrate loss and hence improve the quality factor and self-resonant frequency. Measured Q-factors at 1 GHz are 30 for a 4.8 nH device, 16 for 8.2 nH and 13.8 nH inductors. Several enhancements are proposed that are expected to result in a further improvement of the achievable Q-factor. This research investigates the design and fabrication of silicon-based IC-compatible high-Q tunable capacitors and inductors. The goal of this investigation is to develop a monolithic low phase noise radio-frequency voltage-controlled oscillator using these high-performance passive components for wireless communication applications. Monolithic VCOs will help the miniaturization of current radio transceivers, which offers a potential solution to achieve a single hand-held wireless phone with multistandard capabilities. IC-compatible micromachining fabrication technologies have been developed to realize on-chip high-Q RF tunable capacitors and 3-D coil inductors. The capacitors achieve a nominal capacitance value of 2 pF and can be tuned over 15% with 3 V. A quality factor over 60 has been measured at 1 GHz. 3-D coil inductors obtain values of 4.8 nH, 8.2 nH and 13.8 nH. At 1 GHz a Q factor of 30 has been achieved for a 4.8 nH device and a Q of 16 for 8.2 nH and 13.8 nH inductors. A prototype RF voltage-controlled oscillator has been implemented employing the micromachined tunable capacitors and a 8.2 nH 3-D coil inductor. The active electronics, tunable capacitors and inductor are fabricated on separated silicon substrates and wire bonded to form the VCO. This hybrid approach is used to avoid the complexity of building the prototype oscillator. Both passive components are fabricated on silicon substrates and thus amenable to monolithic integration with standard IC process. The VCO achieves a -136 dBc/Hz phase noise at a 3 MHz offset frequency from the carrier, suitable for most wireless communication applications and is tunable from 855 MHz to 863 MHz with 3 V.

Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

PubMed Central

Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

2012-01-01

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

Efficient 'Optical Furnace': A Cheaper Way to Make Solar Cells is Reaching the Marketplace

DOE Office of Scientific and Technical Information (OSTI.GOV)

von Kuegelgen, T.

In Bhushan Sopori's laboratory, you'll find a series of optical furnaces he has developed for fabricating solar cells. When not in use, they sit there discreetly among the lab equipment. But when a solar silicon wafer is placed inside one for processing, Sopori walks over to a computer and types in a temperature profile. Almost immediately this fires up the furnace, which glows inside and selectively heats up the silicon wafer to 800 degrees centigrade by the intense light it produces. Sopori, a principal engineer at the National Renewable Energy Laboratory, has been researching and developing optical furnace technology formore » around 20 years. He says it's a challenging technology to develop because there are many issues to consider when you process a solar cell, especially in optics. Despite the challenges, Sopori and his research team have advanced the technology to the point where it will benefit all solar cell manufacturers. They are now developing a commercial version of the furnace in partnership with a manufacturer. 'This advanced optical furnace is highly energy efficient, and it can be used to manufacture any type of solar cell,' he says. Each type of solar cell or manufacturing process typically requires a different furnace configuration and temperature profile. With NREL's new optical furnace system, a solar cell manufacturer can ask the computer for any temperature profile needed for processing a solar cell, and the same type of furnace is suitable for several solar cell fabrication process steps. 'In the future, solar cell manufacturers will only need this one optical furnace because it can be used for any process, including diffusion, metallization and oxidation,' Sopori says. 'This helps reduce manufacturing costs.' One startup company, Applied Optical Systems, has recognized the furnace's potential for manufacturing thin-film silicon cells. 'We'd like to develop thin-film silicon cells with higher efficiencies, up to 15 to 18 percent, and we believe this furnace will enable us to do so,' says A. Rangappan, founder and CEO of Applied Optical Systems. Rangappan also says it will take only a few minutes for the optical furnace to process a thin-film solar cell, which reduces manufacturing costs. Overall, he estimates the company's solar cell will cost around 80 cents per watt. For manufacturing these thin-film silicon cells, Applied Optical Systems and NREL have developed a partnership through a cooperative research and development agreement (CRADA) to construct an optical furnace system prototype. DOE is providing $500,000 from its Technology Commercialization Development Fund to help offset the prototype's development costs because of the technology's significant market potential. The program has provided the NREL technology transfer office with a total of $4 million to expand such collaborative efforts between NREL researchers and companies. Applied Optical will construct a small version of the optical furnace based on the prototype design in NREL's process development and integration laboratory through a separate CRADA. This small furnace will only develop one solar cell wafer at a time. Then, the company will construct a large, commercial-scale optical furnace at its own facilities, which will turn out around 1,000 solar cell wafers per hour. 'We hope to start using the optical furnace for manufacturing within four to five years,' Rangappan says. Meanwhile, another partnership using the optical furnace has evolved between NREL and SiXtron Advanced Materials, another startup. Together they'll use the optical furnace to optimize the metallization process for novel antireflective solar cell coatings. The process is not only expected to yield higher efficiencies for silicon-based solar cells, but also lowers processing costs and eliminates safety concerns for manufacturers. Most solar cell manufacturers currently use a plasma-enhanced chemical vapor deposition (PECVD) system with compressed and extremely pyrophoric silane gas (SiH4) for applying passivation antireflective coatings (ARC). If silane is exposed to air, the SiH4 will explode - a serious safety issue for high-volume manufacturers. SiXtron's process uses a solid, silicon-based polymer that's converted into noncompressed, nonexplosive gas, which then flows to a standard PECVD system. 'The solid source is so safe to handle that it can be shipped by FedEx,' says Zbigniew Barwicz, president and CEO of SiXtron. Barwicz says manufacturers can use the same PECVD processing equipment for the SiXtron process that they already use for SiH4, a plug-and-play solution. For this novel passivation ARC process, NREL is helping to optimize the metallization parameters. NREL has developed a new technology called optical processing. One of the applications of this process is fire-through contact formation of silicon solar cells.« less

Silicon Isotopic Measurements in Desolvated Samples by MC-ICP-MS

NASA Astrophysics Data System (ADS)

Cardinal, D.; Alleman, L.; Ziegler, K.; de Jong, J.; Andre, L.

2002-12-01

Silicon, the most ubiquitous rock-forming element presents also a key role in biological processes. In particular, its biogeochemical cycle constitutes one of the most challenging issues in recent years due to its close relationship with the carbon cycle in marine environments (Tréguer et al., 1995; Ragueneau et al., 2000). The most recent silicon isotopic investigations on various natural samples have highlighted the great potential of this (palaeo)-proxy for oceanographers (De La Rocha et al., 1997, 1998). Better understanding the silicon isotope fractionation due to various biogeochemical processes can be achieved by facilitating its measurements through MC-ICPMS technique (De La Rocha et al., 2002; Alleman et al., 2002). In this regard we have developed an original method to analyze silicon isotopes under dry plasma conditions. We demonstrate that coupling a Nu Plasma MC-ICP-MS with a Cetac Aridus desolvator allows the rapid acquisition of natural silicon isotope abundances with high sensitivity and accuracy. To adequately correct for the mass fractionation occurring at the interface between the plasma source and the mass spectrometer line, we combine external normalization using Mg as a dopant with standard-sample bracketing using NBS-28 as the reference. With the desolvating nebulization system, the measurement of 28Si and 29Si isotopes is not hampered by significant interferences. δ29Si values are obtained with an accuracy and repeatability better than 0.1 \\permil. The accuracy has been successfully calibrated against the laser fluorination line technique (De La Rocha et al., 1996; Alleman et al., 2002). We could demonstrate that the isotopic fractionation that might occur in the plasma or the desolvator was adequately corrected by combining Mg isotopes and the sample-standard bracketing procedure. Moreover, the preservation of the Si isotopic signatures of the samples is validated by the different chemical sample treatments required by these two techniques. This method presents clear advantages compared to the wet plasma technique described by De La Rocha et al. (2002), also using a Nu Plasma MC-ICP-MS, as being much more sensitive and less time consuming. We report here single δ29Si data obtained within one hour and requiring less than 3μg Si per sample. Preliminary results over a large range of natural samples including diatomite, large diatoms, sponge spicules, phytoliths and water from lakes and seawater will also be presented and briefly discussed. Alleman et al., 2002, Geochim. Cosmochim. Acta, 66:15A, A14, Abstract.\\De La Rocha et al., 1996, Anal. Chem., 68, 3746-3750.\\De La Rocha et al., 1997, Geochim. Cosmochim. Acta, 61, 5051-5056.\\De La Rocha et al., 1998, Nature, 395, 680-683.\\De La Rocha, 2002, Geochem., Geophys., Geosyst., 3(8), 10.1029/2002GC00310.\\Ragueneau et al., 2000, Global Planet. Change, 26, 317-365.\\Tréguer et al., 1995, Science, 268, 375-379.

Electrochemical Formation of a p-n Junction on Thin Film Silicon Deposited in Molten Salt.

PubMed

Zou, Xingli; Ji, Li; Yang, Xiao; Lim, Taeho; Yu, Edward T; Bard, Allen J

2017-11-15

Herein we report the demonstration of electrochemical deposition of silicon p-n junctions all in molten salt. The results show that a dense robust silicon thin film with embedded junction formation can be produced directly from inexpensive silicates/silicon oxide precursors by a two-step electrodeposition process. The fabricated silicon p-n junction exhibits clear diode rectification behavior and photovoltaic effects, indicating promise for application in low-cost silicon thin film solar cells.

Determination of traces of silicone defoamer in fruit juices by solvent extraction/atomic absorption spectroscopy.

PubMed

Gooch, E G

1993-01-01

Silicone defoamers are used to control foam during the processing of fruit juices. Residual silicones in fruit juices can be separated from the naturally occurring siliceous materials in fruit products and selectively recovered by solvent extraction, after suitable pretreatment. The recovered silicone is measured by atomic absorption spectroscopy. Silicone concentrations as low as about 1 ppm can be measured. The juices are accurately spiked for recovery studies by the addition of silicone dispersed in D-sorbitol.

Integrated Thermal Modules for Cooling Silicon and Silicon Carbide Power Modules

DTIC Science & Technology

2007-06-11

analyses, bench tests, and motor tests comprise the program. The ITMs, in place of standard heatsinks, use a highly conductive pyrolytic graphite to...passively cool power modules. Initial results show that even simple ITMs can lower chip temperatures by 20 deg. C and 10 deg. C with engine oil and

Planned delayed relaxing retinotomy for proliferative vitreoretinopathy.

PubMed

Williamson, Tom H; Gupta, Bhaskar

2010-01-01

A program involving three operations-the first to reattach most of the retina under silicone oil, the second to reattach the remaining retina by planned delayed relaxing retinectomy (PDRR), and the third to remove silicone oil-was tested. Review of electronic records of patients receiving PDRR for proliferative vitreoretinopathy (PVR). The primary end point was reattached retina without silicone oil. Eighty-seven patients had PVR and 27 received PDRR (mean age: 66.6 years; mean follow-up: 2.3 years). Ten patients had grade B PVR, 8 had CP1 to CP6, and 7 had CA2 to CA6. Twenty-four (89%) patients achieved a reattached retina without silicone oil. Mean logarithm of the minimum angle of resolution visual acuities were 1.41 (standard deviation = 0.67) at presentation and 1.21 (standard deviation = 0.58) at final follow-up. Four patients had glaucoma and 1 had scleromalacia. The overall success rate for all patients with PVR was 85% reattached retina without oil tamponade. PDRR contributes to a high chance of reattached retina and oil removal in PVR. Copyright 2010, SLACK Incorporated.

Area Reports. Advanced materials and devices research area. Silicon materials research task, and advanced silicon sheet task

NASA Technical Reports Server (NTRS)

1986-01-01

The objectives of the Silicon Materials Task and the Advanced Silicon Sheet Task are to identify the critical technical barriers to low-cost silicon purification and sheet growth that must be overcome to produce a PV cell substrate material at a price consistent with Flat-plate Solar Array (FSA) Project objectives and to overcome these barriers by performing and supporting appropriate R&D. Progress reports are given on silicon refinement using silane, a chemical vapor transport process for purifying metallurgical grade silicon, silicon particle growth research, and modeling of silane pyrolysis in fluidized-bed reactors.

A high volume cost efficient production macrostructuring process. [for silicon solar cell surface treatment

NASA Technical Reports Server (NTRS)

Chitre, S. R.

1978-01-01

The paper presents an experimentally developed surface macro-structuring process suitable for high volume production of silicon solar cells. The process lends itself easily to automation for high throughput to meet low-cost solar array goals. The tetrahedron structure observed is 0.5 - 12 micron high. The surface has minimal pitting with virtually no or very few undeveloped areas across the surface. This process has been developed for (100) oriented as cut silicon. Chemi-etched, hydrophobic and lapped surfaces were successfully texturized. A cost analysis as per Samics is presented.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Zook, J. D.; Harrison, W. B.; Scott, M. W.; Hendrickson, G.; Wolner, H. A.; Nelson, L. D.; Schuller, T. L.; Peterson, A. A.

1976-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon by dip-coating one surface of carbonized ceramic substrates with a thin layer of large grain polycrystalline silicon was investigated. The dip-coating methods studied were directed toward a minimum cost process with the ultimate objective of producing solar cells with a conversion efficiency of 10% or greater. The technique shows excellent promise for low cost, labor-saving, scale-up potentialities and would provide an end product of sheet silicon with a rigid and strong supportive backing. An experimental dip-coating facility was designed and constructed, several substrates were successfully dip-coated with areas as large as 25 sq cm and thicknesses of 12 micron to 250 micron. There appears to be no serious limitation on the area of a substrate that could be coated. Of the various substrate materials dip-coated, mullite appears to best satisfy the requirement of the program. An inexpensive process was developed for producing mullite in the desired geometry.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Extradural and subarachnoid catheterization using the Seldinger technique.

PubMed

Delhaas, E M

1996-01-01

The Seldinger technique was developed using a plastic introducer through which introduction and manipulations of a silicone spinal catheter, an extradural stimulation lead or a small diameter fibreoptic scope are possible without the risk of damage to the vulnerable devices. It is not intended as a replacement of the standard technique of introducing a spinal catheter through a Tuohy needle in general anaesthetic practice. Silicone spinal catheters and stimulation leads are used for long-term therapy in intractable chronic pain and spasticity. A fibreoptic scope is used for endoscopic examination of the subarachnoid or extradural space. Using a standard Tuohy needle the soft silicone extradural lead can be damaged easily by manipulations during insertion. For this reason the manufacturer modified the Tuohy needle for extradural silicone lead introduction. The disadvantages of this modified Tuohy needle are: first, difficulty in localization of the extradural space, second, the needle is unsuitable for a subarachnoid catheter or introduction of a fibreoptic scope. The Seldinger technique was performed 25 times in 18 patients, introducing a spinal silicone catheter (n = 14), an extradural silicone stimulation lead (n = 2) or a small diameter fibreoptic endoscope (n = 9). Paraesthesiae caused by neural irritation occurred in awake patients. This did not differ from the technique using a Tuohy needle only. Neural damage or trauma did not occur with the Seldinger technique. The incidence of post-spinal headache was the same for both techniques. No further complications were noted.

Use of silicon in liquid sintered silicon nitrides and sialons

DOEpatents

Raj, R.; Baik, S.

1984-12-11

This invention relates to the production of improved high density nitrogen based ceramics by liquid-phase densification of silicon nitride or a compound of silicon-nitrogen-oxygen-metal, e.g. a sialon. In the process and compositions of the invention minor amounts of finely divided silicon are employed together with the conventional liquid phase producing additives to enhance the densification of the resultant ceramic. 4 figs.

Use of free silicon in liquid phase sintering of silicon nitrides and sialons

DOEpatents

Raj, R.; Baik, S.

1985-11-12

This invention relates to the production of improved high density nitrogen based ceramics by liquid-phase densification of silicon nitride or a compound of silicon-nitrogen-oxygen-metal, e.g. a sialon. In the process and compositions of the invention minor amounts of finely divided silicon are employed together with the conventional liquid phase producing additives to enhance the densification of the resultant ceramic. 4 figs.

Use of free silicon in liquid phase sintering of silicon nitrides and sialons

DOEpatents

Raj, Rishi; Baik, Sunggi

1985-11-12

This invention relates to the production of improved high density nitrogen based ceramics by liquid-phase densification of silicon nitride or a compound of silicon-nitrogen-oxygen-metal, e.g. a sialon. In the process and compositions of the invention minor amounts of finely divided silicon are employed together with the conventional liquid phase producing additives to enhance the densification of the resultant ceramic.

Evaluation of the Effect of Silicone Contamination on Various Bond Systems and the Feasibility of Removing the Contamination

NASA Technical Reports Server (NTRS)

Stanley, Stephanie D.

2008-01-01

Silicone is a contaminant that can cause catastrophic failure of a bond system depending on the materials and processes used to fabricate the bond system. Unfortunately, more and more materials are fabricated using silicone. The purpose of this testing was to evaluate which bond systems are sensitive to silicone contamination and whether or not a cleaning process could be utilized to remove the silicone to bring the bond system performance back to baseline. Due to the extensive nature of the testing, attempts will be made to generalize the understanding within classes of substrates, bond systems, and surface preparation and cleaning methods. This study was done by contaminating various metal (steel, Inconel, and aluminum), phenolic (carbon-cloth phenolic [CCP] and glass-cloth phenolic [GCP]), and rubber (natural rubber, asbestos-silicone dioxide filled natural butyldiene rubber [ASNBR]; silica-filled ethylene propylenediene monomer [SFEPDM], and carbon-filled ethylene propylenediene monomer [CFEPDM]) substrates which were then bonded using various adhesives and coatings (epoxy-based adhesives, paints, ablative compounds, and Chemlok adhesives) to determine the effect silicone contamination has on a given bond system's performance. The test configurations depended on the bond system being evaluated. The study also evaluated the feasibility of removing the silicone contamination by cleaning the contaminated substrate prior to bonding. The cleaning processes also varied depending on bond system.

Investigation of Proposed Process Sequence for the Array Automated Assembly Task, Phase 2. [low cost silicon solar array fabrication

NASA Technical Reports Server (NTRS)

Mardesich, N.; Garcia, A.; Bunyan, S.; Pepe, A.

1979-01-01

The technological readiness of the proposed process sequence was reviewed. Process steps evaluated include: (1) plasma etching to establish a standard surface; (2) forming junctions by diffusion from an N-type polymeric spray-on source; (3) forming a p+ back contact by firing a screen printed aluminum paste; (4) forming screen printed front contacts after cleaning the back aluminum and removing the diffusion oxide; (5) cleaning the junction by a laser scribe operation; (6) forming an antireflection coating by baking a polymeric spray-on film; (7) ultrasonically tin padding the cells; and (8) assembling cell strings into solar circuits using ethylene vinyl acetate as an encapsulant and laminating medium.

Effect of processing parameters on reaction bonding of silicon nitride

NASA Technical Reports Server (NTRS)

Richman, M. H.; Gregory, O. J.; Magida, M. B.

1980-01-01

Reaction bonded silicon nitride was developed. The relationship between the various processing parameters and the resulting microstructures was to design and synthesize reaction bonded materials with improved room temperature mechanical properties.

Evaluation of thiolated silicone oil as advanced mucoadhesive antifoaming agent.

PubMed

Partenhauser, Alexandra; Netsomboon, Kesinee; Leonaviciute, Gintare; Bernkop-Schnürch, Andreas

2016-10-01

Silicone oils, such as dimethicone, are commonly administered against gastrointestinal gas accumulation and are attributed with mucoprotective features. Evaluation of thiolated silicone oil as advanced antiflatulence with a prolonged retention on small intestinal mucosa as an intended site of action. 3-Mercaptopropionic acid (MPA) as a thiol ligand was covalently attached to silicone oil. This thiomer was assessed with regard to foam inhibiting action, droplet size of a suitable self-emulsifying system, mucoadhesion and cytotoxicity. Antifoaming activity of silicone-MPA was complying with United States Pharmacopeia (USP) requirements for simethicone as standard antiflatulence. Another antifoaming test performed on porcine mucosa supported silicone-MPA's outstanding foam destruction, as this thiomer was superior in comparison to non-thiolated silicone oil and dimethicone with 14.7 ± 2.1 versus 73.3 ± 9.1 and 66.3 ± 7.5 s, respectively. A significantly enhanced mucoadhesiveness (p < 0.02) with 26.2 ± 7.1% silicone formulation remaining on small intestinal mucosa after 8 h was evident for the thiomer without any toxic effect. Thiolated silicone oil was found to exhibit excellent antifoaming and superior mucoadhesive features. The prolonged residence time of thiolated silicone oil promises to be beneficial in the treatment of flatulence, aerophagy and inflammation throughout the whole gastrointestinal tract.

Vertically Integrated MEMS SOI Composite Porous Silicon-Crystalline Silicon Cantilever-Array Sensors: Concept for Continuous Sensing of Explosives and Warfare Agents

NASA Astrophysics Data System (ADS)

Stolyarova, Sara; Shemesh, Ariel; Aharon, Oren; Cohen, Omer; Gal, Lior; Eichen, Yoav; Nemirovsky, Yael

This study focuses on arrays of cantilevers made of crystalline silicon (c-Si), using SOI wafers as the starting material and using bulk micromachining. The arrays are subsequently transformed into composite porous silicon-crystalline silicon cantilevers, using a unique vapor phase process tailored for providing a thin surface layer of porous silicon on one side only. This results in asymmetric cantilever arrays, with one side providing nano-structured porous large surface, which can be further coated with polymers, thus providing additional sensing capabilities and enhanced sensing. The c-Si cantilevers are vertically integrated with a bottom silicon die with electrodes allowing electrostatic actuation. Flip Chip bonding is used for the vertical integration. The readout is provided by a sensitive Capacitance to Digital Converter. The fabrication, processing and characterization results are reported. The reported study is aimed towards achieving miniature cantilever chips with integrated readout for sensing explosives and chemical warfare agents in the field.

Low energy production processes in manufacturing of silicon solar cells

NASA Technical Reports Server (NTRS)

Kirkpatrick, A. R.

1976-01-01

Ion implantation and pulsed energy techniques are being combined for fabrication of silicon solar cells totally under vacuum and at room temperature. Simplified sequences allow very short processing times with small process energy consumption. Economic projections for fully automated production are excellent.

Low cost solar aray project: Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

NASA Technical Reports Server (NTRS)

1981-01-01

This phase consists of the engineering design, fabrication, assembly, operation, economic analysis, and process support R&D for an Experimental Process System Development Unit (EPSDU). The mechanical bid package was issued and the bid responses are under evaluation. Similarly, the electrical bid package was issued, however, responses are not yet due. The majority of all equipment is on order or has been received at the EPSDU site. The pyrolysis/consolidation process design package was issued. Preparation of process and instrumentation diagram for the free-space reactor was started. In the area of melting/consolidation, Kayex successfully melted chunk silicon and have produced silicon shot. The free-space reactor powder was successfully transported pneumatically from a storage bin to the auger feeder twenty-five feet up and was melted. The fluid-bed PDU has successfully operated at silane feed concentrations up to 21%. The writing of the operating manual has started. Overall, the design phase is nearing completion.

Addressing the Amorphous Content Issue in Quantitative Phase Analysis: The Certification of NIST Standard Reference Material 676a

DOE Office of Scientific and Technical Information (OSTI.GOV)

J Cline; R Von Dreele; R Winburn

2011-12-31

A non-diffracting surface layer exists at any boundary of a crystal and can comprise a mass fraction of several percent in a finely divided solid. This has led to the long-standing issue of amorphous content in standards for quantitative phase analysis (QPA). NIST standard reference material (SRM) 676a is a corundum ({alpha}-Al{sub 2}O{sub 3}) powder, certified with respect to phase purity for use as an internal standard in powder diffraction QPA. The amorphous content of SRM 676a is determined by comparing diffraction data from mixtures with samples of silicon powders that were engineered to vary their specific surface area. Undermore » the (supported) assumption that the thickness of an amorphous surface layer on Si was invariant, this provided a method to control the crystalline/amorphous ratio of the silicon components of 50/50 weight mixtures of SRM 676a with silicon. Powder diffraction experiments utilizing neutron time-of-flight and 25 keV and 67 keV X-ray energies quantified the crystalline phase fractions from a series of specimens. Results from Rietveld analyses, which included a model for extinction effects in the silicon, of these data were extrapolated to the limit of zero amorphous content of the Si powder. The certified phase purity of SRM 676a is 99.02% {+-} 1.11% (95% confidence interval). This novel certification method permits quantification of amorphous content for any sample of interest, by spiking with SRM 676a.« less

Characterization of zinc oxide thin film for pH detector

NASA Astrophysics Data System (ADS)

Hashim, Uda; Fathil, M. F. M.; Arshad, M. K. Md; Gopinath, Subash C. B.; Uda, M. N. A.

2017-03-01

This paper presents the fabrication process of the zinc oxide thin films for using to act as pH detection by using different PH solution. Sol-gel solution technique is used for preparing zinc oxide seed solution, followed by metal oxide deposition process by using spin coater on the silicon dioxide. Silicon dioxide layer is grown on the silicon wafer, then, ZnO seed solution is deposited on the silicon layer, baked, and annealing process carried on to undergo the characterization of its surface morphology, structural and crystalline phase. Electrical characterization is showed by using PH 4, 7, and 10 is dropped on the surface of the die, in addition, APTES solution is used as linker and also as a references of the electrical characterization.

Optofluidic encapsulation and manipulation of silicon microchips using image processing based optofluidic maskless lithography and railed microfluidics.

PubMed

Chung, Su Eun; Lee, Seung Ah; Kim, Jiyun; Kwon, Sunghoon

2009-10-07

We demonstrate optofluidic encapsulation of silicon microchips using image processing based optofluidic maskless lithography and manipulation using railed microfluidics. Optofluidic maskless lithography is a dynamic photopolymerization technique of free-floating microstructures within a fluidic channel using spatial light modulator. Using optofluidic maskless lithography via computer-vision aided image processing, polymer encapsulants are fabricated for chip protection and guiding-fins for efficient chip conveying within a fluidic channel. Encapsulated silicon chips with guiding-fins are assembled using railed microfluidics, which is an efficient guiding and heterogeneous self-assembly system of microcomponents. With our technology, externally fabricated silicon microchips are encapsulated, fluidically guided and self-assembled potentially enabling low cost fluidic manipulation and assembly of integrated circuits.

Heat- and electron-beam-induced transport of gold particles into silicon oxide and silicon studied by in situ high-resolution transmission electron microscopy.

PubMed

Biskupek, Johannes; Kaiser, Ute; Falk, Fritz

2008-06-01

In this study, we describe the transport of gold (Au) nanoparticles from the surface into crystalline silicon (Si) covered by silicon oxide (SiO(2)) as revealed by in situ high-resolution transmission electron microscopy. Complete crystalline Au nanoparticles sink through the SiO(2) layer into the Si substrate when high-dose electron irradiation is applied and temperature is raised above 150 degrees C. Above temperatures of 250 degrees C, the Au nanoparticles finally dissolve into fragments accompanied by crystallization of the amorphized Si substrate around these fragments. The transport process is explained by a wetting process followed by Stokes motion. Modelling this process yields boundaries for the interface energies involved.

Monolithically interconnected silicon-film™ module technology

NASA Astrophysics Data System (ADS)

DelleDonne, E. J.; Ford, D. H.; Hall, R. B.; Ingram, A. E.; Rand, J. A.; Barnett, A. M.

1999-03-01

AstroPower is developing an advanced thin-silicon-based, photovoltaic module product. A low-cost monolithic interconnected device is being integrated into a module that combines the design and process features of advanced light trapped, thin-silicon solar cells. This advanced product incorporates a low-cost substrate, a nominally 50-μm thick grown silicon layer with minority carrier diffusion lengths exceeding the active layer thickness, light trapping due to back-surface reflection, and back-surface passivation. The thin silicon layer enables high solar cell performance and can lead to a module conversion efficiency as high as 19%. These performance design features, combined with low-cost manufacturing using relatively low-cost capital equipment, continuous processing and a low-cost substrate, will lead to high-performance, low-cost photovoltaic panels.

Laser-zone growth in a Ribbon-To-Ribbon, RTR, process silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Gurtler, R. W.; Baghdadi, A.

1977-01-01

A ribbon-to-ribbon process was used for routine growth of samples for analysis and fabrication into solar cells. One lot of solar cells was completely evaluated: ribbon solar cell efficiencies averaged 9.23% with a highest efficiency of 11.7%. Spherical reflectors have demonstrated significant improvements in laser silicon coupling efficiencies. Material analyses were performed including silicon photovoltage and open circuit photovoltage diffusion length measurements, crystal morphology studies, modulus of rupture measurements, and annealing/gettering studies. An initial economic analysis was performed indicating that ribbon-to-ribbon add-on costs of $.10/watt might be expected in the early 1980's.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Laser ablation of single-crystalline silicon by radiation of pulsed frequency-selective fiber laser

NASA Astrophysics Data System (ADS)

Veiko, V. P.; Skvortsov, A. M.; Huynh, C. T.; Petrov, A. A.

2015-07-01

We have studied the process of destruction of the surface of a single-crystalline silicon wafer scanned by the beam of a pulsed ytterbium-doped fiber laser radiation with a wavelength of λ = 1062 nm. It is established that the laser ablation can proceed without melting of silicon and the formation of a plasma plume. Under certain parameters of the process (radiation power, beam scan velocity, and beam overlap density), pronounced oxidation of silicon microparticles with the formation of a characteristic loose layer of fine powdered silicon dioxide has been observed for the first time. The range of lasing and beam scanning regimes in which the growth of SiO2 layer takes place is determined.

Direct Growth of Graphene on Silicon by Metal-Free Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Tai, Lixuan; Zhu, Daming; Liu, Xing; Yang, Tieying; Wang, Lei; Wang, Rui; Jiang, Sheng; Chen, Zhenhua; Xu, Zhongmin; Li, Xiaolong

2018-06-01

The metal-free synthesis of graphene on single-crystal silicon substrates, the most common commercial semiconductor, is of paramount significance for many technological applications. In this work, we report the growth of graphene directly on an upside-down placed, single-crystal silicon substrate using metal-free, ambient-pressure chemical vapor deposition. By controlling the growth temperature, in-plane propagation, edge-propagation, and core-propagation, the process of graphene growth on silicon can be identified. This process produces atomically flat monolayer or bilayer graphene domains, concave bilayer graphene domains, and bulging few-layer graphene domains. This work would be a significant step toward the synthesis of large-area and layer-controlled, high-quality graphene on single-crystal silicon substrates. [Figure not available: see fulltext.

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Optimizing total reflection X-ray fluorescence for direct trace element quantification in proteins I: Influence of sample homogeneity and reflector type

NASA Astrophysics Data System (ADS)

Wellenreuther, G.; Fittschen, U. E. A.; Achard, M. E. S.; Faust, A.; Kreplin, X.; Meyer-Klaucke, W.

2008-12-01

Total reflection X-ray fluorescence (TXRF) is a very promising method for the direct, quick and reliable multi-elemental quantification of trace elements in protein samples. With the introduction of an internal standard consisting of two reference elements, scandium and gallium, a wide range of proteins can be analyzed, regardless of their salt content, buffer composition, additives and amino acid composition. This strategy also enables quantification of matrix effects. Two potential issues associated with drying have been considered in this study: (1) Formation of heterogeneous residues of varying thickness and/or density; and (2) separation of the internal standard and protein during drying (which has to be prevented to allow accurate quantification). These issues were investigated by microbeam X-ray fluorescence (μXRF) with special emphasis on (I) the influence of sample support and (II) the protein / buffer system used. In the first part, a model protein was studied on well established sample supports used in TXRF, PIXE and XRF (Mylar, siliconized quartz, Plexiglas and silicon). In the second part we imaged proteins of different molecular weight, oligomerization state, bound metals and solubility. A partial separation of protein and internal standard was only observed with untreated silicon, suggesting it may not be an adequate support material. Siliconized quartz proved to be the least prone to heterogeneous drying of the sample and yielded the most reliable results.

Development of a direct procedure for the measurement of sulfur isotope variability in beers by MC-ICP-MS.

PubMed

Giner Martínez-Sierra, J; Santamaria-Fernandez, R; Hearn, R; Marchante Gayón, J M; García Alonso, J I

2010-04-14

In this work, a multi-collector inductively coupled plasma mass spectrometer (MC-ICP-MS) was evaluated for the direct measurement of sulfur stable isotope ratios in beers as a first step toward a general study of the natural isotope variability of sulfur in foods and beverages. Sample preparation consisted of a simple dilution of the beers with 1% (v/v) HNO(3). It was observed that different sulfur isotope ratios were obtained for different dilutions of the same sample indicating that matrix effects affected differently the transmission of the sulfur ions at masses 32, 33, and 34 in the mass spectrometer. Correction for mass bias related matrix effects was evaluated using silicon internal standardization. For that purpose, silicon isotopes at masses 29 and 30 were included in the sulfur cup configuration and the natural silicon content in beers used for internal mass bias correction. It was observed that matrix effects on differential ion transmission could be corrected adequately using silicon internal standardization. The natural isotope variability of sulfur has been evaluated by measuring 26 different beer brands. Measured delta(34)S values ranged from -0.2 to 13.8 per thousand. Typical combined standard uncertainties of the measured delta(34)S values were < or = 2 per thousand. The method has therefore great potential to study sulfur isotope variability in foods and beverages.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

From SHG to mid-infrared SPDC generation in strained silicon waveguides

NASA Astrophysics Data System (ADS)

Castellan, Claudio; Trenti, Alessandro; Mancinelli, Mattia; Marchesini, Alessandro; Ghulinyan, Mher; Pucker, Georg; Pavesi, Lorenzo

2017-08-01

The centrosymmetric crystalline structure of Silicon inhibits second order nonlinear optical processes in this material. We report here that, by breaking the silicon symmetry with a stressing silicon nitride over-layer, Second Harmonic Generation (SHG) is obtained in suitably designed waveguides where multi-modal phase-matching is achieved. The modeling of the generated signal provides an effective strain-induced second order nonlinear coefficient of χ(2) = (0.30 +/- 0.02) pm/V. Our work opens also interesting perspectives on the reverse process, the Spontaneous Parametric Down Conversion (SPDC), through which it is possible to generate mid-infrared entangled photon pairs.

Sol-gel-Derived nano-sized double layer anti-reflection coatings (SiO2/TiO2) for low-cost solar cell fabrication.

PubMed

Lee, Seung Jun; Hur, Man Gyu; Yoon, Dae Ho

2013-11-01

We investigate nano-sized double layer anti-reflection coatings (ARCs) using a TiO2 and SiO2 sol-gel solution process for mono-crystalline silicon solar cells. The process can be easily adapted for spraying sol-gel coatings to reduce manufacturing cost. The spray-coated SiO2/TiO2 nano-sized double layer ARCs were deposited on mono-crystalline silicon solar cells, and they showed good optical properties. The spray coating process is a lower-cost fabrication process for large-scale coating than vacuum deposition processes such as PECVD. The measured average optical reflectance (300-1200 nm) was about approximately 8% for SiO2/TiO2 nano-sized double layer ARCs. The electrical parameters of a mono-crystalline silicon solar cell and reflection losses show that the SiO2/TiO2 stacks can improve cell efficiency by 0.2% compared to a non-coated mono-crystalline silicon solar cell. In the results, good correlation between theoretical and experimental data was obtained. We expect that the sol-gel spray-coated mono-crystalline silicon solar cells have high potential for low-cost solar cell fabrication.

High-Accuracy Surface Figure Measurement of Silicon Mirrors at 80 K

NASA Technical Reports Server (NTRS)

Blake, Peter; Mink, Ronald G.; Chambers, John; Davila, Pamela; Robinson, F. David

2004-01-01

This report describes the equipment, experimental methods, and first results at a new facility for interferometric measurement of cryogenically-cooled spherical mirrors at the Goddard Space Flight Center Optics Branch. The procedure, using standard phase-shifting interferometry, has an standard combined uncertainty of 3.6 nm rms in its representation of the two-dimensional surface figure error at 80, and an uncertainty of plus or minus 1 nm in the rms statistic itself. The first mirror tested was a concave spherical silicon foam-core mirror, with a clear aperture of 120 mm. The optic surface was measured at room temperature using standard absolute techniques; and then the change in surface figure error from room temperature to 80 K was measured. The mirror was cooled within a cryostat. and its surface figure error measured through a fused-silica window. The facility and techniques will be used to measure the surface figure error at 20K of prototype lightweight silicon carbide and Cesic mirrors developed by Galileo Avionica (Italy) for the European Space Agency (ESA).

Performance and Transient Behavior of Vertically Integrated Thin-film Silicon Sensors

PubMed Central

Wyrsch, Nicolas; Choong, Gregory; Miazza, Clément; Ballif, Christophe

2008-01-01

Vertical integration of amorphous hydrogenated silicon diodes on CMOS readout chips offers several advantages compared to standard CMOS imagers in terms of sensitivity, dynamic range and dark current while at the same time introducing some undesired transient effects leading to image lag. Performance of such sensors is here reported and their transient behaviour is analysed and compared to the one of corresponding amorphous silicon test diodes deposited on glass. The measurements are further compared to simulations for a deeper investigation. The long time constant observed in dark or photocurrent decay is found to be rather independent of the density of defects present in the intrinsic layer of the amorphous silicon diode. PMID:27873778

Ion implantation reduces radiation sensitivity of metal oxide silicon /MOS/ devices

NASA Technical Reports Server (NTRS)

1971-01-01

Implanting nitrogen ions improves hardening of silicon oxides 30 percent to 60 percent against ionizing radiation effects. Process reduces sensitivity, but retains stability normally shown by interfaces between silicon and thermally grown oxides.

Antireflection/Passivation Step For Silicon Cell

NASA Technical Reports Server (NTRS)

Crotty, Gerald T.; Kachare, Akaram H.; Daud, Taher

1988-01-01

New process excludes usual silicon oxide passivation. Changes in principal electrical parameters during two kinds of processing suggest antireflection treatment almost as effective as oxide treatment in passivating cells. Does so without disadvantages of SiOx passivation.

Process for forming a porous silicon member in a crystalline silicon member

DOEpatents

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

Synthesis of fine-grained .alpha.-silicon nitride by a combustion process

DOEpatents

Holt, J. Birch; Kingman, Donald D.; Bianchini, Gregory M.

1990-01-01

A combustion synthesis process for the preparation of .alpha.-silicon nitride and composites thereof is disclosed. Preparation of the .alpha.-silicon nitride comprises the steps of dry mixing silicon powder with an alkali metal azide, such as sodium azide, cold-pressing the mixture into any desired shape, or loading the mixture into a fused, quartz crucible, loading the crucible into a combustion chamber, pressurizing the chamber with nitrogen and igniting the mixture using an igniter pellet. The method for the preparation of the composites comprises dry mixing silicon powder (Si) or SiO.sub.2, with a metal or metal oxide, adding a small amount of an alkali metal azide such as sodium azide, introducing the mixture into a suitable combustion chamber, pressurizing the combustion chamber with nitrogen, igniting the mixture within the combustion chamber, and isolating the .alpha.-silicon nitride formed as a reaction product.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Method for fabricating silicon cells

DOEpatents

Ruby, Douglas S.; Basore, Paul A.; Schubert, W. Kent

1998-08-11

A process for making high-efficiency solar cells. This is accomplished by forming a diffusion junction and a passivating oxide layer in a single high-temperature process step. The invention includes the class of solar cells made using this process, including high-efficiency solar cells made using Czochralski-grown silicon.

Fluorescence of silicon nanoparticles prepared by nanosecond pulsed laser

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Chunyang, E-mail: chunyangliu@126.com; Sui, Xin; Yang, Fang

2014-03-15

A pulsed laser fabrication method is used to prepare fluorescent microstructures on silicon substrates in this paper. A 355 nm nanosecond pulsed laser micromachining system was designed, and the performance was verified and optimized. Fluorescence microscopy was used to analyze the photoluminescence of the microstructures which were formed using the pulsed laser processing technique. Photoluminescence spectra of the microstructure reveal a peak emission around 500 nm, from 370 nm laser irradiation. The light intensity also shows an exponential decay with irradiation time, which is similar to attenuation processes seen in porous silicon. The surface morphology and chemical composition of themore » microstructure in the fabricated region was also analyzed with multifunction scanning electron microscopy. Spherical particles are produced with diameters around 100 nm. The structure is compared with porous silicon. It is likely that these nanoparticles act as luminescence recombination centers on the silicon surface. The small diameter of the particles modifies the band gap of silicon by quantum confinement effects. Electron-hole pairs recombine and the fluorescence emission shifts into the visible range. The chemical elements of the processed region are also changed during the interaction between laser and silicon. Oxidation and carbonization play an important role in the enhancement of fluorescence emission.« less

Integral glass encapsulation for solar arrays

NASA Technical Reports Server (NTRS)

Young, P. R.

1977-01-01

Electrostatic bonding has been used to join silicon solar cells to borosilicate glass without the aid of any organic binders or adhesives. The results of this investigation have been to demonstrate, without question, the feasibility of this process as an encapsulation technique. The potential of ESB for terrestrial solar arrays was clearly shown. The process is fast, reproducible, and produces a permanent bond between glass and silicon that is stronger than the silicon itself. Since this process is a glass sealing technique requiring no organics it makes moisture tight sealing of solar cells possible.

Fabrication of high aspect ratio tungsten nanostructures on ultrathin c-Si membranes for extreme UV applications

NASA Astrophysics Data System (ADS)

Delachat, F.; Le Drogoff, B.; Constancias, C.; Delprat, S.; Gautier, E.; Chaker, M.; Margot, J.

2016-01-01

In this work, we demonstrate a full process for fabricating high aspect ratio diffraction optics for extreme ultraviolet lithography. The transmissive optics consists in nanometer scale tungsten patterns standing on flat, ultrathin (100 nm) and highly transparent (>85% at 13.5 nm) silicon membranes (diameter of 1 mm). These tungsten patterns were achieved using an innovative pseudo-Bosch etching process based on an inductively coupled plasma ignited in a mixture of SF6 and C4F8. Circular ultra-thin Si membranes were fabricated through a state-of-the-art method using direct-bonding with thermal difference. The silicon membranes were sputter-coated with a few hundred nanometers (100-300 nm) of stress-controlled tungsten and a very thin layer of chromium. Nanoscale features were written in a thin resist layer by electron beam lithography and transferred onto tungsten by plasma etching of both the chromium hard mask and the tungsten layer. This etching process results in highly anisotropic tungsten features at room temperature. The homogeneity and the aspect ratio of the advanced pattern transfer on the membranes were characterized with scanning electron microscopy after focus ion beam milling. An aspect ratio of about 6 for 35 nm size pattern is successfully obtained on a 1 mm diameter 100 nm thick Si membrane. The whole fabrication process is fully compatible with standard industrial semiconductor technology.

Characterization of a Standardized Ex-vivo Porcine Model to Assess Short Term Intraocular Pressure Changes and Trabecular Meshwork Vitality After Pars Plana Vitrectomy with Different Silicone Oil and BSS Tamponades.

PubMed

Ebner, Martina; Mariacher, Siegfried; Hurst, José; Szurman, Peter; Schnichels, Sven; Spitzer, Martin S; Januschowski, Kai

2017-08-01

The aim of this study was to characterize a standardized porcine ex-vivo testing system for intraocular pressure (IOP) monitoring after vitrectomy with different endotamponades. Twenty-four pig eyes, six per endotamponade group were obtained immediately postmortem. After pars plana vitrectomy, vitreous substitutes (silicone oil 1000 mPas, 2000 mPas, 5000 mPas, and Balanced Salt Solution (BSS)) were instillated and IOP was observed over 24-hours. Infusion pumps with Dulbecco's Modified Eagle Medium (DMEM) simulated a constant aqueous humor circulation. A histological examination of the trabecular meshwork with DAPI- and TUNEL-staining was performed to detect the amount of apoptotic cells. TUNEL-assay showed a mean cell death rate of 3.78% (SD ± 1.46%) for silicone oil endotamponades compared to 5.05% (SD ± 2.18%) in BSS group. One-way ANOVA (p = 0.425) showed no significant difference between both groups. Mean IOP in silicone oil endotamponades was 9.50 mmHg (SD ± 1.68 mmHg) at baseline, 13.23 mmHg (SD ± 0.79 mmHg) after 1 hour, 18.46 mmHg (SD ± 2.13 mmHg) after 12 hours and 15.51 mmHg (SD ± 2.82 mmHg) 24 hours after instillation. A comparison of all silicone oil groups (one-way ANOVA, Bonferroni post-hoc test, p = 0.269 to 1.000) didn't reveal significant differences in mean IOP. The standardized ex-vivo porcine model represents an effective alternative to the in-vivo testing in animals. Maintaining the trabecular and uveoscleral outflow pathway enables a pseudo in-vivo analysis.

Narrow band gap amorphous silicon semiconductors

DOEpatents

Madan, A.; Mahan, A.H.

1985-01-10

Disclosed is a narrow band gap amorphous silicon semiconductor comprising an alloy of amorphous silicon and a band gap narrowing element selected from the group consisting of Sn, Ge, and Pb, with an electron donor dopant selected from the group consisting of P, As, Sb, Bi and N. The process for producing the narrow band gap amorphous silicon semiconductor comprises the steps of forming an alloy comprising amorphous silicon and at least one of the aforesaid band gap narrowing elements in amount sufficient to narrow the band gap of the silicon semiconductor alloy below that of amorphous silicon, and also utilizing sufficient amounts of the aforesaid electron donor dopant to maintain the amorphous silicon alloy as an n-type semiconductor.

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Minahan, J. A.

1981-01-01

The fabrication of solar cells from several unconventional silicon materials is described, and cell performance measured and analyzed. Unconventional materials evaluated are edge defined film fed grown (EFG), heat exchanger method (HEM), dendritic web grown, and continuous CZ silicons. Resistivity, current voltage, and spectral sensitivity of the cells were measured. Current voltage was measured under AM0 and AM1 conditions. Maximum conversion efficiencies of cells fabricated from these and other unconventional silicons were compared and test results analyzed. The HEM and continuous CZ silicon were found to be superior to silicon materials considered previously.

Synthesis and devolatilization of M-97 NVB silicone gum compounded into silica reinforced silicone base

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schneider, J.W.

1986-06-01

Silica reinforced silicon bases having 0.31 weight percent vinyl content were prepared by using a blend of low and high vinyl content devolatilized M-97 NVB silicone gum. The M-97 NVB is a custom dimethyl-, diphenyl-, methylvinylsiloxane gum. The silicon gum was devolatilized to evaluate the anticipated improved handling characteristics. Previous procured batches of M-97 NVB had not been devolatilized and difficult handling problems were encountered. The synthesis, devolatilization, and compound processes for the M-97 NVB silicone gum are discussed.

Oblique patterned etching of vertical silicon sidewalls

DOE Office of Scientific and Technical Information (OSTI.GOV)

Burckel, D. Bruce; Finnegan, Patrick S.; Henry, M. David

A method for patterning on vertical silicon surfaces in high aspect ratio silicontopography is presented. A Faraday cage is used to direct energetic reactive ions obliquely through a patterned suspended membrane positioned over the topography. The technique is capable of forming high-fidelity pattern (100 nm) features, adding an additional fabrication capability to standard top-down fabrication approaches.

Oblique patterned etching of vertical silicon sidewalls

DOE PAGES

Burckel, D. Bruce; Finnegan, Patrick S.; Henry, M. David; ...

2016-04-05

A method for patterning on vertical silicon surfaces in high aspect ratio silicontopography is presented. A Faraday cage is used to direct energetic reactive ions obliquely through a patterned suspended membrane positioned over the topography. The technique is capable of forming high-fidelity pattern (100 nm) features, adding an additional fabrication capability to standard top-down fabrication approaches.

Thermal system design and modeling of meniscus controlled silicon growth process for solar applications

NASA Astrophysics Data System (ADS)

Wang, Chenlei

The direct conversion of solar radiation to electricity by photovoltaics has a number of significant advantages as an electricity generator. That is, solar photovoltaic conversion systems tap an inexhaustible resource which is free of charge and available anywhere in the world. Roofing tile photovoltaic generation, for example, saves excess thermal heat and preserves the local heat balance. This means that a considerable reduction of thermal pollution in densely populated city areas can be attained. A semiconductor can only convert photons with the energy of the band gap with good efficiency. It is known that silicon is not at the maximum efficiency but relatively close to it. There are several main parts for the photovoltaic materials, which include, single- and poly-crystalline silicon, ribbon silicon, crystalline thin-film silicon, amorphous silicon, copper indium diselenide and related compounds, cadmium telluride, et al. In this dissertation, we focus on melt growth of the single- and poly-crystalline silicon manufactured by Czochralski (Cz) crystal growth process, and ribbon silicon produced by the edge-defined film-fed growth (EFG) process. These two methods are the most commonly used techniques for growing photovoltaic semiconductors. For each crystal growth process, we introduce the growth mechanism, growth system design, general application, and progress in the numerical simulation. Simulation results are shown for both Czochralski and EFG systems including temperature distribution of the growth system, velocity field inside the silicon melt and electromagnetic field for the EFG growth system. Magnetic field is applied on Cz system to reduce the melt convection inside crucible and this has been simulated in our numerical model. Parametric studies are performed through numerical and analytical models to investigate the relationship between heater power levels and solidification interface movement and shape. An inverse problem control scheme is developed to control the solidification interface of Cz system by adjusting heater powers. For the EFG system, parametric studies are performed to discuss the effect of several growth parameters including window opening size, argon gas flow rate and growth thermal environment on the temperature distribution, silicon tube thickness and pulling rate. Two local models are developed and integrated with the global model to investigate the detailed transport phenomena in a small region around the solidification interface including silicon crystal, silicon melt, free surface, liquid-solid interface and graphite die design. Different convection forms are taken into consideration.

Method for fabricating silicon cells

DOEpatents

Ruby, D.S.; Basore, P.A.; Schubert, W.K.

1998-08-11

A process is described for making high-efficiency solar cells. This is accomplished by forming a diffusion junction and a passivating oxide layer in a single high-temperature process step. The invention includes the class of solar cells made using this process, including high-efficiency solar cells made using Czochralski-grown silicon. 9 figs.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

High quality silicon-based substrates for microwave and millimeter wave passive circuits

NASA Astrophysics Data System (ADS)

Belaroussi, Y.; Rack, M.; Saadi, A. A.; Scheen, G.; Belaroussi, M. T.; Trabelsi, M.; Raskin, J.-P.

2017-09-01

Porous silicon substrate is very promising for next generation wireless communication requiring the avoidance of high-frequency losses originating from the bulk silicon. In this work, new variants of porous silicon (PSi) substrates have been introduced. Through an experimental RF performance, the proposed PSi substrates have been compared with different silicon-based substrates, namely, standard silicon (Std), trap-rich (TR) and high resistivity (HR). All of the mentioned substrates have been fabricated where identical samples of CPW lines have been integrated on. The new PSi substrates have shown successful reduction in the substrate's effective relative permittivity to values as low as 3.7 and great increase in the substrate's effective resistivity to values higher than 7 kΩ cm. As a concept proof, a mm-wave bandpass filter (MBPF) centred at 27 GHz has been integrated on the investigated substrates. Compared with the conventional MBPF implemented on standard silicon-based substrates, the measured S-parameters of the PSi-based MBPF have shown high filtering performance, such as a reduction in insertion loss and an enhancement of the filter selectivity, with the joy of having the same filter performance by varying the temperature. Therefore, the efficiency of the proposed PSi substrates has been well highlighted. From 1994 to 1995, she was assistant of physics at (USTHB), Algiers . From 1998 to 2011, she was a Researcher at characterization laboratory in ionized media and laser division at the Advanced Technologies Development Center. She has integrated the Analog Radio Frequency Integrated Circuits team as Researcher since 2011 until now in Microelectronic and Nanotechnology Division at Advanced Technologies Development Center (CDTA), Algiers. She has been working towards her Ph.D. degree jointly at CDTA and Ecole Nationale Polytechnique, Algiers, since 2012. Her research interest includes fabrication and characterization of microwave passive devices on porous silicon as new substrate, such as characterization of FinFET components.

NREL Paves the Way to Commercialization of Silicon Ink (Fact Sheet)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

In 2008, Innovalight, a start-up company in Sunnyvale, California, invented a liquid form of silicon, called Silicon Ink. It contains silicon nanoparticles that are suspended evenly within the solution. Those nanoparticles contain dopant atoms that can be driven into silicon solar cells, which changes the conductivity of the silicon and creates the internal electric fields that are needed to turn photons into electrons -- and thus into electricity. The ink is applied with a standard screen printer, already commonly used in the solar industry. The distinguishing feature of Silicon Ink is that it can be distributed in exact concentrations inmore » precisely the correct locations on the surface of the solar cell. This allows most of the surface to be lightly doped, enhancing its response to blue light, while heavily doping the area around the electrical contacts, raising the conductivity in that area to allow the contact to work more efficiently. The accuracy and uniformity of the ink distribution allows the production of solar cells that achieve higher power production at a minimal additional cost.« less

Improved reaction sintered silicon nitride. [protective coatings to improve oxidation resistance

NASA Technical Reports Server (NTRS)

Baumgartner, H. R.

1978-01-01

Processing treatments were applied to as-nitrided reaction sintered silicon nitride (RSSN) with the purposes of improving strength after processing to above 350 MN/m2 and improving strength after oxidation exposure. The experimental approaches are divided into three broad classifications: sintering of surface-applied powders; impregnation of solution followed by further thermal processing; and infiltration of molten silicon and subsequent carburization or nitridation of the silicon. The impregnation of RSSN with solutions of aluminum nitrate and zirconyl chloride, followed by heating at 1400-1500 C in a nitrogen atmosphere containing silicon monoxide, improved RSSN strength and oxidation resistance. The room temperature bend strength of RSSN was increased nearly fifty percent above the untreated strength with mean absolute strengths up to 420 MN/m2. Strengths of treated samples that were measured after a 12 hour oxidation exposure in air were up to 90 percent of the original as-nitrided strength, as compared to retained strengths in the range of 35 to 60 percent for untreated RSSN after the same oxidation exposure.

Reduce on the Cost of Photovoltaic Power Generation for Polycrystalline Silicon Solar Cells by Double Printing of Ag/Cu Front Contact Layer

NASA Astrophysics Data System (ADS)

Peng, Zhuoyin; Liu, Zhou; Chen, Jianlin; Liao, Lida; Chen, Jian; Li, Cong; Li, Wei

2018-06-01

With the development of photovoltaic industry, the cost of photovoltaic power generation has become the significant issue. And the metallization process has decided the cost of original materials and photovoltaic efficiency of the solar cells. Nowadays, double printing process has been introduced instead of one-step printing process for front contact of polycrystalline silicon solar cells, which can effectively improve the photovoltaic conversion efficiency of silicon solar cells. Here, the relative cheap Cu paste has replaced the expensive Ag paste to form Ag/Cu composite front contact of silicon solar cells. The photovoltaic performance and the cost of photovoltaic power generation have been investigated. With the optimization on structure and height of Cu finger layer for Ag/Cu composite double-printed front contact, the silicon solar cells have exhibited a photovoltaic conversion efficiency of 18.41%, which has reduced 3.42 cent per Watt for the cost of photovoltaic power generation.

Fine Collimator Grids Using Silicon Metering Structure

NASA Technical Reports Server (NTRS)

Eberhard, Carol

1998-01-01

The project Fine Collimator Grids Using Silicon Metering Structure was managed by Dr. Carol Eberhard of the Electromagnetic Systems & Technology Department (Space & Technology Division) of TRW who also wrote this final report. The KOH chemical etching of the silicon wafers was primarily done by Dr. Simon Prussin of the Electrical Engineering Department of UCLA at the laboratory on campus. Moshe Sergant of the Superconductor Electronics Technology Department (Electronics Systems & Technology Division) of TRW and Dr. Prussin were instrumental in developing the low temperature silicon etching processes. Moshe Sergant and George G. Pinneo of the Microelectronics Production Department (Electronics Systems & Technology Division) of TRW were instrumental in developing the processes for filling the slots etched in the silicon wafers with metal-filled materials. Their work was carried out in the laboratories at the Space Park facility. Moshe Sergant is also responsible for the impressive array of Scanning Electron Microscope images with which the various processes were monitored. Many others also contributed their time and expertise to the project. I wish to thank them all.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Processing method for forming dislocation-free SOI and other materials for semiconductor use

DOEpatents

Holland, Orin Wayne; Thomas, Darrell Keith; Zhou, Dashun

1997-01-01

A method for preparing a silicon-on-insulator material having a relatively defect-free Si overlayer involves the implanting of oxygen ions within a silicon body and the interruption of the oxygen-implanting step to implant Si ions within the silicon body. The implanting of the oxygen ions develops an oxide layer beneath the surface of the silicon body, and the Si ions introduced by the Si ion-implanting step relieves strain which is developed in the Si overlayer during the implanting step without the need for any intervening annealing step. By relieving the strain in this manner, the likelihood of the formation of strain-induced defects in the Si overlayer is reduced. In addition, the method can be carried out at lower processing temperatures than have heretofore been used with SIMOX processes of the prior art. The principles of the invention can also be used to relieve negative strain which has been induced in a silicon body of relatively ordered lattice structure.

High Surface Area of Porous Silicon Drives Desorption of Intact Molecules

PubMed Central

Northen, Trent R.; Woo, Hin-Koon; Northen, Michael T.; Nordström, Anders; Uritboonthail, Winnie; Turner, Kimberly L.; Siuzdak, Gary

2007-01-01

The surface structure of porous silicon used in desorption/ionization on porous silicon (DIOS) mass analysis is known to play a primary role in the desorption/ionization (D/I) process. In this study, mass spectrometry and scanning electron microscopy (SEM) are used to examine the correlation between intact ion generation with surface ablation, and surface morphology. The DIOS process is found to be highly laser energy dependent and correlates directly with the appearance of surface ions (Sin+ and OSiH+). A threshold laser energy for DIOS is observed (10 mJ/cm2), which supports that DIOS is driven by surface restructuring and is not a strictly thermal process. In addition, three DIOS regimes are observed which correspond to surface restructuring and melting. These results suggest that higher surface area silicon substrates may enhance DIOS performance. A recent example which fits into this mechanism is silicon nanowires surface which have a high surface energy and concomitantly requires lower laser energy for analyte desorpton. PMID:17881245

LSA silicon material task closed-cycle process development

NASA Technical Reports Server (NTRS)

Roques, R. A.; Wakefield, G. F.; Blocher, J. M., Jr.; Browning, M. F.; Wilson, W.

1979-01-01

The initial effort on feasibility of the closed cycle process was begun with the design of the two major items of untested equipment, the silicon tetrachloride by product converter and the rotary drum reactor for deposition of silicon from trichlorosilane. The design criteria of the initial laboratory equipment included consideration of the reaction chemistry, thermodynamics, and other technical factors. Design and construction of the laboratory equipment was completed. Preliminary silicon tetrachloride conversion experiments confirmed the expected high yield of trichlorosilane, up to 98 percent of theoretical conversion. A preliminary solar-grade polysilicon cost estimate, including capital costs considered extremely conservative, of $6.91/kg supports the potential of this approach to achieve the cost goal. The closed cycle process appears to have a very likely potential to achieve LSA goals.

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

2018-05-01

Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

Evaluation of the ion implantation process for production of solar cells from silicon sheet materials

NASA Technical Reports Server (NTRS)

Spitzer, M. B.

1983-01-01

The objective of this program is the investigation and evaluation of the capabilities of the ion implantation process for the production of photovoltaic cells from a variety of present-day, state-of-the-art, low-cost silicon sheet materials. Task 1 of the program concerns application of ion implantation and furnace annealing to fabrication of cells made from dendritic web silicon. Task 2 comprises the application of ion implantation and pulsed electron beam annealing (PEBA) to cells made from SEMIX, SILSO, heat-exchanger-method (HEM), edge-defined film-fed growth (EFG) and Czochralski (CZ) silicon. The goals of Task 1 comprise an investigation of implantation and anneal processes applied to dendritic web. A further goal is the evaluation of surface passivation and back surface reflector formation. In this way, processes yielding the very highest efficiency can be evaluated. Task 2 seeks to evaluate the use of PEBA for various sheet materials. A comparison of PEBA to thermal annealing will be made for a variety of ion implantation processes.

THz-wave generation via difference frequency mixing in strained silicon based waveguide utilizing its second order susceptibility χ((2)).

PubMed

Saito, Kyosuke; Tanabe, Tadao; Oyama, Yutaka

2014-07-14

Terahertz (THz) wave generation via difference frequency mixing (DFM) process in strain silicon membrane waveguides by introducing the straining layer is theoretically investigated. The Si(3)N(4) straining layer induces anisotropic compressive strain in the silicon core and results in the appearance of the bulk second order nonlinear susceptibility χ((2)) by breaking the crystal symmetry. We have proposed waveguide structures for THz wave generation under the DFM process by .using the modal birefringence in the waveguide core. Our simulations show that an output power of up to 0.95 mW can be achieved at 9.09 THz. The strained silicon optical device may open a widow in the field of the silicon-based active THz photonic device applications.

Passivation of InGaAs(001)-(2 × 4) by Self-Limiting Chemical Vapor Deposition of a Silicon Hydride Control Layer.

PubMed

Edmonds, Mary; Kent, Tyler; Chagarov, Evgueni; Sardashti, Kasra; Droopad, Ravi; Chang, Mei; Kachian, Jessica; Park, Jun Hong; Kummel, Andrew

2015-07-08

A saturated Si-Hx seed layer for gate oxide or contact conductor ALD has been deposited via two separate self-limiting and saturating CVD processes on InGaAs(001)-(2 × 4) at substrate temperatures of 250 and 350 °C. For the first self-limiting process, a single silicon precursor, Si3H8, was dosed at a substrate temperature of 250 °C, and XPS results show the deposited silicon hydride layer saturated at about 4 monolayers of silicon coverage with hydrogen termination. STS results show the surface Fermi level remains unpinned following the deposition of the saturated silicon hydride layer, indicating the InGaAs surface dangling bonds are electrically passivated by Si-Hx. For the second self-limiting process, Si2Cl6 was dosed at a substrate temperature of 350 °C, and XPS results show the deposited silicon chloride layer saturated at about 2.5 monolayers of silicon coverage with chlorine termination. Atomic hydrogen produced by a thermal gas cracker was subsequently dosed at 350 °C to remove the Si-Cl termination by replacing with Si-H termination as confirmed by XPS, and STS results confirm the saturated Si-Hx bilayer leaves the InGaAs(001)-(2 × 4) surface Fermi level unpinned. Density function theory modeling of silicon hydride surface passivation shows an Si-Hx monolayer can remove all the dangling bonds and leave a charge balanced surface on InGaAs.

Phase-field model for the two-phase lithiation of silicon

NASA Astrophysics Data System (ADS)

Gao, Fangliang; Hong, Wei

2016-09-01

As an ideal anode material, silicon has the highest lithium-ion capacity in theory, but the broader application is limited by the huge volumetric strain caused by lithium insertion and extraction. To better understand the physical process and to resolve the related reliability issue, enormous efforts have been made. Recent experiments observed sharp reaction fronts in both crystalline and amorphous silicon during the first lithiation half-cycle. Such a concentration profile indicates that the process is likely to be reaction limited. Based on this postulation, a phase-field model is developed and implemented into a finite-element code to simulate the coupled large inelastic deformation and motion of the reaction front in a silicon electrode. In contrast to most existing models, the model treats both volumetric and deviatoric inelastic deformation in silicon as a direct consequence of the lithiation at the reaction front. The amount of deviatoric deformation is determined by using the recently developed kinetic model of stress-induced anisotropic reaction. By considering the role of stress in the lithiation process, this model successfully recovers the self-limiting phenomenon of silicon electrodes, and relates it to the local geometry of electrodes. The model is also used to evaluate the energy-release rate of the surface crack on a spherical electrode, and the result suggests a critical size of silicon nanoparticles to avert fracture. As examples, the morphology evolution of a silicon disk and a Si nanowire during lithiation are also investigated.

The parameter influence of ion irradiation on the distribution profile of the defect in silicon films

NASA Astrophysics Data System (ADS)

Shemukhin, A. A.; Balaskshin, Yu. V.; Evseev, A. P.; Chernysh, V. S.

2017-09-01

As silicon is an important element in semiconductor devices, the process of defect formation under ion irradiation in it is studied well enough. Modern electronic components are made on silicon lattices (films) that are 100-300 nm thick (Chernysh et al., 1980; Shemukhin et al., 2012; Ieshkin et al., 2015). However, there are still features to be observed in the process of defect formation in silicon. In our work we investigate the effect of fluence and target temperature on the defect formation in films and bulk silicon samples. To investigate defect formation in the silicon films and bulk silicon samples we present experimental data on Si+ implantation with an energy of 200 keV, fluences range from 5 * 1014 to 5 * 1015 ion/cm2 for a fixed flux 1 μA/cm2 and the substrate temperatures from 150 to 350 K The sample crystallinity was investigated by using the Rutherford backscattering technique (RBS) in channeling and random modes. It is shown that in contrast to bulk silicon for which amorphization is observed at 5 × 1016 ion/cm2, the silicon films on sapphire amorphize at lower critical fluences (1015 ion/cm2). So the amorphization critical fluences depend on the target temperature. In addition it is shown that under similar implantation parameters, the disordering of silicon films under the action of the ion beam is stronger than the bulk silicon.

A strong electro-optically active lead-free ferroelectric integrated on silicon

NASA Astrophysics Data System (ADS)

Abel, Stefan; Stöferle, Thilo; Marchiori, Chiara; Rossel, Christophe; Rossell, Marta D.; Erni, Rolf; Caimi, Daniele; Sousa, Marilyne; Chelnokov, Alexei; Offrein, Bert J.; Fompeyrine, Jean

2013-04-01

The development of silicon photonics could greatly benefit from the linear electro-optical properties, absent in bulk silicon, of ferroelectric oxides, as a novel way to seamlessly connect the electrical and optical domain. Of all oxides, barium titanate exhibits one of the largest linear electro-optical coefficients, which has however not yet been explored for thin films on silicon. Here we report on the electro-optical properties of thin barium titanate films epitaxially grown on silicon substrates. We extract a large effective Pockels coefficient of reff=148 pm V-1, which is five times larger than in the current standard material for electro-optical devices, lithium niobate. We also reveal the tensor nature of the electro-optical properties, as necessary for properly designing future devices, and furthermore unambiguously demonstrate the presence of ferroelectricity. The integration of electro-optical active films on silicon could pave the way towards power-efficient, ultra-compact integrated devices, such as modulators, tuning elements and bistable switches.

Effect of tulle on the mechanical properties of a maxillofacial silicone elastomer.

PubMed

Gunay, Yumushan; Kurtoglu, Cem; Atay, Arzu; Karayazgan, Banu; Gurbuz, Cihan Cem

2008-11-01

The purpose of this research was to investigate if physical properties could be improved by incorporating a tulle reinforcement material into a maxillofacial silicone elastomer. A-2186 silicone elastomer was used in this study. The study group consisted of 20 elastomer specimens incorporated with tulle and fabricated in dumbbell-shaped silicone patterns using ASTM D412 and D624 standards. The control group consisted of 20 elastomer specimens fabricated without tulle. Tensile strength, ultimate elongation, and tear strength of all specimens were measured and analyzed. Statistical analyses were performed using Mann-Whitney U test with a statistical significance at 95% confidence level. It was found that the tensile and tear strengths of tulle-incorporated maxillofacial silicone elastomer were higher than those without tulle incorporation (p < 0.05). Therefore, findings of this study suggested that tulle successfully reinforced a maxillofacial silicone elastomer by providing it with better mechanical properties and augmented strength--especially for the delicate edges of maxillofacial prostheses.

Process for manufacture of semipermeable silicon nitride membranes

DOEpatents

Galambos, Paul Charles; Shul, Randy J.; Willison, Christi Gober

2003-12-09

A new class of semipermeable membranes, and techniques for their fabrication, have been developed. These membranes, formed by appropriate etching of a deposited silicon nitride layer, are robust, easily manufacturable, and compatible with a wide range of silicon micromachining techniques.